2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2011 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #define CARDNAME "sh-eth"
27 #define TX_TIMEOUT (5*HZ)
28 #define TX_RING_SIZE 64 /* Tx ring size */
29 #define RX_RING_SIZE 64 /* Rx ring size */
31 #define PKT_BUF_SZ 1538
34 /* E-DMAC registers */
100 /* TSU Absolute address */
147 /* This value must be written at last. */
148 SH_ETH_MAX_REGISTER_OFFSET,
151 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWEN0] = 0x0010,
205 [TSU_FWEN1] = 0x0014,
207 [TSU_BSYSL0] = 0x0020,
208 [TSU_BSYSL1] = 0x0024,
209 [TSU_PRISL0] = 0x0028,
210 [TSU_PRISL1] = 0x002c,
211 [TSU_FWSL0] = 0x0030,
212 [TSU_FWSL1] = 0x0034,
213 [TSU_FWSLC] = 0x0038,
214 [TSU_QTAG0] = 0x0040,
215 [TSU_QTAG1] = 0x0044,
217 [TSU_FWINMK] = 0x0054,
218 [TSU_ADQT0] = 0x0048,
219 [TSU_ADQT1] = 0x004c,
220 [TSU_VTAG0] = 0x0058,
221 [TSU_VTAG1] = 0x005c,
222 [TSU_ADSBSY] = 0x0060,
224 [TSU_POST1] = 0x0070,
225 [TSU_POST2] = 0x0074,
226 [TSU_POST3] = 0x0078,
227 [TSU_POST4] = 0x007c,
228 [TSU_ADRH0] = 0x0100,
229 [TSU_ADRL0] = 0x0104,
230 [TSU_ADRH31] = 0x01f8,
231 [TSU_ADRL31] = 0x01fc,
247 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
299 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
325 [TSU_CTRST] = 0x0004,
326 [TSU_FWEN0] = 0x0010,
327 [TSU_FWEN1] = 0x0014,
329 [TSU_BSYSL0] = 0x0020,
330 [TSU_BSYSL1] = 0x0024,
331 [TSU_PRISL0] = 0x0028,
332 [TSU_PRISL1] = 0x002c,
333 [TSU_FWSL0] = 0x0030,
334 [TSU_FWSL1] = 0x0034,
335 [TSU_FWSLC] = 0x0038,
336 [TSU_QTAGM0] = 0x0040,
337 [TSU_QTAGM1] = 0x0044,
338 [TSU_ADQT0] = 0x0048,
339 [TSU_ADQT1] = 0x004c,
341 [TSU_FWINMK] = 0x0054,
342 [TSU_ADSBSY] = 0x0060,
344 [TSU_POST1] = 0x0070,
345 [TSU_POST2] = 0x0074,
346 [TSU_POST3] = 0x0078,
347 [TSU_POST4] = 0x007c,
362 [TSU_ADRH0] = 0x0100,
363 [TSU_ADRL0] = 0x0104,
364 [TSU_ADRL31] = 0x01fc,
368 /* Driver's parameters */
369 #if defined(CONFIG_CPU_SH4)
370 #define SH4_SKB_RX_ALIGN 32
372 #define SH2_SH3_SKB_RX_ALIGN 2
378 #ifdef CONFIG_CPU_SUBTYPE_SH7763
381 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
383 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
387 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
393 EDMR_EL = 0x40, /* Litte endian */
394 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
395 EDMR_SRST_GETHER = 0x03,
396 EDMR_SRST_ETHER = 0x01,
401 EDTRR_TRNS_GETHER = 0x03,
402 EDTRR_TRNS_ETHER = 0x01,
412 TPAUSER_TPAUSE = 0x0000ffff,
413 TPAUSER_UNLIMITED = 0,
418 BCFR_RPAUSE = 0x0000ffff,
424 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
428 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
432 EESR_TWB1 = 0x80000000,
433 EESR_TWB = 0x40000000, /* same as TWB0 */
434 EESR_TC1 = 0x20000000,
435 EESR_TUC = 0x10000000,
436 EESR_ROC = 0x08000000,
437 EESR_TABT = 0x04000000,
438 EESR_RABT = 0x02000000,
439 EESR_RFRMER = 0x01000000, /* same as RFCOF */
440 EESR_ADE = 0x00800000,
441 EESR_ECI = 0x00400000,
442 EESR_FTC = 0x00200000, /* same as TC or TC0 */
443 EESR_TDE = 0x00100000,
444 EESR_TFE = 0x00080000, /* same as TFUF */
445 EESR_FRC = 0x00040000, /* same as FR */
446 EESR_RDE = 0x00020000,
447 EESR_RFE = 0x00010000,
448 EESR_CND = 0x00000800,
449 EESR_DLC = 0x00000400,
450 EESR_CD = 0x00000200,
451 EESR_RTO = 0x00000100,
452 EESR_RMAF = 0x00000080,
453 EESR_CEEF = 0x00000040,
454 EESR_CELF = 0x00000020,
455 EESR_RRF = 0x00000010,
456 EESR_RTLF = 0x00000008,
457 EESR_RTSF = 0x00000004,
458 EESR_PRE = 0x00000002,
459 EESR_CERF = 0x00000001,
462 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
464 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
465 EESR_RDE | EESR_RFRMER | EESR_ADE | \
466 EESR_TFE | EESR_TDE | EESR_ECI)
467 #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
472 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
473 DMAC_M_RABT = 0x02000000,
474 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
475 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
476 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
477 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
478 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
479 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
480 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
481 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
482 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
483 DMAC_M_RINT1 = 0x00000001,
486 /* Receive descriptor bit */
488 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
489 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
490 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
491 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
492 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
493 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
494 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
495 RD_RFS1 = 0x00000001,
497 #define RDF1ST RD_RFP1
498 #define RDFEND RD_RFP0
499 #define RD_RFP (RD_RFP1|RD_RFP0)
503 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
504 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
505 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
507 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
508 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
510 /* Transfer descriptor bit */
512 TD_TACT = 0x80000000,
513 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
514 TD_TFP0 = 0x10000000,
516 #define TDF1ST TD_TFP1
517 #define TDFEND TD_TFP0
518 #define TD_TFP (TD_TFP1|TD_TFP0)
521 #define DEFAULT_RMCR_VALUE 0x00000000
524 enum FELIC_MODE_BIT {
525 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
526 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
527 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
528 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
529 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
530 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
531 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
535 enum ECSR_STATUS_BIT {
536 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
538 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
541 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
542 ECSR_ICD | ECSIPR_MPDIP)
545 enum ECSIPR_STATUS_MASK_BIT {
546 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
547 ECSIPR_LCHNGIP = 0x04,
548 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
551 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
552 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
566 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
567 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
568 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
569 DESC_I_RINT1 = 0x0001,
574 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
575 RPADIR_PADR = 0x0003f,
579 #define DEFAULT_FDR_INIT 0x00000707
582 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
583 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
589 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
590 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
591 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
593 #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
597 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
598 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
599 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
600 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
605 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
606 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
607 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
612 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
613 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
614 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
620 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
621 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
626 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
627 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
628 PHY_16_TXselect = 0x0400,
629 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
630 PHY_16_Force100LNK = 0x0080,
631 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
632 PHY_16_RPDCTR_EN = 0x0010,
633 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
634 PHY_16_Sleepmode = 0x0002,
635 PHY_16_RemoteLoopOut = 0x0001,
640 #define POST0_RX (POST_RX)
641 #define POST0_FW (POST_FW)
642 #define POST1_RX (POST_RX >> 2)
643 #define POST1_FW (POST_FW >> 2)
644 #define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
647 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
651 TSU_FWEN0_0 = 0x00000001,
655 enum TSU_ADSBSY_BIT {
656 TSU_ADSBSY_0 = 0x00000001,
661 TSU_TEN_0 = 0x80000000,
666 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
667 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
668 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
673 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
674 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
675 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
676 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
677 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
681 * The sh ether Tx buffer descriptors.
682 * This structure should be 20 bytes.
684 struct sh_eth_txdesc {
685 u32 status; /* TD0 */
686 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
688 u16 buffer_length; /* TD1 */
690 u16 buffer_length; /* TD1 */
694 u32 pad1; /* padding data */
695 } __attribute__((aligned(2), packed));
698 * The sh ether Rx buffer descriptors.
699 * This structure should be 20 bytes.
701 struct sh_eth_rxdesc {
702 u32 status; /* RD0 */
703 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
704 u16 frame_length; /* RD1 */
705 u16 buffer_length; /* RD1 */
707 u16 buffer_length; /* RD1 */
708 u16 frame_length; /* RD1 */
711 u32 pad0; /* padding data */
712 } __attribute__((aligned(2), packed));
714 /* This structure is used by each CPU dependency handling. */
715 struct sh_eth_cpu_data {
716 /* optional functions */
717 void (*chip_reset)(struct net_device *ndev);
718 void (*set_duplex)(struct net_device *ndev);
719 void (*set_rate)(struct net_device *ndev);
721 /* mandatory initialize value */
722 unsigned long eesipr_value;
724 /* optional initialize value */
725 unsigned long ecsr_value;
726 unsigned long ecsipr_value;
727 unsigned long fdr_value;
728 unsigned long fcftr_value;
729 unsigned long rpadir_value;
730 unsigned long rmcr_value;
732 /* interrupt checking mask */
733 unsigned long tx_check;
734 unsigned long eesr_err_check;
735 unsigned long tx_error_check;
737 /* hardware features */
738 unsigned no_psr:1; /* EtherC DO NOT have PSR */
739 unsigned apr:1; /* EtherC have APR */
740 unsigned mpr:1; /* EtherC have MPR */
741 unsigned tpauser:1; /* EtherC have TPAUSER */
742 unsigned bculr:1; /* EtherC have BCULR */
743 unsigned tsu:1; /* EtherC have TSU */
744 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
745 unsigned rpadir:1; /* E-DMAC have RPADIR */
746 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
747 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
750 struct sh_eth_private {
751 struct platform_device *pdev;
752 struct sh_eth_cpu_data *cd;
753 const u16 *reg_offset;
755 void __iomem *tsu_addr;
756 dma_addr_t rx_desc_dma;
757 dma_addr_t tx_desc_dma;
758 struct sh_eth_rxdesc *rx_ring;
759 struct sh_eth_txdesc *tx_ring;
760 struct sk_buff **rx_skbuff;
761 struct sk_buff **tx_skbuff;
762 struct timer_list timer;
764 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
765 u32 cur_tx, dirty_tx;
766 u32 rx_buf_sz; /* Based on MTU+slack. */
768 /* MII transceiver section. */
769 u32 phy_id; /* PHY ID */
770 struct mii_bus *mii_bus; /* MDIO bus control */
771 struct phy_device *phydev; /* PHY device control */
773 phy_interface_t phy_interface;
777 u32 rx_int_var, tx_int_var; /* interrupt control variables */
778 char post_rx; /* POST receive */
779 char post_fw; /* POST forward */
780 struct net_device_stats tsu_stats; /* TSU forward status */
782 unsigned no_ether_link:1;
783 unsigned ether_link_active_low:1;
786 static inline void sh_eth_soft_swap(char *src, int len)
788 #ifdef __LITTLE_ENDIAN__
791 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
793 for (; p < maxp; p++)
798 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
801 struct sh_eth_private *mdp = netdev_priv(ndev);
803 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
806 static inline unsigned long sh_eth_read(struct net_device *ndev,
809 struct sh_eth_private *mdp = netdev_priv(ndev);
811 return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
814 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
815 unsigned long data, int enum_index)
817 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
820 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
823 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
826 #endif /* #ifndef __SH_ETH_H__ */