drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   5  *  Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *
  16  *  The full GNU General Public License is included in this distribution in
  17  *  the file called "COPYING".
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mdio-bitbang.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/phy.h>
  31 #include <linux/cache.h>
  32 #include <linux/io.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/slab.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/clk.h>
  38 #include <linux/sh_eth.h>
  39
  40 #include "sh_eth.h"
  41
  42 #define SH_ETH_DEF_MSG_ENABLE \
  43                 (NETIF_MSG_LINK | \
  44                 NETIF_MSG_TIMER | \
  45                 NETIF_MSG_RX_ERR| \
  46                 NETIF_MSG_TX_ERR)
  47
  48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  49         [EDSR]          = 0x0000,
  50         [EDMR]          = 0x0400,
  51         [EDTRR]         = 0x0408,
  52         [EDRRR]         = 0x0410,
  53         [EESR]          = 0x0428,
  54         [EESIPR]        = 0x0430,
  55         [TDLAR]         = 0x0010,
  56         [TDFAR]         = 0x0014,
  57         [TDFXR]         = 0x0018,
  58         [TDFFR]         = 0x001c,
  59         [RDLAR]         = 0x0030,
  60         [RDFAR]         = 0x0034,
  61         [RDFXR]         = 0x0038,
  62         [RDFFR]         = 0x003c,
  63         [TRSCER]        = 0x0438,
  64         [RMFCR]         = 0x0440,
  65         [TFTR]          = 0x0448,
  66         [FDR]           = 0x0450,
  67         [RMCR]          = 0x0458,
  68         [RPADIR]        = 0x0460,
  69         [FCFTR]         = 0x0468,
  70         [CSMR]          = 0x04E4,
  71
  72         [ECMR]          = 0x0500,
  73         [ECSR]          = 0x0510,
  74         [ECSIPR]        = 0x0518,
  75         [PIR]           = 0x0520,
  76         [PSR]           = 0x0528,
  77         [PIPR]          = 0x052c,
  78         [RFLR]          = 0x0508,
  79         [APR]           = 0x0554,
  80         [MPR]           = 0x0558,
  81         [PFTCR]         = 0x055c,
  82         [PFRCR]         = 0x0560,
  83         [TPAUSER]       = 0x0564,
  84         [GECMR]         = 0x05b0,
  85         [BCULR]         = 0x05b4,
  86         [MAHR]          = 0x05c0,
  87         [MALR]          = 0x05c8,
  88         [TROCR]         = 0x0700,
  89         [CDCR]          = 0x0708,
  90         [LCCR]          = 0x0710,
  91         [CEFCR]         = 0x0740,
  92         [FRECR]         = 0x0748,
  93         [TSFRCR]        = 0x0750,
  94         [TLFRCR]        = 0x0758,
  95         [RFCR]          = 0x0760,
  96         [CERCR]         = 0x0768,
  97         [CEECR]         = 0x0770,
  98         [MAFCR]         = 0x0778,
  99         [RMII_MII]      = 0x0790,
 100
 101         [ARSTR]         = 0x0000,
 102         [TSU_CTRST]     = 0x0004,
 103         [TSU_FWEN0]     = 0x0010,
 104         [TSU_FWEN1]     = 0x0014,
 105         [TSU_FCM]       = 0x0018,
 106         [TSU_BSYSL0]    = 0x0020,
 107         [TSU_BSYSL1]    = 0x0024,
 108         [TSU_PRISL0]    = 0x0028,
 109         [TSU_PRISL1]    = 0x002c,
 110         [TSU_FWSL0]     = 0x0030,
 111         [TSU_FWSL1]     = 0x0034,
 112         [TSU_FWSLC]     = 0x0038,
 113         [TSU_QTAG0]     = 0x0040,
 114         [TSU_QTAG1]     = 0x0044,
 115         [TSU_FWSR]      = 0x0050,
 116         [TSU_FWINMK]    = 0x0054,
 117         [TSU_ADQT0]     = 0x0048,
 118         [TSU_ADQT1]     = 0x004c,
 119         [TSU_VTAG0]     = 0x0058,
 120         [TSU_VTAG1]     = 0x005c,
 121         [TSU_ADSBSY]    = 0x0060,
 122         [TSU_TEN]       = 0x0064,
 123         [TSU_POST1]     = 0x0070,
 124         [TSU_POST2]     = 0x0074,
 125         [TSU_POST3]     = 0x0078,
 126         [TSU_POST4]     = 0x007c,
 127         [TSU_ADRH0]     = 0x0100,
 128         [TSU_ADRL0]     = 0x0104,
 129         [TSU_ADRH31]    = 0x01f8,
 130         [TSU_ADRL31]    = 0x01fc,
 131
 132         [TXNLCR0]       = 0x0080,
 133         [TXALCR0]       = 0x0084,
 134         [RXNLCR0]       = 0x0088,
 135         [RXALCR0]       = 0x008c,
 136         [FWNLCR0]       = 0x0090,
 137         [FWALCR0]       = 0x0094,
 138         [TXNLCR1]       = 0x00a0,
 139         [TXALCR1]       = 0x00a0,
 140         [RXNLCR1]       = 0x00a8,
 141         [RXALCR1]       = 0x00ac,
 142         [FWNLCR1]       = 0x00b0,
 143         [FWALCR1]       = 0x00b4,
 144 };
 145
 146 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 147         [EDSR]          = 0x0000,
 148         [EDMR]          = 0x0400,
 149         [EDTRR]         = 0x0408,
 150         [EDRRR]         = 0x0410,
 151         [EESR]          = 0x0428,
 152         [EESIPR]        = 0x0430,
 153         [TDLAR]         = 0x0010,
 154         [TDFAR]         = 0x0014,
 155         [TDFXR]         = 0x0018,
 156         [TDFFR]         = 0x001c,
 157         [RDLAR]         = 0x0030,
 158         [RDFAR]         = 0x0034,
 159         [RDFXR]         = 0x0038,
 160         [RDFFR]         = 0x003c,
 161         [TRSCER]        = 0x0438,
 162         [RMFCR]         = 0x0440,
 163         [TFTR]          = 0x0448,
 164         [FDR]           = 0x0450,
 165         [RMCR]          = 0x0458,
 166         [RPADIR]        = 0x0460,
 167         [FCFTR]         = 0x0468,
 168         [CSMR]          = 0x04E4,
 169
 170         [ECMR]          = 0x0500,
 171         [RFLR]          = 0x0508,
 172         [ECSR]          = 0x0510,
 173         [ECSIPR]        = 0x0518,
 174         [PIR]           = 0x0520,
 175         [APR]           = 0x0554,
 176         [MPR]           = 0x0558,
 177         [PFTCR]         = 0x055c,
 178         [PFRCR]         = 0x0560,
 179         [TPAUSER]       = 0x0564,
 180         [MAHR]          = 0x05c0,
 181         [MALR]          = 0x05c8,
 182         [CEFCR]         = 0x0740,
 183         [FRECR]         = 0x0748,
 184         [TSFRCR]        = 0x0750,
 185         [TLFRCR]        = 0x0758,
 186         [RFCR]          = 0x0760,
 187         [MAFCR]         = 0x0778,
 188
 189         [ARSTR]         = 0x0000,
 190         [TSU_CTRST]     = 0x0004,
 191         [TSU_VTAG0]     = 0x0058,
 192         [TSU_ADSBSY]    = 0x0060,
 193         [TSU_TEN]       = 0x0064,
 194         [TSU_ADRH0]     = 0x0100,
 195         [TSU_ADRL0]     = 0x0104,
 196         [TSU_ADRH31]    = 0x01f8,
 197         [TSU_ADRL31]    = 0x01fc,
 198
 199         [TXNLCR0]       = 0x0080,
 200         [TXALCR0]       = 0x0084,
 201         [RXNLCR0]       = 0x0088,
 202         [RXALCR0]       = 0x008C,
 203 };
 204
 205 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 206         [ECMR]          = 0x0300,
 207         [RFLR]          = 0x0308,
 208         [ECSR]          = 0x0310,
 209         [ECSIPR]        = 0x0318,
 210         [PIR]           = 0x0320,
 211         [PSR]           = 0x0328,
 212         [RDMLR]         = 0x0340,
 213         [IPGR]          = 0x0350,
 214         [APR]           = 0x0354,
 215         [MPR]           = 0x0358,
 216         [RFCF]          = 0x0360,
 217         [TPAUSER]       = 0x0364,
 218         [TPAUSECR]      = 0x0368,
 219         [MAHR]          = 0x03c0,
 220         [MALR]          = 0x03c8,
 221         [TROCR]         = 0x03d0,
 222         [CDCR]          = 0x03d4,
 223         [LCCR]          = 0x03d8,
 224         [CNDCR]         = 0x03dc,
 225         [CEFCR]         = 0x03e4,
 226         [FRECR]         = 0x03e8,
 227         [TSFRCR]        = 0x03ec,
 228         [TLFRCR]        = 0x03f0,
 229         [RFCR]          = 0x03f4,
 230         [MAFCR]         = 0x03f8,
 231
 232         [EDMR]          = 0x0200,
 233         [EDTRR]         = 0x0208,
 234         [EDRRR]         = 0x0210,
 235         [TDLAR]         = 0x0218,
 236         [RDLAR]         = 0x0220,
 237         [EESR]          = 0x0228,
 238         [EESIPR]        = 0x0230,
 239         [TRSCER]        = 0x0238,
 240         [RMFCR]         = 0x0240,
 241         [TFTR]          = 0x0248,
 242         [FDR]           = 0x0250,
 243         [RMCR]          = 0x0258,
 244         [TFUCR]         = 0x0264,
 245         [RFOCR]         = 0x0268,
 246         [RMIIMODE]      = 0x026c,
 247         [FCFTR]         = 0x0270,
 248         [TRIMD]         = 0x027c,
 249 };
 250
 251 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 252         [ECMR]          = 0x0100,
 253         [RFLR]          = 0x0108,
 254         [ECSR]          = 0x0110,
 255         [ECSIPR]        = 0x0118,
 256         [PIR]           = 0x0120,
 257         [PSR]           = 0x0128,
 258         [RDMLR]         = 0x0140,
 259         [IPGR]          = 0x0150,
 260         [APR]           = 0x0154,
 261         [MPR]           = 0x0158,
 262         [TPAUSER]       = 0x0164,
 263         [RFCF]          = 0x0160,
 264         [TPAUSECR]      = 0x0168,
 265         [BCFRR]         = 0x016c,
 266         [MAHR]          = 0x01c0,
 267         [MALR]          = 0x01c8,
 268         [TROCR]         = 0x01d0,
 269         [CDCR]          = 0x01d4,
 270         [LCCR]          = 0x01d8,
 271         [CNDCR]         = 0x01dc,
 272         [CEFCR]         = 0x01e4,
 273         [FRECR]         = 0x01e8,
 274         [TSFRCR]        = 0x01ec,
 275         [TLFRCR]        = 0x01f0,
 276         [RFCR]          = 0x01f4,
 277         [MAFCR]         = 0x01f8,
 278         [RTRATE]        = 0x01fc,
 279
 280         [EDMR]          = 0x0000,
 281         [EDTRR]         = 0x0008,
 282         [EDRRR]         = 0x0010,
 283         [TDLAR]         = 0x0018,
 284         [RDLAR]         = 0x0020,
 285         [EESR]          = 0x0028,
 286         [EESIPR]        = 0x0030,
 287         [TRSCER]        = 0x0038,
 288         [RMFCR]         = 0x0040,
 289         [TFTR]          = 0x0048,
 290         [FDR]           = 0x0050,
 291         [RMCR]          = 0x0058,
 292         [TFUCR]         = 0x0064,
 293         [RFOCR]         = 0x0068,
 294         [FCFTR]         = 0x0070,
 295         [RPADIR]        = 0x0078,
 296         [TRIMD]         = 0x007c,
 297         [RBWAR]         = 0x00c8,
 298         [RDFAR]         = 0x00cc,
 299         [TBRAR]         = 0x00d4,
 300         [TDFAR]         = 0x00d8,
 301 };
 302
 303 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 304         [ECMR]          = 0x0160,
 305         [ECSR]          = 0x0164,
 306         [ECSIPR]        = 0x0168,
 307         [PIR]           = 0x016c,
 308         [MAHR]          = 0x0170,
 309         [MALR]          = 0x0174,
 310         [RFLR]          = 0x0178,
 311         [PSR]           = 0x017c,
 312         [TROCR]         = 0x0180,
 313         [CDCR]          = 0x0184,
 314         [LCCR]          = 0x0188,
 315         [CNDCR]         = 0x018c,
 316         [CEFCR]         = 0x0194,
 317         [FRECR]         = 0x0198,
 318         [TSFRCR]        = 0x019c,
 319         [TLFRCR]        = 0x01a0,
 320         [RFCR]          = 0x01a4,
 321         [MAFCR]         = 0x01a8,
 322         [IPGR]          = 0x01b4,
 323         [APR]           = 0x01b8,
 324         [MPR]           = 0x01bc,
 325         [TPAUSER]       = 0x01c4,
 326         [BCFR]          = 0x01cc,
 327
 328         [ARSTR]         = 0x0000,
 329         [TSU_CTRST]     = 0x0004,
 330         [TSU_FWEN0]     = 0x0010,
 331         [TSU_FWEN1]     = 0x0014,
 332         [TSU_FCM]       = 0x0018,
 333         [TSU_BSYSL0]    = 0x0020,
 334         [TSU_BSYSL1]    = 0x0024,
 335         [TSU_PRISL0]    = 0x0028,
 336         [TSU_PRISL1]    = 0x002c,
 337         [TSU_FWSL0]     = 0x0030,
 338         [TSU_FWSL1]     = 0x0034,
 339         [TSU_FWSLC]     = 0x0038,
 340         [TSU_QTAGM0]    = 0x0040,
 341         [TSU_QTAGM1]    = 0x0044,
 342         [TSU_ADQT0]     = 0x0048,
 343         [TSU_ADQT1]     = 0x004c,
 344         [TSU_FWSR]      = 0x0050,
 345         [TSU_FWINMK]    = 0x0054,
 346         [TSU_ADSBSY]    = 0x0060,
 347         [TSU_TEN]       = 0x0064,
 348         [TSU_POST1]     = 0x0070,
 349         [TSU_POST2]     = 0x0074,
 350         [TSU_POST3]     = 0x0078,
 351         [TSU_POST4]     = 0x007c,
 352
 353         [TXNLCR0]       = 0x0080,
 354         [TXALCR0]       = 0x0084,
 355         [RXNLCR0]       = 0x0088,
 356         [RXALCR0]       = 0x008c,
 357         [FWNLCR0]       = 0x0090,
 358         [FWALCR0]       = 0x0094,
 359         [TXNLCR1]       = 0x00a0,
 360         [TXALCR1]       = 0x00a0,
 361         [RXNLCR1]       = 0x00a8,
 362         [RXALCR1]       = 0x00ac,
 363         [FWNLCR1]       = 0x00b0,
 364         [FWALCR1]       = 0x00b4,
 365
 366         [TSU_ADRH0]     = 0x0100,
 367         [TSU_ADRL0]     = 0x0104,
 368         [TSU_ADRL31]    = 0x01fc,
 369 };
 370
 371 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 372 {
 373         return mdp->reg_offset == sh_eth_offset_gigabit;
 374 }
 375
 376 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 377 {
 378         return mdp->reg_offset == sh_eth_offset_fast_rz;
 379 }
 380
 381 static void sh_eth_select_mii(struct net_device *ndev)
 382 {
 383         u32 value = 0x0;
 384         struct sh_eth_private *mdp = netdev_priv(ndev);
 385
 386         switch (mdp->phy_interface) {
 387         case PHY_INTERFACE_MODE_GMII:
 388                 value = 0x2;
 389                 break;
 390         case PHY_INTERFACE_MODE_MII:
 391                 value = 0x1;
 392                 break;
 393         case PHY_INTERFACE_MODE_RMII:
 394                 value = 0x0;
 395                 break;
 396         default:
 397                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 398                 value = 0x1;
 399                 break;
 400         }
 401
 402         sh_eth_write(ndev, value, RMII_MII);
 403 }
 404
 405 static void sh_eth_set_duplex(struct net_device *ndev)
 406 {
 407         struct sh_eth_private *mdp = netdev_priv(ndev);
 408
 409         if (mdp->duplex) /* Full */
 410                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 411         else            /* Half */
 412                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 413 }
 414
 415 /* There is CPU dependent code */
 416 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 417 {
 418         struct sh_eth_private *mdp = netdev_priv(ndev);
 419
 420         switch (mdp->speed) {
 421         case 10: /* 10BASE */
 422                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 423                 break;
 424         case 100:/* 100BASE */
 425                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 426                 break;
 427         default:
 428                 break;
 429         }
 430 }
 431
 432 /* R8A7778/9 */
 433 static struct sh_eth_cpu_data r8a777x_data = {
 434         .set_duplex     = sh_eth_set_duplex,
 435         .set_rate       = sh_eth_set_rate_r8a777x,
 436
 437         .register_type  = SH_ETH_REG_FAST_RCAR,
 438
 439         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 440         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 441         .eesipr_value   = 0x01ff009f,
 442
 443         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 444         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 445                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 446                           EESR_ECI,
 447
 448         .apr            = 1,
 449         .mpr            = 1,
 450         .tpauser        = 1,
 451         .hw_swap        = 1,
 452 };
 453
 454 /* R8A7790/1 */
 455 static struct sh_eth_cpu_data r8a779x_data = {
 456         .set_duplex     = sh_eth_set_duplex,
 457         .set_rate       = sh_eth_set_rate_r8a777x,
 458
 459         .register_type  = SH_ETH_REG_FAST_RCAR,
 460
 461         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 462         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 463         .eesipr_value   = 0x01ff009f,
 464
 465         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 466         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 467                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 468                           EESR_ECI,
 469
 470         .apr            = 1,
 471         .mpr            = 1,
 472         .tpauser        = 1,
 473         .hw_swap        = 1,
 474         .rmiimode       = 1,
 475         .shift_rd0      = 1,
 476 };
 477
 478 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 479 {
 480         struct sh_eth_private *mdp = netdev_priv(ndev);
 481
 482         switch (mdp->speed) {
 483         case 10: /* 10BASE */
 484                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 485                 break;
 486         case 100:/* 100BASE */
 487                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 488                 break;
 489         default:
 490                 break;
 491         }
 492 }
 493
 494 /* SH7724 */
 495 static struct sh_eth_cpu_data sh7724_data = {
 496         .set_duplex     = sh_eth_set_duplex,
 497         .set_rate       = sh_eth_set_rate_sh7724,
 498
 499         .register_type  = SH_ETH_REG_FAST_SH4,
 500
 501         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 502         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 503         .eesipr_value   = 0x01ff009f,
 504
 505         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 506         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 507                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 508                           EESR_ECI,
 509
 510         .apr            = 1,
 511         .mpr            = 1,
 512         .tpauser        = 1,
 513         .hw_swap        = 1,
 514         .rpadir         = 1,
 515         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 516 };
 517
 518 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 519 {
 520         struct sh_eth_private *mdp = netdev_priv(ndev);
 521
 522         switch (mdp->speed) {
 523         case 10: /* 10BASE */
 524                 sh_eth_write(ndev, 0, RTRATE);
 525                 break;
 526         case 100:/* 100BASE */
 527                 sh_eth_write(ndev, 1, RTRATE);
 528                 break;
 529         default:
 530                 break;
 531         }
 532 }
 533
 534 /* SH7757 */
 535 static struct sh_eth_cpu_data sh7757_data = {
 536         .set_duplex     = sh_eth_set_duplex,
 537         .set_rate       = sh_eth_set_rate_sh7757,
 538
 539         .register_type  = SH_ETH_REG_FAST_SH4,
 540
 541         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 542
 543         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 544         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 545                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 546                           EESR_ECI,
 547
 548         .irq_flags      = IRQF_SHARED,
 549         .apr            = 1,
 550         .mpr            = 1,
 551         .tpauser        = 1,
 552         .hw_swap        = 1,
 553         .no_ade         = 1,
 554         .rpadir         = 1,
 555         .rpadir_value   = 2 << 16,
 556 };
 557
 558 #define SH_GIGA_ETH_BASE        0xfee00000UL
 559 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 560 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 561 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 562 {
 563         int i;
 564         unsigned long mahr[2], malr[2];
 565
 566         /* save MAHR and MALR */
 567         for (i = 0; i < 2; i++) {
 568                 malr[i] = ioread32((void *)GIGA_MALR(i));
 569                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 570         }
 571
 572         /* reset device */
 573         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 574         mdelay(1);
 575
 576         /* restore MAHR and MALR */
 577         for (i = 0; i < 2; i++) {
 578                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 579                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 580         }
 581 }
 582
 583 static void sh_eth_set_rate_giga(struct net_device *ndev)
 584 {
 585         struct sh_eth_private *mdp = netdev_priv(ndev);
 586
 587         switch (mdp->speed) {
 588         case 10: /* 10BASE */
 589                 sh_eth_write(ndev, 0x00000000, GECMR);
 590                 break;
 591         case 100:/* 100BASE */
 592                 sh_eth_write(ndev, 0x00000010, GECMR);
 593                 break;
 594         case 1000: /* 1000BASE */
 595                 sh_eth_write(ndev, 0x00000020, GECMR);
 596                 break;
 597         default:
 598                 break;
 599         }
 600 }
 601
 602 /* SH7757(GETHERC) */
 603 static struct sh_eth_cpu_data sh7757_data_giga = {
 604         .chip_reset     = sh_eth_chip_reset_giga,
 605         .set_duplex     = sh_eth_set_duplex,
 606         .set_rate       = sh_eth_set_rate_giga,
 607
 608         .register_type  = SH_ETH_REG_GIGABIT,
 609
 610         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 611         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 612         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 613
 614         .tx_check       = EESR_TC1 | EESR_FTC,
 615         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 616                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 617                           EESR_TDE | EESR_ECI,
 618         .fdr_value      = 0x0000072f,
 619
 620         .irq_flags      = IRQF_SHARED,
 621         .apr            = 1,
 622         .mpr            = 1,
 623         .tpauser        = 1,
 624         .bculr          = 1,
 625         .hw_swap        = 1,
 626         .rpadir         = 1,
 627         .rpadir_value   = 2 << 16,
 628         .no_trimd       = 1,
 629         .no_ade         = 1,
 630         .tsu            = 1,
 631 };
 632
 633 static void sh_eth_chip_reset(struct net_device *ndev)
 634 {
 635         struct sh_eth_private *mdp = netdev_priv(ndev);
 636
 637         /* reset device */
 638         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 639         mdelay(1);
 640 }
 641
 642 static void sh_eth_set_rate_gether(struct net_device *ndev)
 643 {
 644         struct sh_eth_private *mdp = netdev_priv(ndev);
 645
 646         switch (mdp->speed) {
 647         case 10: /* 10BASE */
 648                 sh_eth_write(ndev, GECMR_10, GECMR);
 649                 break;
 650         case 100:/* 100BASE */
 651                 sh_eth_write(ndev, GECMR_100, GECMR);
 652                 break;
 653         case 1000: /* 1000BASE */
 654                 sh_eth_write(ndev, GECMR_1000, GECMR);
 655                 break;
 656         default:
 657                 break;
 658         }
 659 }
 660
 661 /* SH7734 */
 662 static struct sh_eth_cpu_data sh7734_data = {
 663         .chip_reset     = sh_eth_chip_reset,
 664         .set_duplex     = sh_eth_set_duplex,
 665         .set_rate       = sh_eth_set_rate_gether,
 666
 667         .register_type  = SH_ETH_REG_GIGABIT,
 668
 669         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 670         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 671         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 672
 673         .tx_check       = EESR_TC1 | EESR_FTC,
 674         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 675                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 676                           EESR_TDE | EESR_ECI,
 677
 678         .apr            = 1,
 679         .mpr            = 1,
 680         .tpauser        = 1,
 681         .bculr          = 1,
 682         .hw_swap        = 1,
 683         .no_trimd       = 1,
 684         .no_ade         = 1,
 685         .tsu            = 1,
 686         .hw_crc         = 1,
 687         .select_mii     = 1,
 688 };
 689
 690 /* SH7763 */
 691 static struct sh_eth_cpu_data sh7763_data = {
 692         .chip_reset     = sh_eth_chip_reset,
 693         .set_duplex     = sh_eth_set_duplex,
 694         .set_rate       = sh_eth_set_rate_gether,
 695
 696         .register_type  = SH_ETH_REG_GIGABIT,
 697
 698         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 699         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 700         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 701
 702         .tx_check       = EESR_TC1 | EESR_FTC,
 703         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 704                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 705                           EESR_ECI,
 706
 707         .apr            = 1,
 708         .mpr            = 1,
 709         .tpauser        = 1,
 710         .bculr          = 1,
 711         .hw_swap        = 1,
 712         .no_trimd       = 1,
 713         .no_ade         = 1,
 714         .tsu            = 1,
 715         .irq_flags      = IRQF_SHARED,
 716 };
 717
 718 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 719 {
 720         struct sh_eth_private *mdp = netdev_priv(ndev);
 721
 722         /* reset device */
 723         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 724         mdelay(1);
 725
 726         sh_eth_select_mii(ndev);
 727 }
 728
 729 /* R8A7740 */
 730 static struct sh_eth_cpu_data r8a7740_data = {
 731         .chip_reset     = sh_eth_chip_reset_r8a7740,
 732         .set_duplex     = sh_eth_set_duplex,
 733         .set_rate       = sh_eth_set_rate_gether,
 734
 735         .register_type  = SH_ETH_REG_GIGABIT,
 736
 737         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 738         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 739         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 740
 741         .tx_check       = EESR_TC1 | EESR_FTC,
 742         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 743                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 744                           EESR_TDE | EESR_ECI,
 745         .fdr_value      = 0x0000070f,
 746
 747         .apr            = 1,
 748         .mpr            = 1,
 749         .tpauser        = 1,
 750         .bculr          = 1,
 751         .hw_swap        = 1,
 752         .rpadir         = 1,
 753         .rpadir_value   = 2 << 16,
 754         .no_trimd       = 1,
 755         .no_ade         = 1,
 756         .tsu            = 1,
 757         .select_mii     = 1,
 758         .shift_rd0      = 1,
 759 };
 760
 761 /* R7S72100 */
 762 static struct sh_eth_cpu_data r7s72100_data = {
 763         .chip_reset     = sh_eth_chip_reset,
 764         .set_duplex     = sh_eth_set_duplex,
 765
 766         .register_type  = SH_ETH_REG_FAST_RZ,
 767
 768         .ecsr_value     = ECSR_ICD,
 769         .ecsipr_value   = ECSIPR_ICDIP,
 770         .eesipr_value   = 0xff7f009f,
 771
 772         .tx_check       = EESR_TC1 | EESR_FTC,
 773         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 774                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 775                           EESR_TDE | EESR_ECI,
 776         .fdr_value      = 0x0000070f,
 777
 778         .no_psr         = 1,
 779         .apr            = 1,
 780         .mpr            = 1,
 781         .tpauser        = 1,
 782         .hw_swap        = 1,
 783         .rpadir         = 1,
 784         .rpadir_value   = 2 << 16,
 785         .no_trimd       = 1,
 786         .no_ade         = 1,
 787         .hw_crc         = 1,
 788         .tsu            = 1,
 789         .shift_rd0      = 1,
 790 };
 791
 792 static struct sh_eth_cpu_data sh7619_data = {
 793         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 794
 795         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 796
 797         .apr            = 1,
 798         .mpr            = 1,
 799         .tpauser        = 1,
 800         .hw_swap        = 1,
 801 };
 802
 803 static struct sh_eth_cpu_data sh771x_data = {
 804         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 805
 806         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 807         .tsu            = 1,
 808 };
 809
 810 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 811 {
 812         if (!cd->ecsr_value)
 813                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 814
 815         if (!cd->ecsipr_value)
 816                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 817
 818         if (!cd->fcftr_value)
 819                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 820                                   DEFAULT_FIFO_F_D_RFD;
 821
 822         if (!cd->fdr_value)
 823                 cd->fdr_value = DEFAULT_FDR_INIT;
 824
 825         if (!cd->tx_check)
 826                 cd->tx_check = DEFAULT_TX_CHECK;
 827
 828         if (!cd->eesr_err_check)
 829                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 830 }
 831
 832 static int sh_eth_check_reset(struct net_device *ndev)
 833 {
 834         int ret = 0;
 835         int cnt = 100;
 836
 837         while (cnt > 0) {
 838                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 839                         break;
 840                 mdelay(1);
 841                 cnt--;
 842         }
 843         if (cnt <= 0) {
 844                 pr_err("Device reset failed\n");
 845                 ret = -ETIMEDOUT;
 846         }
 847         return ret;
 848 }
 849
 850 static int sh_eth_reset(struct net_device *ndev)
 851 {
 852         struct sh_eth_private *mdp = netdev_priv(ndev);
 853         int ret = 0;
 854
 855         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 856                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 857                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 858                              EDMR);
 859
 860                 ret = sh_eth_check_reset(ndev);
 861                 if (ret)
 862                         goto out;
 863
 864                 /* Table Init */
 865                 sh_eth_write(ndev, 0x0, TDLAR);
 866                 sh_eth_write(ndev, 0x0, TDFAR);
 867                 sh_eth_write(ndev, 0x0, TDFXR);
 868                 sh_eth_write(ndev, 0x0, TDFFR);
 869                 sh_eth_write(ndev, 0x0, RDLAR);
 870                 sh_eth_write(ndev, 0x0, RDFAR);
 871                 sh_eth_write(ndev, 0x0, RDFXR);
 872                 sh_eth_write(ndev, 0x0, RDFFR);
 873
 874                 /* Reset HW CRC register */
 875                 if (mdp->cd->hw_crc)
 876                         sh_eth_write(ndev, 0x0, CSMR);
 877
 878                 /* Select MII mode */
 879                 if (mdp->cd->select_mii)
 880                         sh_eth_select_mii(ndev);
 881         } else {
 882                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 883                              EDMR);
 884                 mdelay(3);
 885                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 886                              EDMR);
 887         }
 888
 889 out:
 890         return ret;
 891 }
 892
 893 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 894 static void sh_eth_set_receive_align(struct sk_buff *skb)
 895 {
 896         int reserve;
 897
 898         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 899         if (reserve)
 900                 skb_reserve(skb, reserve);
 901 }
 902 #else
 903 static void sh_eth_set_receive_align(struct sk_buff *skb)
 904 {
 905         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 906 }
 907 #endif
 908
 909
 910 /* CPU <-> EDMAC endian convert */
 911 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 912 {
 913         switch (mdp->edmac_endian) {
 914         case EDMAC_LITTLE_ENDIAN:
 915                 return cpu_to_le32(x);
 916         case EDMAC_BIG_ENDIAN:
 917                 return cpu_to_be32(x);
 918         }
 919         return x;
 920 }
 921
 922 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 923 {
 924         switch (mdp->edmac_endian) {
 925         case EDMAC_LITTLE_ENDIAN:
 926                 return le32_to_cpu(x);
 927         case EDMAC_BIG_ENDIAN:
 928                 return be32_to_cpu(x);
 929         }
 930         return x;
 931 }
 932
 933 /* Program the hardware MAC address from dev->dev_addr. */
 934 static void update_mac_address(struct net_device *ndev)
 935 {
 936         sh_eth_write(ndev,
 937                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 938                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 939         sh_eth_write(ndev,
 940                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 941 }
 942
 943 /* Get MAC address from SuperH MAC address register
 944  *
 945  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 946  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 947  * When you want use this device, you must set MAC address in bootloader.
 948  *
 949  */
 950 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 951 {
 952         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 953                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 954         } else {
 955                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 956                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 957                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 958                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 959                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 960                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 961         }
 962 }
 963
 964 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 965 {
 966         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 967                 return EDTRR_TRNS_GETHER;
 968         else
 969                 return EDTRR_TRNS_ETHER;
 970 }
 971
 972 struct bb_info {
 973         void (*set_gate)(void *addr);
 974         struct mdiobb_ctrl ctrl;
 975         void *addr;
 976         u32 mmd_msk;/* MMD */
 977         u32 mdo_msk;
 978         u32 mdi_msk;
 979         u32 mdc_msk;
 980 };
 981
 982 /* PHY bit set */
 983 static void bb_set(void *addr, u32 msk)
 984 {
 985         iowrite32(ioread32(addr) | msk, addr);
 986 }
 987
 988 /* PHY bit clear */
 989 static void bb_clr(void *addr, u32 msk)
 990 {
 991         iowrite32((ioread32(addr) & ~msk), addr);
 992 }
 993
 994 /* PHY bit read */
 995 static int bb_read(void *addr, u32 msk)
 996 {
 997         return (ioread32(addr) & msk) != 0;
 998 }
 999
1000 /* Data I/O pin control */
1001 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1002 {
1003         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1004
1005         if (bitbang->set_gate)
1006                 bitbang->set_gate(bitbang->addr);
1007
1008         if (bit)
1009                 bb_set(bitbang->addr, bitbang->mmd_msk);
1010         else
1011                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1012 }
1013
1014 /* Set bit data*/
1015 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1016 {
1017         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1018
1019         if (bitbang->set_gate)
1020                 bitbang->set_gate(bitbang->addr);
1021
1022         if (bit)
1023                 bb_set(bitbang->addr, bitbang->mdo_msk);
1024         else
1025                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1026 }
1027
1028 /* Get bit data*/
1029 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1030 {
1031         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032
1033         if (bitbang->set_gate)
1034                 bitbang->set_gate(bitbang->addr);
1035
1036         return bb_read(bitbang->addr, bitbang->mdi_msk);
1037 }
1038
1039 /* MDC pin control */
1040 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1041 {
1042         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1043
1044         if (bitbang->set_gate)
1045                 bitbang->set_gate(bitbang->addr);
1046
1047         if (bit)
1048                 bb_set(bitbang->addr, bitbang->mdc_msk);
1049         else
1050                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1051 }
1052
1053 /* mdio bus control struct */
1054 static struct mdiobb_ops bb_ops = {
1055         .owner = THIS_MODULE,
1056         .set_mdc = sh_mdc_ctrl,
1057         .set_mdio_dir = sh_mmd_ctrl,
1058         .set_mdio_data = sh_set_mdio,
1059         .get_mdio_data = sh_get_mdio,
1060 };
1061
1062 /* free skb and descriptor buffer */
1063 static void sh_eth_ring_free(struct net_device *ndev)
1064 {
1065         struct sh_eth_private *mdp = netdev_priv(ndev);
1066         int i;
1067
1068         /* Free Rx skb ringbuffer */
1069         if (mdp->rx_skbuff) {
1070                 for (i = 0; i < mdp->num_rx_ring; i++) {
1071                         if (mdp->rx_skbuff[i])
1072                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1073                 }
1074         }
1075         kfree(mdp->rx_skbuff);
1076         mdp->rx_skbuff = NULL;
1077
1078         /* Free Tx skb ringbuffer */
1079         if (mdp->tx_skbuff) {
1080                 for (i = 0; i < mdp->num_tx_ring; i++) {
1081                         if (mdp->tx_skbuff[i])
1082                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1083                 }
1084         }
1085         kfree(mdp->tx_skbuff);
1086         mdp->tx_skbuff = NULL;
1087 }
1088
1089 /* format skb and descriptor buffer */
1090 static void sh_eth_ring_format(struct net_device *ndev)
1091 {
1092         struct sh_eth_private *mdp = netdev_priv(ndev);
1093         int i;
1094         struct sk_buff *skb;
1095         struct sh_eth_rxdesc *rxdesc = NULL;
1096         struct sh_eth_txdesc *txdesc = NULL;
1097         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1098         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1099
1100         mdp->cur_rx = 0;
1101         mdp->cur_tx = 0;
1102         mdp->dirty_rx = 0;
1103         mdp->dirty_tx = 0;
1104
1105         memset(mdp->rx_ring, 0, rx_ringsize);
1106
1107         /* build Rx ring buffer */
1108         for (i = 0; i < mdp->num_rx_ring; i++) {
1109                 /* skb */
1110                 mdp->rx_skbuff[i] = NULL;
1111                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1112                 mdp->rx_skbuff[i] = skb;
1113                 if (skb == NULL)
1114                         break;
1115                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1116                                DMA_FROM_DEVICE);
1117                 sh_eth_set_receive_align(skb);
1118
1119                 /* RX descriptor */
1120                 rxdesc = &mdp->rx_ring[i];
1121                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1122                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1123
1124                 /* The size of the buffer is 16 byte boundary. */
1125                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1126                 /* Rx descriptor address set */
1127                 if (i == 0) {
1128                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1129                         if (sh_eth_is_gether(mdp) ||
1130                             sh_eth_is_rz_fast_ether(mdp))
1131                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1132                 }
1133         }
1134
1135         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1136
1137         /* Mark the last entry as wrapping the ring. */
1138         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1139
1140         memset(mdp->tx_ring, 0, tx_ringsize);
1141
1142         /* build Tx ring buffer */
1143         for (i = 0; i < mdp->num_tx_ring; i++) {
1144                 mdp->tx_skbuff[i] = NULL;
1145                 txdesc = &mdp->tx_ring[i];
1146                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1147                 txdesc->buffer_length = 0;
1148                 if (i == 0) {
1149                         /* Tx descriptor address set */
1150                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1151                         if (sh_eth_is_gether(mdp) ||
1152                             sh_eth_is_rz_fast_ether(mdp))
1153                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1154                 }
1155         }
1156
1157         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1158 }
1159
1160 /* Get skb and descriptor buffer */
1161 static int sh_eth_ring_init(struct net_device *ndev)
1162 {
1163         struct sh_eth_private *mdp = netdev_priv(ndev);
1164         int rx_ringsize, tx_ringsize, ret = 0;
1165
1166         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1167          * card needs room to do 8 byte alignment, +2 so we can reserve
1168          * the first 2 bytes, and +16 gets room for the status word from the
1169          * card.
1170          */
1171         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1172                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1173         if (mdp->cd->rpadir)
1174                 mdp->rx_buf_sz += NET_IP_ALIGN;
1175
1176         /* Allocate RX and TX skb rings */
1177         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1178                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1179         if (!mdp->rx_skbuff) {
1180                 ret = -ENOMEM;
1181                 return ret;
1182         }
1183
1184         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1185                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1186         if (!mdp->tx_skbuff) {
1187                 ret = -ENOMEM;
1188                 goto skb_ring_free;
1189         }
1190
1191         /* Allocate all Rx descriptors. */
1192         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1193         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1194                                           GFP_KERNEL);
1195         if (!mdp->rx_ring) {
1196                 ret = -ENOMEM;
1197                 goto desc_ring_free;
1198         }
1199
1200         mdp->dirty_rx = 0;
1201
1202         /* Allocate all Tx descriptors. */
1203         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1204         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1205                                           GFP_KERNEL);
1206         if (!mdp->tx_ring) {
1207                 ret = -ENOMEM;
1208                 goto desc_ring_free;
1209         }
1210         return ret;
1211
1212 desc_ring_free:
1213         /* free DMA buffer */
1214         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1215
1216 skb_ring_free:
1217         /* Free Rx and Tx skb ring buffer */
1218         sh_eth_ring_free(ndev);
1219         mdp->tx_ring = NULL;
1220         mdp->rx_ring = NULL;
1221
1222         return ret;
1223 }
1224
1225 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1226 {
1227         int ringsize;
1228
1229         if (mdp->rx_ring) {
1230                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1231                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1232                                   mdp->rx_desc_dma);
1233                 mdp->rx_ring = NULL;
1234         }
1235
1236         if (mdp->tx_ring) {
1237                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1238                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1239                                   mdp->tx_desc_dma);
1240                 mdp->tx_ring = NULL;
1241         }
1242 }
1243
1244 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1245 {
1246         int ret = 0;
1247         struct sh_eth_private *mdp = netdev_priv(ndev);
1248         u32 val;
1249
1250         /* Soft Reset */
1251         ret = sh_eth_reset(ndev);
1252         if (ret)
1253                 goto out;
1254
1255         if (mdp->cd->rmiimode)
1256                 sh_eth_write(ndev, 0x1, RMIIMODE);
1257
1258         /* Descriptor format */
1259         sh_eth_ring_format(ndev);
1260         if (mdp->cd->rpadir)
1261                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1262
1263         /* all sh_eth int mask */
1264         sh_eth_write(ndev, 0, EESIPR);
1265
1266 #if defined(__LITTLE_ENDIAN)
1267         if (mdp->cd->hw_swap)
1268                 sh_eth_write(ndev, EDMR_EL, EDMR);
1269         else
1270 #endif
1271                 sh_eth_write(ndev, 0, EDMR);
1272
1273         /* FIFO size set */
1274         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1275         sh_eth_write(ndev, 0, TFTR);
1276
1277         /* Frame recv control (enable multiple-packets per rx irq) */
1278         sh_eth_write(ndev, RMCR_RNC, RMCR);
1279
1280         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1281
1282         if (mdp->cd->bculr)
1283                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1284
1285         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1286
1287         if (!mdp->cd->no_trimd)
1288                 sh_eth_write(ndev, 0, TRIMD);
1289
1290         /* Recv frame limit set register */
1291         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1292                      RFLR);
1293
1294         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1295         if (start)
1296                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1297
1298         /* PAUSE Prohibition */
1299         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1300                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1301
1302         sh_eth_write(ndev, val, ECMR);
1303
1304         if (mdp->cd->set_rate)
1305                 mdp->cd->set_rate(ndev);
1306
1307         /* E-MAC Status Register clear */
1308         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1309
1310         /* E-MAC Interrupt Enable register */
1311         if (start)
1312                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1313
1314         /* Set MAC address */
1315         update_mac_address(ndev);
1316
1317         /* mask reset */
1318         if (mdp->cd->apr)
1319                 sh_eth_write(ndev, APR_AP, APR);
1320         if (mdp->cd->mpr)
1321                 sh_eth_write(ndev, MPR_MP, MPR);
1322         if (mdp->cd->tpauser)
1323                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1324
1325         if (start) {
1326                 /* Setting the Rx mode will start the Rx process. */
1327                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1328
1329                 netif_start_queue(ndev);
1330         }
1331
1332 out:
1333         return ret;
1334 }
1335
1336 /* free Tx skb function */
1337 static int sh_eth_txfree(struct net_device *ndev)
1338 {
1339         struct sh_eth_private *mdp = netdev_priv(ndev);
1340         struct sh_eth_txdesc *txdesc;
1341         int free_num = 0;
1342         int entry = 0;
1343
1344         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1345                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1346                 txdesc = &mdp->tx_ring[entry];
1347                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1348                         break;
1349                 /* Free the original skb. */
1350                 if (mdp->tx_skbuff[entry]) {
1351                         dma_unmap_single(&ndev->dev, txdesc->addr,
1352                                          txdesc->buffer_length, DMA_TO_DEVICE);
1353                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1354                         mdp->tx_skbuff[entry] = NULL;
1355                         free_num++;
1356                 }
1357                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1358                 if (entry >= mdp->num_tx_ring - 1)
1359                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1360
1361                 ndev->stats.tx_packets++;
1362                 ndev->stats.tx_bytes += txdesc->buffer_length;
1363         }
1364         return free_num;
1365 }
1366
1367 /* Packet receive function */
1368 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1369 {
1370         struct sh_eth_private *mdp = netdev_priv(ndev);
1371         struct sh_eth_rxdesc *rxdesc;
1372
1373         int entry = mdp->cur_rx % mdp->num_rx_ring;
1374         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1375         struct sk_buff *skb;
1376         int exceeded = 0;
1377         u16 pkt_len = 0;
1378         u32 desc_status;
1379
1380         rxdesc = &mdp->rx_ring[entry];
1381         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1382                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1383                 pkt_len = rxdesc->frame_length;
1384
1385                 if (--boguscnt < 0)
1386                         break;
1387
1388                 if (*quota <= 0) {
1389                         exceeded = 1;
1390                         break;
1391                 }
1392                 (*quota)--;
1393
1394                 if (!(desc_status & RDFEND))
1395                         ndev->stats.rx_length_errors++;
1396
1397                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1398                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1399                  * bit 0. However, in case of the R8A7740, R8A779x, and
1400                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1401                  * driver needs right shifting by 16.
1402                  */
1403                 if (mdp->cd->shift_rd0)
1404                         desc_status >>= 16;
1405
1406                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1407                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1408                         ndev->stats.rx_errors++;
1409                         if (desc_status & RD_RFS1)
1410                                 ndev->stats.rx_crc_errors++;
1411                         if (desc_status & RD_RFS2)
1412                                 ndev->stats.rx_frame_errors++;
1413                         if (desc_status & RD_RFS3)
1414                                 ndev->stats.rx_length_errors++;
1415                         if (desc_status & RD_RFS4)
1416                                 ndev->stats.rx_length_errors++;
1417                         if (desc_status & RD_RFS6)
1418                                 ndev->stats.rx_missed_errors++;
1419                         if (desc_status & RD_RFS10)
1420                                 ndev->stats.rx_over_errors++;
1421                 } else {
1422                         if (!mdp->cd->hw_swap)
1423                                 sh_eth_soft_swap(
1424                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1425                                         pkt_len + 2);
1426                         skb = mdp->rx_skbuff[entry];
1427                         mdp->rx_skbuff[entry] = NULL;
1428                         if (mdp->cd->rpadir)
1429                                 skb_reserve(skb, NET_IP_ALIGN);
1430                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1431                                                 mdp->rx_buf_sz,
1432                                                 DMA_FROM_DEVICE);
1433                         skb_put(skb, pkt_len);
1434                         skb->protocol = eth_type_trans(skb, ndev);
1435                         netif_receive_skb(skb);
1436                         ndev->stats.rx_packets++;
1437                         ndev->stats.rx_bytes += pkt_len;
1438                 }
1439                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1440                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1441                 rxdesc = &mdp->rx_ring[entry];
1442         }
1443
1444         /* Refill the Rx ring buffers. */
1445         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1446                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1447                 rxdesc = &mdp->rx_ring[entry];
1448                 /* The size of the buffer is 16 byte boundary. */
1449                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1450
1451                 if (mdp->rx_skbuff[entry] == NULL) {
1452                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1453                         mdp->rx_skbuff[entry] = skb;
1454                         if (skb == NULL)
1455                                 break;  /* Better luck next round. */
1456                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1457                                        DMA_FROM_DEVICE);
1458                         sh_eth_set_receive_align(skb);
1459
1460                         skb_checksum_none_assert(skb);
1461                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1462                 }
1463                 if (entry >= mdp->num_rx_ring - 1)
1464                         rxdesc->status |=
1465                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1466                 else
1467                         rxdesc->status |=
1468                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1469         }
1470
1471         /* Restart Rx engine if stopped. */
1472         /* If we don't need to check status, don't. -KDU */
1473         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1474                 /* fix the values for the next receiving if RDE is set */
1475                 if (intr_status & EESR_RDE) {
1476                         u32 count = (sh_eth_read(ndev, RDFAR) -
1477                                      sh_eth_read(ndev, RDLAR)) >> 4;
1478
1479                         mdp->cur_rx = count;
1480                         mdp->dirty_rx = count;
1481                 }
1482                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1483         }
1484
1485         return exceeded;
1486 }
1487
1488 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1489 {
1490         /* disable tx and rx */
1491         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1492                 ~(ECMR_RE | ECMR_TE), ECMR);
1493 }
1494
1495 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1496 {
1497         /* enable tx and rx */
1498         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1499                 (ECMR_RE | ECMR_TE), ECMR);
1500 }
1501
1502 /* error control function */
1503 static void sh_eth_error(struct net_device *ndev, int intr_status)
1504 {
1505         struct sh_eth_private *mdp = netdev_priv(ndev);
1506         u32 felic_stat;
1507         u32 link_stat;
1508         u32 mask;
1509
1510         if (intr_status & EESR_ECI) {
1511                 felic_stat = sh_eth_read(ndev, ECSR);
1512                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1513                 if (felic_stat & ECSR_ICD)
1514                         ndev->stats.tx_carrier_errors++;
1515                 if (felic_stat & ECSR_LCHNG) {
1516                         /* Link Changed */
1517                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1518                                 goto ignore_link;
1519                         } else {
1520                                 link_stat = (sh_eth_read(ndev, PSR));
1521                                 if (mdp->ether_link_active_low)
1522                                         link_stat = ~link_stat;
1523                         }
1524                         if (!(link_stat & PHY_ST_LINK)) {
1525                                 sh_eth_rcv_snd_disable(ndev);
1526                         } else {
1527                                 /* Link Up */
1528                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1529                                                    ~DMAC_M_ECI, EESIPR);
1530                                 /* clear int */
1531                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1532                                              ECSR);
1533                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1534                                                    DMAC_M_ECI, EESIPR);
1535                                 /* enable tx and rx */
1536                                 sh_eth_rcv_snd_enable(ndev);
1537                         }
1538                 }
1539         }
1540
1541 ignore_link:
1542         if (intr_status & EESR_TWB) {
1543                 /* Unused write back interrupt */
1544                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1545                         ndev->stats.tx_aborted_errors++;
1546                         if (netif_msg_tx_err(mdp))
1547                                 dev_err(&ndev->dev, "Transmit Abort\n");
1548                 }
1549         }
1550
1551         if (intr_status & EESR_RABT) {
1552                 /* Receive Abort int */
1553                 if (intr_status & EESR_RFRMER) {
1554                         /* Receive Frame Overflow int */
1555                         ndev->stats.rx_frame_errors++;
1556                         if (netif_msg_rx_err(mdp))
1557                                 dev_err(&ndev->dev, "Receive Abort\n");
1558                 }
1559         }
1560
1561         if (intr_status & EESR_TDE) {
1562                 /* Transmit Descriptor Empty int */
1563                 ndev->stats.tx_fifo_errors++;
1564                 if (netif_msg_tx_err(mdp))
1565                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1566         }
1567
1568         if (intr_status & EESR_TFE) {
1569                 /* FIFO under flow */
1570                 ndev->stats.tx_fifo_errors++;
1571                 if (netif_msg_tx_err(mdp))
1572                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1573         }
1574
1575         if (intr_status & EESR_RDE) {
1576                 /* Receive Descriptor Empty int */
1577                 ndev->stats.rx_over_errors++;
1578
1579                 if (netif_msg_rx_err(mdp))
1580                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1581         }
1582
1583         if (intr_status & EESR_RFE) {
1584                 /* Receive FIFO Overflow int */
1585                 ndev->stats.rx_fifo_errors++;
1586                 if (netif_msg_rx_err(mdp))
1587                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1588         }
1589
1590         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1591                 /* Address Error */
1592                 ndev->stats.tx_fifo_errors++;
1593                 if (netif_msg_tx_err(mdp))
1594                         dev_err(&ndev->dev, "Address Error\n");
1595         }
1596
1597         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1598         if (mdp->cd->no_ade)
1599                 mask &= ~EESR_ADE;
1600         if (intr_status & mask) {
1601                 /* Tx error */
1602                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1603
1604                 /* dmesg */
1605                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1606                         intr_status, mdp->cur_tx, mdp->dirty_tx,
1607                         (u32)ndev->state, edtrr);
1608                 /* dirty buffer free */
1609                 sh_eth_txfree(ndev);
1610
1611                 /* SH7712 BUG */
1612                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1613                         /* tx dma start */
1614                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1615                 }
1616                 /* wakeup */
1617                 netif_wake_queue(ndev);
1618         }
1619 }
1620
1621 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1622 {
1623         struct net_device *ndev = netdev;
1624         struct sh_eth_private *mdp = netdev_priv(ndev);
1625         struct sh_eth_cpu_data *cd = mdp->cd;
1626         irqreturn_t ret = IRQ_NONE;
1627         unsigned long intr_status, intr_enable;
1628
1629         spin_lock(&mdp->lock);
1630
1631         /* Get interrupt status */
1632         intr_status = sh_eth_read(ndev, EESR);
1633         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1634          * enabled since it's the one that  comes thru regardless of the mask,
1635          * and we need to fully handle it in sh_eth_error() in order to quench
1636          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1637          */
1638         intr_enable = sh_eth_read(ndev, EESIPR);
1639         intr_status &= intr_enable | DMAC_M_ECI;
1640         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1641                 ret = IRQ_HANDLED;
1642         else
1643                 goto other_irq;
1644
1645         if (intr_status & EESR_RX_CHECK) {
1646                 if (napi_schedule_prep(&mdp->napi)) {
1647                         /* Mask Rx interrupts */
1648                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1649                                      EESIPR);
1650                         __napi_schedule(&mdp->napi);
1651                 } else {
1652                         dev_warn(&ndev->dev,
1653                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1654                                  intr_status, intr_enable);
1655                 }
1656         }
1657
1658         /* Tx Check */
1659         if (intr_status & cd->tx_check) {
1660                 /* Clear Tx interrupts */
1661                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1662
1663                 sh_eth_txfree(ndev);
1664                 netif_wake_queue(ndev);
1665         }
1666
1667         if (intr_status & cd->eesr_err_check) {
1668                 /* Clear error interrupts */
1669                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1670
1671                 sh_eth_error(ndev, intr_status);
1672         }
1673
1674 other_irq:
1675         spin_unlock(&mdp->lock);
1676
1677         return ret;
1678 }
1679
1680 static int sh_eth_poll(struct napi_struct *napi, int budget)
1681 {
1682         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1683                                                   napi);
1684         struct net_device *ndev = napi->dev;
1685         int quota = budget;
1686         unsigned long intr_status;
1687
1688         for (;;) {
1689                 intr_status = sh_eth_read(ndev, EESR);
1690                 if (!(intr_status & EESR_RX_CHECK))
1691                         break;
1692                 /* Clear Rx interrupts */
1693                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1694
1695                 if (sh_eth_rx(ndev, intr_status, &quota))
1696                         goto out;
1697         }
1698
1699         napi_complete(napi);
1700
1701         /* Reenable Rx interrupts */
1702         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1703 out:
1704         return budget - quota;
1705 }
1706
1707 /* PHY state control function */
1708 static void sh_eth_adjust_link(struct net_device *ndev)
1709 {
1710         struct sh_eth_private *mdp = netdev_priv(ndev);
1711         struct phy_device *phydev = mdp->phydev;
1712         int new_state = 0;
1713
1714         if (phydev->link) {
1715                 if (phydev->duplex != mdp->duplex) {
1716                         new_state = 1;
1717                         mdp->duplex = phydev->duplex;
1718                         if (mdp->cd->set_duplex)
1719                                 mdp->cd->set_duplex(ndev);
1720                 }
1721
1722                 if (phydev->speed != mdp->speed) {
1723                         new_state = 1;
1724                         mdp->speed = phydev->speed;
1725                         if (mdp->cd->set_rate)
1726                                 mdp->cd->set_rate(ndev);
1727                 }
1728                 if (!mdp->link) {
1729                         sh_eth_write(ndev,
1730                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1731                                      ECMR);
1732                         new_state = 1;
1733                         mdp->link = phydev->link;
1734                         if (mdp->cd->no_psr || mdp->no_ether_link)
1735                                 sh_eth_rcv_snd_enable(ndev);
1736                 }
1737         } else if (mdp->link) {
1738                 new_state = 1;
1739                 mdp->link = 0;
1740                 mdp->speed = 0;
1741                 mdp->duplex = -1;
1742                 if (mdp->cd->no_psr || mdp->no_ether_link)
1743                         sh_eth_rcv_snd_disable(ndev);
1744         }
1745
1746         if (new_state && netif_msg_link(mdp))
1747                 phy_print_status(phydev);
1748 }
1749
1750 /* PHY init function */
1751 static int sh_eth_phy_init(struct net_device *ndev)
1752 {
1753         struct sh_eth_private *mdp = netdev_priv(ndev);
1754         char phy_id[MII_BUS_ID_SIZE + 3];
1755         struct phy_device *phydev = NULL;
1756
1757         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1758                  mdp->mii_bus->id, mdp->phy_id);
1759
1760         mdp->link = 0;
1761         mdp->speed = 0;
1762         mdp->duplex = -1;
1763
1764         /* Try connect to PHY */
1765         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1766                              mdp->phy_interface);
1767         if (IS_ERR(phydev)) {
1768                 dev_err(&ndev->dev, "phy_connect failed\n");
1769                 return PTR_ERR(phydev);
1770         }
1771
1772         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1773                  phydev->addr, phydev->irq, phydev->drv->name);
1774
1775         mdp->phydev = phydev;
1776
1777         return 0;
1778 }
1779
1780 /* PHY control start function */
1781 static int sh_eth_phy_start(struct net_device *ndev)
1782 {
1783         struct sh_eth_private *mdp = netdev_priv(ndev);
1784         int ret;
1785
1786         ret = sh_eth_phy_init(ndev);
1787         if (ret)
1788                 return ret;
1789
1790         phy_start(mdp->phydev);
1791
1792         return 0;
1793 }
1794
1795 static int sh_eth_get_settings(struct net_device *ndev,
1796                                struct ethtool_cmd *ecmd)
1797 {
1798         struct sh_eth_private *mdp = netdev_priv(ndev);
1799         unsigned long flags;
1800         int ret;
1801
1802         spin_lock_irqsave(&mdp->lock, flags);
1803         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1804         spin_unlock_irqrestore(&mdp->lock, flags);
1805
1806         return ret;
1807 }
1808
1809 static int sh_eth_set_settings(struct net_device *ndev,
1810                                struct ethtool_cmd *ecmd)
1811 {
1812         struct sh_eth_private *mdp = netdev_priv(ndev);
1813         unsigned long flags;
1814         int ret;
1815
1816         spin_lock_irqsave(&mdp->lock, flags);
1817
1818         /* disable tx and rx */
1819         sh_eth_rcv_snd_disable(ndev);
1820
1821         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1822         if (ret)
1823                 goto error_exit;
1824
1825         if (ecmd->duplex == DUPLEX_FULL)
1826                 mdp->duplex = 1;
1827         else
1828                 mdp->duplex = 0;
1829
1830         if (mdp->cd->set_duplex)
1831                 mdp->cd->set_duplex(ndev);
1832
1833 error_exit:
1834         mdelay(1);
1835
1836         /* enable tx and rx */
1837         sh_eth_rcv_snd_enable(ndev);
1838
1839         spin_unlock_irqrestore(&mdp->lock, flags);
1840
1841         return ret;
1842 }
1843
1844 static int sh_eth_nway_reset(struct net_device *ndev)
1845 {
1846         struct sh_eth_private *mdp = netdev_priv(ndev);
1847         unsigned long flags;
1848         int ret;
1849
1850         spin_lock_irqsave(&mdp->lock, flags);
1851         ret = phy_start_aneg(mdp->phydev);
1852         spin_unlock_irqrestore(&mdp->lock, flags);
1853
1854         return ret;
1855 }
1856
1857 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1858 {
1859         struct sh_eth_private *mdp = netdev_priv(ndev);
1860         return mdp->msg_enable;
1861 }
1862
1863 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1864 {
1865         struct sh_eth_private *mdp = netdev_priv(ndev);
1866         mdp->msg_enable = value;
1867 }
1868
1869 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1870         "rx_current", "tx_current",
1871         "rx_dirty", "tx_dirty",
1872 };
1873 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1874
1875 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1876 {
1877         switch (sset) {
1878         case ETH_SS_STATS:
1879                 return SH_ETH_STATS_LEN;
1880         default:
1881                 return -EOPNOTSUPP;
1882         }
1883 }
1884
1885 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1886                                      struct ethtool_stats *stats, u64 *data)
1887 {
1888         struct sh_eth_private *mdp = netdev_priv(ndev);
1889         int i = 0;
1890
1891         /* device-specific stats */
1892         data[i++] = mdp->cur_rx;
1893         data[i++] = mdp->cur_tx;
1894         data[i++] = mdp->dirty_rx;
1895         data[i++] = mdp->dirty_tx;
1896 }
1897
1898 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1899 {
1900         switch (stringset) {
1901         case ETH_SS_STATS:
1902                 memcpy(data, *sh_eth_gstrings_stats,
1903                        sizeof(sh_eth_gstrings_stats));
1904                 break;
1905         }
1906 }
1907
1908 static void sh_eth_get_ringparam(struct net_device *ndev,
1909                                  struct ethtool_ringparam *ring)
1910 {
1911         struct sh_eth_private *mdp = netdev_priv(ndev);
1912
1913         ring->rx_max_pending = RX_RING_MAX;
1914         ring->tx_max_pending = TX_RING_MAX;
1915         ring->rx_pending = mdp->num_rx_ring;
1916         ring->tx_pending = mdp->num_tx_ring;
1917 }
1918
1919 static int sh_eth_set_ringparam(struct net_device *ndev,
1920                                 struct ethtool_ringparam *ring)
1921 {
1922         struct sh_eth_private *mdp = netdev_priv(ndev);
1923         int ret;
1924
1925         if (ring->tx_pending > TX_RING_MAX ||
1926             ring->rx_pending > RX_RING_MAX ||
1927             ring->tx_pending < TX_RING_MIN ||
1928             ring->rx_pending < RX_RING_MIN)
1929                 return -EINVAL;
1930         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1931                 return -EINVAL;
1932
1933         if (netif_running(ndev)) {
1934                 netif_tx_disable(ndev);
1935                 /* Disable interrupts by clearing the interrupt mask. */
1936                 sh_eth_write(ndev, 0x0000, EESIPR);
1937                 /* Stop the chip's Tx and Rx processes. */
1938                 sh_eth_write(ndev, 0, EDTRR);
1939                 sh_eth_write(ndev, 0, EDRRR);
1940                 synchronize_irq(ndev->irq);
1941         }
1942
1943         /* Free all the skbuffs in the Rx queue. */
1944         sh_eth_ring_free(ndev);
1945         /* Free DMA buffer */
1946         sh_eth_free_dma_buffer(mdp);
1947
1948         /* Set new parameters */
1949         mdp->num_rx_ring = ring->rx_pending;
1950         mdp->num_tx_ring = ring->tx_pending;
1951
1952         ret = sh_eth_ring_init(ndev);
1953         if (ret < 0) {
1954                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1955                 return ret;
1956         }
1957         ret = sh_eth_dev_init(ndev, false);
1958         if (ret < 0) {
1959                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1960                 return ret;
1961         }
1962
1963         if (netif_running(ndev)) {
1964                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1965                 /* Setting the Rx mode will start the Rx process. */
1966                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1967                 netif_wake_queue(ndev);
1968         }
1969
1970         return 0;
1971 }
1972
1973 static const struct ethtool_ops sh_eth_ethtool_ops = {
1974         .get_settings   = sh_eth_get_settings,
1975         .set_settings   = sh_eth_set_settings,
1976         .nway_reset     = sh_eth_nway_reset,
1977         .get_msglevel   = sh_eth_get_msglevel,
1978         .set_msglevel   = sh_eth_set_msglevel,
1979         .get_link       = ethtool_op_get_link,
1980         .get_strings    = sh_eth_get_strings,
1981         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1982         .get_sset_count     = sh_eth_get_sset_count,
1983         .get_ringparam  = sh_eth_get_ringparam,
1984         .set_ringparam  = sh_eth_set_ringparam,
1985 };
1986
1987 /* network device open function */
1988 static int sh_eth_open(struct net_device *ndev)
1989 {
1990         int ret = 0;
1991         struct sh_eth_private *mdp = netdev_priv(ndev);
1992
1993         pm_runtime_get_sync(&mdp->pdev->dev);
1994
1995         napi_enable(&mdp->napi);
1996
1997         ret = request_irq(ndev->irq, sh_eth_interrupt,
1998                           mdp->cd->irq_flags, ndev->name, ndev);
1999         if (ret) {
2000                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
2001                 goto out_napi_off;
2002         }
2003
2004         /* Descriptor set */
2005         ret = sh_eth_ring_init(ndev);
2006         if (ret)
2007                 goto out_free_irq;
2008
2009         /* device init */
2010         ret = sh_eth_dev_init(ndev, true);
2011         if (ret)
2012                 goto out_free_irq;
2013
2014         /* PHY control start*/
2015         ret = sh_eth_phy_start(ndev);
2016         if (ret)
2017                 goto out_free_irq;
2018
2019         return ret;
2020
2021 out_free_irq:
2022         free_irq(ndev->irq, ndev);
2023 out_napi_off:
2024         napi_disable(&mdp->napi);
2025         pm_runtime_put_sync(&mdp->pdev->dev);
2026         return ret;
2027 }
2028
2029 /* Timeout function */
2030 static void sh_eth_tx_timeout(struct net_device *ndev)
2031 {
2032         struct sh_eth_private *mdp = netdev_priv(ndev);
2033         struct sh_eth_rxdesc *rxdesc;
2034         int i;
2035
2036         netif_stop_queue(ndev);
2037
2038         if (netif_msg_timer(mdp)) {
2039                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
2040                         ndev->name, (int)sh_eth_read(ndev, EESR));
2041         }
2042
2043         /* tx_errors count up */
2044         ndev->stats.tx_errors++;
2045
2046         /* Free all the skbuffs in the Rx queue. */
2047         for (i = 0; i < mdp->num_rx_ring; i++) {
2048                 rxdesc = &mdp->rx_ring[i];
2049                 rxdesc->status = 0;
2050                 rxdesc->addr = 0xBADF00D0;
2051                 if (mdp->rx_skbuff[i])
2052                         dev_kfree_skb(mdp->rx_skbuff[i]);
2053                 mdp->rx_skbuff[i] = NULL;
2054         }
2055         for (i = 0; i < mdp->num_tx_ring; i++) {
2056                 if (mdp->tx_skbuff[i])
2057                         dev_kfree_skb(mdp->tx_skbuff[i]);
2058                 mdp->tx_skbuff[i] = NULL;
2059         }
2060
2061         /* device init */
2062         sh_eth_dev_init(ndev, true);
2063 }
2064
2065 /* Packet transmit function */
2066 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2067 {
2068         struct sh_eth_private *mdp = netdev_priv(ndev);
2069         struct sh_eth_txdesc *txdesc;
2070         u32 entry;
2071         unsigned long flags;
2072
2073         spin_lock_irqsave(&mdp->lock, flags);
2074         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2075                 if (!sh_eth_txfree(ndev)) {
2076                         if (netif_msg_tx_queued(mdp))
2077                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2078                         netif_stop_queue(ndev);
2079                         spin_unlock_irqrestore(&mdp->lock, flags);
2080                         return NETDEV_TX_BUSY;
2081                 }
2082         }
2083         spin_unlock_irqrestore(&mdp->lock, flags);
2084
2085         entry = mdp->cur_tx % mdp->num_tx_ring;
2086         mdp->tx_skbuff[entry] = skb;
2087         txdesc = &mdp->tx_ring[entry];
2088         /* soft swap. */
2089         if (!mdp->cd->hw_swap)
2090                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2091                                  skb->len + 2);
2092         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2093                                       DMA_TO_DEVICE);
2094         if (skb->len < ETHERSMALL)
2095                 txdesc->buffer_length = ETHERSMALL;
2096         else
2097                 txdesc->buffer_length = skb->len;
2098
2099         if (entry >= mdp->num_tx_ring - 1)
2100                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2101         else
2102                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2103
2104         mdp->cur_tx++;
2105
2106         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2107                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2108
2109         return NETDEV_TX_OK;
2110 }
2111
2112 /* device close function */
2113 static int sh_eth_close(struct net_device *ndev)
2114 {
2115         struct sh_eth_private *mdp = netdev_priv(ndev);
2116
2117         netif_stop_queue(ndev);
2118
2119         /* Disable interrupts by clearing the interrupt mask. */
2120         sh_eth_write(ndev, 0x0000, EESIPR);
2121
2122         /* Stop the chip's Tx and Rx processes. */
2123         sh_eth_write(ndev, 0, EDTRR);
2124         sh_eth_write(ndev, 0, EDRRR);
2125
2126         /* PHY Disconnect */
2127         if (mdp->phydev) {
2128                 phy_stop(mdp->phydev);
2129                 phy_disconnect(mdp->phydev);
2130         }
2131
2132         free_irq(ndev->irq, ndev);
2133
2134         napi_disable(&mdp->napi);
2135
2136         /* Free all the skbuffs in the Rx queue. */
2137         sh_eth_ring_free(ndev);
2138
2139         /* free DMA buffer */
2140         sh_eth_free_dma_buffer(mdp);
2141
2142         pm_runtime_put_sync(&mdp->pdev->dev);
2143
2144         return 0;
2145 }
2146
2147 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2148 {
2149         struct sh_eth_private *mdp = netdev_priv(ndev);
2150
2151         if (sh_eth_is_rz_fast_ether(mdp))
2152                 return &ndev->stats;
2153
2154         pm_runtime_get_sync(&mdp->pdev->dev);
2155
2156         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2157         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2158         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2159         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2160         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2161         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2162         if (sh_eth_is_gether(mdp)) {
2163                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2164                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2165                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2166                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2167         } else {
2168                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2169                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2170         }
2171         pm_runtime_put_sync(&mdp->pdev->dev);
2172
2173         return &ndev->stats;
2174 }
2175
2176 /* ioctl to device function */
2177 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2178 {
2179         struct sh_eth_private *mdp = netdev_priv(ndev);
2180         struct phy_device *phydev = mdp->phydev;
2181
2182         if (!netif_running(ndev))
2183                 return -EINVAL;
2184
2185         if (!phydev)
2186                 return -ENODEV;
2187
2188         return phy_mii_ioctl(phydev, rq, cmd);
2189 }
2190
2191 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2192 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2193                                             int entry)
2194 {
2195         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2196 }
2197
2198 static u32 sh_eth_tsu_get_post_mask(int entry)
2199 {
2200         return 0x0f << (28 - ((entry % 8) * 4));
2201 }
2202
2203 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2204 {
2205         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2206 }
2207
2208 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2209                                              int entry)
2210 {
2211         struct sh_eth_private *mdp = netdev_priv(ndev);
2212         u32 tmp;
2213         void *reg_offset;
2214
2215         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2216         tmp = ioread32(reg_offset);
2217         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2218 }
2219
2220 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2221                                               int entry)
2222 {
2223         struct sh_eth_private *mdp = netdev_priv(ndev);
2224         u32 post_mask, ref_mask, tmp;
2225         void *reg_offset;
2226
2227         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2228         post_mask = sh_eth_tsu_get_post_mask(entry);
2229         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2230
2231         tmp = ioread32(reg_offset);
2232         iowrite32(tmp & ~post_mask, reg_offset);
2233
2234         /* If other port enables, the function returns "true" */
2235         return tmp & ref_mask;
2236 }
2237
2238 static int sh_eth_tsu_busy(struct net_device *ndev)
2239 {
2240         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2241         struct sh_eth_private *mdp = netdev_priv(ndev);
2242
2243         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2244                 udelay(10);
2245                 timeout--;
2246                 if (timeout <= 0) {
2247                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2248                         return -ETIMEDOUT;
2249                 }
2250         }
2251
2252         return 0;
2253 }
2254
2255 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2256                                   const u8 *addr)
2257 {
2258         u32 val;
2259
2260         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2261         iowrite32(val, reg);
2262         if (sh_eth_tsu_busy(ndev) < 0)
2263                 return -EBUSY;
2264
2265         val = addr[4] << 8 | addr[5];
2266         iowrite32(val, reg + 4);
2267         if (sh_eth_tsu_busy(ndev) < 0)
2268                 return -EBUSY;
2269
2270         return 0;
2271 }
2272
2273 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2274 {
2275         u32 val;
2276
2277         val = ioread32(reg);
2278         addr[0] = (val >> 24) & 0xff;
2279         addr[1] = (val >> 16) & 0xff;
2280         addr[2] = (val >> 8) & 0xff;
2281         addr[3] = val & 0xff;
2282         val = ioread32(reg + 4);
2283         addr[4] = (val >> 8) & 0xff;
2284         addr[5] = val & 0xff;
2285 }
2286
2287
2288 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2289 {
2290         struct sh_eth_private *mdp = netdev_priv(ndev);
2291         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2292         int i;
2293         u8 c_addr[ETH_ALEN];
2294
2295         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2296                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2297                 if (ether_addr_equal(addr, c_addr))
2298                         return i;
2299         }
2300
2301         return -ENOENT;
2302 }
2303
2304 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2305 {
2306         u8 blank[ETH_ALEN];
2307         int entry;
2308
2309         memset(blank, 0, sizeof(blank));
2310         entry = sh_eth_tsu_find_entry(ndev, blank);
2311         return (entry < 0) ? -ENOMEM : entry;
2312 }
2313
2314 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2315                                               int entry)
2316 {
2317         struct sh_eth_private *mdp = netdev_priv(ndev);
2318         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2319         int ret;
2320         u8 blank[ETH_ALEN];
2321
2322         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2323                          ~(1 << (31 - entry)), TSU_TEN);
2324
2325         memset(blank, 0, sizeof(blank));
2326         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2327         if (ret < 0)
2328                 return ret;
2329         return 0;
2330 }
2331
2332 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2333 {
2334         struct sh_eth_private *mdp = netdev_priv(ndev);
2335         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2336         int i, ret;
2337
2338         if (!mdp->cd->tsu)
2339                 return 0;
2340
2341         i = sh_eth_tsu_find_entry(ndev, addr);
2342         if (i < 0) {
2343                 /* No entry found, create one */
2344                 i = sh_eth_tsu_find_empty(ndev);
2345                 if (i < 0)
2346                         return -ENOMEM;
2347                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2348                 if (ret < 0)
2349                         return ret;
2350
2351                 /* Enable the entry */
2352                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2353                                  (1 << (31 - i)), TSU_TEN);
2354         }
2355
2356         /* Entry found or created, enable POST */
2357         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2358
2359         return 0;
2360 }
2361
2362 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2363 {
2364         struct sh_eth_private *mdp = netdev_priv(ndev);
2365         int i, ret;
2366
2367         if (!mdp->cd->tsu)
2368                 return 0;
2369
2370         i = sh_eth_tsu_find_entry(ndev, addr);
2371         if (i) {
2372                 /* Entry found */
2373                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2374                         goto done;
2375
2376                 /* Disable the entry if both ports was disabled */
2377                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2378                 if (ret < 0)
2379                         return ret;
2380         }
2381 done:
2382         return 0;
2383 }
2384
2385 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2386 {
2387         struct sh_eth_private *mdp = netdev_priv(ndev);
2388         int i, ret;
2389
2390         if (unlikely(!mdp->cd->tsu))
2391                 return 0;
2392
2393         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2394                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2395                         continue;
2396
2397                 /* Disable the entry if both ports was disabled */
2398                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2399                 if (ret < 0)
2400                         return ret;
2401         }
2402
2403         return 0;
2404 }
2405
2406 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2407 {
2408         struct sh_eth_private *mdp = netdev_priv(ndev);
2409         u8 addr[ETH_ALEN];
2410         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2411         int i;
2412
2413         if (unlikely(!mdp->cd->tsu))
2414                 return;
2415
2416         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2417                 sh_eth_tsu_read_entry(reg_offset, addr);
2418                 if (is_multicast_ether_addr(addr))
2419                         sh_eth_tsu_del_entry(ndev, addr);
2420         }
2421 }
2422
2423 /* Multicast reception directions set */
2424 static void sh_eth_set_multicast_list(struct net_device *ndev)
2425 {
2426         struct sh_eth_private *mdp = netdev_priv(ndev);
2427         u32 ecmr_bits;
2428         int mcast_all = 0;
2429         unsigned long flags;
2430
2431         spin_lock_irqsave(&mdp->lock, flags);
2432         /* Initial condition is MCT = 1, PRM = 0.
2433          * Depending on ndev->flags, set PRM or clear MCT
2434          */
2435         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2436
2437         if (!(ndev->flags & IFF_MULTICAST)) {
2438                 sh_eth_tsu_purge_mcast(ndev);
2439                 mcast_all = 1;
2440         }
2441         if (ndev->flags & IFF_ALLMULTI) {
2442                 sh_eth_tsu_purge_mcast(ndev);
2443                 ecmr_bits &= ~ECMR_MCT;
2444                 mcast_all = 1;
2445         }
2446
2447         if (ndev->flags & IFF_PROMISC) {
2448                 sh_eth_tsu_purge_all(ndev);
2449                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2450         } else if (mdp->cd->tsu) {
2451                 struct netdev_hw_addr *ha;
2452                 netdev_for_each_mc_addr(ha, ndev) {
2453                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2454                                 continue;
2455
2456                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2457                                 if (!mcast_all) {
2458                                         sh_eth_tsu_purge_mcast(ndev);
2459                                         ecmr_bits &= ~ECMR_MCT;
2460                                         mcast_all = 1;
2461                                 }
2462                         }
2463                 }
2464         } else {
2465                 /* Normal, unicast/broadcast-only mode. */
2466                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2467         }
2468
2469         /* update the ethernet mode */
2470         sh_eth_write(ndev, ecmr_bits, ECMR);
2471
2472         spin_unlock_irqrestore(&mdp->lock, flags);
2473 }
2474
2475 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2476 {
2477         if (!mdp->port)
2478                 return TSU_VTAG0;
2479         else
2480                 return TSU_VTAG1;
2481 }
2482
2483 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2484                                   __be16 proto, u16 vid)
2485 {
2486         struct sh_eth_private *mdp = netdev_priv(ndev);
2487         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2488
2489         if (unlikely(!mdp->cd->tsu))
2490                 return -EPERM;
2491
2492         /* No filtering if vid = 0 */
2493         if (!vid)
2494                 return 0;
2495
2496         mdp->vlan_num_ids++;
2497
2498         /* The controller has one VLAN tag HW filter. So, if the filter is
2499          * already enabled, the driver disables it and the filte
2500          */
2501         if (mdp->vlan_num_ids > 1) {
2502                 /* disable VLAN filter */
2503                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2504                 return 0;
2505         }
2506
2507         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2508                          vtag_reg_index);
2509
2510         return 0;
2511 }
2512
2513 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2514                                    __be16 proto, u16 vid)
2515 {
2516         struct sh_eth_private *mdp = netdev_priv(ndev);
2517         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2518
2519         if (unlikely(!mdp->cd->tsu))
2520                 return -EPERM;
2521
2522         /* No filtering if vid = 0 */
2523         if (!vid)
2524                 return 0;
2525
2526         mdp->vlan_num_ids--;
2527         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2528
2529         return 0;
2530 }
2531
2532 /* SuperH's TSU register init function */
2533 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2534 {
2535         if (sh_eth_is_rz_fast_ether(mdp)) {
2536                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2537                 return;
2538         }
2539
2540         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2541         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2542         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2543         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2544         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2545         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2546         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2547         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2548         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2549         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2550         if (sh_eth_is_gether(mdp)) {
2551                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2552                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2553         } else {
2554                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2555                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2556         }
2557         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2558         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2559         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2560         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2561         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2562         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2563         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2564 }
2565
2566 /* MDIO bus release function */
2567 static int sh_mdio_release(struct net_device *ndev)
2568 {
2569         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2570
2571         /* unregister mdio bus */
2572         mdiobus_unregister(bus);
2573
2574         /* remove mdio bus info from net_device */
2575         dev_set_drvdata(&ndev->dev, NULL);
2576
2577         /* free bitbang info */
2578         free_mdio_bitbang(bus);
2579
2580         return 0;
2581 }
2582
2583 /* MDIO bus init function */
2584 static int sh_mdio_init(struct net_device *ndev, int id,
2585                         struct sh_eth_plat_data *pd)
2586 {
2587         int ret, i;
2588         struct bb_info *bitbang;
2589         struct sh_eth_private *mdp = netdev_priv(ndev);
2590
2591         /* create bit control struct for PHY */
2592         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2593                                GFP_KERNEL);
2594         if (!bitbang) {
2595                 ret = -ENOMEM;
2596                 goto out;
2597         }
2598
2599         /* bitbang init */
2600         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2601         bitbang->set_gate = pd->set_mdio_gate;
2602         bitbang->mdi_msk = PIR_MDI;
2603         bitbang->mdo_msk = PIR_MDO;
2604         bitbang->mmd_msk = PIR_MMD;
2605         bitbang->mdc_msk = PIR_MDC;
2606         bitbang->ctrl.ops = &bb_ops;
2607
2608         /* MII controller setting */
2609         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2610         if (!mdp->mii_bus) {
2611                 ret = -ENOMEM;
2612                 goto out;
2613         }
2614
2615         /* Hook up MII support for ethtool */
2616         mdp->mii_bus->name = "sh_mii";
2617         mdp->mii_bus->parent = &ndev->dev;
2618         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2619                  mdp->pdev->name, id);
2620
2621         /* PHY IRQ */
2622         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2623                                          sizeof(int) * PHY_MAX_ADDR,
2624                                          GFP_KERNEL);
2625         if (!mdp->mii_bus->irq) {
2626                 ret = -ENOMEM;
2627                 goto out_free_bus;
2628         }
2629
2630         for (i = 0; i < PHY_MAX_ADDR; i++)
2631                 mdp->mii_bus->irq[i] = PHY_POLL;
2632         if (pd->phy_irq > 0)
2633                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2634
2635         /* register mdio bus */
2636         ret = mdiobus_register(mdp->mii_bus);
2637         if (ret)
2638                 goto out_free_bus;
2639
2640         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2641
2642         return 0;
2643
2644 out_free_bus:
2645         free_mdio_bitbang(mdp->mii_bus);
2646
2647 out:
2648         return ret;
2649 }
2650
2651 static const u16 *sh_eth_get_register_offset(int register_type)
2652 {
2653         const u16 *reg_offset = NULL;
2654
2655         switch (register_type) {
2656         case SH_ETH_REG_GIGABIT:
2657                 reg_offset = sh_eth_offset_gigabit;
2658                 break;
2659         case SH_ETH_REG_FAST_RZ:
2660                 reg_offset = sh_eth_offset_fast_rz;
2661                 break;
2662         case SH_ETH_REG_FAST_RCAR:
2663                 reg_offset = sh_eth_offset_fast_rcar;
2664                 break;
2665         case SH_ETH_REG_FAST_SH4:
2666                 reg_offset = sh_eth_offset_fast_sh4;
2667                 break;
2668         case SH_ETH_REG_FAST_SH3_SH2:
2669                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2670                 break;
2671         default:
2672                 pr_err("Unknown register type (%d)\n", register_type);
2673                 break;
2674         }
2675
2676         return reg_offset;
2677 }
2678
2679 static const struct net_device_ops sh_eth_netdev_ops = {
2680         .ndo_open               = sh_eth_open,
2681         .ndo_stop               = sh_eth_close,
2682         .ndo_start_xmit         = sh_eth_start_xmit,
2683         .ndo_get_stats          = sh_eth_get_stats,
2684         .ndo_tx_timeout         = sh_eth_tx_timeout,
2685         .ndo_do_ioctl           = sh_eth_do_ioctl,
2686         .ndo_validate_addr      = eth_validate_addr,
2687         .ndo_set_mac_address    = eth_mac_addr,
2688         .ndo_change_mtu         = eth_change_mtu,
2689 };
2690
2691 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2692         .ndo_open               = sh_eth_open,
2693         .ndo_stop               = sh_eth_close,
2694         .ndo_start_xmit         = sh_eth_start_xmit,
2695         .ndo_get_stats          = sh_eth_get_stats,
2696         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2697         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2698         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2699         .ndo_tx_timeout         = sh_eth_tx_timeout,
2700         .ndo_do_ioctl           = sh_eth_do_ioctl,
2701         .ndo_validate_addr      = eth_validate_addr,
2702         .ndo_set_mac_address    = eth_mac_addr,
2703         .ndo_change_mtu         = eth_change_mtu,
2704 };
2705
2706 static int sh_eth_drv_probe(struct platform_device *pdev)
2707 {
2708         int ret, devno = 0;
2709         struct resource *res;
2710         struct net_device *ndev = NULL;
2711         struct sh_eth_private *mdp = NULL;
2712         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2713         const struct platform_device_id *id = platform_get_device_id(pdev);
2714
2715         /* get base addr */
2716         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2717         if (unlikely(res == NULL)) {
2718                 dev_err(&pdev->dev, "invalid resource\n");
2719                 ret = -EINVAL;
2720                 goto out;
2721         }
2722
2723         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2724         if (!ndev) {
2725                 ret = -ENOMEM;
2726                 goto out;
2727         }
2728
2729         /* The sh Ether-specific entries in the device structure. */
2730         ndev->base_addr = res->start;
2731         devno = pdev->id;
2732         if (devno < 0)
2733                 devno = 0;
2734
2735         ndev->dma = -1;
2736         ret = platform_get_irq(pdev, 0);
2737         if (ret < 0) {
2738                 ret = -ENODEV;
2739                 goto out_release;
2740         }
2741         ndev->irq = ret;
2742
2743         SET_NETDEV_DEV(ndev, &pdev->dev);
2744
2745         mdp = netdev_priv(ndev);
2746         mdp->num_tx_ring = TX_RING_SIZE;
2747         mdp->num_rx_ring = RX_RING_SIZE;
2748         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2749         if (IS_ERR(mdp->addr)) {
2750                 ret = PTR_ERR(mdp->addr);
2751                 goto out_release;
2752         }
2753
2754         spin_lock_init(&mdp->lock);
2755         mdp->pdev = pdev;
2756         pm_runtime_enable(&pdev->dev);
2757         pm_runtime_resume(&pdev->dev);
2758
2759         if (!pd) {
2760                 dev_err(&pdev->dev, "no platform data\n");
2761                 ret = -EINVAL;
2762                 goto out_release;
2763         }
2764
2765         /* get PHY ID */
2766         mdp->phy_id = pd->phy;
2767         mdp->phy_interface = pd->phy_interface;
2768         /* EDMAC endian */
2769         mdp->edmac_endian = pd->edmac_endian;
2770         mdp->no_ether_link = pd->no_ether_link;
2771         mdp->ether_link_active_low = pd->ether_link_active_low;
2772
2773         /* set cpu data */
2774         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2775         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2776         sh_eth_set_default_cpu_data(mdp->cd);
2777
2778         /* set function */
2779         if (mdp->cd->tsu)
2780                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2781         else
2782                 ndev->netdev_ops = &sh_eth_netdev_ops;
2783         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2784         ndev->watchdog_timeo = TX_TIMEOUT;
2785
2786         /* debug message level */
2787         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2788
2789         /* read and set MAC address */
2790         read_mac_address(ndev, pd->mac_addr);
2791         if (!is_valid_ether_addr(ndev->dev_addr)) {
2792                 dev_warn(&pdev->dev,
2793                          "no valid MAC address supplied, using a random one.\n");
2794                 eth_hw_addr_random(ndev);
2795         }
2796
2797         /* ioremap the TSU registers */
2798         if (mdp->cd->tsu) {
2799                 struct resource *rtsu;
2800                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2801                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2802                 if (IS_ERR(mdp->tsu_addr)) {
2803                         ret = PTR_ERR(mdp->tsu_addr);
2804                         goto out_release;
2805                 }
2806                 mdp->port = devno % 2;
2807                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2808         }
2809
2810         /* initialize first or needed device */
2811         if (!devno || pd->needs_init) {
2812                 if (mdp->cd->chip_reset)
2813                         mdp->cd->chip_reset(ndev);
2814
2815                 if (mdp->cd->tsu) {
2816                         /* TSU init (Init only)*/
2817                         sh_eth_tsu_init(mdp);
2818                 }
2819         }
2820
2821         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2822
2823         /* network device register */
2824         ret = register_netdev(ndev);
2825         if (ret)
2826                 goto out_napi_del;
2827
2828         /* mdio bus init */
2829         ret = sh_mdio_init(ndev, pdev->id, pd);
2830         if (ret)
2831                 goto out_unregister;
2832
2833         /* print device information */
2834         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2835                 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2836
2837         platform_set_drvdata(pdev, ndev);
2838
2839         return ret;
2840
2841 out_unregister:
2842         unregister_netdev(ndev);
2843
2844 out_napi_del:
2845         netif_napi_del(&mdp->napi);
2846
2847 out_release:
2848         /* net_dev free */
2849         if (ndev)
2850                 free_netdev(ndev);
2851
2852 out:
2853         return ret;
2854 }
2855
2856 static int sh_eth_drv_remove(struct platform_device *pdev)
2857 {
2858         struct net_device *ndev = platform_get_drvdata(pdev);
2859         struct sh_eth_private *mdp = netdev_priv(ndev);
2860
2861         sh_mdio_release(ndev);
2862         unregister_netdev(ndev);
2863         netif_napi_del(&mdp->napi);
2864         pm_runtime_disable(&pdev->dev);
2865         free_netdev(ndev);
2866
2867         return 0;
2868 }
2869
2870 #ifdef CONFIG_PM
2871 static int sh_eth_runtime_nop(struct device *dev)
2872 {
2873         /* Runtime PM callback shared between ->runtime_suspend()
2874          * and ->runtime_resume(). Simply returns success.
2875          *
2876          * This driver re-initializes all registers after
2877          * pm_runtime_get_sync() anyway so there is no need
2878          * to save and restore registers here.
2879          */
2880         return 0;
2881 }
2882
2883 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2884         .runtime_suspend = sh_eth_runtime_nop,
2885         .runtime_resume = sh_eth_runtime_nop,
2886 };
2887 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2888 #else
2889 #define SH_ETH_PM_OPS NULL
2890 #endif
2891
2892 static struct platform_device_id sh_eth_id_table[] = {
2893         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2894         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2895         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2896         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2897         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2898         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2899         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2900         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2901         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2902         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2903         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2904         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2905         { }
2906 };
2907 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2908
2909 static struct platform_driver sh_eth_driver = {
2910         .probe = sh_eth_drv_probe,
2911         .remove = sh_eth_drv_remove,
2912         .id_table = sh_eth_id_table,
2913         .driver = {
2914                    .name = CARDNAME,
2915                    .pm = SH_ETH_PM_OPS,
2916         },
2917 };
2918
2919 module_platform_driver(sh_eth_driver);
2920
2921 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2922 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2923 MODULE_LICENSE("GPL v2");