drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   5  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   6  *  Copyright (C) 2014 Codethink Limited
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *
  17  *  The full GNU General Public License is included in this distribution in
  18  *  the file called "COPYING".
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/delay.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mdio-bitbang.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/of_net.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44 #include <linux/of_mdio.h>
  45
  46 #include "sh_eth.h"
  47
  48 #define SH_ETH_DEF_MSG_ENABLE \
  49                 (NETIF_MSG_LINK | \
  50                 NETIF_MSG_TIMER | \
  51                 NETIF_MSG_RX_ERR| \
  52                 NETIF_MSG_TX_ERR)
  53
  54 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  55         [EDSR]          = 0x0000,
  56         [EDMR]          = 0x0400,
  57         [EDTRR]         = 0x0408,
  58         [EDRRR]         = 0x0410,
  59         [EESR]          = 0x0428,
  60         [EESIPR]        = 0x0430,
  61         [TDLAR]         = 0x0010,
  62         [TDFAR]         = 0x0014,
  63         [TDFXR]         = 0x0018,
  64         [TDFFR]         = 0x001c,
  65         [RDLAR]         = 0x0030,
  66         [RDFAR]         = 0x0034,
  67         [RDFXR]         = 0x0038,
  68         [RDFFR]         = 0x003c,
  69         [TRSCER]        = 0x0438,
  70         [RMFCR]         = 0x0440,
  71         [TFTR]          = 0x0448,
  72         [FDR]           = 0x0450,
  73         [RMCR]          = 0x0458,
  74         [RPADIR]        = 0x0460,
  75         [FCFTR]         = 0x0468,
  76         [CSMR]          = 0x04E4,
  77
  78         [ECMR]          = 0x0500,
  79         [ECSR]          = 0x0510,
  80         [ECSIPR]        = 0x0518,
  81         [PIR]           = 0x0520,
  82         [PSR]           = 0x0528,
  83         [PIPR]          = 0x052c,
  84         [RFLR]          = 0x0508,
  85         [APR]           = 0x0554,
  86         [MPR]           = 0x0558,
  87         [PFTCR]         = 0x055c,
  88         [PFRCR]         = 0x0560,
  89         [TPAUSER]       = 0x0564,
  90         [GECMR]         = 0x05b0,
  91         [BCULR]         = 0x05b4,
  92         [MAHR]          = 0x05c0,
  93         [MALR]          = 0x05c8,
  94         [TROCR]         = 0x0700,
  95         [CDCR]          = 0x0708,
  96         [LCCR]          = 0x0710,
  97         [CEFCR]         = 0x0740,
  98         [FRECR]         = 0x0748,
  99         [TSFRCR]        = 0x0750,
 100         [TLFRCR]        = 0x0758,
 101         [RFCR]          = 0x0760,
 102         [CERCR]         = 0x0768,
 103         [CEECR]         = 0x0770,
 104         [MAFCR]         = 0x0778,
 105         [RMII_MII]      = 0x0790,
 106
 107         [ARSTR]         = 0x0000,
 108         [TSU_CTRST]     = 0x0004,
 109         [TSU_FWEN0]     = 0x0010,
 110         [TSU_FWEN1]     = 0x0014,
 111         [TSU_FCM]       = 0x0018,
 112         [TSU_BSYSL0]    = 0x0020,
 113         [TSU_BSYSL1]    = 0x0024,
 114         [TSU_PRISL0]    = 0x0028,
 115         [TSU_PRISL1]    = 0x002c,
 116         [TSU_FWSL0]     = 0x0030,
 117         [TSU_FWSL1]     = 0x0034,
 118         [TSU_FWSLC]     = 0x0038,
 119         [TSU_QTAG0]     = 0x0040,
 120         [TSU_QTAG1]     = 0x0044,
 121         [TSU_FWSR]      = 0x0050,
 122         [TSU_FWINMK]    = 0x0054,
 123         [TSU_ADQT0]     = 0x0048,
 124         [TSU_ADQT1]     = 0x004c,
 125         [TSU_VTAG0]     = 0x0058,
 126         [TSU_VTAG1]     = 0x005c,
 127         [TSU_ADSBSY]    = 0x0060,
 128         [TSU_TEN]       = 0x0064,
 129         [TSU_POST1]     = 0x0070,
 130         [TSU_POST2]     = 0x0074,
 131         [TSU_POST3]     = 0x0078,
 132         [TSU_POST4]     = 0x007c,
 133         [TSU_ADRH0]     = 0x0100,
 134         [TSU_ADRL0]     = 0x0104,
 135         [TSU_ADRH31]    = 0x01f8,
 136         [TSU_ADRL31]    = 0x01fc,
 137
 138         [TXNLCR0]       = 0x0080,
 139         [TXALCR0]       = 0x0084,
 140         [RXNLCR0]       = 0x0088,
 141         [RXALCR0]       = 0x008c,
 142         [FWNLCR0]       = 0x0090,
 143         [FWALCR0]       = 0x0094,
 144         [TXNLCR1]       = 0x00a0,
 145         [TXALCR1]       = 0x00a0,
 146         [RXNLCR1]       = 0x00a8,
 147         [RXALCR1]       = 0x00ac,
 148         [FWNLCR1]       = 0x00b0,
 149         [FWALCR1]       = 0x00b4,
 150 };
 151
 152 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 153         [EDSR]          = 0x0000,
 154         [EDMR]          = 0x0400,
 155         [EDTRR]         = 0x0408,
 156         [EDRRR]         = 0x0410,
 157         [EESR]          = 0x0428,
 158         [EESIPR]        = 0x0430,
 159         [TDLAR]         = 0x0010,
 160         [TDFAR]         = 0x0014,
 161         [TDFXR]         = 0x0018,
 162         [TDFFR]         = 0x001c,
 163         [RDLAR]         = 0x0030,
 164         [RDFAR]         = 0x0034,
 165         [RDFXR]         = 0x0038,
 166         [RDFFR]         = 0x003c,
 167         [TRSCER]        = 0x0438,
 168         [RMFCR]         = 0x0440,
 169         [TFTR]          = 0x0448,
 170         [FDR]           = 0x0450,
 171         [RMCR]          = 0x0458,
 172         [RPADIR]        = 0x0460,
 173         [FCFTR]         = 0x0468,
 174         [CSMR]          = 0x04E4,
 175
 176         [ECMR]          = 0x0500,
 177         [RFLR]          = 0x0508,
 178         [ECSR]          = 0x0510,
 179         [ECSIPR]        = 0x0518,
 180         [PIR]           = 0x0520,
 181         [APR]           = 0x0554,
 182         [MPR]           = 0x0558,
 183         [PFTCR]         = 0x055c,
 184         [PFRCR]         = 0x0560,
 185         [TPAUSER]       = 0x0564,
 186         [MAHR]          = 0x05c0,
 187         [MALR]          = 0x05c8,
 188         [CEFCR]         = 0x0740,
 189         [FRECR]         = 0x0748,
 190         [TSFRCR]        = 0x0750,
 191         [TLFRCR]        = 0x0758,
 192         [RFCR]          = 0x0760,
 193         [MAFCR]         = 0x0778,
 194
 195         [ARSTR]         = 0x0000,
 196         [TSU_CTRST]     = 0x0004,
 197         [TSU_VTAG0]     = 0x0058,
 198         [TSU_ADSBSY]    = 0x0060,
 199         [TSU_TEN]       = 0x0064,
 200         [TSU_ADRH0]     = 0x0100,
 201         [TSU_ADRL0]     = 0x0104,
 202         [TSU_ADRH31]    = 0x01f8,
 203         [TSU_ADRL31]    = 0x01fc,
 204
 205         [TXNLCR0]       = 0x0080,
 206         [TXALCR0]       = 0x0084,
 207         [RXNLCR0]       = 0x0088,
 208         [RXALCR0]       = 0x008C,
 209 };
 210
 211 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 212         [ECMR]          = 0x0300,
 213         [RFLR]          = 0x0308,
 214         [ECSR]          = 0x0310,
 215         [ECSIPR]        = 0x0318,
 216         [PIR]           = 0x0320,
 217         [PSR]           = 0x0328,
 218         [RDMLR]         = 0x0340,
 219         [IPGR]          = 0x0350,
 220         [APR]           = 0x0354,
 221         [MPR]           = 0x0358,
 222         [RFCF]          = 0x0360,
 223         [TPAUSER]       = 0x0364,
 224         [TPAUSECR]      = 0x0368,
 225         [MAHR]          = 0x03c0,
 226         [MALR]          = 0x03c8,
 227         [TROCR]         = 0x03d0,
 228         [CDCR]          = 0x03d4,
 229         [LCCR]          = 0x03d8,
 230         [CNDCR]         = 0x03dc,
 231         [CEFCR]         = 0x03e4,
 232         [FRECR]         = 0x03e8,
 233         [TSFRCR]        = 0x03ec,
 234         [TLFRCR]        = 0x03f0,
 235         [RFCR]          = 0x03f4,
 236         [MAFCR]         = 0x03f8,
 237
 238         [EDMR]          = 0x0200,
 239         [EDTRR]         = 0x0208,
 240         [EDRRR]         = 0x0210,
 241         [TDLAR]         = 0x0218,
 242         [RDLAR]         = 0x0220,
 243         [EESR]          = 0x0228,
 244         [EESIPR]        = 0x0230,
 245         [TRSCER]        = 0x0238,
 246         [RMFCR]         = 0x0240,
 247         [TFTR]          = 0x0248,
 248         [FDR]           = 0x0250,
 249         [RMCR]          = 0x0258,
 250         [TFUCR]         = 0x0264,
 251         [RFOCR]         = 0x0268,
 252         [RMIIMODE]      = 0x026c,
 253         [FCFTR]         = 0x0270,
 254         [TRIMD]         = 0x027c,
 255 };
 256
 257 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 258         [ECMR]          = 0x0100,
 259         [RFLR]          = 0x0108,
 260         [ECSR]          = 0x0110,
 261         [ECSIPR]        = 0x0118,
 262         [PIR]           = 0x0120,
 263         [PSR]           = 0x0128,
 264         [RDMLR]         = 0x0140,
 265         [IPGR]          = 0x0150,
 266         [APR]           = 0x0154,
 267         [MPR]           = 0x0158,
 268         [TPAUSER]       = 0x0164,
 269         [RFCF]          = 0x0160,
 270         [TPAUSECR]      = 0x0168,
 271         [BCFRR]         = 0x016c,
 272         [MAHR]          = 0x01c0,
 273         [MALR]          = 0x01c8,
 274         [TROCR]         = 0x01d0,
 275         [CDCR]          = 0x01d4,
 276         [LCCR]          = 0x01d8,
 277         [CNDCR]         = 0x01dc,
 278         [CEFCR]         = 0x01e4,
 279         [FRECR]         = 0x01e8,
 280         [TSFRCR]        = 0x01ec,
 281         [TLFRCR]        = 0x01f0,
 282         [RFCR]          = 0x01f4,
 283         [MAFCR]         = 0x01f8,
 284         [RTRATE]        = 0x01fc,
 285
 286         [EDMR]          = 0x0000,
 287         [EDTRR]         = 0x0008,
 288         [EDRRR]         = 0x0010,
 289         [TDLAR]         = 0x0018,
 290         [RDLAR]         = 0x0020,
 291         [EESR]          = 0x0028,
 292         [EESIPR]        = 0x0030,
 293         [TRSCER]        = 0x0038,
 294         [RMFCR]         = 0x0040,
 295         [TFTR]          = 0x0048,
 296         [FDR]           = 0x0050,
 297         [RMCR]          = 0x0058,
 298         [TFUCR]         = 0x0064,
 299         [RFOCR]         = 0x0068,
 300         [FCFTR]         = 0x0070,
 301         [RPADIR]        = 0x0078,
 302         [TRIMD]         = 0x007c,
 303         [RBWAR]         = 0x00c8,
 304         [RDFAR]         = 0x00cc,
 305         [TBRAR]         = 0x00d4,
 306         [TDFAR]         = 0x00d8,
 307 };
 308
 309 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 310         [EDMR]          = 0x0000,
 311         [EDTRR]         = 0x0004,
 312         [EDRRR]         = 0x0008,
 313         [TDLAR]         = 0x000c,
 314         [RDLAR]         = 0x0010,
 315         [EESR]          = 0x0014,
 316         [EESIPR]        = 0x0018,
 317         [TRSCER]        = 0x001c,
 318         [RMFCR]         = 0x0020,
 319         [TFTR]          = 0x0024,
 320         [FDR]           = 0x0028,
 321         [RMCR]          = 0x002c,
 322         [EDOCR]         = 0x0030,
 323         [FCFTR]         = 0x0034,
 324         [RPADIR]        = 0x0038,
 325         [TRIMD]         = 0x003c,
 326         [RBWAR]         = 0x0040,
 327         [RDFAR]         = 0x0044,
 328         [TBRAR]         = 0x004c,
 329         [TDFAR]         = 0x0050,
 330
 331         [ECMR]          = 0x0160,
 332         [ECSR]          = 0x0164,
 333         [ECSIPR]        = 0x0168,
 334         [PIR]           = 0x016c,
 335         [MAHR]          = 0x0170,
 336         [MALR]          = 0x0174,
 337         [RFLR]          = 0x0178,
 338         [PSR]           = 0x017c,
 339         [TROCR]         = 0x0180,
 340         [CDCR]          = 0x0184,
 341         [LCCR]          = 0x0188,
 342         [CNDCR]         = 0x018c,
 343         [CEFCR]         = 0x0194,
 344         [FRECR]         = 0x0198,
 345         [TSFRCR]        = 0x019c,
 346         [TLFRCR]        = 0x01a0,
 347         [RFCR]          = 0x01a4,
 348         [MAFCR]         = 0x01a8,
 349         [IPGR]          = 0x01b4,
 350         [APR]           = 0x01b8,
 351         [MPR]           = 0x01bc,
 352         [TPAUSER]       = 0x01c4,
 353         [BCFR]          = 0x01cc,
 354
 355         [ARSTR]         = 0x0000,
 356         [TSU_CTRST]     = 0x0004,
 357         [TSU_FWEN0]     = 0x0010,
 358         [TSU_FWEN1]     = 0x0014,
 359         [TSU_FCM]       = 0x0018,
 360         [TSU_BSYSL0]    = 0x0020,
 361         [TSU_BSYSL1]    = 0x0024,
 362         [TSU_PRISL0]    = 0x0028,
 363         [TSU_PRISL1]    = 0x002c,
 364         [TSU_FWSL0]     = 0x0030,
 365         [TSU_FWSL1]     = 0x0034,
 366         [TSU_FWSLC]     = 0x0038,
 367         [TSU_QTAGM0]    = 0x0040,
 368         [TSU_QTAGM1]    = 0x0044,
 369         [TSU_ADQT0]     = 0x0048,
 370         [TSU_ADQT1]     = 0x004c,
 371         [TSU_FWSR]      = 0x0050,
 372         [TSU_FWINMK]    = 0x0054,
 373         [TSU_ADSBSY]    = 0x0060,
 374         [TSU_TEN]       = 0x0064,
 375         [TSU_POST1]     = 0x0070,
 376         [TSU_POST2]     = 0x0074,
 377         [TSU_POST3]     = 0x0078,
 378         [TSU_POST4]     = 0x007c,
 379
 380         [TXNLCR0]       = 0x0080,
 381         [TXALCR0]       = 0x0084,
 382         [RXNLCR0]       = 0x0088,
 383         [RXALCR0]       = 0x008c,
 384         [FWNLCR0]       = 0x0090,
 385         [FWALCR0]       = 0x0094,
 386         [TXNLCR1]       = 0x00a0,
 387         [TXALCR1]       = 0x00a0,
 388         [RXNLCR1]       = 0x00a8,
 389         [RXALCR1]       = 0x00ac,
 390         [FWNLCR1]       = 0x00b0,
 391         [FWALCR1]       = 0x00b4,
 392
 393         [TSU_ADRH0]     = 0x0100,
 394         [TSU_ADRL0]     = 0x0104,
 395         [TSU_ADRL31]    = 0x01fc,
 396 };
 397
 398 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 399 {
 400         return mdp->reg_offset == sh_eth_offset_gigabit;
 401 }
 402
 403 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 404 {
 405         return mdp->reg_offset == sh_eth_offset_fast_rz;
 406 }
 407
 408 static void sh_eth_select_mii(struct net_device *ndev)
 409 {
 410         u32 value = 0x0;
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412
 413         switch (mdp->phy_interface) {
 414         case PHY_INTERFACE_MODE_GMII:
 415                 value = 0x2;
 416                 break;
 417         case PHY_INTERFACE_MODE_MII:
 418                 value = 0x1;
 419                 break;
 420         case PHY_INTERFACE_MODE_RMII:
 421                 value = 0x0;
 422                 break;
 423         default:
 424                 netdev_warn(ndev,
 425                             "PHY interface mode was not setup. Set to MII.\n");
 426                 value = 0x1;
 427                 break;
 428         }
 429
 430         sh_eth_write(ndev, value, RMII_MII);
 431 }
 432
 433 static void sh_eth_set_duplex(struct net_device *ndev)
 434 {
 435         struct sh_eth_private *mdp = netdev_priv(ndev);
 436
 437         if (mdp->duplex) /* Full */
 438                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 439         else            /* Half */
 440                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 441 }
 442
 443 /* There is CPU dependent code */
 444 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 445 {
 446         struct sh_eth_private *mdp = netdev_priv(ndev);
 447
 448         switch (mdp->speed) {
 449         case 10: /* 10BASE */
 450                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 451                 break;
 452         case 100:/* 100BASE */
 453                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 454                 break;
 455         default:
 456                 break;
 457         }
 458 }
 459
 460 /* R8A7778/9 */
 461 static struct sh_eth_cpu_data r8a777x_data = {
 462         .set_duplex     = sh_eth_set_duplex,
 463         .set_rate       = sh_eth_set_rate_r8a777x,
 464
 465         .register_type  = SH_ETH_REG_FAST_RCAR,
 466
 467         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 468         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 469         .eesipr_value   = 0x01ff009f,
 470
 471         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 472         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 473                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 474                           EESR_ECI,
 475
 476         .apr            = 1,
 477         .mpr            = 1,
 478         .tpauser        = 1,
 479         .hw_swap        = 1,
 480 };
 481
 482 /* R8A7790/1 */
 483 static struct sh_eth_cpu_data r8a779x_data = {
 484         .set_duplex     = sh_eth_set_duplex,
 485         .set_rate       = sh_eth_set_rate_r8a777x,
 486
 487         .register_type  = SH_ETH_REG_FAST_RCAR,
 488
 489         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 490         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 491         .eesipr_value   = 0x01ff009f,
 492
 493         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 494         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 495                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 496                           EESR_ECI,
 497
 498         .apr            = 1,
 499         .mpr            = 1,
 500         .tpauser        = 1,
 501         .hw_swap        = 1,
 502         .rmiimode       = 1,
 503         .shift_rd0      = 1,
 504 };
 505
 506 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 507 {
 508         struct sh_eth_private *mdp = netdev_priv(ndev);
 509
 510         switch (mdp->speed) {
 511         case 10: /* 10BASE */
 512                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 513                 break;
 514         case 100:/* 100BASE */
 515                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 516                 break;
 517         default:
 518                 break;
 519         }
 520 }
 521
 522 /* SH7724 */
 523 static struct sh_eth_cpu_data sh7724_data = {
 524         .set_duplex     = sh_eth_set_duplex,
 525         .set_rate       = sh_eth_set_rate_sh7724,
 526
 527         .register_type  = SH_ETH_REG_FAST_SH4,
 528
 529         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 530         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 531         .eesipr_value   = 0x01ff009f,
 532
 533         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 534         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 535                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 536                           EESR_ECI,
 537
 538         .apr            = 1,
 539         .mpr            = 1,
 540         .tpauser        = 1,
 541         .hw_swap        = 1,
 542         .rpadir         = 1,
 543         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 544 };
 545
 546 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 547 {
 548         struct sh_eth_private *mdp = netdev_priv(ndev);
 549
 550         switch (mdp->speed) {
 551         case 10: /* 10BASE */
 552                 sh_eth_write(ndev, 0, RTRATE);
 553                 break;
 554         case 100:/* 100BASE */
 555                 sh_eth_write(ndev, 1, RTRATE);
 556                 break;
 557         default:
 558                 break;
 559         }
 560 }
 561
 562 /* SH7757 */
 563 static struct sh_eth_cpu_data sh7757_data = {
 564         .set_duplex     = sh_eth_set_duplex,
 565         .set_rate       = sh_eth_set_rate_sh7757,
 566
 567         .register_type  = SH_ETH_REG_FAST_SH4,
 568
 569         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 570
 571         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 572         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 573                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 574                           EESR_ECI,
 575
 576         .irq_flags      = IRQF_SHARED,
 577         .apr            = 1,
 578         .mpr            = 1,
 579         .tpauser        = 1,
 580         .hw_swap        = 1,
 581         .no_ade         = 1,
 582         .rpadir         = 1,
 583         .rpadir_value   = 2 << 16,
 584 };
 585
 586 #define SH_GIGA_ETH_BASE        0xfee00000UL
 587 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 588 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 589 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 590 {
 591         int i;
 592         unsigned long mahr[2], malr[2];
 593
 594         /* save MAHR and MALR */
 595         for (i = 0; i < 2; i++) {
 596                 malr[i] = ioread32((void *)GIGA_MALR(i));
 597                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 598         }
 599
 600         /* reset device */
 601         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 602         mdelay(1);
 603
 604         /* restore MAHR and MALR */
 605         for (i = 0; i < 2; i++) {
 606                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 607                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 608         }
 609 }
 610
 611 static void sh_eth_set_rate_giga(struct net_device *ndev)
 612 {
 613         struct sh_eth_private *mdp = netdev_priv(ndev);
 614
 615         switch (mdp->speed) {
 616         case 10: /* 10BASE */
 617                 sh_eth_write(ndev, 0x00000000, GECMR);
 618                 break;
 619         case 100:/* 100BASE */
 620                 sh_eth_write(ndev, 0x00000010, GECMR);
 621                 break;
 622         case 1000: /* 1000BASE */
 623                 sh_eth_write(ndev, 0x00000020, GECMR);
 624                 break;
 625         default:
 626                 break;
 627         }
 628 }
 629
 630 /* SH7757(GETHERC) */
 631 static struct sh_eth_cpu_data sh7757_data_giga = {
 632         .chip_reset     = sh_eth_chip_reset_giga,
 633         .set_duplex     = sh_eth_set_duplex,
 634         .set_rate       = sh_eth_set_rate_giga,
 635
 636         .register_type  = SH_ETH_REG_GIGABIT,
 637
 638         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 639         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 640         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 641
 642         .tx_check       = EESR_TC1 | EESR_FTC,
 643         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 644                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 645                           EESR_TDE | EESR_ECI,
 646         .fdr_value      = 0x0000072f,
 647
 648         .irq_flags      = IRQF_SHARED,
 649         .apr            = 1,
 650         .mpr            = 1,
 651         .tpauser        = 1,
 652         .bculr          = 1,
 653         .hw_swap        = 1,
 654         .rpadir         = 1,
 655         .rpadir_value   = 2 << 16,
 656         .no_trimd       = 1,
 657         .no_ade         = 1,
 658         .tsu            = 1,
 659 };
 660
 661 static void sh_eth_chip_reset(struct net_device *ndev)
 662 {
 663         struct sh_eth_private *mdp = netdev_priv(ndev);
 664
 665         /* reset device */
 666         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 667         mdelay(1);
 668 }
 669
 670 static void sh_eth_set_rate_gether(struct net_device *ndev)
 671 {
 672         struct sh_eth_private *mdp = netdev_priv(ndev);
 673
 674         switch (mdp->speed) {
 675         case 10: /* 10BASE */
 676                 sh_eth_write(ndev, GECMR_10, GECMR);
 677                 break;
 678         case 100:/* 100BASE */
 679                 sh_eth_write(ndev, GECMR_100, GECMR);
 680                 break;
 681         case 1000: /* 1000BASE */
 682                 sh_eth_write(ndev, GECMR_1000, GECMR);
 683                 break;
 684         default:
 685                 break;
 686         }
 687 }
 688
 689 /* SH7734 */
 690 static struct sh_eth_cpu_data sh7734_data = {
 691         .chip_reset     = sh_eth_chip_reset,
 692         .set_duplex     = sh_eth_set_duplex,
 693         .set_rate       = sh_eth_set_rate_gether,
 694
 695         .register_type  = SH_ETH_REG_GIGABIT,
 696
 697         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 698         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 699         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 700
 701         .tx_check       = EESR_TC1 | EESR_FTC,
 702         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 703                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 704                           EESR_TDE | EESR_ECI,
 705
 706         .apr            = 1,
 707         .mpr            = 1,
 708         .tpauser        = 1,
 709         .bculr          = 1,
 710         .hw_swap        = 1,
 711         .no_trimd       = 1,
 712         .no_ade         = 1,
 713         .tsu            = 1,
 714         .hw_crc         = 1,
 715         .select_mii     = 1,
 716 };
 717
 718 /* SH7763 */
 719 static struct sh_eth_cpu_data sh7763_data = {
 720         .chip_reset     = sh_eth_chip_reset,
 721         .set_duplex     = sh_eth_set_duplex,
 722         .set_rate       = sh_eth_set_rate_gether,
 723
 724         .register_type  = SH_ETH_REG_GIGABIT,
 725
 726         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 727         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 728         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 729
 730         .tx_check       = EESR_TC1 | EESR_FTC,
 731         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 732                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 733                           EESR_ECI,
 734
 735         .apr            = 1,
 736         .mpr            = 1,
 737         .tpauser        = 1,
 738         .bculr          = 1,
 739         .hw_swap        = 1,
 740         .no_trimd       = 1,
 741         .no_ade         = 1,
 742         .tsu            = 1,
 743         .irq_flags      = IRQF_SHARED,
 744 };
 745
 746 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 747 {
 748         struct sh_eth_private *mdp = netdev_priv(ndev);
 749
 750         /* reset device */
 751         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 752         mdelay(1);
 753
 754         sh_eth_select_mii(ndev);
 755 }
 756
 757 /* R8A7740 */
 758 static struct sh_eth_cpu_data r8a7740_data = {
 759         .chip_reset     = sh_eth_chip_reset_r8a7740,
 760         .set_duplex     = sh_eth_set_duplex,
 761         .set_rate       = sh_eth_set_rate_gether,
 762
 763         .register_type  = SH_ETH_REG_GIGABIT,
 764
 765         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 766         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 767         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 768
 769         .tx_check       = EESR_TC1 | EESR_FTC,
 770         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 771                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 772                           EESR_TDE | EESR_ECI,
 773         .fdr_value      = 0x0000070f,
 774
 775         .apr            = 1,
 776         .mpr            = 1,
 777         .tpauser        = 1,
 778         .bculr          = 1,
 779         .hw_swap        = 1,
 780         .rpadir         = 1,
 781         .rpadir_value   = 2 << 16,
 782         .no_trimd       = 1,
 783         .no_ade         = 1,
 784         .tsu            = 1,
 785         .select_mii     = 1,
 786         .shift_rd0      = 1,
 787 };
 788
 789 /* R7S72100 */
 790 static struct sh_eth_cpu_data r7s72100_data = {
 791         .chip_reset     = sh_eth_chip_reset,
 792         .set_duplex     = sh_eth_set_duplex,
 793
 794         .register_type  = SH_ETH_REG_FAST_RZ,
 795
 796         .ecsr_value     = ECSR_ICD,
 797         .ecsipr_value   = ECSIPR_ICDIP,
 798         .eesipr_value   = 0xff7f009f,
 799
 800         .tx_check       = EESR_TC1 | EESR_FTC,
 801         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 802                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 803                           EESR_TDE | EESR_ECI,
 804         .fdr_value      = 0x0000070f,
 805
 806         .no_psr         = 1,
 807         .apr            = 1,
 808         .mpr            = 1,
 809         .tpauser        = 1,
 810         .hw_swap        = 1,
 811         .rpadir         = 1,
 812         .rpadir_value   = 2 << 16,
 813         .no_trimd       = 1,
 814         .no_ade         = 1,
 815         .hw_crc         = 1,
 816         .tsu            = 1,
 817         .shift_rd0      = 1,
 818 };
 819
 820 static struct sh_eth_cpu_data sh7619_data = {
 821         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 822
 823         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 824
 825         .apr            = 1,
 826         .mpr            = 1,
 827         .tpauser        = 1,
 828         .hw_swap        = 1,
 829 };
 830
 831 static struct sh_eth_cpu_data sh771x_data = {
 832         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 833
 834         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 835         .tsu            = 1,
 836 };
 837
 838 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 839 {
 840         if (!cd->ecsr_value)
 841                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 842
 843         if (!cd->ecsipr_value)
 844                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 845
 846         if (!cd->fcftr_value)
 847                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 848                                   DEFAULT_FIFO_F_D_RFD;
 849
 850         if (!cd->fdr_value)
 851                 cd->fdr_value = DEFAULT_FDR_INIT;
 852
 853         if (!cd->tx_check)
 854                 cd->tx_check = DEFAULT_TX_CHECK;
 855
 856         if (!cd->eesr_err_check)
 857                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 858 }
 859
 860 static int sh_eth_check_reset(struct net_device *ndev)
 861 {
 862         int ret = 0;
 863         int cnt = 100;
 864
 865         while (cnt > 0) {
 866                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 867                         break;
 868                 mdelay(1);
 869                 cnt--;
 870         }
 871         if (cnt <= 0) {
 872                 netdev_err(ndev, "Device reset failed\n");
 873                 ret = -ETIMEDOUT;
 874         }
 875         return ret;
 876 }
 877
 878 static int sh_eth_reset(struct net_device *ndev)
 879 {
 880         struct sh_eth_private *mdp = netdev_priv(ndev);
 881         int ret = 0;
 882
 883         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 884                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 885                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 886                              EDMR);
 887
 888                 ret = sh_eth_check_reset(ndev);
 889                 if (ret)
 890                         goto out;
 891
 892                 /* Table Init */
 893                 sh_eth_write(ndev, 0x0, TDLAR);
 894                 sh_eth_write(ndev, 0x0, TDFAR);
 895                 sh_eth_write(ndev, 0x0, TDFXR);
 896                 sh_eth_write(ndev, 0x0, TDFFR);
 897                 sh_eth_write(ndev, 0x0, RDLAR);
 898                 sh_eth_write(ndev, 0x0, RDFAR);
 899                 sh_eth_write(ndev, 0x0, RDFXR);
 900                 sh_eth_write(ndev, 0x0, RDFFR);
 901
 902                 /* Reset HW CRC register */
 903                 if (mdp->cd->hw_crc)
 904                         sh_eth_write(ndev, 0x0, CSMR);
 905
 906                 /* Select MII mode */
 907                 if (mdp->cd->select_mii)
 908                         sh_eth_select_mii(ndev);
 909         } else {
 910                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 911                              EDMR);
 912                 mdelay(3);
 913                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 914                              EDMR);
 915         }
 916
 917 out:
 918         return ret;
 919 }
 920
 921 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 922 static void sh_eth_set_receive_align(struct sk_buff *skb)
 923 {
 924         int reserve;
 925
 926         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 927         if (reserve)
 928                 skb_reserve(skb, reserve);
 929 }
 930 #else
 931 static void sh_eth_set_receive_align(struct sk_buff *skb)
 932 {
 933         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 934 }
 935 #endif
 936
 937
 938 /* CPU <-> EDMAC endian convert */
 939 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 940 {
 941         switch (mdp->edmac_endian) {
 942         case EDMAC_LITTLE_ENDIAN:
 943                 return cpu_to_le32(x);
 944         case EDMAC_BIG_ENDIAN:
 945                 return cpu_to_be32(x);
 946         }
 947         return x;
 948 }
 949
 950 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 951 {
 952         switch (mdp->edmac_endian) {
 953         case EDMAC_LITTLE_ENDIAN:
 954                 return le32_to_cpu(x);
 955         case EDMAC_BIG_ENDIAN:
 956                 return be32_to_cpu(x);
 957         }
 958         return x;
 959 }
 960
 961 /* Program the hardware MAC address from dev->dev_addr. */
 962 static void update_mac_address(struct net_device *ndev)
 963 {
 964         sh_eth_write(ndev,
 965                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 966                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 967         sh_eth_write(ndev,
 968                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 969 }
 970
 971 /* Get MAC address from SuperH MAC address register
 972  *
 973  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 974  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 975  * When you want use this device, you must set MAC address in bootloader.
 976  *
 977  */
 978 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 979 {
 980         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 981                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 982         } else {
 983                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 984                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 985                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 986                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 987                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 988                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 989         }
 990 }
 991
 992 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 993 {
 994         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 995                 return EDTRR_TRNS_GETHER;
 996         else
 997                 return EDTRR_TRNS_ETHER;
 998 }
 999
1000 struct bb_info {
1001         void (*set_gate)(void *addr);
1002         struct mdiobb_ctrl ctrl;
1003         void *addr;
1004         u32 mmd_msk;/* MMD */
1005         u32 mdo_msk;
1006         u32 mdi_msk;
1007         u32 mdc_msk;
1008 };
1009
1010 /* PHY bit set */
1011 static void bb_set(void *addr, u32 msk)
1012 {
1013         iowrite32(ioread32(addr) | msk, addr);
1014 }
1015
1016 /* PHY bit clear */
1017 static void bb_clr(void *addr, u32 msk)
1018 {
1019         iowrite32((ioread32(addr) & ~msk), addr);
1020 }
1021
1022 /* PHY bit read */
1023 static int bb_read(void *addr, u32 msk)
1024 {
1025         return (ioread32(addr) & msk) != 0;
1026 }
1027
1028 /* Data I/O pin control */
1029 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1030 {
1031         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032
1033         if (bitbang->set_gate)
1034                 bitbang->set_gate(bitbang->addr);
1035
1036         if (bit)
1037                 bb_set(bitbang->addr, bitbang->mmd_msk);
1038         else
1039                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1040 }
1041
1042 /* Set bit data*/
1043 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1044 {
1045         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1046
1047         if (bitbang->set_gate)
1048                 bitbang->set_gate(bitbang->addr);
1049
1050         if (bit)
1051                 bb_set(bitbang->addr, bitbang->mdo_msk);
1052         else
1053                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1054 }
1055
1056 /* Get bit data*/
1057 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1058 {
1059         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1060
1061         if (bitbang->set_gate)
1062                 bitbang->set_gate(bitbang->addr);
1063
1064         return bb_read(bitbang->addr, bitbang->mdi_msk);
1065 }
1066
1067 /* MDC pin control */
1068 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1069 {
1070         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1071
1072         if (bitbang->set_gate)
1073                 bitbang->set_gate(bitbang->addr);
1074
1075         if (bit)
1076                 bb_set(bitbang->addr, bitbang->mdc_msk);
1077         else
1078                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1079 }
1080
1081 /* mdio bus control struct */
1082 static struct mdiobb_ops bb_ops = {
1083         .owner = THIS_MODULE,
1084         .set_mdc = sh_mdc_ctrl,
1085         .set_mdio_dir = sh_mmd_ctrl,
1086         .set_mdio_data = sh_set_mdio,
1087         .get_mdio_data = sh_get_mdio,
1088 };
1089
1090 /* free skb and descriptor buffer */
1091 static void sh_eth_ring_free(struct net_device *ndev)
1092 {
1093         struct sh_eth_private *mdp = netdev_priv(ndev);
1094         int i;
1095
1096         /* Free Rx skb ringbuffer */
1097         if (mdp->rx_skbuff) {
1098                 for (i = 0; i < mdp->num_rx_ring; i++) {
1099                         if (mdp->rx_skbuff[i])
1100                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1101                 }
1102         }
1103         kfree(mdp->rx_skbuff);
1104         mdp->rx_skbuff = NULL;
1105
1106         /* Free Tx skb ringbuffer */
1107         if (mdp->tx_skbuff) {
1108                 for (i = 0; i < mdp->num_tx_ring; i++) {
1109                         if (mdp->tx_skbuff[i])
1110                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1111                 }
1112         }
1113         kfree(mdp->tx_skbuff);
1114         mdp->tx_skbuff = NULL;
1115 }
1116
1117 /* format skb and descriptor buffer */
1118 static void sh_eth_ring_format(struct net_device *ndev)
1119 {
1120         struct sh_eth_private *mdp = netdev_priv(ndev);
1121         int i;
1122         struct sk_buff *skb;
1123         struct sh_eth_rxdesc *rxdesc = NULL;
1124         struct sh_eth_txdesc *txdesc = NULL;
1125         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1126         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1127
1128         mdp->cur_rx = 0;
1129         mdp->cur_tx = 0;
1130         mdp->dirty_rx = 0;
1131         mdp->dirty_tx = 0;
1132
1133         memset(mdp->rx_ring, 0, rx_ringsize);
1134
1135         /* build Rx ring buffer */
1136         for (i = 0; i < mdp->num_rx_ring; i++) {
1137                 /* skb */
1138                 mdp->rx_skbuff[i] = NULL;
1139                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1140                 mdp->rx_skbuff[i] = skb;
1141                 if (skb == NULL)
1142                         break;
1143                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1144                                DMA_FROM_DEVICE);
1145                 sh_eth_set_receive_align(skb);
1146
1147                 /* RX descriptor */
1148                 rxdesc = &mdp->rx_ring[i];
1149                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1150                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1151
1152                 /* The size of the buffer is 16 byte boundary. */
1153                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1154                 /* Rx descriptor address set */
1155                 if (i == 0) {
1156                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1157                         if (sh_eth_is_gether(mdp) ||
1158                             sh_eth_is_rz_fast_ether(mdp))
1159                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1160                 }
1161         }
1162
1163         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1164
1165         /* Mark the last entry as wrapping the ring. */
1166         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1167
1168         memset(mdp->tx_ring, 0, tx_ringsize);
1169
1170         /* build Tx ring buffer */
1171         for (i = 0; i < mdp->num_tx_ring; i++) {
1172                 mdp->tx_skbuff[i] = NULL;
1173                 txdesc = &mdp->tx_ring[i];
1174                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1175                 txdesc->buffer_length = 0;
1176                 if (i == 0) {
1177                         /* Tx descriptor address set */
1178                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1179                         if (sh_eth_is_gether(mdp) ||
1180                             sh_eth_is_rz_fast_ether(mdp))
1181                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1182                 }
1183         }
1184
1185         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1186 }
1187
1188 /* Get skb and descriptor buffer */
1189 static int sh_eth_ring_init(struct net_device *ndev)
1190 {
1191         struct sh_eth_private *mdp = netdev_priv(ndev);
1192         int rx_ringsize, tx_ringsize, ret = 0;
1193
1194         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1195          * card needs room to do 8 byte alignment, +2 so we can reserve
1196          * the first 2 bytes, and +16 gets room for the status word from the
1197          * card.
1198          */
1199         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1200                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1201         if (mdp->cd->rpadir)
1202                 mdp->rx_buf_sz += NET_IP_ALIGN;
1203
1204         /* Allocate RX and TX skb rings */
1205         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1206                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1207         if (!mdp->rx_skbuff) {
1208                 ret = -ENOMEM;
1209                 return ret;
1210         }
1211
1212         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1213                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1214         if (!mdp->tx_skbuff) {
1215                 ret = -ENOMEM;
1216                 goto skb_ring_free;
1217         }
1218
1219         /* Allocate all Rx descriptors. */
1220         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1221         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1222                                           GFP_KERNEL);
1223         if (!mdp->rx_ring) {
1224                 ret = -ENOMEM;
1225                 goto desc_ring_free;
1226         }
1227
1228         mdp->dirty_rx = 0;
1229
1230         /* Allocate all Tx descriptors. */
1231         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1232         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1233                                           GFP_KERNEL);
1234         if (!mdp->tx_ring) {
1235                 ret = -ENOMEM;
1236                 goto desc_ring_free;
1237         }
1238         return ret;
1239
1240 desc_ring_free:
1241         /* free DMA buffer */
1242         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1243
1244 skb_ring_free:
1245         /* Free Rx and Tx skb ring buffer */
1246         sh_eth_ring_free(ndev);
1247         mdp->tx_ring = NULL;
1248         mdp->rx_ring = NULL;
1249
1250         return ret;
1251 }
1252
1253 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1254 {
1255         int ringsize;
1256
1257         if (mdp->rx_ring) {
1258                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1259                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1260                                   mdp->rx_desc_dma);
1261                 mdp->rx_ring = NULL;
1262         }
1263
1264         if (mdp->tx_ring) {
1265                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1266                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1267                                   mdp->tx_desc_dma);
1268                 mdp->tx_ring = NULL;
1269         }
1270 }
1271
1272 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1273 {
1274         int ret = 0;
1275         struct sh_eth_private *mdp = netdev_priv(ndev);
1276         u32 val;
1277
1278         /* Soft Reset */
1279         ret = sh_eth_reset(ndev);
1280         if (ret)
1281                 goto out;
1282
1283         if (mdp->cd->rmiimode)
1284                 sh_eth_write(ndev, 0x1, RMIIMODE);
1285
1286         /* Descriptor format */
1287         sh_eth_ring_format(ndev);
1288         if (mdp->cd->rpadir)
1289                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1290
1291         /* all sh_eth int mask */
1292         sh_eth_write(ndev, 0, EESIPR);
1293
1294 #if defined(__LITTLE_ENDIAN)
1295         if (mdp->cd->hw_swap)
1296                 sh_eth_write(ndev, EDMR_EL, EDMR);
1297         else
1298 #endif
1299                 sh_eth_write(ndev, 0, EDMR);
1300
1301         /* FIFO size set */
1302         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1303         sh_eth_write(ndev, 0, TFTR);
1304
1305         /* Frame recv control (enable multiple-packets per rx irq) */
1306         sh_eth_write(ndev, RMCR_RNC, RMCR);
1307
1308         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1309
1310         if (mdp->cd->bculr)
1311                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1312
1313         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1314
1315         if (!mdp->cd->no_trimd)
1316                 sh_eth_write(ndev, 0, TRIMD);
1317
1318         /* Recv frame limit set register */
1319         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1320                      RFLR);
1321
1322         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1323         if (start)
1324                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1325
1326         /* PAUSE Prohibition */
1327         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1328                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1329
1330         sh_eth_write(ndev, val, ECMR);
1331
1332         if (mdp->cd->set_rate)
1333                 mdp->cd->set_rate(ndev);
1334
1335         /* E-MAC Status Register clear */
1336         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1337
1338         /* E-MAC Interrupt Enable register */
1339         if (start)
1340                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1341
1342         /* Set MAC address */
1343         update_mac_address(ndev);
1344
1345         /* mask reset */
1346         if (mdp->cd->apr)
1347                 sh_eth_write(ndev, APR_AP, APR);
1348         if (mdp->cd->mpr)
1349                 sh_eth_write(ndev, MPR_MP, MPR);
1350         if (mdp->cd->tpauser)
1351                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1352
1353         if (start) {
1354                 /* Setting the Rx mode will start the Rx process. */
1355                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1356
1357                 netif_start_queue(ndev);
1358         }
1359
1360 out:
1361         return ret;
1362 }
1363
1364 /* free Tx skb function */
1365 static int sh_eth_txfree(struct net_device *ndev)
1366 {
1367         struct sh_eth_private *mdp = netdev_priv(ndev);
1368         struct sh_eth_txdesc *txdesc;
1369         int free_num = 0;
1370         int entry = 0;
1371
1372         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1373                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1374                 txdesc = &mdp->tx_ring[entry];
1375                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1376                         break;
1377                 /* Free the original skb. */
1378                 if (mdp->tx_skbuff[entry]) {
1379                         dma_unmap_single(&ndev->dev, txdesc->addr,
1380                                          txdesc->buffer_length, DMA_TO_DEVICE);
1381                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1382                         mdp->tx_skbuff[entry] = NULL;
1383                         free_num++;
1384                 }
1385                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1386                 if (entry >= mdp->num_tx_ring - 1)
1387                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1388
1389                 ndev->stats.tx_packets++;
1390                 ndev->stats.tx_bytes += txdesc->buffer_length;
1391         }
1392         return free_num;
1393 }
1394
1395 /* Packet receive function */
1396 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1397 {
1398         struct sh_eth_private *mdp = netdev_priv(ndev);
1399         struct sh_eth_rxdesc *rxdesc;
1400
1401         int entry = mdp->cur_rx % mdp->num_rx_ring;
1402         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1403         struct sk_buff *skb;
1404         int exceeded = 0;
1405         u16 pkt_len = 0;
1406         u32 desc_status;
1407
1408         rxdesc = &mdp->rx_ring[entry];
1409         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1410                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1411                 pkt_len = rxdesc->frame_length;
1412
1413                 if (--boguscnt < 0)
1414                         break;
1415
1416                 if (*quota <= 0) {
1417                         exceeded = 1;
1418                         break;
1419                 }
1420                 (*quota)--;
1421
1422                 if (!(desc_status & RDFEND))
1423                         ndev->stats.rx_length_errors++;
1424
1425                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1426                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1427                  * bit 0. However, in case of the R8A7740, R8A779x, and
1428                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1429                  * driver needs right shifting by 16.
1430                  */
1431                 if (mdp->cd->shift_rd0)
1432                         desc_status >>= 16;
1433
1434                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1435                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1436                         ndev->stats.rx_errors++;
1437                         if (desc_status & RD_RFS1)
1438                                 ndev->stats.rx_crc_errors++;
1439                         if (desc_status & RD_RFS2)
1440                                 ndev->stats.rx_frame_errors++;
1441                         if (desc_status & RD_RFS3)
1442                                 ndev->stats.rx_length_errors++;
1443                         if (desc_status & RD_RFS4)
1444                                 ndev->stats.rx_length_errors++;
1445                         if (desc_status & RD_RFS6)
1446                                 ndev->stats.rx_missed_errors++;
1447                         if (desc_status & RD_RFS10)
1448                                 ndev->stats.rx_over_errors++;
1449                 } else {
1450                         if (!mdp->cd->hw_swap)
1451                                 sh_eth_soft_swap(
1452                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1453                                         pkt_len + 2);
1454                         skb = mdp->rx_skbuff[entry];
1455                         mdp->rx_skbuff[entry] = NULL;
1456                         if (mdp->cd->rpadir)
1457                                 skb_reserve(skb, NET_IP_ALIGN);
1458                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1459                                                 mdp->rx_buf_sz,
1460                                                 DMA_FROM_DEVICE);
1461                         skb_put(skb, pkt_len);
1462                         skb->protocol = eth_type_trans(skb, ndev);
1463                         netif_receive_skb(skb);
1464                         ndev->stats.rx_packets++;
1465                         ndev->stats.rx_bytes += pkt_len;
1466                 }
1467                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1468                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1469                 rxdesc = &mdp->rx_ring[entry];
1470         }
1471
1472         /* Refill the Rx ring buffers. */
1473         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1474                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1475                 rxdesc = &mdp->rx_ring[entry];
1476                 /* The size of the buffer is 16 byte boundary. */
1477                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1478
1479                 if (mdp->rx_skbuff[entry] == NULL) {
1480                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1481                         mdp->rx_skbuff[entry] = skb;
1482                         if (skb == NULL)
1483                                 break;  /* Better luck next round. */
1484                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1485                                        DMA_FROM_DEVICE);
1486                         sh_eth_set_receive_align(skb);
1487
1488                         skb_checksum_none_assert(skb);
1489                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1490                 }
1491                 if (entry >= mdp->num_rx_ring - 1)
1492                         rxdesc->status |=
1493                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1494                 else
1495                         rxdesc->status |=
1496                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1497         }
1498
1499         /* Restart Rx engine if stopped. */
1500         /* If we don't need to check status, don't. -KDU */
1501         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1502                 /* fix the values for the next receiving if RDE is set */
1503                 if (intr_status & EESR_RDE) {
1504                         u32 count = (sh_eth_read(ndev, RDFAR) -
1505                                      sh_eth_read(ndev, RDLAR)) >> 4;
1506
1507                         mdp->cur_rx = count;
1508                         mdp->dirty_rx = count;
1509                 }
1510                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1511         }
1512
1513         return exceeded;
1514 }
1515
1516 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1517 {
1518         /* disable tx and rx */
1519         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1520                 ~(ECMR_RE | ECMR_TE), ECMR);
1521 }
1522
1523 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1524 {
1525         /* enable tx and rx */
1526         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1527                 (ECMR_RE | ECMR_TE), ECMR);
1528 }
1529
1530 /* error control function */
1531 static void sh_eth_error(struct net_device *ndev, int intr_status)
1532 {
1533         struct sh_eth_private *mdp = netdev_priv(ndev);
1534         u32 felic_stat;
1535         u32 link_stat;
1536         u32 mask;
1537
1538         if (intr_status & EESR_ECI) {
1539                 felic_stat = sh_eth_read(ndev, ECSR);
1540                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1541                 if (felic_stat & ECSR_ICD)
1542                         ndev->stats.tx_carrier_errors++;
1543                 if (felic_stat & ECSR_LCHNG) {
1544                         /* Link Changed */
1545                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1546                                 goto ignore_link;
1547                         } else {
1548                                 link_stat = (sh_eth_read(ndev, PSR));
1549                                 if (mdp->ether_link_active_low)
1550                                         link_stat = ~link_stat;
1551                         }
1552                         if (!(link_stat & PHY_ST_LINK)) {
1553                                 sh_eth_rcv_snd_disable(ndev);
1554                         } else {
1555                                 /* Link Up */
1556                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1557                                                    ~DMAC_M_ECI, EESIPR);
1558                                 /* clear int */
1559                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1560                                              ECSR);
1561                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1562                                                    DMAC_M_ECI, EESIPR);
1563                                 /* enable tx and rx */
1564                                 sh_eth_rcv_snd_enable(ndev);
1565                         }
1566                 }
1567         }
1568
1569 ignore_link:
1570         if (intr_status & EESR_TWB) {
1571                 /* Unused write back interrupt */
1572                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1573                         ndev->stats.tx_aborted_errors++;
1574                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1575                 }
1576         }
1577
1578         if (intr_status & EESR_RABT) {
1579                 /* Receive Abort int */
1580                 if (intr_status & EESR_RFRMER) {
1581                         /* Receive Frame Overflow int */
1582                         ndev->stats.rx_frame_errors++;
1583                         netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1584                 }
1585         }
1586
1587         if (intr_status & EESR_TDE) {
1588                 /* Transmit Descriptor Empty int */
1589                 ndev->stats.tx_fifo_errors++;
1590                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1591         }
1592
1593         if (intr_status & EESR_TFE) {
1594                 /* FIFO under flow */
1595                 ndev->stats.tx_fifo_errors++;
1596                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1597         }
1598
1599         if (intr_status & EESR_RDE) {
1600                 /* Receive Descriptor Empty int */
1601                 ndev->stats.rx_over_errors++;
1602                 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1603         }
1604
1605         if (intr_status & EESR_RFE) {
1606                 /* Receive FIFO Overflow int */
1607                 ndev->stats.rx_fifo_errors++;
1608                 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1609         }
1610
1611         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1612                 /* Address Error */
1613                 ndev->stats.tx_fifo_errors++;
1614                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1615         }
1616
1617         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1618         if (mdp->cd->no_ade)
1619                 mask &= ~EESR_ADE;
1620         if (intr_status & mask) {
1621                 /* Tx error */
1622                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1623
1624                 /* dmesg */
1625                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1626                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1627                            (u32)ndev->state, edtrr);
1628                 /* dirty buffer free */
1629                 sh_eth_txfree(ndev);
1630
1631                 /* SH7712 BUG */
1632                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1633                         /* tx dma start */
1634                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1635                 }
1636                 /* wakeup */
1637                 netif_wake_queue(ndev);
1638         }
1639 }
1640
1641 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1642 {
1643         struct net_device *ndev = netdev;
1644         struct sh_eth_private *mdp = netdev_priv(ndev);
1645         struct sh_eth_cpu_data *cd = mdp->cd;
1646         irqreturn_t ret = IRQ_NONE;
1647         unsigned long intr_status, intr_enable;
1648
1649         spin_lock(&mdp->lock);
1650
1651         /* Get interrupt status */
1652         intr_status = sh_eth_read(ndev, EESR);
1653         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1654          * enabled since it's the one that  comes thru regardless of the mask,
1655          * and we need to fully handle it in sh_eth_error() in order to quench
1656          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1657          */
1658         intr_enable = sh_eth_read(ndev, EESIPR);
1659         intr_status &= intr_enable | DMAC_M_ECI;
1660         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1661                 ret = IRQ_HANDLED;
1662         else
1663                 goto other_irq;
1664
1665         if (intr_status & EESR_RX_CHECK) {
1666                 if (napi_schedule_prep(&mdp->napi)) {
1667                         /* Mask Rx interrupts */
1668                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1669                                      EESIPR);
1670                         __napi_schedule(&mdp->napi);
1671                 } else {
1672                         netdev_warn(ndev,
1673                                     "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1674                                     intr_status, intr_enable);
1675                 }
1676         }
1677
1678         /* Tx Check */
1679         if (intr_status & cd->tx_check) {
1680                 /* Clear Tx interrupts */
1681                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1682
1683                 sh_eth_txfree(ndev);
1684                 netif_wake_queue(ndev);
1685         }
1686
1687         if (intr_status & cd->eesr_err_check) {
1688                 /* Clear error interrupts */
1689                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1690
1691                 sh_eth_error(ndev, intr_status);
1692         }
1693
1694 other_irq:
1695         spin_unlock(&mdp->lock);
1696
1697         return ret;
1698 }
1699
1700 static int sh_eth_poll(struct napi_struct *napi, int budget)
1701 {
1702         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1703                                                   napi);
1704         struct net_device *ndev = napi->dev;
1705         int quota = budget;
1706         unsigned long intr_status;
1707
1708         for (;;) {
1709                 intr_status = sh_eth_read(ndev, EESR);
1710                 if (!(intr_status & EESR_RX_CHECK))
1711                         break;
1712                 /* Clear Rx interrupts */
1713                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1714
1715                 if (sh_eth_rx(ndev, intr_status, &quota))
1716                         goto out;
1717         }
1718
1719         napi_complete(napi);
1720
1721         /* Reenable Rx interrupts */
1722         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1723 out:
1724         return budget - quota;
1725 }
1726
1727 /* PHY state control function */
1728 static void sh_eth_adjust_link(struct net_device *ndev)
1729 {
1730         struct sh_eth_private *mdp = netdev_priv(ndev);
1731         struct phy_device *phydev = mdp->phydev;
1732         int new_state = 0;
1733
1734         if (phydev->link) {
1735                 if (phydev->duplex != mdp->duplex) {
1736                         new_state = 1;
1737                         mdp->duplex = phydev->duplex;
1738                         if (mdp->cd->set_duplex)
1739                                 mdp->cd->set_duplex(ndev);
1740                 }
1741
1742                 if (phydev->speed != mdp->speed) {
1743                         new_state = 1;
1744                         mdp->speed = phydev->speed;
1745                         if (mdp->cd->set_rate)
1746                                 mdp->cd->set_rate(ndev);
1747                 }
1748                 if (!mdp->link) {
1749                         sh_eth_write(ndev,
1750                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1751                                      ECMR);
1752                         new_state = 1;
1753                         mdp->link = phydev->link;
1754                         if (mdp->cd->no_psr || mdp->no_ether_link)
1755                                 sh_eth_rcv_snd_enable(ndev);
1756                 }
1757         } else if (mdp->link) {
1758                 new_state = 1;
1759                 mdp->link = 0;
1760                 mdp->speed = 0;
1761                 mdp->duplex = -1;
1762                 if (mdp->cd->no_psr || mdp->no_ether_link)
1763                         sh_eth_rcv_snd_disable(ndev);
1764         }
1765
1766         if (new_state && netif_msg_link(mdp))
1767                 phy_print_status(phydev);
1768 }
1769
1770 /* PHY init function */
1771 static int sh_eth_phy_init(struct net_device *ndev)
1772 {
1773         struct device_node *np = ndev->dev.parent->of_node;
1774         struct sh_eth_private *mdp = netdev_priv(ndev);
1775         struct phy_device *phydev = NULL;
1776
1777         mdp->link = 0;
1778         mdp->speed = 0;
1779         mdp->duplex = -1;
1780
1781         /* Try connect to PHY */
1782         if (np) {
1783                 struct device_node *pn;
1784
1785                 pn = of_parse_phandle(np, "phy-handle", 0);
1786                 phydev = of_phy_connect(ndev, pn,
1787                                         sh_eth_adjust_link, 0,
1788                                         mdp->phy_interface);
1789
1790                 if (!phydev)
1791                         phydev = ERR_PTR(-ENOENT);
1792         } else {
1793                 char phy_id[MII_BUS_ID_SIZE + 3];
1794
1795                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1796                          mdp->mii_bus->id, mdp->phy_id);
1797
1798                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1799                                      mdp->phy_interface);
1800         }
1801
1802         if (IS_ERR(phydev)) {
1803                 netdev_err(ndev, "failed to connect PHY\n");
1804                 return PTR_ERR(phydev);
1805         }
1806
1807         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1808                     phydev->addr, phydev->irq, phydev->drv->name);
1809
1810         mdp->phydev = phydev;
1811
1812         return 0;
1813 }
1814
1815 /* PHY control start function */
1816 static int sh_eth_phy_start(struct net_device *ndev)
1817 {
1818         struct sh_eth_private *mdp = netdev_priv(ndev);
1819         int ret;
1820
1821         ret = sh_eth_phy_init(ndev);
1822         if (ret)
1823                 return ret;
1824
1825         phy_start(mdp->phydev);
1826
1827         return 0;
1828 }
1829
1830 static int sh_eth_get_settings(struct net_device *ndev,
1831                                struct ethtool_cmd *ecmd)
1832 {
1833         struct sh_eth_private *mdp = netdev_priv(ndev);
1834         unsigned long flags;
1835         int ret;
1836
1837         spin_lock_irqsave(&mdp->lock, flags);
1838         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1839         spin_unlock_irqrestore(&mdp->lock, flags);
1840
1841         return ret;
1842 }
1843
1844 static int sh_eth_set_settings(struct net_device *ndev,
1845                                struct ethtool_cmd *ecmd)
1846 {
1847         struct sh_eth_private *mdp = netdev_priv(ndev);
1848         unsigned long flags;
1849         int ret;
1850
1851         spin_lock_irqsave(&mdp->lock, flags);
1852
1853         /* disable tx and rx */
1854         sh_eth_rcv_snd_disable(ndev);
1855
1856         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1857         if (ret)
1858                 goto error_exit;
1859
1860         if (ecmd->duplex == DUPLEX_FULL)
1861                 mdp->duplex = 1;
1862         else
1863                 mdp->duplex = 0;
1864
1865         if (mdp->cd->set_duplex)
1866                 mdp->cd->set_duplex(ndev);
1867
1868 error_exit:
1869         mdelay(1);
1870
1871         /* enable tx and rx */
1872         sh_eth_rcv_snd_enable(ndev);
1873
1874         spin_unlock_irqrestore(&mdp->lock, flags);
1875
1876         return ret;
1877 }
1878
1879 static int sh_eth_nway_reset(struct net_device *ndev)
1880 {
1881         struct sh_eth_private *mdp = netdev_priv(ndev);
1882         unsigned long flags;
1883         int ret;
1884
1885         spin_lock_irqsave(&mdp->lock, flags);
1886         ret = phy_start_aneg(mdp->phydev);
1887         spin_unlock_irqrestore(&mdp->lock, flags);
1888
1889         return ret;
1890 }
1891
1892 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1893 {
1894         struct sh_eth_private *mdp = netdev_priv(ndev);
1895         return mdp->msg_enable;
1896 }
1897
1898 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1899 {
1900         struct sh_eth_private *mdp = netdev_priv(ndev);
1901         mdp->msg_enable = value;
1902 }
1903
1904 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1905         "rx_current", "tx_current",
1906         "rx_dirty", "tx_dirty",
1907 };
1908 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1909
1910 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1911 {
1912         switch (sset) {
1913         case ETH_SS_STATS:
1914                 return SH_ETH_STATS_LEN;
1915         default:
1916                 return -EOPNOTSUPP;
1917         }
1918 }
1919
1920 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1921                                      struct ethtool_stats *stats, u64 *data)
1922 {
1923         struct sh_eth_private *mdp = netdev_priv(ndev);
1924         int i = 0;
1925
1926         /* device-specific stats */
1927         data[i++] = mdp->cur_rx;
1928         data[i++] = mdp->cur_tx;
1929         data[i++] = mdp->dirty_rx;
1930         data[i++] = mdp->dirty_tx;
1931 }
1932
1933 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1934 {
1935         switch (stringset) {
1936         case ETH_SS_STATS:
1937                 memcpy(data, *sh_eth_gstrings_stats,
1938                        sizeof(sh_eth_gstrings_stats));
1939                 break;
1940         }
1941 }
1942
1943 static void sh_eth_get_ringparam(struct net_device *ndev,
1944                                  struct ethtool_ringparam *ring)
1945 {
1946         struct sh_eth_private *mdp = netdev_priv(ndev);
1947
1948         ring->rx_max_pending = RX_RING_MAX;
1949         ring->tx_max_pending = TX_RING_MAX;
1950         ring->rx_pending = mdp->num_rx_ring;
1951         ring->tx_pending = mdp->num_tx_ring;
1952 }
1953
1954 static int sh_eth_set_ringparam(struct net_device *ndev,
1955                                 struct ethtool_ringparam *ring)
1956 {
1957         struct sh_eth_private *mdp = netdev_priv(ndev);
1958         int ret;
1959
1960         if (ring->tx_pending > TX_RING_MAX ||
1961             ring->rx_pending > RX_RING_MAX ||
1962             ring->tx_pending < TX_RING_MIN ||
1963             ring->rx_pending < RX_RING_MIN)
1964                 return -EINVAL;
1965         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1966                 return -EINVAL;
1967
1968         if (netif_running(ndev)) {
1969                 netif_tx_disable(ndev);
1970                 /* Disable interrupts by clearing the interrupt mask. */
1971                 sh_eth_write(ndev, 0x0000, EESIPR);
1972                 /* Stop the chip's Tx and Rx processes. */
1973                 sh_eth_write(ndev, 0, EDTRR);
1974                 sh_eth_write(ndev, 0, EDRRR);
1975                 synchronize_irq(ndev->irq);
1976         }
1977
1978         /* Free all the skbuffs in the Rx queue. */
1979         sh_eth_ring_free(ndev);
1980         /* Free DMA buffer */
1981         sh_eth_free_dma_buffer(mdp);
1982
1983         /* Set new parameters */
1984         mdp->num_rx_ring = ring->rx_pending;
1985         mdp->num_tx_ring = ring->tx_pending;
1986
1987         ret = sh_eth_ring_init(ndev);
1988         if (ret < 0) {
1989                 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1990                 return ret;
1991         }
1992         ret = sh_eth_dev_init(ndev, false);
1993         if (ret < 0) {
1994                 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
1995                 return ret;
1996         }
1997
1998         if (netif_running(ndev)) {
1999                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2000                 /* Setting the Rx mode will start the Rx process. */
2001                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2002                 netif_wake_queue(ndev);
2003         }
2004
2005         return 0;
2006 }
2007
2008 static const struct ethtool_ops sh_eth_ethtool_ops = {
2009         .get_settings   = sh_eth_get_settings,
2010         .set_settings   = sh_eth_set_settings,
2011         .nway_reset     = sh_eth_nway_reset,
2012         .get_msglevel   = sh_eth_get_msglevel,
2013         .set_msglevel   = sh_eth_set_msglevel,
2014         .get_link       = ethtool_op_get_link,
2015         .get_strings    = sh_eth_get_strings,
2016         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2017         .get_sset_count     = sh_eth_get_sset_count,
2018         .get_ringparam  = sh_eth_get_ringparam,
2019         .set_ringparam  = sh_eth_set_ringparam,
2020 };
2021
2022 /* network device open function */
2023 static int sh_eth_open(struct net_device *ndev)
2024 {
2025         int ret = 0;
2026         struct sh_eth_private *mdp = netdev_priv(ndev);
2027
2028         pm_runtime_get_sync(&mdp->pdev->dev);
2029
2030         napi_enable(&mdp->napi);
2031
2032         ret = request_irq(ndev->irq, sh_eth_interrupt,
2033                           mdp->cd->irq_flags, ndev->name, ndev);
2034         if (ret) {
2035                 netdev_err(ndev, "Can not assign IRQ number\n");
2036                 goto out_napi_off;
2037         }
2038
2039         /* Descriptor set */
2040         ret = sh_eth_ring_init(ndev);
2041         if (ret)
2042                 goto out_free_irq;
2043
2044         /* device init */
2045         ret = sh_eth_dev_init(ndev, true);
2046         if (ret)
2047                 goto out_free_irq;
2048
2049         /* PHY control start*/
2050         ret = sh_eth_phy_start(ndev);
2051         if (ret)
2052                 goto out_free_irq;
2053
2054         return ret;
2055
2056 out_free_irq:
2057         free_irq(ndev->irq, ndev);
2058 out_napi_off:
2059         napi_disable(&mdp->napi);
2060         pm_runtime_put_sync(&mdp->pdev->dev);
2061         return ret;
2062 }
2063
2064 /* Timeout function */
2065 static void sh_eth_tx_timeout(struct net_device *ndev)
2066 {
2067         struct sh_eth_private *mdp = netdev_priv(ndev);
2068         struct sh_eth_rxdesc *rxdesc;
2069         int i;
2070
2071         netif_stop_queue(ndev);
2072
2073         netif_err(mdp, timer, ndev,
2074                   "transmit timed out, status %8.8x, resetting...\n",
2075                   (int)sh_eth_read(ndev, EESR));
2076
2077         /* tx_errors count up */
2078         ndev->stats.tx_errors++;
2079
2080         /* Free all the skbuffs in the Rx queue. */
2081         for (i = 0; i < mdp->num_rx_ring; i++) {
2082                 rxdesc = &mdp->rx_ring[i];
2083                 rxdesc->status = 0;
2084                 rxdesc->addr = 0xBADF00D0;
2085                 if (mdp->rx_skbuff[i])
2086                         dev_kfree_skb(mdp->rx_skbuff[i]);
2087                 mdp->rx_skbuff[i] = NULL;
2088         }
2089         for (i = 0; i < mdp->num_tx_ring; i++) {
2090                 if (mdp->tx_skbuff[i])
2091                         dev_kfree_skb(mdp->tx_skbuff[i]);
2092                 mdp->tx_skbuff[i] = NULL;
2093         }
2094
2095         /* device init */
2096         sh_eth_dev_init(ndev, true);
2097 }
2098
2099 /* Packet transmit function */
2100 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2101 {
2102         struct sh_eth_private *mdp = netdev_priv(ndev);
2103         struct sh_eth_txdesc *txdesc;
2104         u32 entry;
2105         unsigned long flags;
2106
2107         spin_lock_irqsave(&mdp->lock, flags);
2108         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2109                 if (!sh_eth_txfree(ndev)) {
2110                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2111                         netif_stop_queue(ndev);
2112                         spin_unlock_irqrestore(&mdp->lock, flags);
2113                         return NETDEV_TX_BUSY;
2114                 }
2115         }
2116         spin_unlock_irqrestore(&mdp->lock, flags);
2117
2118         entry = mdp->cur_tx % mdp->num_tx_ring;
2119         mdp->tx_skbuff[entry] = skb;
2120         txdesc = &mdp->tx_ring[entry];
2121         /* soft swap. */
2122         if (!mdp->cd->hw_swap)
2123                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2124                                  skb->len + 2);
2125         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2126                                       DMA_TO_DEVICE);
2127         if (skb->len < ETH_ZLEN)
2128                 txdesc->buffer_length = ETH_ZLEN;
2129         else
2130                 txdesc->buffer_length = skb->len;
2131
2132         if (entry >= mdp->num_tx_ring - 1)
2133                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2134         else
2135                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2136
2137         mdp->cur_tx++;
2138
2139         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2140                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2141
2142         return NETDEV_TX_OK;
2143 }
2144
2145 /* device close function */
2146 static int sh_eth_close(struct net_device *ndev)
2147 {
2148         struct sh_eth_private *mdp = netdev_priv(ndev);
2149
2150         netif_stop_queue(ndev);
2151
2152         /* Disable interrupts by clearing the interrupt mask. */
2153         sh_eth_write(ndev, 0x0000, EESIPR);
2154
2155         /* Stop the chip's Tx and Rx processes. */
2156         sh_eth_write(ndev, 0, EDTRR);
2157         sh_eth_write(ndev, 0, EDRRR);
2158
2159         /* PHY Disconnect */
2160         if (mdp->phydev) {
2161                 phy_stop(mdp->phydev);
2162                 phy_disconnect(mdp->phydev);
2163         }
2164
2165         free_irq(ndev->irq, ndev);
2166
2167         napi_disable(&mdp->napi);
2168
2169         /* Free all the skbuffs in the Rx queue. */
2170         sh_eth_ring_free(ndev);
2171
2172         /* free DMA buffer */
2173         sh_eth_free_dma_buffer(mdp);
2174
2175         pm_runtime_put_sync(&mdp->pdev->dev);
2176
2177         return 0;
2178 }
2179
2180 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2181 {
2182         struct sh_eth_private *mdp = netdev_priv(ndev);
2183
2184         if (sh_eth_is_rz_fast_ether(mdp))
2185                 return &ndev->stats;
2186
2187         pm_runtime_get_sync(&mdp->pdev->dev);
2188
2189         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2190         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2191         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2192         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2193         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2194         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2195         if (sh_eth_is_gether(mdp)) {
2196                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2197                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2198                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2199                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2200         } else {
2201                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2202                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2203         }
2204         pm_runtime_put_sync(&mdp->pdev->dev);
2205
2206         return &ndev->stats;
2207 }
2208
2209 /* ioctl to device function */
2210 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2211 {
2212         struct sh_eth_private *mdp = netdev_priv(ndev);
2213         struct phy_device *phydev = mdp->phydev;
2214
2215         if (!netif_running(ndev))
2216                 return -EINVAL;
2217
2218         if (!phydev)
2219                 return -ENODEV;
2220
2221         return phy_mii_ioctl(phydev, rq, cmd);
2222 }
2223
2224 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2225 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2226                                             int entry)
2227 {
2228         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2229 }
2230
2231 static u32 sh_eth_tsu_get_post_mask(int entry)
2232 {
2233         return 0x0f << (28 - ((entry % 8) * 4));
2234 }
2235
2236 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2237 {
2238         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2239 }
2240
2241 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2242                                              int entry)
2243 {
2244         struct sh_eth_private *mdp = netdev_priv(ndev);
2245         u32 tmp;
2246         void *reg_offset;
2247
2248         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2249         tmp = ioread32(reg_offset);
2250         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2251 }
2252
2253 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2254                                               int entry)
2255 {
2256         struct sh_eth_private *mdp = netdev_priv(ndev);
2257         u32 post_mask, ref_mask, tmp;
2258         void *reg_offset;
2259
2260         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2261         post_mask = sh_eth_tsu_get_post_mask(entry);
2262         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2263
2264         tmp = ioread32(reg_offset);
2265         iowrite32(tmp & ~post_mask, reg_offset);
2266
2267         /* If other port enables, the function returns "true" */
2268         return tmp & ref_mask;
2269 }
2270
2271 static int sh_eth_tsu_busy(struct net_device *ndev)
2272 {
2273         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2274         struct sh_eth_private *mdp = netdev_priv(ndev);
2275
2276         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2277                 udelay(10);
2278                 timeout--;
2279                 if (timeout <= 0) {
2280                         netdev_err(ndev, "%s: timeout\n", __func__);
2281                         return -ETIMEDOUT;
2282                 }
2283         }
2284
2285         return 0;
2286 }
2287
2288 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2289                                   const u8 *addr)
2290 {
2291         u32 val;
2292
2293         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2294         iowrite32(val, reg);
2295         if (sh_eth_tsu_busy(ndev) < 0)
2296                 return -EBUSY;
2297
2298         val = addr[4] << 8 | addr[5];
2299         iowrite32(val, reg + 4);
2300         if (sh_eth_tsu_busy(ndev) < 0)
2301                 return -EBUSY;
2302
2303         return 0;
2304 }
2305
2306 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2307 {
2308         u32 val;
2309
2310         val = ioread32(reg);
2311         addr[0] = (val >> 24) & 0xff;
2312         addr[1] = (val >> 16) & 0xff;
2313         addr[2] = (val >> 8) & 0xff;
2314         addr[3] = val & 0xff;
2315         val = ioread32(reg + 4);
2316         addr[4] = (val >> 8) & 0xff;
2317         addr[5] = val & 0xff;
2318 }
2319
2320
2321 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2322 {
2323         struct sh_eth_private *mdp = netdev_priv(ndev);
2324         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2325         int i;
2326         u8 c_addr[ETH_ALEN];
2327
2328         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2329                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2330                 if (ether_addr_equal(addr, c_addr))
2331                         return i;
2332         }
2333
2334         return -ENOENT;
2335 }
2336
2337 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2338 {
2339         u8 blank[ETH_ALEN];
2340         int entry;
2341
2342         memset(blank, 0, sizeof(blank));
2343         entry = sh_eth_tsu_find_entry(ndev, blank);
2344         return (entry < 0) ? -ENOMEM : entry;
2345 }
2346
2347 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2348                                               int entry)
2349 {
2350         struct sh_eth_private *mdp = netdev_priv(ndev);
2351         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2352         int ret;
2353         u8 blank[ETH_ALEN];
2354
2355         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2356                          ~(1 << (31 - entry)), TSU_TEN);
2357
2358         memset(blank, 0, sizeof(blank));
2359         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2360         if (ret < 0)
2361                 return ret;
2362         return 0;
2363 }
2364
2365 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2366 {
2367         struct sh_eth_private *mdp = netdev_priv(ndev);
2368         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2369         int i, ret;
2370
2371         if (!mdp->cd->tsu)
2372                 return 0;
2373
2374         i = sh_eth_tsu_find_entry(ndev, addr);
2375         if (i < 0) {
2376                 /* No entry found, create one */
2377                 i = sh_eth_tsu_find_empty(ndev);
2378                 if (i < 0)
2379                         return -ENOMEM;
2380                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2381                 if (ret < 0)
2382                         return ret;
2383
2384                 /* Enable the entry */
2385                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2386                                  (1 << (31 - i)), TSU_TEN);
2387         }
2388
2389         /* Entry found or created, enable POST */
2390         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2391
2392         return 0;
2393 }
2394
2395 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2396 {
2397         struct sh_eth_private *mdp = netdev_priv(ndev);
2398         int i, ret;
2399
2400         if (!mdp->cd->tsu)
2401                 return 0;
2402
2403         i = sh_eth_tsu_find_entry(ndev, addr);
2404         if (i) {
2405                 /* Entry found */
2406                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2407                         goto done;
2408
2409                 /* Disable the entry if both ports was disabled */
2410                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2411                 if (ret < 0)
2412                         return ret;
2413         }
2414 done:
2415         return 0;
2416 }
2417
2418 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2419 {
2420         struct sh_eth_private *mdp = netdev_priv(ndev);
2421         int i, ret;
2422
2423         if (unlikely(!mdp->cd->tsu))
2424                 return 0;
2425
2426         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2427                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2428                         continue;
2429
2430                 /* Disable the entry if both ports was disabled */
2431                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2432                 if (ret < 0)
2433                         return ret;
2434         }
2435
2436         return 0;
2437 }
2438
2439 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2440 {
2441         struct sh_eth_private *mdp = netdev_priv(ndev);
2442         u8 addr[ETH_ALEN];
2443         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2444         int i;
2445
2446         if (unlikely(!mdp->cd->tsu))
2447                 return;
2448
2449         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2450                 sh_eth_tsu_read_entry(reg_offset, addr);
2451                 if (is_multicast_ether_addr(addr))
2452                         sh_eth_tsu_del_entry(ndev, addr);
2453         }
2454 }
2455
2456 /* Multicast reception directions set */
2457 static void sh_eth_set_multicast_list(struct net_device *ndev)
2458 {
2459         struct sh_eth_private *mdp = netdev_priv(ndev);
2460         u32 ecmr_bits;
2461         int mcast_all = 0;
2462         unsigned long flags;
2463
2464         spin_lock_irqsave(&mdp->lock, flags);
2465         /* Initial condition is MCT = 1, PRM = 0.
2466          * Depending on ndev->flags, set PRM or clear MCT
2467          */
2468         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2469
2470         if (!(ndev->flags & IFF_MULTICAST)) {
2471                 sh_eth_tsu_purge_mcast(ndev);
2472                 mcast_all = 1;
2473         }
2474         if (ndev->flags & IFF_ALLMULTI) {
2475                 sh_eth_tsu_purge_mcast(ndev);
2476                 ecmr_bits &= ~ECMR_MCT;
2477                 mcast_all = 1;
2478         }
2479
2480         if (ndev->flags & IFF_PROMISC) {
2481                 sh_eth_tsu_purge_all(ndev);
2482                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2483         } else if (mdp->cd->tsu) {
2484                 struct netdev_hw_addr *ha;
2485                 netdev_for_each_mc_addr(ha, ndev) {
2486                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2487                                 continue;
2488
2489                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2490                                 if (!mcast_all) {
2491                                         sh_eth_tsu_purge_mcast(ndev);
2492                                         ecmr_bits &= ~ECMR_MCT;
2493                                         mcast_all = 1;
2494                                 }
2495                         }
2496                 }
2497         } else {
2498                 /* Normal, unicast/broadcast-only mode. */
2499                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2500         }
2501
2502         /* update the ethernet mode */
2503         sh_eth_write(ndev, ecmr_bits, ECMR);
2504
2505         spin_unlock_irqrestore(&mdp->lock, flags);
2506 }
2507
2508 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2509 {
2510         if (!mdp->port)
2511                 return TSU_VTAG0;
2512         else
2513                 return TSU_VTAG1;
2514 }
2515
2516 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2517                                   __be16 proto, u16 vid)
2518 {
2519         struct sh_eth_private *mdp = netdev_priv(ndev);
2520         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2521
2522         if (unlikely(!mdp->cd->tsu))
2523                 return -EPERM;
2524
2525         /* No filtering if vid = 0 */
2526         if (!vid)
2527                 return 0;
2528
2529         mdp->vlan_num_ids++;
2530
2531         /* The controller has one VLAN tag HW filter. So, if the filter is
2532          * already enabled, the driver disables it and the filte
2533          */
2534         if (mdp->vlan_num_ids > 1) {
2535                 /* disable VLAN filter */
2536                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2537                 return 0;
2538         }
2539
2540         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2541                          vtag_reg_index);
2542
2543         return 0;
2544 }
2545
2546 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2547                                    __be16 proto, u16 vid)
2548 {
2549         struct sh_eth_private *mdp = netdev_priv(ndev);
2550         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2551
2552         if (unlikely(!mdp->cd->tsu))
2553                 return -EPERM;
2554
2555         /* No filtering if vid = 0 */
2556         if (!vid)
2557                 return 0;
2558
2559         mdp->vlan_num_ids--;
2560         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2561
2562         return 0;
2563 }
2564
2565 /* SuperH's TSU register init function */
2566 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2567 {
2568         if (sh_eth_is_rz_fast_ether(mdp)) {
2569                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2570                 return;
2571         }
2572
2573         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2574         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2575         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2576         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2577         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2578         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2579         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2580         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2581         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2582         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2583         if (sh_eth_is_gether(mdp)) {
2584                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2585                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2586         } else {
2587                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2588                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2589         }
2590         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2591         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2592         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2593         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2594         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2595         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2596         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2597 }
2598
2599 /* MDIO bus release function */
2600 static int sh_mdio_release(struct sh_eth_private *mdp)
2601 {
2602         /* unregister mdio bus */
2603         mdiobus_unregister(mdp->mii_bus);
2604
2605         /* free bitbang info */
2606         free_mdio_bitbang(mdp->mii_bus);
2607
2608         return 0;
2609 }
2610
2611 /* MDIO bus init function */
2612 static int sh_mdio_init(struct sh_eth_private *mdp,
2613                         struct sh_eth_plat_data *pd)
2614 {
2615         int ret, i;
2616         struct bb_info *bitbang;
2617         struct platform_device *pdev = mdp->pdev;
2618         struct device *dev = &mdp->pdev->dev;
2619
2620         /* create bit control struct for PHY */
2621         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2622         if (!bitbang) {
2623                 ret = -ENOMEM;
2624                 goto out;
2625         }
2626
2627         /* bitbang init */
2628         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2629         bitbang->set_gate = pd->set_mdio_gate;
2630         bitbang->mdi_msk = PIR_MDI;
2631         bitbang->mdo_msk = PIR_MDO;
2632         bitbang->mmd_msk = PIR_MMD;
2633         bitbang->mdc_msk = PIR_MDC;
2634         bitbang->ctrl.ops = &bb_ops;
2635
2636         /* MII controller setting */
2637         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2638         if (!mdp->mii_bus) {
2639                 ret = -ENOMEM;
2640                 goto out;
2641         }
2642
2643         /* Hook up MII support for ethtool */
2644         mdp->mii_bus->name = "sh_mii";
2645         mdp->mii_bus->parent = dev;
2646         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2647                  pdev->name, pdev->id);
2648
2649         /* PHY IRQ */
2650         mdp->mii_bus->irq = devm_kzalloc(dev, sizeof(int) * PHY_MAX_ADDR,
2651                                          GFP_KERNEL);
2652         if (!mdp->mii_bus->irq) {
2653                 ret = -ENOMEM;
2654                 goto out_free_bus;
2655         }
2656
2657         /* register MDIO bus */
2658         if (dev->of_node) {
2659                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2660         } else {
2661                 for (i = 0; i < PHY_MAX_ADDR; i++)
2662                         mdp->mii_bus->irq[i] = PHY_POLL;
2663                 if (pd->phy_irq > 0)
2664                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2665
2666                 ret = mdiobus_register(mdp->mii_bus);
2667         }
2668
2669         if (ret)
2670                 goto out_free_bus;
2671
2672         return 0;
2673
2674 out_free_bus:
2675         free_mdio_bitbang(mdp->mii_bus);
2676
2677 out:
2678         return ret;
2679 }
2680
2681 static const u16 *sh_eth_get_register_offset(int register_type)
2682 {
2683         const u16 *reg_offset = NULL;
2684
2685         switch (register_type) {
2686         case SH_ETH_REG_GIGABIT:
2687                 reg_offset = sh_eth_offset_gigabit;
2688                 break;
2689         case SH_ETH_REG_FAST_RZ:
2690                 reg_offset = sh_eth_offset_fast_rz;
2691                 break;
2692         case SH_ETH_REG_FAST_RCAR:
2693                 reg_offset = sh_eth_offset_fast_rcar;
2694                 break;
2695         case SH_ETH_REG_FAST_SH4:
2696                 reg_offset = sh_eth_offset_fast_sh4;
2697                 break;
2698         case SH_ETH_REG_FAST_SH3_SH2:
2699                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2700                 break;
2701         default:
2702                 break;
2703         }
2704
2705         return reg_offset;
2706 }
2707
2708 static const struct net_device_ops sh_eth_netdev_ops = {
2709         .ndo_open               = sh_eth_open,
2710         .ndo_stop               = sh_eth_close,
2711         .ndo_start_xmit         = sh_eth_start_xmit,
2712         .ndo_get_stats          = sh_eth_get_stats,
2713         .ndo_tx_timeout         = sh_eth_tx_timeout,
2714         .ndo_do_ioctl           = sh_eth_do_ioctl,
2715         .ndo_validate_addr      = eth_validate_addr,
2716         .ndo_set_mac_address    = eth_mac_addr,
2717         .ndo_change_mtu         = eth_change_mtu,
2718 };
2719
2720 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2721         .ndo_open               = sh_eth_open,
2722         .ndo_stop               = sh_eth_close,
2723         .ndo_start_xmit         = sh_eth_start_xmit,
2724         .ndo_get_stats          = sh_eth_get_stats,
2725         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2726         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2727         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2728         .ndo_tx_timeout         = sh_eth_tx_timeout,
2729         .ndo_do_ioctl           = sh_eth_do_ioctl,
2730         .ndo_validate_addr      = eth_validate_addr,
2731         .ndo_set_mac_address    = eth_mac_addr,
2732         .ndo_change_mtu         = eth_change_mtu,
2733 };
2734
2735 #ifdef CONFIG_OF
2736 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2737 {
2738         struct device_node *np = dev->of_node;
2739         struct sh_eth_plat_data *pdata;
2740         const char *mac_addr;
2741
2742         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2743         if (!pdata)
2744                 return NULL;
2745
2746         pdata->phy_interface = of_get_phy_mode(np);
2747
2748         mac_addr = of_get_mac_address(np);
2749         if (mac_addr)
2750                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2751
2752         pdata->no_ether_link =
2753                 of_property_read_bool(np, "renesas,no-ether-link");
2754         pdata->ether_link_active_low =
2755                 of_property_read_bool(np, "renesas,ether-link-active-low");
2756
2757         return pdata;
2758 }
2759
2760 static const struct of_device_id sh_eth_match_table[] = {
2761         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2762         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2763         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2764         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2765         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2766         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2767         { }
2768 };
2769 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2770 #else
2771 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2772 {
2773         return NULL;
2774 }
2775 #endif
2776
2777 static int sh_eth_drv_probe(struct platform_device *pdev)
2778 {
2779         int ret, devno = 0;
2780         struct resource *res;
2781         struct net_device *ndev = NULL;
2782         struct sh_eth_private *mdp = NULL;
2783         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2784         const struct platform_device_id *id = platform_get_device_id(pdev);
2785
2786         /* get base addr */
2787         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2788         if (unlikely(res == NULL)) {
2789                 dev_err(&pdev->dev, "invalid resource\n");
2790                 ret = -EINVAL;
2791                 goto out;
2792         }
2793
2794         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2795         if (!ndev) {
2796                 ret = -ENOMEM;
2797                 goto out;
2798         }
2799
2800         /* The sh Ether-specific entries in the device structure. */
2801         ndev->base_addr = res->start;
2802         devno = pdev->id;
2803         if (devno < 0)
2804                 devno = 0;
2805
2806         ndev->dma = -1;
2807         ret = platform_get_irq(pdev, 0);
2808         if (ret < 0) {
2809                 ret = -ENODEV;
2810                 goto out_release;
2811         }
2812         ndev->irq = ret;
2813
2814         SET_NETDEV_DEV(ndev, &pdev->dev);
2815
2816         mdp = netdev_priv(ndev);
2817         mdp->num_tx_ring = TX_RING_SIZE;
2818         mdp->num_rx_ring = RX_RING_SIZE;
2819         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2820         if (IS_ERR(mdp->addr)) {
2821                 ret = PTR_ERR(mdp->addr);
2822                 goto out_release;
2823         }
2824
2825         spin_lock_init(&mdp->lock);
2826         mdp->pdev = pdev;
2827         pm_runtime_enable(&pdev->dev);
2828         pm_runtime_resume(&pdev->dev);
2829
2830         if (pdev->dev.of_node)
2831                 pd = sh_eth_parse_dt(&pdev->dev);
2832         if (!pd) {
2833                 dev_err(&pdev->dev, "no platform data\n");
2834                 ret = -EINVAL;
2835                 goto out_release;
2836         }
2837
2838         /* get PHY ID */
2839         mdp->phy_id = pd->phy;
2840         mdp->phy_interface = pd->phy_interface;
2841         /* EDMAC endian */
2842         mdp->edmac_endian = pd->edmac_endian;
2843         mdp->no_ether_link = pd->no_ether_link;
2844         mdp->ether_link_active_low = pd->ether_link_active_low;
2845
2846         /* set cpu data */
2847         if (id) {
2848                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2849         } else  {
2850                 const struct of_device_id *match;
2851
2852                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2853                                         &pdev->dev);
2854                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2855         }
2856         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2857         if (!mdp->reg_offset) {
2858                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2859                         mdp->cd->register_type);
2860                 ret = -EINVAL;
2861                 goto out_release;
2862         }
2863         sh_eth_set_default_cpu_data(mdp->cd);
2864
2865         /* set function */
2866         if (mdp->cd->tsu)
2867                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2868         else
2869                 ndev->netdev_ops = &sh_eth_netdev_ops;
2870         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2871         ndev->watchdog_timeo = TX_TIMEOUT;
2872
2873         /* debug message level */
2874         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2875
2876         /* read and set MAC address */
2877         read_mac_address(ndev, pd->mac_addr);
2878         if (!is_valid_ether_addr(ndev->dev_addr)) {
2879                 dev_warn(&pdev->dev,
2880                          "no valid MAC address supplied, using a random one.\n");
2881                 eth_hw_addr_random(ndev);
2882         }
2883
2884         /* ioremap the TSU registers */
2885         if (mdp->cd->tsu) {
2886                 struct resource *rtsu;
2887                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2888                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2889                 if (IS_ERR(mdp->tsu_addr)) {
2890                         ret = PTR_ERR(mdp->tsu_addr);
2891                         goto out_release;
2892                 }
2893                 mdp->port = devno % 2;
2894                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2895         }
2896
2897         /* initialize first or needed device */
2898         if (!devno || pd->needs_init) {
2899                 if (mdp->cd->chip_reset)
2900                         mdp->cd->chip_reset(ndev);
2901
2902                 if (mdp->cd->tsu) {
2903                         /* TSU init (Init only)*/
2904                         sh_eth_tsu_init(mdp);
2905                 }
2906         }
2907
2908         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2909
2910         /* network device register */
2911         ret = register_netdev(ndev);
2912         if (ret)
2913                 goto out_napi_del;
2914
2915         /* mdio bus init */
2916         ret = sh_mdio_init(mdp, pd);
2917         if (ret) {
2918                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2919                 goto out_unregister;
2920         }
2921
2922         /* print device information */
2923         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2924                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2925
2926         platform_set_drvdata(pdev, ndev);
2927
2928         return ret;
2929
2930 out_unregister:
2931         unregister_netdev(ndev);
2932
2933 out_napi_del:
2934         netif_napi_del(&mdp->napi);
2935
2936 out_release:
2937         /* net_dev free */
2938         if (ndev)
2939                 free_netdev(ndev);
2940
2941 out:
2942         return ret;
2943 }
2944
2945 static int sh_eth_drv_remove(struct platform_device *pdev)
2946 {
2947         struct net_device *ndev = platform_get_drvdata(pdev);
2948         struct sh_eth_private *mdp = netdev_priv(ndev);
2949
2950         sh_mdio_release(mdp);
2951         unregister_netdev(ndev);
2952         netif_napi_del(&mdp->napi);
2953         pm_runtime_disable(&pdev->dev);
2954         free_netdev(ndev);
2955
2956         return 0;
2957 }
2958
2959 #ifdef CONFIG_PM
2960 static int sh_eth_runtime_nop(struct device *dev)
2961 {
2962         /* Runtime PM callback shared between ->runtime_suspend()
2963          * and ->runtime_resume(). Simply returns success.
2964          *
2965          * This driver re-initializes all registers after
2966          * pm_runtime_get_sync() anyway so there is no need
2967          * to save and restore registers here.
2968          */
2969         return 0;
2970 }
2971
2972 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2973         .runtime_suspend = sh_eth_runtime_nop,
2974         .runtime_resume = sh_eth_runtime_nop,
2975 };
2976 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2977 #else
2978 #define SH_ETH_PM_OPS NULL
2979 #endif
2980
2981 static struct platform_device_id sh_eth_id_table[] = {
2982         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2983         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2984         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2985         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2986         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2987         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2988         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2989         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2990         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2991         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2992         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2993         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2994         { }
2995 };
2996 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2997
2998 static struct platform_driver sh_eth_driver = {
2999         .probe = sh_eth_drv_probe,
3000         .remove = sh_eth_drv_remove,
3001         .id_table = sh_eth_id_table,
3002         .driver = {
3003                    .name = CARDNAME,
3004                    .pm = SH_ETH_PM_OPS,
3005                    .of_match_table = of_match_ptr(sh_eth_match_table),
3006         },
3007 };
3008
3009 module_platform_driver(sh_eth_driver);
3010
3011 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3012 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3013 MODULE_LICENSE("GPL v2");