drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   5  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   6  *  Copyright (C) 2014 Codethink Limited
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *
  17  *  The full GNU General Public License is included in this distribution in
  18  *  the file called "COPYING".
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/delay.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mdio-bitbang.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/of_net.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44 #include <linux/of_mdio.h>
  45
  46 #include "sh_eth.h"
  47
  48 #define SH_ETH_DEF_MSG_ENABLE \
  49                 (NETIF_MSG_LINK | \
  50                 NETIF_MSG_TIMER | \
  51                 NETIF_MSG_RX_ERR| \
  52                 NETIF_MSG_TX_ERR)
  53
  54 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  55         [EDSR]          = 0x0000,
  56         [EDMR]          = 0x0400,
  57         [EDTRR]         = 0x0408,
  58         [EDRRR]         = 0x0410,
  59         [EESR]          = 0x0428,
  60         [EESIPR]        = 0x0430,
  61         [TDLAR]         = 0x0010,
  62         [TDFAR]         = 0x0014,
  63         [TDFXR]         = 0x0018,
  64         [TDFFR]         = 0x001c,
  65         [RDLAR]         = 0x0030,
  66         [RDFAR]         = 0x0034,
  67         [RDFXR]         = 0x0038,
  68         [RDFFR]         = 0x003c,
  69         [TRSCER]        = 0x0438,
  70         [RMFCR]         = 0x0440,
  71         [TFTR]          = 0x0448,
  72         [FDR]           = 0x0450,
  73         [RMCR]          = 0x0458,
  74         [RPADIR]        = 0x0460,
  75         [FCFTR]         = 0x0468,
  76         [CSMR]          = 0x04E4,
  77
  78         [ECMR]          = 0x0500,
  79         [ECSR]          = 0x0510,
  80         [ECSIPR]        = 0x0518,
  81         [PIR]           = 0x0520,
  82         [PSR]           = 0x0528,
  83         [PIPR]          = 0x052c,
  84         [RFLR]          = 0x0508,
  85         [APR]           = 0x0554,
  86         [MPR]           = 0x0558,
  87         [PFTCR]         = 0x055c,
  88         [PFRCR]         = 0x0560,
  89         [TPAUSER]       = 0x0564,
  90         [GECMR]         = 0x05b0,
  91         [BCULR]         = 0x05b4,
  92         [MAHR]          = 0x05c0,
  93         [MALR]          = 0x05c8,
  94         [TROCR]         = 0x0700,
  95         [CDCR]          = 0x0708,
  96         [LCCR]          = 0x0710,
  97         [CEFCR]         = 0x0740,
  98         [FRECR]         = 0x0748,
  99         [TSFRCR]        = 0x0750,
 100         [TLFRCR]        = 0x0758,
 101         [RFCR]          = 0x0760,
 102         [CERCR]         = 0x0768,
 103         [CEECR]         = 0x0770,
 104         [MAFCR]         = 0x0778,
 105         [RMII_MII]      = 0x0790,
 106
 107         [ARSTR]         = 0x0000,
 108         [TSU_CTRST]     = 0x0004,
 109         [TSU_FWEN0]     = 0x0010,
 110         [TSU_FWEN1]     = 0x0014,
 111         [TSU_FCM]       = 0x0018,
 112         [TSU_BSYSL0]    = 0x0020,
 113         [TSU_BSYSL1]    = 0x0024,
 114         [TSU_PRISL0]    = 0x0028,
 115         [TSU_PRISL1]    = 0x002c,
 116         [TSU_FWSL0]     = 0x0030,
 117         [TSU_FWSL1]     = 0x0034,
 118         [TSU_FWSLC]     = 0x0038,
 119         [TSU_QTAG0]     = 0x0040,
 120         [TSU_QTAG1]     = 0x0044,
 121         [TSU_FWSR]      = 0x0050,
 122         [TSU_FWINMK]    = 0x0054,
 123         [TSU_ADQT0]     = 0x0048,
 124         [TSU_ADQT1]     = 0x004c,
 125         [TSU_VTAG0]     = 0x0058,
 126         [TSU_VTAG1]     = 0x005c,
 127         [TSU_ADSBSY]    = 0x0060,
 128         [TSU_TEN]       = 0x0064,
 129         [TSU_POST1]     = 0x0070,
 130         [TSU_POST2]     = 0x0074,
 131         [TSU_POST3]     = 0x0078,
 132         [TSU_POST4]     = 0x007c,
 133         [TSU_ADRH0]     = 0x0100,
 134         [TSU_ADRL0]     = 0x0104,
 135         [TSU_ADRH31]    = 0x01f8,
 136         [TSU_ADRL31]    = 0x01fc,
 137
 138         [TXNLCR0]       = 0x0080,
 139         [TXALCR0]       = 0x0084,
 140         [RXNLCR0]       = 0x0088,
 141         [RXALCR0]       = 0x008c,
 142         [FWNLCR0]       = 0x0090,
 143         [FWALCR0]       = 0x0094,
 144         [TXNLCR1]       = 0x00a0,
 145         [TXALCR1]       = 0x00a0,
 146         [RXNLCR1]       = 0x00a8,
 147         [RXALCR1]       = 0x00ac,
 148         [FWNLCR1]       = 0x00b0,
 149         [FWALCR1]       = 0x00b4,
 150 };
 151
 152 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 153         [EDSR]          = 0x0000,
 154         [EDMR]          = 0x0400,
 155         [EDTRR]         = 0x0408,
 156         [EDRRR]         = 0x0410,
 157         [EESR]          = 0x0428,
 158         [EESIPR]        = 0x0430,
 159         [TDLAR]         = 0x0010,
 160         [TDFAR]         = 0x0014,
 161         [TDFXR]         = 0x0018,
 162         [TDFFR]         = 0x001c,
 163         [RDLAR]         = 0x0030,
 164         [RDFAR]         = 0x0034,
 165         [RDFXR]         = 0x0038,
 166         [RDFFR]         = 0x003c,
 167         [TRSCER]        = 0x0438,
 168         [RMFCR]         = 0x0440,
 169         [TFTR]          = 0x0448,
 170         [FDR]           = 0x0450,
 171         [RMCR]          = 0x0458,
 172         [RPADIR]        = 0x0460,
 173         [FCFTR]         = 0x0468,
 174         [CSMR]          = 0x04E4,
 175
 176         [ECMR]          = 0x0500,
 177         [RFLR]          = 0x0508,
 178         [ECSR]          = 0x0510,
 179         [ECSIPR]        = 0x0518,
 180         [PIR]           = 0x0520,
 181         [APR]           = 0x0554,
 182         [MPR]           = 0x0558,
 183         [PFTCR]         = 0x055c,
 184         [PFRCR]         = 0x0560,
 185         [TPAUSER]       = 0x0564,
 186         [MAHR]          = 0x05c0,
 187         [MALR]          = 0x05c8,
 188         [CEFCR]         = 0x0740,
 189         [FRECR]         = 0x0748,
 190         [TSFRCR]        = 0x0750,
 191         [TLFRCR]        = 0x0758,
 192         [RFCR]          = 0x0760,
 193         [MAFCR]         = 0x0778,
 194
 195         [ARSTR]         = 0x0000,
 196         [TSU_CTRST]     = 0x0004,
 197         [TSU_VTAG0]     = 0x0058,
 198         [TSU_ADSBSY]    = 0x0060,
 199         [TSU_TEN]       = 0x0064,
 200         [TSU_ADRH0]     = 0x0100,
 201         [TSU_ADRL0]     = 0x0104,
 202         [TSU_ADRH31]    = 0x01f8,
 203         [TSU_ADRL31]    = 0x01fc,
 204
 205         [TXNLCR0]       = 0x0080,
 206         [TXALCR0]       = 0x0084,
 207         [RXNLCR0]       = 0x0088,
 208         [RXALCR0]       = 0x008C,
 209 };
 210
 211 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 212         [ECMR]          = 0x0300,
 213         [RFLR]          = 0x0308,
 214         [ECSR]          = 0x0310,
 215         [ECSIPR]        = 0x0318,
 216         [PIR]           = 0x0320,
 217         [PSR]           = 0x0328,
 218         [RDMLR]         = 0x0340,
 219         [IPGR]          = 0x0350,
 220         [APR]           = 0x0354,
 221         [MPR]           = 0x0358,
 222         [RFCF]          = 0x0360,
 223         [TPAUSER]       = 0x0364,
 224         [TPAUSECR]      = 0x0368,
 225         [MAHR]          = 0x03c0,
 226         [MALR]          = 0x03c8,
 227         [TROCR]         = 0x03d0,
 228         [CDCR]          = 0x03d4,
 229         [LCCR]          = 0x03d8,
 230         [CNDCR]         = 0x03dc,
 231         [CEFCR]         = 0x03e4,
 232         [FRECR]         = 0x03e8,
 233         [TSFRCR]        = 0x03ec,
 234         [TLFRCR]        = 0x03f0,
 235         [RFCR]          = 0x03f4,
 236         [MAFCR]         = 0x03f8,
 237
 238         [EDMR]          = 0x0200,
 239         [EDTRR]         = 0x0208,
 240         [EDRRR]         = 0x0210,
 241         [TDLAR]         = 0x0218,
 242         [RDLAR]         = 0x0220,
 243         [EESR]          = 0x0228,
 244         [EESIPR]        = 0x0230,
 245         [TRSCER]        = 0x0238,
 246         [RMFCR]         = 0x0240,
 247         [TFTR]          = 0x0248,
 248         [FDR]           = 0x0250,
 249         [RMCR]          = 0x0258,
 250         [TFUCR]         = 0x0264,
 251         [RFOCR]         = 0x0268,
 252         [RMIIMODE]      = 0x026c,
 253         [FCFTR]         = 0x0270,
 254         [TRIMD]         = 0x027c,
 255 };
 256
 257 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 258         [ECMR]          = 0x0100,
 259         [RFLR]          = 0x0108,
 260         [ECSR]          = 0x0110,
 261         [ECSIPR]        = 0x0118,
 262         [PIR]           = 0x0120,
 263         [PSR]           = 0x0128,
 264         [RDMLR]         = 0x0140,
 265         [IPGR]          = 0x0150,
 266         [APR]           = 0x0154,
 267         [MPR]           = 0x0158,
 268         [TPAUSER]       = 0x0164,
 269         [RFCF]          = 0x0160,
 270         [TPAUSECR]      = 0x0168,
 271         [BCFRR]         = 0x016c,
 272         [MAHR]          = 0x01c0,
 273         [MALR]          = 0x01c8,
 274         [TROCR]         = 0x01d0,
 275         [CDCR]          = 0x01d4,
 276         [LCCR]          = 0x01d8,
 277         [CNDCR]         = 0x01dc,
 278         [CEFCR]         = 0x01e4,
 279         [FRECR]         = 0x01e8,
 280         [TSFRCR]        = 0x01ec,
 281         [TLFRCR]        = 0x01f0,
 282         [RFCR]          = 0x01f4,
 283         [MAFCR]         = 0x01f8,
 284         [RTRATE]        = 0x01fc,
 285
 286         [EDMR]          = 0x0000,
 287         [EDTRR]         = 0x0008,
 288         [EDRRR]         = 0x0010,
 289         [TDLAR]         = 0x0018,
 290         [RDLAR]         = 0x0020,
 291         [EESR]          = 0x0028,
 292         [EESIPR]        = 0x0030,
 293         [TRSCER]        = 0x0038,
 294         [RMFCR]         = 0x0040,
 295         [TFTR]          = 0x0048,
 296         [FDR]           = 0x0050,
 297         [RMCR]          = 0x0058,
 298         [TFUCR]         = 0x0064,
 299         [RFOCR]         = 0x0068,
 300         [FCFTR]         = 0x0070,
 301         [RPADIR]        = 0x0078,
 302         [TRIMD]         = 0x007c,
 303         [RBWAR]         = 0x00c8,
 304         [RDFAR]         = 0x00cc,
 305         [TBRAR]         = 0x00d4,
 306         [TDFAR]         = 0x00d8,
 307 };
 308
 309 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 310         [EDMR]          = 0x0000,
 311         [EDTRR]         = 0x0004,
 312         [EDRRR]         = 0x0008,
 313         [TDLAR]         = 0x000c,
 314         [RDLAR]         = 0x0010,
 315         [EESR]          = 0x0014,
 316         [EESIPR]        = 0x0018,
 317         [TRSCER]        = 0x001c,
 318         [RMFCR]         = 0x0020,
 319         [TFTR]          = 0x0024,
 320         [FDR]           = 0x0028,
 321         [RMCR]          = 0x002c,
 322         [EDOCR]         = 0x0030,
 323         [FCFTR]         = 0x0034,
 324         [RPADIR]        = 0x0038,
 325         [TRIMD]         = 0x003c,
 326         [RBWAR]         = 0x0040,
 327         [RDFAR]         = 0x0044,
 328         [TBRAR]         = 0x004c,
 329         [TDFAR]         = 0x0050,
 330
 331         [ECMR]          = 0x0160,
 332         [ECSR]          = 0x0164,
 333         [ECSIPR]        = 0x0168,
 334         [PIR]           = 0x016c,
 335         [MAHR]          = 0x0170,
 336         [MALR]          = 0x0174,
 337         [RFLR]          = 0x0178,
 338         [PSR]           = 0x017c,
 339         [TROCR]         = 0x0180,
 340         [CDCR]          = 0x0184,
 341         [LCCR]          = 0x0188,
 342         [CNDCR]         = 0x018c,
 343         [CEFCR]         = 0x0194,
 344         [FRECR]         = 0x0198,
 345         [TSFRCR]        = 0x019c,
 346         [TLFRCR]        = 0x01a0,
 347         [RFCR]          = 0x01a4,
 348         [MAFCR]         = 0x01a8,
 349         [IPGR]          = 0x01b4,
 350         [APR]           = 0x01b8,
 351         [MPR]           = 0x01bc,
 352         [TPAUSER]       = 0x01c4,
 353         [BCFR]          = 0x01cc,
 354
 355         [ARSTR]         = 0x0000,
 356         [TSU_CTRST]     = 0x0004,
 357         [TSU_FWEN0]     = 0x0010,
 358         [TSU_FWEN1]     = 0x0014,
 359         [TSU_FCM]       = 0x0018,
 360         [TSU_BSYSL0]    = 0x0020,
 361         [TSU_BSYSL1]    = 0x0024,
 362         [TSU_PRISL0]    = 0x0028,
 363         [TSU_PRISL1]    = 0x002c,
 364         [TSU_FWSL0]     = 0x0030,
 365         [TSU_FWSL1]     = 0x0034,
 366         [TSU_FWSLC]     = 0x0038,
 367         [TSU_QTAGM0]    = 0x0040,
 368         [TSU_QTAGM1]    = 0x0044,
 369         [TSU_ADQT0]     = 0x0048,
 370         [TSU_ADQT1]     = 0x004c,
 371         [TSU_FWSR]      = 0x0050,
 372         [TSU_FWINMK]    = 0x0054,
 373         [TSU_ADSBSY]    = 0x0060,
 374         [TSU_TEN]       = 0x0064,
 375         [TSU_POST1]     = 0x0070,
 376         [TSU_POST2]     = 0x0074,
 377         [TSU_POST3]     = 0x0078,
 378         [TSU_POST4]     = 0x007c,
 379
 380         [TXNLCR0]       = 0x0080,
 381         [TXALCR0]       = 0x0084,
 382         [RXNLCR0]       = 0x0088,
 383         [RXALCR0]       = 0x008c,
 384         [FWNLCR0]       = 0x0090,
 385         [FWALCR0]       = 0x0094,
 386         [TXNLCR1]       = 0x00a0,
 387         [TXALCR1]       = 0x00a0,
 388         [RXNLCR1]       = 0x00a8,
 389         [RXALCR1]       = 0x00ac,
 390         [FWNLCR1]       = 0x00b0,
 391         [FWALCR1]       = 0x00b4,
 392
 393         [TSU_ADRH0]     = 0x0100,
 394         [TSU_ADRL0]     = 0x0104,
 395         [TSU_ADRL31]    = 0x01fc,
 396 };
 397
 398 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 399 {
 400         return mdp->reg_offset == sh_eth_offset_gigabit;
 401 }
 402
 403 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 404 {
 405         return mdp->reg_offset == sh_eth_offset_fast_rz;
 406 }
 407
 408 static void sh_eth_select_mii(struct net_device *ndev)
 409 {
 410         u32 value = 0x0;
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412
 413         switch (mdp->phy_interface) {
 414         case PHY_INTERFACE_MODE_GMII:
 415                 value = 0x2;
 416                 break;
 417         case PHY_INTERFACE_MODE_MII:
 418                 value = 0x1;
 419                 break;
 420         case PHY_INTERFACE_MODE_RMII:
 421                 value = 0x0;
 422                 break;
 423         default:
 424                 netdev_warn(ndev,
 425                             "PHY interface mode was not setup. Set to MII.\n");
 426                 value = 0x1;
 427                 break;
 428         }
 429
 430         sh_eth_write(ndev, value, RMII_MII);
 431 }
 432
 433 static void sh_eth_set_duplex(struct net_device *ndev)
 434 {
 435         struct sh_eth_private *mdp = netdev_priv(ndev);
 436
 437         if (mdp->duplex) /* Full */
 438                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 439         else            /* Half */
 440                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 441 }
 442
 443 /* There is CPU dependent code */
 444 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 445 {
 446         struct sh_eth_private *mdp = netdev_priv(ndev);
 447
 448         switch (mdp->speed) {
 449         case 10: /* 10BASE */
 450                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 451                 break;
 452         case 100:/* 100BASE */
 453                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 454                 break;
 455         default:
 456                 break;
 457         }
 458 }
 459
 460 /* R8A7778/9 */
 461 static struct sh_eth_cpu_data r8a777x_data = {
 462         .set_duplex     = sh_eth_set_duplex,
 463         .set_rate       = sh_eth_set_rate_r8a777x,
 464
 465         .register_type  = SH_ETH_REG_FAST_RCAR,
 466
 467         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 468         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 469         .eesipr_value   = 0x01ff009f,
 470
 471         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 472         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 473                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 474                           EESR_ECI,
 475
 476         .apr            = 1,
 477         .mpr            = 1,
 478         .tpauser        = 1,
 479         .hw_swap        = 1,
 480 };
 481
 482 /* R8A7790/1 */
 483 static struct sh_eth_cpu_data r8a779x_data = {
 484         .set_duplex     = sh_eth_set_duplex,
 485         .set_rate       = sh_eth_set_rate_r8a777x,
 486
 487         .register_type  = SH_ETH_REG_FAST_RCAR,
 488
 489         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 490         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 491         .eesipr_value   = 0x01ff009f,
 492
 493         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 494         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 495                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 496                           EESR_ECI,
 497
 498         .apr            = 1,
 499         .mpr            = 1,
 500         .tpauser        = 1,
 501         .hw_swap        = 1,
 502         .rmiimode       = 1,
 503         .shift_rd0      = 1,
 504 };
 505
 506 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 507 {
 508         struct sh_eth_private *mdp = netdev_priv(ndev);
 509
 510         switch (mdp->speed) {
 511         case 10: /* 10BASE */
 512                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 513                 break;
 514         case 100:/* 100BASE */
 515                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 516                 break;
 517         default:
 518                 break;
 519         }
 520 }
 521
 522 /* SH7724 */
 523 static struct sh_eth_cpu_data sh7724_data = {
 524         .set_duplex     = sh_eth_set_duplex,
 525         .set_rate       = sh_eth_set_rate_sh7724,
 526
 527         .register_type  = SH_ETH_REG_FAST_SH4,
 528
 529         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 530         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 531         .eesipr_value   = 0x01ff009f,
 532
 533         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 534         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 535                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 536                           EESR_ECI,
 537
 538         .apr            = 1,
 539         .mpr            = 1,
 540         .tpauser        = 1,
 541         .hw_swap        = 1,
 542         .rpadir         = 1,
 543         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 544 };
 545
 546 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 547 {
 548         struct sh_eth_private *mdp = netdev_priv(ndev);
 549
 550         switch (mdp->speed) {
 551         case 10: /* 10BASE */
 552                 sh_eth_write(ndev, 0, RTRATE);
 553                 break;
 554         case 100:/* 100BASE */
 555                 sh_eth_write(ndev, 1, RTRATE);
 556                 break;
 557         default:
 558                 break;
 559         }
 560 }
 561
 562 /* SH7757 */
 563 static struct sh_eth_cpu_data sh7757_data = {
 564         .set_duplex     = sh_eth_set_duplex,
 565         .set_rate       = sh_eth_set_rate_sh7757,
 566
 567         .register_type  = SH_ETH_REG_FAST_SH4,
 568
 569         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 570
 571         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 572         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 573                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 574                           EESR_ECI,
 575
 576         .irq_flags      = IRQF_SHARED,
 577         .apr            = 1,
 578         .mpr            = 1,
 579         .tpauser        = 1,
 580         .hw_swap        = 1,
 581         .no_ade         = 1,
 582         .rpadir         = 1,
 583         .rpadir_value   = 2 << 16,
 584 };
 585
 586 #define SH_GIGA_ETH_BASE        0xfee00000UL
 587 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 588 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 589 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 590 {
 591         int i;
 592         unsigned long mahr[2], malr[2];
 593
 594         /* save MAHR and MALR */
 595         for (i = 0; i < 2; i++) {
 596                 malr[i] = ioread32((void *)GIGA_MALR(i));
 597                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 598         }
 599
 600         /* reset device */
 601         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 602         mdelay(1);
 603
 604         /* restore MAHR and MALR */
 605         for (i = 0; i < 2; i++) {
 606                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 607                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 608         }
 609 }
 610
 611 static void sh_eth_set_rate_giga(struct net_device *ndev)
 612 {
 613         struct sh_eth_private *mdp = netdev_priv(ndev);
 614
 615         switch (mdp->speed) {
 616         case 10: /* 10BASE */
 617                 sh_eth_write(ndev, 0x00000000, GECMR);
 618                 break;
 619         case 100:/* 100BASE */
 620                 sh_eth_write(ndev, 0x00000010, GECMR);
 621                 break;
 622         case 1000: /* 1000BASE */
 623                 sh_eth_write(ndev, 0x00000020, GECMR);
 624                 break;
 625         default:
 626                 break;
 627         }
 628 }
 629
 630 /* SH7757(GETHERC) */
 631 static struct sh_eth_cpu_data sh7757_data_giga = {
 632         .chip_reset     = sh_eth_chip_reset_giga,
 633         .set_duplex     = sh_eth_set_duplex,
 634         .set_rate       = sh_eth_set_rate_giga,
 635
 636         .register_type  = SH_ETH_REG_GIGABIT,
 637
 638         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 639         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 640         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 641
 642         .tx_check       = EESR_TC1 | EESR_FTC,
 643         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 644                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 645                           EESR_TDE | EESR_ECI,
 646         .fdr_value      = 0x0000072f,
 647
 648         .irq_flags      = IRQF_SHARED,
 649         .apr            = 1,
 650         .mpr            = 1,
 651         .tpauser        = 1,
 652         .bculr          = 1,
 653         .hw_swap        = 1,
 654         .rpadir         = 1,
 655         .rpadir_value   = 2 << 16,
 656         .no_trimd       = 1,
 657         .no_ade         = 1,
 658         .tsu            = 1,
 659 };
 660
 661 static void sh_eth_chip_reset(struct net_device *ndev)
 662 {
 663         struct sh_eth_private *mdp = netdev_priv(ndev);
 664
 665         /* reset device */
 666         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 667         mdelay(1);
 668 }
 669
 670 static void sh_eth_set_rate_gether(struct net_device *ndev)
 671 {
 672         struct sh_eth_private *mdp = netdev_priv(ndev);
 673
 674         switch (mdp->speed) {
 675         case 10: /* 10BASE */
 676                 sh_eth_write(ndev, GECMR_10, GECMR);
 677                 break;
 678         case 100:/* 100BASE */
 679                 sh_eth_write(ndev, GECMR_100, GECMR);
 680                 break;
 681         case 1000: /* 1000BASE */
 682                 sh_eth_write(ndev, GECMR_1000, GECMR);
 683                 break;
 684         default:
 685                 break;
 686         }
 687 }
 688
 689 /* SH7734 */
 690 static struct sh_eth_cpu_data sh7734_data = {
 691         .chip_reset     = sh_eth_chip_reset,
 692         .set_duplex     = sh_eth_set_duplex,
 693         .set_rate       = sh_eth_set_rate_gether,
 694
 695         .register_type  = SH_ETH_REG_GIGABIT,
 696
 697         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 698         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 699         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 700
 701         .tx_check       = EESR_TC1 | EESR_FTC,
 702         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 703                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 704                           EESR_TDE | EESR_ECI,
 705
 706         .apr            = 1,
 707         .mpr            = 1,
 708         .tpauser        = 1,
 709         .bculr          = 1,
 710         .hw_swap        = 1,
 711         .no_trimd       = 1,
 712         .no_ade         = 1,
 713         .tsu            = 1,
 714         .hw_crc         = 1,
 715         .select_mii     = 1,
 716 };
 717
 718 /* SH7763 */
 719 static struct sh_eth_cpu_data sh7763_data = {
 720         .chip_reset     = sh_eth_chip_reset,
 721         .set_duplex     = sh_eth_set_duplex,
 722         .set_rate       = sh_eth_set_rate_gether,
 723
 724         .register_type  = SH_ETH_REG_GIGABIT,
 725
 726         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 727         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 728         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 729
 730         .tx_check       = EESR_TC1 | EESR_FTC,
 731         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 732                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 733                           EESR_ECI,
 734
 735         .apr            = 1,
 736         .mpr            = 1,
 737         .tpauser        = 1,
 738         .bculr          = 1,
 739         .hw_swap        = 1,
 740         .no_trimd       = 1,
 741         .no_ade         = 1,
 742         .tsu            = 1,
 743         .irq_flags      = IRQF_SHARED,
 744 };
 745
 746 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 747 {
 748         struct sh_eth_private *mdp = netdev_priv(ndev);
 749
 750         /* reset device */
 751         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 752         mdelay(1);
 753
 754         sh_eth_select_mii(ndev);
 755 }
 756
 757 /* R8A7740 */
 758 static struct sh_eth_cpu_data r8a7740_data = {
 759         .chip_reset     = sh_eth_chip_reset_r8a7740,
 760         .set_duplex     = sh_eth_set_duplex,
 761         .set_rate       = sh_eth_set_rate_gether,
 762
 763         .register_type  = SH_ETH_REG_GIGABIT,
 764
 765         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 766         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 767         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 768
 769         .tx_check       = EESR_TC1 | EESR_FTC,
 770         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 771                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 772                           EESR_TDE | EESR_ECI,
 773         .fdr_value      = 0x0000070f,
 774
 775         .apr            = 1,
 776         .mpr            = 1,
 777         .tpauser        = 1,
 778         .bculr          = 1,
 779         .hw_swap        = 1,
 780         .rpadir         = 1,
 781         .rpadir_value   = 2 << 16,
 782         .no_trimd       = 1,
 783         .no_ade         = 1,
 784         .tsu            = 1,
 785         .select_mii     = 1,
 786         .shift_rd0      = 1,
 787 };
 788
 789 /* R7S72100 */
 790 static struct sh_eth_cpu_data r7s72100_data = {
 791         .chip_reset     = sh_eth_chip_reset,
 792         .set_duplex     = sh_eth_set_duplex,
 793
 794         .register_type  = SH_ETH_REG_FAST_RZ,
 795
 796         .ecsr_value     = ECSR_ICD,
 797         .ecsipr_value   = ECSIPR_ICDIP,
 798         .eesipr_value   = 0xff7f009f,
 799
 800         .tx_check       = EESR_TC1 | EESR_FTC,
 801         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 802                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 803                           EESR_TDE | EESR_ECI,
 804         .fdr_value      = 0x0000070f,
 805
 806         .no_psr         = 1,
 807         .apr            = 1,
 808         .mpr            = 1,
 809         .tpauser        = 1,
 810         .hw_swap        = 1,
 811         .rpadir         = 1,
 812         .rpadir_value   = 2 << 16,
 813         .no_trimd       = 1,
 814         .no_ade         = 1,
 815         .hw_crc         = 1,
 816         .tsu            = 1,
 817         .shift_rd0      = 1,
 818 };
 819
 820 static struct sh_eth_cpu_data sh7619_data = {
 821         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 822
 823         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 824
 825         .apr            = 1,
 826         .mpr            = 1,
 827         .tpauser        = 1,
 828         .hw_swap        = 1,
 829 };
 830
 831 static struct sh_eth_cpu_data sh771x_data = {
 832         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 833
 834         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 835         .tsu            = 1,
 836 };
 837
 838 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 839 {
 840         if (!cd->ecsr_value)
 841                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 842
 843         if (!cd->ecsipr_value)
 844                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 845
 846         if (!cd->fcftr_value)
 847                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 848                                   DEFAULT_FIFO_F_D_RFD;
 849
 850         if (!cd->fdr_value)
 851                 cd->fdr_value = DEFAULT_FDR_INIT;
 852
 853         if (!cd->tx_check)
 854                 cd->tx_check = DEFAULT_TX_CHECK;
 855
 856         if (!cd->eesr_err_check)
 857                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 858 }
 859
 860 static int sh_eth_check_reset(struct net_device *ndev)
 861 {
 862         int ret = 0;
 863         int cnt = 100;
 864
 865         while (cnt > 0) {
 866                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 867                         break;
 868                 mdelay(1);
 869                 cnt--;
 870         }
 871         if (cnt <= 0) {
 872                 netdev_err(ndev, "Device reset failed\n");
 873                 ret = -ETIMEDOUT;
 874         }
 875         return ret;
 876 }
 877
 878 static int sh_eth_reset(struct net_device *ndev)
 879 {
 880         struct sh_eth_private *mdp = netdev_priv(ndev);
 881         int ret = 0;
 882
 883         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 884                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 885                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 886                              EDMR);
 887
 888                 ret = sh_eth_check_reset(ndev);
 889                 if (ret)
 890                         goto out;
 891
 892                 /* Table Init */
 893                 sh_eth_write(ndev, 0x0, TDLAR);
 894                 sh_eth_write(ndev, 0x0, TDFAR);
 895                 sh_eth_write(ndev, 0x0, TDFXR);
 896                 sh_eth_write(ndev, 0x0, TDFFR);
 897                 sh_eth_write(ndev, 0x0, RDLAR);
 898                 sh_eth_write(ndev, 0x0, RDFAR);
 899                 sh_eth_write(ndev, 0x0, RDFXR);
 900                 sh_eth_write(ndev, 0x0, RDFFR);
 901
 902                 /* Reset HW CRC register */
 903                 if (mdp->cd->hw_crc)
 904                         sh_eth_write(ndev, 0x0, CSMR);
 905
 906                 /* Select MII mode */
 907                 if (mdp->cd->select_mii)
 908                         sh_eth_select_mii(ndev);
 909         } else {
 910                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 911                              EDMR);
 912                 mdelay(3);
 913                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 914                              EDMR);
 915         }
 916
 917 out:
 918         return ret;
 919 }
 920
 921 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 922 static void sh_eth_set_receive_align(struct sk_buff *skb)
 923 {
 924         int reserve;
 925
 926         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 927         if (reserve)
 928                 skb_reserve(skb, reserve);
 929 }
 930 #else
 931 static void sh_eth_set_receive_align(struct sk_buff *skb)
 932 {
 933         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 934 }
 935 #endif
 936
 937
 938 /* CPU <-> EDMAC endian convert */
 939 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 940 {
 941         switch (mdp->edmac_endian) {
 942         case EDMAC_LITTLE_ENDIAN:
 943                 return cpu_to_le32(x);
 944         case EDMAC_BIG_ENDIAN:
 945                 return cpu_to_be32(x);
 946         }
 947         return x;
 948 }
 949
 950 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 951 {
 952         switch (mdp->edmac_endian) {
 953         case EDMAC_LITTLE_ENDIAN:
 954                 return le32_to_cpu(x);
 955         case EDMAC_BIG_ENDIAN:
 956                 return be32_to_cpu(x);
 957         }
 958         return x;
 959 }
 960
 961 /* Program the hardware MAC address from dev->dev_addr. */
 962 static void update_mac_address(struct net_device *ndev)
 963 {
 964         sh_eth_write(ndev,
 965                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 966                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 967         sh_eth_write(ndev,
 968                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 969 }
 970
 971 /* Get MAC address from SuperH MAC address register
 972  *
 973  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 974  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 975  * When you want use this device, you must set MAC address in bootloader.
 976  *
 977  */
 978 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 979 {
 980         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 981                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 982         } else {
 983                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 984                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 985                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 986                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 987                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 988                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 989         }
 990 }
 991
 992 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 993 {
 994         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 995                 return EDTRR_TRNS_GETHER;
 996         else
 997                 return EDTRR_TRNS_ETHER;
 998 }
 999
1000 struct bb_info {
1001         void (*set_gate)(void *addr);
1002         struct mdiobb_ctrl ctrl;
1003         void *addr;
1004         u32 mmd_msk;/* MMD */
1005         u32 mdo_msk;
1006         u32 mdi_msk;
1007         u32 mdc_msk;
1008 };
1009
1010 /* PHY bit set */
1011 static void bb_set(void *addr, u32 msk)
1012 {
1013         iowrite32(ioread32(addr) | msk, addr);
1014 }
1015
1016 /* PHY bit clear */
1017 static void bb_clr(void *addr, u32 msk)
1018 {
1019         iowrite32((ioread32(addr) & ~msk), addr);
1020 }
1021
1022 /* PHY bit read */
1023 static int bb_read(void *addr, u32 msk)
1024 {
1025         return (ioread32(addr) & msk) != 0;
1026 }
1027
1028 /* Data I/O pin control */
1029 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1030 {
1031         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032
1033         if (bitbang->set_gate)
1034                 bitbang->set_gate(bitbang->addr);
1035
1036         if (bit)
1037                 bb_set(bitbang->addr, bitbang->mmd_msk);
1038         else
1039                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1040 }
1041
1042 /* Set bit data*/
1043 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1044 {
1045         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1046
1047         if (bitbang->set_gate)
1048                 bitbang->set_gate(bitbang->addr);
1049
1050         if (bit)
1051                 bb_set(bitbang->addr, bitbang->mdo_msk);
1052         else
1053                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1054 }
1055
1056 /* Get bit data*/
1057 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1058 {
1059         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1060
1061         if (bitbang->set_gate)
1062                 bitbang->set_gate(bitbang->addr);
1063
1064         return bb_read(bitbang->addr, bitbang->mdi_msk);
1065 }
1066
1067 /* MDC pin control */
1068 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1069 {
1070         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1071
1072         if (bitbang->set_gate)
1073                 bitbang->set_gate(bitbang->addr);
1074
1075         if (bit)
1076                 bb_set(bitbang->addr, bitbang->mdc_msk);
1077         else
1078                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1079 }
1080
1081 /* mdio bus control struct */
1082 static struct mdiobb_ops bb_ops = {
1083         .owner = THIS_MODULE,
1084         .set_mdc = sh_mdc_ctrl,
1085         .set_mdio_dir = sh_mmd_ctrl,
1086         .set_mdio_data = sh_set_mdio,
1087         .get_mdio_data = sh_get_mdio,
1088 };
1089
1090 /* free skb and descriptor buffer */
1091 static void sh_eth_ring_free(struct net_device *ndev)
1092 {
1093         struct sh_eth_private *mdp = netdev_priv(ndev);
1094         int i;
1095
1096         /* Free Rx skb ringbuffer */
1097         if (mdp->rx_skbuff) {
1098                 for (i = 0; i < mdp->num_rx_ring; i++) {
1099                         if (mdp->rx_skbuff[i])
1100                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1101                 }
1102         }
1103         kfree(mdp->rx_skbuff);
1104         mdp->rx_skbuff = NULL;
1105
1106         /* Free Tx skb ringbuffer */
1107         if (mdp->tx_skbuff) {
1108                 for (i = 0; i < mdp->num_tx_ring; i++) {
1109                         if (mdp->tx_skbuff[i])
1110                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1111                 }
1112         }
1113         kfree(mdp->tx_skbuff);
1114         mdp->tx_skbuff = NULL;
1115 }
1116
1117 /* format skb and descriptor buffer */
1118 static void sh_eth_ring_format(struct net_device *ndev)
1119 {
1120         struct sh_eth_private *mdp = netdev_priv(ndev);
1121         int i;
1122         struct sk_buff *skb;
1123         struct sh_eth_rxdesc *rxdesc = NULL;
1124         struct sh_eth_txdesc *txdesc = NULL;
1125         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1126         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1127
1128         mdp->cur_rx = 0;
1129         mdp->cur_tx = 0;
1130         mdp->dirty_rx = 0;
1131         mdp->dirty_tx = 0;
1132
1133         memset(mdp->rx_ring, 0, rx_ringsize);
1134
1135         /* build Rx ring buffer */
1136         for (i = 0; i < mdp->num_rx_ring; i++) {
1137                 /* skb */
1138                 mdp->rx_skbuff[i] = NULL;
1139                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1140                 mdp->rx_skbuff[i] = skb;
1141                 if (skb == NULL)
1142                         break;
1143                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1144                                DMA_FROM_DEVICE);
1145                 sh_eth_set_receive_align(skb);
1146
1147                 /* RX descriptor */
1148                 rxdesc = &mdp->rx_ring[i];
1149                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1150                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1151
1152                 /* The size of the buffer is 16 byte boundary. */
1153                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1154                 /* Rx descriptor address set */
1155                 if (i == 0) {
1156                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1157                         if (sh_eth_is_gether(mdp) ||
1158                             sh_eth_is_rz_fast_ether(mdp))
1159                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1160                 }
1161         }
1162
1163         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1164
1165         /* Mark the last entry as wrapping the ring. */
1166         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1167
1168         memset(mdp->tx_ring, 0, tx_ringsize);
1169
1170         /* build Tx ring buffer */
1171         for (i = 0; i < mdp->num_tx_ring; i++) {
1172                 mdp->tx_skbuff[i] = NULL;
1173                 txdesc = &mdp->tx_ring[i];
1174                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1175                 txdesc->buffer_length = 0;
1176                 if (i == 0) {
1177                         /* Tx descriptor address set */
1178                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1179                         if (sh_eth_is_gether(mdp) ||
1180                             sh_eth_is_rz_fast_ether(mdp))
1181                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1182                 }
1183         }
1184
1185         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1186 }
1187
1188 /* Get skb and descriptor buffer */
1189 static int sh_eth_ring_init(struct net_device *ndev)
1190 {
1191         struct sh_eth_private *mdp = netdev_priv(ndev);
1192         int rx_ringsize, tx_ringsize, ret = 0;
1193
1194         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1195          * card needs room to do 8 byte alignment, +2 so we can reserve
1196          * the first 2 bytes, and +16 gets room for the status word from the
1197          * card.
1198          */
1199         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1200                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1201         if (mdp->cd->rpadir)
1202                 mdp->rx_buf_sz += NET_IP_ALIGN;
1203
1204         /* Allocate RX and TX skb rings */
1205         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1206                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1207         if (!mdp->rx_skbuff) {
1208                 ret = -ENOMEM;
1209                 return ret;
1210         }
1211
1212         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1213                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1214         if (!mdp->tx_skbuff) {
1215                 ret = -ENOMEM;
1216                 goto skb_ring_free;
1217         }
1218
1219         /* Allocate all Rx descriptors. */
1220         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1221         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1222                                           GFP_KERNEL);
1223         if (!mdp->rx_ring) {
1224                 ret = -ENOMEM;
1225                 goto desc_ring_free;
1226         }
1227
1228         mdp->dirty_rx = 0;
1229
1230         /* Allocate all Tx descriptors. */
1231         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1232         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1233                                           GFP_KERNEL);
1234         if (!mdp->tx_ring) {
1235                 ret = -ENOMEM;
1236                 goto desc_ring_free;
1237         }
1238         return ret;
1239
1240 desc_ring_free:
1241         /* free DMA buffer */
1242         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1243
1244 skb_ring_free:
1245         /* Free Rx and Tx skb ring buffer */
1246         sh_eth_ring_free(ndev);
1247         mdp->tx_ring = NULL;
1248         mdp->rx_ring = NULL;
1249
1250         return ret;
1251 }
1252
1253 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1254 {
1255         int ringsize;
1256
1257         if (mdp->rx_ring) {
1258                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1259                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1260                                   mdp->rx_desc_dma);
1261                 mdp->rx_ring = NULL;
1262         }
1263
1264         if (mdp->tx_ring) {
1265                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1266                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1267                                   mdp->tx_desc_dma);
1268                 mdp->tx_ring = NULL;
1269         }
1270 }
1271
1272 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1273 {
1274         int ret = 0;
1275         struct sh_eth_private *mdp = netdev_priv(ndev);
1276         u32 val;
1277
1278         /* Soft Reset */
1279         ret = sh_eth_reset(ndev);
1280         if (ret)
1281                 goto out;
1282
1283         if (mdp->cd->rmiimode)
1284                 sh_eth_write(ndev, 0x1, RMIIMODE);
1285
1286         /* Descriptor format */
1287         sh_eth_ring_format(ndev);
1288         if (mdp->cd->rpadir)
1289                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1290
1291         /* all sh_eth int mask */
1292         sh_eth_write(ndev, 0, EESIPR);
1293
1294 #if defined(__LITTLE_ENDIAN)
1295         if (mdp->cd->hw_swap)
1296                 sh_eth_write(ndev, EDMR_EL, EDMR);
1297         else
1298 #endif
1299                 sh_eth_write(ndev, 0, EDMR);
1300
1301         /* FIFO size set */
1302         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1303         sh_eth_write(ndev, 0, TFTR);
1304
1305         /* Frame recv control (enable multiple-packets per rx irq) */
1306         sh_eth_write(ndev, RMCR_RNC, RMCR);
1307
1308         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1309
1310         if (mdp->cd->bculr)
1311                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1312
1313         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1314
1315         if (!mdp->cd->no_trimd)
1316                 sh_eth_write(ndev, 0, TRIMD);
1317
1318         /* Recv frame limit set register */
1319         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1320                      RFLR);
1321
1322         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1323         if (start)
1324                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1325
1326         /* PAUSE Prohibition */
1327         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1328                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1329
1330         sh_eth_write(ndev, val, ECMR);
1331
1332         if (mdp->cd->set_rate)
1333                 mdp->cd->set_rate(ndev);
1334
1335         /* E-MAC Status Register clear */
1336         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1337
1338         /* E-MAC Interrupt Enable register */
1339         if (start)
1340                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1341
1342         /* Set MAC address */
1343         update_mac_address(ndev);
1344
1345         /* mask reset */
1346         if (mdp->cd->apr)
1347                 sh_eth_write(ndev, APR_AP, APR);
1348         if (mdp->cd->mpr)
1349                 sh_eth_write(ndev, MPR_MP, MPR);
1350         if (mdp->cd->tpauser)
1351                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1352
1353         if (start) {
1354                 /* Setting the Rx mode will start the Rx process. */
1355                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1356
1357                 netif_start_queue(ndev);
1358         }
1359
1360 out:
1361         return ret;
1362 }
1363
1364 /* free Tx skb function */
1365 static int sh_eth_txfree(struct net_device *ndev)
1366 {
1367         struct sh_eth_private *mdp = netdev_priv(ndev);
1368         struct sh_eth_txdesc *txdesc;
1369         int free_num = 0;
1370         int entry = 0;
1371
1372         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1373                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1374                 txdesc = &mdp->tx_ring[entry];
1375                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1376                         break;
1377                 /* Free the original skb. */
1378                 if (mdp->tx_skbuff[entry]) {
1379                         dma_unmap_single(&ndev->dev, txdesc->addr,
1380                                          txdesc->buffer_length, DMA_TO_DEVICE);
1381                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1382                         mdp->tx_skbuff[entry] = NULL;
1383                         free_num++;
1384                 }
1385                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1386                 if (entry >= mdp->num_tx_ring - 1)
1387                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1388
1389                 ndev->stats.tx_packets++;
1390                 ndev->stats.tx_bytes += txdesc->buffer_length;
1391         }
1392         return free_num;
1393 }
1394
1395 /* Packet receive function */
1396 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1397 {
1398         struct sh_eth_private *mdp = netdev_priv(ndev);
1399         struct sh_eth_rxdesc *rxdesc;
1400
1401         int entry = mdp->cur_rx % mdp->num_rx_ring;
1402         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1403         struct sk_buff *skb;
1404         int exceeded = 0;
1405         u16 pkt_len = 0;
1406         u32 desc_status;
1407
1408         rxdesc = &mdp->rx_ring[entry];
1409         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1410                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1411                 pkt_len = rxdesc->frame_length;
1412
1413                 if (--boguscnt < 0)
1414                         break;
1415
1416                 if (*quota <= 0) {
1417                         exceeded = 1;
1418                         break;
1419                 }
1420                 (*quota)--;
1421
1422                 if (!(desc_status & RDFEND))
1423                         ndev->stats.rx_length_errors++;
1424
1425                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1426                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1427                  * bit 0. However, in case of the R8A7740, R8A779x, and
1428                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1429                  * driver needs right shifting by 16.
1430                  */
1431                 if (mdp->cd->shift_rd0)
1432                         desc_status >>= 16;
1433
1434                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1435                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1436                         ndev->stats.rx_errors++;
1437                         if (desc_status & RD_RFS1)
1438                                 ndev->stats.rx_crc_errors++;
1439                         if (desc_status & RD_RFS2)
1440                                 ndev->stats.rx_frame_errors++;
1441                         if (desc_status & RD_RFS3)
1442                                 ndev->stats.rx_length_errors++;
1443                         if (desc_status & RD_RFS4)
1444                                 ndev->stats.rx_length_errors++;
1445                         if (desc_status & RD_RFS6)
1446                                 ndev->stats.rx_missed_errors++;
1447                         if (desc_status & RD_RFS10)
1448                                 ndev->stats.rx_over_errors++;
1449                 } else {
1450                         if (!mdp->cd->hw_swap)
1451                                 sh_eth_soft_swap(
1452                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1453                                         pkt_len + 2);
1454                         skb = mdp->rx_skbuff[entry];
1455                         mdp->rx_skbuff[entry] = NULL;
1456                         if (mdp->cd->rpadir)
1457                                 skb_reserve(skb, NET_IP_ALIGN);
1458                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1459                                                 mdp->rx_buf_sz,
1460                                                 DMA_FROM_DEVICE);
1461                         skb_put(skb, pkt_len);
1462                         skb->protocol = eth_type_trans(skb, ndev);
1463                         netif_receive_skb(skb);
1464                         ndev->stats.rx_packets++;
1465                         ndev->stats.rx_bytes += pkt_len;
1466                 }
1467                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1468                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1469                 rxdesc = &mdp->rx_ring[entry];
1470         }
1471
1472         /* Refill the Rx ring buffers. */
1473         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1474                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1475                 rxdesc = &mdp->rx_ring[entry];
1476                 /* The size of the buffer is 16 byte boundary. */
1477                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1478
1479                 if (mdp->rx_skbuff[entry] == NULL) {
1480                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1481                         mdp->rx_skbuff[entry] = skb;
1482                         if (skb == NULL)
1483                                 break;  /* Better luck next round. */
1484                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1485                                        DMA_FROM_DEVICE);
1486                         sh_eth_set_receive_align(skb);
1487
1488                         skb_checksum_none_assert(skb);
1489                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1490                 }
1491                 if (entry >= mdp->num_rx_ring - 1)
1492                         rxdesc->status |=
1493                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1494                 else
1495                         rxdesc->status |=
1496                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1497         }
1498
1499         /* Restart Rx engine if stopped. */
1500         /* If we don't need to check status, don't. -KDU */
1501         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1502                 /* fix the values for the next receiving if RDE is set */
1503                 if (intr_status & EESR_RDE) {
1504                         u32 count = (sh_eth_read(ndev, RDFAR) -
1505                                      sh_eth_read(ndev, RDLAR)) >> 4;
1506
1507                         mdp->cur_rx = count;
1508                         mdp->dirty_rx = count;
1509                 }
1510                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1511         }
1512
1513         return exceeded;
1514 }
1515
1516 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1517 {
1518         /* disable tx and rx */
1519         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1520                 ~(ECMR_RE | ECMR_TE), ECMR);
1521 }
1522
1523 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1524 {
1525         /* enable tx and rx */
1526         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1527                 (ECMR_RE | ECMR_TE), ECMR);
1528 }
1529
1530 /* error control function */
1531 static void sh_eth_error(struct net_device *ndev, int intr_status)
1532 {
1533         struct sh_eth_private *mdp = netdev_priv(ndev);
1534         u32 felic_stat;
1535         u32 link_stat;
1536         u32 mask;
1537
1538         if (intr_status & EESR_ECI) {
1539                 felic_stat = sh_eth_read(ndev, ECSR);
1540                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1541                 if (felic_stat & ECSR_ICD)
1542                         ndev->stats.tx_carrier_errors++;
1543                 if (felic_stat & ECSR_LCHNG) {
1544                         /* Link Changed */
1545                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1546                                 goto ignore_link;
1547                         } else {
1548                                 link_stat = (sh_eth_read(ndev, PSR));
1549                                 if (mdp->ether_link_active_low)
1550                                         link_stat = ~link_stat;
1551                         }
1552                         if (!(link_stat & PHY_ST_LINK)) {
1553                                 sh_eth_rcv_snd_disable(ndev);
1554                         } else {
1555                                 /* Link Up */
1556                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1557                                                    ~DMAC_M_ECI, EESIPR);
1558                                 /* clear int */
1559                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1560                                              ECSR);
1561                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1562                                                    DMAC_M_ECI, EESIPR);
1563                                 /* enable tx and rx */
1564                                 sh_eth_rcv_snd_enable(ndev);
1565                         }
1566                 }
1567         }
1568
1569 ignore_link:
1570         if (intr_status & EESR_TWB) {
1571                 /* Unused write back interrupt */
1572                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1573                         ndev->stats.tx_aborted_errors++;
1574                         if (netif_msg_tx_err(mdp))
1575                                 netdev_err(ndev, "Transmit Abort\n");
1576                 }
1577         }
1578
1579         if (intr_status & EESR_RABT) {
1580                 /* Receive Abort int */
1581                 if (intr_status & EESR_RFRMER) {
1582                         /* Receive Frame Overflow int */
1583                         ndev->stats.rx_frame_errors++;
1584                         if (netif_msg_rx_err(mdp))
1585                                 netdev_err(ndev, "Receive Abort\n");
1586                 }
1587         }
1588
1589         if (intr_status & EESR_TDE) {
1590                 /* Transmit Descriptor Empty int */
1591                 ndev->stats.tx_fifo_errors++;
1592                 if (netif_msg_tx_err(mdp))
1593                         netdev_err(ndev, "Transmit Descriptor Empty\n");
1594         }
1595
1596         if (intr_status & EESR_TFE) {
1597                 /* FIFO under flow */
1598                 ndev->stats.tx_fifo_errors++;
1599                 if (netif_msg_tx_err(mdp))
1600                         netdev_err(ndev, "Transmit FIFO Under flow\n");
1601         }
1602
1603         if (intr_status & EESR_RDE) {
1604                 /* Receive Descriptor Empty int */
1605                 ndev->stats.rx_over_errors++;
1606
1607                 if (netif_msg_rx_err(mdp))
1608                         netdev_err(ndev, "Receive Descriptor Empty\n");
1609         }
1610
1611         if (intr_status & EESR_RFE) {
1612                 /* Receive FIFO Overflow int */
1613                 ndev->stats.rx_fifo_errors++;
1614                 if (netif_msg_rx_err(mdp))
1615                         netdev_err(ndev, "Receive FIFO Overflow\n");
1616         }
1617
1618         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1619                 /* Address Error */
1620                 ndev->stats.tx_fifo_errors++;
1621                 if (netif_msg_tx_err(mdp))
1622                         netdev_err(ndev, "Address Error\n");
1623         }
1624
1625         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1626         if (mdp->cd->no_ade)
1627                 mask &= ~EESR_ADE;
1628         if (intr_status & mask) {
1629                 /* Tx error */
1630                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1631
1632                 /* dmesg */
1633                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1634                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1635                            (u32)ndev->state, edtrr);
1636                 /* dirty buffer free */
1637                 sh_eth_txfree(ndev);
1638
1639                 /* SH7712 BUG */
1640                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1641                         /* tx dma start */
1642                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1643                 }
1644                 /* wakeup */
1645                 netif_wake_queue(ndev);
1646         }
1647 }
1648
1649 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1650 {
1651         struct net_device *ndev = netdev;
1652         struct sh_eth_private *mdp = netdev_priv(ndev);
1653         struct sh_eth_cpu_data *cd = mdp->cd;
1654         irqreturn_t ret = IRQ_NONE;
1655         unsigned long intr_status, intr_enable;
1656
1657         spin_lock(&mdp->lock);
1658
1659         /* Get interrupt status */
1660         intr_status = sh_eth_read(ndev, EESR);
1661         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1662          * enabled since it's the one that  comes thru regardless of the mask,
1663          * and we need to fully handle it in sh_eth_error() in order to quench
1664          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1665          */
1666         intr_enable = sh_eth_read(ndev, EESIPR);
1667         intr_status &= intr_enable | DMAC_M_ECI;
1668         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1669                 ret = IRQ_HANDLED;
1670         else
1671                 goto other_irq;
1672
1673         if (intr_status & EESR_RX_CHECK) {
1674                 if (napi_schedule_prep(&mdp->napi)) {
1675                         /* Mask Rx interrupts */
1676                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1677                                      EESIPR);
1678                         __napi_schedule(&mdp->napi);
1679                 } else {
1680                         netdev_warn(ndev,
1681                                     "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1682                                     intr_status, intr_enable);
1683                 }
1684         }
1685
1686         /* Tx Check */
1687         if (intr_status & cd->tx_check) {
1688                 /* Clear Tx interrupts */
1689                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1690
1691                 sh_eth_txfree(ndev);
1692                 netif_wake_queue(ndev);
1693         }
1694
1695         if (intr_status & cd->eesr_err_check) {
1696                 /* Clear error interrupts */
1697                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1698
1699                 sh_eth_error(ndev, intr_status);
1700         }
1701
1702 other_irq:
1703         spin_unlock(&mdp->lock);
1704
1705         return ret;
1706 }
1707
1708 static int sh_eth_poll(struct napi_struct *napi, int budget)
1709 {
1710         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1711                                                   napi);
1712         struct net_device *ndev = napi->dev;
1713         int quota = budget;
1714         unsigned long intr_status;
1715
1716         for (;;) {
1717                 intr_status = sh_eth_read(ndev, EESR);
1718                 if (!(intr_status & EESR_RX_CHECK))
1719                         break;
1720                 /* Clear Rx interrupts */
1721                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1722
1723                 if (sh_eth_rx(ndev, intr_status, &quota))
1724                         goto out;
1725         }
1726
1727         napi_complete(napi);
1728
1729         /* Reenable Rx interrupts */
1730         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1731 out:
1732         return budget - quota;
1733 }
1734
1735 /* PHY state control function */
1736 static void sh_eth_adjust_link(struct net_device *ndev)
1737 {
1738         struct sh_eth_private *mdp = netdev_priv(ndev);
1739         struct phy_device *phydev = mdp->phydev;
1740         int new_state = 0;
1741
1742         if (phydev->link) {
1743                 if (phydev->duplex != mdp->duplex) {
1744                         new_state = 1;
1745                         mdp->duplex = phydev->duplex;
1746                         if (mdp->cd->set_duplex)
1747                                 mdp->cd->set_duplex(ndev);
1748                 }
1749
1750                 if (phydev->speed != mdp->speed) {
1751                         new_state = 1;
1752                         mdp->speed = phydev->speed;
1753                         if (mdp->cd->set_rate)
1754                                 mdp->cd->set_rate(ndev);
1755                 }
1756                 if (!mdp->link) {
1757                         sh_eth_write(ndev,
1758                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1759                                      ECMR);
1760                         new_state = 1;
1761                         mdp->link = phydev->link;
1762                         if (mdp->cd->no_psr || mdp->no_ether_link)
1763                                 sh_eth_rcv_snd_enable(ndev);
1764                 }
1765         } else if (mdp->link) {
1766                 new_state = 1;
1767                 mdp->link = 0;
1768                 mdp->speed = 0;
1769                 mdp->duplex = -1;
1770                 if (mdp->cd->no_psr || mdp->no_ether_link)
1771                         sh_eth_rcv_snd_disable(ndev);
1772         }
1773
1774         if (new_state && netif_msg_link(mdp))
1775                 phy_print_status(phydev);
1776 }
1777
1778 /* PHY init function */
1779 static int sh_eth_phy_init(struct net_device *ndev)
1780 {
1781         struct device_node *np = ndev->dev.parent->of_node;
1782         struct sh_eth_private *mdp = netdev_priv(ndev);
1783         struct phy_device *phydev = NULL;
1784
1785         mdp->link = 0;
1786         mdp->speed = 0;
1787         mdp->duplex = -1;
1788
1789         /* Try connect to PHY */
1790         if (np) {
1791                 struct device_node *pn;
1792
1793                 pn = of_parse_phandle(np, "phy-handle", 0);
1794                 phydev = of_phy_connect(ndev, pn,
1795                                         sh_eth_adjust_link, 0,
1796                                         mdp->phy_interface);
1797
1798                 if (!phydev)
1799                         phydev = ERR_PTR(-ENOENT);
1800         } else {
1801                 char phy_id[MII_BUS_ID_SIZE + 3];
1802
1803                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1804                          mdp->mii_bus->id, mdp->phy_id);
1805
1806                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1807                                      mdp->phy_interface);
1808         }
1809
1810         if (IS_ERR(phydev)) {
1811                 netdev_err(ndev, "failed to connect PHY\n");
1812                 return PTR_ERR(phydev);
1813         }
1814
1815         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1816                     phydev->addr, phydev->irq, phydev->drv->name);
1817
1818         mdp->phydev = phydev;
1819
1820         return 0;
1821 }
1822
1823 /* PHY control start function */
1824 static int sh_eth_phy_start(struct net_device *ndev)
1825 {
1826         struct sh_eth_private *mdp = netdev_priv(ndev);
1827         int ret;
1828
1829         ret = sh_eth_phy_init(ndev);
1830         if (ret)
1831                 return ret;
1832
1833         phy_start(mdp->phydev);
1834
1835         return 0;
1836 }
1837
1838 static int sh_eth_get_settings(struct net_device *ndev,
1839                                struct ethtool_cmd *ecmd)
1840 {
1841         struct sh_eth_private *mdp = netdev_priv(ndev);
1842         unsigned long flags;
1843         int ret;
1844
1845         spin_lock_irqsave(&mdp->lock, flags);
1846         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1847         spin_unlock_irqrestore(&mdp->lock, flags);
1848
1849         return ret;
1850 }
1851
1852 static int sh_eth_set_settings(struct net_device *ndev,
1853                                struct ethtool_cmd *ecmd)
1854 {
1855         struct sh_eth_private *mdp = netdev_priv(ndev);
1856         unsigned long flags;
1857         int ret;
1858
1859         spin_lock_irqsave(&mdp->lock, flags);
1860
1861         /* disable tx and rx */
1862         sh_eth_rcv_snd_disable(ndev);
1863
1864         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1865         if (ret)
1866                 goto error_exit;
1867
1868         if (ecmd->duplex == DUPLEX_FULL)
1869                 mdp->duplex = 1;
1870         else
1871                 mdp->duplex = 0;
1872
1873         if (mdp->cd->set_duplex)
1874                 mdp->cd->set_duplex(ndev);
1875
1876 error_exit:
1877         mdelay(1);
1878
1879         /* enable tx and rx */
1880         sh_eth_rcv_snd_enable(ndev);
1881
1882         spin_unlock_irqrestore(&mdp->lock, flags);
1883
1884         return ret;
1885 }
1886
1887 static int sh_eth_nway_reset(struct net_device *ndev)
1888 {
1889         struct sh_eth_private *mdp = netdev_priv(ndev);
1890         unsigned long flags;
1891         int ret;
1892
1893         spin_lock_irqsave(&mdp->lock, flags);
1894         ret = phy_start_aneg(mdp->phydev);
1895         spin_unlock_irqrestore(&mdp->lock, flags);
1896
1897         return ret;
1898 }
1899
1900 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1901 {
1902         struct sh_eth_private *mdp = netdev_priv(ndev);
1903         return mdp->msg_enable;
1904 }
1905
1906 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1907 {
1908         struct sh_eth_private *mdp = netdev_priv(ndev);
1909         mdp->msg_enable = value;
1910 }
1911
1912 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1913         "rx_current", "tx_current",
1914         "rx_dirty", "tx_dirty",
1915 };
1916 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1917
1918 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1919 {
1920         switch (sset) {
1921         case ETH_SS_STATS:
1922                 return SH_ETH_STATS_LEN;
1923         default:
1924                 return -EOPNOTSUPP;
1925         }
1926 }
1927
1928 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1929                                      struct ethtool_stats *stats, u64 *data)
1930 {
1931         struct sh_eth_private *mdp = netdev_priv(ndev);
1932         int i = 0;
1933
1934         /* device-specific stats */
1935         data[i++] = mdp->cur_rx;
1936         data[i++] = mdp->cur_tx;
1937         data[i++] = mdp->dirty_rx;
1938         data[i++] = mdp->dirty_tx;
1939 }
1940
1941 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1942 {
1943         switch (stringset) {
1944         case ETH_SS_STATS:
1945                 memcpy(data, *sh_eth_gstrings_stats,
1946                        sizeof(sh_eth_gstrings_stats));
1947                 break;
1948         }
1949 }
1950
1951 static void sh_eth_get_ringparam(struct net_device *ndev,
1952                                  struct ethtool_ringparam *ring)
1953 {
1954         struct sh_eth_private *mdp = netdev_priv(ndev);
1955
1956         ring->rx_max_pending = RX_RING_MAX;
1957         ring->tx_max_pending = TX_RING_MAX;
1958         ring->rx_pending = mdp->num_rx_ring;
1959         ring->tx_pending = mdp->num_tx_ring;
1960 }
1961
1962 static int sh_eth_set_ringparam(struct net_device *ndev,
1963                                 struct ethtool_ringparam *ring)
1964 {
1965         struct sh_eth_private *mdp = netdev_priv(ndev);
1966         int ret;
1967
1968         if (ring->tx_pending > TX_RING_MAX ||
1969             ring->rx_pending > RX_RING_MAX ||
1970             ring->tx_pending < TX_RING_MIN ||
1971             ring->rx_pending < RX_RING_MIN)
1972                 return -EINVAL;
1973         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1974                 return -EINVAL;
1975
1976         if (netif_running(ndev)) {
1977                 netif_tx_disable(ndev);
1978                 /* Disable interrupts by clearing the interrupt mask. */
1979                 sh_eth_write(ndev, 0x0000, EESIPR);
1980                 /* Stop the chip's Tx and Rx processes. */
1981                 sh_eth_write(ndev, 0, EDTRR);
1982                 sh_eth_write(ndev, 0, EDRRR);
1983                 synchronize_irq(ndev->irq);
1984         }
1985
1986         /* Free all the skbuffs in the Rx queue. */
1987         sh_eth_ring_free(ndev);
1988         /* Free DMA buffer */
1989         sh_eth_free_dma_buffer(mdp);
1990
1991         /* Set new parameters */
1992         mdp->num_rx_ring = ring->rx_pending;
1993         mdp->num_tx_ring = ring->tx_pending;
1994
1995         ret = sh_eth_ring_init(ndev);
1996         if (ret < 0) {
1997                 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1998                 return ret;
1999         }
2000         ret = sh_eth_dev_init(ndev, false);
2001         if (ret < 0) {
2002                 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
2003                 return ret;
2004         }
2005
2006         if (netif_running(ndev)) {
2007                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2008                 /* Setting the Rx mode will start the Rx process. */
2009                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2010                 netif_wake_queue(ndev);
2011         }
2012
2013         return 0;
2014 }
2015
2016 static const struct ethtool_ops sh_eth_ethtool_ops = {
2017         .get_settings   = sh_eth_get_settings,
2018         .set_settings   = sh_eth_set_settings,
2019         .nway_reset     = sh_eth_nway_reset,
2020         .get_msglevel   = sh_eth_get_msglevel,
2021         .set_msglevel   = sh_eth_set_msglevel,
2022         .get_link       = ethtool_op_get_link,
2023         .get_strings    = sh_eth_get_strings,
2024         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2025         .get_sset_count     = sh_eth_get_sset_count,
2026         .get_ringparam  = sh_eth_get_ringparam,
2027         .set_ringparam  = sh_eth_set_ringparam,
2028 };
2029
2030 /* network device open function */
2031 static int sh_eth_open(struct net_device *ndev)
2032 {
2033         int ret = 0;
2034         struct sh_eth_private *mdp = netdev_priv(ndev);
2035
2036         pm_runtime_get_sync(&mdp->pdev->dev);
2037
2038         napi_enable(&mdp->napi);
2039
2040         ret = request_irq(ndev->irq, sh_eth_interrupt,
2041                           mdp->cd->irq_flags, ndev->name, ndev);
2042         if (ret) {
2043                 netdev_err(ndev, "Can not assign IRQ number\n");
2044                 goto out_napi_off;
2045         }
2046
2047         /* Descriptor set */
2048         ret = sh_eth_ring_init(ndev);
2049         if (ret)
2050                 goto out_free_irq;
2051
2052         /* device init */
2053         ret = sh_eth_dev_init(ndev, true);
2054         if (ret)
2055                 goto out_free_irq;
2056
2057         /* PHY control start*/
2058         ret = sh_eth_phy_start(ndev);
2059         if (ret)
2060                 goto out_free_irq;
2061
2062         return ret;
2063
2064 out_free_irq:
2065         free_irq(ndev->irq, ndev);
2066 out_napi_off:
2067         napi_disable(&mdp->napi);
2068         pm_runtime_put_sync(&mdp->pdev->dev);
2069         return ret;
2070 }
2071
2072 /* Timeout function */
2073 static void sh_eth_tx_timeout(struct net_device *ndev)
2074 {
2075         struct sh_eth_private *mdp = netdev_priv(ndev);
2076         struct sh_eth_rxdesc *rxdesc;
2077         int i;
2078
2079         netif_stop_queue(ndev);
2080
2081         if (netif_msg_timer(mdp)) {
2082                 netdev_err(ndev,
2083                            "transmit timed out, status %8.8x, resetting...\n",
2084                            (int)sh_eth_read(ndev, EESR));
2085         }
2086
2087         /* tx_errors count up */
2088         ndev->stats.tx_errors++;
2089
2090         /* Free all the skbuffs in the Rx queue. */
2091         for (i = 0; i < mdp->num_rx_ring; i++) {
2092                 rxdesc = &mdp->rx_ring[i];
2093                 rxdesc->status = 0;
2094                 rxdesc->addr = 0xBADF00D0;
2095                 if (mdp->rx_skbuff[i])
2096                         dev_kfree_skb(mdp->rx_skbuff[i]);
2097                 mdp->rx_skbuff[i] = NULL;
2098         }
2099         for (i = 0; i < mdp->num_tx_ring; i++) {
2100                 if (mdp->tx_skbuff[i])
2101                         dev_kfree_skb(mdp->tx_skbuff[i]);
2102                 mdp->tx_skbuff[i] = NULL;
2103         }
2104
2105         /* device init */
2106         sh_eth_dev_init(ndev, true);
2107 }
2108
2109 /* Packet transmit function */
2110 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2111 {
2112         struct sh_eth_private *mdp = netdev_priv(ndev);
2113         struct sh_eth_txdesc *txdesc;
2114         u32 entry;
2115         unsigned long flags;
2116
2117         spin_lock_irqsave(&mdp->lock, flags);
2118         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2119                 if (!sh_eth_txfree(ndev)) {
2120                         if (netif_msg_tx_queued(mdp))
2121                                 netdev_warn(ndev, "TxFD exhausted.\n");
2122                         netif_stop_queue(ndev);
2123                         spin_unlock_irqrestore(&mdp->lock, flags);
2124                         return NETDEV_TX_BUSY;
2125                 }
2126         }
2127         spin_unlock_irqrestore(&mdp->lock, flags);
2128
2129         entry = mdp->cur_tx % mdp->num_tx_ring;
2130         mdp->tx_skbuff[entry] = skb;
2131         txdesc = &mdp->tx_ring[entry];
2132         /* soft swap. */
2133         if (!mdp->cd->hw_swap)
2134                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2135                                  skb->len + 2);
2136         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2137                                       DMA_TO_DEVICE);
2138         if (skb->len < ETH_ZLEN)
2139                 txdesc->buffer_length = ETH_ZLEN;
2140         else
2141                 txdesc->buffer_length = skb->len;
2142
2143         if (entry >= mdp->num_tx_ring - 1)
2144                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2145         else
2146                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2147
2148         mdp->cur_tx++;
2149
2150         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2151                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2152
2153         return NETDEV_TX_OK;
2154 }
2155
2156 /* device close function */
2157 static int sh_eth_close(struct net_device *ndev)
2158 {
2159         struct sh_eth_private *mdp = netdev_priv(ndev);
2160
2161         netif_stop_queue(ndev);
2162
2163         /* Disable interrupts by clearing the interrupt mask. */
2164         sh_eth_write(ndev, 0x0000, EESIPR);
2165
2166         /* Stop the chip's Tx and Rx processes. */
2167         sh_eth_write(ndev, 0, EDTRR);
2168         sh_eth_write(ndev, 0, EDRRR);
2169
2170         /* PHY Disconnect */
2171         if (mdp->phydev) {
2172                 phy_stop(mdp->phydev);
2173                 phy_disconnect(mdp->phydev);
2174         }
2175
2176         free_irq(ndev->irq, ndev);
2177
2178         napi_disable(&mdp->napi);
2179
2180         /* Free all the skbuffs in the Rx queue. */
2181         sh_eth_ring_free(ndev);
2182
2183         /* free DMA buffer */
2184         sh_eth_free_dma_buffer(mdp);
2185
2186         pm_runtime_put_sync(&mdp->pdev->dev);
2187
2188         return 0;
2189 }
2190
2191 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2192 {
2193         struct sh_eth_private *mdp = netdev_priv(ndev);
2194
2195         if (sh_eth_is_rz_fast_ether(mdp))
2196                 return &ndev->stats;
2197
2198         pm_runtime_get_sync(&mdp->pdev->dev);
2199
2200         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2201         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2202         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2203         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2204         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2205         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2206         if (sh_eth_is_gether(mdp)) {
2207                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2208                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2209                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2210                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2211         } else {
2212                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2213                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2214         }
2215         pm_runtime_put_sync(&mdp->pdev->dev);
2216
2217         return &ndev->stats;
2218 }
2219
2220 /* ioctl to device function */
2221 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2222 {
2223         struct sh_eth_private *mdp = netdev_priv(ndev);
2224         struct phy_device *phydev = mdp->phydev;
2225
2226         if (!netif_running(ndev))
2227                 return -EINVAL;
2228
2229         if (!phydev)
2230                 return -ENODEV;
2231
2232         return phy_mii_ioctl(phydev, rq, cmd);
2233 }
2234
2235 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2236 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2237                                             int entry)
2238 {
2239         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2240 }
2241
2242 static u32 sh_eth_tsu_get_post_mask(int entry)
2243 {
2244         return 0x0f << (28 - ((entry % 8) * 4));
2245 }
2246
2247 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2248 {
2249         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2250 }
2251
2252 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2253                                              int entry)
2254 {
2255         struct sh_eth_private *mdp = netdev_priv(ndev);
2256         u32 tmp;
2257         void *reg_offset;
2258
2259         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2260         tmp = ioread32(reg_offset);
2261         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2262 }
2263
2264 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2265                                               int entry)
2266 {
2267         struct sh_eth_private *mdp = netdev_priv(ndev);
2268         u32 post_mask, ref_mask, tmp;
2269         void *reg_offset;
2270
2271         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2272         post_mask = sh_eth_tsu_get_post_mask(entry);
2273         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2274
2275         tmp = ioread32(reg_offset);
2276         iowrite32(tmp & ~post_mask, reg_offset);
2277
2278         /* If other port enables, the function returns "true" */
2279         return tmp & ref_mask;
2280 }
2281
2282 static int sh_eth_tsu_busy(struct net_device *ndev)
2283 {
2284         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2285         struct sh_eth_private *mdp = netdev_priv(ndev);
2286
2287         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2288                 udelay(10);
2289                 timeout--;
2290                 if (timeout <= 0) {
2291                         netdev_err(ndev, "%s: timeout\n", __func__);
2292                         return -ETIMEDOUT;
2293                 }
2294         }
2295
2296         return 0;
2297 }
2298
2299 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2300                                   const u8 *addr)
2301 {
2302         u32 val;
2303
2304         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2305         iowrite32(val, reg);
2306         if (sh_eth_tsu_busy(ndev) < 0)
2307                 return -EBUSY;
2308
2309         val = addr[4] << 8 | addr[5];
2310         iowrite32(val, reg + 4);
2311         if (sh_eth_tsu_busy(ndev) < 0)
2312                 return -EBUSY;
2313
2314         return 0;
2315 }
2316
2317 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2318 {
2319         u32 val;
2320
2321         val = ioread32(reg);
2322         addr[0] = (val >> 24) & 0xff;
2323         addr[1] = (val >> 16) & 0xff;
2324         addr[2] = (val >> 8) & 0xff;
2325         addr[3] = val & 0xff;
2326         val = ioread32(reg + 4);
2327         addr[4] = (val >> 8) & 0xff;
2328         addr[5] = val & 0xff;
2329 }
2330
2331
2332 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2333 {
2334         struct sh_eth_private *mdp = netdev_priv(ndev);
2335         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2336         int i;
2337         u8 c_addr[ETH_ALEN];
2338
2339         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2340                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2341                 if (ether_addr_equal(addr, c_addr))
2342                         return i;
2343         }
2344
2345         return -ENOENT;
2346 }
2347
2348 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2349 {
2350         u8 blank[ETH_ALEN];
2351         int entry;
2352
2353         memset(blank, 0, sizeof(blank));
2354         entry = sh_eth_tsu_find_entry(ndev, blank);
2355         return (entry < 0) ? -ENOMEM : entry;
2356 }
2357
2358 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2359                                               int entry)
2360 {
2361         struct sh_eth_private *mdp = netdev_priv(ndev);
2362         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2363         int ret;
2364         u8 blank[ETH_ALEN];
2365
2366         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2367                          ~(1 << (31 - entry)), TSU_TEN);
2368
2369         memset(blank, 0, sizeof(blank));
2370         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2371         if (ret < 0)
2372                 return ret;
2373         return 0;
2374 }
2375
2376 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2377 {
2378         struct sh_eth_private *mdp = netdev_priv(ndev);
2379         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2380         int i, ret;
2381
2382         if (!mdp->cd->tsu)
2383                 return 0;
2384
2385         i = sh_eth_tsu_find_entry(ndev, addr);
2386         if (i < 0) {
2387                 /* No entry found, create one */
2388                 i = sh_eth_tsu_find_empty(ndev);
2389                 if (i < 0)
2390                         return -ENOMEM;
2391                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2392                 if (ret < 0)
2393                         return ret;
2394
2395                 /* Enable the entry */
2396                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2397                                  (1 << (31 - i)), TSU_TEN);
2398         }
2399
2400         /* Entry found or created, enable POST */
2401         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2402
2403         return 0;
2404 }
2405
2406 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2407 {
2408         struct sh_eth_private *mdp = netdev_priv(ndev);
2409         int i, ret;
2410
2411         if (!mdp->cd->tsu)
2412                 return 0;
2413
2414         i = sh_eth_tsu_find_entry(ndev, addr);
2415         if (i) {
2416                 /* Entry found */
2417                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2418                         goto done;
2419
2420                 /* Disable the entry if both ports was disabled */
2421                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2422                 if (ret < 0)
2423                         return ret;
2424         }
2425 done:
2426         return 0;
2427 }
2428
2429 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2430 {
2431         struct sh_eth_private *mdp = netdev_priv(ndev);
2432         int i, ret;
2433
2434         if (unlikely(!mdp->cd->tsu))
2435                 return 0;
2436
2437         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2438                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2439                         continue;
2440
2441                 /* Disable the entry if both ports was disabled */
2442                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2443                 if (ret < 0)
2444                         return ret;
2445         }
2446
2447         return 0;
2448 }
2449
2450 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2451 {
2452         struct sh_eth_private *mdp = netdev_priv(ndev);
2453         u8 addr[ETH_ALEN];
2454         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2455         int i;
2456
2457         if (unlikely(!mdp->cd->tsu))
2458                 return;
2459
2460         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2461                 sh_eth_tsu_read_entry(reg_offset, addr);
2462                 if (is_multicast_ether_addr(addr))
2463                         sh_eth_tsu_del_entry(ndev, addr);
2464         }
2465 }
2466
2467 /* Multicast reception directions set */
2468 static void sh_eth_set_multicast_list(struct net_device *ndev)
2469 {
2470         struct sh_eth_private *mdp = netdev_priv(ndev);
2471         u32 ecmr_bits;
2472         int mcast_all = 0;
2473         unsigned long flags;
2474
2475         spin_lock_irqsave(&mdp->lock, flags);
2476         /* Initial condition is MCT = 1, PRM = 0.
2477          * Depending on ndev->flags, set PRM or clear MCT
2478          */
2479         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2480
2481         if (!(ndev->flags & IFF_MULTICAST)) {
2482                 sh_eth_tsu_purge_mcast(ndev);
2483                 mcast_all = 1;
2484         }
2485         if (ndev->flags & IFF_ALLMULTI) {
2486                 sh_eth_tsu_purge_mcast(ndev);
2487                 ecmr_bits &= ~ECMR_MCT;
2488                 mcast_all = 1;
2489         }
2490
2491         if (ndev->flags & IFF_PROMISC) {
2492                 sh_eth_tsu_purge_all(ndev);
2493                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2494         } else if (mdp->cd->tsu) {
2495                 struct netdev_hw_addr *ha;
2496                 netdev_for_each_mc_addr(ha, ndev) {
2497                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2498                                 continue;
2499
2500                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2501                                 if (!mcast_all) {
2502                                         sh_eth_tsu_purge_mcast(ndev);
2503                                         ecmr_bits &= ~ECMR_MCT;
2504                                         mcast_all = 1;
2505                                 }
2506                         }
2507                 }
2508         } else {
2509                 /* Normal, unicast/broadcast-only mode. */
2510                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2511         }
2512
2513         /* update the ethernet mode */
2514         sh_eth_write(ndev, ecmr_bits, ECMR);
2515
2516         spin_unlock_irqrestore(&mdp->lock, flags);
2517 }
2518
2519 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2520 {
2521         if (!mdp->port)
2522                 return TSU_VTAG0;
2523         else
2524                 return TSU_VTAG1;
2525 }
2526
2527 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2528                                   __be16 proto, u16 vid)
2529 {
2530         struct sh_eth_private *mdp = netdev_priv(ndev);
2531         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2532
2533         if (unlikely(!mdp->cd->tsu))
2534                 return -EPERM;
2535
2536         /* No filtering if vid = 0 */
2537         if (!vid)
2538                 return 0;
2539
2540         mdp->vlan_num_ids++;
2541
2542         /* The controller has one VLAN tag HW filter. So, if the filter is
2543          * already enabled, the driver disables it and the filte
2544          */
2545         if (mdp->vlan_num_ids > 1) {
2546                 /* disable VLAN filter */
2547                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2548                 return 0;
2549         }
2550
2551         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2552                          vtag_reg_index);
2553
2554         return 0;
2555 }
2556
2557 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2558                                    __be16 proto, u16 vid)
2559 {
2560         struct sh_eth_private *mdp = netdev_priv(ndev);
2561         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2562
2563         if (unlikely(!mdp->cd->tsu))
2564                 return -EPERM;
2565
2566         /* No filtering if vid = 0 */
2567         if (!vid)
2568                 return 0;
2569
2570         mdp->vlan_num_ids--;
2571         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2572
2573         return 0;
2574 }
2575
2576 /* SuperH's TSU register init function */
2577 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2578 {
2579         if (sh_eth_is_rz_fast_ether(mdp)) {
2580                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2581                 return;
2582         }
2583
2584         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2585         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2586         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2587         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2588         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2589         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2590         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2591         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2592         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2593         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2594         if (sh_eth_is_gether(mdp)) {
2595                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2596                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2597         } else {
2598                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2599                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2600         }
2601         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2602         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2603         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2604         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2605         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2606         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2607         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2608 }
2609
2610 /* MDIO bus release function */
2611 static int sh_mdio_release(struct net_device *ndev)
2612 {
2613         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2614
2615         /* unregister mdio bus */
2616         mdiobus_unregister(bus);
2617
2618         /* remove mdio bus info from net_device */
2619         dev_set_drvdata(&ndev->dev, NULL);
2620
2621         /* free bitbang info */
2622         free_mdio_bitbang(bus);
2623
2624         return 0;
2625 }
2626
2627 /* MDIO bus init function */
2628 static int sh_mdio_init(struct net_device *ndev, int id,
2629                         struct sh_eth_plat_data *pd)
2630 {
2631         int ret, i;
2632         struct bb_info *bitbang;
2633         struct sh_eth_private *mdp = netdev_priv(ndev);
2634
2635         /* create bit control struct for PHY */
2636         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2637                                GFP_KERNEL);
2638         if (!bitbang) {
2639                 ret = -ENOMEM;
2640                 goto out;
2641         }
2642
2643         /* bitbang init */
2644         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2645         bitbang->set_gate = pd->set_mdio_gate;
2646         bitbang->mdi_msk = PIR_MDI;
2647         bitbang->mdo_msk = PIR_MDO;
2648         bitbang->mmd_msk = PIR_MMD;
2649         bitbang->mdc_msk = PIR_MDC;
2650         bitbang->ctrl.ops = &bb_ops;
2651
2652         /* MII controller setting */
2653         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2654         if (!mdp->mii_bus) {
2655                 ret = -ENOMEM;
2656                 goto out;
2657         }
2658
2659         /* Hook up MII support for ethtool */
2660         mdp->mii_bus->name = "sh_mii";
2661         mdp->mii_bus->parent = &ndev->dev;
2662         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2663                  mdp->pdev->name, id);
2664
2665         /* PHY IRQ */
2666         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2667                                          sizeof(int) * PHY_MAX_ADDR,
2668                                          GFP_KERNEL);
2669         if (!mdp->mii_bus->irq) {
2670                 ret = -ENOMEM;
2671                 goto out_free_bus;
2672         }
2673
2674         /* register mdio bus */
2675         if (ndev->dev.parent->of_node) {
2676                 ret = of_mdiobus_register(mdp->mii_bus,
2677                                           ndev->dev.parent->of_node);
2678         } else {
2679                 for (i = 0; i < PHY_MAX_ADDR; i++)
2680                         mdp->mii_bus->irq[i] = PHY_POLL;
2681                 if (pd->phy_irq > 0)
2682                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2683
2684                 ret = mdiobus_register(mdp->mii_bus);
2685         }
2686
2687         if (ret)
2688                 goto out_free_bus;
2689
2690         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2691
2692         return 0;
2693
2694 out_free_bus:
2695         free_mdio_bitbang(mdp->mii_bus);
2696
2697 out:
2698         return ret;
2699 }
2700
2701 static const u16 *sh_eth_get_register_offset(int register_type)
2702 {
2703         const u16 *reg_offset = NULL;
2704
2705         switch (register_type) {
2706         case SH_ETH_REG_GIGABIT:
2707                 reg_offset = sh_eth_offset_gigabit;
2708                 break;
2709         case SH_ETH_REG_FAST_RZ:
2710                 reg_offset = sh_eth_offset_fast_rz;
2711                 break;
2712         case SH_ETH_REG_FAST_RCAR:
2713                 reg_offset = sh_eth_offset_fast_rcar;
2714                 break;
2715         case SH_ETH_REG_FAST_SH4:
2716                 reg_offset = sh_eth_offset_fast_sh4;
2717                 break;
2718         case SH_ETH_REG_FAST_SH3_SH2:
2719                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2720                 break;
2721         default:
2722                 break;
2723         }
2724
2725         return reg_offset;
2726 }
2727
2728 static const struct net_device_ops sh_eth_netdev_ops = {
2729         .ndo_open               = sh_eth_open,
2730         .ndo_stop               = sh_eth_close,
2731         .ndo_start_xmit         = sh_eth_start_xmit,
2732         .ndo_get_stats          = sh_eth_get_stats,
2733         .ndo_tx_timeout         = sh_eth_tx_timeout,
2734         .ndo_do_ioctl           = sh_eth_do_ioctl,
2735         .ndo_validate_addr      = eth_validate_addr,
2736         .ndo_set_mac_address    = eth_mac_addr,
2737         .ndo_change_mtu         = eth_change_mtu,
2738 };
2739
2740 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2741         .ndo_open               = sh_eth_open,
2742         .ndo_stop               = sh_eth_close,
2743         .ndo_start_xmit         = sh_eth_start_xmit,
2744         .ndo_get_stats          = sh_eth_get_stats,
2745         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2746         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2747         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2748         .ndo_tx_timeout         = sh_eth_tx_timeout,
2749         .ndo_do_ioctl           = sh_eth_do_ioctl,
2750         .ndo_validate_addr      = eth_validate_addr,
2751         .ndo_set_mac_address    = eth_mac_addr,
2752         .ndo_change_mtu         = eth_change_mtu,
2753 };
2754
2755 #ifdef CONFIG_OF
2756 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2757 {
2758         struct device_node *np = dev->of_node;
2759         struct sh_eth_plat_data *pdata;
2760         const char *mac_addr;
2761
2762         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2763         if (!pdata)
2764                 return NULL;
2765
2766         pdata->phy_interface = of_get_phy_mode(np);
2767
2768         mac_addr = of_get_mac_address(np);
2769         if (mac_addr)
2770                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2771
2772         pdata->no_ether_link =
2773                 of_property_read_bool(np, "renesas,no-ether-link");
2774         pdata->ether_link_active_low =
2775                 of_property_read_bool(np, "renesas,ether-link-active-low");
2776
2777         return pdata;
2778 }
2779
2780 static const struct of_device_id sh_eth_match_table[] = {
2781         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2782         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2783         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2784         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2785         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2786         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2787         { }
2788 };
2789 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2790 #else
2791 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2792 {
2793         return NULL;
2794 }
2795 #endif
2796
2797 static int sh_eth_drv_probe(struct platform_device *pdev)
2798 {
2799         int ret, devno = 0;
2800         struct resource *res;
2801         struct net_device *ndev = NULL;
2802         struct sh_eth_private *mdp = NULL;
2803         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2804         const struct platform_device_id *id = platform_get_device_id(pdev);
2805
2806         /* get base addr */
2807         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2808         if (unlikely(res == NULL)) {
2809                 dev_err(&pdev->dev, "invalid resource\n");
2810                 ret = -EINVAL;
2811                 goto out;
2812         }
2813
2814         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2815         if (!ndev) {
2816                 ret = -ENOMEM;
2817                 goto out;
2818         }
2819
2820         /* The sh Ether-specific entries in the device structure. */
2821         ndev->base_addr = res->start;
2822         devno = pdev->id;
2823         if (devno < 0)
2824                 devno = 0;
2825
2826         ndev->dma = -1;
2827         ret = platform_get_irq(pdev, 0);
2828         if (ret < 0) {
2829                 ret = -ENODEV;
2830                 goto out_release;
2831         }
2832         ndev->irq = ret;
2833
2834         SET_NETDEV_DEV(ndev, &pdev->dev);
2835
2836         mdp = netdev_priv(ndev);
2837         mdp->num_tx_ring = TX_RING_SIZE;
2838         mdp->num_rx_ring = RX_RING_SIZE;
2839         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2840         if (IS_ERR(mdp->addr)) {
2841                 ret = PTR_ERR(mdp->addr);
2842                 goto out_release;
2843         }
2844
2845         spin_lock_init(&mdp->lock);
2846         mdp->pdev = pdev;
2847         pm_runtime_enable(&pdev->dev);
2848         pm_runtime_resume(&pdev->dev);
2849
2850         if (pdev->dev.of_node)
2851                 pd = sh_eth_parse_dt(&pdev->dev);
2852         if (!pd) {
2853                 dev_err(&pdev->dev, "no platform data\n");
2854                 ret = -EINVAL;
2855                 goto out_release;
2856         }
2857
2858         /* get PHY ID */
2859         mdp->phy_id = pd->phy;
2860         mdp->phy_interface = pd->phy_interface;
2861         /* EDMAC endian */
2862         mdp->edmac_endian = pd->edmac_endian;
2863         mdp->no_ether_link = pd->no_ether_link;
2864         mdp->ether_link_active_low = pd->ether_link_active_low;
2865
2866         /* set cpu data */
2867         if (id) {
2868                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2869         } else  {
2870                 const struct of_device_id *match;
2871
2872                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2873                                         &pdev->dev);
2874                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2875         }
2876         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2877         if (!mdp->reg_offset) {
2878                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2879                         mdp->cd->register_type);
2880                 ret = -EINVAL;
2881                 goto out_release;
2882         }
2883         sh_eth_set_default_cpu_data(mdp->cd);
2884
2885         /* set function */
2886         if (mdp->cd->tsu)
2887                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2888         else
2889                 ndev->netdev_ops = &sh_eth_netdev_ops;
2890         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2891         ndev->watchdog_timeo = TX_TIMEOUT;
2892
2893         /* debug message level */
2894         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2895
2896         /* read and set MAC address */
2897         read_mac_address(ndev, pd->mac_addr);
2898         if (!is_valid_ether_addr(ndev->dev_addr)) {
2899                 dev_warn(&pdev->dev,
2900                          "no valid MAC address supplied, using a random one.\n");
2901                 eth_hw_addr_random(ndev);
2902         }
2903
2904         /* ioremap the TSU registers */
2905         if (mdp->cd->tsu) {
2906                 struct resource *rtsu;
2907                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2908                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2909                 if (IS_ERR(mdp->tsu_addr)) {
2910                         ret = PTR_ERR(mdp->tsu_addr);
2911                         goto out_release;
2912                 }
2913                 mdp->port = devno % 2;
2914                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2915         }
2916
2917         /* initialize first or needed device */
2918         if (!devno || pd->needs_init) {
2919                 if (mdp->cd->chip_reset)
2920                         mdp->cd->chip_reset(ndev);
2921
2922                 if (mdp->cd->tsu) {
2923                         /* TSU init (Init only)*/
2924                         sh_eth_tsu_init(mdp);
2925                 }
2926         }
2927
2928         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2929
2930         /* network device register */
2931         ret = register_netdev(ndev);
2932         if (ret)
2933                 goto out_napi_del;
2934
2935         /* mdio bus init */
2936         ret = sh_mdio_init(ndev, pdev->id, pd);
2937         if (ret) {
2938                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2939                 goto out_unregister;
2940         }
2941
2942         /* print device information */
2943         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2944                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2945
2946         platform_set_drvdata(pdev, ndev);
2947
2948         return ret;
2949
2950 out_unregister:
2951         unregister_netdev(ndev);
2952
2953 out_napi_del:
2954         netif_napi_del(&mdp->napi);
2955
2956 out_release:
2957         /* net_dev free */
2958         if (ndev)
2959                 free_netdev(ndev);
2960
2961 out:
2962         return ret;
2963 }
2964
2965 static int sh_eth_drv_remove(struct platform_device *pdev)
2966 {
2967         struct net_device *ndev = platform_get_drvdata(pdev);
2968         struct sh_eth_private *mdp = netdev_priv(ndev);
2969
2970         sh_mdio_release(ndev);
2971         unregister_netdev(ndev);
2972         netif_napi_del(&mdp->napi);
2973         pm_runtime_disable(&pdev->dev);
2974         free_netdev(ndev);
2975
2976         return 0;
2977 }
2978
2979 #ifdef CONFIG_PM
2980 static int sh_eth_runtime_nop(struct device *dev)
2981 {
2982         /* Runtime PM callback shared between ->runtime_suspend()
2983          * and ->runtime_resume(). Simply returns success.
2984          *
2985          * This driver re-initializes all registers after
2986          * pm_runtime_get_sync() anyway so there is no need
2987          * to save and restore registers here.
2988          */
2989         return 0;
2990 }
2991
2992 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2993         .runtime_suspend = sh_eth_runtime_nop,
2994         .runtime_resume = sh_eth_runtime_nop,
2995 };
2996 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2997 #else
2998 #define SH_ETH_PM_OPS NULL
2999 #endif
3000
3001 static struct platform_device_id sh_eth_id_table[] = {
3002         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3003         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3004         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3005         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3006         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3007         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3008         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3009         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3010         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3011         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3012         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3013         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3014         { }
3015 };
3016 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3017
3018 static struct platform_driver sh_eth_driver = {
3019         .probe = sh_eth_drv_probe,
3020         .remove = sh_eth_drv_remove,
3021         .id_table = sh_eth_id_table,
3022         .driver = {
3023                    .name = CARDNAME,
3024                    .pm = SH_ETH_PM_OPS,
3025                    .of_match_table = of_match_ptr(sh_eth_match_table),
3026         },
3027 };
3028
3029 module_platform_driver(sh_eth_driver);
3030
3031 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3032 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3033 MODULE_LICENSE("GPL v2");