drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   5  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   6  *  Copyright (C) 2014 Codethink Limited
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *
  17  *  The full GNU General Public License is included in this distribution in
  18  *  the file called "COPYING".
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/delay.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mdio-bitbang.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/of_net.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44 #include <linux/of_mdio.h>
  45
  46 #include "sh_eth.h"
  47
  48 #define SH_ETH_DEF_MSG_ENABLE \
  49                 (NETIF_MSG_LINK | \
  50                 NETIF_MSG_TIMER | \
  51                 NETIF_MSG_RX_ERR| \
  52                 NETIF_MSG_TX_ERR)
  53
  54 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  55         [EDSR]          = 0x0000,
  56         [EDMR]          = 0x0400,
  57         [EDTRR]         = 0x0408,
  58         [EDRRR]         = 0x0410,
  59         [EESR]          = 0x0428,
  60         [EESIPR]        = 0x0430,
  61         [TDLAR]         = 0x0010,
  62         [TDFAR]         = 0x0014,
  63         [TDFXR]         = 0x0018,
  64         [TDFFR]         = 0x001c,
  65         [RDLAR]         = 0x0030,
  66         [RDFAR]         = 0x0034,
  67         [RDFXR]         = 0x0038,
  68         [RDFFR]         = 0x003c,
  69         [TRSCER]        = 0x0438,
  70         [RMFCR]         = 0x0440,
  71         [TFTR]          = 0x0448,
  72         [FDR]           = 0x0450,
  73         [RMCR]          = 0x0458,
  74         [RPADIR]        = 0x0460,
  75         [FCFTR]         = 0x0468,
  76         [CSMR]          = 0x04E4,
  77
  78         [ECMR]          = 0x0500,
  79         [ECSR]          = 0x0510,
  80         [ECSIPR]        = 0x0518,
  81         [PIR]           = 0x0520,
  82         [PSR]           = 0x0528,
  83         [PIPR]          = 0x052c,
  84         [RFLR]          = 0x0508,
  85         [APR]           = 0x0554,
  86         [MPR]           = 0x0558,
  87         [PFTCR]         = 0x055c,
  88         [PFRCR]         = 0x0560,
  89         [TPAUSER]       = 0x0564,
  90         [GECMR]         = 0x05b0,
  91         [BCULR]         = 0x05b4,
  92         [MAHR]          = 0x05c0,
  93         [MALR]          = 0x05c8,
  94         [TROCR]         = 0x0700,
  95         [CDCR]          = 0x0708,
  96         [LCCR]          = 0x0710,
  97         [CEFCR]         = 0x0740,
  98         [FRECR]         = 0x0748,
  99         [TSFRCR]        = 0x0750,
 100         [TLFRCR]        = 0x0758,
 101         [RFCR]          = 0x0760,
 102         [CERCR]         = 0x0768,
 103         [CEECR]         = 0x0770,
 104         [MAFCR]         = 0x0778,
 105         [RMII_MII]      = 0x0790,
 106
 107         [ARSTR]         = 0x0000,
 108         [TSU_CTRST]     = 0x0004,
 109         [TSU_FWEN0]     = 0x0010,
 110         [TSU_FWEN1]     = 0x0014,
 111         [TSU_FCM]       = 0x0018,
 112         [TSU_BSYSL0]    = 0x0020,
 113         [TSU_BSYSL1]    = 0x0024,
 114         [TSU_PRISL0]    = 0x0028,
 115         [TSU_PRISL1]    = 0x002c,
 116         [TSU_FWSL0]     = 0x0030,
 117         [TSU_FWSL1]     = 0x0034,
 118         [TSU_FWSLC]     = 0x0038,
 119         [TSU_QTAG0]     = 0x0040,
 120         [TSU_QTAG1]     = 0x0044,
 121         [TSU_FWSR]      = 0x0050,
 122         [TSU_FWINMK]    = 0x0054,
 123         [TSU_ADQT0]     = 0x0048,
 124         [TSU_ADQT1]     = 0x004c,
 125         [TSU_VTAG0]     = 0x0058,
 126         [TSU_VTAG1]     = 0x005c,
 127         [TSU_ADSBSY]    = 0x0060,
 128         [TSU_TEN]       = 0x0064,
 129         [TSU_POST1]     = 0x0070,
 130         [TSU_POST2]     = 0x0074,
 131         [TSU_POST3]     = 0x0078,
 132         [TSU_POST4]     = 0x007c,
 133         [TSU_ADRH0]     = 0x0100,
 134         [TSU_ADRL0]     = 0x0104,
 135         [TSU_ADRH31]    = 0x01f8,
 136         [TSU_ADRL31]    = 0x01fc,
 137
 138         [TXNLCR0]       = 0x0080,
 139         [TXALCR0]       = 0x0084,
 140         [RXNLCR0]       = 0x0088,
 141         [RXALCR0]       = 0x008c,
 142         [FWNLCR0]       = 0x0090,
 143         [FWALCR0]       = 0x0094,
 144         [TXNLCR1]       = 0x00a0,
 145         [TXALCR1]       = 0x00a0,
 146         [RXNLCR1]       = 0x00a8,
 147         [RXALCR1]       = 0x00ac,
 148         [FWNLCR1]       = 0x00b0,
 149         [FWALCR1]       = 0x00b4,
 150 };
 151
 152 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 153         [EDSR]          = 0x0000,
 154         [EDMR]          = 0x0400,
 155         [EDTRR]         = 0x0408,
 156         [EDRRR]         = 0x0410,
 157         [EESR]          = 0x0428,
 158         [EESIPR]        = 0x0430,
 159         [TDLAR]         = 0x0010,
 160         [TDFAR]         = 0x0014,
 161         [TDFXR]         = 0x0018,
 162         [TDFFR]         = 0x001c,
 163         [RDLAR]         = 0x0030,
 164         [RDFAR]         = 0x0034,
 165         [RDFXR]         = 0x0038,
 166         [RDFFR]         = 0x003c,
 167         [TRSCER]        = 0x0438,
 168         [RMFCR]         = 0x0440,
 169         [TFTR]          = 0x0448,
 170         [FDR]           = 0x0450,
 171         [RMCR]          = 0x0458,
 172         [RPADIR]        = 0x0460,
 173         [FCFTR]         = 0x0468,
 174         [CSMR]          = 0x04E4,
 175
 176         [ECMR]          = 0x0500,
 177         [RFLR]          = 0x0508,
 178         [ECSR]          = 0x0510,
 179         [ECSIPR]        = 0x0518,
 180         [PIR]           = 0x0520,
 181         [APR]           = 0x0554,
 182         [MPR]           = 0x0558,
 183         [PFTCR]         = 0x055c,
 184         [PFRCR]         = 0x0560,
 185         [TPAUSER]       = 0x0564,
 186         [MAHR]          = 0x05c0,
 187         [MALR]          = 0x05c8,
 188         [CEFCR]         = 0x0740,
 189         [FRECR]         = 0x0748,
 190         [TSFRCR]        = 0x0750,
 191         [TLFRCR]        = 0x0758,
 192         [RFCR]          = 0x0760,
 193         [MAFCR]         = 0x0778,
 194
 195         [ARSTR]         = 0x0000,
 196         [TSU_CTRST]     = 0x0004,
 197         [TSU_VTAG0]     = 0x0058,
 198         [TSU_ADSBSY]    = 0x0060,
 199         [TSU_TEN]       = 0x0064,
 200         [TSU_ADRH0]     = 0x0100,
 201         [TSU_ADRL0]     = 0x0104,
 202         [TSU_ADRH31]    = 0x01f8,
 203         [TSU_ADRL31]    = 0x01fc,
 204
 205         [TXNLCR0]       = 0x0080,
 206         [TXALCR0]       = 0x0084,
 207         [RXNLCR0]       = 0x0088,
 208         [RXALCR0]       = 0x008C,
 209 };
 210
 211 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 212         [ECMR]          = 0x0300,
 213         [RFLR]          = 0x0308,
 214         [ECSR]          = 0x0310,
 215         [ECSIPR]        = 0x0318,
 216         [PIR]           = 0x0320,
 217         [PSR]           = 0x0328,
 218         [RDMLR]         = 0x0340,
 219         [IPGR]          = 0x0350,
 220         [APR]           = 0x0354,
 221         [MPR]           = 0x0358,
 222         [RFCF]          = 0x0360,
 223         [TPAUSER]       = 0x0364,
 224         [TPAUSECR]      = 0x0368,
 225         [MAHR]          = 0x03c0,
 226         [MALR]          = 0x03c8,
 227         [TROCR]         = 0x03d0,
 228         [CDCR]          = 0x03d4,
 229         [LCCR]          = 0x03d8,
 230         [CNDCR]         = 0x03dc,
 231         [CEFCR]         = 0x03e4,
 232         [FRECR]         = 0x03e8,
 233         [TSFRCR]        = 0x03ec,
 234         [TLFRCR]        = 0x03f0,
 235         [RFCR]          = 0x03f4,
 236         [MAFCR]         = 0x03f8,
 237
 238         [EDMR]          = 0x0200,
 239         [EDTRR]         = 0x0208,
 240         [EDRRR]         = 0x0210,
 241         [TDLAR]         = 0x0218,
 242         [RDLAR]         = 0x0220,
 243         [EESR]          = 0x0228,
 244         [EESIPR]        = 0x0230,
 245         [TRSCER]        = 0x0238,
 246         [RMFCR]         = 0x0240,
 247         [TFTR]          = 0x0248,
 248         [FDR]           = 0x0250,
 249         [RMCR]          = 0x0258,
 250         [TFUCR]         = 0x0264,
 251         [RFOCR]         = 0x0268,
 252         [RMIIMODE]      = 0x026c,
 253         [FCFTR]         = 0x0270,
 254         [TRIMD]         = 0x027c,
 255 };
 256
 257 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 258         [ECMR]          = 0x0100,
 259         [RFLR]          = 0x0108,
 260         [ECSR]          = 0x0110,
 261         [ECSIPR]        = 0x0118,
 262         [PIR]           = 0x0120,
 263         [PSR]           = 0x0128,
 264         [RDMLR]         = 0x0140,
 265         [IPGR]          = 0x0150,
 266         [APR]           = 0x0154,
 267         [MPR]           = 0x0158,
 268         [TPAUSER]       = 0x0164,
 269         [RFCF]          = 0x0160,
 270         [TPAUSECR]      = 0x0168,
 271         [BCFRR]         = 0x016c,
 272         [MAHR]          = 0x01c0,
 273         [MALR]          = 0x01c8,
 274         [TROCR]         = 0x01d0,
 275         [CDCR]          = 0x01d4,
 276         [LCCR]          = 0x01d8,
 277         [CNDCR]         = 0x01dc,
 278         [CEFCR]         = 0x01e4,
 279         [FRECR]         = 0x01e8,
 280         [TSFRCR]        = 0x01ec,
 281         [TLFRCR]        = 0x01f0,
 282         [RFCR]          = 0x01f4,
 283         [MAFCR]         = 0x01f8,
 284         [RTRATE]        = 0x01fc,
 285
 286         [EDMR]          = 0x0000,
 287         [EDTRR]         = 0x0008,
 288         [EDRRR]         = 0x0010,
 289         [TDLAR]         = 0x0018,
 290         [RDLAR]         = 0x0020,
 291         [EESR]          = 0x0028,
 292         [EESIPR]        = 0x0030,
 293         [TRSCER]        = 0x0038,
 294         [RMFCR]         = 0x0040,
 295         [TFTR]          = 0x0048,
 296         [FDR]           = 0x0050,
 297         [RMCR]          = 0x0058,
 298         [TFUCR]         = 0x0064,
 299         [RFOCR]         = 0x0068,
 300         [FCFTR]         = 0x0070,
 301         [RPADIR]        = 0x0078,
 302         [TRIMD]         = 0x007c,
 303         [RBWAR]         = 0x00c8,
 304         [RDFAR]         = 0x00cc,
 305         [TBRAR]         = 0x00d4,
 306         [TDFAR]         = 0x00d8,
 307 };
 308
 309 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 310         [EDMR]          = 0x0000,
 311         [EDTRR]         = 0x0004,
 312         [EDRRR]         = 0x0008,
 313         [TDLAR]         = 0x000c,
 314         [RDLAR]         = 0x0010,
 315         [EESR]          = 0x0014,
 316         [EESIPR]        = 0x0018,
 317         [TRSCER]        = 0x001c,
 318         [RMFCR]         = 0x0020,
 319         [TFTR]          = 0x0024,
 320         [FDR]           = 0x0028,
 321         [RMCR]          = 0x002c,
 322         [EDOCR]         = 0x0030,
 323         [FCFTR]         = 0x0034,
 324         [RPADIR]        = 0x0038,
 325         [TRIMD]         = 0x003c,
 326         [RBWAR]         = 0x0040,
 327         [RDFAR]         = 0x0044,
 328         [TBRAR]         = 0x004c,
 329         [TDFAR]         = 0x0050,
 330
 331         [ECMR]          = 0x0160,
 332         [ECSR]          = 0x0164,
 333         [ECSIPR]        = 0x0168,
 334         [PIR]           = 0x016c,
 335         [MAHR]          = 0x0170,
 336         [MALR]          = 0x0174,
 337         [RFLR]          = 0x0178,
 338         [PSR]           = 0x017c,
 339         [TROCR]         = 0x0180,
 340         [CDCR]          = 0x0184,
 341         [LCCR]          = 0x0188,
 342         [CNDCR]         = 0x018c,
 343         [CEFCR]         = 0x0194,
 344         [FRECR]         = 0x0198,
 345         [TSFRCR]        = 0x019c,
 346         [TLFRCR]        = 0x01a0,
 347         [RFCR]          = 0x01a4,
 348         [MAFCR]         = 0x01a8,
 349         [IPGR]          = 0x01b4,
 350         [APR]           = 0x01b8,
 351         [MPR]           = 0x01bc,
 352         [TPAUSER]       = 0x01c4,
 353         [BCFR]          = 0x01cc,
 354
 355         [ARSTR]         = 0x0000,
 356         [TSU_CTRST]     = 0x0004,
 357         [TSU_FWEN0]     = 0x0010,
 358         [TSU_FWEN1]     = 0x0014,
 359         [TSU_FCM]       = 0x0018,
 360         [TSU_BSYSL0]    = 0x0020,
 361         [TSU_BSYSL1]    = 0x0024,
 362         [TSU_PRISL0]    = 0x0028,
 363         [TSU_PRISL1]    = 0x002c,
 364         [TSU_FWSL0]     = 0x0030,
 365         [TSU_FWSL1]     = 0x0034,
 366         [TSU_FWSLC]     = 0x0038,
 367         [TSU_QTAGM0]    = 0x0040,
 368         [TSU_QTAGM1]    = 0x0044,
 369         [TSU_ADQT0]     = 0x0048,
 370         [TSU_ADQT1]     = 0x004c,
 371         [TSU_FWSR]      = 0x0050,
 372         [TSU_FWINMK]    = 0x0054,
 373         [TSU_ADSBSY]    = 0x0060,
 374         [TSU_TEN]       = 0x0064,
 375         [TSU_POST1]     = 0x0070,
 376         [TSU_POST2]     = 0x0074,
 377         [TSU_POST3]     = 0x0078,
 378         [TSU_POST4]     = 0x007c,
 379
 380         [TXNLCR0]       = 0x0080,
 381         [TXALCR0]       = 0x0084,
 382         [RXNLCR0]       = 0x0088,
 383         [RXALCR0]       = 0x008c,
 384         [FWNLCR0]       = 0x0090,
 385         [FWALCR0]       = 0x0094,
 386         [TXNLCR1]       = 0x00a0,
 387         [TXALCR1]       = 0x00a0,
 388         [RXNLCR1]       = 0x00a8,
 389         [RXALCR1]       = 0x00ac,
 390         [FWNLCR1]       = 0x00b0,
 391         [FWALCR1]       = 0x00b4,
 392
 393         [TSU_ADRH0]     = 0x0100,
 394         [TSU_ADRL0]     = 0x0104,
 395         [TSU_ADRL31]    = 0x01fc,
 396 };
 397
 398 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 399 {
 400         return mdp->reg_offset == sh_eth_offset_gigabit;
 401 }
 402
 403 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 404 {
 405         return mdp->reg_offset == sh_eth_offset_fast_rz;
 406 }
 407
 408 static void sh_eth_select_mii(struct net_device *ndev)
 409 {
 410         u32 value = 0x0;
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412
 413         switch (mdp->phy_interface) {
 414         case PHY_INTERFACE_MODE_GMII:
 415                 value = 0x2;
 416                 break;
 417         case PHY_INTERFACE_MODE_MII:
 418                 value = 0x1;
 419                 break;
 420         case PHY_INTERFACE_MODE_RMII:
 421                 value = 0x0;
 422                 break;
 423         default:
 424                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 425                 value = 0x1;
 426                 break;
 427         }
 428
 429         sh_eth_write(ndev, value, RMII_MII);
 430 }
 431
 432 static void sh_eth_set_duplex(struct net_device *ndev)
 433 {
 434         struct sh_eth_private *mdp = netdev_priv(ndev);
 435
 436         if (mdp->duplex) /* Full */
 437                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 438         else            /* Half */
 439                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 440 }
 441
 442 /* There is CPU dependent code */
 443 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 444 {
 445         struct sh_eth_private *mdp = netdev_priv(ndev);
 446
 447         switch (mdp->speed) {
 448         case 10: /* 10BASE */
 449                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 450                 break;
 451         case 100:/* 100BASE */
 452                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 453                 break;
 454         default:
 455                 break;
 456         }
 457 }
 458
 459 /* R8A7778/9 */
 460 static struct sh_eth_cpu_data r8a777x_data = {
 461         .set_duplex     = sh_eth_set_duplex,
 462         .set_rate       = sh_eth_set_rate_r8a777x,
 463
 464         .register_type  = SH_ETH_REG_FAST_RCAR,
 465
 466         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 467         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 468         .eesipr_value   = 0x01ff009f,
 469
 470         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 471         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 472                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 473                           EESR_ECI,
 474
 475         .apr            = 1,
 476         .mpr            = 1,
 477         .tpauser        = 1,
 478         .hw_swap        = 1,
 479 };
 480
 481 /* R8A7790/1 */
 482 static struct sh_eth_cpu_data r8a779x_data = {
 483         .set_duplex     = sh_eth_set_duplex,
 484         .set_rate       = sh_eth_set_rate_r8a777x,
 485
 486         .register_type  = SH_ETH_REG_FAST_RCAR,
 487
 488         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 489         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 490         .eesipr_value   = 0x01ff009f,
 491
 492         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 493         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 494                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 495                           EESR_ECI,
 496
 497         .apr            = 1,
 498         .mpr            = 1,
 499         .tpauser        = 1,
 500         .hw_swap        = 1,
 501         .rmiimode       = 1,
 502         .shift_rd0      = 1,
 503 };
 504
 505 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 506 {
 507         struct sh_eth_private *mdp = netdev_priv(ndev);
 508
 509         switch (mdp->speed) {
 510         case 10: /* 10BASE */
 511                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 512                 break;
 513         case 100:/* 100BASE */
 514                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 515                 break;
 516         default:
 517                 break;
 518         }
 519 }
 520
 521 /* SH7724 */
 522 static struct sh_eth_cpu_data sh7724_data = {
 523         .set_duplex     = sh_eth_set_duplex,
 524         .set_rate       = sh_eth_set_rate_sh7724,
 525
 526         .register_type  = SH_ETH_REG_FAST_SH4,
 527
 528         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 529         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 530         .eesipr_value   = 0x01ff009f,
 531
 532         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 533         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 534                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 535                           EESR_ECI,
 536
 537         .apr            = 1,
 538         .mpr            = 1,
 539         .tpauser        = 1,
 540         .hw_swap        = 1,
 541         .rpadir         = 1,
 542         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 543 };
 544
 545 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 546 {
 547         struct sh_eth_private *mdp = netdev_priv(ndev);
 548
 549         switch (mdp->speed) {
 550         case 10: /* 10BASE */
 551                 sh_eth_write(ndev, 0, RTRATE);
 552                 break;
 553         case 100:/* 100BASE */
 554                 sh_eth_write(ndev, 1, RTRATE);
 555                 break;
 556         default:
 557                 break;
 558         }
 559 }
 560
 561 /* SH7757 */
 562 static struct sh_eth_cpu_data sh7757_data = {
 563         .set_duplex     = sh_eth_set_duplex,
 564         .set_rate       = sh_eth_set_rate_sh7757,
 565
 566         .register_type  = SH_ETH_REG_FAST_SH4,
 567
 568         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 569
 570         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 571         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 572                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 573                           EESR_ECI,
 574
 575         .irq_flags      = IRQF_SHARED,
 576         .apr            = 1,
 577         .mpr            = 1,
 578         .tpauser        = 1,
 579         .hw_swap        = 1,
 580         .no_ade         = 1,
 581         .rpadir         = 1,
 582         .rpadir_value   = 2 << 16,
 583 };
 584
 585 #define SH_GIGA_ETH_BASE        0xfee00000UL
 586 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 587 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 588 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 589 {
 590         int i;
 591         unsigned long mahr[2], malr[2];
 592
 593         /* save MAHR and MALR */
 594         for (i = 0; i < 2; i++) {
 595                 malr[i] = ioread32((void *)GIGA_MALR(i));
 596                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 597         }
 598
 599         /* reset device */
 600         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 601         mdelay(1);
 602
 603         /* restore MAHR and MALR */
 604         for (i = 0; i < 2; i++) {
 605                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 606                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 607         }
 608 }
 609
 610 static void sh_eth_set_rate_giga(struct net_device *ndev)
 611 {
 612         struct sh_eth_private *mdp = netdev_priv(ndev);
 613
 614         switch (mdp->speed) {
 615         case 10: /* 10BASE */
 616                 sh_eth_write(ndev, 0x00000000, GECMR);
 617                 break;
 618         case 100:/* 100BASE */
 619                 sh_eth_write(ndev, 0x00000010, GECMR);
 620                 break;
 621         case 1000: /* 1000BASE */
 622                 sh_eth_write(ndev, 0x00000020, GECMR);
 623                 break;
 624         default:
 625                 break;
 626         }
 627 }
 628
 629 /* SH7757(GETHERC) */
 630 static struct sh_eth_cpu_data sh7757_data_giga = {
 631         .chip_reset     = sh_eth_chip_reset_giga,
 632         .set_duplex     = sh_eth_set_duplex,
 633         .set_rate       = sh_eth_set_rate_giga,
 634
 635         .register_type  = SH_ETH_REG_GIGABIT,
 636
 637         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 638         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 639         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 640
 641         .tx_check       = EESR_TC1 | EESR_FTC,
 642         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 643                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 644                           EESR_TDE | EESR_ECI,
 645         .fdr_value      = 0x0000072f,
 646
 647         .irq_flags      = IRQF_SHARED,
 648         .apr            = 1,
 649         .mpr            = 1,
 650         .tpauser        = 1,
 651         .bculr          = 1,
 652         .hw_swap        = 1,
 653         .rpadir         = 1,
 654         .rpadir_value   = 2 << 16,
 655         .no_trimd       = 1,
 656         .no_ade         = 1,
 657         .tsu            = 1,
 658 };
 659
 660 static void sh_eth_chip_reset(struct net_device *ndev)
 661 {
 662         struct sh_eth_private *mdp = netdev_priv(ndev);
 663
 664         /* reset device */
 665         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 666         mdelay(1);
 667 }
 668
 669 static void sh_eth_set_rate_gether(struct net_device *ndev)
 670 {
 671         struct sh_eth_private *mdp = netdev_priv(ndev);
 672
 673         switch (mdp->speed) {
 674         case 10: /* 10BASE */
 675                 sh_eth_write(ndev, GECMR_10, GECMR);
 676                 break;
 677         case 100:/* 100BASE */
 678                 sh_eth_write(ndev, GECMR_100, GECMR);
 679                 break;
 680         case 1000: /* 1000BASE */
 681                 sh_eth_write(ndev, GECMR_1000, GECMR);
 682                 break;
 683         default:
 684                 break;
 685         }
 686 }
 687
 688 /* SH7734 */
 689 static struct sh_eth_cpu_data sh7734_data = {
 690         .chip_reset     = sh_eth_chip_reset,
 691         .set_duplex     = sh_eth_set_duplex,
 692         .set_rate       = sh_eth_set_rate_gether,
 693
 694         .register_type  = SH_ETH_REG_GIGABIT,
 695
 696         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 697         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 698         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 699
 700         .tx_check       = EESR_TC1 | EESR_FTC,
 701         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 702                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 703                           EESR_TDE | EESR_ECI,
 704
 705         .apr            = 1,
 706         .mpr            = 1,
 707         .tpauser        = 1,
 708         .bculr          = 1,
 709         .hw_swap        = 1,
 710         .no_trimd       = 1,
 711         .no_ade         = 1,
 712         .tsu            = 1,
 713         .hw_crc         = 1,
 714         .select_mii     = 1,
 715 };
 716
 717 /* SH7763 */
 718 static struct sh_eth_cpu_data sh7763_data = {
 719         .chip_reset     = sh_eth_chip_reset,
 720         .set_duplex     = sh_eth_set_duplex,
 721         .set_rate       = sh_eth_set_rate_gether,
 722
 723         .register_type  = SH_ETH_REG_GIGABIT,
 724
 725         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 726         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 727         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 728
 729         .tx_check       = EESR_TC1 | EESR_FTC,
 730         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 731                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 732                           EESR_ECI,
 733
 734         .apr            = 1,
 735         .mpr            = 1,
 736         .tpauser        = 1,
 737         .bculr          = 1,
 738         .hw_swap        = 1,
 739         .no_trimd       = 1,
 740         .no_ade         = 1,
 741         .tsu            = 1,
 742         .irq_flags      = IRQF_SHARED,
 743 };
 744
 745 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 746 {
 747         struct sh_eth_private *mdp = netdev_priv(ndev);
 748
 749         /* reset device */
 750         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 751         mdelay(1);
 752
 753         sh_eth_select_mii(ndev);
 754 }
 755
 756 /* R8A7740 */
 757 static struct sh_eth_cpu_data r8a7740_data = {
 758         .chip_reset     = sh_eth_chip_reset_r8a7740,
 759         .set_duplex     = sh_eth_set_duplex,
 760         .set_rate       = sh_eth_set_rate_gether,
 761
 762         .register_type  = SH_ETH_REG_GIGABIT,
 763
 764         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 765         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 766         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 767
 768         .tx_check       = EESR_TC1 | EESR_FTC,
 769         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 770                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 771                           EESR_TDE | EESR_ECI,
 772         .fdr_value      = 0x0000070f,
 773
 774         .apr            = 1,
 775         .mpr            = 1,
 776         .tpauser        = 1,
 777         .bculr          = 1,
 778         .hw_swap        = 1,
 779         .rpadir         = 1,
 780         .rpadir_value   = 2 << 16,
 781         .no_trimd       = 1,
 782         .no_ade         = 1,
 783         .tsu            = 1,
 784         .select_mii     = 1,
 785         .shift_rd0      = 1,
 786 };
 787
 788 /* R7S72100 */
 789 static struct sh_eth_cpu_data r7s72100_data = {
 790         .chip_reset     = sh_eth_chip_reset,
 791         .set_duplex     = sh_eth_set_duplex,
 792
 793         .register_type  = SH_ETH_REG_FAST_RZ,
 794
 795         .ecsr_value     = ECSR_ICD,
 796         .ecsipr_value   = ECSIPR_ICDIP,
 797         .eesipr_value   = 0xff7f009f,
 798
 799         .tx_check       = EESR_TC1 | EESR_FTC,
 800         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 801                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 802                           EESR_TDE | EESR_ECI,
 803         .fdr_value      = 0x0000070f,
 804
 805         .no_psr         = 1,
 806         .apr            = 1,
 807         .mpr            = 1,
 808         .tpauser        = 1,
 809         .hw_swap        = 1,
 810         .rpadir         = 1,
 811         .rpadir_value   = 2 << 16,
 812         .no_trimd       = 1,
 813         .no_ade         = 1,
 814         .hw_crc         = 1,
 815         .tsu            = 1,
 816         .shift_rd0      = 1,
 817 };
 818
 819 static struct sh_eth_cpu_data sh7619_data = {
 820         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 821
 822         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 823
 824         .apr            = 1,
 825         .mpr            = 1,
 826         .tpauser        = 1,
 827         .hw_swap        = 1,
 828 };
 829
 830 static struct sh_eth_cpu_data sh771x_data = {
 831         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 832
 833         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 834         .tsu            = 1,
 835 };
 836
 837 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 838 {
 839         if (!cd->ecsr_value)
 840                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 841
 842         if (!cd->ecsipr_value)
 843                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 844
 845         if (!cd->fcftr_value)
 846                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 847                                   DEFAULT_FIFO_F_D_RFD;
 848
 849         if (!cd->fdr_value)
 850                 cd->fdr_value = DEFAULT_FDR_INIT;
 851
 852         if (!cd->tx_check)
 853                 cd->tx_check = DEFAULT_TX_CHECK;
 854
 855         if (!cd->eesr_err_check)
 856                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 857 }
 858
 859 static int sh_eth_check_reset(struct net_device *ndev)
 860 {
 861         int ret = 0;
 862         int cnt = 100;
 863
 864         while (cnt > 0) {
 865                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 866                         break;
 867                 mdelay(1);
 868                 cnt--;
 869         }
 870         if (cnt <= 0) {
 871                 pr_err("Device reset failed\n");
 872                 ret = -ETIMEDOUT;
 873         }
 874         return ret;
 875 }
 876
 877 static int sh_eth_reset(struct net_device *ndev)
 878 {
 879         struct sh_eth_private *mdp = netdev_priv(ndev);
 880         int ret = 0;
 881
 882         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 883                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 884                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 885                              EDMR);
 886
 887                 ret = sh_eth_check_reset(ndev);
 888                 if (ret)
 889                         goto out;
 890
 891                 /* Table Init */
 892                 sh_eth_write(ndev, 0x0, TDLAR);
 893                 sh_eth_write(ndev, 0x0, TDFAR);
 894                 sh_eth_write(ndev, 0x0, TDFXR);
 895                 sh_eth_write(ndev, 0x0, TDFFR);
 896                 sh_eth_write(ndev, 0x0, RDLAR);
 897                 sh_eth_write(ndev, 0x0, RDFAR);
 898                 sh_eth_write(ndev, 0x0, RDFXR);
 899                 sh_eth_write(ndev, 0x0, RDFFR);
 900
 901                 /* Reset HW CRC register */
 902                 if (mdp->cd->hw_crc)
 903                         sh_eth_write(ndev, 0x0, CSMR);
 904
 905                 /* Select MII mode */
 906                 if (mdp->cd->select_mii)
 907                         sh_eth_select_mii(ndev);
 908         } else {
 909                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 910                              EDMR);
 911                 mdelay(3);
 912                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 913                              EDMR);
 914         }
 915
 916 out:
 917         return ret;
 918 }
 919
 920 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 921 static void sh_eth_set_receive_align(struct sk_buff *skb)
 922 {
 923         int reserve;
 924
 925         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 926         if (reserve)
 927                 skb_reserve(skb, reserve);
 928 }
 929 #else
 930 static void sh_eth_set_receive_align(struct sk_buff *skb)
 931 {
 932         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 933 }
 934 #endif
 935
 936
 937 /* CPU <-> EDMAC endian convert */
 938 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 939 {
 940         switch (mdp->edmac_endian) {
 941         case EDMAC_LITTLE_ENDIAN:
 942                 return cpu_to_le32(x);
 943         case EDMAC_BIG_ENDIAN:
 944                 return cpu_to_be32(x);
 945         }
 946         return x;
 947 }
 948
 949 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 950 {
 951         switch (mdp->edmac_endian) {
 952         case EDMAC_LITTLE_ENDIAN:
 953                 return le32_to_cpu(x);
 954         case EDMAC_BIG_ENDIAN:
 955                 return be32_to_cpu(x);
 956         }
 957         return x;
 958 }
 959
 960 /* Program the hardware MAC address from dev->dev_addr. */
 961 static void update_mac_address(struct net_device *ndev)
 962 {
 963         sh_eth_write(ndev,
 964                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 965                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 966         sh_eth_write(ndev,
 967                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 968 }
 969
 970 /* Get MAC address from SuperH MAC address register
 971  *
 972  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 973  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 974  * When you want use this device, you must set MAC address in bootloader.
 975  *
 976  */
 977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 978 {
 979         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 980                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 981         } else {
 982                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 983                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 984                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 985                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 986                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 987                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 988         }
 989 }
 990
 991 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 992 {
 993         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 994                 return EDTRR_TRNS_GETHER;
 995         else
 996                 return EDTRR_TRNS_ETHER;
 997 }
 998
 999 struct bb_info {
1000         void (*set_gate)(void *addr);
1001         struct mdiobb_ctrl ctrl;
1002         void *addr;
1003         u32 mmd_msk;/* MMD */
1004         u32 mdo_msk;
1005         u32 mdi_msk;
1006         u32 mdc_msk;
1007 };
1008
1009 /* PHY bit set */
1010 static void bb_set(void *addr, u32 msk)
1011 {
1012         iowrite32(ioread32(addr) | msk, addr);
1013 }
1014
1015 /* PHY bit clear */
1016 static void bb_clr(void *addr, u32 msk)
1017 {
1018         iowrite32((ioread32(addr) & ~msk), addr);
1019 }
1020
1021 /* PHY bit read */
1022 static int bb_read(void *addr, u32 msk)
1023 {
1024         return (ioread32(addr) & msk) != 0;
1025 }
1026
1027 /* Data I/O pin control */
1028 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1029 {
1030         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1031
1032         if (bitbang->set_gate)
1033                 bitbang->set_gate(bitbang->addr);
1034
1035         if (bit)
1036                 bb_set(bitbang->addr, bitbang->mmd_msk);
1037         else
1038                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1039 }
1040
1041 /* Set bit data*/
1042 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1043 {
1044         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1045
1046         if (bitbang->set_gate)
1047                 bitbang->set_gate(bitbang->addr);
1048
1049         if (bit)
1050                 bb_set(bitbang->addr, bitbang->mdo_msk);
1051         else
1052                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1053 }
1054
1055 /* Get bit data*/
1056 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1057 {
1058         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1059
1060         if (bitbang->set_gate)
1061                 bitbang->set_gate(bitbang->addr);
1062
1063         return bb_read(bitbang->addr, bitbang->mdi_msk);
1064 }
1065
1066 /* MDC pin control */
1067 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1068 {
1069         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1070
1071         if (bitbang->set_gate)
1072                 bitbang->set_gate(bitbang->addr);
1073
1074         if (bit)
1075                 bb_set(bitbang->addr, bitbang->mdc_msk);
1076         else
1077                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1078 }
1079
1080 /* mdio bus control struct */
1081 static struct mdiobb_ops bb_ops = {
1082         .owner = THIS_MODULE,
1083         .set_mdc = sh_mdc_ctrl,
1084         .set_mdio_dir = sh_mmd_ctrl,
1085         .set_mdio_data = sh_set_mdio,
1086         .get_mdio_data = sh_get_mdio,
1087 };
1088
1089 /* free skb and descriptor buffer */
1090 static void sh_eth_ring_free(struct net_device *ndev)
1091 {
1092         struct sh_eth_private *mdp = netdev_priv(ndev);
1093         int i;
1094
1095         /* Free Rx skb ringbuffer */
1096         if (mdp->rx_skbuff) {
1097                 for (i = 0; i < mdp->num_rx_ring; i++) {
1098                         if (mdp->rx_skbuff[i])
1099                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1100                 }
1101         }
1102         kfree(mdp->rx_skbuff);
1103         mdp->rx_skbuff = NULL;
1104
1105         /* Free Tx skb ringbuffer */
1106         if (mdp->tx_skbuff) {
1107                 for (i = 0; i < mdp->num_tx_ring; i++) {
1108                         if (mdp->tx_skbuff[i])
1109                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1110                 }
1111         }
1112         kfree(mdp->tx_skbuff);
1113         mdp->tx_skbuff = NULL;
1114 }
1115
1116 /* format skb and descriptor buffer */
1117 static void sh_eth_ring_format(struct net_device *ndev)
1118 {
1119         struct sh_eth_private *mdp = netdev_priv(ndev);
1120         int i;
1121         struct sk_buff *skb;
1122         struct sh_eth_rxdesc *rxdesc = NULL;
1123         struct sh_eth_txdesc *txdesc = NULL;
1124         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1125         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1126
1127         mdp->cur_rx = 0;
1128         mdp->cur_tx = 0;
1129         mdp->dirty_rx = 0;
1130         mdp->dirty_tx = 0;
1131
1132         memset(mdp->rx_ring, 0, rx_ringsize);
1133
1134         /* build Rx ring buffer */
1135         for (i = 0; i < mdp->num_rx_ring; i++) {
1136                 /* skb */
1137                 mdp->rx_skbuff[i] = NULL;
1138                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1139                 mdp->rx_skbuff[i] = skb;
1140                 if (skb == NULL)
1141                         break;
1142                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1143                                DMA_FROM_DEVICE);
1144                 sh_eth_set_receive_align(skb);
1145
1146                 /* RX descriptor */
1147                 rxdesc = &mdp->rx_ring[i];
1148                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1149                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1150
1151                 /* The size of the buffer is 16 byte boundary. */
1152                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1153                 /* Rx descriptor address set */
1154                 if (i == 0) {
1155                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1156                         if (sh_eth_is_gether(mdp) ||
1157                             sh_eth_is_rz_fast_ether(mdp))
1158                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1159                 }
1160         }
1161
1162         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1163
1164         /* Mark the last entry as wrapping the ring. */
1165         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1166
1167         memset(mdp->tx_ring, 0, tx_ringsize);
1168
1169         /* build Tx ring buffer */
1170         for (i = 0; i < mdp->num_tx_ring; i++) {
1171                 mdp->tx_skbuff[i] = NULL;
1172                 txdesc = &mdp->tx_ring[i];
1173                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1174                 txdesc->buffer_length = 0;
1175                 if (i == 0) {
1176                         /* Tx descriptor address set */
1177                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1178                         if (sh_eth_is_gether(mdp) ||
1179                             sh_eth_is_rz_fast_ether(mdp))
1180                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1181                 }
1182         }
1183
1184         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1185 }
1186
1187 /* Get skb and descriptor buffer */
1188 static int sh_eth_ring_init(struct net_device *ndev)
1189 {
1190         struct sh_eth_private *mdp = netdev_priv(ndev);
1191         int rx_ringsize, tx_ringsize, ret = 0;
1192
1193         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1194          * card needs room to do 8 byte alignment, +2 so we can reserve
1195          * the first 2 bytes, and +16 gets room for the status word from the
1196          * card.
1197          */
1198         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1199                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1200         if (mdp->cd->rpadir)
1201                 mdp->rx_buf_sz += NET_IP_ALIGN;
1202
1203         /* Allocate RX and TX skb rings */
1204         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1205                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1206         if (!mdp->rx_skbuff) {
1207                 ret = -ENOMEM;
1208                 return ret;
1209         }
1210
1211         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1212                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1213         if (!mdp->tx_skbuff) {
1214                 ret = -ENOMEM;
1215                 goto skb_ring_free;
1216         }
1217
1218         /* Allocate all Rx descriptors. */
1219         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1220         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1221                                           GFP_KERNEL);
1222         if (!mdp->rx_ring) {
1223                 ret = -ENOMEM;
1224                 goto desc_ring_free;
1225         }
1226
1227         mdp->dirty_rx = 0;
1228
1229         /* Allocate all Tx descriptors. */
1230         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1231         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1232                                           GFP_KERNEL);
1233         if (!mdp->tx_ring) {
1234                 ret = -ENOMEM;
1235                 goto desc_ring_free;
1236         }
1237         return ret;
1238
1239 desc_ring_free:
1240         /* free DMA buffer */
1241         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1242
1243 skb_ring_free:
1244         /* Free Rx and Tx skb ring buffer */
1245         sh_eth_ring_free(ndev);
1246         mdp->tx_ring = NULL;
1247         mdp->rx_ring = NULL;
1248
1249         return ret;
1250 }
1251
1252 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1253 {
1254         int ringsize;
1255
1256         if (mdp->rx_ring) {
1257                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1258                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1259                                   mdp->rx_desc_dma);
1260                 mdp->rx_ring = NULL;
1261         }
1262
1263         if (mdp->tx_ring) {
1264                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1265                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1266                                   mdp->tx_desc_dma);
1267                 mdp->tx_ring = NULL;
1268         }
1269 }
1270
1271 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1272 {
1273         int ret = 0;
1274         struct sh_eth_private *mdp = netdev_priv(ndev);
1275         u32 val;
1276
1277         /* Soft Reset */
1278         ret = sh_eth_reset(ndev);
1279         if (ret)
1280                 goto out;
1281
1282         if (mdp->cd->rmiimode)
1283                 sh_eth_write(ndev, 0x1, RMIIMODE);
1284
1285         /* Descriptor format */
1286         sh_eth_ring_format(ndev);
1287         if (mdp->cd->rpadir)
1288                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1289
1290         /* all sh_eth int mask */
1291         sh_eth_write(ndev, 0, EESIPR);
1292
1293 #if defined(__LITTLE_ENDIAN)
1294         if (mdp->cd->hw_swap)
1295                 sh_eth_write(ndev, EDMR_EL, EDMR);
1296         else
1297 #endif
1298                 sh_eth_write(ndev, 0, EDMR);
1299
1300         /* FIFO size set */
1301         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1302         sh_eth_write(ndev, 0, TFTR);
1303
1304         /* Frame recv control (enable multiple-packets per rx irq) */
1305         sh_eth_write(ndev, RMCR_RNC, RMCR);
1306
1307         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1308
1309         if (mdp->cd->bculr)
1310                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1311
1312         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1313
1314         if (!mdp->cd->no_trimd)
1315                 sh_eth_write(ndev, 0, TRIMD);
1316
1317         /* Recv frame limit set register */
1318         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1319                      RFLR);
1320
1321         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1322         if (start)
1323                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1324
1325         /* PAUSE Prohibition */
1326         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1327                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1328
1329         sh_eth_write(ndev, val, ECMR);
1330
1331         if (mdp->cd->set_rate)
1332                 mdp->cd->set_rate(ndev);
1333
1334         /* E-MAC Status Register clear */
1335         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1336
1337         /* E-MAC Interrupt Enable register */
1338         if (start)
1339                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1340
1341         /* Set MAC address */
1342         update_mac_address(ndev);
1343
1344         /* mask reset */
1345         if (mdp->cd->apr)
1346                 sh_eth_write(ndev, APR_AP, APR);
1347         if (mdp->cd->mpr)
1348                 sh_eth_write(ndev, MPR_MP, MPR);
1349         if (mdp->cd->tpauser)
1350                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1351
1352         if (start) {
1353                 /* Setting the Rx mode will start the Rx process. */
1354                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1355
1356                 netif_start_queue(ndev);
1357         }
1358
1359 out:
1360         return ret;
1361 }
1362
1363 /* free Tx skb function */
1364 static int sh_eth_txfree(struct net_device *ndev)
1365 {
1366         struct sh_eth_private *mdp = netdev_priv(ndev);
1367         struct sh_eth_txdesc *txdesc;
1368         int free_num = 0;
1369         int entry = 0;
1370
1371         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1372                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1373                 txdesc = &mdp->tx_ring[entry];
1374                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1375                         break;
1376                 /* Free the original skb. */
1377                 if (mdp->tx_skbuff[entry]) {
1378                         dma_unmap_single(&ndev->dev, txdesc->addr,
1379                                          txdesc->buffer_length, DMA_TO_DEVICE);
1380                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1381                         mdp->tx_skbuff[entry] = NULL;
1382                         free_num++;
1383                 }
1384                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1385                 if (entry >= mdp->num_tx_ring - 1)
1386                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1387
1388                 ndev->stats.tx_packets++;
1389                 ndev->stats.tx_bytes += txdesc->buffer_length;
1390         }
1391         return free_num;
1392 }
1393
1394 /* Packet receive function */
1395 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1396 {
1397         struct sh_eth_private *mdp = netdev_priv(ndev);
1398         struct sh_eth_rxdesc *rxdesc;
1399
1400         int entry = mdp->cur_rx % mdp->num_rx_ring;
1401         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1402         struct sk_buff *skb;
1403         int exceeded = 0;
1404         u16 pkt_len = 0;
1405         u32 desc_status;
1406
1407         rxdesc = &mdp->rx_ring[entry];
1408         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1409                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1410                 pkt_len = rxdesc->frame_length;
1411
1412                 if (--boguscnt < 0)
1413                         break;
1414
1415                 if (*quota <= 0) {
1416                         exceeded = 1;
1417                         break;
1418                 }
1419                 (*quota)--;
1420
1421                 if (!(desc_status & RDFEND))
1422                         ndev->stats.rx_length_errors++;
1423
1424                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1425                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1426                  * bit 0. However, in case of the R8A7740, R8A779x, and
1427                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1428                  * driver needs right shifting by 16.
1429                  */
1430                 if (mdp->cd->shift_rd0)
1431                         desc_status >>= 16;
1432
1433                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1434                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1435                         ndev->stats.rx_errors++;
1436                         if (desc_status & RD_RFS1)
1437                                 ndev->stats.rx_crc_errors++;
1438                         if (desc_status & RD_RFS2)
1439                                 ndev->stats.rx_frame_errors++;
1440                         if (desc_status & RD_RFS3)
1441                                 ndev->stats.rx_length_errors++;
1442                         if (desc_status & RD_RFS4)
1443                                 ndev->stats.rx_length_errors++;
1444                         if (desc_status & RD_RFS6)
1445                                 ndev->stats.rx_missed_errors++;
1446                         if (desc_status & RD_RFS10)
1447                                 ndev->stats.rx_over_errors++;
1448                 } else {
1449                         if (!mdp->cd->hw_swap)
1450                                 sh_eth_soft_swap(
1451                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1452                                         pkt_len + 2);
1453                         skb = mdp->rx_skbuff[entry];
1454                         mdp->rx_skbuff[entry] = NULL;
1455                         if (mdp->cd->rpadir)
1456                                 skb_reserve(skb, NET_IP_ALIGN);
1457                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1458                                                 mdp->rx_buf_sz,
1459                                                 DMA_FROM_DEVICE);
1460                         skb_put(skb, pkt_len);
1461                         skb->protocol = eth_type_trans(skb, ndev);
1462                         netif_receive_skb(skb);
1463                         ndev->stats.rx_packets++;
1464                         ndev->stats.rx_bytes += pkt_len;
1465                 }
1466                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1467                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1468                 rxdesc = &mdp->rx_ring[entry];
1469         }
1470
1471         /* Refill the Rx ring buffers. */
1472         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1473                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1474                 rxdesc = &mdp->rx_ring[entry];
1475                 /* The size of the buffer is 16 byte boundary. */
1476                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1477
1478                 if (mdp->rx_skbuff[entry] == NULL) {
1479                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1480                         mdp->rx_skbuff[entry] = skb;
1481                         if (skb == NULL)
1482                                 break;  /* Better luck next round. */
1483                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1484                                        DMA_FROM_DEVICE);
1485                         sh_eth_set_receive_align(skb);
1486
1487                         skb_checksum_none_assert(skb);
1488                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1489                 }
1490                 if (entry >= mdp->num_rx_ring - 1)
1491                         rxdesc->status |=
1492                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1493                 else
1494                         rxdesc->status |=
1495                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1496         }
1497
1498         /* Restart Rx engine if stopped. */
1499         /* If we don't need to check status, don't. -KDU */
1500         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1501                 /* fix the values for the next receiving if RDE is set */
1502                 if (intr_status & EESR_RDE) {
1503                         u32 count = (sh_eth_read(ndev, RDFAR) -
1504                                      sh_eth_read(ndev, RDLAR)) >> 4;
1505
1506                         mdp->cur_rx = count;
1507                         mdp->dirty_rx = count;
1508                 }
1509                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1510         }
1511
1512         return exceeded;
1513 }
1514
1515 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1516 {
1517         /* disable tx and rx */
1518         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1519                 ~(ECMR_RE | ECMR_TE), ECMR);
1520 }
1521
1522 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1523 {
1524         /* enable tx and rx */
1525         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1526                 (ECMR_RE | ECMR_TE), ECMR);
1527 }
1528
1529 /* error control function */
1530 static void sh_eth_error(struct net_device *ndev, int intr_status)
1531 {
1532         struct sh_eth_private *mdp = netdev_priv(ndev);
1533         u32 felic_stat;
1534         u32 link_stat;
1535         u32 mask;
1536
1537         if (intr_status & EESR_ECI) {
1538                 felic_stat = sh_eth_read(ndev, ECSR);
1539                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1540                 if (felic_stat & ECSR_ICD)
1541                         ndev->stats.tx_carrier_errors++;
1542                 if (felic_stat & ECSR_LCHNG) {
1543                         /* Link Changed */
1544                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1545                                 goto ignore_link;
1546                         } else {
1547                                 link_stat = (sh_eth_read(ndev, PSR));
1548                                 if (mdp->ether_link_active_low)
1549                                         link_stat = ~link_stat;
1550                         }
1551                         if (!(link_stat & PHY_ST_LINK)) {
1552                                 sh_eth_rcv_snd_disable(ndev);
1553                         } else {
1554                                 /* Link Up */
1555                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1556                                                    ~DMAC_M_ECI, EESIPR);
1557                                 /* clear int */
1558                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1559                                              ECSR);
1560                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1561                                                    DMAC_M_ECI, EESIPR);
1562                                 /* enable tx and rx */
1563                                 sh_eth_rcv_snd_enable(ndev);
1564                         }
1565                 }
1566         }
1567
1568 ignore_link:
1569         if (intr_status & EESR_TWB) {
1570                 /* Unused write back interrupt */
1571                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1572                         ndev->stats.tx_aborted_errors++;
1573                         if (netif_msg_tx_err(mdp))
1574                                 dev_err(&ndev->dev, "Transmit Abort\n");
1575                 }
1576         }
1577
1578         if (intr_status & EESR_RABT) {
1579                 /* Receive Abort int */
1580                 if (intr_status & EESR_RFRMER) {
1581                         /* Receive Frame Overflow int */
1582                         ndev->stats.rx_frame_errors++;
1583                         if (netif_msg_rx_err(mdp))
1584                                 dev_err(&ndev->dev, "Receive Abort\n");
1585                 }
1586         }
1587
1588         if (intr_status & EESR_TDE) {
1589                 /* Transmit Descriptor Empty int */
1590                 ndev->stats.tx_fifo_errors++;
1591                 if (netif_msg_tx_err(mdp))
1592                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1593         }
1594
1595         if (intr_status & EESR_TFE) {
1596                 /* FIFO under flow */
1597                 ndev->stats.tx_fifo_errors++;
1598                 if (netif_msg_tx_err(mdp))
1599                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1600         }
1601
1602         if (intr_status & EESR_RDE) {
1603                 /* Receive Descriptor Empty int */
1604                 ndev->stats.rx_over_errors++;
1605
1606                 if (netif_msg_rx_err(mdp))
1607                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1608         }
1609
1610         if (intr_status & EESR_RFE) {
1611                 /* Receive FIFO Overflow int */
1612                 ndev->stats.rx_fifo_errors++;
1613                 if (netif_msg_rx_err(mdp))
1614                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1615         }
1616
1617         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1618                 /* Address Error */
1619                 ndev->stats.tx_fifo_errors++;
1620                 if (netif_msg_tx_err(mdp))
1621                         dev_err(&ndev->dev, "Address Error\n");
1622         }
1623
1624         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1625         if (mdp->cd->no_ade)
1626                 mask &= ~EESR_ADE;
1627         if (intr_status & mask) {
1628                 /* Tx error */
1629                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1630
1631                 /* dmesg */
1632                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1633                         intr_status, mdp->cur_tx, mdp->dirty_tx,
1634                         (u32)ndev->state, edtrr);
1635                 /* dirty buffer free */
1636                 sh_eth_txfree(ndev);
1637
1638                 /* SH7712 BUG */
1639                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1640                         /* tx dma start */
1641                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1642                 }
1643                 /* wakeup */
1644                 netif_wake_queue(ndev);
1645         }
1646 }
1647
1648 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1649 {
1650         struct net_device *ndev = netdev;
1651         struct sh_eth_private *mdp = netdev_priv(ndev);
1652         struct sh_eth_cpu_data *cd = mdp->cd;
1653         irqreturn_t ret = IRQ_NONE;
1654         unsigned long intr_status, intr_enable;
1655
1656         spin_lock(&mdp->lock);
1657
1658         /* Get interrupt status */
1659         intr_status = sh_eth_read(ndev, EESR);
1660         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1661          * enabled since it's the one that  comes thru regardless of the mask,
1662          * and we need to fully handle it in sh_eth_error() in order to quench
1663          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1664          */
1665         intr_enable = sh_eth_read(ndev, EESIPR);
1666         intr_status &= intr_enable | DMAC_M_ECI;
1667         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1668                 ret = IRQ_HANDLED;
1669         else
1670                 goto other_irq;
1671
1672         if (intr_status & EESR_RX_CHECK) {
1673                 if (napi_schedule_prep(&mdp->napi)) {
1674                         /* Mask Rx interrupts */
1675                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1676                                      EESIPR);
1677                         __napi_schedule(&mdp->napi);
1678                 } else {
1679                         dev_warn(&ndev->dev,
1680                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1681                                  intr_status, intr_enable);
1682                 }
1683         }
1684
1685         /* Tx Check */
1686         if (intr_status & cd->tx_check) {
1687                 /* Clear Tx interrupts */
1688                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1689
1690                 sh_eth_txfree(ndev);
1691                 netif_wake_queue(ndev);
1692         }
1693
1694         if (intr_status & cd->eesr_err_check) {
1695                 /* Clear error interrupts */
1696                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1697
1698                 sh_eth_error(ndev, intr_status);
1699         }
1700
1701 other_irq:
1702         spin_unlock(&mdp->lock);
1703
1704         return ret;
1705 }
1706
1707 static int sh_eth_poll(struct napi_struct *napi, int budget)
1708 {
1709         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1710                                                   napi);
1711         struct net_device *ndev = napi->dev;
1712         int quota = budget;
1713         unsigned long intr_status;
1714
1715         for (;;) {
1716                 intr_status = sh_eth_read(ndev, EESR);
1717                 if (!(intr_status & EESR_RX_CHECK))
1718                         break;
1719                 /* Clear Rx interrupts */
1720                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1721
1722                 if (sh_eth_rx(ndev, intr_status, &quota))
1723                         goto out;
1724         }
1725
1726         napi_complete(napi);
1727
1728         /* Reenable Rx interrupts */
1729         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1730 out:
1731         return budget - quota;
1732 }
1733
1734 /* PHY state control function */
1735 static void sh_eth_adjust_link(struct net_device *ndev)
1736 {
1737         struct sh_eth_private *mdp = netdev_priv(ndev);
1738         struct phy_device *phydev = mdp->phydev;
1739         int new_state = 0;
1740
1741         if (phydev->link) {
1742                 if (phydev->duplex != mdp->duplex) {
1743                         new_state = 1;
1744                         mdp->duplex = phydev->duplex;
1745                         if (mdp->cd->set_duplex)
1746                                 mdp->cd->set_duplex(ndev);
1747                 }
1748
1749                 if (phydev->speed != mdp->speed) {
1750                         new_state = 1;
1751                         mdp->speed = phydev->speed;
1752                         if (mdp->cd->set_rate)
1753                                 mdp->cd->set_rate(ndev);
1754                 }
1755                 if (!mdp->link) {
1756                         sh_eth_write(ndev,
1757                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1758                                      ECMR);
1759                         new_state = 1;
1760                         mdp->link = phydev->link;
1761                         if (mdp->cd->no_psr || mdp->no_ether_link)
1762                                 sh_eth_rcv_snd_enable(ndev);
1763                 }
1764         } else if (mdp->link) {
1765                 new_state = 1;
1766                 mdp->link = 0;
1767                 mdp->speed = 0;
1768                 mdp->duplex = -1;
1769                 if (mdp->cd->no_psr || mdp->no_ether_link)
1770                         sh_eth_rcv_snd_disable(ndev);
1771         }
1772
1773         if (new_state && netif_msg_link(mdp))
1774                 phy_print_status(phydev);
1775 }
1776
1777 /* PHY init function */
1778 static int sh_eth_phy_init(struct net_device *ndev)
1779 {
1780         struct device_node *np = ndev->dev.parent->of_node;
1781         struct sh_eth_private *mdp = netdev_priv(ndev);
1782         struct phy_device *phydev = NULL;
1783
1784         mdp->link = 0;
1785         mdp->speed = 0;
1786         mdp->duplex = -1;
1787
1788         /* Try connect to PHY */
1789         if (np) {
1790                 struct device_node *pn;
1791
1792                 pn = of_parse_phandle(np, "phy-handle", 0);
1793                 phydev = of_phy_connect(ndev, pn,
1794                                         sh_eth_adjust_link, 0,
1795                                         mdp->phy_interface);
1796
1797                 if (!phydev)
1798                         phydev = ERR_PTR(-ENOENT);
1799         } else {
1800                 char phy_id[MII_BUS_ID_SIZE + 3];
1801
1802                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1803                          mdp->mii_bus->id, mdp->phy_id);
1804
1805                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1806                                      mdp->phy_interface);
1807         }
1808
1809         if (IS_ERR(phydev)) {
1810                 dev_err(&ndev->dev, "failed to connect PHY\n");
1811                 return PTR_ERR(phydev);
1812         }
1813
1814         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1815                  phydev->addr, phydev->irq, phydev->drv->name);
1816
1817         mdp->phydev = phydev;
1818
1819         return 0;
1820 }
1821
1822 /* PHY control start function */
1823 static int sh_eth_phy_start(struct net_device *ndev)
1824 {
1825         struct sh_eth_private *mdp = netdev_priv(ndev);
1826         int ret;
1827
1828         ret = sh_eth_phy_init(ndev);
1829         if (ret)
1830                 return ret;
1831
1832         phy_start(mdp->phydev);
1833
1834         return 0;
1835 }
1836
1837 static int sh_eth_get_settings(struct net_device *ndev,
1838                                struct ethtool_cmd *ecmd)
1839 {
1840         struct sh_eth_private *mdp = netdev_priv(ndev);
1841         unsigned long flags;
1842         int ret;
1843
1844         spin_lock_irqsave(&mdp->lock, flags);
1845         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1846         spin_unlock_irqrestore(&mdp->lock, flags);
1847
1848         return ret;
1849 }
1850
1851 static int sh_eth_set_settings(struct net_device *ndev,
1852                                struct ethtool_cmd *ecmd)
1853 {
1854         struct sh_eth_private *mdp = netdev_priv(ndev);
1855         unsigned long flags;
1856         int ret;
1857
1858         spin_lock_irqsave(&mdp->lock, flags);
1859
1860         /* disable tx and rx */
1861         sh_eth_rcv_snd_disable(ndev);
1862
1863         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1864         if (ret)
1865                 goto error_exit;
1866
1867         if (ecmd->duplex == DUPLEX_FULL)
1868                 mdp->duplex = 1;
1869         else
1870                 mdp->duplex = 0;
1871
1872         if (mdp->cd->set_duplex)
1873                 mdp->cd->set_duplex(ndev);
1874
1875 error_exit:
1876         mdelay(1);
1877
1878         /* enable tx and rx */
1879         sh_eth_rcv_snd_enable(ndev);
1880
1881         spin_unlock_irqrestore(&mdp->lock, flags);
1882
1883         return ret;
1884 }
1885
1886 static int sh_eth_nway_reset(struct net_device *ndev)
1887 {
1888         struct sh_eth_private *mdp = netdev_priv(ndev);
1889         unsigned long flags;
1890         int ret;
1891
1892         spin_lock_irqsave(&mdp->lock, flags);
1893         ret = phy_start_aneg(mdp->phydev);
1894         spin_unlock_irqrestore(&mdp->lock, flags);
1895
1896         return ret;
1897 }
1898
1899 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1900 {
1901         struct sh_eth_private *mdp = netdev_priv(ndev);
1902         return mdp->msg_enable;
1903 }
1904
1905 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1906 {
1907         struct sh_eth_private *mdp = netdev_priv(ndev);
1908         mdp->msg_enable = value;
1909 }
1910
1911 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1912         "rx_current", "tx_current",
1913         "rx_dirty", "tx_dirty",
1914 };
1915 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1916
1917 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1918 {
1919         switch (sset) {
1920         case ETH_SS_STATS:
1921                 return SH_ETH_STATS_LEN;
1922         default:
1923                 return -EOPNOTSUPP;
1924         }
1925 }
1926
1927 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1928                                      struct ethtool_stats *stats, u64 *data)
1929 {
1930         struct sh_eth_private *mdp = netdev_priv(ndev);
1931         int i = 0;
1932
1933         /* device-specific stats */
1934         data[i++] = mdp->cur_rx;
1935         data[i++] = mdp->cur_tx;
1936         data[i++] = mdp->dirty_rx;
1937         data[i++] = mdp->dirty_tx;
1938 }
1939
1940 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1941 {
1942         switch (stringset) {
1943         case ETH_SS_STATS:
1944                 memcpy(data, *sh_eth_gstrings_stats,
1945                        sizeof(sh_eth_gstrings_stats));
1946                 break;
1947         }
1948 }
1949
1950 static void sh_eth_get_ringparam(struct net_device *ndev,
1951                                  struct ethtool_ringparam *ring)
1952 {
1953         struct sh_eth_private *mdp = netdev_priv(ndev);
1954
1955         ring->rx_max_pending = RX_RING_MAX;
1956         ring->tx_max_pending = TX_RING_MAX;
1957         ring->rx_pending = mdp->num_rx_ring;
1958         ring->tx_pending = mdp->num_tx_ring;
1959 }
1960
1961 static int sh_eth_set_ringparam(struct net_device *ndev,
1962                                 struct ethtool_ringparam *ring)
1963 {
1964         struct sh_eth_private *mdp = netdev_priv(ndev);
1965         int ret;
1966
1967         if (ring->tx_pending > TX_RING_MAX ||
1968             ring->rx_pending > RX_RING_MAX ||
1969             ring->tx_pending < TX_RING_MIN ||
1970             ring->rx_pending < RX_RING_MIN)
1971                 return -EINVAL;
1972         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1973                 return -EINVAL;
1974
1975         if (netif_running(ndev)) {
1976                 netif_tx_disable(ndev);
1977                 /* Disable interrupts by clearing the interrupt mask. */
1978                 sh_eth_write(ndev, 0x0000, EESIPR);
1979                 /* Stop the chip's Tx and Rx processes. */
1980                 sh_eth_write(ndev, 0, EDTRR);
1981                 sh_eth_write(ndev, 0, EDRRR);
1982                 synchronize_irq(ndev->irq);
1983         }
1984
1985         /* Free all the skbuffs in the Rx queue. */
1986         sh_eth_ring_free(ndev);
1987         /* Free DMA buffer */
1988         sh_eth_free_dma_buffer(mdp);
1989
1990         /* Set new parameters */
1991         mdp->num_rx_ring = ring->rx_pending;
1992         mdp->num_tx_ring = ring->tx_pending;
1993
1994         ret = sh_eth_ring_init(ndev);
1995         if (ret < 0) {
1996                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1997                 return ret;
1998         }
1999         ret = sh_eth_dev_init(ndev, false);
2000         if (ret < 0) {
2001                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
2002                 return ret;
2003         }
2004
2005         if (netif_running(ndev)) {
2006                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2007                 /* Setting the Rx mode will start the Rx process. */
2008                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2009                 netif_wake_queue(ndev);
2010         }
2011
2012         return 0;
2013 }
2014
2015 static const struct ethtool_ops sh_eth_ethtool_ops = {
2016         .get_settings   = sh_eth_get_settings,
2017         .set_settings   = sh_eth_set_settings,
2018         .nway_reset     = sh_eth_nway_reset,
2019         .get_msglevel   = sh_eth_get_msglevel,
2020         .set_msglevel   = sh_eth_set_msglevel,
2021         .get_link       = ethtool_op_get_link,
2022         .get_strings    = sh_eth_get_strings,
2023         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2024         .get_sset_count     = sh_eth_get_sset_count,
2025         .get_ringparam  = sh_eth_get_ringparam,
2026         .set_ringparam  = sh_eth_set_ringparam,
2027 };
2028
2029 /* network device open function */
2030 static int sh_eth_open(struct net_device *ndev)
2031 {
2032         int ret = 0;
2033         struct sh_eth_private *mdp = netdev_priv(ndev);
2034
2035         pm_runtime_get_sync(&mdp->pdev->dev);
2036
2037         napi_enable(&mdp->napi);
2038
2039         ret = request_irq(ndev->irq, sh_eth_interrupt,
2040                           mdp->cd->irq_flags, ndev->name, ndev);
2041         if (ret) {
2042                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
2043                 goto out_napi_off;
2044         }
2045
2046         /* Descriptor set */
2047         ret = sh_eth_ring_init(ndev);
2048         if (ret)
2049                 goto out_free_irq;
2050
2051         /* device init */
2052         ret = sh_eth_dev_init(ndev, true);
2053         if (ret)
2054                 goto out_free_irq;
2055
2056         /* PHY control start*/
2057         ret = sh_eth_phy_start(ndev);
2058         if (ret)
2059                 goto out_free_irq;
2060
2061         return ret;
2062
2063 out_free_irq:
2064         free_irq(ndev->irq, ndev);
2065 out_napi_off:
2066         napi_disable(&mdp->napi);
2067         pm_runtime_put_sync(&mdp->pdev->dev);
2068         return ret;
2069 }
2070
2071 /* Timeout function */
2072 static void sh_eth_tx_timeout(struct net_device *ndev)
2073 {
2074         struct sh_eth_private *mdp = netdev_priv(ndev);
2075         struct sh_eth_rxdesc *rxdesc;
2076         int i;
2077
2078         netif_stop_queue(ndev);
2079
2080         if (netif_msg_timer(mdp)) {
2081                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
2082                         ndev->name, (int)sh_eth_read(ndev, EESR));
2083         }
2084
2085         /* tx_errors count up */
2086         ndev->stats.tx_errors++;
2087
2088         /* Free all the skbuffs in the Rx queue. */
2089         for (i = 0; i < mdp->num_rx_ring; i++) {
2090                 rxdesc = &mdp->rx_ring[i];
2091                 rxdesc->status = 0;
2092                 rxdesc->addr = 0xBADF00D0;
2093                 if (mdp->rx_skbuff[i])
2094                         dev_kfree_skb(mdp->rx_skbuff[i]);
2095                 mdp->rx_skbuff[i] = NULL;
2096         }
2097         for (i = 0; i < mdp->num_tx_ring; i++) {
2098                 if (mdp->tx_skbuff[i])
2099                         dev_kfree_skb(mdp->tx_skbuff[i]);
2100                 mdp->tx_skbuff[i] = NULL;
2101         }
2102
2103         /* device init */
2104         sh_eth_dev_init(ndev, true);
2105 }
2106
2107 /* Packet transmit function */
2108 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2109 {
2110         struct sh_eth_private *mdp = netdev_priv(ndev);
2111         struct sh_eth_txdesc *txdesc;
2112         u32 entry;
2113         unsigned long flags;
2114
2115         spin_lock_irqsave(&mdp->lock, flags);
2116         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2117                 if (!sh_eth_txfree(ndev)) {
2118                         if (netif_msg_tx_queued(mdp))
2119                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2120                         netif_stop_queue(ndev);
2121                         spin_unlock_irqrestore(&mdp->lock, flags);
2122                         return NETDEV_TX_BUSY;
2123                 }
2124         }
2125         spin_unlock_irqrestore(&mdp->lock, flags);
2126
2127         entry = mdp->cur_tx % mdp->num_tx_ring;
2128         mdp->tx_skbuff[entry] = skb;
2129         txdesc = &mdp->tx_ring[entry];
2130         /* soft swap. */
2131         if (!mdp->cd->hw_swap)
2132                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2133                                  skb->len + 2);
2134         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2135                                       DMA_TO_DEVICE);
2136         if (skb->len < ETH_ZLEN)
2137                 txdesc->buffer_length = ETH_ZLEN;
2138         else
2139                 txdesc->buffer_length = skb->len;
2140
2141         if (entry >= mdp->num_tx_ring - 1)
2142                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2143         else
2144                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2145
2146         mdp->cur_tx++;
2147
2148         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2149                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2150
2151         return NETDEV_TX_OK;
2152 }
2153
2154 /* device close function */
2155 static int sh_eth_close(struct net_device *ndev)
2156 {
2157         struct sh_eth_private *mdp = netdev_priv(ndev);
2158
2159         netif_stop_queue(ndev);
2160
2161         /* Disable interrupts by clearing the interrupt mask. */
2162         sh_eth_write(ndev, 0x0000, EESIPR);
2163
2164         /* Stop the chip's Tx and Rx processes. */
2165         sh_eth_write(ndev, 0, EDTRR);
2166         sh_eth_write(ndev, 0, EDRRR);
2167
2168         /* PHY Disconnect */
2169         if (mdp->phydev) {
2170                 phy_stop(mdp->phydev);
2171                 phy_disconnect(mdp->phydev);
2172         }
2173
2174         free_irq(ndev->irq, ndev);
2175
2176         napi_disable(&mdp->napi);
2177
2178         /* Free all the skbuffs in the Rx queue. */
2179         sh_eth_ring_free(ndev);
2180
2181         /* free DMA buffer */
2182         sh_eth_free_dma_buffer(mdp);
2183
2184         pm_runtime_put_sync(&mdp->pdev->dev);
2185
2186         return 0;
2187 }
2188
2189 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2190 {
2191         struct sh_eth_private *mdp = netdev_priv(ndev);
2192
2193         if (sh_eth_is_rz_fast_ether(mdp))
2194                 return &ndev->stats;
2195
2196         pm_runtime_get_sync(&mdp->pdev->dev);
2197
2198         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2199         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2200         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2201         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2202         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2203         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2204         if (sh_eth_is_gether(mdp)) {
2205                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2206                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2207                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2208                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2209         } else {
2210                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2211                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2212         }
2213         pm_runtime_put_sync(&mdp->pdev->dev);
2214
2215         return &ndev->stats;
2216 }
2217
2218 /* ioctl to device function */
2219 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2220 {
2221         struct sh_eth_private *mdp = netdev_priv(ndev);
2222         struct phy_device *phydev = mdp->phydev;
2223
2224         if (!netif_running(ndev))
2225                 return -EINVAL;
2226
2227         if (!phydev)
2228                 return -ENODEV;
2229
2230         return phy_mii_ioctl(phydev, rq, cmd);
2231 }
2232
2233 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2234 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2235                                             int entry)
2236 {
2237         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2238 }
2239
2240 static u32 sh_eth_tsu_get_post_mask(int entry)
2241 {
2242         return 0x0f << (28 - ((entry % 8) * 4));
2243 }
2244
2245 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2246 {
2247         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2248 }
2249
2250 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2251                                              int entry)
2252 {
2253         struct sh_eth_private *mdp = netdev_priv(ndev);
2254         u32 tmp;
2255         void *reg_offset;
2256
2257         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2258         tmp = ioread32(reg_offset);
2259         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2260 }
2261
2262 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2263                                               int entry)
2264 {
2265         struct sh_eth_private *mdp = netdev_priv(ndev);
2266         u32 post_mask, ref_mask, tmp;
2267         void *reg_offset;
2268
2269         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2270         post_mask = sh_eth_tsu_get_post_mask(entry);
2271         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2272
2273         tmp = ioread32(reg_offset);
2274         iowrite32(tmp & ~post_mask, reg_offset);
2275
2276         /* If other port enables, the function returns "true" */
2277         return tmp & ref_mask;
2278 }
2279
2280 static int sh_eth_tsu_busy(struct net_device *ndev)
2281 {
2282         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2283         struct sh_eth_private *mdp = netdev_priv(ndev);
2284
2285         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2286                 udelay(10);
2287                 timeout--;
2288                 if (timeout <= 0) {
2289                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2290                         return -ETIMEDOUT;
2291                 }
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2298                                   const u8 *addr)
2299 {
2300         u32 val;
2301
2302         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2303         iowrite32(val, reg);
2304         if (sh_eth_tsu_busy(ndev) < 0)
2305                 return -EBUSY;
2306
2307         val = addr[4] << 8 | addr[5];
2308         iowrite32(val, reg + 4);
2309         if (sh_eth_tsu_busy(ndev) < 0)
2310                 return -EBUSY;
2311
2312         return 0;
2313 }
2314
2315 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2316 {
2317         u32 val;
2318
2319         val = ioread32(reg);
2320         addr[0] = (val >> 24) & 0xff;
2321         addr[1] = (val >> 16) & 0xff;
2322         addr[2] = (val >> 8) & 0xff;
2323         addr[3] = val & 0xff;
2324         val = ioread32(reg + 4);
2325         addr[4] = (val >> 8) & 0xff;
2326         addr[5] = val & 0xff;
2327 }
2328
2329
2330 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2331 {
2332         struct sh_eth_private *mdp = netdev_priv(ndev);
2333         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2334         int i;
2335         u8 c_addr[ETH_ALEN];
2336
2337         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2338                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2339                 if (ether_addr_equal(addr, c_addr))
2340                         return i;
2341         }
2342
2343         return -ENOENT;
2344 }
2345
2346 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2347 {
2348         u8 blank[ETH_ALEN];
2349         int entry;
2350
2351         memset(blank, 0, sizeof(blank));
2352         entry = sh_eth_tsu_find_entry(ndev, blank);
2353         return (entry < 0) ? -ENOMEM : entry;
2354 }
2355
2356 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2357                                               int entry)
2358 {
2359         struct sh_eth_private *mdp = netdev_priv(ndev);
2360         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2361         int ret;
2362         u8 blank[ETH_ALEN];
2363
2364         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2365                          ~(1 << (31 - entry)), TSU_TEN);
2366
2367         memset(blank, 0, sizeof(blank));
2368         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2369         if (ret < 0)
2370                 return ret;
2371         return 0;
2372 }
2373
2374 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2375 {
2376         struct sh_eth_private *mdp = netdev_priv(ndev);
2377         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2378         int i, ret;
2379
2380         if (!mdp->cd->tsu)
2381                 return 0;
2382
2383         i = sh_eth_tsu_find_entry(ndev, addr);
2384         if (i < 0) {
2385                 /* No entry found, create one */
2386                 i = sh_eth_tsu_find_empty(ndev);
2387                 if (i < 0)
2388                         return -ENOMEM;
2389                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2390                 if (ret < 0)
2391                         return ret;
2392
2393                 /* Enable the entry */
2394                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2395                                  (1 << (31 - i)), TSU_TEN);
2396         }
2397
2398         /* Entry found or created, enable POST */
2399         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2400
2401         return 0;
2402 }
2403
2404 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2405 {
2406         struct sh_eth_private *mdp = netdev_priv(ndev);
2407         int i, ret;
2408
2409         if (!mdp->cd->tsu)
2410                 return 0;
2411
2412         i = sh_eth_tsu_find_entry(ndev, addr);
2413         if (i) {
2414                 /* Entry found */
2415                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2416                         goto done;
2417
2418                 /* Disable the entry if both ports was disabled */
2419                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2420                 if (ret < 0)
2421                         return ret;
2422         }
2423 done:
2424         return 0;
2425 }
2426
2427 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2428 {
2429         struct sh_eth_private *mdp = netdev_priv(ndev);
2430         int i, ret;
2431
2432         if (unlikely(!mdp->cd->tsu))
2433                 return 0;
2434
2435         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2436                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2437                         continue;
2438
2439                 /* Disable the entry if both ports was disabled */
2440                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2441                 if (ret < 0)
2442                         return ret;
2443         }
2444
2445         return 0;
2446 }
2447
2448 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2449 {
2450         struct sh_eth_private *mdp = netdev_priv(ndev);
2451         u8 addr[ETH_ALEN];
2452         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2453         int i;
2454
2455         if (unlikely(!mdp->cd->tsu))
2456                 return;
2457
2458         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2459                 sh_eth_tsu_read_entry(reg_offset, addr);
2460                 if (is_multicast_ether_addr(addr))
2461                         sh_eth_tsu_del_entry(ndev, addr);
2462         }
2463 }
2464
2465 /* Multicast reception directions set */
2466 static void sh_eth_set_multicast_list(struct net_device *ndev)
2467 {
2468         struct sh_eth_private *mdp = netdev_priv(ndev);
2469         u32 ecmr_bits;
2470         int mcast_all = 0;
2471         unsigned long flags;
2472
2473         spin_lock_irqsave(&mdp->lock, flags);
2474         /* Initial condition is MCT = 1, PRM = 0.
2475          * Depending on ndev->flags, set PRM or clear MCT
2476          */
2477         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2478
2479         if (!(ndev->flags & IFF_MULTICAST)) {
2480                 sh_eth_tsu_purge_mcast(ndev);
2481                 mcast_all = 1;
2482         }
2483         if (ndev->flags & IFF_ALLMULTI) {
2484                 sh_eth_tsu_purge_mcast(ndev);
2485                 ecmr_bits &= ~ECMR_MCT;
2486                 mcast_all = 1;
2487         }
2488
2489         if (ndev->flags & IFF_PROMISC) {
2490                 sh_eth_tsu_purge_all(ndev);
2491                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2492         } else if (mdp->cd->tsu) {
2493                 struct netdev_hw_addr *ha;
2494                 netdev_for_each_mc_addr(ha, ndev) {
2495                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2496                                 continue;
2497
2498                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2499                                 if (!mcast_all) {
2500                                         sh_eth_tsu_purge_mcast(ndev);
2501                                         ecmr_bits &= ~ECMR_MCT;
2502                                         mcast_all = 1;
2503                                 }
2504                         }
2505                 }
2506         } else {
2507                 /* Normal, unicast/broadcast-only mode. */
2508                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2509         }
2510
2511         /* update the ethernet mode */
2512         sh_eth_write(ndev, ecmr_bits, ECMR);
2513
2514         spin_unlock_irqrestore(&mdp->lock, flags);
2515 }
2516
2517 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2518 {
2519         if (!mdp->port)
2520                 return TSU_VTAG0;
2521         else
2522                 return TSU_VTAG1;
2523 }
2524
2525 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2526                                   __be16 proto, u16 vid)
2527 {
2528         struct sh_eth_private *mdp = netdev_priv(ndev);
2529         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2530
2531         if (unlikely(!mdp->cd->tsu))
2532                 return -EPERM;
2533
2534         /* No filtering if vid = 0 */
2535         if (!vid)
2536                 return 0;
2537
2538         mdp->vlan_num_ids++;
2539
2540         /* The controller has one VLAN tag HW filter. So, if the filter is
2541          * already enabled, the driver disables it and the filte
2542          */
2543         if (mdp->vlan_num_ids > 1) {
2544                 /* disable VLAN filter */
2545                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2546                 return 0;
2547         }
2548
2549         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2550                          vtag_reg_index);
2551
2552         return 0;
2553 }
2554
2555 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2556                                    __be16 proto, u16 vid)
2557 {
2558         struct sh_eth_private *mdp = netdev_priv(ndev);
2559         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2560
2561         if (unlikely(!mdp->cd->tsu))
2562                 return -EPERM;
2563
2564         /* No filtering if vid = 0 */
2565         if (!vid)
2566                 return 0;
2567
2568         mdp->vlan_num_ids--;
2569         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2570
2571         return 0;
2572 }
2573
2574 /* SuperH's TSU register init function */
2575 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2576 {
2577         if (sh_eth_is_rz_fast_ether(mdp)) {
2578                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2579                 return;
2580         }
2581
2582         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2583         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2584         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2585         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2586         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2587         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2588         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2589         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2590         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2591         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2592         if (sh_eth_is_gether(mdp)) {
2593                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2594                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2595         } else {
2596                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2597                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2598         }
2599         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2600         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2601         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2602         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2603         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2604         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2605         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2606 }
2607
2608 /* MDIO bus release function */
2609 static int sh_mdio_release(struct net_device *ndev)
2610 {
2611         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2612
2613         /* unregister mdio bus */
2614         mdiobus_unregister(bus);
2615
2616         /* remove mdio bus info from net_device */
2617         dev_set_drvdata(&ndev->dev, NULL);
2618
2619         /* free bitbang info */
2620         free_mdio_bitbang(bus);
2621
2622         return 0;
2623 }
2624
2625 /* MDIO bus init function */
2626 static int sh_mdio_init(struct net_device *ndev, int id,
2627                         struct sh_eth_plat_data *pd)
2628 {
2629         int ret, i;
2630         struct bb_info *bitbang;
2631         struct sh_eth_private *mdp = netdev_priv(ndev);
2632
2633         /* create bit control struct for PHY */
2634         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2635                                GFP_KERNEL);
2636         if (!bitbang) {
2637                 ret = -ENOMEM;
2638                 goto out;
2639         }
2640
2641         /* bitbang init */
2642         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2643         bitbang->set_gate = pd->set_mdio_gate;
2644         bitbang->mdi_msk = PIR_MDI;
2645         bitbang->mdo_msk = PIR_MDO;
2646         bitbang->mmd_msk = PIR_MMD;
2647         bitbang->mdc_msk = PIR_MDC;
2648         bitbang->ctrl.ops = &bb_ops;
2649
2650         /* MII controller setting */
2651         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2652         if (!mdp->mii_bus) {
2653                 ret = -ENOMEM;
2654                 goto out;
2655         }
2656
2657         /* Hook up MII support for ethtool */
2658         mdp->mii_bus->name = "sh_mii";
2659         mdp->mii_bus->parent = &ndev->dev;
2660         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2661                  mdp->pdev->name, id);
2662
2663         /* PHY IRQ */
2664         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2665                                          sizeof(int) * PHY_MAX_ADDR,
2666                                          GFP_KERNEL);
2667         if (!mdp->mii_bus->irq) {
2668                 ret = -ENOMEM;
2669                 goto out_free_bus;
2670         }
2671
2672         /* register mdio bus */
2673         if (ndev->dev.parent->of_node) {
2674                 ret = of_mdiobus_register(mdp->mii_bus,
2675                                           ndev->dev.parent->of_node);
2676         } else {
2677                 for (i = 0; i < PHY_MAX_ADDR; i++)
2678                         mdp->mii_bus->irq[i] = PHY_POLL;
2679                 if (pd->phy_irq > 0)
2680                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2681
2682                 ret = mdiobus_register(mdp->mii_bus);
2683         }
2684
2685         if (ret)
2686                 goto out_free_bus;
2687
2688         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2689
2690         return 0;
2691
2692 out_free_bus:
2693         free_mdio_bitbang(mdp->mii_bus);
2694
2695 out:
2696         return ret;
2697 }
2698
2699 static const u16 *sh_eth_get_register_offset(int register_type)
2700 {
2701         const u16 *reg_offset = NULL;
2702
2703         switch (register_type) {
2704         case SH_ETH_REG_GIGABIT:
2705                 reg_offset = sh_eth_offset_gigabit;
2706                 break;
2707         case SH_ETH_REG_FAST_RZ:
2708                 reg_offset = sh_eth_offset_fast_rz;
2709                 break;
2710         case SH_ETH_REG_FAST_RCAR:
2711                 reg_offset = sh_eth_offset_fast_rcar;
2712                 break;
2713         case SH_ETH_REG_FAST_SH4:
2714                 reg_offset = sh_eth_offset_fast_sh4;
2715                 break;
2716         case SH_ETH_REG_FAST_SH3_SH2:
2717                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2718                 break;
2719         default:
2720                 pr_err("Unknown register type (%d)\n", register_type);
2721                 break;
2722         }
2723
2724         return reg_offset;
2725 }
2726
2727 static const struct net_device_ops sh_eth_netdev_ops = {
2728         .ndo_open               = sh_eth_open,
2729         .ndo_stop               = sh_eth_close,
2730         .ndo_start_xmit         = sh_eth_start_xmit,
2731         .ndo_get_stats          = sh_eth_get_stats,
2732         .ndo_tx_timeout         = sh_eth_tx_timeout,
2733         .ndo_do_ioctl           = sh_eth_do_ioctl,
2734         .ndo_validate_addr      = eth_validate_addr,
2735         .ndo_set_mac_address    = eth_mac_addr,
2736         .ndo_change_mtu         = eth_change_mtu,
2737 };
2738
2739 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2740         .ndo_open               = sh_eth_open,
2741         .ndo_stop               = sh_eth_close,
2742         .ndo_start_xmit         = sh_eth_start_xmit,
2743         .ndo_get_stats          = sh_eth_get_stats,
2744         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2745         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2746         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2747         .ndo_tx_timeout         = sh_eth_tx_timeout,
2748         .ndo_do_ioctl           = sh_eth_do_ioctl,
2749         .ndo_validate_addr      = eth_validate_addr,
2750         .ndo_set_mac_address    = eth_mac_addr,
2751         .ndo_change_mtu         = eth_change_mtu,
2752 };
2753
2754 #ifdef CONFIG_OF
2755 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2756 {
2757         struct device_node *np = dev->of_node;
2758         struct sh_eth_plat_data *pdata;
2759         const char *mac_addr;
2760
2761         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2762         if (!pdata)
2763                 return NULL;
2764
2765         pdata->phy_interface = of_get_phy_mode(np);
2766
2767         mac_addr = of_get_mac_address(np);
2768         if (mac_addr)
2769                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2770
2771         pdata->no_ether_link =
2772                 of_property_read_bool(np, "renesas,no-ether-link");
2773         pdata->ether_link_active_low =
2774                 of_property_read_bool(np, "renesas,ether-link-active-low");
2775
2776         return pdata;
2777 }
2778
2779 static const struct of_device_id sh_eth_match_table[] = {
2780         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2781         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2782         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2783         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2784         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2785         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2786         { }
2787 };
2788 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2789 #else
2790 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2791 {
2792         return NULL;
2793 }
2794 #endif
2795
2796 static int sh_eth_drv_probe(struct platform_device *pdev)
2797 {
2798         int ret, devno = 0;
2799         struct resource *res;
2800         struct net_device *ndev = NULL;
2801         struct sh_eth_private *mdp = NULL;
2802         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2803         const struct platform_device_id *id = platform_get_device_id(pdev);
2804
2805         /* get base addr */
2806         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2807         if (unlikely(res == NULL)) {
2808                 dev_err(&pdev->dev, "invalid resource\n");
2809                 ret = -EINVAL;
2810                 goto out;
2811         }
2812
2813         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2814         if (!ndev) {
2815                 ret = -ENOMEM;
2816                 goto out;
2817         }
2818
2819         /* The sh Ether-specific entries in the device structure. */
2820         ndev->base_addr = res->start;
2821         devno = pdev->id;
2822         if (devno < 0)
2823                 devno = 0;
2824
2825         ndev->dma = -1;
2826         ret = platform_get_irq(pdev, 0);
2827         if (ret < 0) {
2828                 ret = -ENODEV;
2829                 goto out_release;
2830         }
2831         ndev->irq = ret;
2832
2833         SET_NETDEV_DEV(ndev, &pdev->dev);
2834
2835         mdp = netdev_priv(ndev);
2836         mdp->num_tx_ring = TX_RING_SIZE;
2837         mdp->num_rx_ring = RX_RING_SIZE;
2838         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2839         if (IS_ERR(mdp->addr)) {
2840                 ret = PTR_ERR(mdp->addr);
2841                 goto out_release;
2842         }
2843
2844         spin_lock_init(&mdp->lock);
2845         mdp->pdev = pdev;
2846         pm_runtime_enable(&pdev->dev);
2847         pm_runtime_resume(&pdev->dev);
2848
2849         if (pdev->dev.of_node)
2850                 pd = sh_eth_parse_dt(&pdev->dev);
2851         if (!pd) {
2852                 dev_err(&pdev->dev, "no platform data\n");
2853                 ret = -EINVAL;
2854                 goto out_release;
2855         }
2856
2857         /* get PHY ID */
2858         mdp->phy_id = pd->phy;
2859         mdp->phy_interface = pd->phy_interface;
2860         /* EDMAC endian */
2861         mdp->edmac_endian = pd->edmac_endian;
2862         mdp->no_ether_link = pd->no_ether_link;
2863         mdp->ether_link_active_low = pd->ether_link_active_low;
2864
2865         /* set cpu data */
2866         if (id) {
2867                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2868         } else  {
2869                 const struct of_device_id *match;
2870
2871                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2872                                         &pdev->dev);
2873                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2874         }
2875         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2876         sh_eth_set_default_cpu_data(mdp->cd);
2877
2878         /* set function */
2879         if (mdp->cd->tsu)
2880                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2881         else
2882                 ndev->netdev_ops = &sh_eth_netdev_ops;
2883         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2884         ndev->watchdog_timeo = TX_TIMEOUT;
2885
2886         /* debug message level */
2887         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2888
2889         /* read and set MAC address */
2890         read_mac_address(ndev, pd->mac_addr);
2891         if (!is_valid_ether_addr(ndev->dev_addr)) {
2892                 dev_warn(&pdev->dev,
2893                          "no valid MAC address supplied, using a random one.\n");
2894                 eth_hw_addr_random(ndev);
2895         }
2896
2897         /* ioremap the TSU registers */
2898         if (mdp->cd->tsu) {
2899                 struct resource *rtsu;
2900                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2901                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2902                 if (IS_ERR(mdp->tsu_addr)) {
2903                         ret = PTR_ERR(mdp->tsu_addr);
2904                         goto out_release;
2905                 }
2906                 mdp->port = devno % 2;
2907                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2908         }
2909
2910         /* initialize first or needed device */
2911         if (!devno || pd->needs_init) {
2912                 if (mdp->cd->chip_reset)
2913                         mdp->cd->chip_reset(ndev);
2914
2915                 if (mdp->cd->tsu) {
2916                         /* TSU init (Init only)*/
2917                         sh_eth_tsu_init(mdp);
2918                 }
2919         }
2920
2921         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2922
2923         /* network device register */
2924         ret = register_netdev(ndev);
2925         if (ret)
2926                 goto out_napi_del;
2927
2928         /* mdio bus init */
2929         ret = sh_mdio_init(ndev, pdev->id, pd);
2930         if (ret) {
2931                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2932                 goto out_unregister;
2933         }
2934
2935         /* print device information */
2936         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2937                 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2938
2939         platform_set_drvdata(pdev, ndev);
2940
2941         return ret;
2942
2943 out_unregister:
2944         unregister_netdev(ndev);
2945
2946 out_napi_del:
2947         netif_napi_del(&mdp->napi);
2948
2949 out_release:
2950         /* net_dev free */
2951         if (ndev)
2952                 free_netdev(ndev);
2953
2954 out:
2955         return ret;
2956 }
2957
2958 static int sh_eth_drv_remove(struct platform_device *pdev)
2959 {
2960         struct net_device *ndev = platform_get_drvdata(pdev);
2961         struct sh_eth_private *mdp = netdev_priv(ndev);
2962
2963         sh_mdio_release(ndev);
2964         unregister_netdev(ndev);
2965         netif_napi_del(&mdp->napi);
2966         pm_runtime_disable(&pdev->dev);
2967         free_netdev(ndev);
2968
2969         return 0;
2970 }
2971
2972 #ifdef CONFIG_PM
2973 static int sh_eth_runtime_nop(struct device *dev)
2974 {
2975         /* Runtime PM callback shared between ->runtime_suspend()
2976          * and ->runtime_resume(). Simply returns success.
2977          *
2978          * This driver re-initializes all registers after
2979          * pm_runtime_get_sync() anyway so there is no need
2980          * to save and restore registers here.
2981          */
2982         return 0;
2983 }
2984
2985 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2986         .runtime_suspend = sh_eth_runtime_nop,
2987         .runtime_resume = sh_eth_runtime_nop,
2988 };
2989 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2990 #else
2991 #define SH_ETH_PM_OPS NULL
2992 #endif
2993
2994 static struct platform_device_id sh_eth_id_table[] = {
2995         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2996         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2997         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2998         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2999         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3000         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3001         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3002         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3003         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3004         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3005         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3006         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3007         { }
3008 };
3009 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3010
3011 static struct platform_driver sh_eth_driver = {
3012         .probe = sh_eth_drv_probe,
3013         .remove = sh_eth_drv_remove,
3014         .id_table = sh_eth_id_table,
3015         .driver = {
3016                    .name = CARDNAME,
3017                    .pm = SH_ETH_PM_OPS,
3018                    .of_match_table = of_match_ptr(sh_eth_match_table),
3019         },
3020 };
3021
3022 module_platform_driver(sh_eth_driver);
3023
3024 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3025 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3026 MODULE_LICENSE("GPL v2");