drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   5  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *
  16  *  The full GNU General Public License is included in this distribution in
  17  *  the file called "COPYING".
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mdio-bitbang.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_net.h>
  34 #include <linux/phy.h>
  35 #include <linux/cache.h>
  36 #include <linux/io.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/slab.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/clk.h>
  42 #include <linux/sh_eth.h>
  43
  44 #include "sh_eth.h"
  45
  46 #define SH_ETH_DEF_MSG_ENABLE \
  47                 (NETIF_MSG_LINK | \
  48                 NETIF_MSG_TIMER | \
  49                 NETIF_MSG_RX_ERR| \
  50                 NETIF_MSG_TX_ERR)
  51
  52 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  53         [EDSR]          = 0x0000,
  54         [EDMR]          = 0x0400,
  55         [EDTRR]         = 0x0408,
  56         [EDRRR]         = 0x0410,
  57         [EESR]          = 0x0428,
  58         [EESIPR]        = 0x0430,
  59         [TDLAR]         = 0x0010,
  60         [TDFAR]         = 0x0014,
  61         [TDFXR]         = 0x0018,
  62         [TDFFR]         = 0x001c,
  63         [RDLAR]         = 0x0030,
  64         [RDFAR]         = 0x0034,
  65         [RDFXR]         = 0x0038,
  66         [RDFFR]         = 0x003c,
  67         [TRSCER]        = 0x0438,
  68         [RMFCR]         = 0x0440,
  69         [TFTR]          = 0x0448,
  70         [FDR]           = 0x0450,
  71         [RMCR]          = 0x0458,
  72         [RPADIR]        = 0x0460,
  73         [FCFTR]         = 0x0468,
  74         [CSMR]          = 0x04E4,
  75
  76         [ECMR]          = 0x0500,
  77         [ECSR]          = 0x0510,
  78         [ECSIPR]        = 0x0518,
  79         [PIR]           = 0x0520,
  80         [PSR]           = 0x0528,
  81         [PIPR]          = 0x052c,
  82         [RFLR]          = 0x0508,
  83         [APR]           = 0x0554,
  84         [MPR]           = 0x0558,
  85         [PFTCR]         = 0x055c,
  86         [PFRCR]         = 0x0560,
  87         [TPAUSER]       = 0x0564,
  88         [GECMR]         = 0x05b0,
  89         [BCULR]         = 0x05b4,
  90         [MAHR]          = 0x05c0,
  91         [MALR]          = 0x05c8,
  92         [TROCR]         = 0x0700,
  93         [CDCR]          = 0x0708,
  94         [LCCR]          = 0x0710,
  95         [CEFCR]         = 0x0740,
  96         [FRECR]         = 0x0748,
  97         [TSFRCR]        = 0x0750,
  98         [TLFRCR]        = 0x0758,
  99         [RFCR]          = 0x0760,
 100         [CERCR]         = 0x0768,
 101         [CEECR]         = 0x0770,
 102         [MAFCR]         = 0x0778,
 103         [RMII_MII]      = 0x0790,
 104
 105         [ARSTR]         = 0x0000,
 106         [TSU_CTRST]     = 0x0004,
 107         [TSU_FWEN0]     = 0x0010,
 108         [TSU_FWEN1]     = 0x0014,
 109         [TSU_FCM]       = 0x0018,
 110         [TSU_BSYSL0]    = 0x0020,
 111         [TSU_BSYSL1]    = 0x0024,
 112         [TSU_PRISL0]    = 0x0028,
 113         [TSU_PRISL1]    = 0x002c,
 114         [TSU_FWSL0]     = 0x0030,
 115         [TSU_FWSL1]     = 0x0034,
 116         [TSU_FWSLC]     = 0x0038,
 117         [TSU_QTAG0]     = 0x0040,
 118         [TSU_QTAG1]     = 0x0044,
 119         [TSU_FWSR]      = 0x0050,
 120         [TSU_FWINMK]    = 0x0054,
 121         [TSU_ADQT0]     = 0x0048,
 122         [TSU_ADQT1]     = 0x004c,
 123         [TSU_VTAG0]     = 0x0058,
 124         [TSU_VTAG1]     = 0x005c,
 125         [TSU_ADSBSY]    = 0x0060,
 126         [TSU_TEN]       = 0x0064,
 127         [TSU_POST1]     = 0x0070,
 128         [TSU_POST2]     = 0x0074,
 129         [TSU_POST3]     = 0x0078,
 130         [TSU_POST4]     = 0x007c,
 131         [TSU_ADRH0]     = 0x0100,
 132         [TSU_ADRL0]     = 0x0104,
 133         [TSU_ADRH31]    = 0x01f8,
 134         [TSU_ADRL31]    = 0x01fc,
 135
 136         [TXNLCR0]       = 0x0080,
 137         [TXALCR0]       = 0x0084,
 138         [RXNLCR0]       = 0x0088,
 139         [RXALCR0]       = 0x008c,
 140         [FWNLCR0]       = 0x0090,
 141         [FWALCR0]       = 0x0094,
 142         [TXNLCR1]       = 0x00a0,
 143         [TXALCR1]       = 0x00a0,
 144         [RXNLCR1]       = 0x00a8,
 145         [RXALCR1]       = 0x00ac,
 146         [FWNLCR1]       = 0x00b0,
 147         [FWALCR1]       = 0x00b4,
 148 };
 149
 150 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 151         [EDSR]          = 0x0000,
 152         [EDMR]          = 0x0400,
 153         [EDTRR]         = 0x0408,
 154         [EDRRR]         = 0x0410,
 155         [EESR]          = 0x0428,
 156         [EESIPR]        = 0x0430,
 157         [TDLAR]         = 0x0010,
 158         [TDFAR]         = 0x0014,
 159         [TDFXR]         = 0x0018,
 160         [TDFFR]         = 0x001c,
 161         [RDLAR]         = 0x0030,
 162         [RDFAR]         = 0x0034,
 163         [RDFXR]         = 0x0038,
 164         [RDFFR]         = 0x003c,
 165         [TRSCER]        = 0x0438,
 166         [RMFCR]         = 0x0440,
 167         [TFTR]          = 0x0448,
 168         [FDR]           = 0x0450,
 169         [RMCR]          = 0x0458,
 170         [RPADIR]        = 0x0460,
 171         [FCFTR]         = 0x0468,
 172         [CSMR]          = 0x04E4,
 173
 174         [ECMR]          = 0x0500,
 175         [RFLR]          = 0x0508,
 176         [ECSR]          = 0x0510,
 177         [ECSIPR]        = 0x0518,
 178         [PIR]           = 0x0520,
 179         [APR]           = 0x0554,
 180         [MPR]           = 0x0558,
 181         [PFTCR]         = 0x055c,
 182         [PFRCR]         = 0x0560,
 183         [TPAUSER]       = 0x0564,
 184         [MAHR]          = 0x05c0,
 185         [MALR]          = 0x05c8,
 186         [CEFCR]         = 0x0740,
 187         [FRECR]         = 0x0748,
 188         [TSFRCR]        = 0x0750,
 189         [TLFRCR]        = 0x0758,
 190         [RFCR]          = 0x0760,
 191         [MAFCR]         = 0x0778,
 192
 193         [ARSTR]         = 0x0000,
 194         [TSU_CTRST]     = 0x0004,
 195         [TSU_VTAG0]     = 0x0058,
 196         [TSU_ADSBSY]    = 0x0060,
 197         [TSU_TEN]       = 0x0064,
 198         [TSU_ADRH0]     = 0x0100,
 199         [TSU_ADRL0]     = 0x0104,
 200         [TSU_ADRH31]    = 0x01f8,
 201         [TSU_ADRL31]    = 0x01fc,
 202
 203         [TXNLCR0]       = 0x0080,
 204         [TXALCR0]       = 0x0084,
 205         [RXNLCR0]       = 0x0088,
 206         [RXALCR0]       = 0x008C,
 207 };
 208
 209 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 210         [ECMR]          = 0x0300,
 211         [RFLR]          = 0x0308,
 212         [ECSR]          = 0x0310,
 213         [ECSIPR]        = 0x0318,
 214         [PIR]           = 0x0320,
 215         [PSR]           = 0x0328,
 216         [RDMLR]         = 0x0340,
 217         [IPGR]          = 0x0350,
 218         [APR]           = 0x0354,
 219         [MPR]           = 0x0358,
 220         [RFCF]          = 0x0360,
 221         [TPAUSER]       = 0x0364,
 222         [TPAUSECR]      = 0x0368,
 223         [MAHR]          = 0x03c0,
 224         [MALR]          = 0x03c8,
 225         [TROCR]         = 0x03d0,
 226         [CDCR]          = 0x03d4,
 227         [LCCR]          = 0x03d8,
 228         [CNDCR]         = 0x03dc,
 229         [CEFCR]         = 0x03e4,
 230         [FRECR]         = 0x03e8,
 231         [TSFRCR]        = 0x03ec,
 232         [TLFRCR]        = 0x03f0,
 233         [RFCR]          = 0x03f4,
 234         [MAFCR]         = 0x03f8,
 235
 236         [EDMR]          = 0x0200,
 237         [EDTRR]         = 0x0208,
 238         [EDRRR]         = 0x0210,
 239         [TDLAR]         = 0x0218,
 240         [RDLAR]         = 0x0220,
 241         [EESR]          = 0x0228,
 242         [EESIPR]        = 0x0230,
 243         [TRSCER]        = 0x0238,
 244         [RMFCR]         = 0x0240,
 245         [TFTR]          = 0x0248,
 246         [FDR]           = 0x0250,
 247         [RMCR]          = 0x0258,
 248         [TFUCR]         = 0x0264,
 249         [RFOCR]         = 0x0268,
 250         [RMIIMODE]      = 0x026c,
 251         [FCFTR]         = 0x0270,
 252         [TRIMD]         = 0x027c,
 253 };
 254
 255 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 256         [ECMR]          = 0x0100,
 257         [RFLR]          = 0x0108,
 258         [ECSR]          = 0x0110,
 259         [ECSIPR]        = 0x0118,
 260         [PIR]           = 0x0120,
 261         [PSR]           = 0x0128,
 262         [RDMLR]         = 0x0140,
 263         [IPGR]          = 0x0150,
 264         [APR]           = 0x0154,
 265         [MPR]           = 0x0158,
 266         [TPAUSER]       = 0x0164,
 267         [RFCF]          = 0x0160,
 268         [TPAUSECR]      = 0x0168,
 269         [BCFRR]         = 0x016c,
 270         [MAHR]          = 0x01c0,
 271         [MALR]          = 0x01c8,
 272         [TROCR]         = 0x01d0,
 273         [CDCR]          = 0x01d4,
 274         [LCCR]          = 0x01d8,
 275         [CNDCR]         = 0x01dc,
 276         [CEFCR]         = 0x01e4,
 277         [FRECR]         = 0x01e8,
 278         [TSFRCR]        = 0x01ec,
 279         [TLFRCR]        = 0x01f0,
 280         [RFCR]          = 0x01f4,
 281         [MAFCR]         = 0x01f8,
 282         [RTRATE]        = 0x01fc,
 283
 284         [EDMR]          = 0x0000,
 285         [EDTRR]         = 0x0008,
 286         [EDRRR]         = 0x0010,
 287         [TDLAR]         = 0x0018,
 288         [RDLAR]         = 0x0020,
 289         [EESR]          = 0x0028,
 290         [EESIPR]        = 0x0030,
 291         [TRSCER]        = 0x0038,
 292         [RMFCR]         = 0x0040,
 293         [TFTR]          = 0x0048,
 294         [FDR]           = 0x0050,
 295         [RMCR]          = 0x0058,
 296         [TFUCR]         = 0x0064,
 297         [RFOCR]         = 0x0068,
 298         [FCFTR]         = 0x0070,
 299         [RPADIR]        = 0x0078,
 300         [TRIMD]         = 0x007c,
 301         [RBWAR]         = 0x00c8,
 302         [RDFAR]         = 0x00cc,
 303         [TBRAR]         = 0x00d4,
 304         [TDFAR]         = 0x00d8,
 305 };
 306
 307 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 308         [EDMR]          = 0x0000,
 309         [EDTRR]         = 0x0004,
 310         [EDRRR]         = 0x0008,
 311         [TDLAR]         = 0x000c,
 312         [RDLAR]         = 0x0010,
 313         [EESR]          = 0x0014,
 314         [EESIPR]        = 0x0018,
 315         [TRSCER]        = 0x001c,
 316         [RMFCR]         = 0x0020,
 317         [TFTR]          = 0x0024,
 318         [FDR]           = 0x0028,
 319         [RMCR]          = 0x002c,
 320         [EDOCR]         = 0x0030,
 321         [FCFTR]         = 0x0034,
 322         [RPADIR]        = 0x0038,
 323         [TRIMD]         = 0x003c,
 324         [RBWAR]         = 0x0040,
 325         [RDFAR]         = 0x0044,
 326         [TBRAR]         = 0x004c,
 327         [TDFAR]         = 0x0050,
 328
 329         [ECMR]          = 0x0160,
 330         [ECSR]          = 0x0164,
 331         [ECSIPR]        = 0x0168,
 332         [PIR]           = 0x016c,
 333         [MAHR]          = 0x0170,
 334         [MALR]          = 0x0174,
 335         [RFLR]          = 0x0178,
 336         [PSR]           = 0x017c,
 337         [TROCR]         = 0x0180,
 338         [CDCR]          = 0x0184,
 339         [LCCR]          = 0x0188,
 340         [CNDCR]         = 0x018c,
 341         [CEFCR]         = 0x0194,
 342         [FRECR]         = 0x0198,
 343         [TSFRCR]        = 0x019c,
 344         [TLFRCR]        = 0x01a0,
 345         [RFCR]          = 0x01a4,
 346         [MAFCR]         = 0x01a8,
 347         [IPGR]          = 0x01b4,
 348         [APR]           = 0x01b8,
 349         [MPR]           = 0x01bc,
 350         [TPAUSER]       = 0x01c4,
 351         [BCFR]          = 0x01cc,
 352
 353         [ARSTR]         = 0x0000,
 354         [TSU_CTRST]     = 0x0004,
 355         [TSU_FWEN0]     = 0x0010,
 356         [TSU_FWEN1]     = 0x0014,
 357         [TSU_FCM]       = 0x0018,
 358         [TSU_BSYSL0]    = 0x0020,
 359         [TSU_BSYSL1]    = 0x0024,
 360         [TSU_PRISL0]    = 0x0028,
 361         [TSU_PRISL1]    = 0x002c,
 362         [TSU_FWSL0]     = 0x0030,
 363         [TSU_FWSL1]     = 0x0034,
 364         [TSU_FWSLC]     = 0x0038,
 365         [TSU_QTAGM0]    = 0x0040,
 366         [TSU_QTAGM1]    = 0x0044,
 367         [TSU_ADQT0]     = 0x0048,
 368         [TSU_ADQT1]     = 0x004c,
 369         [TSU_FWSR]      = 0x0050,
 370         [TSU_FWINMK]    = 0x0054,
 371         [TSU_ADSBSY]    = 0x0060,
 372         [TSU_TEN]       = 0x0064,
 373         [TSU_POST1]     = 0x0070,
 374         [TSU_POST2]     = 0x0074,
 375         [TSU_POST3]     = 0x0078,
 376         [TSU_POST4]     = 0x007c,
 377
 378         [TXNLCR0]       = 0x0080,
 379         [TXALCR0]       = 0x0084,
 380         [RXNLCR0]       = 0x0088,
 381         [RXALCR0]       = 0x008c,
 382         [FWNLCR0]       = 0x0090,
 383         [FWALCR0]       = 0x0094,
 384         [TXNLCR1]       = 0x00a0,
 385         [TXALCR1]       = 0x00a0,
 386         [RXNLCR1]       = 0x00a8,
 387         [RXALCR1]       = 0x00ac,
 388         [FWNLCR1]       = 0x00b0,
 389         [FWALCR1]       = 0x00b4,
 390
 391         [TSU_ADRH0]     = 0x0100,
 392         [TSU_ADRL0]     = 0x0104,
 393         [TSU_ADRL31]    = 0x01fc,
 394 };
 395
 396 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 397 {
 398         return mdp->reg_offset == sh_eth_offset_gigabit;
 399 }
 400
 401 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 402 {
 403         return mdp->reg_offset == sh_eth_offset_fast_rz;
 404 }
 405
 406 static void sh_eth_select_mii(struct net_device *ndev)
 407 {
 408         u32 value = 0x0;
 409         struct sh_eth_private *mdp = netdev_priv(ndev);
 410
 411         switch (mdp->phy_interface) {
 412         case PHY_INTERFACE_MODE_GMII:
 413                 value = 0x2;
 414                 break;
 415         case PHY_INTERFACE_MODE_MII:
 416                 value = 0x1;
 417                 break;
 418         case PHY_INTERFACE_MODE_RMII:
 419                 value = 0x0;
 420                 break;
 421         default:
 422                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 423                 value = 0x1;
 424                 break;
 425         }
 426
 427         sh_eth_write(ndev, value, RMII_MII);
 428 }
 429
 430 static void sh_eth_set_duplex(struct net_device *ndev)
 431 {
 432         struct sh_eth_private *mdp = netdev_priv(ndev);
 433
 434         if (mdp->duplex) /* Full */
 435                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 436         else            /* Half */
 437                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 438 }
 439
 440 /* There is CPU dependent code */
 441 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 442 {
 443         struct sh_eth_private *mdp = netdev_priv(ndev);
 444
 445         switch (mdp->speed) {
 446         case 10: /* 10BASE */
 447                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 448                 break;
 449         case 100:/* 100BASE */
 450                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 451                 break;
 452         default:
 453                 break;
 454         }
 455 }
 456
 457 /* R8A7778/9 */
 458 static struct sh_eth_cpu_data r8a777x_data = {
 459         .set_duplex     = sh_eth_set_duplex,
 460         .set_rate       = sh_eth_set_rate_r8a777x,
 461
 462         .register_type  = SH_ETH_REG_FAST_RCAR,
 463
 464         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 465         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 466         .eesipr_value   = 0x01ff009f,
 467
 468         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 469         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 470                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 471                           EESR_ECI,
 472
 473         .apr            = 1,
 474         .mpr            = 1,
 475         .tpauser        = 1,
 476         .hw_swap        = 1,
 477 };
 478
 479 /* R8A7790/1 */
 480 static struct sh_eth_cpu_data r8a779x_data = {
 481         .set_duplex     = sh_eth_set_duplex,
 482         .set_rate       = sh_eth_set_rate_r8a777x,
 483
 484         .register_type  = SH_ETH_REG_FAST_RCAR,
 485
 486         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 487         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 488         .eesipr_value   = 0x01ff009f,
 489
 490         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 491         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 492                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 493                           EESR_ECI,
 494
 495         .apr            = 1,
 496         .mpr            = 1,
 497         .tpauser        = 1,
 498         .hw_swap        = 1,
 499         .rmiimode       = 1,
 500         .shift_rd0      = 1,
 501 };
 502
 503 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 504 {
 505         struct sh_eth_private *mdp = netdev_priv(ndev);
 506
 507         switch (mdp->speed) {
 508         case 10: /* 10BASE */
 509                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 510                 break;
 511         case 100:/* 100BASE */
 512                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 513                 break;
 514         default:
 515                 break;
 516         }
 517 }
 518
 519 /* SH7724 */
 520 static struct sh_eth_cpu_data sh7724_data = {
 521         .set_duplex     = sh_eth_set_duplex,
 522         .set_rate       = sh_eth_set_rate_sh7724,
 523
 524         .register_type  = SH_ETH_REG_FAST_SH4,
 525
 526         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 527         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 528         .eesipr_value   = 0x01ff009f,
 529
 530         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 531         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 532                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 533                           EESR_ECI,
 534
 535         .apr            = 1,
 536         .mpr            = 1,
 537         .tpauser        = 1,
 538         .hw_swap        = 1,
 539         .rpadir         = 1,
 540         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 541 };
 542
 543 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 544 {
 545         struct sh_eth_private *mdp = netdev_priv(ndev);
 546
 547         switch (mdp->speed) {
 548         case 10: /* 10BASE */
 549                 sh_eth_write(ndev, 0, RTRATE);
 550                 break;
 551         case 100:/* 100BASE */
 552                 sh_eth_write(ndev, 1, RTRATE);
 553                 break;
 554         default:
 555                 break;
 556         }
 557 }
 558
 559 /* SH7757 */
 560 static struct sh_eth_cpu_data sh7757_data = {
 561         .set_duplex     = sh_eth_set_duplex,
 562         .set_rate       = sh_eth_set_rate_sh7757,
 563
 564         .register_type  = SH_ETH_REG_FAST_SH4,
 565
 566         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 567
 568         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 569         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 570                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 571                           EESR_ECI,
 572
 573         .irq_flags      = IRQF_SHARED,
 574         .apr            = 1,
 575         .mpr            = 1,
 576         .tpauser        = 1,
 577         .hw_swap        = 1,
 578         .no_ade         = 1,
 579         .rpadir         = 1,
 580         .rpadir_value   = 2 << 16,
 581 };
 582
 583 #define SH_GIGA_ETH_BASE        0xfee00000UL
 584 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 585 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 586 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 587 {
 588         int i;
 589         unsigned long mahr[2], malr[2];
 590
 591         /* save MAHR and MALR */
 592         for (i = 0; i < 2; i++) {
 593                 malr[i] = ioread32((void *)GIGA_MALR(i));
 594                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 595         }
 596
 597         /* reset device */
 598         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 599         mdelay(1);
 600
 601         /* restore MAHR and MALR */
 602         for (i = 0; i < 2; i++) {
 603                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 604                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 605         }
 606 }
 607
 608 static void sh_eth_set_rate_giga(struct net_device *ndev)
 609 {
 610         struct sh_eth_private *mdp = netdev_priv(ndev);
 611
 612         switch (mdp->speed) {
 613         case 10: /* 10BASE */
 614                 sh_eth_write(ndev, 0x00000000, GECMR);
 615                 break;
 616         case 100:/* 100BASE */
 617                 sh_eth_write(ndev, 0x00000010, GECMR);
 618                 break;
 619         case 1000: /* 1000BASE */
 620                 sh_eth_write(ndev, 0x00000020, GECMR);
 621                 break;
 622         default:
 623                 break;
 624         }
 625 }
 626
 627 /* SH7757(GETHERC) */
 628 static struct sh_eth_cpu_data sh7757_data_giga = {
 629         .chip_reset     = sh_eth_chip_reset_giga,
 630         .set_duplex     = sh_eth_set_duplex,
 631         .set_rate       = sh_eth_set_rate_giga,
 632
 633         .register_type  = SH_ETH_REG_GIGABIT,
 634
 635         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 636         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 637         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 638
 639         .tx_check       = EESR_TC1 | EESR_FTC,
 640         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 641                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 642                           EESR_TDE | EESR_ECI,
 643         .fdr_value      = 0x0000072f,
 644
 645         .irq_flags      = IRQF_SHARED,
 646         .apr            = 1,
 647         .mpr            = 1,
 648         .tpauser        = 1,
 649         .bculr          = 1,
 650         .hw_swap        = 1,
 651         .rpadir         = 1,
 652         .rpadir_value   = 2 << 16,
 653         .no_trimd       = 1,
 654         .no_ade         = 1,
 655         .tsu            = 1,
 656 };
 657
 658 static void sh_eth_chip_reset(struct net_device *ndev)
 659 {
 660         struct sh_eth_private *mdp = netdev_priv(ndev);
 661
 662         /* reset device */
 663         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 664         mdelay(1);
 665 }
 666
 667 static void sh_eth_set_rate_gether(struct net_device *ndev)
 668 {
 669         struct sh_eth_private *mdp = netdev_priv(ndev);
 670
 671         switch (mdp->speed) {
 672         case 10: /* 10BASE */
 673                 sh_eth_write(ndev, GECMR_10, GECMR);
 674                 break;
 675         case 100:/* 100BASE */
 676                 sh_eth_write(ndev, GECMR_100, GECMR);
 677                 break;
 678         case 1000: /* 1000BASE */
 679                 sh_eth_write(ndev, GECMR_1000, GECMR);
 680                 break;
 681         default:
 682                 break;
 683         }
 684 }
 685
 686 /* SH7734 */
 687 static struct sh_eth_cpu_data sh7734_data = {
 688         .chip_reset     = sh_eth_chip_reset,
 689         .set_duplex     = sh_eth_set_duplex,
 690         .set_rate       = sh_eth_set_rate_gether,
 691
 692         .register_type  = SH_ETH_REG_GIGABIT,
 693
 694         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 695         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 696         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 697
 698         .tx_check       = EESR_TC1 | EESR_FTC,
 699         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 700                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 701                           EESR_TDE | EESR_ECI,
 702
 703         .apr            = 1,
 704         .mpr            = 1,
 705         .tpauser        = 1,
 706         .bculr          = 1,
 707         .hw_swap        = 1,
 708         .no_trimd       = 1,
 709         .no_ade         = 1,
 710         .tsu            = 1,
 711         .hw_crc         = 1,
 712         .select_mii     = 1,
 713 };
 714
 715 /* SH7763 */
 716 static struct sh_eth_cpu_data sh7763_data = {
 717         .chip_reset     = sh_eth_chip_reset,
 718         .set_duplex     = sh_eth_set_duplex,
 719         .set_rate       = sh_eth_set_rate_gether,
 720
 721         .register_type  = SH_ETH_REG_GIGABIT,
 722
 723         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 724         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 725         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 726
 727         .tx_check       = EESR_TC1 | EESR_FTC,
 728         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 729                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 730                           EESR_ECI,
 731
 732         .apr            = 1,
 733         .mpr            = 1,
 734         .tpauser        = 1,
 735         .bculr          = 1,
 736         .hw_swap        = 1,
 737         .no_trimd       = 1,
 738         .no_ade         = 1,
 739         .tsu            = 1,
 740         .irq_flags      = IRQF_SHARED,
 741 };
 742
 743 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 744 {
 745         struct sh_eth_private *mdp = netdev_priv(ndev);
 746
 747         /* reset device */
 748         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 749         mdelay(1);
 750
 751         sh_eth_select_mii(ndev);
 752 }
 753
 754 /* R8A7740 */
 755 static struct sh_eth_cpu_data r8a7740_data = {
 756         .chip_reset     = sh_eth_chip_reset_r8a7740,
 757         .set_duplex     = sh_eth_set_duplex,
 758         .set_rate       = sh_eth_set_rate_gether,
 759
 760         .register_type  = SH_ETH_REG_GIGABIT,
 761
 762         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 763         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 764         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 765
 766         .tx_check       = EESR_TC1 | EESR_FTC,
 767         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 768                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 769                           EESR_TDE | EESR_ECI,
 770         .fdr_value      = 0x0000070f,
 771
 772         .apr            = 1,
 773         .mpr            = 1,
 774         .tpauser        = 1,
 775         .bculr          = 1,
 776         .hw_swap        = 1,
 777         .rpadir         = 1,
 778         .rpadir_value   = 2 << 16,
 779         .no_trimd       = 1,
 780         .no_ade         = 1,
 781         .tsu            = 1,
 782         .select_mii     = 1,
 783         .shift_rd0      = 1,
 784 };
 785
 786 /* R7S72100 */
 787 static struct sh_eth_cpu_data r7s72100_data = {
 788         .chip_reset     = sh_eth_chip_reset,
 789         .set_duplex     = sh_eth_set_duplex,
 790
 791         .register_type  = SH_ETH_REG_FAST_RZ,
 792
 793         .ecsr_value     = ECSR_ICD,
 794         .ecsipr_value   = ECSIPR_ICDIP,
 795         .eesipr_value   = 0xff7f009f,
 796
 797         .tx_check       = EESR_TC1 | EESR_FTC,
 798         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 799                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 800                           EESR_TDE | EESR_ECI,
 801         .fdr_value      = 0x0000070f,
 802
 803         .no_psr         = 1,
 804         .apr            = 1,
 805         .mpr            = 1,
 806         .tpauser        = 1,
 807         .hw_swap        = 1,
 808         .rpadir         = 1,
 809         .rpadir_value   = 2 << 16,
 810         .no_trimd       = 1,
 811         .no_ade         = 1,
 812         .hw_crc         = 1,
 813         .tsu            = 1,
 814         .shift_rd0      = 1,
 815 };
 816
 817 static struct sh_eth_cpu_data sh7619_data = {
 818         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 819
 820         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 821
 822         .apr            = 1,
 823         .mpr            = 1,
 824         .tpauser        = 1,
 825         .hw_swap        = 1,
 826 };
 827
 828 static struct sh_eth_cpu_data sh771x_data = {
 829         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 830
 831         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 832         .tsu            = 1,
 833 };
 834
 835 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 836 {
 837         if (!cd->ecsr_value)
 838                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 839
 840         if (!cd->ecsipr_value)
 841                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 842
 843         if (!cd->fcftr_value)
 844                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 845                                   DEFAULT_FIFO_F_D_RFD;
 846
 847         if (!cd->fdr_value)
 848                 cd->fdr_value = DEFAULT_FDR_INIT;
 849
 850         if (!cd->tx_check)
 851                 cd->tx_check = DEFAULT_TX_CHECK;
 852
 853         if (!cd->eesr_err_check)
 854                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 855 }
 856
 857 static int sh_eth_check_reset(struct net_device *ndev)
 858 {
 859         int ret = 0;
 860         int cnt = 100;
 861
 862         while (cnt > 0) {
 863                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 864                         break;
 865                 mdelay(1);
 866                 cnt--;
 867         }
 868         if (cnt <= 0) {
 869                 pr_err("Device reset failed\n");
 870                 ret = -ETIMEDOUT;
 871         }
 872         return ret;
 873 }
 874
 875 static int sh_eth_reset(struct net_device *ndev)
 876 {
 877         struct sh_eth_private *mdp = netdev_priv(ndev);
 878         int ret = 0;
 879
 880         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 881                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 882                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 883                              EDMR);
 884
 885                 ret = sh_eth_check_reset(ndev);
 886                 if (ret)
 887                         goto out;
 888
 889                 /* Table Init */
 890                 sh_eth_write(ndev, 0x0, TDLAR);
 891                 sh_eth_write(ndev, 0x0, TDFAR);
 892                 sh_eth_write(ndev, 0x0, TDFXR);
 893                 sh_eth_write(ndev, 0x0, TDFFR);
 894                 sh_eth_write(ndev, 0x0, RDLAR);
 895                 sh_eth_write(ndev, 0x0, RDFAR);
 896                 sh_eth_write(ndev, 0x0, RDFXR);
 897                 sh_eth_write(ndev, 0x0, RDFFR);
 898
 899                 /* Reset HW CRC register */
 900                 if (mdp->cd->hw_crc)
 901                         sh_eth_write(ndev, 0x0, CSMR);
 902
 903                 /* Select MII mode */
 904                 if (mdp->cd->select_mii)
 905                         sh_eth_select_mii(ndev);
 906         } else {
 907                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 908                              EDMR);
 909                 mdelay(3);
 910                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 911                              EDMR);
 912         }
 913
 914 out:
 915         return ret;
 916 }
 917
 918 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 919 static void sh_eth_set_receive_align(struct sk_buff *skb)
 920 {
 921         int reserve;
 922
 923         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 924         if (reserve)
 925                 skb_reserve(skb, reserve);
 926 }
 927 #else
 928 static void sh_eth_set_receive_align(struct sk_buff *skb)
 929 {
 930         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 931 }
 932 #endif
 933
 934
 935 /* CPU <-> EDMAC endian convert */
 936 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 937 {
 938         switch (mdp->edmac_endian) {
 939         case EDMAC_LITTLE_ENDIAN:
 940                 return cpu_to_le32(x);
 941         case EDMAC_BIG_ENDIAN:
 942                 return cpu_to_be32(x);
 943         }
 944         return x;
 945 }
 946
 947 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 948 {
 949         switch (mdp->edmac_endian) {
 950         case EDMAC_LITTLE_ENDIAN:
 951                 return le32_to_cpu(x);
 952         case EDMAC_BIG_ENDIAN:
 953                 return be32_to_cpu(x);
 954         }
 955         return x;
 956 }
 957
 958 /* Program the hardware MAC address from dev->dev_addr. */
 959 static void update_mac_address(struct net_device *ndev)
 960 {
 961         sh_eth_write(ndev,
 962                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 963                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 964         sh_eth_write(ndev,
 965                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 966 }
 967
 968 /* Get MAC address from SuperH MAC address register
 969  *
 970  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 971  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 972  * When you want use this device, you must set MAC address in bootloader.
 973  *
 974  */
 975 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 976 {
 977         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 978                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 979         } else {
 980                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 981                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 982                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 983                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 984                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 985                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 986         }
 987 }
 988
 989 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 990 {
 991         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 992                 return EDTRR_TRNS_GETHER;
 993         else
 994                 return EDTRR_TRNS_ETHER;
 995 }
 996
 997 struct bb_info {
 998         void (*set_gate)(void *addr);
 999         struct mdiobb_ctrl ctrl;
1000         void *addr;
1001         u32 mmd_msk;/* MMD */
1002         u32 mdo_msk;
1003         u32 mdi_msk;
1004         u32 mdc_msk;
1005 };
1006
1007 /* PHY bit set */
1008 static void bb_set(void *addr, u32 msk)
1009 {
1010         iowrite32(ioread32(addr) | msk, addr);
1011 }
1012
1013 /* PHY bit clear */
1014 static void bb_clr(void *addr, u32 msk)
1015 {
1016         iowrite32((ioread32(addr) & ~msk), addr);
1017 }
1018
1019 /* PHY bit read */
1020 static int bb_read(void *addr, u32 msk)
1021 {
1022         return (ioread32(addr) & msk) != 0;
1023 }
1024
1025 /* Data I/O pin control */
1026 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027 {
1028         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1029
1030         if (bitbang->set_gate)
1031                 bitbang->set_gate(bitbang->addr);
1032
1033         if (bit)
1034                 bb_set(bitbang->addr, bitbang->mmd_msk);
1035         else
1036                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1037 }
1038
1039 /* Set bit data*/
1040 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1041 {
1042         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1043
1044         if (bitbang->set_gate)
1045                 bitbang->set_gate(bitbang->addr);
1046
1047         if (bit)
1048                 bb_set(bitbang->addr, bitbang->mdo_msk);
1049         else
1050                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1051 }
1052
1053 /* Get bit data*/
1054 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1055 {
1056         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1057
1058         if (bitbang->set_gate)
1059                 bitbang->set_gate(bitbang->addr);
1060
1061         return bb_read(bitbang->addr, bitbang->mdi_msk);
1062 }
1063
1064 /* MDC pin control */
1065 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1066 {
1067         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1068
1069         if (bitbang->set_gate)
1070                 bitbang->set_gate(bitbang->addr);
1071
1072         if (bit)
1073                 bb_set(bitbang->addr, bitbang->mdc_msk);
1074         else
1075                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1076 }
1077
1078 /* mdio bus control struct */
1079 static struct mdiobb_ops bb_ops = {
1080         .owner = THIS_MODULE,
1081         .set_mdc = sh_mdc_ctrl,
1082         .set_mdio_dir = sh_mmd_ctrl,
1083         .set_mdio_data = sh_set_mdio,
1084         .get_mdio_data = sh_get_mdio,
1085 };
1086
1087 /* free skb and descriptor buffer */
1088 static void sh_eth_ring_free(struct net_device *ndev)
1089 {
1090         struct sh_eth_private *mdp = netdev_priv(ndev);
1091         int i;
1092
1093         /* Free Rx skb ringbuffer */
1094         if (mdp->rx_skbuff) {
1095                 for (i = 0; i < mdp->num_rx_ring; i++) {
1096                         if (mdp->rx_skbuff[i])
1097                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1098                 }
1099         }
1100         kfree(mdp->rx_skbuff);
1101         mdp->rx_skbuff = NULL;
1102
1103         /* Free Tx skb ringbuffer */
1104         if (mdp->tx_skbuff) {
1105                 for (i = 0; i < mdp->num_tx_ring; i++) {
1106                         if (mdp->tx_skbuff[i])
1107                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1108                 }
1109         }
1110         kfree(mdp->tx_skbuff);
1111         mdp->tx_skbuff = NULL;
1112 }
1113
1114 /* format skb and descriptor buffer */
1115 static void sh_eth_ring_format(struct net_device *ndev)
1116 {
1117         struct sh_eth_private *mdp = netdev_priv(ndev);
1118         int i;
1119         struct sk_buff *skb;
1120         struct sh_eth_rxdesc *rxdesc = NULL;
1121         struct sh_eth_txdesc *txdesc = NULL;
1122         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1123         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1124
1125         mdp->cur_rx = 0;
1126         mdp->cur_tx = 0;
1127         mdp->dirty_rx = 0;
1128         mdp->dirty_tx = 0;
1129
1130         memset(mdp->rx_ring, 0, rx_ringsize);
1131
1132         /* build Rx ring buffer */
1133         for (i = 0; i < mdp->num_rx_ring; i++) {
1134                 /* skb */
1135                 mdp->rx_skbuff[i] = NULL;
1136                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1137                 mdp->rx_skbuff[i] = skb;
1138                 if (skb == NULL)
1139                         break;
1140                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1141                                DMA_FROM_DEVICE);
1142                 sh_eth_set_receive_align(skb);
1143
1144                 /* RX descriptor */
1145                 rxdesc = &mdp->rx_ring[i];
1146                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1147                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1148
1149                 /* The size of the buffer is 16 byte boundary. */
1150                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1151                 /* Rx descriptor address set */
1152                 if (i == 0) {
1153                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1154                         if (sh_eth_is_gether(mdp) ||
1155                             sh_eth_is_rz_fast_ether(mdp))
1156                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1157                 }
1158         }
1159
1160         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1161
1162         /* Mark the last entry as wrapping the ring. */
1163         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1164
1165         memset(mdp->tx_ring, 0, tx_ringsize);
1166
1167         /* build Tx ring buffer */
1168         for (i = 0; i < mdp->num_tx_ring; i++) {
1169                 mdp->tx_skbuff[i] = NULL;
1170                 txdesc = &mdp->tx_ring[i];
1171                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1172                 txdesc->buffer_length = 0;
1173                 if (i == 0) {
1174                         /* Tx descriptor address set */
1175                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1176                         if (sh_eth_is_gether(mdp) ||
1177                             sh_eth_is_rz_fast_ether(mdp))
1178                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1179                 }
1180         }
1181
1182         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1183 }
1184
1185 /* Get skb and descriptor buffer */
1186 static int sh_eth_ring_init(struct net_device *ndev)
1187 {
1188         struct sh_eth_private *mdp = netdev_priv(ndev);
1189         int rx_ringsize, tx_ringsize, ret = 0;
1190
1191         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1192          * card needs room to do 8 byte alignment, +2 so we can reserve
1193          * the first 2 bytes, and +16 gets room for the status word from the
1194          * card.
1195          */
1196         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1197                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1198         if (mdp->cd->rpadir)
1199                 mdp->rx_buf_sz += NET_IP_ALIGN;
1200
1201         /* Allocate RX and TX skb rings */
1202         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1203                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1204         if (!mdp->rx_skbuff) {
1205                 ret = -ENOMEM;
1206                 return ret;
1207         }
1208
1209         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1210                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1211         if (!mdp->tx_skbuff) {
1212                 ret = -ENOMEM;
1213                 goto skb_ring_free;
1214         }
1215
1216         /* Allocate all Rx descriptors. */
1217         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1218         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1219                                           GFP_KERNEL);
1220         if (!mdp->rx_ring) {
1221                 ret = -ENOMEM;
1222                 goto desc_ring_free;
1223         }
1224
1225         mdp->dirty_rx = 0;
1226
1227         /* Allocate all Tx descriptors. */
1228         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1229         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1230                                           GFP_KERNEL);
1231         if (!mdp->tx_ring) {
1232                 ret = -ENOMEM;
1233                 goto desc_ring_free;
1234         }
1235         return ret;
1236
1237 desc_ring_free:
1238         /* free DMA buffer */
1239         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1240
1241 skb_ring_free:
1242         /* Free Rx and Tx skb ring buffer */
1243         sh_eth_ring_free(ndev);
1244         mdp->tx_ring = NULL;
1245         mdp->rx_ring = NULL;
1246
1247         return ret;
1248 }
1249
1250 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1251 {
1252         int ringsize;
1253
1254         if (mdp->rx_ring) {
1255                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1256                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1257                                   mdp->rx_desc_dma);
1258                 mdp->rx_ring = NULL;
1259         }
1260
1261         if (mdp->tx_ring) {
1262                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1263                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1264                                   mdp->tx_desc_dma);
1265                 mdp->tx_ring = NULL;
1266         }
1267 }
1268
1269 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1270 {
1271         int ret = 0;
1272         struct sh_eth_private *mdp = netdev_priv(ndev);
1273         u32 val;
1274
1275         /* Soft Reset */
1276         ret = sh_eth_reset(ndev);
1277         if (ret)
1278                 goto out;
1279
1280         if (mdp->cd->rmiimode)
1281                 sh_eth_write(ndev, 0x1, RMIIMODE);
1282
1283         /* Descriptor format */
1284         sh_eth_ring_format(ndev);
1285         if (mdp->cd->rpadir)
1286                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1287
1288         /* all sh_eth int mask */
1289         sh_eth_write(ndev, 0, EESIPR);
1290
1291 #if defined(__LITTLE_ENDIAN)
1292         if (mdp->cd->hw_swap)
1293                 sh_eth_write(ndev, EDMR_EL, EDMR);
1294         else
1295 #endif
1296                 sh_eth_write(ndev, 0, EDMR);
1297
1298         /* FIFO size set */
1299         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1300         sh_eth_write(ndev, 0, TFTR);
1301
1302         /* Frame recv control (enable multiple-packets per rx irq) */
1303         sh_eth_write(ndev, RMCR_RNC, RMCR);
1304
1305         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1306
1307         if (mdp->cd->bculr)
1308                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1309
1310         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1311
1312         if (!mdp->cd->no_trimd)
1313                 sh_eth_write(ndev, 0, TRIMD);
1314
1315         /* Recv frame limit set register */
1316         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1317                      RFLR);
1318
1319         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1320         if (start)
1321                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1322
1323         /* PAUSE Prohibition */
1324         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1325                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1326
1327         sh_eth_write(ndev, val, ECMR);
1328
1329         if (mdp->cd->set_rate)
1330                 mdp->cd->set_rate(ndev);
1331
1332         /* E-MAC Status Register clear */
1333         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1334
1335         /* E-MAC Interrupt Enable register */
1336         if (start)
1337                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1338
1339         /* Set MAC address */
1340         update_mac_address(ndev);
1341
1342         /* mask reset */
1343         if (mdp->cd->apr)
1344                 sh_eth_write(ndev, APR_AP, APR);
1345         if (mdp->cd->mpr)
1346                 sh_eth_write(ndev, MPR_MP, MPR);
1347         if (mdp->cd->tpauser)
1348                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1349
1350         if (start) {
1351                 /* Setting the Rx mode will start the Rx process. */
1352                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1353
1354                 netif_start_queue(ndev);
1355         }
1356
1357 out:
1358         return ret;
1359 }
1360
1361 /* free Tx skb function */
1362 static int sh_eth_txfree(struct net_device *ndev)
1363 {
1364         struct sh_eth_private *mdp = netdev_priv(ndev);
1365         struct sh_eth_txdesc *txdesc;
1366         int free_num = 0;
1367         int entry = 0;
1368
1369         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1370                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1371                 txdesc = &mdp->tx_ring[entry];
1372                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1373                         break;
1374                 /* Free the original skb. */
1375                 if (mdp->tx_skbuff[entry]) {
1376                         dma_unmap_single(&ndev->dev, txdesc->addr,
1377                                          txdesc->buffer_length, DMA_TO_DEVICE);
1378                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1379                         mdp->tx_skbuff[entry] = NULL;
1380                         free_num++;
1381                 }
1382                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1383                 if (entry >= mdp->num_tx_ring - 1)
1384                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1385
1386                 ndev->stats.tx_packets++;
1387                 ndev->stats.tx_bytes += txdesc->buffer_length;
1388         }
1389         return free_num;
1390 }
1391
1392 /* Packet receive function */
1393 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1394 {
1395         struct sh_eth_private *mdp = netdev_priv(ndev);
1396         struct sh_eth_rxdesc *rxdesc;
1397
1398         int entry = mdp->cur_rx % mdp->num_rx_ring;
1399         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1400         struct sk_buff *skb;
1401         int exceeded = 0;
1402         u16 pkt_len = 0;
1403         u32 desc_status;
1404
1405         rxdesc = &mdp->rx_ring[entry];
1406         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1407                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1408                 pkt_len = rxdesc->frame_length;
1409
1410                 if (--boguscnt < 0)
1411                         break;
1412
1413                 if (*quota <= 0) {
1414                         exceeded = 1;
1415                         break;
1416                 }
1417                 (*quota)--;
1418
1419                 if (!(desc_status & RDFEND))
1420                         ndev->stats.rx_length_errors++;
1421
1422                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1423                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1424                  * bit 0. However, in case of the R8A7740, R8A779x, and
1425                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1426                  * driver needs right shifting by 16.
1427                  */
1428                 if (mdp->cd->shift_rd0)
1429                         desc_status >>= 16;
1430
1431                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1432                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1433                         ndev->stats.rx_errors++;
1434                         if (desc_status & RD_RFS1)
1435                                 ndev->stats.rx_crc_errors++;
1436                         if (desc_status & RD_RFS2)
1437                                 ndev->stats.rx_frame_errors++;
1438                         if (desc_status & RD_RFS3)
1439                                 ndev->stats.rx_length_errors++;
1440                         if (desc_status & RD_RFS4)
1441                                 ndev->stats.rx_length_errors++;
1442                         if (desc_status & RD_RFS6)
1443                                 ndev->stats.rx_missed_errors++;
1444                         if (desc_status & RD_RFS10)
1445                                 ndev->stats.rx_over_errors++;
1446                 } else {
1447                         if (!mdp->cd->hw_swap)
1448                                 sh_eth_soft_swap(
1449                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1450                                         pkt_len + 2);
1451                         skb = mdp->rx_skbuff[entry];
1452                         mdp->rx_skbuff[entry] = NULL;
1453                         if (mdp->cd->rpadir)
1454                                 skb_reserve(skb, NET_IP_ALIGN);
1455                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1456                                                 mdp->rx_buf_sz,
1457                                                 DMA_FROM_DEVICE);
1458                         skb_put(skb, pkt_len);
1459                         skb->protocol = eth_type_trans(skb, ndev);
1460                         netif_receive_skb(skb);
1461                         ndev->stats.rx_packets++;
1462                         ndev->stats.rx_bytes += pkt_len;
1463                 }
1464                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1465                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1466                 rxdesc = &mdp->rx_ring[entry];
1467         }
1468
1469         /* Refill the Rx ring buffers. */
1470         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1471                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1472                 rxdesc = &mdp->rx_ring[entry];
1473                 /* The size of the buffer is 16 byte boundary. */
1474                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1475
1476                 if (mdp->rx_skbuff[entry] == NULL) {
1477                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1478                         mdp->rx_skbuff[entry] = skb;
1479                         if (skb == NULL)
1480                                 break;  /* Better luck next round. */
1481                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1482                                        DMA_FROM_DEVICE);
1483                         sh_eth_set_receive_align(skb);
1484
1485                         skb_checksum_none_assert(skb);
1486                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1487                 }
1488                 if (entry >= mdp->num_rx_ring - 1)
1489                         rxdesc->status |=
1490                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1491                 else
1492                         rxdesc->status |=
1493                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1494         }
1495
1496         /* Restart Rx engine if stopped. */
1497         /* If we don't need to check status, don't. -KDU */
1498         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1499                 /* fix the values for the next receiving if RDE is set */
1500                 if (intr_status & EESR_RDE) {
1501                         u32 count = (sh_eth_read(ndev, RDFAR) -
1502                                      sh_eth_read(ndev, RDLAR)) >> 4;
1503
1504                         mdp->cur_rx = count;
1505                         mdp->dirty_rx = count;
1506                 }
1507                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1508         }
1509
1510         return exceeded;
1511 }
1512
1513 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1514 {
1515         /* disable tx and rx */
1516         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1517                 ~(ECMR_RE | ECMR_TE), ECMR);
1518 }
1519
1520 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1521 {
1522         /* enable tx and rx */
1523         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1524                 (ECMR_RE | ECMR_TE), ECMR);
1525 }
1526
1527 /* error control function */
1528 static void sh_eth_error(struct net_device *ndev, int intr_status)
1529 {
1530         struct sh_eth_private *mdp = netdev_priv(ndev);
1531         u32 felic_stat;
1532         u32 link_stat;
1533         u32 mask;
1534
1535         if (intr_status & EESR_ECI) {
1536                 felic_stat = sh_eth_read(ndev, ECSR);
1537                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1538                 if (felic_stat & ECSR_ICD)
1539                         ndev->stats.tx_carrier_errors++;
1540                 if (felic_stat & ECSR_LCHNG) {
1541                         /* Link Changed */
1542                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1543                                 goto ignore_link;
1544                         } else {
1545                                 link_stat = (sh_eth_read(ndev, PSR));
1546                                 if (mdp->ether_link_active_low)
1547                                         link_stat = ~link_stat;
1548                         }
1549                         if (!(link_stat & PHY_ST_LINK)) {
1550                                 sh_eth_rcv_snd_disable(ndev);
1551                         } else {
1552                                 /* Link Up */
1553                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1554                                                    ~DMAC_M_ECI, EESIPR);
1555                                 /* clear int */
1556                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1557                                              ECSR);
1558                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1559                                                    DMAC_M_ECI, EESIPR);
1560                                 /* enable tx and rx */
1561                                 sh_eth_rcv_snd_enable(ndev);
1562                         }
1563                 }
1564         }
1565
1566 ignore_link:
1567         if (intr_status & EESR_TWB) {
1568                 /* Unused write back interrupt */
1569                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1570                         ndev->stats.tx_aborted_errors++;
1571                         if (netif_msg_tx_err(mdp))
1572                                 dev_err(&ndev->dev, "Transmit Abort\n");
1573                 }
1574         }
1575
1576         if (intr_status & EESR_RABT) {
1577                 /* Receive Abort int */
1578                 if (intr_status & EESR_RFRMER) {
1579                         /* Receive Frame Overflow int */
1580                         ndev->stats.rx_frame_errors++;
1581                         if (netif_msg_rx_err(mdp))
1582                                 dev_err(&ndev->dev, "Receive Abort\n");
1583                 }
1584         }
1585
1586         if (intr_status & EESR_TDE) {
1587                 /* Transmit Descriptor Empty int */
1588                 ndev->stats.tx_fifo_errors++;
1589                 if (netif_msg_tx_err(mdp))
1590                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1591         }
1592
1593         if (intr_status & EESR_TFE) {
1594                 /* FIFO under flow */
1595                 ndev->stats.tx_fifo_errors++;
1596                 if (netif_msg_tx_err(mdp))
1597                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1598         }
1599
1600         if (intr_status & EESR_RDE) {
1601                 /* Receive Descriptor Empty int */
1602                 ndev->stats.rx_over_errors++;
1603
1604                 if (netif_msg_rx_err(mdp))
1605                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1606         }
1607
1608         if (intr_status & EESR_RFE) {
1609                 /* Receive FIFO Overflow int */
1610                 ndev->stats.rx_fifo_errors++;
1611                 if (netif_msg_rx_err(mdp))
1612                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1613         }
1614
1615         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1616                 /* Address Error */
1617                 ndev->stats.tx_fifo_errors++;
1618                 if (netif_msg_tx_err(mdp))
1619                         dev_err(&ndev->dev, "Address Error\n");
1620         }
1621
1622         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1623         if (mdp->cd->no_ade)
1624                 mask &= ~EESR_ADE;
1625         if (intr_status & mask) {
1626                 /* Tx error */
1627                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1628
1629                 /* dmesg */
1630                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1631                         intr_status, mdp->cur_tx, mdp->dirty_tx,
1632                         (u32)ndev->state, edtrr);
1633                 /* dirty buffer free */
1634                 sh_eth_txfree(ndev);
1635
1636                 /* SH7712 BUG */
1637                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1638                         /* tx dma start */
1639                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1640                 }
1641                 /* wakeup */
1642                 netif_wake_queue(ndev);
1643         }
1644 }
1645
1646 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1647 {
1648         struct net_device *ndev = netdev;
1649         struct sh_eth_private *mdp = netdev_priv(ndev);
1650         struct sh_eth_cpu_data *cd = mdp->cd;
1651         irqreturn_t ret = IRQ_NONE;
1652         unsigned long intr_status, intr_enable;
1653
1654         spin_lock(&mdp->lock);
1655
1656         /* Get interrupt status */
1657         intr_status = sh_eth_read(ndev, EESR);
1658         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1659          * enabled since it's the one that  comes thru regardless of the mask,
1660          * and we need to fully handle it in sh_eth_error() in order to quench
1661          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1662          */
1663         intr_enable = sh_eth_read(ndev, EESIPR);
1664         intr_status &= intr_enable | DMAC_M_ECI;
1665         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1666                 ret = IRQ_HANDLED;
1667         else
1668                 goto other_irq;
1669
1670         if (intr_status & EESR_RX_CHECK) {
1671                 if (napi_schedule_prep(&mdp->napi)) {
1672                         /* Mask Rx interrupts */
1673                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1674                                      EESIPR);
1675                         __napi_schedule(&mdp->napi);
1676                 } else {
1677                         dev_warn(&ndev->dev,
1678                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1679                                  intr_status, intr_enable);
1680                 }
1681         }
1682
1683         /* Tx Check */
1684         if (intr_status & cd->tx_check) {
1685                 /* Clear Tx interrupts */
1686                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1687
1688                 sh_eth_txfree(ndev);
1689                 netif_wake_queue(ndev);
1690         }
1691
1692         if (intr_status & cd->eesr_err_check) {
1693                 /* Clear error interrupts */
1694                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1695
1696                 sh_eth_error(ndev, intr_status);
1697         }
1698
1699 other_irq:
1700         spin_unlock(&mdp->lock);
1701
1702         return ret;
1703 }
1704
1705 static int sh_eth_poll(struct napi_struct *napi, int budget)
1706 {
1707         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1708                                                   napi);
1709         struct net_device *ndev = napi->dev;
1710         int quota = budget;
1711         unsigned long intr_status;
1712
1713         for (;;) {
1714                 intr_status = sh_eth_read(ndev, EESR);
1715                 if (!(intr_status & EESR_RX_CHECK))
1716                         break;
1717                 /* Clear Rx interrupts */
1718                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1719
1720                 if (sh_eth_rx(ndev, intr_status, &quota))
1721                         goto out;
1722         }
1723
1724         napi_complete(napi);
1725
1726         /* Reenable Rx interrupts */
1727         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1728 out:
1729         return budget - quota;
1730 }
1731
1732 /* PHY state control function */
1733 static void sh_eth_adjust_link(struct net_device *ndev)
1734 {
1735         struct sh_eth_private *mdp = netdev_priv(ndev);
1736         struct phy_device *phydev = mdp->phydev;
1737         int new_state = 0;
1738
1739         if (phydev->link) {
1740                 if (phydev->duplex != mdp->duplex) {
1741                         new_state = 1;
1742                         mdp->duplex = phydev->duplex;
1743                         if (mdp->cd->set_duplex)
1744                                 mdp->cd->set_duplex(ndev);
1745                 }
1746
1747                 if (phydev->speed != mdp->speed) {
1748                         new_state = 1;
1749                         mdp->speed = phydev->speed;
1750                         if (mdp->cd->set_rate)
1751                                 mdp->cd->set_rate(ndev);
1752                 }
1753                 if (!mdp->link) {
1754                         sh_eth_write(ndev,
1755                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1756                                      ECMR);
1757                         new_state = 1;
1758                         mdp->link = phydev->link;
1759                         if (mdp->cd->no_psr || mdp->no_ether_link)
1760                                 sh_eth_rcv_snd_enable(ndev);
1761                 }
1762         } else if (mdp->link) {
1763                 new_state = 1;
1764                 mdp->link = 0;
1765                 mdp->speed = 0;
1766                 mdp->duplex = -1;
1767                 if (mdp->cd->no_psr || mdp->no_ether_link)
1768                         sh_eth_rcv_snd_disable(ndev);
1769         }
1770
1771         if (new_state && netif_msg_link(mdp))
1772                 phy_print_status(phydev);
1773 }
1774
1775 /* PHY init function */
1776 static int sh_eth_phy_init(struct net_device *ndev)
1777 {
1778         struct sh_eth_private *mdp = netdev_priv(ndev);
1779         char phy_id[MII_BUS_ID_SIZE + 3];
1780         struct phy_device *phydev = NULL;
1781
1782         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1783                  mdp->mii_bus->id, mdp->phy_id);
1784
1785         mdp->link = 0;
1786         mdp->speed = 0;
1787         mdp->duplex = -1;
1788
1789         /* Try connect to PHY */
1790         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1791                              mdp->phy_interface);
1792         if (IS_ERR(phydev)) {
1793                 dev_err(&ndev->dev, "phy_connect failed\n");
1794                 return PTR_ERR(phydev);
1795         }
1796
1797         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1798                  phydev->addr, phydev->irq, phydev->drv->name);
1799
1800         mdp->phydev = phydev;
1801
1802         return 0;
1803 }
1804
1805 /* PHY control start function */
1806 static int sh_eth_phy_start(struct net_device *ndev)
1807 {
1808         struct sh_eth_private *mdp = netdev_priv(ndev);
1809         int ret;
1810
1811         ret = sh_eth_phy_init(ndev);
1812         if (ret)
1813                 return ret;
1814
1815         phy_start(mdp->phydev);
1816
1817         return 0;
1818 }
1819
1820 static int sh_eth_get_settings(struct net_device *ndev,
1821                                struct ethtool_cmd *ecmd)
1822 {
1823         struct sh_eth_private *mdp = netdev_priv(ndev);
1824         unsigned long flags;
1825         int ret;
1826
1827         spin_lock_irqsave(&mdp->lock, flags);
1828         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1829         spin_unlock_irqrestore(&mdp->lock, flags);
1830
1831         return ret;
1832 }
1833
1834 static int sh_eth_set_settings(struct net_device *ndev,
1835                                struct ethtool_cmd *ecmd)
1836 {
1837         struct sh_eth_private *mdp = netdev_priv(ndev);
1838         unsigned long flags;
1839         int ret;
1840
1841         spin_lock_irqsave(&mdp->lock, flags);
1842
1843         /* disable tx and rx */
1844         sh_eth_rcv_snd_disable(ndev);
1845
1846         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1847         if (ret)
1848                 goto error_exit;
1849
1850         if (ecmd->duplex == DUPLEX_FULL)
1851                 mdp->duplex = 1;
1852         else
1853                 mdp->duplex = 0;
1854
1855         if (mdp->cd->set_duplex)
1856                 mdp->cd->set_duplex(ndev);
1857
1858 error_exit:
1859         mdelay(1);
1860
1861         /* enable tx and rx */
1862         sh_eth_rcv_snd_enable(ndev);
1863
1864         spin_unlock_irqrestore(&mdp->lock, flags);
1865
1866         return ret;
1867 }
1868
1869 static int sh_eth_nway_reset(struct net_device *ndev)
1870 {
1871         struct sh_eth_private *mdp = netdev_priv(ndev);
1872         unsigned long flags;
1873         int ret;
1874
1875         spin_lock_irqsave(&mdp->lock, flags);
1876         ret = phy_start_aneg(mdp->phydev);
1877         spin_unlock_irqrestore(&mdp->lock, flags);
1878
1879         return ret;
1880 }
1881
1882 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1883 {
1884         struct sh_eth_private *mdp = netdev_priv(ndev);
1885         return mdp->msg_enable;
1886 }
1887
1888 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1889 {
1890         struct sh_eth_private *mdp = netdev_priv(ndev);
1891         mdp->msg_enable = value;
1892 }
1893
1894 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1895         "rx_current", "tx_current",
1896         "rx_dirty", "tx_dirty",
1897 };
1898 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1899
1900 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1901 {
1902         switch (sset) {
1903         case ETH_SS_STATS:
1904                 return SH_ETH_STATS_LEN;
1905         default:
1906                 return -EOPNOTSUPP;
1907         }
1908 }
1909
1910 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1911                                      struct ethtool_stats *stats, u64 *data)
1912 {
1913         struct sh_eth_private *mdp = netdev_priv(ndev);
1914         int i = 0;
1915
1916         /* device-specific stats */
1917         data[i++] = mdp->cur_rx;
1918         data[i++] = mdp->cur_tx;
1919         data[i++] = mdp->dirty_rx;
1920         data[i++] = mdp->dirty_tx;
1921 }
1922
1923 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1924 {
1925         switch (stringset) {
1926         case ETH_SS_STATS:
1927                 memcpy(data, *sh_eth_gstrings_stats,
1928                        sizeof(sh_eth_gstrings_stats));
1929                 break;
1930         }
1931 }
1932
1933 static void sh_eth_get_ringparam(struct net_device *ndev,
1934                                  struct ethtool_ringparam *ring)
1935 {
1936         struct sh_eth_private *mdp = netdev_priv(ndev);
1937
1938         ring->rx_max_pending = RX_RING_MAX;
1939         ring->tx_max_pending = TX_RING_MAX;
1940         ring->rx_pending = mdp->num_rx_ring;
1941         ring->tx_pending = mdp->num_tx_ring;
1942 }
1943
1944 static int sh_eth_set_ringparam(struct net_device *ndev,
1945                                 struct ethtool_ringparam *ring)
1946 {
1947         struct sh_eth_private *mdp = netdev_priv(ndev);
1948         int ret;
1949
1950         if (ring->tx_pending > TX_RING_MAX ||
1951             ring->rx_pending > RX_RING_MAX ||
1952             ring->tx_pending < TX_RING_MIN ||
1953             ring->rx_pending < RX_RING_MIN)
1954                 return -EINVAL;
1955         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1956                 return -EINVAL;
1957
1958         if (netif_running(ndev)) {
1959                 netif_tx_disable(ndev);
1960                 /* Disable interrupts by clearing the interrupt mask. */
1961                 sh_eth_write(ndev, 0x0000, EESIPR);
1962                 /* Stop the chip's Tx and Rx processes. */
1963                 sh_eth_write(ndev, 0, EDTRR);
1964                 sh_eth_write(ndev, 0, EDRRR);
1965                 synchronize_irq(ndev->irq);
1966         }
1967
1968         /* Free all the skbuffs in the Rx queue. */
1969         sh_eth_ring_free(ndev);
1970         /* Free DMA buffer */
1971         sh_eth_free_dma_buffer(mdp);
1972
1973         /* Set new parameters */
1974         mdp->num_rx_ring = ring->rx_pending;
1975         mdp->num_tx_ring = ring->tx_pending;
1976
1977         ret = sh_eth_ring_init(ndev);
1978         if (ret < 0) {
1979                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1980                 return ret;
1981         }
1982         ret = sh_eth_dev_init(ndev, false);
1983         if (ret < 0) {
1984                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1985                 return ret;
1986         }
1987
1988         if (netif_running(ndev)) {
1989                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1990                 /* Setting the Rx mode will start the Rx process. */
1991                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1992                 netif_wake_queue(ndev);
1993         }
1994
1995         return 0;
1996 }
1997
1998 static const struct ethtool_ops sh_eth_ethtool_ops = {
1999         .get_settings   = sh_eth_get_settings,
2000         .set_settings   = sh_eth_set_settings,
2001         .nway_reset     = sh_eth_nway_reset,
2002         .get_msglevel   = sh_eth_get_msglevel,
2003         .set_msglevel   = sh_eth_set_msglevel,
2004         .get_link       = ethtool_op_get_link,
2005         .get_strings    = sh_eth_get_strings,
2006         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2007         .get_sset_count     = sh_eth_get_sset_count,
2008         .get_ringparam  = sh_eth_get_ringparam,
2009         .set_ringparam  = sh_eth_set_ringparam,
2010 };
2011
2012 /* network device open function */
2013 static int sh_eth_open(struct net_device *ndev)
2014 {
2015         int ret = 0;
2016         struct sh_eth_private *mdp = netdev_priv(ndev);
2017
2018         pm_runtime_get_sync(&mdp->pdev->dev);
2019
2020         napi_enable(&mdp->napi);
2021
2022         ret = request_irq(ndev->irq, sh_eth_interrupt,
2023                           mdp->cd->irq_flags, ndev->name, ndev);
2024         if (ret) {
2025                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
2026                 goto out_napi_off;
2027         }
2028
2029         /* Descriptor set */
2030         ret = sh_eth_ring_init(ndev);
2031         if (ret)
2032                 goto out_free_irq;
2033
2034         /* device init */
2035         ret = sh_eth_dev_init(ndev, true);
2036         if (ret)
2037                 goto out_free_irq;
2038
2039         /* PHY control start*/
2040         ret = sh_eth_phy_start(ndev);
2041         if (ret)
2042                 goto out_free_irq;
2043
2044         return ret;
2045
2046 out_free_irq:
2047         free_irq(ndev->irq, ndev);
2048 out_napi_off:
2049         napi_disable(&mdp->napi);
2050         pm_runtime_put_sync(&mdp->pdev->dev);
2051         return ret;
2052 }
2053
2054 /* Timeout function */
2055 static void sh_eth_tx_timeout(struct net_device *ndev)
2056 {
2057         struct sh_eth_private *mdp = netdev_priv(ndev);
2058         struct sh_eth_rxdesc *rxdesc;
2059         int i;
2060
2061         netif_stop_queue(ndev);
2062
2063         if (netif_msg_timer(mdp)) {
2064                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
2065                         ndev->name, (int)sh_eth_read(ndev, EESR));
2066         }
2067
2068         /* tx_errors count up */
2069         ndev->stats.tx_errors++;
2070
2071         /* Free all the skbuffs in the Rx queue. */
2072         for (i = 0; i < mdp->num_rx_ring; i++) {
2073                 rxdesc = &mdp->rx_ring[i];
2074                 rxdesc->status = 0;
2075                 rxdesc->addr = 0xBADF00D0;
2076                 if (mdp->rx_skbuff[i])
2077                         dev_kfree_skb(mdp->rx_skbuff[i]);
2078                 mdp->rx_skbuff[i] = NULL;
2079         }
2080         for (i = 0; i < mdp->num_tx_ring; i++) {
2081                 if (mdp->tx_skbuff[i])
2082                         dev_kfree_skb(mdp->tx_skbuff[i]);
2083                 mdp->tx_skbuff[i] = NULL;
2084         }
2085
2086         /* device init */
2087         sh_eth_dev_init(ndev, true);
2088 }
2089
2090 /* Packet transmit function */
2091 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2092 {
2093         struct sh_eth_private *mdp = netdev_priv(ndev);
2094         struct sh_eth_txdesc *txdesc;
2095         u32 entry;
2096         unsigned long flags;
2097
2098         spin_lock_irqsave(&mdp->lock, flags);
2099         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2100                 if (!sh_eth_txfree(ndev)) {
2101                         if (netif_msg_tx_queued(mdp))
2102                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2103                         netif_stop_queue(ndev);
2104                         spin_unlock_irqrestore(&mdp->lock, flags);
2105                         return NETDEV_TX_BUSY;
2106                 }
2107         }
2108         spin_unlock_irqrestore(&mdp->lock, flags);
2109
2110         entry = mdp->cur_tx % mdp->num_tx_ring;
2111         mdp->tx_skbuff[entry] = skb;
2112         txdesc = &mdp->tx_ring[entry];
2113         /* soft swap. */
2114         if (!mdp->cd->hw_swap)
2115                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2116                                  skb->len + 2);
2117         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2118                                       DMA_TO_DEVICE);
2119         if (skb->len < ETH_ZLEN)
2120                 txdesc->buffer_length = ETH_ZLEN;
2121         else
2122                 txdesc->buffer_length = skb->len;
2123
2124         if (entry >= mdp->num_tx_ring - 1)
2125                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2126         else
2127                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2128
2129         mdp->cur_tx++;
2130
2131         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2132                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2133
2134         return NETDEV_TX_OK;
2135 }
2136
2137 /* device close function */
2138 static int sh_eth_close(struct net_device *ndev)
2139 {
2140         struct sh_eth_private *mdp = netdev_priv(ndev);
2141
2142         netif_stop_queue(ndev);
2143
2144         /* Disable interrupts by clearing the interrupt mask. */
2145         sh_eth_write(ndev, 0x0000, EESIPR);
2146
2147         /* Stop the chip's Tx and Rx processes. */
2148         sh_eth_write(ndev, 0, EDTRR);
2149         sh_eth_write(ndev, 0, EDRRR);
2150
2151         /* PHY Disconnect */
2152         if (mdp->phydev) {
2153                 phy_stop(mdp->phydev);
2154                 phy_disconnect(mdp->phydev);
2155         }
2156
2157         free_irq(ndev->irq, ndev);
2158
2159         napi_disable(&mdp->napi);
2160
2161         /* Free all the skbuffs in the Rx queue. */
2162         sh_eth_ring_free(ndev);
2163
2164         /* free DMA buffer */
2165         sh_eth_free_dma_buffer(mdp);
2166
2167         pm_runtime_put_sync(&mdp->pdev->dev);
2168
2169         return 0;
2170 }
2171
2172 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2173 {
2174         struct sh_eth_private *mdp = netdev_priv(ndev);
2175
2176         if (sh_eth_is_rz_fast_ether(mdp))
2177                 return &ndev->stats;
2178
2179         pm_runtime_get_sync(&mdp->pdev->dev);
2180
2181         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2182         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2183         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2184         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2185         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2186         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2187         if (sh_eth_is_gether(mdp)) {
2188                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2189                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2190                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2191                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2192         } else {
2193                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2194                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2195         }
2196         pm_runtime_put_sync(&mdp->pdev->dev);
2197
2198         return &ndev->stats;
2199 }
2200
2201 /* ioctl to device function */
2202 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2203 {
2204         struct sh_eth_private *mdp = netdev_priv(ndev);
2205         struct phy_device *phydev = mdp->phydev;
2206
2207         if (!netif_running(ndev))
2208                 return -EINVAL;
2209
2210         if (!phydev)
2211                 return -ENODEV;
2212
2213         return phy_mii_ioctl(phydev, rq, cmd);
2214 }
2215
2216 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2217 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2218                                             int entry)
2219 {
2220         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2221 }
2222
2223 static u32 sh_eth_tsu_get_post_mask(int entry)
2224 {
2225         return 0x0f << (28 - ((entry % 8) * 4));
2226 }
2227
2228 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2229 {
2230         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2231 }
2232
2233 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2234                                              int entry)
2235 {
2236         struct sh_eth_private *mdp = netdev_priv(ndev);
2237         u32 tmp;
2238         void *reg_offset;
2239
2240         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2241         tmp = ioread32(reg_offset);
2242         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2243 }
2244
2245 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2246                                               int entry)
2247 {
2248         struct sh_eth_private *mdp = netdev_priv(ndev);
2249         u32 post_mask, ref_mask, tmp;
2250         void *reg_offset;
2251
2252         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2253         post_mask = sh_eth_tsu_get_post_mask(entry);
2254         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2255
2256         tmp = ioread32(reg_offset);
2257         iowrite32(tmp & ~post_mask, reg_offset);
2258
2259         /* If other port enables, the function returns "true" */
2260         return tmp & ref_mask;
2261 }
2262
2263 static int sh_eth_tsu_busy(struct net_device *ndev)
2264 {
2265         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2266         struct sh_eth_private *mdp = netdev_priv(ndev);
2267
2268         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2269                 udelay(10);
2270                 timeout--;
2271                 if (timeout <= 0) {
2272                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2273                         return -ETIMEDOUT;
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2281                                   const u8 *addr)
2282 {
2283         u32 val;
2284
2285         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2286         iowrite32(val, reg);
2287         if (sh_eth_tsu_busy(ndev) < 0)
2288                 return -EBUSY;
2289
2290         val = addr[4] << 8 | addr[5];
2291         iowrite32(val, reg + 4);
2292         if (sh_eth_tsu_busy(ndev) < 0)
2293                 return -EBUSY;
2294
2295         return 0;
2296 }
2297
2298 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2299 {
2300         u32 val;
2301
2302         val = ioread32(reg);
2303         addr[0] = (val >> 24) & 0xff;
2304         addr[1] = (val >> 16) & 0xff;
2305         addr[2] = (val >> 8) & 0xff;
2306         addr[3] = val & 0xff;
2307         val = ioread32(reg + 4);
2308         addr[4] = (val >> 8) & 0xff;
2309         addr[5] = val & 0xff;
2310 }
2311
2312
2313 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2314 {
2315         struct sh_eth_private *mdp = netdev_priv(ndev);
2316         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2317         int i;
2318         u8 c_addr[ETH_ALEN];
2319
2320         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2321                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2322                 if (ether_addr_equal(addr, c_addr))
2323                         return i;
2324         }
2325
2326         return -ENOENT;
2327 }
2328
2329 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2330 {
2331         u8 blank[ETH_ALEN];
2332         int entry;
2333
2334         memset(blank, 0, sizeof(blank));
2335         entry = sh_eth_tsu_find_entry(ndev, blank);
2336         return (entry < 0) ? -ENOMEM : entry;
2337 }
2338
2339 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2340                                               int entry)
2341 {
2342         struct sh_eth_private *mdp = netdev_priv(ndev);
2343         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2344         int ret;
2345         u8 blank[ETH_ALEN];
2346
2347         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2348                          ~(1 << (31 - entry)), TSU_TEN);
2349
2350         memset(blank, 0, sizeof(blank));
2351         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2352         if (ret < 0)
2353                 return ret;
2354         return 0;
2355 }
2356
2357 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2358 {
2359         struct sh_eth_private *mdp = netdev_priv(ndev);
2360         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2361         int i, ret;
2362
2363         if (!mdp->cd->tsu)
2364                 return 0;
2365
2366         i = sh_eth_tsu_find_entry(ndev, addr);
2367         if (i < 0) {
2368                 /* No entry found, create one */
2369                 i = sh_eth_tsu_find_empty(ndev);
2370                 if (i < 0)
2371                         return -ENOMEM;
2372                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2373                 if (ret < 0)
2374                         return ret;
2375
2376                 /* Enable the entry */
2377                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2378                                  (1 << (31 - i)), TSU_TEN);
2379         }
2380
2381         /* Entry found or created, enable POST */
2382         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2383
2384         return 0;
2385 }
2386
2387 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2388 {
2389         struct sh_eth_private *mdp = netdev_priv(ndev);
2390         int i, ret;
2391
2392         if (!mdp->cd->tsu)
2393                 return 0;
2394
2395         i = sh_eth_tsu_find_entry(ndev, addr);
2396         if (i) {
2397                 /* Entry found */
2398                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2399                         goto done;
2400
2401                 /* Disable the entry if both ports was disabled */
2402                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2403                 if (ret < 0)
2404                         return ret;
2405         }
2406 done:
2407         return 0;
2408 }
2409
2410 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2411 {
2412         struct sh_eth_private *mdp = netdev_priv(ndev);
2413         int i, ret;
2414
2415         if (unlikely(!mdp->cd->tsu))
2416                 return 0;
2417
2418         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2419                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2420                         continue;
2421
2422                 /* Disable the entry if both ports was disabled */
2423                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2424                 if (ret < 0)
2425                         return ret;
2426         }
2427
2428         return 0;
2429 }
2430
2431 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2432 {
2433         struct sh_eth_private *mdp = netdev_priv(ndev);
2434         u8 addr[ETH_ALEN];
2435         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2436         int i;
2437
2438         if (unlikely(!mdp->cd->tsu))
2439                 return;
2440
2441         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2442                 sh_eth_tsu_read_entry(reg_offset, addr);
2443                 if (is_multicast_ether_addr(addr))
2444                         sh_eth_tsu_del_entry(ndev, addr);
2445         }
2446 }
2447
2448 /* Multicast reception directions set */
2449 static void sh_eth_set_multicast_list(struct net_device *ndev)
2450 {
2451         struct sh_eth_private *mdp = netdev_priv(ndev);
2452         u32 ecmr_bits;
2453         int mcast_all = 0;
2454         unsigned long flags;
2455
2456         spin_lock_irqsave(&mdp->lock, flags);
2457         /* Initial condition is MCT = 1, PRM = 0.
2458          * Depending on ndev->flags, set PRM or clear MCT
2459          */
2460         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2461
2462         if (!(ndev->flags & IFF_MULTICAST)) {
2463                 sh_eth_tsu_purge_mcast(ndev);
2464                 mcast_all = 1;
2465         }
2466         if (ndev->flags & IFF_ALLMULTI) {
2467                 sh_eth_tsu_purge_mcast(ndev);
2468                 ecmr_bits &= ~ECMR_MCT;
2469                 mcast_all = 1;
2470         }
2471
2472         if (ndev->flags & IFF_PROMISC) {
2473                 sh_eth_tsu_purge_all(ndev);
2474                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2475         } else if (mdp->cd->tsu) {
2476                 struct netdev_hw_addr *ha;
2477                 netdev_for_each_mc_addr(ha, ndev) {
2478                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2479                                 continue;
2480
2481                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2482                                 if (!mcast_all) {
2483                                         sh_eth_tsu_purge_mcast(ndev);
2484                                         ecmr_bits &= ~ECMR_MCT;
2485                                         mcast_all = 1;
2486                                 }
2487                         }
2488                 }
2489         } else {
2490                 /* Normal, unicast/broadcast-only mode. */
2491                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2492         }
2493
2494         /* update the ethernet mode */
2495         sh_eth_write(ndev, ecmr_bits, ECMR);
2496
2497         spin_unlock_irqrestore(&mdp->lock, flags);
2498 }
2499
2500 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2501 {
2502         if (!mdp->port)
2503                 return TSU_VTAG0;
2504         else
2505                 return TSU_VTAG1;
2506 }
2507
2508 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2509                                   __be16 proto, u16 vid)
2510 {
2511         struct sh_eth_private *mdp = netdev_priv(ndev);
2512         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2513
2514         if (unlikely(!mdp->cd->tsu))
2515                 return -EPERM;
2516
2517         /* No filtering if vid = 0 */
2518         if (!vid)
2519                 return 0;
2520
2521         mdp->vlan_num_ids++;
2522
2523         /* The controller has one VLAN tag HW filter. So, if the filter is
2524          * already enabled, the driver disables it and the filte
2525          */
2526         if (mdp->vlan_num_ids > 1) {
2527                 /* disable VLAN filter */
2528                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2529                 return 0;
2530         }
2531
2532         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2533                          vtag_reg_index);
2534
2535         return 0;
2536 }
2537
2538 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2539                                    __be16 proto, u16 vid)
2540 {
2541         struct sh_eth_private *mdp = netdev_priv(ndev);
2542         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2543
2544         if (unlikely(!mdp->cd->tsu))
2545                 return -EPERM;
2546
2547         /* No filtering if vid = 0 */
2548         if (!vid)
2549                 return 0;
2550
2551         mdp->vlan_num_ids--;
2552         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2553
2554         return 0;
2555 }
2556
2557 /* SuperH's TSU register init function */
2558 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2559 {
2560         if (sh_eth_is_rz_fast_ether(mdp)) {
2561                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2562                 return;
2563         }
2564
2565         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2566         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2567         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2568         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2569         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2570         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2571         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2572         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2573         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2574         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2575         if (sh_eth_is_gether(mdp)) {
2576                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2577                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2578         } else {
2579                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2580                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2581         }
2582         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2583         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2584         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2585         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2586         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2587         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2588         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2589 }
2590
2591 /* MDIO bus release function */
2592 static int sh_mdio_release(struct net_device *ndev)
2593 {
2594         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2595
2596         /* unregister mdio bus */
2597         mdiobus_unregister(bus);
2598
2599         /* remove mdio bus info from net_device */
2600         dev_set_drvdata(&ndev->dev, NULL);
2601
2602         /* free bitbang info */
2603         free_mdio_bitbang(bus);
2604
2605         return 0;
2606 }
2607
2608 /* MDIO bus init function */
2609 static int sh_mdio_init(struct net_device *ndev, int id,
2610                         struct sh_eth_plat_data *pd)
2611 {
2612         int ret, i;
2613         struct bb_info *bitbang;
2614         struct sh_eth_private *mdp = netdev_priv(ndev);
2615
2616         /* create bit control struct for PHY */
2617         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2618                                GFP_KERNEL);
2619         if (!bitbang) {
2620                 ret = -ENOMEM;
2621                 goto out;
2622         }
2623
2624         /* bitbang init */
2625         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2626         bitbang->set_gate = pd->set_mdio_gate;
2627         bitbang->mdi_msk = PIR_MDI;
2628         bitbang->mdo_msk = PIR_MDO;
2629         bitbang->mmd_msk = PIR_MMD;
2630         bitbang->mdc_msk = PIR_MDC;
2631         bitbang->ctrl.ops = &bb_ops;
2632
2633         /* MII controller setting */
2634         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2635         if (!mdp->mii_bus) {
2636                 ret = -ENOMEM;
2637                 goto out;
2638         }
2639
2640         /* Hook up MII support for ethtool */
2641         mdp->mii_bus->name = "sh_mii";
2642         mdp->mii_bus->parent = &ndev->dev;
2643         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2644                  mdp->pdev->name, id);
2645
2646         /* PHY IRQ */
2647         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2648                                          sizeof(int) * PHY_MAX_ADDR,
2649                                          GFP_KERNEL);
2650         if (!mdp->mii_bus->irq) {
2651                 ret = -ENOMEM;
2652                 goto out_free_bus;
2653         }
2654
2655         for (i = 0; i < PHY_MAX_ADDR; i++)
2656                 mdp->mii_bus->irq[i] = PHY_POLL;
2657         if (pd->phy_irq > 0)
2658                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2659
2660         /* register mdio bus */
2661         ret = mdiobus_register(mdp->mii_bus);
2662         if (ret)
2663                 goto out_free_bus;
2664
2665         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2666
2667         return 0;
2668
2669 out_free_bus:
2670         free_mdio_bitbang(mdp->mii_bus);
2671
2672 out:
2673         return ret;
2674 }
2675
2676 static const u16 *sh_eth_get_register_offset(int register_type)
2677 {
2678         const u16 *reg_offset = NULL;
2679
2680         switch (register_type) {
2681         case SH_ETH_REG_GIGABIT:
2682                 reg_offset = sh_eth_offset_gigabit;
2683                 break;
2684         case SH_ETH_REG_FAST_RZ:
2685                 reg_offset = sh_eth_offset_fast_rz;
2686                 break;
2687         case SH_ETH_REG_FAST_RCAR:
2688                 reg_offset = sh_eth_offset_fast_rcar;
2689                 break;
2690         case SH_ETH_REG_FAST_SH4:
2691                 reg_offset = sh_eth_offset_fast_sh4;
2692                 break;
2693         case SH_ETH_REG_FAST_SH3_SH2:
2694                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2695                 break;
2696         default:
2697                 pr_err("Unknown register type (%d)\n", register_type);
2698                 break;
2699         }
2700
2701         return reg_offset;
2702 }
2703
2704 static const struct net_device_ops sh_eth_netdev_ops = {
2705         .ndo_open               = sh_eth_open,
2706         .ndo_stop               = sh_eth_close,
2707         .ndo_start_xmit         = sh_eth_start_xmit,
2708         .ndo_get_stats          = sh_eth_get_stats,
2709         .ndo_tx_timeout         = sh_eth_tx_timeout,
2710         .ndo_do_ioctl           = sh_eth_do_ioctl,
2711         .ndo_validate_addr      = eth_validate_addr,
2712         .ndo_set_mac_address    = eth_mac_addr,
2713         .ndo_change_mtu         = eth_change_mtu,
2714 };
2715
2716 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2717         .ndo_open               = sh_eth_open,
2718         .ndo_stop               = sh_eth_close,
2719         .ndo_start_xmit         = sh_eth_start_xmit,
2720         .ndo_get_stats          = sh_eth_get_stats,
2721         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2722         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2723         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2724         .ndo_tx_timeout         = sh_eth_tx_timeout,
2725         .ndo_do_ioctl           = sh_eth_do_ioctl,
2726         .ndo_validate_addr      = eth_validate_addr,
2727         .ndo_set_mac_address    = eth_mac_addr,
2728         .ndo_change_mtu         = eth_change_mtu,
2729 };
2730
2731 #ifdef CONFIG_OF
2732 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2733 {
2734         struct device_node *np = dev->of_node;
2735         struct sh_eth_plat_data *pdata;
2736         struct device_node *phy;
2737         const char *mac_addr;
2738
2739         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2740         if (!pdata)
2741                 return NULL;
2742
2743         pdata->phy_interface = of_get_phy_mode(np);
2744
2745         phy = of_parse_phandle(np, "phy-handle", 0);
2746         if (of_property_read_u32(phy, "reg", &pdata->phy))
2747                 return NULL;
2748         pdata->phy_irq = irq_of_parse_and_map(phy, 0);
2749
2750         mac_addr = of_get_mac_address(np);
2751         if (mac_addr)
2752                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2753
2754         pdata->no_ether_link =
2755                 of_property_read_bool(np, "renesas,no-ether-link");
2756         pdata->ether_link_active_low =
2757                 of_property_read_bool(np, "renesas,ether-link-active-low");
2758
2759         return pdata;
2760 }
2761
2762 static const struct of_device_id sh_eth_match_table[] = {
2763         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2764         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2765         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2766         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2767         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2768         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2769         { }
2770 };
2771 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2772 #else
2773 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2774 {
2775         return NULL;
2776 }
2777 #endif
2778
2779 static int sh_eth_drv_probe(struct platform_device *pdev)
2780 {
2781         int ret, devno = 0;
2782         struct resource *res;
2783         struct net_device *ndev = NULL;
2784         struct sh_eth_private *mdp = NULL;
2785         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2786         const struct platform_device_id *id = platform_get_device_id(pdev);
2787
2788         /* get base addr */
2789         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2790         if (unlikely(res == NULL)) {
2791                 dev_err(&pdev->dev, "invalid resource\n");
2792                 ret = -EINVAL;
2793                 goto out;
2794         }
2795
2796         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2797         if (!ndev) {
2798                 ret = -ENOMEM;
2799                 goto out;
2800         }
2801
2802         /* The sh Ether-specific entries in the device structure. */
2803         ndev->base_addr = res->start;
2804         devno = pdev->id;
2805         if (devno < 0)
2806                 devno = 0;
2807
2808         ndev->dma = -1;
2809         ret = platform_get_irq(pdev, 0);
2810         if (ret < 0) {
2811                 ret = -ENODEV;
2812                 goto out_release;
2813         }
2814         ndev->irq = ret;
2815
2816         SET_NETDEV_DEV(ndev, &pdev->dev);
2817
2818         mdp = netdev_priv(ndev);
2819         mdp->num_tx_ring = TX_RING_SIZE;
2820         mdp->num_rx_ring = RX_RING_SIZE;
2821         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2822         if (IS_ERR(mdp->addr)) {
2823                 ret = PTR_ERR(mdp->addr);
2824                 goto out_release;
2825         }
2826
2827         spin_lock_init(&mdp->lock);
2828         mdp->pdev = pdev;
2829         pm_runtime_enable(&pdev->dev);
2830         pm_runtime_resume(&pdev->dev);
2831
2832         if (pdev->dev.of_node)
2833                 pd = sh_eth_parse_dt(&pdev->dev);
2834         if (!pd) {
2835                 dev_err(&pdev->dev, "no platform data\n");
2836                 ret = -EINVAL;
2837                 goto out_release;
2838         }
2839
2840         /* get PHY ID */
2841         mdp->phy_id = pd->phy;
2842         mdp->phy_interface = pd->phy_interface;
2843         /* EDMAC endian */
2844         mdp->edmac_endian = pd->edmac_endian;
2845         mdp->no_ether_link = pd->no_ether_link;
2846         mdp->ether_link_active_low = pd->ether_link_active_low;
2847
2848         /* set cpu data */
2849         if (id) {
2850                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2851         } else  {
2852                 const struct of_device_id *match;
2853
2854                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2855                                         &pdev->dev);
2856                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2857         }
2858         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2859         sh_eth_set_default_cpu_data(mdp->cd);
2860
2861         /* set function */
2862         if (mdp->cd->tsu)
2863                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2864         else
2865                 ndev->netdev_ops = &sh_eth_netdev_ops;
2866         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2867         ndev->watchdog_timeo = TX_TIMEOUT;
2868
2869         /* debug message level */
2870         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2871
2872         /* read and set MAC address */
2873         read_mac_address(ndev, pd->mac_addr);
2874         if (!is_valid_ether_addr(ndev->dev_addr)) {
2875                 dev_warn(&pdev->dev,
2876                          "no valid MAC address supplied, using a random one.\n");
2877                 eth_hw_addr_random(ndev);
2878         }
2879
2880         /* ioremap the TSU registers */
2881         if (mdp->cd->tsu) {
2882                 struct resource *rtsu;
2883                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2884                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2885                 if (IS_ERR(mdp->tsu_addr)) {
2886                         ret = PTR_ERR(mdp->tsu_addr);
2887                         goto out_release;
2888                 }
2889                 mdp->port = devno % 2;
2890                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2891         }
2892
2893         /* initialize first or needed device */
2894         if (!devno || pd->needs_init) {
2895                 if (mdp->cd->chip_reset)
2896                         mdp->cd->chip_reset(ndev);
2897
2898                 if (mdp->cd->tsu) {
2899                         /* TSU init (Init only)*/
2900                         sh_eth_tsu_init(mdp);
2901                 }
2902         }
2903
2904         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2905
2906         /* network device register */
2907         ret = register_netdev(ndev);
2908         if (ret)
2909                 goto out_napi_del;
2910
2911         /* mdio bus init */
2912         ret = sh_mdio_init(ndev, pdev->id, pd);
2913         if (ret)
2914                 goto out_unregister;
2915
2916         /* print device information */
2917         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2918                 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2919
2920         platform_set_drvdata(pdev, ndev);
2921
2922         return ret;
2923
2924 out_unregister:
2925         unregister_netdev(ndev);
2926
2927 out_napi_del:
2928         netif_napi_del(&mdp->napi);
2929
2930 out_release:
2931         /* net_dev free */
2932         if (ndev)
2933                 free_netdev(ndev);
2934
2935 out:
2936         return ret;
2937 }
2938
2939 static int sh_eth_drv_remove(struct platform_device *pdev)
2940 {
2941         struct net_device *ndev = platform_get_drvdata(pdev);
2942         struct sh_eth_private *mdp = netdev_priv(ndev);
2943
2944         sh_mdio_release(ndev);
2945         unregister_netdev(ndev);
2946         netif_napi_del(&mdp->napi);
2947         pm_runtime_disable(&pdev->dev);
2948         free_netdev(ndev);
2949
2950         return 0;
2951 }
2952
2953 #ifdef CONFIG_PM
2954 static int sh_eth_runtime_nop(struct device *dev)
2955 {
2956         /* Runtime PM callback shared between ->runtime_suspend()
2957          * and ->runtime_resume(). Simply returns success.
2958          *
2959          * This driver re-initializes all registers after
2960          * pm_runtime_get_sync() anyway so there is no need
2961          * to save and restore registers here.
2962          */
2963         return 0;
2964 }
2965
2966 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2967         .runtime_suspend = sh_eth_runtime_nop,
2968         .runtime_resume = sh_eth_runtime_nop,
2969 };
2970 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2971 #else
2972 #define SH_ETH_PM_OPS NULL
2973 #endif
2974
2975 static struct platform_device_id sh_eth_id_table[] = {
2976         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2977         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2978         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2979         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2980         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2981         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2982         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2983         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2984         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2985         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2986         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2987         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2988         { }
2989 };
2990 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2991
2992 static struct platform_driver sh_eth_driver = {
2993         .probe = sh_eth_drv_probe,
2994         .remove = sh_eth_drv_remove,
2995         .id_table = sh_eth_id_table,
2996         .driver = {
2997                    .name = CARDNAME,
2998                    .pm = SH_ETH_PM_OPS,
2999                    .of_match_table = of_match_ptr(sh_eth_match_table),
3000         },
3001 };
3002
3003 module_platform_driver(sh_eth_driver);
3004
3005 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3006 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3007 MODULE_LICENSE("GPL v2");