drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   5  *  Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *
  16  *  The full GNU General Public License is included in this distribution in
  17  *  the file called "COPYING".
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/mdio-bitbang.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/phy.h>
  31 #include <linux/cache.h>
  32 #include <linux/io.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/slab.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/clk.h>
  38 #include <linux/sh_eth.h>
  39
  40 #include "sh_eth.h"
  41
  42 #define SH_ETH_DEF_MSG_ENABLE \
  43                 (NETIF_MSG_LINK | \
  44                 NETIF_MSG_TIMER | \
  45                 NETIF_MSG_RX_ERR| \
  46                 NETIF_MSG_TX_ERR)
  47
  48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  49         [EDSR]          = 0x0000,
  50         [EDMR]          = 0x0400,
  51         [EDTRR]         = 0x0408,
  52         [EDRRR]         = 0x0410,
  53         [EESR]          = 0x0428,
  54         [EESIPR]        = 0x0430,
  55         [TDLAR]         = 0x0010,
  56         [TDFAR]         = 0x0014,
  57         [TDFXR]         = 0x0018,
  58         [TDFFR]         = 0x001c,
  59         [RDLAR]         = 0x0030,
  60         [RDFAR]         = 0x0034,
  61         [RDFXR]         = 0x0038,
  62         [RDFFR]         = 0x003c,
  63         [TRSCER]        = 0x0438,
  64         [RMFCR]         = 0x0440,
  65         [TFTR]          = 0x0448,
  66         [FDR]           = 0x0450,
  67         [RMCR]          = 0x0458,
  68         [RPADIR]        = 0x0460,
  69         [FCFTR]         = 0x0468,
  70         [CSMR]          = 0x04E4,
  71
  72         [ECMR]          = 0x0500,
  73         [ECSR]          = 0x0510,
  74         [ECSIPR]        = 0x0518,
  75         [PIR]           = 0x0520,
  76         [PSR]           = 0x0528,
  77         [PIPR]          = 0x052c,
  78         [RFLR]          = 0x0508,
  79         [APR]           = 0x0554,
  80         [MPR]           = 0x0558,
  81         [PFTCR]         = 0x055c,
  82         [PFRCR]         = 0x0560,
  83         [TPAUSER]       = 0x0564,
  84         [GECMR]         = 0x05b0,
  85         [BCULR]         = 0x05b4,
  86         [MAHR]          = 0x05c0,
  87         [MALR]          = 0x05c8,
  88         [TROCR]         = 0x0700,
  89         [CDCR]          = 0x0708,
  90         [LCCR]          = 0x0710,
  91         [CEFCR]         = 0x0740,
  92         [FRECR]         = 0x0748,
  93         [TSFRCR]        = 0x0750,
  94         [TLFRCR]        = 0x0758,
  95         [RFCR]          = 0x0760,
  96         [CERCR]         = 0x0768,
  97         [CEECR]         = 0x0770,
  98         [MAFCR]         = 0x0778,
  99         [RMII_MII]      = 0x0790,
 100
 101         [ARSTR]         = 0x0000,
 102         [TSU_CTRST]     = 0x0004,
 103         [TSU_FWEN0]     = 0x0010,
 104         [TSU_FWEN1]     = 0x0014,
 105         [TSU_FCM]       = 0x0018,
 106         [TSU_BSYSL0]    = 0x0020,
 107         [TSU_BSYSL1]    = 0x0024,
 108         [TSU_PRISL0]    = 0x0028,
 109         [TSU_PRISL1]    = 0x002c,
 110         [TSU_FWSL0]     = 0x0030,
 111         [TSU_FWSL1]     = 0x0034,
 112         [TSU_FWSLC]     = 0x0038,
 113         [TSU_QTAG0]     = 0x0040,
 114         [TSU_QTAG1]     = 0x0044,
 115         [TSU_FWSR]      = 0x0050,
 116         [TSU_FWINMK]    = 0x0054,
 117         [TSU_ADQT0]     = 0x0048,
 118         [TSU_ADQT1]     = 0x004c,
 119         [TSU_VTAG0]     = 0x0058,
 120         [TSU_VTAG1]     = 0x005c,
 121         [TSU_ADSBSY]    = 0x0060,
 122         [TSU_TEN]       = 0x0064,
 123         [TSU_POST1]     = 0x0070,
 124         [TSU_POST2]     = 0x0074,
 125         [TSU_POST3]     = 0x0078,
 126         [TSU_POST4]     = 0x007c,
 127         [TSU_ADRH0]     = 0x0100,
 128         [TSU_ADRL0]     = 0x0104,
 129         [TSU_ADRH31]    = 0x01f8,
 130         [TSU_ADRL31]    = 0x01fc,
 131
 132         [TXNLCR0]       = 0x0080,
 133         [TXALCR0]       = 0x0084,
 134         [RXNLCR0]       = 0x0088,
 135         [RXALCR0]       = 0x008c,
 136         [FWNLCR0]       = 0x0090,
 137         [FWALCR0]       = 0x0094,
 138         [TXNLCR1]       = 0x00a0,
 139         [TXALCR1]       = 0x00a0,
 140         [RXNLCR1]       = 0x00a8,
 141         [RXALCR1]       = 0x00ac,
 142         [FWNLCR1]       = 0x00b0,
 143         [FWALCR1]       = 0x00b4,
 144 };
 145
 146 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 147         [EDSR]          = 0x0000,
 148         [EDMR]          = 0x0400,
 149         [EDTRR]         = 0x0408,
 150         [EDRRR]         = 0x0410,
 151         [EESR]          = 0x0428,
 152         [EESIPR]        = 0x0430,
 153         [TDLAR]         = 0x0010,
 154         [TDFAR]         = 0x0014,
 155         [TDFXR]         = 0x0018,
 156         [TDFFR]         = 0x001c,
 157         [RDLAR]         = 0x0030,
 158         [RDFAR]         = 0x0034,
 159         [RDFXR]         = 0x0038,
 160         [RDFFR]         = 0x003c,
 161         [TRSCER]        = 0x0438,
 162         [RMFCR]         = 0x0440,
 163         [TFTR]          = 0x0448,
 164         [FDR]           = 0x0450,
 165         [RMCR]          = 0x0458,
 166         [RPADIR]        = 0x0460,
 167         [FCFTR]         = 0x0468,
 168         [CSMR]          = 0x04E4,
 169
 170         [ECMR]          = 0x0500,
 171         [RFLR]          = 0x0508,
 172         [ECSR]          = 0x0510,
 173         [ECSIPR]        = 0x0518,
 174         [PIR]           = 0x0520,
 175         [APR]           = 0x0554,
 176         [MPR]           = 0x0558,
 177         [PFTCR]         = 0x055c,
 178         [PFRCR]         = 0x0560,
 179         [TPAUSER]       = 0x0564,
 180         [MAHR]          = 0x05c0,
 181         [MALR]          = 0x05c8,
 182         [CEFCR]         = 0x0740,
 183         [FRECR]         = 0x0748,
 184         [TSFRCR]        = 0x0750,
 185         [TLFRCR]        = 0x0758,
 186         [RFCR]          = 0x0760,
 187         [MAFCR]         = 0x0778,
 188
 189         [ARSTR]         = 0x0000,
 190         [TSU_CTRST]     = 0x0004,
 191         [TSU_VTAG0]     = 0x0058,
 192         [TSU_ADSBSY]    = 0x0060,
 193         [TSU_TEN]       = 0x0064,
 194         [TSU_ADRH0]     = 0x0100,
 195         [TSU_ADRL0]     = 0x0104,
 196         [TSU_ADRH31]    = 0x01f8,
 197         [TSU_ADRL31]    = 0x01fc,
 198
 199         [TXNLCR0]       = 0x0080,
 200         [TXALCR0]       = 0x0084,
 201         [RXNLCR0]       = 0x0088,
 202         [RXALCR0]       = 0x008C,
 203 };
 204
 205 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 206         [ECMR]          = 0x0300,
 207         [RFLR]          = 0x0308,
 208         [ECSR]          = 0x0310,
 209         [ECSIPR]        = 0x0318,
 210         [PIR]           = 0x0320,
 211         [PSR]           = 0x0328,
 212         [RDMLR]         = 0x0340,
 213         [IPGR]          = 0x0350,
 214         [APR]           = 0x0354,
 215         [MPR]           = 0x0358,
 216         [RFCF]          = 0x0360,
 217         [TPAUSER]       = 0x0364,
 218         [TPAUSECR]      = 0x0368,
 219         [MAHR]          = 0x03c0,
 220         [MALR]          = 0x03c8,
 221         [TROCR]         = 0x03d0,
 222         [CDCR]          = 0x03d4,
 223         [LCCR]          = 0x03d8,
 224         [CNDCR]         = 0x03dc,
 225         [CEFCR]         = 0x03e4,
 226         [FRECR]         = 0x03e8,
 227         [TSFRCR]        = 0x03ec,
 228         [TLFRCR]        = 0x03f0,
 229         [RFCR]          = 0x03f4,
 230         [MAFCR]         = 0x03f8,
 231
 232         [EDMR]          = 0x0200,
 233         [EDTRR]         = 0x0208,
 234         [EDRRR]         = 0x0210,
 235         [TDLAR]         = 0x0218,
 236         [RDLAR]         = 0x0220,
 237         [EESR]          = 0x0228,
 238         [EESIPR]        = 0x0230,
 239         [TRSCER]        = 0x0238,
 240         [RMFCR]         = 0x0240,
 241         [TFTR]          = 0x0248,
 242         [FDR]           = 0x0250,
 243         [RMCR]          = 0x0258,
 244         [TFUCR]         = 0x0264,
 245         [RFOCR]         = 0x0268,
 246         [RMIIMODE]      = 0x026c,
 247         [FCFTR]         = 0x0270,
 248         [TRIMD]         = 0x027c,
 249 };
 250
 251 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 252         [ECMR]          = 0x0100,
 253         [RFLR]          = 0x0108,
 254         [ECSR]          = 0x0110,
 255         [ECSIPR]        = 0x0118,
 256         [PIR]           = 0x0120,
 257         [PSR]           = 0x0128,
 258         [RDMLR]         = 0x0140,
 259         [IPGR]          = 0x0150,
 260         [APR]           = 0x0154,
 261         [MPR]           = 0x0158,
 262         [TPAUSER]       = 0x0164,
 263         [RFCF]          = 0x0160,
 264         [TPAUSECR]      = 0x0168,
 265         [BCFRR]         = 0x016c,
 266         [MAHR]          = 0x01c0,
 267         [MALR]          = 0x01c8,
 268         [TROCR]         = 0x01d0,
 269         [CDCR]          = 0x01d4,
 270         [LCCR]          = 0x01d8,
 271         [CNDCR]         = 0x01dc,
 272         [CEFCR]         = 0x01e4,
 273         [FRECR]         = 0x01e8,
 274         [TSFRCR]        = 0x01ec,
 275         [TLFRCR]        = 0x01f0,
 276         [RFCR]          = 0x01f4,
 277         [MAFCR]         = 0x01f8,
 278         [RTRATE]        = 0x01fc,
 279
 280         [EDMR]          = 0x0000,
 281         [EDTRR]         = 0x0008,
 282         [EDRRR]         = 0x0010,
 283         [TDLAR]         = 0x0018,
 284         [RDLAR]         = 0x0020,
 285         [EESR]          = 0x0028,
 286         [EESIPR]        = 0x0030,
 287         [TRSCER]        = 0x0038,
 288         [RMFCR]         = 0x0040,
 289         [TFTR]          = 0x0048,
 290         [FDR]           = 0x0050,
 291         [RMCR]          = 0x0058,
 292         [TFUCR]         = 0x0064,
 293         [RFOCR]         = 0x0068,
 294         [FCFTR]         = 0x0070,
 295         [RPADIR]        = 0x0078,
 296         [TRIMD]         = 0x007c,
 297         [RBWAR]         = 0x00c8,
 298         [RDFAR]         = 0x00cc,
 299         [TBRAR]         = 0x00d4,
 300         [TDFAR]         = 0x00d8,
 301 };
 302
 303 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 304         [EDMR]          = 0x0000,
 305         [EDTRR]         = 0x0004,
 306         [EDRRR]         = 0x0008,
 307         [TDLAR]         = 0x000c,
 308         [RDLAR]         = 0x0010,
 309         [EESR]          = 0x0014,
 310         [EESIPR]        = 0x0018,
 311         [TRSCER]        = 0x001c,
 312         [RMFCR]         = 0x0020,
 313         [TFTR]          = 0x0024,
 314         [FDR]           = 0x0028,
 315         [RMCR]          = 0x002c,
 316         [EDOCR]         = 0x0030,
 317         [FCFTR]         = 0x0034,
 318         [RPADIR]        = 0x0038,
 319         [TRIMD]         = 0x003c,
 320         [RBWAR]         = 0x0040,
 321         [RDFAR]         = 0x0044,
 322         [TBRAR]         = 0x004c,
 323         [TDFAR]         = 0x0050,
 324
 325         [ECMR]          = 0x0160,
 326         [ECSR]          = 0x0164,
 327         [ECSIPR]        = 0x0168,
 328         [PIR]           = 0x016c,
 329         [MAHR]          = 0x0170,
 330         [MALR]          = 0x0174,
 331         [RFLR]          = 0x0178,
 332         [PSR]           = 0x017c,
 333         [TROCR]         = 0x0180,
 334         [CDCR]          = 0x0184,
 335         [LCCR]          = 0x0188,
 336         [CNDCR]         = 0x018c,
 337         [CEFCR]         = 0x0194,
 338         [FRECR]         = 0x0198,
 339         [TSFRCR]        = 0x019c,
 340         [TLFRCR]        = 0x01a0,
 341         [RFCR]          = 0x01a4,
 342         [MAFCR]         = 0x01a8,
 343         [IPGR]          = 0x01b4,
 344         [APR]           = 0x01b8,
 345         [MPR]           = 0x01bc,
 346         [TPAUSER]       = 0x01c4,
 347         [BCFR]          = 0x01cc,
 348
 349         [ARSTR]         = 0x0000,
 350         [TSU_CTRST]     = 0x0004,
 351         [TSU_FWEN0]     = 0x0010,
 352         [TSU_FWEN1]     = 0x0014,
 353         [TSU_FCM]       = 0x0018,
 354         [TSU_BSYSL0]    = 0x0020,
 355         [TSU_BSYSL1]    = 0x0024,
 356         [TSU_PRISL0]    = 0x0028,
 357         [TSU_PRISL1]    = 0x002c,
 358         [TSU_FWSL0]     = 0x0030,
 359         [TSU_FWSL1]     = 0x0034,
 360         [TSU_FWSLC]     = 0x0038,
 361         [TSU_QTAGM0]    = 0x0040,
 362         [TSU_QTAGM1]    = 0x0044,
 363         [TSU_ADQT0]     = 0x0048,
 364         [TSU_ADQT1]     = 0x004c,
 365         [TSU_FWSR]      = 0x0050,
 366         [TSU_FWINMK]    = 0x0054,
 367         [TSU_ADSBSY]    = 0x0060,
 368         [TSU_TEN]       = 0x0064,
 369         [TSU_POST1]     = 0x0070,
 370         [TSU_POST2]     = 0x0074,
 371         [TSU_POST3]     = 0x0078,
 372         [TSU_POST4]     = 0x007c,
 373
 374         [TXNLCR0]       = 0x0080,
 375         [TXALCR0]       = 0x0084,
 376         [RXNLCR0]       = 0x0088,
 377         [RXALCR0]       = 0x008c,
 378         [FWNLCR0]       = 0x0090,
 379         [FWALCR0]       = 0x0094,
 380         [TXNLCR1]       = 0x00a0,
 381         [TXALCR1]       = 0x00a0,
 382         [RXNLCR1]       = 0x00a8,
 383         [RXALCR1]       = 0x00ac,
 384         [FWNLCR1]       = 0x00b0,
 385         [FWALCR1]       = 0x00b4,
 386
 387         [TSU_ADRH0]     = 0x0100,
 388         [TSU_ADRL0]     = 0x0104,
 389         [TSU_ADRL31]    = 0x01fc,
 390 };
 391
 392 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 393 {
 394         return mdp->reg_offset == sh_eth_offset_gigabit;
 395 }
 396
 397 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 398 {
 399         return mdp->reg_offset == sh_eth_offset_fast_rz;
 400 }
 401
 402 static void sh_eth_select_mii(struct net_device *ndev)
 403 {
 404         u32 value = 0x0;
 405         struct sh_eth_private *mdp = netdev_priv(ndev);
 406
 407         switch (mdp->phy_interface) {
 408         case PHY_INTERFACE_MODE_GMII:
 409                 value = 0x2;
 410                 break;
 411         case PHY_INTERFACE_MODE_MII:
 412                 value = 0x1;
 413                 break;
 414         case PHY_INTERFACE_MODE_RMII:
 415                 value = 0x0;
 416                 break;
 417         default:
 418                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 419                 value = 0x1;
 420                 break;
 421         }
 422
 423         sh_eth_write(ndev, value, RMII_MII);
 424 }
 425
 426 static void sh_eth_set_duplex(struct net_device *ndev)
 427 {
 428         struct sh_eth_private *mdp = netdev_priv(ndev);
 429
 430         if (mdp->duplex) /* Full */
 431                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 432         else            /* Half */
 433                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 434 }
 435
 436 /* There is CPU dependent code */
 437 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 438 {
 439         struct sh_eth_private *mdp = netdev_priv(ndev);
 440
 441         switch (mdp->speed) {
 442         case 10: /* 10BASE */
 443                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 444                 break;
 445         case 100:/* 100BASE */
 446                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 447                 break;
 448         default:
 449                 break;
 450         }
 451 }
 452
 453 /* R8A7778/9 */
 454 static struct sh_eth_cpu_data r8a777x_data = {
 455         .set_duplex     = sh_eth_set_duplex,
 456         .set_rate       = sh_eth_set_rate_r8a777x,
 457
 458         .register_type  = SH_ETH_REG_FAST_RCAR,
 459
 460         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 461         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 462         .eesipr_value   = 0x01ff009f,
 463
 464         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 465         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 466                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 467                           EESR_ECI,
 468
 469         .apr            = 1,
 470         .mpr            = 1,
 471         .tpauser        = 1,
 472         .hw_swap        = 1,
 473 };
 474
 475 /* R8A7790/1 */
 476 static struct sh_eth_cpu_data r8a779x_data = {
 477         .set_duplex     = sh_eth_set_duplex,
 478         .set_rate       = sh_eth_set_rate_r8a777x,
 479
 480         .register_type  = SH_ETH_REG_FAST_RCAR,
 481
 482         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 483         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 484         .eesipr_value   = 0x01ff009f,
 485
 486         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 487         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 488                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 489                           EESR_ECI,
 490
 491         .apr            = 1,
 492         .mpr            = 1,
 493         .tpauser        = 1,
 494         .hw_swap        = 1,
 495         .rmiimode       = 1,
 496         .shift_rd0      = 1,
 497 };
 498
 499 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 500 {
 501         struct sh_eth_private *mdp = netdev_priv(ndev);
 502
 503         switch (mdp->speed) {
 504         case 10: /* 10BASE */
 505                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 506                 break;
 507         case 100:/* 100BASE */
 508                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 509                 break;
 510         default:
 511                 break;
 512         }
 513 }
 514
 515 /* SH7724 */
 516 static struct sh_eth_cpu_data sh7724_data = {
 517         .set_duplex     = sh_eth_set_duplex,
 518         .set_rate       = sh_eth_set_rate_sh7724,
 519
 520         .register_type  = SH_ETH_REG_FAST_SH4,
 521
 522         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 523         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 524         .eesipr_value   = 0x01ff009f,
 525
 526         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 527         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 528                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 529                           EESR_ECI,
 530
 531         .apr            = 1,
 532         .mpr            = 1,
 533         .tpauser        = 1,
 534         .hw_swap        = 1,
 535         .rpadir         = 1,
 536         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 537 };
 538
 539 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 540 {
 541         struct sh_eth_private *mdp = netdev_priv(ndev);
 542
 543         switch (mdp->speed) {
 544         case 10: /* 10BASE */
 545                 sh_eth_write(ndev, 0, RTRATE);
 546                 break;
 547         case 100:/* 100BASE */
 548                 sh_eth_write(ndev, 1, RTRATE);
 549                 break;
 550         default:
 551                 break;
 552         }
 553 }
 554
 555 /* SH7757 */
 556 static struct sh_eth_cpu_data sh7757_data = {
 557         .set_duplex     = sh_eth_set_duplex,
 558         .set_rate       = sh_eth_set_rate_sh7757,
 559
 560         .register_type  = SH_ETH_REG_FAST_SH4,
 561
 562         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 563
 564         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 565         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 566                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 567                           EESR_ECI,
 568
 569         .irq_flags      = IRQF_SHARED,
 570         .apr            = 1,
 571         .mpr            = 1,
 572         .tpauser        = 1,
 573         .hw_swap        = 1,
 574         .no_ade         = 1,
 575         .rpadir         = 1,
 576         .rpadir_value   = 2 << 16,
 577 };
 578
 579 #define SH_GIGA_ETH_BASE        0xfee00000UL
 580 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 581 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 582 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 583 {
 584         int i;
 585         unsigned long mahr[2], malr[2];
 586
 587         /* save MAHR and MALR */
 588         for (i = 0; i < 2; i++) {
 589                 malr[i] = ioread32((void *)GIGA_MALR(i));
 590                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 591         }
 592
 593         /* reset device */
 594         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 595         mdelay(1);
 596
 597         /* restore MAHR and MALR */
 598         for (i = 0; i < 2; i++) {
 599                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 600                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 601         }
 602 }
 603
 604 static void sh_eth_set_rate_giga(struct net_device *ndev)
 605 {
 606         struct sh_eth_private *mdp = netdev_priv(ndev);
 607
 608         switch (mdp->speed) {
 609         case 10: /* 10BASE */
 610                 sh_eth_write(ndev, 0x00000000, GECMR);
 611                 break;
 612         case 100:/* 100BASE */
 613                 sh_eth_write(ndev, 0x00000010, GECMR);
 614                 break;
 615         case 1000: /* 1000BASE */
 616                 sh_eth_write(ndev, 0x00000020, GECMR);
 617                 break;
 618         default:
 619                 break;
 620         }
 621 }
 622
 623 /* SH7757(GETHERC) */
 624 static struct sh_eth_cpu_data sh7757_data_giga = {
 625         .chip_reset     = sh_eth_chip_reset_giga,
 626         .set_duplex     = sh_eth_set_duplex,
 627         .set_rate       = sh_eth_set_rate_giga,
 628
 629         .register_type  = SH_ETH_REG_GIGABIT,
 630
 631         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 632         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 633         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 634
 635         .tx_check       = EESR_TC1 | EESR_FTC,
 636         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 637                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 638                           EESR_TDE | EESR_ECI,
 639         .fdr_value      = 0x0000072f,
 640
 641         .irq_flags      = IRQF_SHARED,
 642         .apr            = 1,
 643         .mpr            = 1,
 644         .tpauser        = 1,
 645         .bculr          = 1,
 646         .hw_swap        = 1,
 647         .rpadir         = 1,
 648         .rpadir_value   = 2 << 16,
 649         .no_trimd       = 1,
 650         .no_ade         = 1,
 651         .tsu            = 1,
 652 };
 653
 654 static void sh_eth_chip_reset(struct net_device *ndev)
 655 {
 656         struct sh_eth_private *mdp = netdev_priv(ndev);
 657
 658         /* reset device */
 659         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 660         mdelay(1);
 661 }
 662
 663 static void sh_eth_set_rate_gether(struct net_device *ndev)
 664 {
 665         struct sh_eth_private *mdp = netdev_priv(ndev);
 666
 667         switch (mdp->speed) {
 668         case 10: /* 10BASE */
 669                 sh_eth_write(ndev, GECMR_10, GECMR);
 670                 break;
 671         case 100:/* 100BASE */
 672                 sh_eth_write(ndev, GECMR_100, GECMR);
 673                 break;
 674         case 1000: /* 1000BASE */
 675                 sh_eth_write(ndev, GECMR_1000, GECMR);
 676                 break;
 677         default:
 678                 break;
 679         }
 680 }
 681
 682 /* SH7734 */
 683 static struct sh_eth_cpu_data sh7734_data = {
 684         .chip_reset     = sh_eth_chip_reset,
 685         .set_duplex     = sh_eth_set_duplex,
 686         .set_rate       = sh_eth_set_rate_gether,
 687
 688         .register_type  = SH_ETH_REG_GIGABIT,
 689
 690         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 691         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 692         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 693
 694         .tx_check       = EESR_TC1 | EESR_FTC,
 695         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 696                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 697                           EESR_TDE | EESR_ECI,
 698
 699         .apr            = 1,
 700         .mpr            = 1,
 701         .tpauser        = 1,
 702         .bculr          = 1,
 703         .hw_swap        = 1,
 704         .no_trimd       = 1,
 705         .no_ade         = 1,
 706         .tsu            = 1,
 707         .hw_crc         = 1,
 708         .select_mii     = 1,
 709 };
 710
 711 /* SH7763 */
 712 static struct sh_eth_cpu_data sh7763_data = {
 713         .chip_reset     = sh_eth_chip_reset,
 714         .set_duplex     = sh_eth_set_duplex,
 715         .set_rate       = sh_eth_set_rate_gether,
 716
 717         .register_type  = SH_ETH_REG_GIGABIT,
 718
 719         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 720         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 721         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 722
 723         .tx_check       = EESR_TC1 | EESR_FTC,
 724         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 725                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 726                           EESR_ECI,
 727
 728         .apr            = 1,
 729         .mpr            = 1,
 730         .tpauser        = 1,
 731         .bculr          = 1,
 732         .hw_swap        = 1,
 733         .no_trimd       = 1,
 734         .no_ade         = 1,
 735         .tsu            = 1,
 736         .irq_flags      = IRQF_SHARED,
 737 };
 738
 739 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 740 {
 741         struct sh_eth_private *mdp = netdev_priv(ndev);
 742
 743         /* reset device */
 744         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 745         mdelay(1);
 746
 747         sh_eth_select_mii(ndev);
 748 }
 749
 750 /* R8A7740 */
 751 static struct sh_eth_cpu_data r8a7740_data = {
 752         .chip_reset     = sh_eth_chip_reset_r8a7740,
 753         .set_duplex     = sh_eth_set_duplex,
 754         .set_rate       = sh_eth_set_rate_gether,
 755
 756         .register_type  = SH_ETH_REG_GIGABIT,
 757
 758         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 759         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 760         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 761
 762         .tx_check       = EESR_TC1 | EESR_FTC,
 763         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 764                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 765                           EESR_TDE | EESR_ECI,
 766         .fdr_value      = 0x0000070f,
 767
 768         .apr            = 1,
 769         .mpr            = 1,
 770         .tpauser        = 1,
 771         .bculr          = 1,
 772         .hw_swap        = 1,
 773         .rpadir         = 1,
 774         .rpadir_value   = 2 << 16,
 775         .no_trimd       = 1,
 776         .no_ade         = 1,
 777         .tsu            = 1,
 778         .select_mii     = 1,
 779         .shift_rd0      = 1,
 780 };
 781
 782 /* R7S72100 */
 783 static struct sh_eth_cpu_data r7s72100_data = {
 784         .chip_reset     = sh_eth_chip_reset,
 785         .set_duplex     = sh_eth_set_duplex,
 786
 787         .register_type  = SH_ETH_REG_FAST_RZ,
 788
 789         .ecsr_value     = ECSR_ICD,
 790         .ecsipr_value   = ECSIPR_ICDIP,
 791         .eesipr_value   = 0xff7f009f,
 792
 793         .tx_check       = EESR_TC1 | EESR_FTC,
 794         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 795                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 796                           EESR_TDE | EESR_ECI,
 797         .fdr_value      = 0x0000070f,
 798
 799         .no_psr         = 1,
 800         .apr            = 1,
 801         .mpr            = 1,
 802         .tpauser        = 1,
 803         .hw_swap        = 1,
 804         .rpadir         = 1,
 805         .rpadir_value   = 2 << 16,
 806         .no_trimd       = 1,
 807         .no_ade         = 1,
 808         .hw_crc         = 1,
 809         .tsu            = 1,
 810         .shift_rd0      = 1,
 811 };
 812
 813 static struct sh_eth_cpu_data sh7619_data = {
 814         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 815
 816         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 817
 818         .apr            = 1,
 819         .mpr            = 1,
 820         .tpauser        = 1,
 821         .hw_swap        = 1,
 822 };
 823
 824 static struct sh_eth_cpu_data sh771x_data = {
 825         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 826
 827         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 828         .tsu            = 1,
 829 };
 830
 831 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 832 {
 833         if (!cd->ecsr_value)
 834                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 835
 836         if (!cd->ecsipr_value)
 837                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 838
 839         if (!cd->fcftr_value)
 840                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 841                                   DEFAULT_FIFO_F_D_RFD;
 842
 843         if (!cd->fdr_value)
 844                 cd->fdr_value = DEFAULT_FDR_INIT;
 845
 846         if (!cd->tx_check)
 847                 cd->tx_check = DEFAULT_TX_CHECK;
 848
 849         if (!cd->eesr_err_check)
 850                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 851 }
 852
 853 static int sh_eth_check_reset(struct net_device *ndev)
 854 {
 855         int ret = 0;
 856         int cnt = 100;
 857
 858         while (cnt > 0) {
 859                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 860                         break;
 861                 mdelay(1);
 862                 cnt--;
 863         }
 864         if (cnt <= 0) {
 865                 pr_err("Device reset failed\n");
 866                 ret = -ETIMEDOUT;
 867         }
 868         return ret;
 869 }
 870
 871 static int sh_eth_reset(struct net_device *ndev)
 872 {
 873         struct sh_eth_private *mdp = netdev_priv(ndev);
 874         int ret = 0;
 875
 876         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 877                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 878                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 879                              EDMR);
 880
 881                 ret = sh_eth_check_reset(ndev);
 882                 if (ret)
 883                         goto out;
 884
 885                 /* Table Init */
 886                 sh_eth_write(ndev, 0x0, TDLAR);
 887                 sh_eth_write(ndev, 0x0, TDFAR);
 888                 sh_eth_write(ndev, 0x0, TDFXR);
 889                 sh_eth_write(ndev, 0x0, TDFFR);
 890                 sh_eth_write(ndev, 0x0, RDLAR);
 891                 sh_eth_write(ndev, 0x0, RDFAR);
 892                 sh_eth_write(ndev, 0x0, RDFXR);
 893                 sh_eth_write(ndev, 0x0, RDFFR);
 894
 895                 /* Reset HW CRC register */
 896                 if (mdp->cd->hw_crc)
 897                         sh_eth_write(ndev, 0x0, CSMR);
 898
 899                 /* Select MII mode */
 900                 if (mdp->cd->select_mii)
 901                         sh_eth_select_mii(ndev);
 902         } else {
 903                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 904                              EDMR);
 905                 mdelay(3);
 906                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 907                              EDMR);
 908         }
 909
 910 out:
 911         return ret;
 912 }
 913
 914 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 915 static void sh_eth_set_receive_align(struct sk_buff *skb)
 916 {
 917         int reserve;
 918
 919         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 920         if (reserve)
 921                 skb_reserve(skb, reserve);
 922 }
 923 #else
 924 static void sh_eth_set_receive_align(struct sk_buff *skb)
 925 {
 926         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 927 }
 928 #endif
 929
 930
 931 /* CPU <-> EDMAC endian convert */
 932 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 933 {
 934         switch (mdp->edmac_endian) {
 935         case EDMAC_LITTLE_ENDIAN:
 936                 return cpu_to_le32(x);
 937         case EDMAC_BIG_ENDIAN:
 938                 return cpu_to_be32(x);
 939         }
 940         return x;
 941 }
 942
 943 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 944 {
 945         switch (mdp->edmac_endian) {
 946         case EDMAC_LITTLE_ENDIAN:
 947                 return le32_to_cpu(x);
 948         case EDMAC_BIG_ENDIAN:
 949                 return be32_to_cpu(x);
 950         }
 951         return x;
 952 }
 953
 954 /* Program the hardware MAC address from dev->dev_addr. */
 955 static void update_mac_address(struct net_device *ndev)
 956 {
 957         sh_eth_write(ndev,
 958                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 959                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 960         sh_eth_write(ndev,
 961                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 962 }
 963
 964 /* Get MAC address from SuperH MAC address register
 965  *
 966  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 967  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 968  * When you want use this device, you must set MAC address in bootloader.
 969  *
 970  */
 971 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 972 {
 973         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 974                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 975         } else {
 976                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 977                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 978                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 979                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 980                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 981                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 982         }
 983 }
 984
 985 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 986 {
 987         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 988                 return EDTRR_TRNS_GETHER;
 989         else
 990                 return EDTRR_TRNS_ETHER;
 991 }
 992
 993 struct bb_info {
 994         void (*set_gate)(void *addr);
 995         struct mdiobb_ctrl ctrl;
 996         void *addr;
 997         u32 mmd_msk;/* MMD */
 998         u32 mdo_msk;
 999         u32 mdi_msk;
1000         u32 mdc_msk;
1001 };
1002
1003 /* PHY bit set */
1004 static void bb_set(void *addr, u32 msk)
1005 {
1006         iowrite32(ioread32(addr) | msk, addr);
1007 }
1008
1009 /* PHY bit clear */
1010 static void bb_clr(void *addr, u32 msk)
1011 {
1012         iowrite32((ioread32(addr) & ~msk), addr);
1013 }
1014
1015 /* PHY bit read */
1016 static int bb_read(void *addr, u32 msk)
1017 {
1018         return (ioread32(addr) & msk) != 0;
1019 }
1020
1021 /* Data I/O pin control */
1022 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1023 {
1024         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1025
1026         if (bitbang->set_gate)
1027                 bitbang->set_gate(bitbang->addr);
1028
1029         if (bit)
1030                 bb_set(bitbang->addr, bitbang->mmd_msk);
1031         else
1032                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1033 }
1034
1035 /* Set bit data*/
1036 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1037 {
1038         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1039
1040         if (bitbang->set_gate)
1041                 bitbang->set_gate(bitbang->addr);
1042
1043         if (bit)
1044                 bb_set(bitbang->addr, bitbang->mdo_msk);
1045         else
1046                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1047 }
1048
1049 /* Get bit data*/
1050 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1051 {
1052         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1053
1054         if (bitbang->set_gate)
1055                 bitbang->set_gate(bitbang->addr);
1056
1057         return bb_read(bitbang->addr, bitbang->mdi_msk);
1058 }
1059
1060 /* MDC pin control */
1061 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1062 {
1063         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1064
1065         if (bitbang->set_gate)
1066                 bitbang->set_gate(bitbang->addr);
1067
1068         if (bit)
1069                 bb_set(bitbang->addr, bitbang->mdc_msk);
1070         else
1071                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1072 }
1073
1074 /* mdio bus control struct */
1075 static struct mdiobb_ops bb_ops = {
1076         .owner = THIS_MODULE,
1077         .set_mdc = sh_mdc_ctrl,
1078         .set_mdio_dir = sh_mmd_ctrl,
1079         .set_mdio_data = sh_set_mdio,
1080         .get_mdio_data = sh_get_mdio,
1081 };
1082
1083 /* free skb and descriptor buffer */
1084 static void sh_eth_ring_free(struct net_device *ndev)
1085 {
1086         struct sh_eth_private *mdp = netdev_priv(ndev);
1087         int i;
1088
1089         /* Free Rx skb ringbuffer */
1090         if (mdp->rx_skbuff) {
1091                 for (i = 0; i < mdp->num_rx_ring; i++) {
1092                         if (mdp->rx_skbuff[i])
1093                                 dev_kfree_skb(mdp->rx_skbuff[i]);
1094                 }
1095         }
1096         kfree(mdp->rx_skbuff);
1097         mdp->rx_skbuff = NULL;
1098
1099         /* Free Tx skb ringbuffer */
1100         if (mdp->tx_skbuff) {
1101                 for (i = 0; i < mdp->num_tx_ring; i++) {
1102                         if (mdp->tx_skbuff[i])
1103                                 dev_kfree_skb(mdp->tx_skbuff[i]);
1104                 }
1105         }
1106         kfree(mdp->tx_skbuff);
1107         mdp->tx_skbuff = NULL;
1108 }
1109
1110 /* format skb and descriptor buffer */
1111 static void sh_eth_ring_format(struct net_device *ndev)
1112 {
1113         struct sh_eth_private *mdp = netdev_priv(ndev);
1114         int i;
1115         struct sk_buff *skb;
1116         struct sh_eth_rxdesc *rxdesc = NULL;
1117         struct sh_eth_txdesc *txdesc = NULL;
1118         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1119         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1120
1121         mdp->cur_rx = 0;
1122         mdp->cur_tx = 0;
1123         mdp->dirty_rx = 0;
1124         mdp->dirty_tx = 0;
1125
1126         memset(mdp->rx_ring, 0, rx_ringsize);
1127
1128         /* build Rx ring buffer */
1129         for (i = 0; i < mdp->num_rx_ring; i++) {
1130                 /* skb */
1131                 mdp->rx_skbuff[i] = NULL;
1132                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1133                 mdp->rx_skbuff[i] = skb;
1134                 if (skb == NULL)
1135                         break;
1136                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1137                                DMA_FROM_DEVICE);
1138                 sh_eth_set_receive_align(skb);
1139
1140                 /* RX descriptor */
1141                 rxdesc = &mdp->rx_ring[i];
1142                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1143                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1144
1145                 /* The size of the buffer is 16 byte boundary. */
1146                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1147                 /* Rx descriptor address set */
1148                 if (i == 0) {
1149                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1150                         if (sh_eth_is_gether(mdp) ||
1151                             sh_eth_is_rz_fast_ether(mdp))
1152                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1153                 }
1154         }
1155
1156         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1157
1158         /* Mark the last entry as wrapping the ring. */
1159         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1160
1161         memset(mdp->tx_ring, 0, tx_ringsize);
1162
1163         /* build Tx ring buffer */
1164         for (i = 0; i < mdp->num_tx_ring; i++) {
1165                 mdp->tx_skbuff[i] = NULL;
1166                 txdesc = &mdp->tx_ring[i];
1167                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1168                 txdesc->buffer_length = 0;
1169                 if (i == 0) {
1170                         /* Tx descriptor address set */
1171                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1172                         if (sh_eth_is_gether(mdp) ||
1173                             sh_eth_is_rz_fast_ether(mdp))
1174                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1175                 }
1176         }
1177
1178         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1179 }
1180
1181 /* Get skb and descriptor buffer */
1182 static int sh_eth_ring_init(struct net_device *ndev)
1183 {
1184         struct sh_eth_private *mdp = netdev_priv(ndev);
1185         int rx_ringsize, tx_ringsize, ret = 0;
1186
1187         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1188          * card needs room to do 8 byte alignment, +2 so we can reserve
1189          * the first 2 bytes, and +16 gets room for the status word from the
1190          * card.
1191          */
1192         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1193                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1194         if (mdp->cd->rpadir)
1195                 mdp->rx_buf_sz += NET_IP_ALIGN;
1196
1197         /* Allocate RX and TX skb rings */
1198         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1199                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1200         if (!mdp->rx_skbuff) {
1201                 ret = -ENOMEM;
1202                 return ret;
1203         }
1204
1205         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1206                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1207         if (!mdp->tx_skbuff) {
1208                 ret = -ENOMEM;
1209                 goto skb_ring_free;
1210         }
1211
1212         /* Allocate all Rx descriptors. */
1213         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1214         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1215                                           GFP_KERNEL);
1216         if (!mdp->rx_ring) {
1217                 ret = -ENOMEM;
1218                 goto desc_ring_free;
1219         }
1220
1221         mdp->dirty_rx = 0;
1222
1223         /* Allocate all Tx descriptors. */
1224         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1225         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1226                                           GFP_KERNEL);
1227         if (!mdp->tx_ring) {
1228                 ret = -ENOMEM;
1229                 goto desc_ring_free;
1230         }
1231         return ret;
1232
1233 desc_ring_free:
1234         /* free DMA buffer */
1235         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1236
1237 skb_ring_free:
1238         /* Free Rx and Tx skb ring buffer */
1239         sh_eth_ring_free(ndev);
1240         mdp->tx_ring = NULL;
1241         mdp->rx_ring = NULL;
1242
1243         return ret;
1244 }
1245
1246 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1247 {
1248         int ringsize;
1249
1250         if (mdp->rx_ring) {
1251                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1252                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1253                                   mdp->rx_desc_dma);
1254                 mdp->rx_ring = NULL;
1255         }
1256
1257         if (mdp->tx_ring) {
1258                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1259                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1260                                   mdp->tx_desc_dma);
1261                 mdp->tx_ring = NULL;
1262         }
1263 }
1264
1265 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1266 {
1267         int ret = 0;
1268         struct sh_eth_private *mdp = netdev_priv(ndev);
1269         u32 val;
1270
1271         /* Soft Reset */
1272         ret = sh_eth_reset(ndev);
1273         if (ret)
1274                 goto out;
1275
1276         if (mdp->cd->rmiimode)
1277                 sh_eth_write(ndev, 0x1, RMIIMODE);
1278
1279         /* Descriptor format */
1280         sh_eth_ring_format(ndev);
1281         if (mdp->cd->rpadir)
1282                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1283
1284         /* all sh_eth int mask */
1285         sh_eth_write(ndev, 0, EESIPR);
1286
1287 #if defined(__LITTLE_ENDIAN)
1288         if (mdp->cd->hw_swap)
1289                 sh_eth_write(ndev, EDMR_EL, EDMR);
1290         else
1291 #endif
1292                 sh_eth_write(ndev, 0, EDMR);
1293
1294         /* FIFO size set */
1295         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1296         sh_eth_write(ndev, 0, TFTR);
1297
1298         /* Frame recv control (enable multiple-packets per rx irq) */
1299         sh_eth_write(ndev, RMCR_RNC, RMCR);
1300
1301         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1302
1303         if (mdp->cd->bculr)
1304                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1305
1306         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1307
1308         if (!mdp->cd->no_trimd)
1309                 sh_eth_write(ndev, 0, TRIMD);
1310
1311         /* Recv frame limit set register */
1312         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1313                      RFLR);
1314
1315         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1316         if (start)
1317                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1318
1319         /* PAUSE Prohibition */
1320         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1321                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1322
1323         sh_eth_write(ndev, val, ECMR);
1324
1325         if (mdp->cd->set_rate)
1326                 mdp->cd->set_rate(ndev);
1327
1328         /* E-MAC Status Register clear */
1329         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1330
1331         /* E-MAC Interrupt Enable register */
1332         if (start)
1333                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1334
1335         /* Set MAC address */
1336         update_mac_address(ndev);
1337
1338         /* mask reset */
1339         if (mdp->cd->apr)
1340                 sh_eth_write(ndev, APR_AP, APR);
1341         if (mdp->cd->mpr)
1342                 sh_eth_write(ndev, MPR_MP, MPR);
1343         if (mdp->cd->tpauser)
1344                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1345
1346         if (start) {
1347                 /* Setting the Rx mode will start the Rx process. */
1348                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1349
1350                 netif_start_queue(ndev);
1351         }
1352
1353 out:
1354         return ret;
1355 }
1356
1357 /* free Tx skb function */
1358 static int sh_eth_txfree(struct net_device *ndev)
1359 {
1360         struct sh_eth_private *mdp = netdev_priv(ndev);
1361         struct sh_eth_txdesc *txdesc;
1362         int free_num = 0;
1363         int entry = 0;
1364
1365         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1366                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1367                 txdesc = &mdp->tx_ring[entry];
1368                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1369                         break;
1370                 /* Free the original skb. */
1371                 if (mdp->tx_skbuff[entry]) {
1372                         dma_unmap_single(&ndev->dev, txdesc->addr,
1373                                          txdesc->buffer_length, DMA_TO_DEVICE);
1374                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1375                         mdp->tx_skbuff[entry] = NULL;
1376                         free_num++;
1377                 }
1378                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1379                 if (entry >= mdp->num_tx_ring - 1)
1380                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1381
1382                 ndev->stats.tx_packets++;
1383                 ndev->stats.tx_bytes += txdesc->buffer_length;
1384         }
1385         return free_num;
1386 }
1387
1388 /* Packet receive function */
1389 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1390 {
1391         struct sh_eth_private *mdp = netdev_priv(ndev);
1392         struct sh_eth_rxdesc *rxdesc;
1393
1394         int entry = mdp->cur_rx % mdp->num_rx_ring;
1395         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1396         struct sk_buff *skb;
1397         int exceeded = 0;
1398         u16 pkt_len = 0;
1399         u32 desc_status;
1400
1401         rxdesc = &mdp->rx_ring[entry];
1402         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1403                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1404                 pkt_len = rxdesc->frame_length;
1405
1406                 if (--boguscnt < 0)
1407                         break;
1408
1409                 if (*quota <= 0) {
1410                         exceeded = 1;
1411                         break;
1412                 }
1413                 (*quota)--;
1414
1415                 if (!(desc_status & RDFEND))
1416                         ndev->stats.rx_length_errors++;
1417
1418                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1419                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1420                  * bit 0. However, in case of the R8A7740, R8A779x, and
1421                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1422                  * driver needs right shifting by 16.
1423                  */
1424                 if (mdp->cd->shift_rd0)
1425                         desc_status >>= 16;
1426
1427                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1428                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1429                         ndev->stats.rx_errors++;
1430                         if (desc_status & RD_RFS1)
1431                                 ndev->stats.rx_crc_errors++;
1432                         if (desc_status & RD_RFS2)
1433                                 ndev->stats.rx_frame_errors++;
1434                         if (desc_status & RD_RFS3)
1435                                 ndev->stats.rx_length_errors++;
1436                         if (desc_status & RD_RFS4)
1437                                 ndev->stats.rx_length_errors++;
1438                         if (desc_status & RD_RFS6)
1439                                 ndev->stats.rx_missed_errors++;
1440                         if (desc_status & RD_RFS10)
1441                                 ndev->stats.rx_over_errors++;
1442                 } else {
1443                         if (!mdp->cd->hw_swap)
1444                                 sh_eth_soft_swap(
1445                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1446                                         pkt_len + 2);
1447                         skb = mdp->rx_skbuff[entry];
1448                         mdp->rx_skbuff[entry] = NULL;
1449                         if (mdp->cd->rpadir)
1450                                 skb_reserve(skb, NET_IP_ALIGN);
1451                         dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1452                                                 mdp->rx_buf_sz,
1453                                                 DMA_FROM_DEVICE);
1454                         skb_put(skb, pkt_len);
1455                         skb->protocol = eth_type_trans(skb, ndev);
1456                         netif_receive_skb(skb);
1457                         ndev->stats.rx_packets++;
1458                         ndev->stats.rx_bytes += pkt_len;
1459                 }
1460                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1461                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1462                 rxdesc = &mdp->rx_ring[entry];
1463         }
1464
1465         /* Refill the Rx ring buffers. */
1466         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1467                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1468                 rxdesc = &mdp->rx_ring[entry];
1469                 /* The size of the buffer is 16 byte boundary. */
1470                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1471
1472                 if (mdp->rx_skbuff[entry] == NULL) {
1473                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1474                         mdp->rx_skbuff[entry] = skb;
1475                         if (skb == NULL)
1476                                 break;  /* Better luck next round. */
1477                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1478                                        DMA_FROM_DEVICE);
1479                         sh_eth_set_receive_align(skb);
1480
1481                         skb_checksum_none_assert(skb);
1482                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1483                 }
1484                 if (entry >= mdp->num_rx_ring - 1)
1485                         rxdesc->status |=
1486                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1487                 else
1488                         rxdesc->status |=
1489                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1490         }
1491
1492         /* Restart Rx engine if stopped. */
1493         /* If we don't need to check status, don't. -KDU */
1494         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1495                 /* fix the values for the next receiving if RDE is set */
1496                 if (intr_status & EESR_RDE) {
1497                         u32 count = (sh_eth_read(ndev, RDFAR) -
1498                                      sh_eth_read(ndev, RDLAR)) >> 4;
1499
1500                         mdp->cur_rx = count;
1501                         mdp->dirty_rx = count;
1502                 }
1503                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1504         }
1505
1506         return exceeded;
1507 }
1508
1509 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1510 {
1511         /* disable tx and rx */
1512         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1513                 ~(ECMR_RE | ECMR_TE), ECMR);
1514 }
1515
1516 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1517 {
1518         /* enable tx and rx */
1519         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1520                 (ECMR_RE | ECMR_TE), ECMR);
1521 }
1522
1523 /* error control function */
1524 static void sh_eth_error(struct net_device *ndev, int intr_status)
1525 {
1526         struct sh_eth_private *mdp = netdev_priv(ndev);
1527         u32 felic_stat;
1528         u32 link_stat;
1529         u32 mask;
1530
1531         if (intr_status & EESR_ECI) {
1532                 felic_stat = sh_eth_read(ndev, ECSR);
1533                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1534                 if (felic_stat & ECSR_ICD)
1535                         ndev->stats.tx_carrier_errors++;
1536                 if (felic_stat & ECSR_LCHNG) {
1537                         /* Link Changed */
1538                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1539                                 goto ignore_link;
1540                         } else {
1541                                 link_stat = (sh_eth_read(ndev, PSR));
1542                                 if (mdp->ether_link_active_low)
1543                                         link_stat = ~link_stat;
1544                         }
1545                         if (!(link_stat & PHY_ST_LINK)) {
1546                                 sh_eth_rcv_snd_disable(ndev);
1547                         } else {
1548                                 /* Link Up */
1549                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1550                                                    ~DMAC_M_ECI, EESIPR);
1551                                 /* clear int */
1552                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1553                                              ECSR);
1554                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1555                                                    DMAC_M_ECI, EESIPR);
1556                                 /* enable tx and rx */
1557                                 sh_eth_rcv_snd_enable(ndev);
1558                         }
1559                 }
1560         }
1561
1562 ignore_link:
1563         if (intr_status & EESR_TWB) {
1564                 /* Unused write back interrupt */
1565                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1566                         ndev->stats.tx_aborted_errors++;
1567                         if (netif_msg_tx_err(mdp))
1568                                 dev_err(&ndev->dev, "Transmit Abort\n");
1569                 }
1570         }
1571
1572         if (intr_status & EESR_RABT) {
1573                 /* Receive Abort int */
1574                 if (intr_status & EESR_RFRMER) {
1575                         /* Receive Frame Overflow int */
1576                         ndev->stats.rx_frame_errors++;
1577                         if (netif_msg_rx_err(mdp))
1578                                 dev_err(&ndev->dev, "Receive Abort\n");
1579                 }
1580         }
1581
1582         if (intr_status & EESR_TDE) {
1583                 /* Transmit Descriptor Empty int */
1584                 ndev->stats.tx_fifo_errors++;
1585                 if (netif_msg_tx_err(mdp))
1586                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1587         }
1588
1589         if (intr_status & EESR_TFE) {
1590                 /* FIFO under flow */
1591                 ndev->stats.tx_fifo_errors++;
1592                 if (netif_msg_tx_err(mdp))
1593                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1594         }
1595
1596         if (intr_status & EESR_RDE) {
1597                 /* Receive Descriptor Empty int */
1598                 ndev->stats.rx_over_errors++;
1599
1600                 if (netif_msg_rx_err(mdp))
1601                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1602         }
1603
1604         if (intr_status & EESR_RFE) {
1605                 /* Receive FIFO Overflow int */
1606                 ndev->stats.rx_fifo_errors++;
1607                 if (netif_msg_rx_err(mdp))
1608                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1609         }
1610
1611         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1612                 /* Address Error */
1613                 ndev->stats.tx_fifo_errors++;
1614                 if (netif_msg_tx_err(mdp))
1615                         dev_err(&ndev->dev, "Address Error\n");
1616         }
1617
1618         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1619         if (mdp->cd->no_ade)
1620                 mask &= ~EESR_ADE;
1621         if (intr_status & mask) {
1622                 /* Tx error */
1623                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1624
1625                 /* dmesg */
1626                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1627                         intr_status, mdp->cur_tx, mdp->dirty_tx,
1628                         (u32)ndev->state, edtrr);
1629                 /* dirty buffer free */
1630                 sh_eth_txfree(ndev);
1631
1632                 /* SH7712 BUG */
1633                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1634                         /* tx dma start */
1635                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1636                 }
1637                 /* wakeup */
1638                 netif_wake_queue(ndev);
1639         }
1640 }
1641
1642 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1643 {
1644         struct net_device *ndev = netdev;
1645         struct sh_eth_private *mdp = netdev_priv(ndev);
1646         struct sh_eth_cpu_data *cd = mdp->cd;
1647         irqreturn_t ret = IRQ_NONE;
1648         unsigned long intr_status, intr_enable;
1649
1650         spin_lock(&mdp->lock);
1651
1652         /* Get interrupt status */
1653         intr_status = sh_eth_read(ndev, EESR);
1654         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1655          * enabled since it's the one that  comes thru regardless of the mask,
1656          * and we need to fully handle it in sh_eth_error() in order to quench
1657          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1658          */
1659         intr_enable = sh_eth_read(ndev, EESIPR);
1660         intr_status &= intr_enable | DMAC_M_ECI;
1661         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1662                 ret = IRQ_HANDLED;
1663         else
1664                 goto other_irq;
1665
1666         if (intr_status & EESR_RX_CHECK) {
1667                 if (napi_schedule_prep(&mdp->napi)) {
1668                         /* Mask Rx interrupts */
1669                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1670                                      EESIPR);
1671                         __napi_schedule(&mdp->napi);
1672                 } else {
1673                         dev_warn(&ndev->dev,
1674                                  "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1675                                  intr_status, intr_enable);
1676                 }
1677         }
1678
1679         /* Tx Check */
1680         if (intr_status & cd->tx_check) {
1681                 /* Clear Tx interrupts */
1682                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1683
1684                 sh_eth_txfree(ndev);
1685                 netif_wake_queue(ndev);
1686         }
1687
1688         if (intr_status & cd->eesr_err_check) {
1689                 /* Clear error interrupts */
1690                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1691
1692                 sh_eth_error(ndev, intr_status);
1693         }
1694
1695 other_irq:
1696         spin_unlock(&mdp->lock);
1697
1698         return ret;
1699 }
1700
1701 static int sh_eth_poll(struct napi_struct *napi, int budget)
1702 {
1703         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1704                                                   napi);
1705         struct net_device *ndev = napi->dev;
1706         int quota = budget;
1707         unsigned long intr_status;
1708
1709         for (;;) {
1710                 intr_status = sh_eth_read(ndev, EESR);
1711                 if (!(intr_status & EESR_RX_CHECK))
1712                         break;
1713                 /* Clear Rx interrupts */
1714                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1715
1716                 if (sh_eth_rx(ndev, intr_status, &quota))
1717                         goto out;
1718         }
1719
1720         napi_complete(napi);
1721
1722         /* Reenable Rx interrupts */
1723         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1724 out:
1725         return budget - quota;
1726 }
1727
1728 /* PHY state control function */
1729 static void sh_eth_adjust_link(struct net_device *ndev)
1730 {
1731         struct sh_eth_private *mdp = netdev_priv(ndev);
1732         struct phy_device *phydev = mdp->phydev;
1733         int new_state = 0;
1734
1735         if (phydev->link) {
1736                 if (phydev->duplex != mdp->duplex) {
1737                         new_state = 1;
1738                         mdp->duplex = phydev->duplex;
1739                         if (mdp->cd->set_duplex)
1740                                 mdp->cd->set_duplex(ndev);
1741                 }
1742
1743                 if (phydev->speed != mdp->speed) {
1744                         new_state = 1;
1745                         mdp->speed = phydev->speed;
1746                         if (mdp->cd->set_rate)
1747                                 mdp->cd->set_rate(ndev);
1748                 }
1749                 if (!mdp->link) {
1750                         sh_eth_write(ndev,
1751                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1752                                      ECMR);
1753                         new_state = 1;
1754                         mdp->link = phydev->link;
1755                         if (mdp->cd->no_psr || mdp->no_ether_link)
1756                                 sh_eth_rcv_snd_enable(ndev);
1757                 }
1758         } else if (mdp->link) {
1759                 new_state = 1;
1760                 mdp->link = 0;
1761                 mdp->speed = 0;
1762                 mdp->duplex = -1;
1763                 if (mdp->cd->no_psr || mdp->no_ether_link)
1764                         sh_eth_rcv_snd_disable(ndev);
1765         }
1766
1767         if (new_state && netif_msg_link(mdp))
1768                 phy_print_status(phydev);
1769 }
1770
1771 /* PHY init function */
1772 static int sh_eth_phy_init(struct net_device *ndev)
1773 {
1774         struct sh_eth_private *mdp = netdev_priv(ndev);
1775         char phy_id[MII_BUS_ID_SIZE + 3];
1776         struct phy_device *phydev = NULL;
1777
1778         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1779                  mdp->mii_bus->id, mdp->phy_id);
1780
1781         mdp->link = 0;
1782         mdp->speed = 0;
1783         mdp->duplex = -1;
1784
1785         /* Try connect to PHY */
1786         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1787                              mdp->phy_interface);
1788         if (IS_ERR(phydev)) {
1789                 dev_err(&ndev->dev, "phy_connect failed\n");
1790                 return PTR_ERR(phydev);
1791         }
1792
1793         dev_info(&ndev->dev, "attached PHY %d (IRQ %d) to driver %s\n",
1794                  phydev->addr, phydev->irq, phydev->drv->name);
1795
1796         mdp->phydev = phydev;
1797
1798         return 0;
1799 }
1800
1801 /* PHY control start function */
1802 static int sh_eth_phy_start(struct net_device *ndev)
1803 {
1804         struct sh_eth_private *mdp = netdev_priv(ndev);
1805         int ret;
1806
1807         ret = sh_eth_phy_init(ndev);
1808         if (ret)
1809                 return ret;
1810
1811         phy_start(mdp->phydev);
1812
1813         return 0;
1814 }
1815
1816 static int sh_eth_get_settings(struct net_device *ndev,
1817                                struct ethtool_cmd *ecmd)
1818 {
1819         struct sh_eth_private *mdp = netdev_priv(ndev);
1820         unsigned long flags;
1821         int ret;
1822
1823         spin_lock_irqsave(&mdp->lock, flags);
1824         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1825         spin_unlock_irqrestore(&mdp->lock, flags);
1826
1827         return ret;
1828 }
1829
1830 static int sh_eth_set_settings(struct net_device *ndev,
1831                                struct ethtool_cmd *ecmd)
1832 {
1833         struct sh_eth_private *mdp = netdev_priv(ndev);
1834         unsigned long flags;
1835         int ret;
1836
1837         spin_lock_irqsave(&mdp->lock, flags);
1838
1839         /* disable tx and rx */
1840         sh_eth_rcv_snd_disable(ndev);
1841
1842         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1843         if (ret)
1844                 goto error_exit;
1845
1846         if (ecmd->duplex == DUPLEX_FULL)
1847                 mdp->duplex = 1;
1848         else
1849                 mdp->duplex = 0;
1850
1851         if (mdp->cd->set_duplex)
1852                 mdp->cd->set_duplex(ndev);
1853
1854 error_exit:
1855         mdelay(1);
1856
1857         /* enable tx and rx */
1858         sh_eth_rcv_snd_enable(ndev);
1859
1860         spin_unlock_irqrestore(&mdp->lock, flags);
1861
1862         return ret;
1863 }
1864
1865 static int sh_eth_nway_reset(struct net_device *ndev)
1866 {
1867         struct sh_eth_private *mdp = netdev_priv(ndev);
1868         unsigned long flags;
1869         int ret;
1870
1871         spin_lock_irqsave(&mdp->lock, flags);
1872         ret = phy_start_aneg(mdp->phydev);
1873         spin_unlock_irqrestore(&mdp->lock, flags);
1874
1875         return ret;
1876 }
1877
1878 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1879 {
1880         struct sh_eth_private *mdp = netdev_priv(ndev);
1881         return mdp->msg_enable;
1882 }
1883
1884 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1885 {
1886         struct sh_eth_private *mdp = netdev_priv(ndev);
1887         mdp->msg_enable = value;
1888 }
1889
1890 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1891         "rx_current", "tx_current",
1892         "rx_dirty", "tx_dirty",
1893 };
1894 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1895
1896 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1897 {
1898         switch (sset) {
1899         case ETH_SS_STATS:
1900                 return SH_ETH_STATS_LEN;
1901         default:
1902                 return -EOPNOTSUPP;
1903         }
1904 }
1905
1906 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1907                                      struct ethtool_stats *stats, u64 *data)
1908 {
1909         struct sh_eth_private *mdp = netdev_priv(ndev);
1910         int i = 0;
1911
1912         /* device-specific stats */
1913         data[i++] = mdp->cur_rx;
1914         data[i++] = mdp->cur_tx;
1915         data[i++] = mdp->dirty_rx;
1916         data[i++] = mdp->dirty_tx;
1917 }
1918
1919 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1920 {
1921         switch (stringset) {
1922         case ETH_SS_STATS:
1923                 memcpy(data, *sh_eth_gstrings_stats,
1924                        sizeof(sh_eth_gstrings_stats));
1925                 break;
1926         }
1927 }
1928
1929 static void sh_eth_get_ringparam(struct net_device *ndev,
1930                                  struct ethtool_ringparam *ring)
1931 {
1932         struct sh_eth_private *mdp = netdev_priv(ndev);
1933
1934         ring->rx_max_pending = RX_RING_MAX;
1935         ring->tx_max_pending = TX_RING_MAX;
1936         ring->rx_pending = mdp->num_rx_ring;
1937         ring->tx_pending = mdp->num_tx_ring;
1938 }
1939
1940 static int sh_eth_set_ringparam(struct net_device *ndev,
1941                                 struct ethtool_ringparam *ring)
1942 {
1943         struct sh_eth_private *mdp = netdev_priv(ndev);
1944         int ret;
1945
1946         if (ring->tx_pending > TX_RING_MAX ||
1947             ring->rx_pending > RX_RING_MAX ||
1948             ring->tx_pending < TX_RING_MIN ||
1949             ring->rx_pending < RX_RING_MIN)
1950                 return -EINVAL;
1951         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1952                 return -EINVAL;
1953
1954         if (netif_running(ndev)) {
1955                 netif_tx_disable(ndev);
1956                 /* Disable interrupts by clearing the interrupt mask. */
1957                 sh_eth_write(ndev, 0x0000, EESIPR);
1958                 /* Stop the chip's Tx and Rx processes. */
1959                 sh_eth_write(ndev, 0, EDTRR);
1960                 sh_eth_write(ndev, 0, EDRRR);
1961                 synchronize_irq(ndev->irq);
1962         }
1963
1964         /* Free all the skbuffs in the Rx queue. */
1965         sh_eth_ring_free(ndev);
1966         /* Free DMA buffer */
1967         sh_eth_free_dma_buffer(mdp);
1968
1969         /* Set new parameters */
1970         mdp->num_rx_ring = ring->rx_pending;
1971         mdp->num_tx_ring = ring->tx_pending;
1972
1973         ret = sh_eth_ring_init(ndev);
1974         if (ret < 0) {
1975                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1976                 return ret;
1977         }
1978         ret = sh_eth_dev_init(ndev, false);
1979         if (ret < 0) {
1980                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1981                 return ret;
1982         }
1983
1984         if (netif_running(ndev)) {
1985                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1986                 /* Setting the Rx mode will start the Rx process. */
1987                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1988                 netif_wake_queue(ndev);
1989         }
1990
1991         return 0;
1992 }
1993
1994 static const struct ethtool_ops sh_eth_ethtool_ops = {
1995         .get_settings   = sh_eth_get_settings,
1996         .set_settings   = sh_eth_set_settings,
1997         .nway_reset     = sh_eth_nway_reset,
1998         .get_msglevel   = sh_eth_get_msglevel,
1999         .set_msglevel   = sh_eth_set_msglevel,
2000         .get_link       = ethtool_op_get_link,
2001         .get_strings    = sh_eth_get_strings,
2002         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2003         .get_sset_count     = sh_eth_get_sset_count,
2004         .get_ringparam  = sh_eth_get_ringparam,
2005         .set_ringparam  = sh_eth_set_ringparam,
2006 };
2007
2008 /* network device open function */
2009 static int sh_eth_open(struct net_device *ndev)
2010 {
2011         int ret = 0;
2012         struct sh_eth_private *mdp = netdev_priv(ndev);
2013
2014         pm_runtime_get_sync(&mdp->pdev->dev);
2015
2016         napi_enable(&mdp->napi);
2017
2018         ret = request_irq(ndev->irq, sh_eth_interrupt,
2019                           mdp->cd->irq_flags, ndev->name, ndev);
2020         if (ret) {
2021                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
2022                 goto out_napi_off;
2023         }
2024
2025         /* Descriptor set */
2026         ret = sh_eth_ring_init(ndev);
2027         if (ret)
2028                 goto out_free_irq;
2029
2030         /* device init */
2031         ret = sh_eth_dev_init(ndev, true);
2032         if (ret)
2033                 goto out_free_irq;
2034
2035         /* PHY control start*/
2036         ret = sh_eth_phy_start(ndev);
2037         if (ret)
2038                 goto out_free_irq;
2039
2040         return ret;
2041
2042 out_free_irq:
2043         free_irq(ndev->irq, ndev);
2044 out_napi_off:
2045         napi_disable(&mdp->napi);
2046         pm_runtime_put_sync(&mdp->pdev->dev);
2047         return ret;
2048 }
2049
2050 /* Timeout function */
2051 static void sh_eth_tx_timeout(struct net_device *ndev)
2052 {
2053         struct sh_eth_private *mdp = netdev_priv(ndev);
2054         struct sh_eth_rxdesc *rxdesc;
2055         int i;
2056
2057         netif_stop_queue(ndev);
2058
2059         if (netif_msg_timer(mdp)) {
2060                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x, resetting...\n",
2061                         ndev->name, (int)sh_eth_read(ndev, EESR));
2062         }
2063
2064         /* tx_errors count up */
2065         ndev->stats.tx_errors++;
2066
2067         /* Free all the skbuffs in the Rx queue. */
2068         for (i = 0; i < mdp->num_rx_ring; i++) {
2069                 rxdesc = &mdp->rx_ring[i];
2070                 rxdesc->status = 0;
2071                 rxdesc->addr = 0xBADF00D0;
2072                 if (mdp->rx_skbuff[i])
2073                         dev_kfree_skb(mdp->rx_skbuff[i]);
2074                 mdp->rx_skbuff[i] = NULL;
2075         }
2076         for (i = 0; i < mdp->num_tx_ring; i++) {
2077                 if (mdp->tx_skbuff[i])
2078                         dev_kfree_skb(mdp->tx_skbuff[i]);
2079                 mdp->tx_skbuff[i] = NULL;
2080         }
2081
2082         /* device init */
2083         sh_eth_dev_init(ndev, true);
2084 }
2085
2086 /* Packet transmit function */
2087 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2088 {
2089         struct sh_eth_private *mdp = netdev_priv(ndev);
2090         struct sh_eth_txdesc *txdesc;
2091         u32 entry;
2092         unsigned long flags;
2093
2094         spin_lock_irqsave(&mdp->lock, flags);
2095         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2096                 if (!sh_eth_txfree(ndev)) {
2097                         if (netif_msg_tx_queued(mdp))
2098                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
2099                         netif_stop_queue(ndev);
2100                         spin_unlock_irqrestore(&mdp->lock, flags);
2101                         return NETDEV_TX_BUSY;
2102                 }
2103         }
2104         spin_unlock_irqrestore(&mdp->lock, flags);
2105
2106         entry = mdp->cur_tx % mdp->num_tx_ring;
2107         mdp->tx_skbuff[entry] = skb;
2108         txdesc = &mdp->tx_ring[entry];
2109         /* soft swap. */
2110         if (!mdp->cd->hw_swap)
2111                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2112                                  skb->len + 2);
2113         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2114                                       DMA_TO_DEVICE);
2115         if (skb->len < ETHERSMALL)
2116                 txdesc->buffer_length = ETHERSMALL;
2117         else
2118                 txdesc->buffer_length = skb->len;
2119
2120         if (entry >= mdp->num_tx_ring - 1)
2121                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2122         else
2123                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2124
2125         mdp->cur_tx++;
2126
2127         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2128                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2129
2130         return NETDEV_TX_OK;
2131 }
2132
2133 /* device close function */
2134 static int sh_eth_close(struct net_device *ndev)
2135 {
2136         struct sh_eth_private *mdp = netdev_priv(ndev);
2137
2138         netif_stop_queue(ndev);
2139
2140         /* Disable interrupts by clearing the interrupt mask. */
2141         sh_eth_write(ndev, 0x0000, EESIPR);
2142
2143         /* Stop the chip's Tx and Rx processes. */
2144         sh_eth_write(ndev, 0, EDTRR);
2145         sh_eth_write(ndev, 0, EDRRR);
2146
2147         /* PHY Disconnect */
2148         if (mdp->phydev) {
2149                 phy_stop(mdp->phydev);
2150                 phy_disconnect(mdp->phydev);
2151         }
2152
2153         free_irq(ndev->irq, ndev);
2154
2155         napi_disable(&mdp->napi);
2156
2157         /* Free all the skbuffs in the Rx queue. */
2158         sh_eth_ring_free(ndev);
2159
2160         /* free DMA buffer */
2161         sh_eth_free_dma_buffer(mdp);
2162
2163         pm_runtime_put_sync(&mdp->pdev->dev);
2164
2165         return 0;
2166 }
2167
2168 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2169 {
2170         struct sh_eth_private *mdp = netdev_priv(ndev);
2171
2172         if (sh_eth_is_rz_fast_ether(mdp))
2173                 return &ndev->stats;
2174
2175         pm_runtime_get_sync(&mdp->pdev->dev);
2176
2177         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2178         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2179         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2180         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2181         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2182         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2183         if (sh_eth_is_gether(mdp)) {
2184                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2185                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2186                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2187                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2188         } else {
2189                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2190                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2191         }
2192         pm_runtime_put_sync(&mdp->pdev->dev);
2193
2194         return &ndev->stats;
2195 }
2196
2197 /* ioctl to device function */
2198 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2199 {
2200         struct sh_eth_private *mdp = netdev_priv(ndev);
2201         struct phy_device *phydev = mdp->phydev;
2202
2203         if (!netif_running(ndev))
2204                 return -EINVAL;
2205
2206         if (!phydev)
2207                 return -ENODEV;
2208
2209         return phy_mii_ioctl(phydev, rq, cmd);
2210 }
2211
2212 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2213 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2214                                             int entry)
2215 {
2216         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2217 }
2218
2219 static u32 sh_eth_tsu_get_post_mask(int entry)
2220 {
2221         return 0x0f << (28 - ((entry % 8) * 4));
2222 }
2223
2224 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2225 {
2226         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2227 }
2228
2229 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2230                                              int entry)
2231 {
2232         struct sh_eth_private *mdp = netdev_priv(ndev);
2233         u32 tmp;
2234         void *reg_offset;
2235
2236         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2237         tmp = ioread32(reg_offset);
2238         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2239 }
2240
2241 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2242                                               int entry)
2243 {
2244         struct sh_eth_private *mdp = netdev_priv(ndev);
2245         u32 post_mask, ref_mask, tmp;
2246         void *reg_offset;
2247
2248         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2249         post_mask = sh_eth_tsu_get_post_mask(entry);
2250         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2251
2252         tmp = ioread32(reg_offset);
2253         iowrite32(tmp & ~post_mask, reg_offset);
2254
2255         /* If other port enables, the function returns "true" */
2256         return tmp & ref_mask;
2257 }
2258
2259 static int sh_eth_tsu_busy(struct net_device *ndev)
2260 {
2261         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2262         struct sh_eth_private *mdp = netdev_priv(ndev);
2263
2264         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2265                 udelay(10);
2266                 timeout--;
2267                 if (timeout <= 0) {
2268                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2269                         return -ETIMEDOUT;
2270                 }
2271         }
2272
2273         return 0;
2274 }
2275
2276 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2277                                   const u8 *addr)
2278 {
2279         u32 val;
2280
2281         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2282         iowrite32(val, reg);
2283         if (sh_eth_tsu_busy(ndev) < 0)
2284                 return -EBUSY;
2285
2286         val = addr[4] << 8 | addr[5];
2287         iowrite32(val, reg + 4);
2288         if (sh_eth_tsu_busy(ndev) < 0)
2289                 return -EBUSY;
2290
2291         return 0;
2292 }
2293
2294 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2295 {
2296         u32 val;
2297
2298         val = ioread32(reg);
2299         addr[0] = (val >> 24) & 0xff;
2300         addr[1] = (val >> 16) & 0xff;
2301         addr[2] = (val >> 8) & 0xff;
2302         addr[3] = val & 0xff;
2303         val = ioread32(reg + 4);
2304         addr[4] = (val >> 8) & 0xff;
2305         addr[5] = val & 0xff;
2306 }
2307
2308
2309 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2310 {
2311         struct sh_eth_private *mdp = netdev_priv(ndev);
2312         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2313         int i;
2314         u8 c_addr[ETH_ALEN];
2315
2316         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2317                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2318                 if (ether_addr_equal(addr, c_addr))
2319                         return i;
2320         }
2321
2322         return -ENOENT;
2323 }
2324
2325 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2326 {
2327         u8 blank[ETH_ALEN];
2328         int entry;
2329
2330         memset(blank, 0, sizeof(blank));
2331         entry = sh_eth_tsu_find_entry(ndev, blank);
2332         return (entry < 0) ? -ENOMEM : entry;
2333 }
2334
2335 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2336                                               int entry)
2337 {
2338         struct sh_eth_private *mdp = netdev_priv(ndev);
2339         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2340         int ret;
2341         u8 blank[ETH_ALEN];
2342
2343         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2344                          ~(1 << (31 - entry)), TSU_TEN);
2345
2346         memset(blank, 0, sizeof(blank));
2347         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2348         if (ret < 0)
2349                 return ret;
2350         return 0;
2351 }
2352
2353 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2354 {
2355         struct sh_eth_private *mdp = netdev_priv(ndev);
2356         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2357         int i, ret;
2358
2359         if (!mdp->cd->tsu)
2360                 return 0;
2361
2362         i = sh_eth_tsu_find_entry(ndev, addr);
2363         if (i < 0) {
2364                 /* No entry found, create one */
2365                 i = sh_eth_tsu_find_empty(ndev);
2366                 if (i < 0)
2367                         return -ENOMEM;
2368                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2369                 if (ret < 0)
2370                         return ret;
2371
2372                 /* Enable the entry */
2373                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2374                                  (1 << (31 - i)), TSU_TEN);
2375         }
2376
2377         /* Entry found or created, enable POST */
2378         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2379
2380         return 0;
2381 }
2382
2383 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2384 {
2385         struct sh_eth_private *mdp = netdev_priv(ndev);
2386         int i, ret;
2387
2388         if (!mdp->cd->tsu)
2389                 return 0;
2390
2391         i = sh_eth_tsu_find_entry(ndev, addr);
2392         if (i) {
2393                 /* Entry found */
2394                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2395                         goto done;
2396
2397                 /* Disable the entry if both ports was disabled */
2398                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2399                 if (ret < 0)
2400                         return ret;
2401         }
2402 done:
2403         return 0;
2404 }
2405
2406 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2407 {
2408         struct sh_eth_private *mdp = netdev_priv(ndev);
2409         int i, ret;
2410
2411         if (unlikely(!mdp->cd->tsu))
2412                 return 0;
2413
2414         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2415                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2416                         continue;
2417
2418                 /* Disable the entry if both ports was disabled */
2419                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2420                 if (ret < 0)
2421                         return ret;
2422         }
2423
2424         return 0;
2425 }
2426
2427 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2428 {
2429         struct sh_eth_private *mdp = netdev_priv(ndev);
2430         u8 addr[ETH_ALEN];
2431         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2432         int i;
2433
2434         if (unlikely(!mdp->cd->tsu))
2435                 return;
2436
2437         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2438                 sh_eth_tsu_read_entry(reg_offset, addr);
2439                 if (is_multicast_ether_addr(addr))
2440                         sh_eth_tsu_del_entry(ndev, addr);
2441         }
2442 }
2443
2444 /* Multicast reception directions set */
2445 static void sh_eth_set_multicast_list(struct net_device *ndev)
2446 {
2447         struct sh_eth_private *mdp = netdev_priv(ndev);
2448         u32 ecmr_bits;
2449         int mcast_all = 0;
2450         unsigned long flags;
2451
2452         spin_lock_irqsave(&mdp->lock, flags);
2453         /* Initial condition is MCT = 1, PRM = 0.
2454          * Depending on ndev->flags, set PRM or clear MCT
2455          */
2456         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2457
2458         if (!(ndev->flags & IFF_MULTICAST)) {
2459                 sh_eth_tsu_purge_mcast(ndev);
2460                 mcast_all = 1;
2461         }
2462         if (ndev->flags & IFF_ALLMULTI) {
2463                 sh_eth_tsu_purge_mcast(ndev);
2464                 ecmr_bits &= ~ECMR_MCT;
2465                 mcast_all = 1;
2466         }
2467
2468         if (ndev->flags & IFF_PROMISC) {
2469                 sh_eth_tsu_purge_all(ndev);
2470                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2471         } else if (mdp->cd->tsu) {
2472                 struct netdev_hw_addr *ha;
2473                 netdev_for_each_mc_addr(ha, ndev) {
2474                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2475                                 continue;
2476
2477                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2478                                 if (!mcast_all) {
2479                                         sh_eth_tsu_purge_mcast(ndev);
2480                                         ecmr_bits &= ~ECMR_MCT;
2481                                         mcast_all = 1;
2482                                 }
2483                         }
2484                 }
2485         } else {
2486                 /* Normal, unicast/broadcast-only mode. */
2487                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2488         }
2489
2490         /* update the ethernet mode */
2491         sh_eth_write(ndev, ecmr_bits, ECMR);
2492
2493         spin_unlock_irqrestore(&mdp->lock, flags);
2494 }
2495
2496 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2497 {
2498         if (!mdp->port)
2499                 return TSU_VTAG0;
2500         else
2501                 return TSU_VTAG1;
2502 }
2503
2504 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2505                                   __be16 proto, u16 vid)
2506 {
2507         struct sh_eth_private *mdp = netdev_priv(ndev);
2508         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2509
2510         if (unlikely(!mdp->cd->tsu))
2511                 return -EPERM;
2512
2513         /* No filtering if vid = 0 */
2514         if (!vid)
2515                 return 0;
2516
2517         mdp->vlan_num_ids++;
2518
2519         /* The controller has one VLAN tag HW filter. So, if the filter is
2520          * already enabled, the driver disables it and the filte
2521          */
2522         if (mdp->vlan_num_ids > 1) {
2523                 /* disable VLAN filter */
2524                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2525                 return 0;
2526         }
2527
2528         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2529                          vtag_reg_index);
2530
2531         return 0;
2532 }
2533
2534 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2535                                    __be16 proto, u16 vid)
2536 {
2537         struct sh_eth_private *mdp = netdev_priv(ndev);
2538         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2539
2540         if (unlikely(!mdp->cd->tsu))
2541                 return -EPERM;
2542
2543         /* No filtering if vid = 0 */
2544         if (!vid)
2545                 return 0;
2546
2547         mdp->vlan_num_ids--;
2548         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2549
2550         return 0;
2551 }
2552
2553 /* SuperH's TSU register init function */
2554 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2555 {
2556         if (sh_eth_is_rz_fast_ether(mdp)) {
2557                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2558                 return;
2559         }
2560
2561         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2562         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2563         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2564         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2565         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2566         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2567         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2568         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2569         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2570         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2571         if (sh_eth_is_gether(mdp)) {
2572                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2573                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2574         } else {
2575                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2576                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2577         }
2578         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2579         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2580         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2581         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2582         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2583         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2584         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2585 }
2586
2587 /* MDIO bus release function */
2588 static int sh_mdio_release(struct net_device *ndev)
2589 {
2590         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2591
2592         /* unregister mdio bus */
2593         mdiobus_unregister(bus);
2594
2595         /* remove mdio bus info from net_device */
2596         dev_set_drvdata(&ndev->dev, NULL);
2597
2598         /* free bitbang info */
2599         free_mdio_bitbang(bus);
2600
2601         return 0;
2602 }
2603
2604 /* MDIO bus init function */
2605 static int sh_mdio_init(struct net_device *ndev, int id,
2606                         struct sh_eth_plat_data *pd)
2607 {
2608         int ret, i;
2609         struct bb_info *bitbang;
2610         struct sh_eth_private *mdp = netdev_priv(ndev);
2611
2612         /* create bit control struct for PHY */
2613         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2614                                GFP_KERNEL);
2615         if (!bitbang) {
2616                 ret = -ENOMEM;
2617                 goto out;
2618         }
2619
2620         /* bitbang init */
2621         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2622         bitbang->set_gate = pd->set_mdio_gate;
2623         bitbang->mdi_msk = PIR_MDI;
2624         bitbang->mdo_msk = PIR_MDO;
2625         bitbang->mmd_msk = PIR_MMD;
2626         bitbang->mdc_msk = PIR_MDC;
2627         bitbang->ctrl.ops = &bb_ops;
2628
2629         /* MII controller setting */
2630         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2631         if (!mdp->mii_bus) {
2632                 ret = -ENOMEM;
2633                 goto out;
2634         }
2635
2636         /* Hook up MII support for ethtool */
2637         mdp->mii_bus->name = "sh_mii";
2638         mdp->mii_bus->parent = &ndev->dev;
2639         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2640                  mdp->pdev->name, id);
2641
2642         /* PHY IRQ */
2643         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2644                                          sizeof(int) * PHY_MAX_ADDR,
2645                                          GFP_KERNEL);
2646         if (!mdp->mii_bus->irq) {
2647                 ret = -ENOMEM;
2648                 goto out_free_bus;
2649         }
2650
2651         for (i = 0; i < PHY_MAX_ADDR; i++)
2652                 mdp->mii_bus->irq[i] = PHY_POLL;
2653         if (pd->phy_irq > 0)
2654                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2655
2656         /* register mdio bus */
2657         ret = mdiobus_register(mdp->mii_bus);
2658         if (ret)
2659                 goto out_free_bus;
2660
2661         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2662
2663         return 0;
2664
2665 out_free_bus:
2666         free_mdio_bitbang(mdp->mii_bus);
2667
2668 out:
2669         return ret;
2670 }
2671
2672 static const u16 *sh_eth_get_register_offset(int register_type)
2673 {
2674         const u16 *reg_offset = NULL;
2675
2676         switch (register_type) {
2677         case SH_ETH_REG_GIGABIT:
2678                 reg_offset = sh_eth_offset_gigabit;
2679                 break;
2680         case SH_ETH_REG_FAST_RZ:
2681                 reg_offset = sh_eth_offset_fast_rz;
2682                 break;
2683         case SH_ETH_REG_FAST_RCAR:
2684                 reg_offset = sh_eth_offset_fast_rcar;
2685                 break;
2686         case SH_ETH_REG_FAST_SH4:
2687                 reg_offset = sh_eth_offset_fast_sh4;
2688                 break;
2689         case SH_ETH_REG_FAST_SH3_SH2:
2690                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2691                 break;
2692         default:
2693                 pr_err("Unknown register type (%d)\n", register_type);
2694                 break;
2695         }
2696
2697         return reg_offset;
2698 }
2699
2700 static const struct net_device_ops sh_eth_netdev_ops = {
2701         .ndo_open               = sh_eth_open,
2702         .ndo_stop               = sh_eth_close,
2703         .ndo_start_xmit         = sh_eth_start_xmit,
2704         .ndo_get_stats          = sh_eth_get_stats,
2705         .ndo_tx_timeout         = sh_eth_tx_timeout,
2706         .ndo_do_ioctl           = sh_eth_do_ioctl,
2707         .ndo_validate_addr      = eth_validate_addr,
2708         .ndo_set_mac_address    = eth_mac_addr,
2709         .ndo_change_mtu         = eth_change_mtu,
2710 };
2711
2712 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2713         .ndo_open               = sh_eth_open,
2714         .ndo_stop               = sh_eth_close,
2715         .ndo_start_xmit         = sh_eth_start_xmit,
2716         .ndo_get_stats          = sh_eth_get_stats,
2717         .ndo_set_rx_mode        = sh_eth_set_multicast_list,
2718         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2719         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2720         .ndo_tx_timeout         = sh_eth_tx_timeout,
2721         .ndo_do_ioctl           = sh_eth_do_ioctl,
2722         .ndo_validate_addr      = eth_validate_addr,
2723         .ndo_set_mac_address    = eth_mac_addr,
2724         .ndo_change_mtu         = eth_change_mtu,
2725 };
2726
2727 static int sh_eth_drv_probe(struct platform_device *pdev)
2728 {
2729         int ret, devno = 0;
2730         struct resource *res;
2731         struct net_device *ndev = NULL;
2732         struct sh_eth_private *mdp = NULL;
2733         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2734         const struct platform_device_id *id = platform_get_device_id(pdev);
2735
2736         /* get base addr */
2737         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2738         if (unlikely(res == NULL)) {
2739                 dev_err(&pdev->dev, "invalid resource\n");
2740                 ret = -EINVAL;
2741                 goto out;
2742         }
2743
2744         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2745         if (!ndev) {
2746                 ret = -ENOMEM;
2747                 goto out;
2748         }
2749
2750         /* The sh Ether-specific entries in the device structure. */
2751         ndev->base_addr = res->start;
2752         devno = pdev->id;
2753         if (devno < 0)
2754                 devno = 0;
2755
2756         ndev->dma = -1;
2757         ret = platform_get_irq(pdev, 0);
2758         if (ret < 0) {
2759                 ret = -ENODEV;
2760                 goto out_release;
2761         }
2762         ndev->irq = ret;
2763
2764         SET_NETDEV_DEV(ndev, &pdev->dev);
2765
2766         mdp = netdev_priv(ndev);
2767         mdp->num_tx_ring = TX_RING_SIZE;
2768         mdp->num_rx_ring = RX_RING_SIZE;
2769         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2770         if (IS_ERR(mdp->addr)) {
2771                 ret = PTR_ERR(mdp->addr);
2772                 goto out_release;
2773         }
2774
2775         spin_lock_init(&mdp->lock);
2776         mdp->pdev = pdev;
2777         pm_runtime_enable(&pdev->dev);
2778         pm_runtime_resume(&pdev->dev);
2779
2780         if (!pd) {
2781                 dev_err(&pdev->dev, "no platform data\n");
2782                 ret = -EINVAL;
2783                 goto out_release;
2784         }
2785
2786         /* get PHY ID */
2787         mdp->phy_id = pd->phy;
2788         mdp->phy_interface = pd->phy_interface;
2789         /* EDMAC endian */
2790         mdp->edmac_endian = pd->edmac_endian;
2791         mdp->no_ether_link = pd->no_ether_link;
2792         mdp->ether_link_active_low = pd->ether_link_active_low;
2793
2794         /* set cpu data */
2795         mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2796         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2797         sh_eth_set_default_cpu_data(mdp->cd);
2798
2799         /* set function */
2800         if (mdp->cd->tsu)
2801                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2802         else
2803                 ndev->netdev_ops = &sh_eth_netdev_ops;
2804         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2805         ndev->watchdog_timeo = TX_TIMEOUT;
2806
2807         /* debug message level */
2808         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2809
2810         /* read and set MAC address */
2811         read_mac_address(ndev, pd->mac_addr);
2812         if (!is_valid_ether_addr(ndev->dev_addr)) {
2813                 dev_warn(&pdev->dev,
2814                          "no valid MAC address supplied, using a random one.\n");
2815                 eth_hw_addr_random(ndev);
2816         }
2817
2818         /* ioremap the TSU registers */
2819         if (mdp->cd->tsu) {
2820                 struct resource *rtsu;
2821                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2822                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2823                 if (IS_ERR(mdp->tsu_addr)) {
2824                         ret = PTR_ERR(mdp->tsu_addr);
2825                         goto out_release;
2826                 }
2827                 mdp->port = devno % 2;
2828                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2829         }
2830
2831         /* initialize first or needed device */
2832         if (!devno || pd->needs_init) {
2833                 if (mdp->cd->chip_reset)
2834                         mdp->cd->chip_reset(ndev);
2835
2836                 if (mdp->cd->tsu) {
2837                         /* TSU init (Init only)*/
2838                         sh_eth_tsu_init(mdp);
2839                 }
2840         }
2841
2842         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2843
2844         /* network device register */
2845         ret = register_netdev(ndev);
2846         if (ret)
2847                 goto out_napi_del;
2848
2849         /* mdio bus init */
2850         ret = sh_mdio_init(ndev, pdev->id, pd);
2851         if (ret)
2852                 goto out_unregister;
2853
2854         /* print device information */
2855         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2856                 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2857
2858         platform_set_drvdata(pdev, ndev);
2859
2860         return ret;
2861
2862 out_unregister:
2863         unregister_netdev(ndev);
2864
2865 out_napi_del:
2866         netif_napi_del(&mdp->napi);
2867
2868 out_release:
2869         /* net_dev free */
2870         if (ndev)
2871                 free_netdev(ndev);
2872
2873 out:
2874         return ret;
2875 }
2876
2877 static int sh_eth_drv_remove(struct platform_device *pdev)
2878 {
2879         struct net_device *ndev = platform_get_drvdata(pdev);
2880         struct sh_eth_private *mdp = netdev_priv(ndev);
2881
2882         sh_mdio_release(ndev);
2883         unregister_netdev(ndev);
2884         netif_napi_del(&mdp->napi);
2885         pm_runtime_disable(&pdev->dev);
2886         free_netdev(ndev);
2887
2888         return 0;
2889 }
2890
2891 #ifdef CONFIG_PM
2892 static int sh_eth_runtime_nop(struct device *dev)
2893 {
2894         /* Runtime PM callback shared between ->runtime_suspend()
2895          * and ->runtime_resume(). Simply returns success.
2896          *
2897          * This driver re-initializes all registers after
2898          * pm_runtime_get_sync() anyway so there is no need
2899          * to save and restore registers here.
2900          */
2901         return 0;
2902 }
2903
2904 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2905         .runtime_suspend = sh_eth_runtime_nop,
2906         .runtime_resume = sh_eth_runtime_nop,
2907 };
2908 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2909 #else
2910 #define SH_ETH_PM_OPS NULL
2911 #endif
2912
2913 static struct platform_device_id sh_eth_id_table[] = {
2914         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2915         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2916         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2917         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2918         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2919         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2920         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2921         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2922         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2923         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2924         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2925         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2926         { }
2927 };
2928 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2929
2930 static struct platform_driver sh_eth_driver = {
2931         .probe = sh_eth_drv_probe,
2932         .remove = sh_eth_drv_remove,
2933         .id_table = sh_eth_id_table,
2934         .driver = {
2935                    .name = CARDNAME,
2936                    .pm = SH_ETH_PM_OPS,
2937         },
2938 };
2939
2940 module_platform_driver(sh_eth_driver);
2941
2942 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2943 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2944 MODULE_LICENSE("GPL v2");