drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014 Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_FWSLC]     = 0x0038,
 205         [TSU_VTAG0]     = 0x0058,
 206         [TSU_ADSBSY]    = 0x0060,
 207         [TSU_TEN]       = 0x0064,
 208         [TSU_POST1]     = 0x0070,
 209         [TSU_POST2]     = 0x0074,
 210         [TSU_POST3]     = 0x0078,
 211         [TSU_POST4]     = 0x007c,
 212         [TSU_ADRH0]     = 0x0100,
 213
 214         [TXNLCR0]       = 0x0080,
 215         [TXALCR0]       = 0x0084,
 216         [RXNLCR0]       = 0x0088,
 217         [RXALCR0]       = 0x008C,
 218 };
 219
 220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 221         SH_ETH_OFFSET_DEFAULTS,
 222
 223         [ECMR]          = 0x0300,
 224         [RFLR]          = 0x0308,
 225         [ECSR]          = 0x0310,
 226         [ECSIPR]        = 0x0318,
 227         [PIR]           = 0x0320,
 228         [PSR]           = 0x0328,
 229         [RDMLR]         = 0x0340,
 230         [IPGR]          = 0x0350,
 231         [APR]           = 0x0354,
 232         [MPR]           = 0x0358,
 233         [RFCF]          = 0x0360,
 234         [TPAUSER]       = 0x0364,
 235         [TPAUSECR]      = 0x0368,
 236         [MAHR]          = 0x03c0,
 237         [MALR]          = 0x03c8,
 238         [TROCR]         = 0x03d0,
 239         [CDCR]          = 0x03d4,
 240         [LCCR]          = 0x03d8,
 241         [CNDCR]         = 0x03dc,
 242         [CEFCR]         = 0x03e4,
 243         [FRECR]         = 0x03e8,
 244         [TSFRCR]        = 0x03ec,
 245         [TLFRCR]        = 0x03f0,
 246         [RFCR]          = 0x03f4,
 247         [MAFCR]         = 0x03f8,
 248
 249         [EDMR]          = 0x0200,
 250         [EDTRR]         = 0x0208,
 251         [EDRRR]         = 0x0210,
 252         [TDLAR]         = 0x0218,
 253         [RDLAR]         = 0x0220,
 254         [EESR]          = 0x0228,
 255         [EESIPR]        = 0x0230,
 256         [TRSCER]        = 0x0238,
 257         [RMFCR]         = 0x0240,
 258         [TFTR]          = 0x0248,
 259         [FDR]           = 0x0250,
 260         [RMCR]          = 0x0258,
 261         [TFUCR]         = 0x0264,
 262         [RFOCR]         = 0x0268,
 263         [RMIIMODE]      = 0x026c,
 264         [FCFTR]         = 0x0270,
 265         [TRIMD]         = 0x027c,
 266 };
 267
 268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 269         SH_ETH_OFFSET_DEFAULTS,
 270
 271         [ECMR]          = 0x0100,
 272         [RFLR]          = 0x0108,
 273         [ECSR]          = 0x0110,
 274         [ECSIPR]        = 0x0118,
 275         [PIR]           = 0x0120,
 276         [PSR]           = 0x0128,
 277         [RDMLR]         = 0x0140,
 278         [IPGR]          = 0x0150,
 279         [APR]           = 0x0154,
 280         [MPR]           = 0x0158,
 281         [TPAUSER]       = 0x0164,
 282         [RFCF]          = 0x0160,
 283         [TPAUSECR]      = 0x0168,
 284         [BCFRR]         = 0x016c,
 285         [MAHR]          = 0x01c0,
 286         [MALR]          = 0x01c8,
 287         [TROCR]         = 0x01d0,
 288         [CDCR]          = 0x01d4,
 289         [LCCR]          = 0x01d8,
 290         [CNDCR]         = 0x01dc,
 291         [CEFCR]         = 0x01e4,
 292         [FRECR]         = 0x01e8,
 293         [TSFRCR]        = 0x01ec,
 294         [TLFRCR]        = 0x01f0,
 295         [RFCR]          = 0x01f4,
 296         [MAFCR]         = 0x01f8,
 297         [RTRATE]        = 0x01fc,
 298
 299         [EDMR]          = 0x0000,
 300         [EDTRR]         = 0x0008,
 301         [EDRRR]         = 0x0010,
 302         [TDLAR]         = 0x0018,
 303         [RDLAR]         = 0x0020,
 304         [EESR]          = 0x0028,
 305         [EESIPR]        = 0x0030,
 306         [TRSCER]        = 0x0038,
 307         [RMFCR]         = 0x0040,
 308         [TFTR]          = 0x0048,
 309         [FDR]           = 0x0050,
 310         [RMCR]          = 0x0058,
 311         [TFUCR]         = 0x0064,
 312         [RFOCR]         = 0x0068,
 313         [FCFTR]         = 0x0070,
 314         [RPADIR]        = 0x0078,
 315         [TRIMD]         = 0x007c,
 316         [RBWAR]         = 0x00c8,
 317         [RDFAR]         = 0x00cc,
 318         [TBRAR]         = 0x00d4,
 319         [TDFAR]         = 0x00d8,
 320 };
 321
 322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 323         SH_ETH_OFFSET_DEFAULTS,
 324
 325         [EDMR]          = 0x0000,
 326         [EDTRR]         = 0x0004,
 327         [EDRRR]         = 0x0008,
 328         [TDLAR]         = 0x000c,
 329         [RDLAR]         = 0x0010,
 330         [EESR]          = 0x0014,
 331         [EESIPR]        = 0x0018,
 332         [TRSCER]        = 0x001c,
 333         [RMFCR]         = 0x0020,
 334         [TFTR]          = 0x0024,
 335         [FDR]           = 0x0028,
 336         [RMCR]          = 0x002c,
 337         [EDOCR]         = 0x0030,
 338         [FCFTR]         = 0x0034,
 339         [RPADIR]        = 0x0038,
 340         [TRIMD]         = 0x003c,
 341         [RBWAR]         = 0x0040,
 342         [RDFAR]         = 0x0044,
 343         [TBRAR]         = 0x004c,
 344         [TDFAR]         = 0x0050,
 345
 346         [ECMR]          = 0x0160,
 347         [ECSR]          = 0x0164,
 348         [ECSIPR]        = 0x0168,
 349         [PIR]           = 0x016c,
 350         [MAHR]          = 0x0170,
 351         [MALR]          = 0x0174,
 352         [RFLR]          = 0x0178,
 353         [PSR]           = 0x017c,
 354         [TROCR]         = 0x0180,
 355         [CDCR]          = 0x0184,
 356         [LCCR]          = 0x0188,
 357         [CNDCR]         = 0x018c,
 358         [CEFCR]         = 0x0194,
 359         [FRECR]         = 0x0198,
 360         [TSFRCR]        = 0x019c,
 361         [TLFRCR]        = 0x01a0,
 362         [RFCR]          = 0x01a4,
 363         [MAFCR]         = 0x01a8,
 364         [IPGR]          = 0x01b4,
 365         [APR]           = 0x01b8,
 366         [MPR]           = 0x01bc,
 367         [TPAUSER]       = 0x01c4,
 368         [BCFR]          = 0x01cc,
 369
 370         [ARSTR]         = 0x0000,
 371         [TSU_CTRST]     = 0x0004,
 372         [TSU_FWEN0]     = 0x0010,
 373         [TSU_FWEN1]     = 0x0014,
 374         [TSU_FCM]       = 0x0018,
 375         [TSU_BSYSL0]    = 0x0020,
 376         [TSU_BSYSL1]    = 0x0024,
 377         [TSU_PRISL0]    = 0x0028,
 378         [TSU_PRISL1]    = 0x002c,
 379         [TSU_FWSL0]     = 0x0030,
 380         [TSU_FWSL1]     = 0x0034,
 381         [TSU_FWSLC]     = 0x0038,
 382         [TSU_QTAGM0]    = 0x0040,
 383         [TSU_QTAGM1]    = 0x0044,
 384         [TSU_ADQT0]     = 0x0048,
 385         [TSU_ADQT1]     = 0x004c,
 386         [TSU_FWSR]      = 0x0050,
 387         [TSU_FWINMK]    = 0x0054,
 388         [TSU_ADSBSY]    = 0x0060,
 389         [TSU_TEN]       = 0x0064,
 390         [TSU_POST1]     = 0x0070,
 391         [TSU_POST2]     = 0x0074,
 392         [TSU_POST3]     = 0x0078,
 393         [TSU_POST4]     = 0x007c,
 394
 395         [TXNLCR0]       = 0x0080,
 396         [TXALCR0]       = 0x0084,
 397         [RXNLCR0]       = 0x0088,
 398         [RXALCR0]       = 0x008c,
 399         [FWNLCR0]       = 0x0090,
 400         [FWALCR0]       = 0x0094,
 401         [TXNLCR1]       = 0x00a0,
 402         [TXALCR1]       = 0x00a0,
 403         [RXNLCR1]       = 0x00a8,
 404         [RXALCR1]       = 0x00ac,
 405         [FWNLCR1]       = 0x00b0,
 406         [FWALCR1]       = 0x00b4,
 407
 408         [TSU_ADRH0]     = 0x0100,
 409 };
 410
 411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 413
 414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 415 {
 416         struct sh_eth_private *mdp = netdev_priv(ndev);
 417         u16 offset = mdp->reg_offset[enum_index];
 418
 419         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 420                 return;
 421
 422         iowrite32(data, mdp->addr + offset);
 423 }
 424
 425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 426 {
 427         struct sh_eth_private *mdp = netdev_priv(ndev);
 428         u16 offset = mdp->reg_offset[enum_index];
 429
 430         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 431                 return ~0U;
 432
 433         return ioread32(mdp->addr + offset);
 434 }
 435
 436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 437                           u32 set)
 438 {
 439         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 440                      enum_index);
 441 }
 442
 443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 444 {
 445         return mdp->reg_offset == sh_eth_offset_gigabit;
 446 }
 447
 448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 449 {
 450         return mdp->reg_offset == sh_eth_offset_fast_rz;
 451 }
 452
 453 static void sh_eth_select_mii(struct net_device *ndev)
 454 {
 455         struct sh_eth_private *mdp = netdev_priv(ndev);
 456         u32 value;
 457
 458         switch (mdp->phy_interface) {
 459         case PHY_INTERFACE_MODE_GMII:
 460                 value = 0x2;
 461                 break;
 462         case PHY_INTERFACE_MODE_MII:
 463                 value = 0x1;
 464                 break;
 465         case PHY_INTERFACE_MODE_RMII:
 466                 value = 0x0;
 467                 break;
 468         default:
 469                 netdev_warn(ndev,
 470                             "PHY interface mode was not setup. Set to MII.\n");
 471                 value = 0x1;
 472                 break;
 473         }
 474
 475         sh_eth_write(ndev, value, RMII_MII);
 476 }
 477
 478 static void sh_eth_set_duplex(struct net_device *ndev)
 479 {
 480         struct sh_eth_private *mdp = netdev_priv(ndev);
 481
 482         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 483 }
 484
 485 static void sh_eth_chip_reset(struct net_device *ndev)
 486 {
 487         struct sh_eth_private *mdp = netdev_priv(ndev);
 488
 489         /* reset device */
 490         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 491         mdelay(1);
 492 }
 493
 494 static void sh_eth_set_rate_gether(struct net_device *ndev)
 495 {
 496         struct sh_eth_private *mdp = netdev_priv(ndev);
 497
 498         switch (mdp->speed) {
 499         case 10: /* 10BASE */
 500                 sh_eth_write(ndev, GECMR_10, GECMR);
 501                 break;
 502         case 100:/* 100BASE */
 503                 sh_eth_write(ndev, GECMR_100, GECMR);
 504                 break;
 505         case 1000: /* 1000BASE */
 506                 sh_eth_write(ndev, GECMR_1000, GECMR);
 507                 break;
 508         }
 509 }
 510
 511 #ifdef CONFIG_OF
 512 /* R7S72100 */
 513 static struct sh_eth_cpu_data r7s72100_data = {
 514         .chip_reset     = sh_eth_chip_reset,
 515         .set_duplex     = sh_eth_set_duplex,
 516
 517         .register_type  = SH_ETH_REG_FAST_RZ,
 518
 519         .ecsr_value     = ECSR_ICD,
 520         .ecsipr_value   = ECSIPR_ICDIP,
 521         .eesipr_value   = 0xe77f009f,
 522
 523         .tx_check       = EESR_TC1 | EESR_FTC,
 524         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 525                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 526                           EESR_TDE,
 527         .fdr_value      = 0x0000070f,
 528
 529         .no_psr         = 1,
 530         .apr            = 1,
 531         .mpr            = 1,
 532         .tpauser        = 1,
 533         .hw_swap        = 1,
 534         .rpadir         = 1,
 535         .rpadir_value   = 2 << 16,
 536         .no_trimd       = 1,
 537         .no_ade         = 1,
 538         .hw_checksum    = 1,
 539         .tsu            = 1,
 540 };
 541
 542 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 543 {
 544         sh_eth_chip_reset(ndev);
 545
 546         sh_eth_select_mii(ndev);
 547 }
 548
 549 /* R8A7740 */
 550 static struct sh_eth_cpu_data r8a7740_data = {
 551         .chip_reset     = sh_eth_chip_reset_r8a7740,
 552         .set_duplex     = sh_eth_set_duplex,
 553         .set_rate       = sh_eth_set_rate_gether,
 554
 555         .register_type  = SH_ETH_REG_GIGABIT,
 556
 557         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 558         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 559         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 560
 561         .tx_check       = EESR_TC1 | EESR_FTC,
 562         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 563                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 564                           EESR_TDE,
 565         .fdr_value      = 0x0000070f,
 566
 567         .apr            = 1,
 568         .mpr            = 1,
 569         .tpauser        = 1,
 570         .bculr          = 1,
 571         .hw_swap        = 1,
 572         .rpadir         = 1,
 573         .rpadir_value   = 2 << 16,
 574         .no_trimd       = 1,
 575         .no_ade         = 1,
 576         .hw_checksum    = 1,
 577         .tsu            = 1,
 578         .select_mii     = 1,
 579         .magic          = 1,
 580 };
 581
 582 /* There is CPU dependent code */
 583 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 584 {
 585         struct sh_eth_private *mdp = netdev_priv(ndev);
 586
 587         switch (mdp->speed) {
 588         case 10: /* 10BASE */
 589                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 590                 break;
 591         case 100:/* 100BASE */
 592                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 593                 break;
 594         }
 595 }
 596
 597 /* R8A7778/9 */
 598 static struct sh_eth_cpu_data r8a777x_data = {
 599         .set_duplex     = sh_eth_set_duplex,
 600         .set_rate       = sh_eth_set_rate_r8a777x,
 601
 602         .register_type  = SH_ETH_REG_FAST_RCAR,
 603
 604         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 605         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 606         .eesipr_value   = 0x01ff009f,
 607
 608         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 609         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 610                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 611         .fdr_value      = 0x00000f0f,
 612
 613         .apr            = 1,
 614         .mpr            = 1,
 615         .tpauser        = 1,
 616         .hw_swap        = 1,
 617 };
 618
 619 /* R8A7790/1 */
 620 static struct sh_eth_cpu_data r8a779x_data = {
 621         .set_duplex     = sh_eth_set_duplex,
 622         .set_rate       = sh_eth_set_rate_r8a777x,
 623
 624         .register_type  = SH_ETH_REG_FAST_RCAR,
 625
 626         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 627         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 628                           ECSIPR_MPDIP,
 629         .eesipr_value   = 0x01ff009f,
 630
 631         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 632         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 633                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 634         .fdr_value      = 0x00000f0f,
 635
 636         .trscer_err_mask = DESC_I_RINT8,
 637
 638         .apr            = 1,
 639         .mpr            = 1,
 640         .tpauser        = 1,
 641         .hw_swap        = 1,
 642         .rmiimode       = 1,
 643         .magic          = 1,
 644 };
 645 #endif /* CONFIG_OF */
 646
 647 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 648 {
 649         struct sh_eth_private *mdp = netdev_priv(ndev);
 650
 651         switch (mdp->speed) {
 652         case 10: /* 10BASE */
 653                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 654                 break;
 655         case 100:/* 100BASE */
 656                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 657                 break;
 658         }
 659 }
 660
 661 /* SH7724 */
 662 static struct sh_eth_cpu_data sh7724_data = {
 663         .set_duplex     = sh_eth_set_duplex,
 664         .set_rate       = sh_eth_set_rate_sh7724,
 665
 666         .register_type  = SH_ETH_REG_FAST_SH4,
 667
 668         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 669         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 670         .eesipr_value   = 0x01ff009f,
 671
 672         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 673         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 674                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 675
 676         .apr            = 1,
 677         .mpr            = 1,
 678         .tpauser        = 1,
 679         .hw_swap        = 1,
 680         .rpadir         = 1,
 681         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 682 };
 683
 684 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 685 {
 686         struct sh_eth_private *mdp = netdev_priv(ndev);
 687
 688         switch (mdp->speed) {
 689         case 10: /* 10BASE */
 690                 sh_eth_write(ndev, 0, RTRATE);
 691                 break;
 692         case 100:/* 100BASE */
 693                 sh_eth_write(ndev, 1, RTRATE);
 694                 break;
 695         }
 696 }
 697
 698 /* SH7757 */
 699 static struct sh_eth_cpu_data sh7757_data = {
 700         .set_duplex     = sh_eth_set_duplex,
 701         .set_rate       = sh_eth_set_rate_sh7757,
 702
 703         .register_type  = SH_ETH_REG_FAST_SH4,
 704
 705         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 706
 707         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 708         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 709                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 710
 711         .irq_flags      = IRQF_SHARED,
 712         .apr            = 1,
 713         .mpr            = 1,
 714         .tpauser        = 1,
 715         .hw_swap        = 1,
 716         .no_ade         = 1,
 717         .rpadir         = 1,
 718         .rpadir_value   = 2 << 16,
 719         .rtrate         = 1,
 720 };
 721
 722 #define SH_GIGA_ETH_BASE        0xfee00000UL
 723 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 724 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 725 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 726 {
 727         u32 mahr[2], malr[2];
 728         int i;
 729
 730         /* save MAHR and MALR */
 731         for (i = 0; i < 2; i++) {
 732                 malr[i] = ioread32((void *)GIGA_MALR(i));
 733                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 734         }
 735
 736         sh_eth_chip_reset(ndev);
 737
 738         /* restore MAHR and MALR */
 739         for (i = 0; i < 2; i++) {
 740                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 741                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 742         }
 743 }
 744
 745 static void sh_eth_set_rate_giga(struct net_device *ndev)
 746 {
 747         struct sh_eth_private *mdp = netdev_priv(ndev);
 748
 749         switch (mdp->speed) {
 750         case 10: /* 10BASE */
 751                 sh_eth_write(ndev, 0x00000000, GECMR);
 752                 break;
 753         case 100:/* 100BASE */
 754                 sh_eth_write(ndev, 0x00000010, GECMR);
 755                 break;
 756         case 1000: /* 1000BASE */
 757                 sh_eth_write(ndev, 0x00000020, GECMR);
 758                 break;
 759         }
 760 }
 761
 762 /* SH7757(GETHERC) */
 763 static struct sh_eth_cpu_data sh7757_data_giga = {
 764         .chip_reset     = sh_eth_chip_reset_giga,
 765         .set_duplex     = sh_eth_set_duplex,
 766         .set_rate       = sh_eth_set_rate_giga,
 767
 768         .register_type  = SH_ETH_REG_GIGABIT,
 769
 770         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 771         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 772         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 773
 774         .tx_check       = EESR_TC1 | EESR_FTC,
 775         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 776                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 777                           EESR_TDE,
 778         .fdr_value      = 0x0000072f,
 779
 780         .irq_flags      = IRQF_SHARED,
 781         .apr            = 1,
 782         .mpr            = 1,
 783         .tpauser        = 1,
 784         .bculr          = 1,
 785         .hw_swap        = 1,
 786         .rpadir         = 1,
 787         .rpadir_value   = 2 << 16,
 788         .no_trimd       = 1,
 789         .no_ade         = 1,
 790         .tsu            = 1,
 791 };
 792
 793 /* SH7734 */
 794 static struct sh_eth_cpu_data sh7734_data = {
 795         .chip_reset     = sh_eth_chip_reset,
 796         .set_duplex     = sh_eth_set_duplex,
 797         .set_rate       = sh_eth_set_rate_gether,
 798
 799         .register_type  = SH_ETH_REG_GIGABIT,
 800
 801         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 802         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 803         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
 804
 805         .tx_check       = EESR_TC1 | EESR_FTC,
 806         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 807                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 808                           EESR_TDE,
 809
 810         .apr            = 1,
 811         .mpr            = 1,
 812         .tpauser        = 1,
 813         .bculr          = 1,
 814         .hw_swap        = 1,
 815         .no_trimd       = 1,
 816         .no_ade         = 1,
 817         .tsu            = 1,
 818         .hw_checksum    = 1,
 819         .select_mii     = 1,
 820         .magic          = 1,
 821 };
 822
 823 /* SH7763 */
 824 static struct sh_eth_cpu_data sh7763_data = {
 825         .chip_reset     = sh_eth_chip_reset,
 826         .set_duplex     = sh_eth_set_duplex,
 827         .set_rate       = sh_eth_set_rate_gether,
 828
 829         .register_type  = SH_ETH_REG_GIGABIT,
 830
 831         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 832         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 833         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
 834
 835         .tx_check       = EESR_TC1 | EESR_FTC,
 836         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 837                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 838
 839         .apr            = 1,
 840         .mpr            = 1,
 841         .tpauser        = 1,
 842         .bculr          = 1,
 843         .hw_swap        = 1,
 844         .no_trimd       = 1,
 845         .no_ade         = 1,
 846         .tsu            = 1,
 847         .irq_flags      = IRQF_SHARED,
 848 };
 849
 850 static struct sh_eth_cpu_data sh7619_data = {
 851         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 852
 853         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 854
 855         .apr            = 1,
 856         .mpr            = 1,
 857         .tpauser        = 1,
 858         .hw_swap        = 1,
 859 };
 860
 861 static struct sh_eth_cpu_data sh771x_data = {
 862         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 863
 864         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 865         .tsu            = 1,
 866 };
 867
 868 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 869 {
 870         if (!cd->ecsr_value)
 871                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 872
 873         if (!cd->ecsipr_value)
 874                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 875
 876         if (!cd->fcftr_value)
 877                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 878                                   DEFAULT_FIFO_F_D_RFD;
 879
 880         if (!cd->fdr_value)
 881                 cd->fdr_value = DEFAULT_FDR_INIT;
 882
 883         if (!cd->tx_check)
 884                 cd->tx_check = DEFAULT_TX_CHECK;
 885
 886         if (!cd->eesr_err_check)
 887                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 888
 889         if (!cd->trscer_err_mask)
 890                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 891 }
 892
 893 static int sh_eth_check_reset(struct net_device *ndev)
 894 {
 895         int ret = 0;
 896         int cnt = 100;
 897
 898         while (cnt > 0) {
 899                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 900                         break;
 901                 mdelay(1);
 902                 cnt--;
 903         }
 904         if (cnt <= 0) {
 905                 netdev_err(ndev, "Device reset failed\n");
 906                 ret = -ETIMEDOUT;
 907         }
 908         return ret;
 909 }
 910
 911 static int sh_eth_reset(struct net_device *ndev)
 912 {
 913         struct sh_eth_private *mdp = netdev_priv(ndev);
 914         int ret = 0;
 915
 916         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 917                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 918                 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 919
 920                 ret = sh_eth_check_reset(ndev);
 921                 if (ret)
 922                         return ret;
 923
 924                 /* Table Init */
 925                 sh_eth_write(ndev, 0x0, TDLAR);
 926                 sh_eth_write(ndev, 0x0, TDFAR);
 927                 sh_eth_write(ndev, 0x0, TDFXR);
 928                 sh_eth_write(ndev, 0x0, TDFFR);
 929                 sh_eth_write(ndev, 0x0, RDLAR);
 930                 sh_eth_write(ndev, 0x0, RDFAR);
 931                 sh_eth_write(ndev, 0x0, RDFXR);
 932                 sh_eth_write(ndev, 0x0, RDFFR);
 933
 934                 /* Reset HW CRC register */
 935                 if (mdp->cd->hw_checksum)
 936                         sh_eth_write(ndev, 0x0, CSMR);
 937
 938                 /* Select MII mode */
 939                 if (mdp->cd->select_mii)
 940                         sh_eth_select_mii(ndev);
 941         } else {
 942                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 943                 mdelay(3);
 944                 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 945         }
 946
 947         return ret;
 948 }
 949
 950 static void sh_eth_set_receive_align(struct sk_buff *skb)
 951 {
 952         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 953
 954         if (reserve)
 955                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 956 }
 957
 958 /* Program the hardware MAC address from dev->dev_addr. */
 959 static void update_mac_address(struct net_device *ndev)
 960 {
 961         sh_eth_write(ndev,
 962                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 963                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 964         sh_eth_write(ndev,
 965                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 966 }
 967
 968 /* Get MAC address from SuperH MAC address register
 969  *
 970  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 971  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 972  * When you want use this device, you must set MAC address in bootloader.
 973  *
 974  */
 975 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 976 {
 977         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 978                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 979         } else {
 980                 u32 mahr = sh_eth_read(ndev, MAHR);
 981                 u32 malr = sh_eth_read(ndev, MALR);
 982
 983                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
 984                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
 985                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
 986                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
 987                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
 988                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
 989         }
 990 }
 991
 992 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 993 {
 994         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 995                 return EDTRR_TRNS_GETHER;
 996         else
 997                 return EDTRR_TRNS_ETHER;
 998 }
 999
1000 struct bb_info {
1001         void (*set_gate)(void *addr);
1002         struct mdiobb_ctrl ctrl;
1003         void *addr;
1004 };
1005
1006 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1007 {
1008         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1009         u32 pir;
1010
1011         if (bitbang->set_gate)
1012                 bitbang->set_gate(bitbang->addr);
1013
1014         pir = ioread32(bitbang->addr);
1015         if (set)
1016                 pir |=  mask;
1017         else
1018                 pir &= ~mask;
1019         iowrite32(pir, bitbang->addr);
1020 }
1021
1022 /* Data I/O pin control */
1023 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1024 {
1025         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1026 }
1027
1028 /* Set bit data*/
1029 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1030 {
1031         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1032 }
1033
1034 /* Get bit data*/
1035 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1036 {
1037         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1038
1039         if (bitbang->set_gate)
1040                 bitbang->set_gate(bitbang->addr);
1041
1042         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1043 }
1044
1045 /* MDC pin control */
1046 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1047 {
1048         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1049 }
1050
1051 /* mdio bus control struct */
1052 static struct mdiobb_ops bb_ops = {
1053         .owner = THIS_MODULE,
1054         .set_mdc = sh_mdc_ctrl,
1055         .set_mdio_dir = sh_mmd_ctrl,
1056         .set_mdio_data = sh_set_mdio,
1057         .get_mdio_data = sh_get_mdio,
1058 };
1059
1060 /* free skb and descriptor buffer */
1061 static void sh_eth_ring_free(struct net_device *ndev)
1062 {
1063         struct sh_eth_private *mdp = netdev_priv(ndev);
1064         int ringsize, i;
1065
1066         /* Free Rx skb ringbuffer */
1067         if (mdp->rx_skbuff) {
1068                 for (i = 0; i < mdp->num_rx_ring; i++)
1069                         dev_kfree_skb(mdp->rx_skbuff[i]);
1070         }
1071         kfree(mdp->rx_skbuff);
1072         mdp->rx_skbuff = NULL;
1073
1074         /* Free Tx skb ringbuffer */
1075         if (mdp->tx_skbuff) {
1076                 for (i = 0; i < mdp->num_tx_ring; i++)
1077                         dev_kfree_skb(mdp->tx_skbuff[i]);
1078         }
1079         kfree(mdp->tx_skbuff);
1080         mdp->tx_skbuff = NULL;
1081
1082         if (mdp->rx_ring) {
1083                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1084                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1085                                   mdp->rx_desc_dma);
1086                 mdp->rx_ring = NULL;
1087         }
1088
1089         if (mdp->tx_ring) {
1090                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1091                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1092                                   mdp->tx_desc_dma);
1093                 mdp->tx_ring = NULL;
1094         }
1095 }
1096
1097 /* format skb and descriptor buffer */
1098 static void sh_eth_ring_format(struct net_device *ndev)
1099 {
1100         struct sh_eth_private *mdp = netdev_priv(ndev);
1101         int i;
1102         struct sk_buff *skb;
1103         struct sh_eth_rxdesc *rxdesc = NULL;
1104         struct sh_eth_txdesc *txdesc = NULL;
1105         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1106         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1107         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1108         dma_addr_t dma_addr;
1109         u32 buf_len;
1110
1111         mdp->cur_rx = 0;
1112         mdp->cur_tx = 0;
1113         mdp->dirty_rx = 0;
1114         mdp->dirty_tx = 0;
1115
1116         memset(mdp->rx_ring, 0, rx_ringsize);
1117
1118         /* build Rx ring buffer */
1119         for (i = 0; i < mdp->num_rx_ring; i++) {
1120                 /* skb */
1121                 mdp->rx_skbuff[i] = NULL;
1122                 skb = netdev_alloc_skb(ndev, skbuff_size);
1123                 if (skb == NULL)
1124                         break;
1125                 sh_eth_set_receive_align(skb);
1126
1127                 /* The size of the buffer is a multiple of 32 bytes. */
1128                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1129                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1130                                           DMA_FROM_DEVICE);
1131                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1132                         kfree_skb(skb);
1133                         break;
1134                 }
1135                 mdp->rx_skbuff[i] = skb;
1136
1137                 /* RX descriptor */
1138                 rxdesc = &mdp->rx_ring[i];
1139                 rxdesc->len = cpu_to_le32(buf_len << 16);
1140                 rxdesc->addr = cpu_to_le32(dma_addr);
1141                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1142
1143                 /* Rx descriptor address set */
1144                 if (i == 0) {
1145                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1146                         if (sh_eth_is_gether(mdp) ||
1147                             sh_eth_is_rz_fast_ether(mdp))
1148                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1149                 }
1150         }
1151
1152         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1153
1154         /* Mark the last entry as wrapping the ring. */
1155         if (rxdesc)
1156                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1157
1158         memset(mdp->tx_ring, 0, tx_ringsize);
1159
1160         /* build Tx ring buffer */
1161         for (i = 0; i < mdp->num_tx_ring; i++) {
1162                 mdp->tx_skbuff[i] = NULL;
1163                 txdesc = &mdp->tx_ring[i];
1164                 txdesc->status = cpu_to_le32(TD_TFP);
1165                 txdesc->len = cpu_to_le32(0);
1166                 if (i == 0) {
1167                         /* Tx descriptor address set */
1168                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1169                         if (sh_eth_is_gether(mdp) ||
1170                             sh_eth_is_rz_fast_ether(mdp))
1171                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1172                 }
1173         }
1174
1175         txdesc->status |= cpu_to_le32(TD_TDLE);
1176 }
1177
1178 /* Get skb and descriptor buffer */
1179 static int sh_eth_ring_init(struct net_device *ndev)
1180 {
1181         struct sh_eth_private *mdp = netdev_priv(ndev);
1182         int rx_ringsize, tx_ringsize;
1183
1184         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1185          * card needs room to do 8 byte alignment, +2 so we can reserve
1186          * the first 2 bytes, and +16 gets room for the status word from the
1187          * card.
1188          */
1189         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1190                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1191         if (mdp->cd->rpadir)
1192                 mdp->rx_buf_sz += NET_IP_ALIGN;
1193
1194         /* Allocate RX and TX skb rings */
1195         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1196                                  GFP_KERNEL);
1197         if (!mdp->rx_skbuff)
1198                 return -ENOMEM;
1199
1200         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1201                                  GFP_KERNEL);
1202         if (!mdp->tx_skbuff)
1203                 goto ring_free;
1204
1205         /* Allocate all Rx descriptors. */
1206         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1207         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1208                                           GFP_KERNEL);
1209         if (!mdp->rx_ring)
1210                 goto ring_free;
1211
1212         mdp->dirty_rx = 0;
1213
1214         /* Allocate all Tx descriptors. */
1215         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1216         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1217                                           GFP_KERNEL);
1218         if (!mdp->tx_ring)
1219                 goto ring_free;
1220         return 0;
1221
1222 ring_free:
1223         /* Free Rx and Tx skb ring buffer and DMA buffer */
1224         sh_eth_ring_free(ndev);
1225
1226         return -ENOMEM;
1227 }
1228
1229 static int sh_eth_dev_init(struct net_device *ndev)
1230 {
1231         struct sh_eth_private *mdp = netdev_priv(ndev);
1232         int ret;
1233
1234         /* Soft Reset */
1235         ret = sh_eth_reset(ndev);
1236         if (ret)
1237                 return ret;
1238
1239         if (mdp->cd->rmiimode)
1240                 sh_eth_write(ndev, 0x1, RMIIMODE);
1241
1242         /* Descriptor format */
1243         sh_eth_ring_format(ndev);
1244         if (mdp->cd->rpadir)
1245                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1246
1247         /* all sh_eth int mask */
1248         sh_eth_write(ndev, 0, EESIPR);
1249
1250 #if defined(__LITTLE_ENDIAN)
1251         if (mdp->cd->hw_swap)
1252                 sh_eth_write(ndev, EDMR_EL, EDMR);
1253         else
1254 #endif
1255                 sh_eth_write(ndev, 0, EDMR);
1256
1257         /* FIFO size set */
1258         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1259         sh_eth_write(ndev, 0, TFTR);
1260
1261         /* Frame recv control (enable multiple-packets per rx irq) */
1262         sh_eth_write(ndev, RMCR_RNC, RMCR);
1263
1264         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1265
1266         if (mdp->cd->bculr)
1267                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1268
1269         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1270
1271         if (!mdp->cd->no_trimd)
1272                 sh_eth_write(ndev, 0, TRIMD);
1273
1274         /* Recv frame limit set register */
1275         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1276                      RFLR);
1277
1278         sh_eth_modify(ndev, EESR, 0, 0);
1279         mdp->irq_enabled = true;
1280         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1281
1282         /* PAUSE Prohibition */
1283         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1284                      ECMR_TE | ECMR_RE, ECMR);
1285
1286         if (mdp->cd->set_rate)
1287                 mdp->cd->set_rate(ndev);
1288
1289         /* E-MAC Status Register clear */
1290         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1291
1292         /* E-MAC Interrupt Enable register */
1293         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1294
1295         /* Set MAC address */
1296         update_mac_address(ndev);
1297
1298         /* mask reset */
1299         if (mdp->cd->apr)
1300                 sh_eth_write(ndev, APR_AP, APR);
1301         if (mdp->cd->mpr)
1302                 sh_eth_write(ndev, MPR_MP, MPR);
1303         if (mdp->cd->tpauser)
1304                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1305
1306         /* Setting the Rx mode will start the Rx process. */
1307         sh_eth_write(ndev, EDRRR_R, EDRRR);
1308
1309         return ret;
1310 }
1311
1312 static void sh_eth_dev_exit(struct net_device *ndev)
1313 {
1314         struct sh_eth_private *mdp = netdev_priv(ndev);
1315         int i;
1316
1317         /* Deactivate all TX descriptors, so DMA should stop at next
1318          * packet boundary if it's currently running
1319          */
1320         for (i = 0; i < mdp->num_tx_ring; i++)
1321                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1322
1323         /* Disable TX FIFO egress to MAC */
1324         sh_eth_rcv_snd_disable(ndev);
1325
1326         /* Stop RX DMA at next packet boundary */
1327         sh_eth_write(ndev, 0, EDRRR);
1328
1329         /* Aside from TX DMA, we can't tell when the hardware is
1330          * really stopped, so we need to reset to make sure.
1331          * Before doing that, wait for long enough to *probably*
1332          * finish transmitting the last packet and poll stats.
1333          */
1334         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1335         sh_eth_get_stats(ndev);
1336         sh_eth_reset(ndev);
1337
1338         /* Set MAC address again */
1339         update_mac_address(ndev);
1340 }
1341
1342 /* free Tx skb function */
1343 static int sh_eth_txfree(struct net_device *ndev)
1344 {
1345         struct sh_eth_private *mdp = netdev_priv(ndev);
1346         struct sh_eth_txdesc *txdesc;
1347         int free_num = 0;
1348         int entry;
1349
1350         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1351                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1352                 txdesc = &mdp->tx_ring[entry];
1353                 if (txdesc->status & cpu_to_le32(TD_TACT))
1354                         break;
1355                 /* TACT bit must be checked before all the following reads */
1356                 dma_rmb();
1357                 netif_info(mdp, tx_done, ndev,
1358                            "tx entry %d status 0x%08x\n",
1359                            entry, le32_to_cpu(txdesc->status));
1360                 /* Free the original skb. */
1361                 if (mdp->tx_skbuff[entry]) {
1362                         dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1363                                          le32_to_cpu(txdesc->len) >> 16,
1364                                          DMA_TO_DEVICE);
1365                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1366                         mdp->tx_skbuff[entry] = NULL;
1367                         free_num++;
1368                 }
1369                 txdesc->status = cpu_to_le32(TD_TFP);
1370                 if (entry >= mdp->num_tx_ring - 1)
1371                         txdesc->status |= cpu_to_le32(TD_TDLE);
1372
1373                 ndev->stats.tx_packets++;
1374                 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1375         }
1376         return free_num;
1377 }
1378
1379 /* Packet receive function */
1380 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1381 {
1382         struct sh_eth_private *mdp = netdev_priv(ndev);
1383         struct sh_eth_rxdesc *rxdesc;
1384
1385         int entry = mdp->cur_rx % mdp->num_rx_ring;
1386         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1387         int limit;
1388         struct sk_buff *skb;
1389         u32 desc_status;
1390         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1391         dma_addr_t dma_addr;
1392         u16 pkt_len;
1393         u32 buf_len;
1394
1395         boguscnt = min(boguscnt, *quota);
1396         limit = boguscnt;
1397         rxdesc = &mdp->rx_ring[entry];
1398         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1399                 /* RACT bit must be checked before all the following reads */
1400                 dma_rmb();
1401                 desc_status = le32_to_cpu(rxdesc->status);
1402                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1403
1404                 if (--boguscnt < 0)
1405                         break;
1406
1407                 netif_info(mdp, rx_status, ndev,
1408                            "rx entry %d status 0x%08x len %d\n",
1409                            entry, desc_status, pkt_len);
1410
1411                 if (!(desc_status & RDFEND))
1412                         ndev->stats.rx_length_errors++;
1413
1414                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1415                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1416                  * bit 0. However, in case of the R8A7740 and R7S72100
1417                  * the RFS bits are from bit 25 to bit 16. So, the
1418                  * driver needs right shifting by 16.
1419                  */
1420                 if (mdp->cd->hw_checksum)
1421                         desc_status >>= 16;
1422
1423                 skb = mdp->rx_skbuff[entry];
1424                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1425                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1426                         ndev->stats.rx_errors++;
1427                         if (desc_status & RD_RFS1)
1428                                 ndev->stats.rx_crc_errors++;
1429                         if (desc_status & RD_RFS2)
1430                                 ndev->stats.rx_frame_errors++;
1431                         if (desc_status & RD_RFS3)
1432                                 ndev->stats.rx_length_errors++;
1433                         if (desc_status & RD_RFS4)
1434                                 ndev->stats.rx_length_errors++;
1435                         if (desc_status & RD_RFS6)
1436                                 ndev->stats.rx_missed_errors++;
1437                         if (desc_status & RD_RFS10)
1438                                 ndev->stats.rx_over_errors++;
1439                 } else  if (skb) {
1440                         dma_addr = le32_to_cpu(rxdesc->addr);
1441                         if (!mdp->cd->hw_swap)
1442                                 sh_eth_soft_swap(
1443                                         phys_to_virt(ALIGN(dma_addr, 4)),
1444                                         pkt_len + 2);
1445                         mdp->rx_skbuff[entry] = NULL;
1446                         if (mdp->cd->rpadir)
1447                                 skb_reserve(skb, NET_IP_ALIGN);
1448                         dma_unmap_single(&ndev->dev, dma_addr,
1449                                          ALIGN(mdp->rx_buf_sz, 32),
1450                                          DMA_FROM_DEVICE);
1451                         skb_put(skb, pkt_len);
1452                         skb->protocol = eth_type_trans(skb, ndev);
1453                         netif_receive_skb(skb);
1454                         ndev->stats.rx_packets++;
1455                         ndev->stats.rx_bytes += pkt_len;
1456                         if (desc_status & RD_RFS8)
1457                                 ndev->stats.multicast++;
1458                 }
1459                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1460                 rxdesc = &mdp->rx_ring[entry];
1461         }
1462
1463         /* Refill the Rx ring buffers. */
1464         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1465                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1466                 rxdesc = &mdp->rx_ring[entry];
1467                 /* The size of the buffer is 32 byte boundary. */
1468                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1469                 rxdesc->len = cpu_to_le32(buf_len << 16);
1470
1471                 if (mdp->rx_skbuff[entry] == NULL) {
1472                         skb = netdev_alloc_skb(ndev, skbuff_size);
1473                         if (skb == NULL)
1474                                 break;  /* Better luck next round. */
1475                         sh_eth_set_receive_align(skb);
1476                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1477                                                   buf_len, DMA_FROM_DEVICE);
1478                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1479                                 kfree_skb(skb);
1480                                 break;
1481                         }
1482                         mdp->rx_skbuff[entry] = skb;
1483
1484                         skb_checksum_none_assert(skb);
1485                         rxdesc->addr = cpu_to_le32(dma_addr);
1486                 }
1487                 dma_wmb(); /* RACT bit must be set after all the above writes */
1488                 if (entry >= mdp->num_rx_ring - 1)
1489                         rxdesc->status |=
1490                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1491                 else
1492                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1493         }
1494
1495         /* Restart Rx engine if stopped. */
1496         /* If we don't need to check status, don't. -KDU */
1497         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1498                 /* fix the values for the next receiving if RDE is set */
1499                 if (intr_status & EESR_RDE &&
1500                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1501                         u32 count = (sh_eth_read(ndev, RDFAR) -
1502                                      sh_eth_read(ndev, RDLAR)) >> 4;
1503
1504                         mdp->cur_rx = count;
1505                         mdp->dirty_rx = count;
1506                 }
1507                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1508         }
1509
1510         *quota -= limit - boguscnt - 1;
1511
1512         return *quota <= 0;
1513 }
1514
1515 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1516 {
1517         /* disable tx and rx */
1518         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1519 }
1520
1521 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1522 {
1523         /* enable tx and rx */
1524         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1525 }
1526
1527 /* E-MAC interrupt handler */
1528 static void sh_eth_emac_interrupt(struct net_device *ndev)
1529 {
1530         struct sh_eth_private *mdp = netdev_priv(ndev);
1531         u32 felic_stat;
1532         u32 link_stat;
1533
1534         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1535         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1536         if (felic_stat & ECSR_ICD)
1537                 ndev->stats.tx_carrier_errors++;
1538         if (felic_stat & ECSR_LCHNG) {
1539                 /* Link Changed */
1540                 if (mdp->cd->no_psr || mdp->no_ether_link)
1541                         return;
1542                 link_stat = sh_eth_read(ndev, PSR);
1543                 if (mdp->ether_link_active_low)
1544                         link_stat = ~link_stat;
1545                 if (!(link_stat & PHY_ST_LINK)) {
1546                         sh_eth_rcv_snd_disable(ndev);
1547                 } else {
1548                         /* Link Up */
1549                         sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1550                         /* clear int */
1551                         sh_eth_modify(ndev, ECSR, 0, 0);
1552                         sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
1553                         /* enable tx and rx */
1554                         sh_eth_rcv_snd_enable(ndev);
1555                 }
1556         }
1557         if (felic_stat & ECSR_MPD)
1558                 pm_wakeup_event(&mdp->pdev->dev, 0);
1559 }
1560
1561 /* error control function */
1562 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1563 {
1564         struct sh_eth_private *mdp = netdev_priv(ndev);
1565         u32 mask;
1566
1567         if (intr_status & EESR_TWB) {
1568                 /* Unused write back interrupt */
1569                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1570                         ndev->stats.tx_aborted_errors++;
1571                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1572                 }
1573         }
1574
1575         if (intr_status & EESR_RABT) {
1576                 /* Receive Abort int */
1577                 if (intr_status & EESR_RFRMER) {
1578                         /* Receive Frame Overflow int */
1579                         ndev->stats.rx_frame_errors++;
1580                 }
1581         }
1582
1583         if (intr_status & EESR_TDE) {
1584                 /* Transmit Descriptor Empty int */
1585                 ndev->stats.tx_fifo_errors++;
1586                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1587         }
1588
1589         if (intr_status & EESR_TFE) {
1590                 /* FIFO under flow */
1591                 ndev->stats.tx_fifo_errors++;
1592                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1593         }
1594
1595         if (intr_status & EESR_RDE) {
1596                 /* Receive Descriptor Empty int */
1597                 ndev->stats.rx_over_errors++;
1598         }
1599
1600         if (intr_status & EESR_RFE) {
1601                 /* Receive FIFO Overflow int */
1602                 ndev->stats.rx_fifo_errors++;
1603         }
1604
1605         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1606                 /* Address Error */
1607                 ndev->stats.tx_fifo_errors++;
1608                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1609         }
1610
1611         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1612         if (mdp->cd->no_ade)
1613                 mask &= ~EESR_ADE;
1614         if (intr_status & mask) {
1615                 /* Tx error */
1616                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1617
1618                 /* dmesg */
1619                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1620                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1621                            (u32)ndev->state, edtrr);
1622                 /* dirty buffer free */
1623                 sh_eth_txfree(ndev);
1624
1625                 /* SH7712 BUG */
1626                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1627                         /* tx dma start */
1628                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1629                 }
1630                 /* wakeup */
1631                 netif_wake_queue(ndev);
1632         }
1633 }
1634
1635 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1636 {
1637         struct net_device *ndev = netdev;
1638         struct sh_eth_private *mdp = netdev_priv(ndev);
1639         struct sh_eth_cpu_data *cd = mdp->cd;
1640         irqreturn_t ret = IRQ_NONE;
1641         u32 intr_status, intr_enable;
1642
1643         spin_lock(&mdp->lock);
1644
1645         /* Get interrupt status */
1646         intr_status = sh_eth_read(ndev, EESR);
1647         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1648          * enabled since it's the one that  comes  thru regardless of the mask,
1649          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1650          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1651          * bit...
1652          */
1653         intr_enable = sh_eth_read(ndev, EESIPR);
1654         intr_status &= intr_enable | DMAC_M_ECI;
1655         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1656                            cd->eesr_err_check))
1657                 ret = IRQ_HANDLED;
1658         else
1659                 goto out;
1660
1661         if (unlikely(!mdp->irq_enabled)) {
1662                 sh_eth_write(ndev, 0, EESIPR);
1663                 goto out;
1664         }
1665
1666         if (intr_status & EESR_RX_CHECK) {
1667                 if (napi_schedule_prep(&mdp->napi)) {
1668                         /* Mask Rx interrupts */
1669                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1670                                      EESIPR);
1671                         __napi_schedule(&mdp->napi);
1672                 } else {
1673                         netdev_warn(ndev,
1674                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1675                                     intr_status, intr_enable);
1676                 }
1677         }
1678
1679         /* Tx Check */
1680         if (intr_status & cd->tx_check) {
1681                 /* Clear Tx interrupts */
1682                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1683
1684                 sh_eth_txfree(ndev);
1685                 netif_wake_queue(ndev);
1686         }
1687
1688         /* E-MAC interrupt */
1689         if (intr_status & EESR_ECI)
1690                 sh_eth_emac_interrupt(ndev);
1691
1692         if (intr_status & cd->eesr_err_check) {
1693                 /* Clear error interrupts */
1694                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1695
1696                 sh_eth_error(ndev, intr_status);
1697         }
1698
1699 out:
1700         spin_unlock(&mdp->lock);
1701
1702         return ret;
1703 }
1704
1705 static int sh_eth_poll(struct napi_struct *napi, int budget)
1706 {
1707         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1708                                                   napi);
1709         struct net_device *ndev = napi->dev;
1710         int quota = budget;
1711         u32 intr_status;
1712
1713         for (;;) {
1714                 intr_status = sh_eth_read(ndev, EESR);
1715                 if (!(intr_status & EESR_RX_CHECK))
1716                         break;
1717                 /* Clear Rx interrupts */
1718                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1719
1720                 if (sh_eth_rx(ndev, intr_status, &quota))
1721                         goto out;
1722         }
1723
1724         napi_complete(napi);
1725
1726         /* Reenable Rx interrupts */
1727         if (mdp->irq_enabled)
1728                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1729 out:
1730         return budget - quota;
1731 }
1732
1733 /* PHY state control function */
1734 static void sh_eth_adjust_link(struct net_device *ndev)
1735 {
1736         struct sh_eth_private *mdp = netdev_priv(ndev);
1737         struct phy_device *phydev = ndev->phydev;
1738         int new_state = 0;
1739
1740         if (phydev->link) {
1741                 if (phydev->duplex != mdp->duplex) {
1742                         new_state = 1;
1743                         mdp->duplex = phydev->duplex;
1744                         if (mdp->cd->set_duplex)
1745                                 mdp->cd->set_duplex(ndev);
1746                 }
1747
1748                 if (phydev->speed != mdp->speed) {
1749                         new_state = 1;
1750                         mdp->speed = phydev->speed;
1751                         if (mdp->cd->set_rate)
1752                                 mdp->cd->set_rate(ndev);
1753                 }
1754                 if (!mdp->link) {
1755                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1756                         new_state = 1;
1757                         mdp->link = phydev->link;
1758                         if (mdp->cd->no_psr || mdp->no_ether_link)
1759                                 sh_eth_rcv_snd_enable(ndev);
1760                 }
1761         } else if (mdp->link) {
1762                 new_state = 1;
1763                 mdp->link = 0;
1764                 mdp->speed = 0;
1765                 mdp->duplex = -1;
1766                 if (mdp->cd->no_psr || mdp->no_ether_link)
1767                         sh_eth_rcv_snd_disable(ndev);
1768         }
1769
1770         if (new_state && netif_msg_link(mdp))
1771                 phy_print_status(phydev);
1772 }
1773
1774 /* PHY init function */
1775 static int sh_eth_phy_init(struct net_device *ndev)
1776 {
1777         struct device_node *np = ndev->dev.parent->of_node;
1778         struct sh_eth_private *mdp = netdev_priv(ndev);
1779         struct phy_device *phydev;
1780
1781         mdp->link = 0;
1782         mdp->speed = 0;
1783         mdp->duplex = -1;
1784
1785         /* Try connect to PHY */
1786         if (np) {
1787                 struct device_node *pn;
1788
1789                 pn = of_parse_phandle(np, "phy-handle", 0);
1790                 phydev = of_phy_connect(ndev, pn,
1791                                         sh_eth_adjust_link, 0,
1792                                         mdp->phy_interface);
1793
1794                 of_node_put(pn);
1795                 if (!phydev)
1796                         phydev = ERR_PTR(-ENOENT);
1797         } else {
1798                 char phy_id[MII_BUS_ID_SIZE + 3];
1799
1800                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1801                          mdp->mii_bus->id, mdp->phy_id);
1802
1803                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1804                                      mdp->phy_interface);
1805         }
1806
1807         if (IS_ERR(phydev)) {
1808                 netdev_err(ndev, "failed to connect PHY\n");
1809                 return PTR_ERR(phydev);
1810         }
1811
1812         phy_attached_info(phydev);
1813
1814         return 0;
1815 }
1816
1817 /* PHY control start function */
1818 static int sh_eth_phy_start(struct net_device *ndev)
1819 {
1820         int ret;
1821
1822         ret = sh_eth_phy_init(ndev);
1823         if (ret)
1824                 return ret;
1825
1826         phy_start(ndev->phydev);
1827
1828         return 0;
1829 }
1830
1831 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1832                                      struct ethtool_link_ksettings *cmd)
1833 {
1834         struct sh_eth_private *mdp = netdev_priv(ndev);
1835         unsigned long flags;
1836         int ret;
1837
1838         if (!ndev->phydev)
1839                 return -ENODEV;
1840
1841         spin_lock_irqsave(&mdp->lock, flags);
1842         ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1843         spin_unlock_irqrestore(&mdp->lock, flags);
1844
1845         return ret;
1846 }
1847
1848 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1849                                      const struct ethtool_link_ksettings *cmd)
1850 {
1851         struct sh_eth_private *mdp = netdev_priv(ndev);
1852         unsigned long flags;
1853         int ret;
1854
1855         if (!ndev->phydev)
1856                 return -ENODEV;
1857
1858         spin_lock_irqsave(&mdp->lock, flags);
1859
1860         /* disable tx and rx */
1861         sh_eth_rcv_snd_disable(ndev);
1862
1863         ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1864         if (ret)
1865                 goto error_exit;
1866
1867         if (cmd->base.duplex == DUPLEX_FULL)
1868                 mdp->duplex = 1;
1869         else
1870                 mdp->duplex = 0;
1871
1872         if (mdp->cd->set_duplex)
1873                 mdp->cd->set_duplex(ndev);
1874
1875 error_exit:
1876         mdelay(1);
1877
1878         /* enable tx and rx */
1879         sh_eth_rcv_snd_enable(ndev);
1880
1881         spin_unlock_irqrestore(&mdp->lock, flags);
1882
1883         return ret;
1884 }
1885
1886 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1887  * version must be bumped as well.  Just adding registers up to that
1888  * limit is fine, as long as the existing register indices don't
1889  * change.
1890  */
1891 #define SH_ETH_REG_DUMP_VERSION         1
1892 #define SH_ETH_REG_DUMP_MAX_REGS        256
1893
1894 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1895 {
1896         struct sh_eth_private *mdp = netdev_priv(ndev);
1897         struct sh_eth_cpu_data *cd = mdp->cd;
1898         u32 *valid_map;
1899         size_t len;
1900
1901         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1902
1903         /* Dump starts with a bitmap that tells ethtool which
1904          * registers are defined for this chip.
1905          */
1906         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1907         if (buf) {
1908                 valid_map = buf;
1909                 buf += len;
1910         } else {
1911                 valid_map = NULL;
1912         }
1913
1914         /* Add a register to the dump, if it has a defined offset.
1915          * This automatically skips most undefined registers, but for
1916          * some it is also necessary to check a capability flag in
1917          * struct sh_eth_cpu_data.
1918          */
1919 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1920 #define add_reg_from(reg, read_expr) do {                               \
1921                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1922                         if (buf) {                                      \
1923                                 mark_reg_valid(reg);                    \
1924                                 *buf++ = read_expr;                     \
1925                         }                                               \
1926                         ++len;                                          \
1927                 }                                                       \
1928         } while (0)
1929 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1930 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1931
1932         add_reg(EDSR);
1933         add_reg(EDMR);
1934         add_reg(EDTRR);
1935         add_reg(EDRRR);
1936         add_reg(EESR);
1937         add_reg(EESIPR);
1938         add_reg(TDLAR);
1939         add_reg(TDFAR);
1940         add_reg(TDFXR);
1941         add_reg(TDFFR);
1942         add_reg(RDLAR);
1943         add_reg(RDFAR);
1944         add_reg(RDFXR);
1945         add_reg(RDFFR);
1946         add_reg(TRSCER);
1947         add_reg(RMFCR);
1948         add_reg(TFTR);
1949         add_reg(FDR);
1950         add_reg(RMCR);
1951         add_reg(TFUCR);
1952         add_reg(RFOCR);
1953         if (cd->rmiimode)
1954                 add_reg(RMIIMODE);
1955         add_reg(FCFTR);
1956         if (cd->rpadir)
1957                 add_reg(RPADIR);
1958         if (!cd->no_trimd)
1959                 add_reg(TRIMD);
1960         add_reg(ECMR);
1961         add_reg(ECSR);
1962         add_reg(ECSIPR);
1963         add_reg(PIR);
1964         if (!cd->no_psr)
1965                 add_reg(PSR);
1966         add_reg(RDMLR);
1967         add_reg(RFLR);
1968         add_reg(IPGR);
1969         if (cd->apr)
1970                 add_reg(APR);
1971         if (cd->mpr)
1972                 add_reg(MPR);
1973         add_reg(RFCR);
1974         add_reg(RFCF);
1975         if (cd->tpauser)
1976                 add_reg(TPAUSER);
1977         add_reg(TPAUSECR);
1978         add_reg(GECMR);
1979         if (cd->bculr)
1980                 add_reg(BCULR);
1981         add_reg(MAHR);
1982         add_reg(MALR);
1983         add_reg(TROCR);
1984         add_reg(CDCR);
1985         add_reg(LCCR);
1986         add_reg(CNDCR);
1987         add_reg(CEFCR);
1988         add_reg(FRECR);
1989         add_reg(TSFRCR);
1990         add_reg(TLFRCR);
1991         add_reg(CERCR);
1992         add_reg(CEECR);
1993         add_reg(MAFCR);
1994         if (cd->rtrate)
1995                 add_reg(RTRATE);
1996         if (cd->hw_checksum)
1997                 add_reg(CSMR);
1998         if (cd->select_mii)
1999                 add_reg(RMII_MII);
2000         add_reg(ARSTR);
2001         if (cd->tsu) {
2002                 add_tsu_reg(TSU_CTRST);
2003                 add_tsu_reg(TSU_FWEN0);
2004                 add_tsu_reg(TSU_FWEN1);
2005                 add_tsu_reg(TSU_FCM);
2006                 add_tsu_reg(TSU_BSYSL0);
2007                 add_tsu_reg(TSU_BSYSL1);
2008                 add_tsu_reg(TSU_PRISL0);
2009                 add_tsu_reg(TSU_PRISL1);
2010                 add_tsu_reg(TSU_FWSL0);
2011                 add_tsu_reg(TSU_FWSL1);
2012                 add_tsu_reg(TSU_FWSLC);
2013                 add_tsu_reg(TSU_QTAG0);
2014                 add_tsu_reg(TSU_QTAG1);
2015                 add_tsu_reg(TSU_QTAGM0);
2016                 add_tsu_reg(TSU_QTAGM1);
2017                 add_tsu_reg(TSU_FWSR);
2018                 add_tsu_reg(TSU_FWINMK);
2019                 add_tsu_reg(TSU_ADQT0);
2020                 add_tsu_reg(TSU_ADQT1);
2021                 add_tsu_reg(TSU_VTAG0);
2022                 add_tsu_reg(TSU_VTAG1);
2023                 add_tsu_reg(TSU_ADSBSY);
2024                 add_tsu_reg(TSU_TEN);
2025                 add_tsu_reg(TSU_POST1);
2026                 add_tsu_reg(TSU_POST2);
2027                 add_tsu_reg(TSU_POST3);
2028                 add_tsu_reg(TSU_POST4);
2029                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2030                         /* This is the start of a table, not just a single
2031                          * register.
2032                          */
2033                         if (buf) {
2034                                 unsigned int i;
2035
2036                                 mark_reg_valid(TSU_ADRH0);
2037                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2038                                         *buf++ = ioread32(
2039                                                 mdp->tsu_addr +
2040                                                 mdp->reg_offset[TSU_ADRH0] +
2041                                                 i * 4);
2042                         }
2043                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2044                 }
2045         }
2046
2047 #undef mark_reg_valid
2048 #undef add_reg_from
2049 #undef add_reg
2050 #undef add_tsu_reg
2051
2052         return len * 4;
2053 }
2054
2055 static int sh_eth_get_regs_len(struct net_device *ndev)
2056 {
2057         return __sh_eth_get_regs(ndev, NULL);
2058 }
2059
2060 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2061                             void *buf)
2062 {
2063         struct sh_eth_private *mdp = netdev_priv(ndev);
2064
2065         regs->version = SH_ETH_REG_DUMP_VERSION;
2066
2067         pm_runtime_get_sync(&mdp->pdev->dev);
2068         __sh_eth_get_regs(ndev, buf);
2069         pm_runtime_put_sync(&mdp->pdev->dev);
2070 }
2071
2072 static int sh_eth_nway_reset(struct net_device *ndev)
2073 {
2074         struct sh_eth_private *mdp = netdev_priv(ndev);
2075         unsigned long flags;
2076         int ret;
2077
2078         if (!ndev->phydev)
2079                 return -ENODEV;
2080
2081         spin_lock_irqsave(&mdp->lock, flags);
2082         ret = phy_start_aneg(ndev->phydev);
2083         spin_unlock_irqrestore(&mdp->lock, flags);
2084
2085         return ret;
2086 }
2087
2088 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2089 {
2090         struct sh_eth_private *mdp = netdev_priv(ndev);
2091         return mdp->msg_enable;
2092 }
2093
2094 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2095 {
2096         struct sh_eth_private *mdp = netdev_priv(ndev);
2097         mdp->msg_enable = value;
2098 }
2099
2100 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2101         "rx_current", "tx_current",
2102         "rx_dirty", "tx_dirty",
2103 };
2104 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2105
2106 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2107 {
2108         switch (sset) {
2109         case ETH_SS_STATS:
2110                 return SH_ETH_STATS_LEN;
2111         default:
2112                 return -EOPNOTSUPP;
2113         }
2114 }
2115
2116 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2117                                      struct ethtool_stats *stats, u64 *data)
2118 {
2119         struct sh_eth_private *mdp = netdev_priv(ndev);
2120         int i = 0;
2121
2122         /* device-specific stats */
2123         data[i++] = mdp->cur_rx;
2124         data[i++] = mdp->cur_tx;
2125         data[i++] = mdp->dirty_rx;
2126         data[i++] = mdp->dirty_tx;
2127 }
2128
2129 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2130 {
2131         switch (stringset) {
2132         case ETH_SS_STATS:
2133                 memcpy(data, *sh_eth_gstrings_stats,
2134                        sizeof(sh_eth_gstrings_stats));
2135                 break;
2136         }
2137 }
2138
2139 static void sh_eth_get_ringparam(struct net_device *ndev,
2140                                  struct ethtool_ringparam *ring)
2141 {
2142         struct sh_eth_private *mdp = netdev_priv(ndev);
2143
2144         ring->rx_max_pending = RX_RING_MAX;
2145         ring->tx_max_pending = TX_RING_MAX;
2146         ring->rx_pending = mdp->num_rx_ring;
2147         ring->tx_pending = mdp->num_tx_ring;
2148 }
2149
2150 static int sh_eth_set_ringparam(struct net_device *ndev,
2151                                 struct ethtool_ringparam *ring)
2152 {
2153         struct sh_eth_private *mdp = netdev_priv(ndev);
2154         int ret;
2155
2156         if (ring->tx_pending > TX_RING_MAX ||
2157             ring->rx_pending > RX_RING_MAX ||
2158             ring->tx_pending < TX_RING_MIN ||
2159             ring->rx_pending < RX_RING_MIN)
2160                 return -EINVAL;
2161         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2162                 return -EINVAL;
2163
2164         if (netif_running(ndev)) {
2165                 netif_device_detach(ndev);
2166                 netif_tx_disable(ndev);
2167
2168                 /* Serialise with the interrupt handler and NAPI, then
2169                  * disable interrupts.  We have to clear the
2170                  * irq_enabled flag first to ensure that interrupts
2171                  * won't be re-enabled.
2172                  */
2173                 mdp->irq_enabled = false;
2174                 synchronize_irq(ndev->irq);
2175                 napi_synchronize(&mdp->napi);
2176                 sh_eth_write(ndev, 0x0000, EESIPR);
2177
2178                 sh_eth_dev_exit(ndev);
2179
2180                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2181                 sh_eth_ring_free(ndev);
2182         }
2183
2184         /* Set new parameters */
2185         mdp->num_rx_ring = ring->rx_pending;
2186         mdp->num_tx_ring = ring->tx_pending;
2187
2188         if (netif_running(ndev)) {
2189                 ret = sh_eth_ring_init(ndev);
2190                 if (ret < 0) {
2191                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2192                                    __func__);
2193                         return ret;
2194                 }
2195                 ret = sh_eth_dev_init(ndev);
2196                 if (ret < 0) {
2197                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2198                                    __func__);
2199                         return ret;
2200                 }
2201
2202                 netif_device_attach(ndev);
2203         }
2204
2205         return 0;
2206 }
2207
2208 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2209 {
2210         struct sh_eth_private *mdp = netdev_priv(ndev);
2211
2212         wol->supported = 0;
2213         wol->wolopts = 0;
2214
2215         if (mdp->cd->magic && mdp->clk) {
2216                 wol->supported = WAKE_MAGIC;
2217                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2218         }
2219 }
2220
2221 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2222 {
2223         struct sh_eth_private *mdp = netdev_priv(ndev);
2224
2225         if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
2226                 return -EOPNOTSUPP;
2227
2228         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2229
2230         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2231
2232         return 0;
2233 }
2234
2235 static const struct ethtool_ops sh_eth_ethtool_ops = {
2236         .get_regs_len   = sh_eth_get_regs_len,
2237         .get_regs       = sh_eth_get_regs,
2238         .nway_reset     = sh_eth_nway_reset,
2239         .get_msglevel   = sh_eth_get_msglevel,
2240         .set_msglevel   = sh_eth_set_msglevel,
2241         .get_link       = ethtool_op_get_link,
2242         .get_strings    = sh_eth_get_strings,
2243         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2244         .get_sset_count     = sh_eth_get_sset_count,
2245         .get_ringparam  = sh_eth_get_ringparam,
2246         .set_ringparam  = sh_eth_set_ringparam,
2247         .get_link_ksettings = sh_eth_get_link_ksettings,
2248         .set_link_ksettings = sh_eth_set_link_ksettings,
2249         .get_wol        = sh_eth_get_wol,
2250         .set_wol        = sh_eth_set_wol,
2251 };
2252
2253 /* network device open function */
2254 static int sh_eth_open(struct net_device *ndev)
2255 {
2256         struct sh_eth_private *mdp = netdev_priv(ndev);
2257         int ret;
2258
2259         pm_runtime_get_sync(&mdp->pdev->dev);
2260
2261         napi_enable(&mdp->napi);
2262
2263         ret = request_irq(ndev->irq, sh_eth_interrupt,
2264                           mdp->cd->irq_flags, ndev->name, ndev);
2265         if (ret) {
2266                 netdev_err(ndev, "Can not assign IRQ number\n");
2267                 goto out_napi_off;
2268         }
2269
2270         /* Descriptor set */
2271         ret = sh_eth_ring_init(ndev);
2272         if (ret)
2273                 goto out_free_irq;
2274
2275         /* device init */
2276         ret = sh_eth_dev_init(ndev);
2277         if (ret)
2278                 goto out_free_irq;
2279
2280         /* PHY control start*/
2281         ret = sh_eth_phy_start(ndev);
2282         if (ret)
2283                 goto out_free_irq;
2284
2285         netif_start_queue(ndev);
2286
2287         mdp->is_opened = 1;
2288
2289         return ret;
2290
2291 out_free_irq:
2292         free_irq(ndev->irq, ndev);
2293 out_napi_off:
2294         napi_disable(&mdp->napi);
2295         pm_runtime_put_sync(&mdp->pdev->dev);
2296         return ret;
2297 }
2298
2299 /* Timeout function */
2300 static void sh_eth_tx_timeout(struct net_device *ndev)
2301 {
2302         struct sh_eth_private *mdp = netdev_priv(ndev);
2303         struct sh_eth_rxdesc *rxdesc;
2304         int i;
2305
2306         netif_stop_queue(ndev);
2307
2308         netif_err(mdp, timer, ndev,
2309                   "transmit timed out, status %8.8x, resetting...\n",
2310                   sh_eth_read(ndev, EESR));
2311
2312         /* tx_errors count up */
2313         ndev->stats.tx_errors++;
2314
2315         /* Free all the skbuffs in the Rx queue. */
2316         for (i = 0; i < mdp->num_rx_ring; i++) {
2317                 rxdesc = &mdp->rx_ring[i];
2318                 rxdesc->status = cpu_to_le32(0);
2319                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2320                 dev_kfree_skb(mdp->rx_skbuff[i]);
2321                 mdp->rx_skbuff[i] = NULL;
2322         }
2323         for (i = 0; i < mdp->num_tx_ring; i++) {
2324                 dev_kfree_skb(mdp->tx_skbuff[i]);
2325                 mdp->tx_skbuff[i] = NULL;
2326         }
2327
2328         /* device init */
2329         sh_eth_dev_init(ndev);
2330
2331         netif_start_queue(ndev);
2332 }
2333
2334 /* Packet transmit function */
2335 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2336 {
2337         struct sh_eth_private *mdp = netdev_priv(ndev);
2338         struct sh_eth_txdesc *txdesc;
2339         dma_addr_t dma_addr;
2340         u32 entry;
2341         unsigned long flags;
2342
2343         spin_lock_irqsave(&mdp->lock, flags);
2344         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2345                 if (!sh_eth_txfree(ndev)) {
2346                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2347                         netif_stop_queue(ndev);
2348                         spin_unlock_irqrestore(&mdp->lock, flags);
2349                         return NETDEV_TX_BUSY;
2350                 }
2351         }
2352         spin_unlock_irqrestore(&mdp->lock, flags);
2353
2354         if (skb_put_padto(skb, ETH_ZLEN))
2355                 return NETDEV_TX_OK;
2356
2357         entry = mdp->cur_tx % mdp->num_tx_ring;
2358         mdp->tx_skbuff[entry] = skb;
2359         txdesc = &mdp->tx_ring[entry];
2360         /* soft swap. */
2361         if (!mdp->cd->hw_swap)
2362                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2363         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2364                                   DMA_TO_DEVICE);
2365         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2366                 kfree_skb(skb);
2367                 return NETDEV_TX_OK;
2368         }
2369         txdesc->addr = cpu_to_le32(dma_addr);
2370         txdesc->len  = cpu_to_le32(skb->len << 16);
2371
2372         dma_wmb(); /* TACT bit must be set after all the above writes */
2373         if (entry >= mdp->num_tx_ring - 1)
2374                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2375         else
2376                 txdesc->status |= cpu_to_le32(TD_TACT);
2377
2378         mdp->cur_tx++;
2379
2380         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2381                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2382
2383         return NETDEV_TX_OK;
2384 }
2385
2386 /* The statistics registers have write-clear behaviour, which means we
2387  * will lose any increment between the read and write.  We mitigate
2388  * this by only clearing when we read a non-zero value, so we will
2389  * never falsely report a total of zero.
2390  */
2391 static void
2392 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2393 {
2394         u32 delta = sh_eth_read(ndev, reg);
2395
2396         if (delta) {
2397                 *stat += delta;
2398                 sh_eth_write(ndev, 0, reg);
2399         }
2400 }
2401
2402 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2403 {
2404         struct sh_eth_private *mdp = netdev_priv(ndev);
2405
2406         if (sh_eth_is_rz_fast_ether(mdp))
2407                 return &ndev->stats;
2408
2409         if (!mdp->is_opened)
2410                 return &ndev->stats;
2411
2412         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2413         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2414         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2415
2416         if (sh_eth_is_gether(mdp)) {
2417                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2418                                    CERCR);
2419                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2420                                    CEECR);
2421         } else {
2422                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2423                                    CNDCR);
2424         }
2425
2426         return &ndev->stats;
2427 }
2428
2429 /* device close function */
2430 static int sh_eth_close(struct net_device *ndev)
2431 {
2432         struct sh_eth_private *mdp = netdev_priv(ndev);
2433
2434         netif_stop_queue(ndev);
2435
2436         /* Serialise with the interrupt handler and NAPI, then disable
2437          * interrupts.  We have to clear the irq_enabled flag first to
2438          * ensure that interrupts won't be re-enabled.
2439          */
2440         mdp->irq_enabled = false;
2441         synchronize_irq(ndev->irq);
2442         napi_disable(&mdp->napi);
2443         sh_eth_write(ndev, 0x0000, EESIPR);
2444
2445         sh_eth_dev_exit(ndev);
2446
2447         /* PHY Disconnect */
2448         if (ndev->phydev) {
2449                 phy_stop(ndev->phydev);
2450                 phy_disconnect(ndev->phydev);
2451         }
2452
2453         free_irq(ndev->irq, ndev);
2454
2455         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2456         sh_eth_ring_free(ndev);
2457
2458         pm_runtime_put_sync(&mdp->pdev->dev);
2459
2460         mdp->is_opened = 0;
2461
2462         return 0;
2463 }
2464
2465 /* ioctl to device function */
2466 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2467 {
2468         struct phy_device *phydev = ndev->phydev;
2469
2470         if (!netif_running(ndev))
2471                 return -EINVAL;
2472
2473         if (!phydev)
2474                 return -ENODEV;
2475
2476         return phy_mii_ioctl(phydev, rq, cmd);
2477 }
2478
2479 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2480 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2481                                             int entry)
2482 {
2483         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2484 }
2485
2486 static u32 sh_eth_tsu_get_post_mask(int entry)
2487 {
2488         return 0x0f << (28 - ((entry % 8) * 4));
2489 }
2490
2491 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2492 {
2493         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2494 }
2495
2496 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2497                                              int entry)
2498 {
2499         struct sh_eth_private *mdp = netdev_priv(ndev);
2500         u32 tmp;
2501         void *reg_offset;
2502
2503         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2504         tmp = ioread32(reg_offset);
2505         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2506 }
2507
2508 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2509                                               int entry)
2510 {
2511         struct sh_eth_private *mdp = netdev_priv(ndev);
2512         u32 post_mask, ref_mask, tmp;
2513         void *reg_offset;
2514
2515         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2516         post_mask = sh_eth_tsu_get_post_mask(entry);
2517         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2518
2519         tmp = ioread32(reg_offset);
2520         iowrite32(tmp & ~post_mask, reg_offset);
2521
2522         /* If other port enables, the function returns "true" */
2523         return tmp & ref_mask;
2524 }
2525
2526 static int sh_eth_tsu_busy(struct net_device *ndev)
2527 {
2528         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2529         struct sh_eth_private *mdp = netdev_priv(ndev);
2530
2531         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2532                 udelay(10);
2533                 timeout--;
2534                 if (timeout <= 0) {
2535                         netdev_err(ndev, "%s: timeout\n", __func__);
2536                         return -ETIMEDOUT;
2537                 }
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2544                                   const u8 *addr)
2545 {
2546         u32 val;
2547
2548         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2549         iowrite32(val, reg);
2550         if (sh_eth_tsu_busy(ndev) < 0)
2551                 return -EBUSY;
2552
2553         val = addr[4] << 8 | addr[5];
2554         iowrite32(val, reg + 4);
2555         if (sh_eth_tsu_busy(ndev) < 0)
2556                 return -EBUSY;
2557
2558         return 0;
2559 }
2560
2561 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2562 {
2563         u32 val;
2564
2565         val = ioread32(reg);
2566         addr[0] = (val >> 24) & 0xff;
2567         addr[1] = (val >> 16) & 0xff;
2568         addr[2] = (val >> 8) & 0xff;
2569         addr[3] = val & 0xff;
2570         val = ioread32(reg + 4);
2571         addr[4] = (val >> 8) & 0xff;
2572         addr[5] = val & 0xff;
2573 }
2574
2575
2576 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2577 {
2578         struct sh_eth_private *mdp = netdev_priv(ndev);
2579         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2580         int i;
2581         u8 c_addr[ETH_ALEN];
2582
2583         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2584                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2585                 if (ether_addr_equal(addr, c_addr))
2586                         return i;
2587         }
2588
2589         return -ENOENT;
2590 }
2591
2592 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2593 {
2594         u8 blank[ETH_ALEN];
2595         int entry;
2596
2597         memset(blank, 0, sizeof(blank));
2598         entry = sh_eth_tsu_find_entry(ndev, blank);
2599         return (entry < 0) ? -ENOMEM : entry;
2600 }
2601
2602 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2603                                               int entry)
2604 {
2605         struct sh_eth_private *mdp = netdev_priv(ndev);
2606         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2607         int ret;
2608         u8 blank[ETH_ALEN];
2609
2610         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2611                          ~(1 << (31 - entry)), TSU_TEN);
2612
2613         memset(blank, 0, sizeof(blank));
2614         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2615         if (ret < 0)
2616                 return ret;
2617         return 0;
2618 }
2619
2620 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2621 {
2622         struct sh_eth_private *mdp = netdev_priv(ndev);
2623         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2624         int i, ret;
2625
2626         if (!mdp->cd->tsu)
2627                 return 0;
2628
2629         i = sh_eth_tsu_find_entry(ndev, addr);
2630         if (i < 0) {
2631                 /* No entry found, create one */
2632                 i = sh_eth_tsu_find_empty(ndev);
2633                 if (i < 0)
2634                         return -ENOMEM;
2635                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2636                 if (ret < 0)
2637                         return ret;
2638
2639                 /* Enable the entry */
2640                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2641                                  (1 << (31 - i)), TSU_TEN);
2642         }
2643
2644         /* Entry found or created, enable POST */
2645         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2646
2647         return 0;
2648 }
2649
2650 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2651 {
2652         struct sh_eth_private *mdp = netdev_priv(ndev);
2653         int i, ret;
2654
2655         if (!mdp->cd->tsu)
2656                 return 0;
2657
2658         i = sh_eth_tsu_find_entry(ndev, addr);
2659         if (i) {
2660                 /* Entry found */
2661                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2662                         goto done;
2663
2664                 /* Disable the entry if both ports was disabled */
2665                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2666                 if (ret < 0)
2667                         return ret;
2668         }
2669 done:
2670         return 0;
2671 }
2672
2673 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2674 {
2675         struct sh_eth_private *mdp = netdev_priv(ndev);
2676         int i, ret;
2677
2678         if (!mdp->cd->tsu)
2679                 return 0;
2680
2681         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2682                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2683                         continue;
2684
2685                 /* Disable the entry if both ports was disabled */
2686                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2687                 if (ret < 0)
2688                         return ret;
2689         }
2690
2691         return 0;
2692 }
2693
2694 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2695 {
2696         struct sh_eth_private *mdp = netdev_priv(ndev);
2697         u8 addr[ETH_ALEN];
2698         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2699         int i;
2700
2701         if (!mdp->cd->tsu)
2702                 return;
2703
2704         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2705                 sh_eth_tsu_read_entry(reg_offset, addr);
2706                 if (is_multicast_ether_addr(addr))
2707                         sh_eth_tsu_del_entry(ndev, addr);
2708         }
2709 }
2710
2711 /* Update promiscuous flag and multicast filter */
2712 static void sh_eth_set_rx_mode(struct net_device *ndev)
2713 {
2714         struct sh_eth_private *mdp = netdev_priv(ndev);
2715         u32 ecmr_bits;
2716         int mcast_all = 0;
2717         unsigned long flags;
2718
2719         spin_lock_irqsave(&mdp->lock, flags);
2720         /* Initial condition is MCT = 1, PRM = 0.
2721          * Depending on ndev->flags, set PRM or clear MCT
2722          */
2723         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2724         if (mdp->cd->tsu)
2725                 ecmr_bits |= ECMR_MCT;
2726
2727         if (!(ndev->flags & IFF_MULTICAST)) {
2728                 sh_eth_tsu_purge_mcast(ndev);
2729                 mcast_all = 1;
2730         }
2731         if (ndev->flags & IFF_ALLMULTI) {
2732                 sh_eth_tsu_purge_mcast(ndev);
2733                 ecmr_bits &= ~ECMR_MCT;
2734                 mcast_all = 1;
2735         }
2736
2737         if (ndev->flags & IFF_PROMISC) {
2738                 sh_eth_tsu_purge_all(ndev);
2739                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2740         } else if (mdp->cd->tsu) {
2741                 struct netdev_hw_addr *ha;
2742                 netdev_for_each_mc_addr(ha, ndev) {
2743                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2744                                 continue;
2745
2746                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2747                                 if (!mcast_all) {
2748                                         sh_eth_tsu_purge_mcast(ndev);
2749                                         ecmr_bits &= ~ECMR_MCT;
2750                                         mcast_all = 1;
2751                                 }
2752                         }
2753                 }
2754         }
2755
2756         /* update the ethernet mode */
2757         sh_eth_write(ndev, ecmr_bits, ECMR);
2758
2759         spin_unlock_irqrestore(&mdp->lock, flags);
2760 }
2761
2762 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2763 {
2764         if (!mdp->port)
2765                 return TSU_VTAG0;
2766         else
2767                 return TSU_VTAG1;
2768 }
2769
2770 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2771                                   __be16 proto, u16 vid)
2772 {
2773         struct sh_eth_private *mdp = netdev_priv(ndev);
2774         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2775
2776         if (unlikely(!mdp->cd->tsu))
2777                 return -EPERM;
2778
2779         /* No filtering if vid = 0 */
2780         if (!vid)
2781                 return 0;
2782
2783         mdp->vlan_num_ids++;
2784
2785         /* The controller has one VLAN tag HW filter. So, if the filter is
2786          * already enabled, the driver disables it and the filte
2787          */
2788         if (mdp->vlan_num_ids > 1) {
2789                 /* disable VLAN filter */
2790                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2791                 return 0;
2792         }
2793
2794         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2795                          vtag_reg_index);
2796
2797         return 0;
2798 }
2799
2800 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2801                                    __be16 proto, u16 vid)
2802 {
2803         struct sh_eth_private *mdp = netdev_priv(ndev);
2804         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2805
2806         if (unlikely(!mdp->cd->tsu))
2807                 return -EPERM;
2808
2809         /* No filtering if vid = 0 */
2810         if (!vid)
2811                 return 0;
2812
2813         mdp->vlan_num_ids--;
2814         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2815
2816         return 0;
2817 }
2818
2819 /* SuperH's TSU register init function */
2820 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2821 {
2822         if (sh_eth_is_rz_fast_ether(mdp)) {
2823                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2824                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2825                                  TSU_FWSLC);    /* Enable POST registers */
2826                 return;
2827         }
2828
2829         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2830         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2831         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2832         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2833         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2834         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2835         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2836         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2837         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2838         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2839         if (sh_eth_is_gether(mdp)) {
2840                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2841                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2842         } else {
2843                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2844                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2845         }
2846         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2847         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2848         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2849         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2850         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2851         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2852         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2853 }
2854
2855 /* MDIO bus release function */
2856 static int sh_mdio_release(struct sh_eth_private *mdp)
2857 {
2858         /* unregister mdio bus */
2859         mdiobus_unregister(mdp->mii_bus);
2860
2861         /* free bitbang info */
2862         free_mdio_bitbang(mdp->mii_bus);
2863
2864         return 0;
2865 }
2866
2867 /* MDIO bus init function */
2868 static int sh_mdio_init(struct sh_eth_private *mdp,
2869                         struct sh_eth_plat_data *pd)
2870 {
2871         int ret;
2872         struct bb_info *bitbang;
2873         struct platform_device *pdev = mdp->pdev;
2874         struct device *dev = &mdp->pdev->dev;
2875
2876         /* create bit control struct for PHY */
2877         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2878         if (!bitbang)
2879                 return -ENOMEM;
2880
2881         /* bitbang init */
2882         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2883         bitbang->set_gate = pd->set_mdio_gate;
2884         bitbang->ctrl.ops = &bb_ops;
2885
2886         /* MII controller setting */
2887         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2888         if (!mdp->mii_bus)
2889                 return -ENOMEM;
2890
2891         /* Hook up MII support for ethtool */
2892         mdp->mii_bus->name = "sh_mii";
2893         mdp->mii_bus->parent = dev;
2894         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2895                  pdev->name, pdev->id);
2896
2897         /* register MDIO bus */
2898         if (dev->of_node) {
2899                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2900         } else {
2901                 if (pd->phy_irq > 0)
2902                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2903
2904                 ret = mdiobus_register(mdp->mii_bus);
2905         }
2906
2907         if (ret)
2908                 goto out_free_bus;
2909
2910         return 0;
2911
2912 out_free_bus:
2913         free_mdio_bitbang(mdp->mii_bus);
2914         return ret;
2915 }
2916
2917 static const u16 *sh_eth_get_register_offset(int register_type)
2918 {
2919         const u16 *reg_offset = NULL;
2920
2921         switch (register_type) {
2922         case SH_ETH_REG_GIGABIT:
2923                 reg_offset = sh_eth_offset_gigabit;
2924                 break;
2925         case SH_ETH_REG_FAST_RZ:
2926                 reg_offset = sh_eth_offset_fast_rz;
2927                 break;
2928         case SH_ETH_REG_FAST_RCAR:
2929                 reg_offset = sh_eth_offset_fast_rcar;
2930                 break;
2931         case SH_ETH_REG_FAST_SH4:
2932                 reg_offset = sh_eth_offset_fast_sh4;
2933                 break;
2934         case SH_ETH_REG_FAST_SH3_SH2:
2935                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2936                 break;
2937         }
2938
2939         return reg_offset;
2940 }
2941
2942 static const struct net_device_ops sh_eth_netdev_ops = {
2943         .ndo_open               = sh_eth_open,
2944         .ndo_stop               = sh_eth_close,
2945         .ndo_start_xmit         = sh_eth_start_xmit,
2946         .ndo_get_stats          = sh_eth_get_stats,
2947         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2948         .ndo_tx_timeout         = sh_eth_tx_timeout,
2949         .ndo_do_ioctl           = sh_eth_do_ioctl,
2950         .ndo_validate_addr      = eth_validate_addr,
2951         .ndo_set_mac_address    = eth_mac_addr,
2952 };
2953
2954 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2955         .ndo_open               = sh_eth_open,
2956         .ndo_stop               = sh_eth_close,
2957         .ndo_start_xmit         = sh_eth_start_xmit,
2958         .ndo_get_stats          = sh_eth_get_stats,
2959         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2960         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2961         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2962         .ndo_tx_timeout         = sh_eth_tx_timeout,
2963         .ndo_do_ioctl           = sh_eth_do_ioctl,
2964         .ndo_validate_addr      = eth_validate_addr,
2965         .ndo_set_mac_address    = eth_mac_addr,
2966 };
2967
2968 #ifdef CONFIG_OF
2969 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2970 {
2971         struct device_node *np = dev->of_node;
2972         struct sh_eth_plat_data *pdata;
2973         const char *mac_addr;
2974
2975         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2976         if (!pdata)
2977                 return NULL;
2978
2979         pdata->phy_interface = of_get_phy_mode(np);
2980
2981         mac_addr = of_get_mac_address(np);
2982         if (mac_addr)
2983                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2984
2985         pdata->no_ether_link =
2986                 of_property_read_bool(np, "renesas,no-ether-link");
2987         pdata->ether_link_active_low =
2988                 of_property_read_bool(np, "renesas,ether-link-active-low");
2989
2990         return pdata;
2991 }
2992
2993 static const struct of_device_id sh_eth_match_table[] = {
2994         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2995         { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2996         { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
2997         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2998         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2999         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3000         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3001         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3002         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3003         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3004         { }
3005 };
3006 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3007 #else
3008 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3009 {
3010         return NULL;
3011 }
3012 #endif
3013
3014 static int sh_eth_drv_probe(struct platform_device *pdev)
3015 {
3016         struct resource *res;
3017         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3018         const struct platform_device_id *id = platform_get_device_id(pdev);
3019         struct sh_eth_private *mdp;
3020         struct net_device *ndev;
3021         int ret, devno;
3022
3023         /* get base addr */
3024         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3025
3026         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3027         if (!ndev)
3028                 return -ENOMEM;
3029
3030         pm_runtime_enable(&pdev->dev);
3031         pm_runtime_get_sync(&pdev->dev);
3032
3033         devno = pdev->id;
3034         if (devno < 0)
3035                 devno = 0;
3036
3037         ret = platform_get_irq(pdev, 0);
3038         if (ret < 0)
3039                 goto out_release;
3040         ndev->irq = ret;
3041
3042         SET_NETDEV_DEV(ndev, &pdev->dev);
3043
3044         mdp = netdev_priv(ndev);
3045         mdp->num_tx_ring = TX_RING_SIZE;
3046         mdp->num_rx_ring = RX_RING_SIZE;
3047         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3048         if (IS_ERR(mdp->addr)) {
3049                 ret = PTR_ERR(mdp->addr);
3050                 goto out_release;
3051         }
3052
3053         /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
3054         mdp->clk = devm_clk_get(&pdev->dev, NULL);
3055         if (IS_ERR(mdp->clk))
3056                 mdp->clk = NULL;
3057
3058         ndev->base_addr = res->start;
3059
3060         spin_lock_init(&mdp->lock);
3061         mdp->pdev = pdev;
3062
3063         if (pdev->dev.of_node)
3064                 pd = sh_eth_parse_dt(&pdev->dev);
3065         if (!pd) {
3066                 dev_err(&pdev->dev, "no platform data\n");
3067                 ret = -EINVAL;
3068                 goto out_release;
3069         }
3070
3071         /* get PHY ID */
3072         mdp->phy_id = pd->phy;
3073         mdp->phy_interface = pd->phy_interface;
3074         mdp->no_ether_link = pd->no_ether_link;
3075         mdp->ether_link_active_low = pd->ether_link_active_low;
3076
3077         /* set cpu data */
3078         if (id)
3079                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3080         else
3081                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3082
3083         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3084         if (!mdp->reg_offset) {
3085                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3086                         mdp->cd->register_type);
3087                 ret = -EINVAL;
3088                 goto out_release;
3089         }
3090         sh_eth_set_default_cpu_data(mdp->cd);
3091
3092         /* set function */
3093         if (mdp->cd->tsu)
3094                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3095         else
3096                 ndev->netdev_ops = &sh_eth_netdev_ops;
3097         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3098         ndev->watchdog_timeo = TX_TIMEOUT;
3099
3100         /* debug message level */
3101         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3102
3103         /* read and set MAC address */
3104         read_mac_address(ndev, pd->mac_addr);
3105         if (!is_valid_ether_addr(ndev->dev_addr)) {
3106                 dev_warn(&pdev->dev,
3107                          "no valid MAC address supplied, using a random one.\n");
3108                 eth_hw_addr_random(ndev);
3109         }
3110
3111         /* ioremap the TSU registers */
3112         if (mdp->cd->tsu) {
3113                 struct resource *rtsu;
3114                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3115                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3116                 if (IS_ERR(mdp->tsu_addr)) {
3117                         ret = PTR_ERR(mdp->tsu_addr);
3118                         goto out_release;
3119                 }
3120                 mdp->port = devno % 2;
3121                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3122         }
3123
3124         /* initialize first or needed device */
3125         if (!devno || pd->needs_init) {
3126                 if (mdp->cd->chip_reset)
3127                         mdp->cd->chip_reset(ndev);
3128
3129                 if (mdp->cd->tsu) {
3130                         /* TSU init (Init only)*/
3131                         sh_eth_tsu_init(mdp);
3132                 }
3133         }
3134
3135         if (mdp->cd->rmiimode)
3136                 sh_eth_write(ndev, 0x1, RMIIMODE);
3137
3138         /* MDIO bus init */
3139         ret = sh_mdio_init(mdp, pd);
3140         if (ret) {
3141                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3142                 goto out_release;
3143         }
3144
3145         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3146
3147         /* network device register */
3148         ret = register_netdev(ndev);
3149         if (ret)
3150                 goto out_napi_del;
3151
3152         if (mdp->cd->magic && mdp->clk)
3153                 device_set_wakeup_capable(&pdev->dev, 1);
3154
3155         /* print device information */
3156         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3157                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3158
3159         pm_runtime_put(&pdev->dev);
3160         platform_set_drvdata(pdev, ndev);
3161
3162         return ret;
3163
3164 out_napi_del:
3165         netif_napi_del(&mdp->napi);
3166         sh_mdio_release(mdp);
3167
3168 out_release:
3169         /* net_dev free */
3170         if (ndev)
3171                 free_netdev(ndev);
3172
3173         pm_runtime_put(&pdev->dev);
3174         pm_runtime_disable(&pdev->dev);
3175         return ret;
3176 }
3177
3178 static int sh_eth_drv_remove(struct platform_device *pdev)
3179 {
3180         struct net_device *ndev = platform_get_drvdata(pdev);
3181         struct sh_eth_private *mdp = netdev_priv(ndev);
3182
3183         unregister_netdev(ndev);
3184         netif_napi_del(&mdp->napi);
3185         sh_mdio_release(mdp);
3186         pm_runtime_disable(&pdev->dev);
3187         free_netdev(ndev);
3188
3189         return 0;
3190 }
3191
3192 #ifdef CONFIG_PM
3193 #ifdef CONFIG_PM_SLEEP
3194 static int sh_eth_wol_setup(struct net_device *ndev)
3195 {
3196         struct sh_eth_private *mdp = netdev_priv(ndev);
3197
3198         /* Only allow ECI interrupts */
3199         synchronize_irq(ndev->irq);
3200         napi_disable(&mdp->napi);
3201         sh_eth_write(ndev, DMAC_M_ECI, EESIPR);
3202
3203         /* Enable MagicPacket */
3204         sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE);
3205
3206         /* Increased clock usage so device won't be suspended */
3207         clk_enable(mdp->clk);
3208
3209         return enable_irq_wake(ndev->irq);
3210 }
3211
3212 static int sh_eth_wol_restore(struct net_device *ndev)
3213 {
3214         struct sh_eth_private *mdp = netdev_priv(ndev);
3215         int ret;
3216
3217         napi_enable(&mdp->napi);
3218
3219         /* Disable MagicPacket */
3220         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3221
3222         /* The device needs to be reset to restore MagicPacket logic
3223          * for next wakeup. If we close and open the device it will
3224          * both be reset and all registers restored. This is what
3225          * happens during suspend and resume without WoL enabled.
3226          */
3227         ret = sh_eth_close(ndev);
3228         if (ret < 0)
3229                 return ret;
3230         ret = sh_eth_open(ndev);
3231         if (ret < 0)
3232                 return ret;
3233
3234         /* Restore clock usage count */
3235         clk_disable(mdp->clk);
3236
3237         return disable_irq_wake(ndev->irq);
3238 }
3239
3240 static int sh_eth_suspend(struct device *dev)
3241 {
3242         struct net_device *ndev = dev_get_drvdata(dev);
3243         struct sh_eth_private *mdp = netdev_priv(ndev);
3244         int ret = 0;
3245
3246         if (!netif_running(ndev))
3247                 return 0;
3248
3249         netif_device_detach(ndev);
3250
3251         if (mdp->wol_enabled)
3252                 ret = sh_eth_wol_setup(ndev);
3253         else
3254                 ret = sh_eth_close(ndev);
3255
3256         return ret;
3257 }
3258
3259 static int sh_eth_resume(struct device *dev)
3260 {
3261         struct net_device *ndev = dev_get_drvdata(dev);
3262         struct sh_eth_private *mdp = netdev_priv(ndev);
3263         int ret = 0;
3264
3265         if (!netif_running(ndev))
3266                 return 0;
3267
3268         if (mdp->wol_enabled)
3269                 ret = sh_eth_wol_restore(ndev);
3270         else
3271                 ret = sh_eth_open(ndev);
3272
3273         if (ret < 0)
3274                 return ret;
3275
3276         netif_device_attach(ndev);
3277
3278         return ret;
3279 }
3280 #endif
3281
3282 static int sh_eth_runtime_nop(struct device *dev)
3283 {
3284         /* Runtime PM callback shared between ->runtime_suspend()
3285          * and ->runtime_resume(). Simply returns success.
3286          *
3287          * This driver re-initializes all registers after
3288          * pm_runtime_get_sync() anyway so there is no need
3289          * to save and restore registers here.
3290          */
3291         return 0;
3292 }
3293
3294 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3295         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3296         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3297 };
3298 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3299 #else
3300 #define SH_ETH_PM_OPS NULL
3301 #endif
3302
3303 static struct platform_device_id sh_eth_id_table[] = {
3304         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3305         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3306         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3307         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3308         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3309         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3310         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3311         { }
3312 };
3313 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3314
3315 static struct platform_driver sh_eth_driver = {
3316         .probe = sh_eth_drv_probe,
3317         .remove = sh_eth_drv_remove,
3318         .id_table = sh_eth_id_table,
3319         .driver = {
3320                    .name = CARDNAME,
3321                    .pm = SH_ETH_PM_OPS,
3322                    .of_match_table = of_match_ptr(sh_eth_match_table),
3323         },
3324 };
3325
3326 module_platform_driver(sh_eth_driver);
3327
3328 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3329 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3330 MODULE_LICENSE("GPL v2");