1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet Switch device driver
4 * Copyright (C) 2022 Renesas Electronics Corporation
10 #include <linux/platform_device.h>
11 #include "rcar_gen4_ptp.h"
13 #define RSWITCH_MAX_NUM_QUEUES 128
15 #define RSWITCH_NUM_PORTS 3
16 #define rswitch_for_each_enabled_port(priv, i) \
17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
18 if (priv->rdev[i]->disabled) \
22 #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \
23 for (i--; i >= 0; i--) \
24 if (priv->rdev[i]->disabled) \
28 #define TX_RING_SIZE 1024
29 #define RX_RING_SIZE 1024
30 #define TS_RING_SIZE (TX_RING_SIZE * RSWITCH_NUM_PORTS)
32 #define PKT_BUF_SZ 1584
33 #define RSWITCH_ALIGN 128
34 #define RSWITCH_MAX_CTAG_PCP 7
36 #define RSWITCH_TIMEOUT_US 100000
38 #define RSWITCH_TOP_OFFSET 0x00008000
39 #define RSWITCH_COMA_OFFSET 0x00009000
40 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
41 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
42 #define RSWITCH_GWCA0_OFFSET 0x00010000
43 #define RSWITCH_GWCA1_OFFSET 0x00012000
45 /* TODO: hardcoded ETHA/GWCA settings for now */
46 #define GWCA_IRQ_RESOURCE_NAME "gwca0_rxtx%d"
47 #define GWCA_IRQ_NAME "rswitch: gwca0_rxtx%d"
48 #define GWCA_NUM_IRQS 8
50 #define AGENT_INDEX_GWCA 3
51 #define GWCA_IPV_NUM 0
52 #define GWRO RSWITCH_GWCA0_OFFSET
54 #define GWCA_TS_IRQ_RESOURCE_NAME "gwca0_rxts0"
55 #define GWCA_TS_IRQ_NAME "rswitch: gwca0_rxts0"
56 #define GWCA_TS_IRQ_BIT BIT(0)
59 #define TPRO RSWITCH_TOP_OFFSET
60 #define CARO RSWITCH_COMA_OFFSET
65 FWTTC0 = FWRO + 0x0010,
66 FWTTC1 = FWRO + 0x0014,
67 FWLBMC = FWRO + 0x0018,
68 FWCEPTC = FWRO + 0x0020,
69 FWCEPRC0 = FWRO + 0x0024,
70 FWCEPRC1 = FWRO + 0x0028,
71 FWCEPRC2 = FWRO + 0x002c,
72 FWCLPTC = FWRO + 0x0030,
73 FWCLPRC = FWRO + 0x0034,
74 FWCMPTC = FWRO + 0x0040,
75 FWEMPTC = FWRO + 0x0044,
76 FWSDMPTC = FWRO + 0x0050,
77 FWSDMPVC = FWRO + 0x0054,
78 FWLBWMC0 = FWRO + 0x0080,
79 FWPC00 = FWRO + 0x0100,
80 FWPC10 = FWRO + 0x0104,
81 FWPC20 = FWRO + 0x0108,
82 FWCTGC00 = FWRO + 0x0400,
83 FWCTGC10 = FWRO + 0x0404,
84 FWCTTC00 = FWRO + 0x0408,
85 FWCTTC10 = FWRO + 0x040c,
86 FWCTTC200 = FWRO + 0x0410,
87 FWCTSC00 = FWRO + 0x0420,
88 FWCTSC10 = FWRO + 0x0424,
89 FWCTSC20 = FWRO + 0x0428,
90 FWCTSC30 = FWRO + 0x042c,
91 FWCTSC40 = FWRO + 0x0430,
92 FWTWBFC0 = FWRO + 0x1000,
93 FWTWBFVC0 = FWRO + 0x1004,
94 FWTHBFC0 = FWRO + 0x1400,
95 FWTHBFV0C0 = FWRO + 0x1404,
96 FWTHBFV1C0 = FWRO + 0x1408,
97 FWFOBFC0 = FWRO + 0x1800,
98 FWFOBFV0C0 = FWRO + 0x1804,
99 FWFOBFV1C0 = FWRO + 0x1808,
100 FWRFC0 = FWRO + 0x1c00,
101 FWRFVC0 = FWRO + 0x1c04,
102 FWCFC0 = FWRO + 0x2000,
103 FWCFMC00 = FWRO + 0x2004,
104 FWIP4SC = FWRO + 0x4008,
105 FWIP6SC = FWRO + 0x4018,
106 FWIP6OC = FWRO + 0x401c,
107 FWL2SC = FWRO + 0x4020,
108 FWSFHEC = FWRO + 0x4030,
109 FWSHCR0 = FWRO + 0x4040,
110 FWSHCR1 = FWRO + 0x4044,
111 FWSHCR2 = FWRO + 0x4048,
112 FWSHCR3 = FWRO + 0x404c,
113 FWSHCR4 = FWRO + 0x4050,
114 FWSHCR5 = FWRO + 0x4054,
115 FWSHCR6 = FWRO + 0x4058,
116 FWSHCR7 = FWRO + 0x405c,
117 FWSHCR8 = FWRO + 0x4060,
118 FWSHCR9 = FWRO + 0x4064,
119 FWSHCR10 = FWRO + 0x4068,
120 FWSHCR11 = FWRO + 0x406c,
121 FWSHCR12 = FWRO + 0x4070,
122 FWSHCR13 = FWRO + 0x4074,
123 FWSHCRR = FWRO + 0x4078,
124 FWLTHHEC = FWRO + 0x4090,
125 FWLTHHC = FWRO + 0x4094,
126 FWLTHTL0 = FWRO + 0x40a0,
127 FWLTHTL1 = FWRO + 0x40a4,
128 FWLTHTL2 = FWRO + 0x40a8,
129 FWLTHTL3 = FWRO + 0x40ac,
130 FWLTHTL4 = FWRO + 0x40b0,
131 FWLTHTL5 = FWRO + 0x40b4,
132 FWLTHTL6 = FWRO + 0x40b8,
133 FWLTHTL7 = FWRO + 0x40bc,
134 FWLTHTL80 = FWRO + 0x40c0,
135 FWLTHTL9 = FWRO + 0x40d0,
136 FWLTHTLR = FWRO + 0x40d4,
137 FWLTHTIM = FWRO + 0x40e0,
138 FWLTHTEM = FWRO + 0x40e4,
139 FWLTHTS0 = FWRO + 0x4100,
140 FWLTHTS1 = FWRO + 0x4104,
141 FWLTHTS2 = FWRO + 0x4108,
142 FWLTHTS3 = FWRO + 0x410c,
143 FWLTHTS4 = FWRO + 0x4110,
144 FWLTHTSR0 = FWRO + 0x4120,
145 FWLTHTSR1 = FWRO + 0x4124,
146 FWLTHTSR2 = FWRO + 0x4128,
147 FWLTHTSR3 = FWRO + 0x412c,
148 FWLTHTSR40 = FWRO + 0x4130,
149 FWLTHTSR5 = FWRO + 0x4140,
150 FWLTHTR = FWRO + 0x4150,
151 FWLTHTRR0 = FWRO + 0x4154,
152 FWLTHTRR1 = FWRO + 0x4158,
153 FWLTHTRR2 = FWRO + 0x415c,
154 FWLTHTRR3 = FWRO + 0x4160,
155 FWLTHTRR4 = FWRO + 0x4164,
156 FWLTHTRR5 = FWRO + 0x4168,
157 FWLTHTRR6 = FWRO + 0x416c,
158 FWLTHTRR7 = FWRO + 0x4170,
159 FWLTHTRR8 = FWRO + 0x4174,
160 FWLTHTRR9 = FWRO + 0x4180,
161 FWLTHTRR10 = FWRO + 0x4190,
162 FWIPHEC = FWRO + 0x4214,
163 FWIPHC = FWRO + 0x4218,
164 FWIPTL0 = FWRO + 0x4220,
165 FWIPTL1 = FWRO + 0x4224,
166 FWIPTL2 = FWRO + 0x4228,
167 FWIPTL3 = FWRO + 0x422c,
168 FWIPTL4 = FWRO + 0x4230,
169 FWIPTL5 = FWRO + 0x4234,
170 FWIPTL6 = FWRO + 0x4238,
171 FWIPTL7 = FWRO + 0x4240,
172 FWIPTL8 = FWRO + 0x4250,
173 FWIPTLR = FWRO + 0x4254,
174 FWIPTIM = FWRO + 0x4260,
175 FWIPTEM = FWRO + 0x4264,
176 FWIPTS0 = FWRO + 0x4270,
177 FWIPTS1 = FWRO + 0x4274,
178 FWIPTS2 = FWRO + 0x4278,
179 FWIPTS3 = FWRO + 0x427c,
180 FWIPTS4 = FWRO + 0x4280,
181 FWIPTSR0 = FWRO + 0x4284,
182 FWIPTSR1 = FWRO + 0x4288,
183 FWIPTSR2 = FWRO + 0x428c,
184 FWIPTSR3 = FWRO + 0x4290,
185 FWIPTSR4 = FWRO + 0x42a0,
186 FWIPTR = FWRO + 0x42b0,
187 FWIPTRR0 = FWRO + 0x42b4,
188 FWIPTRR1 = FWRO + 0x42b8,
189 FWIPTRR2 = FWRO + 0x42bc,
190 FWIPTRR3 = FWRO + 0x42c0,
191 FWIPTRR4 = FWRO + 0x42c4,
192 FWIPTRR5 = FWRO + 0x42c8,
193 FWIPTRR6 = FWRO + 0x42cc,
194 FWIPTRR7 = FWRO + 0x42d0,
195 FWIPTRR8 = FWRO + 0x42e0,
196 FWIPTRR9 = FWRO + 0x42f0,
197 FWIPHLEC = FWRO + 0x4300,
198 FWIPAGUSPC = FWRO + 0x4500,
199 FWIPAGC = FWRO + 0x4504,
200 FWIPAGM0 = FWRO + 0x4510,
201 FWIPAGM1 = FWRO + 0x4514,
202 FWIPAGM2 = FWRO + 0x4518,
203 FWIPAGM3 = FWRO + 0x451c,
204 FWIPAGM4 = FWRO + 0x4520,
205 FWMACHEC = FWRO + 0x4620,
206 FWMACHC = FWRO + 0x4624,
207 FWMACTL0 = FWRO + 0x4630,
208 FWMACTL1 = FWRO + 0x4634,
209 FWMACTL2 = FWRO + 0x4638,
210 FWMACTL3 = FWRO + 0x463c,
211 FWMACTL4 = FWRO + 0x4640,
212 FWMACTL5 = FWRO + 0x4650,
213 FWMACTLR = FWRO + 0x4654,
214 FWMACTIM = FWRO + 0x4660,
215 FWMACTEM = FWRO + 0x4664,
216 FWMACTS0 = FWRO + 0x4670,
217 FWMACTS1 = FWRO + 0x4674,
218 FWMACTSR0 = FWRO + 0x4678,
219 FWMACTSR1 = FWRO + 0x467c,
220 FWMACTSR2 = FWRO + 0x4680,
221 FWMACTSR3 = FWRO + 0x4690,
222 FWMACTR = FWRO + 0x46a0,
223 FWMACTRR0 = FWRO + 0x46a4,
224 FWMACTRR1 = FWRO + 0x46a8,
225 FWMACTRR2 = FWRO + 0x46ac,
226 FWMACTRR3 = FWRO + 0x46b0,
227 FWMACTRR4 = FWRO + 0x46b4,
228 FWMACTRR5 = FWRO + 0x46c0,
229 FWMACTRR6 = FWRO + 0x46d0,
230 FWMACHLEC = FWRO + 0x4700,
231 FWMACAGUSPC = FWRO + 0x4880,
232 FWMACAGC = FWRO + 0x4884,
233 FWMACAGM0 = FWRO + 0x4888,
234 FWMACAGM1 = FWRO + 0x488c,
235 FWVLANTEC = FWRO + 0x4900,
236 FWVLANTL0 = FWRO + 0x4910,
237 FWVLANTL1 = FWRO + 0x4914,
238 FWVLANTL2 = FWRO + 0x4918,
239 FWVLANTL3 = FWRO + 0x4920,
240 FWVLANTL4 = FWRO + 0x4930,
241 FWVLANTLR = FWRO + 0x4934,
242 FWVLANTIM = FWRO + 0x4940,
243 FWVLANTEM = FWRO + 0x4944,
244 FWVLANTS = FWRO + 0x4950,
245 FWVLANTSR0 = FWRO + 0x4954,
246 FWVLANTSR1 = FWRO + 0x4958,
247 FWVLANTSR2 = FWRO + 0x4960,
248 FWVLANTSR3 = FWRO + 0x4970,
249 FWPBFC0 = FWRO + 0x4a00,
250 FWPBFCSDC00 = FWRO + 0x4a04,
251 FWL23URL0 = FWRO + 0x4e00,
252 FWL23URL1 = FWRO + 0x4e04,
253 FWL23URL2 = FWRO + 0x4e08,
254 FWL23URL3 = FWRO + 0x4e0c,
255 FWL23URLR = FWRO + 0x4e10,
256 FWL23UTIM = FWRO + 0x4e20,
257 FWL23URR = FWRO + 0x4e30,
258 FWL23URRR0 = FWRO + 0x4e34,
259 FWL23URRR1 = FWRO + 0x4e38,
260 FWL23URRR2 = FWRO + 0x4e3c,
261 FWL23URRR3 = FWRO + 0x4e40,
262 FWL23URMC0 = FWRO + 0x4f00,
263 FWPMFGC0 = FWRO + 0x5000,
264 FWPGFC0 = FWRO + 0x5100,
265 FWPGFIGSC0 = FWRO + 0x5104,
266 FWPGFENC0 = FWRO + 0x5108,
267 FWPGFENM0 = FWRO + 0x510c,
268 FWPGFCSTC00 = FWRO + 0x5110,
269 FWPGFCSTC10 = FWRO + 0x5114,
270 FWPGFCSTM00 = FWRO + 0x5118,
271 FWPGFCSTM10 = FWRO + 0x511c,
272 FWPGFCTC0 = FWRO + 0x5120,
273 FWPGFCTM0 = FWRO + 0x5124,
274 FWPGFHCC0 = FWRO + 0x5128,
275 FWPGFSM0 = FWRO + 0x512c,
276 FWPGFGC0 = FWRO + 0x5130,
277 FWPGFGL0 = FWRO + 0x5500,
278 FWPGFGL1 = FWRO + 0x5504,
279 FWPGFGLR = FWRO + 0x5518,
280 FWPGFGR = FWRO + 0x5510,
281 FWPGFGRR0 = FWRO + 0x5514,
282 FWPGFGRR1 = FWRO + 0x5518,
283 FWPGFRIM = FWRO + 0x5520,
284 FWPMTRFC0 = FWRO + 0x5600,
285 FWPMTRCBSC0 = FWRO + 0x5604,
286 FWPMTRC0RC0 = FWRO + 0x5608,
287 FWPMTREBSC0 = FWRO + 0x560c,
288 FWPMTREIRC0 = FWRO + 0x5610,
289 FWPMTRFM0 = FWRO + 0x5614,
290 FWFTL0 = FWRO + 0x6000,
291 FWFTL1 = FWRO + 0x6004,
292 FWFTLR = FWRO + 0x6008,
293 FWFTOC = FWRO + 0x6010,
294 FWFTOPC = FWRO + 0x6014,
295 FWFTIM = FWRO + 0x6020,
296 FWFTR = FWRO + 0x6030,
297 FWFTRR0 = FWRO + 0x6034,
298 FWFTRR1 = FWRO + 0x6038,
299 FWFTRR2 = FWRO + 0x603c,
300 FWSEQNGC0 = FWRO + 0x6100,
301 FWSEQNGM0 = FWRO + 0x6104,
302 FWSEQNRC = FWRO + 0x6200,
303 FWCTFDCN0 = FWRO + 0x6300,
304 FWLTHFDCN0 = FWRO + 0x6304,
305 FWIPFDCN0 = FWRO + 0x6308,
306 FWLTWFDCN0 = FWRO + 0x630c,
307 FWPBFDCN0 = FWRO + 0x6310,
308 FWMHLCN0 = FWRO + 0x6314,
309 FWIHLCN0 = FWRO + 0x6318,
310 FWICRDCN0 = FWRO + 0x6500,
311 FWWMRDCN0 = FWRO + 0x6504,
312 FWCTRDCN0 = FWRO + 0x6508,
313 FWLTHRDCN0 = FWRO + 0x650c,
314 FWIPRDCN0 = FWRO + 0x6510,
315 FWLTWRDCN0 = FWRO + 0x6514,
316 FWPBRDCN0 = FWRO + 0x6518,
317 FWPMFDCN0 = FWRO + 0x6700,
318 FWPGFDCN0 = FWRO + 0x6780,
319 FWPMGDCN0 = FWRO + 0x6800,
320 FWPMYDCN0 = FWRO + 0x6804,
321 FWPMRDCN0 = FWRO + 0x6808,
322 FWFRPPCN0 = FWRO + 0x6a00,
323 FWFRDPCN0 = FWRO + 0x6a04,
324 FWEIS00 = FWRO + 0x7900,
325 FWEIE00 = FWRO + 0x7904,
326 FWEID00 = FWRO + 0x7908,
327 FWEIS1 = FWRO + 0x7a00,
328 FWEIE1 = FWRO + 0x7a04,
329 FWEID1 = FWRO + 0x7a08,
330 FWEIS2 = FWRO + 0x7a10,
331 FWEIE2 = FWRO + 0x7a14,
332 FWEID2 = FWRO + 0x7a18,
333 FWEIS3 = FWRO + 0x7a20,
334 FWEIE3 = FWRO + 0x7a24,
335 FWEID3 = FWRO + 0x7a28,
336 FWEIS4 = FWRO + 0x7a30,
337 FWEIE4 = FWRO + 0x7a34,
338 FWEID4 = FWRO + 0x7a38,
339 FWEIS5 = FWRO + 0x7a40,
340 FWEIE5 = FWRO + 0x7a44,
341 FWEID5 = FWRO + 0x7a48,
342 FWEIS60 = FWRO + 0x7a50,
343 FWEIE60 = FWRO + 0x7a54,
344 FWEID60 = FWRO + 0x7a58,
345 FWEIS61 = FWRO + 0x7a60,
346 FWEIE61 = FWRO + 0x7a64,
347 FWEID61 = FWRO + 0x7a68,
348 FWEIS62 = FWRO + 0x7a70,
349 FWEIE62 = FWRO + 0x7a74,
350 FWEID62 = FWRO + 0x7a78,
351 FWEIS63 = FWRO + 0x7a80,
352 FWEIE63 = FWRO + 0x7a84,
353 FWEID63 = FWRO + 0x7a88,
354 FWEIS70 = FWRO + 0x7a90,
355 FWEIE70 = FWRO + 0x7A94,
356 FWEID70 = FWRO + 0x7a98,
357 FWEIS71 = FWRO + 0x7aa0,
358 FWEIE71 = FWRO + 0x7aa4,
359 FWEID71 = FWRO + 0x7aa8,
360 FWEIS72 = FWRO + 0x7ab0,
361 FWEIE72 = FWRO + 0x7ab4,
362 FWEID72 = FWRO + 0x7ab8,
363 FWEIS73 = FWRO + 0x7ac0,
364 FWEIE73 = FWRO + 0x7ac4,
365 FWEID73 = FWRO + 0x7ac8,
366 FWEIS80 = FWRO + 0x7ad0,
367 FWEIE80 = FWRO + 0x7ad4,
368 FWEID80 = FWRO + 0x7ad8,
369 FWEIS81 = FWRO + 0x7ae0,
370 FWEIE81 = FWRO + 0x7ae4,
371 FWEID81 = FWRO + 0x7ae8,
372 FWEIS82 = FWRO + 0x7af0,
373 FWEIE82 = FWRO + 0x7af4,
374 FWEID82 = FWRO + 0x7af8,
375 FWEIS83 = FWRO + 0x7b00,
376 FWEIE83 = FWRO + 0x7b04,
377 FWEID83 = FWRO + 0x7b08,
378 FWMIS0 = FWRO + 0x7c00,
379 FWMIE0 = FWRO + 0x7c04,
380 FWMID0 = FWRO + 0x7c08,
381 FWSCR0 = FWRO + 0x7d00,
382 FWSCR1 = FWRO + 0x7d04,
383 FWSCR2 = FWRO + 0x7d08,
384 FWSCR3 = FWRO + 0x7d0c,
385 FWSCR4 = FWRO + 0x7d10,
386 FWSCR5 = FWRO + 0x7d14,
387 FWSCR6 = FWRO + 0x7d18,
388 FWSCR7 = FWRO + 0x7d1c,
389 FWSCR8 = FWRO + 0x7d20,
390 FWSCR9 = FWRO + 0x7d24,
391 FWSCR10 = FWRO + 0x7d28,
392 FWSCR11 = FWRO + 0x7d2c,
393 FWSCR12 = FWRO + 0x7d30,
394 FWSCR13 = FWRO + 0x7d34,
395 FWSCR14 = FWRO + 0x7d38,
396 FWSCR15 = FWRO + 0x7d3c,
397 FWSCR16 = FWRO + 0x7d40,
398 FWSCR17 = FWRO + 0x7d44,
399 FWSCR18 = FWRO + 0x7d48,
400 FWSCR19 = FWRO + 0x7d4c,
401 FWSCR20 = FWRO + 0x7d50,
402 FWSCR21 = FWRO + 0x7d54,
403 FWSCR22 = FWRO + 0x7d58,
404 FWSCR23 = FWRO + 0x7d5c,
405 FWSCR24 = FWRO + 0x7d60,
406 FWSCR25 = FWRO + 0x7d64,
407 FWSCR26 = FWRO + 0x7d68,
408 FWSCR27 = FWRO + 0x7d6c,
409 FWSCR28 = FWRO + 0x7d70,
410 FWSCR29 = FWRO + 0x7d74,
411 FWSCR30 = FWRO + 0x7d78,
412 FWSCR31 = FWRO + 0x7d7c,
413 FWSCR32 = FWRO + 0x7d80,
414 FWSCR33 = FWRO + 0x7d84,
415 FWSCR34 = FWRO + 0x7d88,
416 FWSCR35 = FWRO + 0x7d8c,
417 FWSCR36 = FWRO + 0x7d90,
418 FWSCR37 = FWRO + 0x7d94,
419 FWSCR38 = FWRO + 0x7d98,
420 FWSCR39 = FWRO + 0x7d9c,
421 FWSCR40 = FWRO + 0x7da0,
422 FWSCR41 = FWRO + 0x7da4,
423 FWSCR42 = FWRO + 0x7da8,
424 FWSCR43 = FWRO + 0x7dac,
425 FWSCR44 = FWRO + 0x7db0,
426 FWSCR45 = FWRO + 0x7db4,
427 FWSCR46 = FWRO + 0x7db8,
429 TPEMIMC0 = TPRO + 0x0000,
430 TPEMIMC1 = TPRO + 0x0004,
431 TPEMIMC2 = TPRO + 0x0008,
432 TPEMIMC3 = TPRO + 0x000c,
433 TPEMIMC4 = TPRO + 0x0010,
434 TPEMIMC5 = TPRO + 0x0014,
435 TPEMIMC60 = TPRO + 0x0080,
436 TPEMIMC70 = TPRO + 0x0100,
437 TSIM = TPRO + 0x0700,
438 TFIM = TPRO + 0x0704,
439 TCIM = TPRO + 0x0708,
440 TGIM0 = TPRO + 0x0710,
441 TGIM1 = TPRO + 0x0714,
442 TEIM0 = TPRO + 0x0720,
443 TEIM1 = TPRO + 0x0724,
444 TEIM2 = TPRO + 0x0728,
446 RIPV = CARO + 0x0000,
448 RCEC = CARO + 0x0008,
449 RCDC = CARO + 0x000c,
450 RSSIS = CARO + 0x0010,
451 RSSIE = CARO + 0x0014,
452 RSSID = CARO + 0x0018,
453 CABPIBWMC = CARO + 0x0020,
454 CABPWMLC = CARO + 0x0040,
455 CABPPFLC0 = CARO + 0x0050,
456 CABPPWMLC0 = CARO + 0x0060,
457 CABPPPFLC00 = CARO + 0x00a0,
458 CABPULC = CARO + 0x0100,
459 CABPIRM = CARO + 0x0140,
460 CABPPCM = CARO + 0x0144,
461 CABPLCM = CARO + 0x0148,
462 CABPCPM = CARO + 0x0180,
463 CABPMCPM = CARO + 0x0200,
464 CARDNM = CARO + 0x0280,
465 CARDMNM = CARO + 0x0284,
466 CARDCN = CARO + 0x0290,
467 CAEIS0 = CARO + 0x0300,
468 CAEIE0 = CARO + 0x0304,
469 CAEID0 = CARO + 0x0308,
470 CAEIS1 = CARO + 0x0310,
471 CAEIE1 = CARO + 0x0314,
472 CAEID1 = CARO + 0x0318,
473 CAMIS0 = CARO + 0x0340,
474 CAMIE0 = CARO + 0x0344,
475 CAMID0 = CARO + 0x0348,
476 CAMIS1 = CARO + 0x0350,
477 CAMIE1 = CARO + 0x0354,
478 CAMID1 = CARO + 0x0358,
479 CASCR = CARO + 0x0380,
481 EAMC = TARO + 0x0000,
482 EAMS = TARO + 0x0004,
483 EAIRC = TARO + 0x0010,
484 EATDQSC = TARO + 0x0014,
485 EATDQC = TARO + 0x0018,
486 EATDQAC = TARO + 0x001c,
487 EATPEC = TARO + 0x0020,
488 EATMFSC0 = TARO + 0x0040,
489 EATDQDC0 = TARO + 0x0060,
490 EATDQM0 = TARO + 0x0080,
491 EATDQMLM0 = TARO + 0x00a0,
492 EACTQC = TARO + 0x0100,
493 EACTDQDC = TARO + 0x0104,
494 EACTDQM = TARO + 0x0108,
495 EACTDQMLM = TARO + 0x010c,
496 EAVCC = TARO + 0x0130,
497 EAVTC = TARO + 0x0134,
498 EATTFC = TARO + 0x0138,
499 EACAEC = TARO + 0x0200,
500 EACC = TARO + 0x0204,
501 EACAIVC0 = TARO + 0x0220,
502 EACAULC0 = TARO + 0x0240,
503 EACOEM = TARO + 0x0260,
504 EACOIVM0 = TARO + 0x0280,
505 EACOULM0 = TARO + 0x02a0,
506 EACGSM = TARO + 0x02c0,
507 EATASC = TARO + 0x0300,
508 EATASENC0 = TARO + 0x0320,
509 EATASCTENC = TARO + 0x0340,
510 EATASENM0 = TARO + 0x0360,
511 EATASCTENM = TARO + 0x0380,
512 EATASCSTC0 = TARO + 0x03a0,
513 EATASCSTC1 = TARO + 0x03a4,
514 EATASCSTM0 = TARO + 0x03a8,
515 EATASCSTM1 = TARO + 0x03ac,
516 EATASCTC = TARO + 0x03b0,
517 EATASCTM = TARO + 0x03b4,
518 EATASGL0 = TARO + 0x03c0,
519 EATASGL1 = TARO + 0x03c4,
520 EATASGLR = TARO + 0x03c8,
521 EATASGR = TARO + 0x03d0,
522 EATASGRR = TARO + 0x03d4,
523 EATASHCC = TARO + 0x03e0,
524 EATASRIRM = TARO + 0x03e4,
525 EATASSM = TARO + 0x03e8,
526 EAUSMFSECN = TARO + 0x0400,
527 EATFECN = TARO + 0x0404,
528 EAFSECN = TARO + 0x0408,
529 EADQOECN = TARO + 0x040c,
530 EADQSECN = TARO + 0x0410,
531 EACKSECN = TARO + 0x0414,
532 EAEIS0 = TARO + 0x0500,
533 EAEIE0 = TARO + 0x0504,
534 EAEID0 = TARO + 0x0508,
535 EAEIS1 = TARO + 0x0510,
536 EAEIE1 = TARO + 0x0514,
537 EAEID1 = TARO + 0x0518,
538 EAEIS2 = TARO + 0x0520,
539 EAEIE2 = TARO + 0x0524,
540 EAEID2 = TARO + 0x0528,
541 EASCR = TARO + 0x0580,
543 MPSM = RMRO + 0x0000,
544 MPIC = RMRO + 0x0004,
545 MPIM = RMRO + 0x0008,
546 MIOC = RMRO + 0x0010,
547 MIOM = RMRO + 0x0014,
548 MXMS = RMRO + 0x0018,
549 MTFFC = RMRO + 0x0020,
550 MTPFC = RMRO + 0x0024,
551 MTPFC2 = RMRO + 0x0028,
552 MTPFC30 = RMRO + 0x0030,
553 MTATC0 = RMRO + 0x0050,
554 MTIM = RMRO + 0x0060,
555 MRGC = RMRO + 0x0080,
556 MRMAC0 = RMRO + 0x0084,
557 MRMAC1 = RMRO + 0x0088,
558 MRAFC = RMRO + 0x008c,
559 MRSCE = RMRO + 0x0090,
560 MRSCP = RMRO + 0x0094,
561 MRSCC = RMRO + 0x0098,
562 MRFSCE = RMRO + 0x009c,
563 MRFSCP = RMRO + 0x00a0,
564 MTRC = RMRO + 0x00a4,
565 MRIM = RMRO + 0x00a8,
566 MRPFM = RMRO + 0x00ac,
567 MPFC0 = RMRO + 0x0100,
568 MLVC = RMRO + 0x0180,
569 MEEEC = RMRO + 0x0184,
570 MLBC = RMRO + 0x0188,
571 MXGMIIC = RMRO + 0x0190,
572 MPCH = RMRO + 0x0194,
573 MANC = RMRO + 0x0198,
574 MANM = RMRO + 0x019c,
575 MPLCA1 = RMRO + 0x01a0,
576 MPLCA2 = RMRO + 0x01a4,
577 MPLCA3 = RMRO + 0x01a8,
578 MPLCA4 = RMRO + 0x01ac,
579 MPLCAM = RMRO + 0x01b0,
580 MHDC1 = RMRO + 0x01c0,
581 MHDC2 = RMRO + 0x01c4,
582 MEIS = RMRO + 0x0200,
583 MEIE = RMRO + 0x0204,
584 MEID = RMRO + 0x0208,
585 MMIS0 = RMRO + 0x0210,
586 MMIE0 = RMRO + 0x0214,
587 MMID0 = RMRO + 0x0218,
588 MMIS1 = RMRO + 0x0220,
589 MMIE1 = RMRO + 0x0224,
590 MMID1 = RMRO + 0x0228,
591 MMIS2 = RMRO + 0x0230,
592 MMIE2 = RMRO + 0x0234,
593 MMID2 = RMRO + 0x0238,
594 MMPFTCT = RMRO + 0x0300,
595 MAPFTCT = RMRO + 0x0304,
596 MPFRCT = RMRO + 0x0308,
597 MFCICT = RMRO + 0x030c,
598 MEEECT = RMRO + 0x0310,
599 MMPCFTCT0 = RMRO + 0x0320,
600 MAPCFTCT0 = RMRO + 0x0330,
601 MPCFRCT0 = RMRO + 0x0340,
602 MHDCC = RMRO + 0x0350,
603 MROVFC = RMRO + 0x0354,
604 MRHCRCEC = RMRO + 0x0358,
605 MRXBCE = RMRO + 0x0400,
606 MRXBCP = RMRO + 0x0404,
607 MRGFCE = RMRO + 0x0408,
608 MRGFCP = RMRO + 0x040c,
609 MRBFC = RMRO + 0x0410,
610 MRMFC = RMRO + 0x0414,
611 MRUFC = RMRO + 0x0418,
612 MRPEFC = RMRO + 0x041c,
613 MRNEFC = RMRO + 0x0420,
614 MRFMEFC = RMRO + 0x0424,
615 MRFFMEFC = RMRO + 0x0428,
616 MRCFCEFC = RMRO + 0x042c,
617 MRFCEFC = RMRO + 0x0430,
618 MRRCFEFC = RMRO + 0x0434,
619 MRUEFC = RMRO + 0x043c,
620 MROEFC = RMRO + 0x0440,
621 MRBOEC = RMRO + 0x0444,
622 MTXBCE = RMRO + 0x0500,
623 MTXBCP = RMRO + 0x0504,
624 MTGFCE = RMRO + 0x0508,
625 MTGFCP = RMRO + 0x050c,
626 MTBFC = RMRO + 0x0510,
627 MTMFC = RMRO + 0x0514,
628 MTUFC = RMRO + 0x0518,
629 MTEFC = RMRO + 0x051c,
631 GWMC = GWRO + 0x0000,
632 GWMS = GWRO + 0x0004,
633 GWIRC = GWRO + 0x0010,
634 GWRDQSC = GWRO + 0x0014,
635 GWRDQC = GWRO + 0x0018,
636 GWRDQAC = GWRO + 0x001c,
637 GWRGC = GWRO + 0x0020,
638 GWRMFSC0 = GWRO + 0x0040,
639 GWRDQDC0 = GWRO + 0x0060,
640 GWRDQM0 = GWRO + 0x0080,
641 GWRDQMLM0 = GWRO + 0x00a0,
642 GWMTIRM = GWRO + 0x0100,
643 GWMSTLS = GWRO + 0x0104,
644 GWMSTLR = GWRO + 0x0108,
645 GWMSTSS = GWRO + 0x010c,
646 GWMSTSR = GWRO + 0x0110,
647 GWMAC0 = GWRO + 0x0120,
648 GWMAC1 = GWRO + 0x0124,
649 GWVCC = GWRO + 0x0130,
650 GWVTC = GWRO + 0x0134,
651 GWTTFC = GWRO + 0x0138,
652 GWTDCAC00 = GWRO + 0x0140,
653 GWTDCAC10 = GWRO + 0x0144,
654 GWTSDCC0 = GWRO + 0x0160,
655 GWTNM = GWRO + 0x0180,
656 GWTMNM = GWRO + 0x0184,
657 GWAC = GWRO + 0x0190,
658 GWDCBAC0 = GWRO + 0x0194,
659 GWDCBAC1 = GWRO + 0x0198,
660 GWIICBSC = GWRO + 0x019c,
661 GWMDNC = GWRO + 0x01a0,
662 GWTRC0 = GWRO + 0x0200,
663 GWTPC0 = GWRO + 0x0300,
664 GWARIRM = GWRO + 0x0380,
665 GWDCC0 = GWRO + 0x0400,
666 GWAARSS = GWRO + 0x0800,
667 GWAARSR0 = GWRO + 0x0804,
668 GWAARSR1 = GWRO + 0x0808,
669 GWIDAUAS0 = GWRO + 0x0840,
670 GWIDASM0 = GWRO + 0x0880,
671 GWIDASAM00 = GWRO + 0x0900,
672 GWIDASAM10 = GWRO + 0x0904,
673 GWIDACAM00 = GWRO + 0x0980,
674 GWIDACAM10 = GWRO + 0x0984,
675 GWGRLC = GWRO + 0x0a00,
676 GWGRLULC = GWRO + 0x0a04,
677 GWRLIVC0 = GWRO + 0x0a80,
678 GWRLULC0 = GWRO + 0x0a84,
679 GWIDPC = GWRO + 0x0b00,
680 GWIDC0 = GWRO + 0x0c00,
681 GWDIS0 = GWRO + 0x1100,
682 GWDIE0 = GWRO + 0x1104,
683 GWDID0 = GWRO + 0x1108,
684 GWTSDIS = GWRO + 0x1180,
685 GWTSDIE = GWRO + 0x1184,
686 GWTSDID = GWRO + 0x1188,
687 GWEIS0 = GWRO + 0x1190,
688 GWEIE0 = GWRO + 0x1194,
689 GWEID0 = GWRO + 0x1198,
690 GWEIS1 = GWRO + 0x11a0,
691 GWEIE1 = GWRO + 0x11a4,
692 GWEID1 = GWRO + 0x11a8,
693 GWEIS20 = GWRO + 0x1200,
694 GWEIE20 = GWRO + 0x1204,
695 GWEID20 = GWRO + 0x1208,
696 GWEIS3 = GWRO + 0x1280,
697 GWEIE3 = GWRO + 0x1284,
698 GWEID3 = GWRO + 0x1288,
699 GWEIS4 = GWRO + 0x1290,
700 GWEIE4 = GWRO + 0x1294,
701 GWEID4 = GWRO + 0x1298,
702 GWEIS5 = GWRO + 0x12a0,
703 GWEIE5 = GWRO + 0x12a4,
704 GWEID5 = GWRO + 0x12a8,
705 GWSCR0 = GWRO + 0x1800,
706 GWSCR1 = GWRO + 0x1900,
710 enum rswitch_etha_mode {
717 #define EAMS_OPS_MASK EAMC_OPC_OPERATION
719 #define EAVCC_VEM_SC_TAG (0x3 << 16)
721 #define MPIC_PIS_MII 0x00
722 #define MPIC_PIS_GMII 0x02
723 #define MPIC_PIS_XGMII 0x04
724 #define MPIC_LSC_SHIFT 3
725 #define MPIC_LSC_100M (1 << MPIC_LSC_SHIFT)
726 #define MPIC_LSC_1G (2 << MPIC_LSC_SHIFT)
727 #define MPIC_LSC_2_5G (3 << MPIC_LSC_SHIFT)
729 #define MDIO_READ_C45 0x03
730 #define MDIO_WRITE_C45 0x01
732 #define MPSM_PSME BIT(0)
733 #define MPSM_MFF_C45 BIT(2)
734 #define MPSM_PRD_SHIFT 16
735 #define MPSM_PRD_MASK GENMASK(31, MPSM_PRD_SHIFT)
737 /* Completion flags */
738 #define MMIS1_PAACS BIT(2) /* Address */
739 #define MMIS1_PWACS BIT(1) /* Write */
740 #define MMIS1_PRACS BIT(0) /* Read */
741 #define MMIS1_CLEAR_FLAGS 0xf
743 #define MPIC_PSMCS_SHIFT 16
744 #define MPIC_PSMCS_MASK GENMASK(22, MPIC_PSMCS_SHIFT)
745 #define MPIC_PSMCS(val) ((val) << MPIC_PSMCS_SHIFT)
747 #define MPIC_PSMHT_SHIFT 24
748 #define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)
749 #define MPIC_PSMHT(val) ((val) << MPIC_PSMHT_SHIFT)
751 #define MLVC_PLV BIT(16)
754 enum rswitch_gwca_mode {
761 #define GWMS_OPS_MASK GWMC_OPC_OPERATION
763 #define GWMTIRM_MTIOG BIT(0)
764 #define GWMTIRM_MTR BIT(1)
766 #define GWVCC_VEM_SC_TAG (0x3 << 16)
768 #define GWARIRM_ARIOG BIT(0)
769 #define GWARIRM_ARR BIT(1)
771 #define GWDCC_BALR BIT(24)
772 #define GWDCC_DCP_MASK GENMASK(18, 16)
773 #define GWDCC_DCP(prio) FIELD_PREP(GWDCC_DCP_MASK, (prio))
774 #define GWDCC_DQT BIT(11)
775 #define GWDCC_ETS BIT(9)
776 #define GWDCC_EDE BIT(8)
778 #define GWTRC(queue) (GWTRC0 + (queue) / 32 * 4)
779 #define GWTPC_PPPL(ipv) BIT(ipv)
780 #define GWDCC_OFFS(queue) (GWDCC0 + (queue) * 4)
782 #define GWDIS(i) (GWDIS0 + (i) * 0x10)
783 #define GWDIE(i) (GWDIE0 + (i) * 0x10)
784 #define GWDID(i) (GWDID0 + (i) * 0x10)
787 #define RRC_RR BIT(0)
789 #define RCEC_ACE_DEFAULT (BIT(0) | BIT(AGENT_INDEX_GWCA))
790 #define RCEC_RCE BIT(16)
791 #define RCDC_RCD BIT(16)
793 #define CABPIRM_BPIOG BIT(0)
794 #define CABPIRM_BPR BIT(1)
796 #define CABPPFLC_INIT_VALUE 0x00800080
799 #define FWPC0_LTHTA BIT(0)
800 #define FWPC0_IP4UE BIT(3)
801 #define FWPC0_IP4TE BIT(4)
802 #define FWPC0_IP4OE BIT(5)
803 #define FWPC0_L2SE BIT(9)
804 #define FWPC0_IP4EA BIT(10)
805 #define FWPC0_IPDSA BIT(12)
806 #define FWPC0_IPHLA BIT(18)
807 #define FWPC0_MACSDA BIT(20)
808 #define FWPC0_MACHLA BIT(26)
809 #define FWPC0_MACHMA BIT(27)
810 #define FWPC0_VLANSA BIT(28)
812 #define FWPC0(i) (FWPC00 + (i) * 0x10)
813 #define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
814 FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
815 FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
816 FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
817 #define FWPC1(i) (FWPC10 + (i) * 0x10)
818 #define FWPC1_DDE BIT(0)
820 #define FWPBFC(i) (FWPBFC0 + (i) * 0x10)
822 #define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)
825 #define TPEMIMC7(queue) (TPEMIMC70 + (queue) * 4)
829 RX_DS = 0x0fff, /* Data size */
830 RX_TR = 0x1000, /* Truncation indication */
831 RX_EI = 0x2000, /* Error indication */
832 RX_PS = 0xc000, /* Padding selection */
835 enum TX_DS_TAGL_BIT {
836 TX_DS = 0x0fff, /* Data size */
837 TX_TAGL = 0xf000, /* Frame tag LSBs */
853 /* HW/SW arbitration */
858 DT_FEMPTY_START = 0x50,
859 DT_FEMPTY_MID = 0x60,
860 DT_FEMPTY_END = 0x70,
863 DIE = 0x08, /* Descriptor Interrupt Enable */
866 /* Both transmission and reception */
867 #define INFO1_FMT BIT(2)
868 #define INFO1_TXC BIT(3)
870 /* For transmission */
871 #define INFO1_TSUN(val) ((u64)(val) << 8ULL)
872 #define INFO1_IPV(prio) ((u64)(prio) << 28ULL)
873 #define INFO1_CSD0(index) ((u64)(index) << 32ULL)
874 #define INFO1_CSD1(index) ((u64)(index) << 40ULL)
875 #define INFO1_DV(port_vector) ((u64)(port_vector) << 48ULL)
878 #define INFO1_SPN(port) ((u64)(port) << 36ULL)
880 /* For timestamp descriptor in dptrl (Byte 4 to 7) */
881 #define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0))
882 #define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8)
883 #define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16)
884 #define TS_DESC_TN(dptrl) ((dptrl) & BIT(24))
886 struct rswitch_desc {
887 __le16 info_ds; /* Descriptor size */
888 u8 die_dt; /* Descriptor interrupt enable and type */
889 __u8 dptrh; /* Descriptor pointer MSB */
890 __le32 dptrl; /* Descriptor pointer LSW */
893 struct rswitch_ts_desc {
894 struct rswitch_desc desc;
899 struct rswitch_ext_desc {
900 struct rswitch_desc desc;
904 struct rswitch_ext_ts_desc {
905 struct rswitch_desc desc;
911 struct rswitch_etha {
914 void __iomem *coma_addr;
917 phy_interface_t phy_interface;
918 u8 mac_addr[MAX_ADDR_LEN];
922 /* This hardware could not be initialized twice so that marked
923 * this flag to avoid multiple initialization.
928 /* The datasheet said descriptor "chain" and/or "queue". For consistency of
929 * name, this driver calls "queue".
931 struct rswitch_gwca_queue {
933 struct rswitch_ext_desc *tx_ring;
934 struct rswitch_ext_ts_desc *rx_ring;
935 struct rswitch_ts_desc *ts_ring;
947 struct sk_buff **skbs;
948 struct net_device *ndev; /* queue to ndev for irq */
951 struct rswitch_gwca_ts_info {
953 struct list_head list;
959 #define RSWITCH_NUM_IRQ_REGS (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))
960 struct rswitch_gwca {
962 struct rswitch_desc *linkfix_table;
963 dma_addr_t linkfix_table_dma;
964 u32 linkfix_table_size;
965 struct rswitch_gwca_queue *queues;
967 struct rswitch_gwca_queue ts_queue;
968 struct list_head ts_info_list;
969 DECLARE_BITMAP(used, RSWITCH_MAX_NUM_QUEUES);
970 u32 tx_irq_bits[RSWITCH_NUM_IRQ_REGS];
971 u32 rx_irq_bits[RSWITCH_NUM_IRQ_REGS];
975 #define NUM_QUEUES_PER_NDEV 2
976 struct rswitch_device {
977 struct rswitch_private *priv;
978 struct net_device *ndev;
979 struct napi_struct napi;
981 struct rswitch_gwca_queue *tx_queue;
982 struct rswitch_gwca_queue *rx_queue;
987 struct rswitch_etha *etha;
988 struct device_node *np_port;
992 struct rswitch_mfwd_mac_table_entry {
994 unsigned char addr[MAX_ADDR_LEN];
997 struct rswitch_mfwd {
998 struct rswitch_mac_table_entry *mac_table_entries;
999 int num_mac_table_entries;
1002 struct rswitch_private {
1003 struct platform_device *pdev;
1005 struct rcar_gen4_ptp_private *ptp_priv;
1007 struct rswitch_device *rdev[RSWITCH_NUM_PORTS];
1008 DECLARE_BITMAP(opened_ports, RSWITCH_NUM_PORTS);
1010 struct rswitch_gwca gwca;
1011 struct rswitch_etha etha[RSWITCH_NUM_PORTS];
1012 struct rswitch_mfwd mfwd;
1014 spinlock_t lock; /* lock interrupt registers' control */
1016 bool etha_no_runtime_change;
1020 #endif /* #ifndef __RSWITCH_H__ */