1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32 #include <linux/reset.h>
33 #include <linux/math64.h>
37 #define RAVB_DEF_MSG_ENABLE \
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
71 static int ravb_config(struct net_device *ndev)
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
80 netdev_err(ndev, "failed to switch device to config mode\n");
85 static void ravb_set_rate_gbeth(struct net_device *ndev)
87 struct ravb_private *priv = netdev_priv(ndev);
89 switch (priv->speed) {
91 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
93 case 100: /* 100BASE */
94 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
96 case 1000: /* 1000BASE */
97 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
102 static void ravb_set_rate_rcar(struct net_device *ndev)
104 struct ravb_private *priv = netdev_priv(ndev);
106 switch (priv->speed) {
107 case 100: /* 100BASE */
108 ravb_write(ndev, GECMR_SPEED_100, GECMR);
110 case 1000: /* 1000BASE */
111 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
116 static void ravb_set_buffer_align(struct sk_buff *skb)
118 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
121 skb_reserve(skb, RAVB_ALIGN - reserve);
124 /* Get MAC address from the MAC address registers
126 * Ethernet AVB device doesn't have ROM for MAC address.
127 * This function gets the MAC address that was used by a bootloader.
129 static void ravb_read_mac_address(struct device_node *np,
130 struct net_device *ndev)
134 ret = of_get_ethdev_address(np, ndev);
136 u32 mahr = ravb_read(ndev, MAHR);
137 u32 malr = ravb_read(ndev, MALR);
140 addr[0] = (mahr >> 24) & 0xFF;
141 addr[1] = (mahr >> 16) & 0xFF;
142 addr[2] = (mahr >> 8) & 0xFF;
143 addr[3] = (mahr >> 0) & 0xFF;
144 addr[4] = (malr >> 8) & 0xFF;
145 addr[5] = (malr >> 0) & 0xFF;
146 eth_hw_addr_set(ndev, addr);
150 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
152 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
155 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
158 /* MDC pin control */
159 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
161 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
164 /* Data I/O pin control */
165 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
167 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
171 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
173 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
177 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
179 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
182 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
185 /* MDIO bus control struct */
186 static const struct mdiobb_ops bb_ops = {
187 .owner = THIS_MODULE,
188 .set_mdc = ravb_set_mdc,
189 .set_mdio_dir = ravb_set_mdio_dir,
190 .set_mdio_data = ravb_set_mdio_data,
191 .get_mdio_data = ravb_get_mdio_data,
194 /* Free TX skb function for AVB-IP */
195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
197 struct ravb_private *priv = netdev_priv(ndev);
198 struct net_device_stats *stats = &priv->stats[q];
199 unsigned int num_tx_desc = priv->num_tx_desc;
200 struct ravb_tx_desc *desc;
205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
210 desc = &priv->tx_ring[q][entry];
211 txed = desc->die_dt == DT_FEMPTY;
212 if (free_txed_only && !txed)
214 /* Descriptor type must be checked before all other reads */
216 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
217 /* Free the original skb. */
218 if (priv->tx_skb[q][entry / num_tx_desc]) {
219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
220 size, DMA_TO_DEVICE);
221 /* Last packet descriptor? */
222 if (entry % num_tx_desc == num_tx_desc - 1) {
223 entry /= num_tx_desc;
224 dev_kfree_skb_any(priv->tx_skb[q][entry]);
225 priv->tx_skb[q][entry] = NULL;
232 stats->tx_bytes += size;
233 desc->die_dt = DT_EEMPTY;
238 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
240 struct ravb_private *priv = netdev_priv(ndev);
241 unsigned int ring_size;
244 if (!priv->gbeth_rx_ring)
247 for (i = 0; i < priv->num_rx_ring[q]; i++) {
248 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
250 if (!dma_mapping_error(ndev->dev.parent,
251 le32_to_cpu(desc->dptr)))
252 dma_unmap_single(ndev->dev.parent,
253 le32_to_cpu(desc->dptr),
257 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
258 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
259 priv->rx_desc_dma[q]);
260 priv->gbeth_rx_ring = NULL;
263 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
265 struct ravb_private *priv = netdev_priv(ndev);
266 unsigned int ring_size;
269 if (!priv->rx_ring[q])
272 for (i = 0; i < priv->num_rx_ring[q]; i++) {
273 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
275 if (!dma_mapping_error(ndev->dev.parent,
276 le32_to_cpu(desc->dptr)))
277 dma_unmap_single(ndev->dev.parent,
278 le32_to_cpu(desc->dptr),
282 ring_size = sizeof(struct ravb_ex_rx_desc) *
283 (priv->num_rx_ring[q] + 1);
284 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
285 priv->rx_desc_dma[q]);
286 priv->rx_ring[q] = NULL;
289 /* Free skb's and DMA buffers for Ethernet AVB */
290 static void ravb_ring_free(struct net_device *ndev, int q)
292 struct ravb_private *priv = netdev_priv(ndev);
293 const struct ravb_hw_info *info = priv->info;
294 unsigned int num_tx_desc = priv->num_tx_desc;
295 unsigned int ring_size;
298 info->rx_ring_free(ndev, q);
300 if (priv->tx_ring[q]) {
301 ravb_tx_free(ndev, q, false);
303 ring_size = sizeof(struct ravb_tx_desc) *
304 (priv->num_tx_ring[q] * num_tx_desc + 1);
305 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
306 priv->tx_desc_dma[q]);
307 priv->tx_ring[q] = NULL;
310 /* Free RX skb ringbuffer */
311 if (priv->rx_skb[q]) {
312 for (i = 0; i < priv->num_rx_ring[q]; i++)
313 dev_kfree_skb(priv->rx_skb[q][i]);
315 kfree(priv->rx_skb[q]);
316 priv->rx_skb[q] = NULL;
318 /* Free aligned TX buffers */
319 kfree(priv->tx_align[q]);
320 priv->tx_align[q] = NULL;
322 /* Free TX skb ringbuffer.
323 * SKBs are freed by ravb_tx_free() call above.
325 kfree(priv->tx_skb[q]);
326 priv->tx_skb[q] = NULL;
329 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
331 struct ravb_private *priv = netdev_priv(ndev);
332 struct ravb_rx_desc *rx_desc;
333 unsigned int rx_ring_size;
337 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
338 memset(priv->gbeth_rx_ring, 0, rx_ring_size);
339 /* Build RX ring buffer */
340 for (i = 0; i < priv->num_rx_ring[q]; i++) {
342 rx_desc = &priv->gbeth_rx_ring[i];
343 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
344 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
347 /* We just set the data size to 0 for a failed mapping which
348 * should prevent DMA from happening...
350 if (dma_mapping_error(ndev->dev.parent, dma_addr))
351 rx_desc->ds_cc = cpu_to_le16(0);
352 rx_desc->dptr = cpu_to_le32(dma_addr);
353 rx_desc->die_dt = DT_FEMPTY;
355 rx_desc = &priv->gbeth_rx_ring[i];
356 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
357 rx_desc->die_dt = DT_LINKFIX; /* type */
360 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
362 struct ravb_private *priv = netdev_priv(ndev);
363 struct ravb_ex_rx_desc *rx_desc;
364 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
368 memset(priv->rx_ring[q], 0, rx_ring_size);
369 /* Build RX ring buffer */
370 for (i = 0; i < priv->num_rx_ring[q]; i++) {
372 rx_desc = &priv->rx_ring[q][i];
373 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
374 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
377 /* We just set the data size to 0 for a failed mapping which
378 * should prevent DMA from happening...
380 if (dma_mapping_error(ndev->dev.parent, dma_addr))
381 rx_desc->ds_cc = cpu_to_le16(0);
382 rx_desc->dptr = cpu_to_le32(dma_addr);
383 rx_desc->die_dt = DT_FEMPTY;
385 rx_desc = &priv->rx_ring[q][i];
386 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
387 rx_desc->die_dt = DT_LINKFIX; /* type */
390 /* Format skb and descriptor buffer for Ethernet AVB */
391 static void ravb_ring_format(struct net_device *ndev, int q)
393 struct ravb_private *priv = netdev_priv(ndev);
394 const struct ravb_hw_info *info = priv->info;
395 unsigned int num_tx_desc = priv->num_tx_desc;
396 struct ravb_tx_desc *tx_desc;
397 struct ravb_desc *desc;
398 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
404 priv->dirty_rx[q] = 0;
405 priv->dirty_tx[q] = 0;
407 info->rx_ring_format(ndev, q);
409 memset(priv->tx_ring[q], 0, tx_ring_size);
410 /* Build TX ring buffer */
411 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
413 tx_desc->die_dt = DT_EEMPTY;
414 if (num_tx_desc > 1) {
416 tx_desc->die_dt = DT_EEMPTY;
419 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
420 tx_desc->die_dt = DT_LINKFIX; /* type */
422 /* RX descriptor base address for best effort */
423 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
424 desc->die_dt = DT_LINKFIX; /* type */
425 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
427 /* TX descriptor base address for best effort */
428 desc = &priv->desc_bat[q];
429 desc->die_dt = DT_LINKFIX; /* type */
430 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
433 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
435 struct ravb_private *priv = netdev_priv(ndev);
436 unsigned int ring_size;
438 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
440 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
441 &priv->rx_desc_dma[q],
443 return priv->gbeth_rx_ring;
446 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
448 struct ravb_private *priv = netdev_priv(ndev);
449 unsigned int ring_size;
451 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
453 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
454 &priv->rx_desc_dma[q],
456 return priv->rx_ring[q];
459 /* Init skb and descriptor buffer for Ethernet AVB */
460 static int ravb_ring_init(struct net_device *ndev, int q)
462 struct ravb_private *priv = netdev_priv(ndev);
463 const struct ravb_hw_info *info = priv->info;
464 unsigned int num_tx_desc = priv->num_tx_desc;
465 unsigned int ring_size;
469 /* Allocate RX and TX skb rings */
470 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
471 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
472 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
473 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
474 if (!priv->rx_skb[q] || !priv->tx_skb[q])
477 for (i = 0; i < priv->num_rx_ring[q]; i++) {
478 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
481 ravb_set_buffer_align(skb);
482 priv->rx_skb[q][i] = skb;
485 if (num_tx_desc > 1) {
486 /* Allocate rings for the aligned buffers */
487 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
488 DPTR_ALIGN - 1, GFP_KERNEL);
489 if (!priv->tx_align[q])
493 /* Allocate all RX descriptors. */
494 if (!info->alloc_rx_desc(ndev, q))
497 priv->dirty_rx[q] = 0;
499 /* Allocate all TX descriptors. */
500 ring_size = sizeof(struct ravb_tx_desc) *
501 (priv->num_tx_ring[q] * num_tx_desc + 1);
502 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
503 &priv->tx_desc_dma[q],
505 if (!priv->tx_ring[q])
511 ravb_ring_free(ndev, q);
516 static void ravb_emac_init_gbeth(struct net_device *ndev)
518 struct ravb_private *priv = netdev_priv(ndev);
520 /* Receive frame limit set register */
521 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
523 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
524 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
525 ECMR_TE | ECMR_RE | ECMR_RCPT |
526 ECMR_TXF | ECMR_RXF, ECMR);
528 ravb_set_rate_gbeth(ndev);
530 /* Set MAC address */
532 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
533 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
534 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
536 /* E-MAC status register clear */
537 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
538 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
540 /* E-MAC interrupt enable register */
541 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
543 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
544 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
545 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
547 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
552 static void ravb_emac_init_rcar(struct net_device *ndev)
554 /* Receive frame limit set register */
555 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
557 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
558 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
559 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
560 ECMR_TE | ECMR_RE, ECMR);
562 ravb_set_rate_rcar(ndev);
564 /* Set MAC address */
566 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
567 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
569 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
571 /* E-MAC status register clear */
572 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
574 /* E-MAC interrupt enable register */
575 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
578 /* E-MAC init function */
579 static void ravb_emac_init(struct net_device *ndev)
581 struct ravb_private *priv = netdev_priv(ndev);
582 const struct ravb_hw_info *info = priv->info;
584 info->emac_init(ndev);
587 static int ravb_dmac_init_gbeth(struct net_device *ndev)
591 error = ravb_ring_init(ndev, RAVB_BE);
595 /* Descriptor format */
596 ravb_ring_format(ndev, RAVB_BE);
599 ravb_write(ndev, 0x60000000, RCR);
601 /* Set Max Frame Length (RTC) */
602 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
605 ravb_write(ndev, 0x00222200, TGC);
607 ravb_write(ndev, 0, TCCR);
610 ravb_write(ndev, RIC0_FRE0, RIC0);
611 /* Disable FIFO full warning */
612 ravb_write(ndev, 0x0, RIC1);
613 /* Receive FIFO full error, descriptor empty */
614 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
616 ravb_write(ndev, TIC_FTE0, TIC);
621 static int ravb_dmac_init_rcar(struct net_device *ndev)
623 struct ravb_private *priv = netdev_priv(ndev);
624 const struct ravb_hw_info *info = priv->info;
627 error = ravb_ring_init(ndev, RAVB_BE);
630 error = ravb_ring_init(ndev, RAVB_NC);
632 ravb_ring_free(ndev, RAVB_BE);
636 /* Descriptor format */
637 ravb_ring_format(ndev, RAVB_BE);
638 ravb_ring_format(ndev, RAVB_NC);
642 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
645 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
647 /* Timestamp enable */
648 ravb_write(ndev, TCCR_TFEN, TCCR);
650 /* Interrupt init: */
651 if (info->multi_irqs) {
653 ravb_write(ndev, 0, DIL);
654 /* Set queue specific interrupt */
655 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
658 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
659 /* Disable FIFO full warning */
660 ravb_write(ndev, 0, RIC1);
661 /* Receive FIFO full error, descriptor empty */
662 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
663 /* Frame transmitted, timestamp FIFO updated */
664 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
669 /* Device init function for Ethernet AVB */
670 static int ravb_dmac_init(struct net_device *ndev)
672 struct ravb_private *priv = netdev_priv(ndev);
673 const struct ravb_hw_info *info = priv->info;
676 /* Set CONFIG mode */
677 error = ravb_config(ndev);
681 error = info->dmac_init(ndev);
685 /* Setting the control will start the AVB-DMAC process. */
686 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
691 static void ravb_get_tx_tstamp(struct net_device *ndev)
693 struct ravb_private *priv = netdev_priv(ndev);
694 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
695 struct skb_shared_hwtstamps shhwtstamps;
697 struct timespec64 ts;
702 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
704 tfa2 = ravb_read(ndev, TFA2);
705 tfa_tag = (tfa2 & TFA2_TST) >> 16;
706 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
707 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
708 ravb_read(ndev, TFA1);
709 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
710 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
711 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
715 list_del(&ts_skb->list);
717 if (tag == tfa_tag) {
718 skb_tstamp_tx(skb, &shhwtstamps);
719 dev_consume_skb_any(skb);
722 dev_kfree_skb_any(skb);
725 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
729 static void ravb_rx_csum(struct sk_buff *skb)
733 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
734 * appended to packet data
736 if (unlikely(skb->len < sizeof(__sum16)))
738 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
739 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
740 skb->ip_summed = CHECKSUM_COMPLETE;
741 skb_trim(skb, skb->len - sizeof(__sum16));
744 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
745 struct ravb_rx_desc *desc)
747 struct ravb_private *priv = netdev_priv(ndev);
750 skb = priv->rx_skb[RAVB_BE][entry];
751 priv->rx_skb[RAVB_BE][entry] = NULL;
752 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
753 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
758 /* Packet receive function for Gigabit Ethernet */
759 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
761 struct ravb_private *priv = netdev_priv(ndev);
762 const struct ravb_hw_info *info = priv->info;
763 struct net_device_stats *stats;
764 struct ravb_rx_desc *desc;
774 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
775 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
776 stats = &priv->stats[q];
778 boguscnt = min(boguscnt, *quota);
780 desc = &priv->gbeth_rx_ring[entry];
781 while (desc->die_dt != DT_FEMPTY) {
782 /* Descriptor type must be checked before all other reads */
784 desc_status = desc->msc;
785 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
790 /* We use 0-byte descriptors to mark the DMA mapping errors */
794 if (desc_status & MSC_MC)
797 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
799 if (desc_status & MSC_CRC)
800 stats->rx_crc_errors++;
801 if (desc_status & MSC_RFE)
802 stats->rx_frame_errors++;
803 if (desc_status & (MSC_RTLF | MSC_RTSF))
804 stats->rx_length_errors++;
805 if (desc_status & MSC_CEEF)
806 stats->rx_missed_errors++;
808 die_dt = desc->die_dt & 0xF0;
811 skb = ravb_get_skb_gbeth(ndev, entry, desc);
812 skb_put(skb, pkt_len);
813 skb->protocol = eth_type_trans(skb, ndev);
814 napi_gro_receive(&priv->napi[q], skb);
816 stats->rx_bytes += pkt_len;
819 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
820 skb_put(priv->rx_1st_skb, pkt_len);
823 skb = ravb_get_skb_gbeth(ndev, entry, desc);
824 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
825 priv->rx_1st_skb->len,
828 skb_put(priv->rx_1st_skb, pkt_len);
832 skb = ravb_get_skb_gbeth(ndev, entry, desc);
833 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
834 priv->rx_1st_skb->len,
837 skb_put(priv->rx_1st_skb, pkt_len);
839 priv->rx_1st_skb->protocol =
840 eth_type_trans(priv->rx_1st_skb, ndev);
841 napi_gro_receive(&priv->napi[q],
844 stats->rx_bytes += priv->rx_1st_skb->len;
849 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
850 desc = &priv->gbeth_rx_ring[entry];
853 /* Refill the RX ring buffers. */
854 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
855 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
856 desc = &priv->gbeth_rx_ring[entry];
857 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
859 if (!priv->rx_skb[q][entry]) {
860 skb = netdev_alloc_skb(ndev, info->max_rx_len);
863 ravb_set_buffer_align(skb);
864 dma_addr = dma_map_single(ndev->dev.parent,
868 skb_checksum_none_assert(skb);
869 /* We just set the data size to 0 for a failed mapping
870 * which should prevent DMA from happening...
872 if (dma_mapping_error(ndev->dev.parent, dma_addr))
873 desc->ds_cc = cpu_to_le16(0);
874 desc->dptr = cpu_to_le32(dma_addr);
875 priv->rx_skb[q][entry] = skb;
877 /* Descriptor type must be set after all the above writes */
879 desc->die_dt = DT_FEMPTY;
882 *quota -= limit - (++boguscnt);
884 return boguscnt <= 0;
887 /* Packet receive function for Ethernet AVB */
888 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
890 struct ravb_private *priv = netdev_priv(ndev);
891 const struct ravb_hw_info *info = priv->info;
892 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
893 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
895 struct net_device_stats *stats = &priv->stats[q];
896 struct ravb_ex_rx_desc *desc;
899 struct timespec64 ts;
904 boguscnt = min(boguscnt, *quota);
906 desc = &priv->rx_ring[q][entry];
907 while (desc->die_dt != DT_FEMPTY) {
908 /* Descriptor type must be checked before all other reads */
910 desc_status = desc->msc;
911 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
916 /* We use 0-byte descriptors to mark the DMA mapping errors */
920 if (desc_status & MSC_MC)
923 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
926 if (desc_status & MSC_CRC)
927 stats->rx_crc_errors++;
928 if (desc_status & MSC_RFE)
929 stats->rx_frame_errors++;
930 if (desc_status & (MSC_RTLF | MSC_RTSF))
931 stats->rx_length_errors++;
932 if (desc_status & MSC_CEEF)
933 stats->rx_missed_errors++;
935 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
937 skb = priv->rx_skb[q][entry];
938 priv->rx_skb[q][entry] = NULL;
939 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
942 get_ts &= (q == RAVB_NC) ?
943 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
944 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
946 struct skb_shared_hwtstamps *shhwtstamps;
948 shhwtstamps = skb_hwtstamps(skb);
949 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
950 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
951 32) | le32_to_cpu(desc->ts_sl);
952 ts.tv_nsec = le32_to_cpu(desc->ts_n);
953 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
956 skb_put(skb, pkt_len);
957 skb->protocol = eth_type_trans(skb, ndev);
958 if (ndev->features & NETIF_F_RXCSUM)
960 napi_gro_receive(&priv->napi[q], skb);
962 stats->rx_bytes += pkt_len;
965 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
966 desc = &priv->rx_ring[q][entry];
969 /* Refill the RX ring buffers. */
970 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
971 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
972 desc = &priv->rx_ring[q][entry];
973 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
975 if (!priv->rx_skb[q][entry]) {
976 skb = netdev_alloc_skb(ndev, info->max_rx_len);
978 break; /* Better luck next round. */
979 ravb_set_buffer_align(skb);
980 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
981 le16_to_cpu(desc->ds_cc),
983 skb_checksum_none_assert(skb);
984 /* We just set the data size to 0 for a failed mapping
985 * which should prevent DMA from happening...
987 if (dma_mapping_error(ndev->dev.parent, dma_addr))
988 desc->ds_cc = cpu_to_le16(0);
989 desc->dptr = cpu_to_le32(dma_addr);
990 priv->rx_skb[q][entry] = skb;
992 /* Descriptor type must be set after all the above writes */
994 desc->die_dt = DT_FEMPTY;
997 *quota -= limit - (++boguscnt);
999 return boguscnt <= 0;
1002 /* Packet receive function for Ethernet AVB */
1003 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1005 struct ravb_private *priv = netdev_priv(ndev);
1006 const struct ravb_hw_info *info = priv->info;
1008 return info->receive(ndev, quota, q);
1011 static void ravb_rcv_snd_disable(struct net_device *ndev)
1013 /* Disable TX and RX */
1014 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1017 static void ravb_rcv_snd_enable(struct net_device *ndev)
1019 /* Enable TX and RX */
1020 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1023 /* function for waiting dma process finished */
1024 static int ravb_stop_dma(struct net_device *ndev)
1026 struct ravb_private *priv = netdev_priv(ndev);
1027 const struct ravb_hw_info *info = priv->info;
1030 /* Wait for stopping the hardware TX process */
1031 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1036 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1041 /* Stop the E-MAC's RX/TX processes. */
1042 ravb_rcv_snd_disable(ndev);
1044 /* Wait for stopping the RX DMA process */
1045 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1049 /* Stop AVB-DMAC process */
1050 return ravb_config(ndev);
1053 /* E-MAC interrupt handler */
1054 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1056 struct ravb_private *priv = netdev_priv(ndev);
1059 ecsr = ravb_read(ndev, ECSR);
1060 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1062 if (ecsr & ECSR_MPD)
1063 pm_wakeup_event(&priv->pdev->dev, 0);
1064 if (ecsr & ECSR_ICD)
1065 ndev->stats.tx_carrier_errors++;
1066 if (ecsr & ECSR_LCHNG) {
1068 if (priv->no_avb_link)
1070 psr = ravb_read(ndev, PSR);
1071 if (priv->avb_link_active_low)
1073 if (!(psr & PSR_LMON)) {
1074 /* DIsable RX and TX */
1075 ravb_rcv_snd_disable(ndev);
1077 /* Enable RX and TX */
1078 ravb_rcv_snd_enable(ndev);
1083 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1085 struct net_device *ndev = dev_id;
1086 struct ravb_private *priv = netdev_priv(ndev);
1088 spin_lock(&priv->lock);
1089 ravb_emac_interrupt_unlocked(ndev);
1090 spin_unlock(&priv->lock);
1094 /* Error interrupt handler */
1095 static void ravb_error_interrupt(struct net_device *ndev)
1097 struct ravb_private *priv = netdev_priv(ndev);
1100 eis = ravb_read(ndev, EIS);
1101 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1102 if (eis & EIS_QFS) {
1103 ris2 = ravb_read(ndev, RIS2);
1104 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
1107 /* Receive Descriptor Empty int */
1108 if (ris2 & RIS2_QFF0)
1109 priv->stats[RAVB_BE].rx_over_errors++;
1111 /* Receive Descriptor Empty int */
1112 if (ris2 & RIS2_QFF1)
1113 priv->stats[RAVB_NC].rx_over_errors++;
1115 /* Receive FIFO Overflow int */
1116 if (ris2 & RIS2_RFFF)
1117 priv->rx_fifo_errors++;
1121 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1123 struct ravb_private *priv = netdev_priv(ndev);
1124 const struct ravb_hw_info *info = priv->info;
1125 u32 ris0 = ravb_read(ndev, RIS0);
1126 u32 ric0 = ravb_read(ndev, RIC0);
1127 u32 tis = ravb_read(ndev, TIS);
1128 u32 tic = ravb_read(ndev, TIC);
1130 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1131 if (napi_schedule_prep(&priv->napi[q])) {
1132 /* Mask RX and TX interrupts */
1133 if (!info->irq_en_dis) {
1134 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1135 ravb_write(ndev, tic & ~BIT(q), TIC);
1137 ravb_write(ndev, BIT(q), RID0);
1138 ravb_write(ndev, BIT(q), TID);
1140 __napi_schedule(&priv->napi[q]);
1143 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1146 " tx status 0x%08x, tx mask 0x%08x.\n",
1154 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1156 u32 tis = ravb_read(ndev, TIS);
1158 if (tis & TIS_TFUF) {
1159 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1160 ravb_get_tx_tstamp(ndev);
1166 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1168 struct net_device *ndev = dev_id;
1169 struct ravb_private *priv = netdev_priv(ndev);
1170 const struct ravb_hw_info *info = priv->info;
1171 irqreturn_t result = IRQ_NONE;
1174 spin_lock(&priv->lock);
1175 /* Get interrupt status */
1176 iss = ravb_read(ndev, ISS);
1178 /* Received and transmitted interrupts */
1179 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1182 /* Timestamp updated */
1183 if (ravb_timestamp_interrupt(ndev))
1184 result = IRQ_HANDLED;
1186 /* Network control and best effort queue RX/TX */
1187 if (info->nc_queues) {
1188 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1189 if (ravb_queue_interrupt(ndev, q))
1190 result = IRQ_HANDLED;
1193 if (ravb_queue_interrupt(ndev, RAVB_BE))
1194 result = IRQ_HANDLED;
1198 /* E-MAC status summary */
1200 ravb_emac_interrupt_unlocked(ndev);
1201 result = IRQ_HANDLED;
1204 /* Error status summary */
1206 ravb_error_interrupt(ndev);
1207 result = IRQ_HANDLED;
1210 /* gPTP interrupt status summary */
1211 if (iss & ISS_CGIS) {
1212 ravb_ptp_interrupt(ndev);
1213 result = IRQ_HANDLED;
1216 spin_unlock(&priv->lock);
1220 /* Timestamp/Error/gPTP interrupt handler */
1221 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1223 struct net_device *ndev = dev_id;
1224 struct ravb_private *priv = netdev_priv(ndev);
1225 irqreturn_t result = IRQ_NONE;
1228 spin_lock(&priv->lock);
1229 /* Get interrupt status */
1230 iss = ravb_read(ndev, ISS);
1232 /* Timestamp updated */
1233 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1234 result = IRQ_HANDLED;
1236 /* Error status summary */
1238 ravb_error_interrupt(ndev);
1239 result = IRQ_HANDLED;
1242 /* gPTP interrupt status summary */
1243 if (iss & ISS_CGIS) {
1244 ravb_ptp_interrupt(ndev);
1245 result = IRQ_HANDLED;
1248 spin_unlock(&priv->lock);
1252 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1254 struct net_device *ndev = dev_id;
1255 struct ravb_private *priv = netdev_priv(ndev);
1256 irqreturn_t result = IRQ_NONE;
1258 spin_lock(&priv->lock);
1260 /* Network control/Best effort queue RX/TX */
1261 if (ravb_queue_interrupt(ndev, q))
1262 result = IRQ_HANDLED;
1264 spin_unlock(&priv->lock);
1268 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1270 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1273 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1275 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1278 static int ravb_poll(struct napi_struct *napi, int budget)
1280 struct net_device *ndev = napi->dev;
1281 struct ravb_private *priv = netdev_priv(ndev);
1282 const struct ravb_hw_info *info = priv->info;
1283 bool gptp = info->gptp || info->ccc_gac;
1284 struct ravb_rx_desc *desc;
1285 unsigned long flags;
1286 int q = napi - priv->napi;
1292 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
1293 desc = &priv->gbeth_rx_ring[entry];
1295 /* Processing RX Descriptor Ring */
1296 /* Clear RX interrupt */
1297 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1298 if (gptp || desc->die_dt != DT_FEMPTY) {
1299 if (ravb_rx(ndev, "a, q))
1303 /* Processing TX Descriptor Ring */
1304 spin_lock_irqsave(&priv->lock, flags);
1305 /* Clear TX interrupt */
1306 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1307 ravb_tx_free(ndev, q, true);
1308 netif_wake_subqueue(ndev, q);
1309 spin_unlock_irqrestore(&priv->lock, flags);
1311 napi_complete(napi);
1313 /* Re-enable RX/TX interrupts */
1314 spin_lock_irqsave(&priv->lock, flags);
1315 if (!info->irq_en_dis) {
1316 ravb_modify(ndev, RIC0, mask, mask);
1317 ravb_modify(ndev, TIC, mask, mask);
1319 ravb_write(ndev, mask, RIE0);
1320 ravb_write(ndev, mask, TIE);
1322 spin_unlock_irqrestore(&priv->lock, flags);
1324 /* Receive error message handling */
1325 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1326 if (info->nc_queues)
1327 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1328 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1329 ndev->stats.rx_over_errors = priv->rx_over_errors;
1330 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1331 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1333 return budget - quota;
1336 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1338 struct ravb_private *priv = netdev_priv(ndev);
1340 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1343 /* PHY state control function */
1344 static void ravb_adjust_link(struct net_device *ndev)
1346 struct ravb_private *priv = netdev_priv(ndev);
1347 const struct ravb_hw_info *info = priv->info;
1348 struct phy_device *phydev = ndev->phydev;
1349 bool new_state = false;
1350 unsigned long flags;
1352 spin_lock_irqsave(&priv->lock, flags);
1354 /* Disable TX and RX right over here, if E-MAC change is ignored */
1355 if (priv->no_avb_link)
1356 ravb_rcv_snd_disable(ndev);
1359 if (info->half_duplex && phydev->duplex != priv->duplex) {
1361 priv->duplex = phydev->duplex;
1362 ravb_set_duplex_gbeth(ndev);
1365 if (phydev->speed != priv->speed) {
1367 priv->speed = phydev->speed;
1368 info->set_rate(ndev);
1371 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1373 priv->link = phydev->link;
1375 } else if (priv->link) {
1379 if (info->half_duplex)
1383 /* Enable TX and RX right over here, if E-MAC change is ignored */
1384 if (priv->no_avb_link && phydev->link)
1385 ravb_rcv_snd_enable(ndev);
1387 spin_unlock_irqrestore(&priv->lock, flags);
1389 if (new_state && netif_msg_link(priv))
1390 phy_print_status(phydev);
1393 static const struct soc_device_attribute r8a7795es10[] = {
1394 { .soc_id = "r8a7795", .revision = "ES1.0", },
1398 /* PHY init function */
1399 static int ravb_phy_init(struct net_device *ndev)
1401 struct device_node *np = ndev->dev.parent->of_node;
1402 struct ravb_private *priv = netdev_priv(ndev);
1403 const struct ravb_hw_info *info = priv->info;
1404 struct phy_device *phydev;
1405 struct device_node *pn;
1406 phy_interface_t iface;
1413 /* Try connecting to PHY */
1414 pn = of_parse_phandle(np, "phy-handle", 0);
1416 /* In the case of a fixed PHY, the DT node associated
1417 * to the PHY is the Ethernet MAC DT node.
1419 if (of_phy_is_fixed_link(np)) {
1420 err = of_phy_register_fixed_link(np);
1424 pn = of_node_get(np);
1427 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1428 : priv->phy_interface;
1429 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1432 netdev_err(ndev, "failed to connect PHY\n");
1434 goto err_deregister_fixed_link;
1437 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1440 if (soc_device_match(r8a7795es10)) {
1441 phy_set_max_speed(phydev, SPEED_100);
1443 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1446 if (!info->half_duplex) {
1447 /* 10BASE, Pause and Asym Pause is not supported */
1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1449 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1450 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1451 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1453 /* Half Duplex is not supported */
1454 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1455 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1458 phy_attached_info(phydev);
1462 err_deregister_fixed_link:
1463 if (of_phy_is_fixed_link(np))
1464 of_phy_deregister_fixed_link(np);
1469 /* PHY control start function */
1470 static int ravb_phy_start(struct net_device *ndev)
1474 error = ravb_phy_init(ndev);
1478 phy_start(ndev->phydev);
1483 static u32 ravb_get_msglevel(struct net_device *ndev)
1485 struct ravb_private *priv = netdev_priv(ndev);
1487 return priv->msg_enable;
1490 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1492 struct ravb_private *priv = netdev_priv(ndev);
1494 priv->msg_enable = value;
1497 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1498 "rx_queue_0_current",
1499 "tx_queue_0_current",
1502 "rx_queue_0_packets",
1503 "tx_queue_0_packets",
1506 "rx_queue_0_mcast_packets",
1507 "rx_queue_0_errors",
1508 "rx_queue_0_crc_errors",
1509 "rx_queue_0_frame_errors",
1510 "rx_queue_0_length_errors",
1511 "rx_queue_0_csum_offload_errors",
1512 "rx_queue_0_over_errors",
1515 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1516 "rx_queue_0_current",
1517 "tx_queue_0_current",
1520 "rx_queue_0_packets",
1521 "tx_queue_0_packets",
1524 "rx_queue_0_mcast_packets",
1525 "rx_queue_0_errors",
1526 "rx_queue_0_crc_errors",
1527 "rx_queue_0_frame_errors",
1528 "rx_queue_0_length_errors",
1529 "rx_queue_0_missed_errors",
1530 "rx_queue_0_over_errors",
1532 "rx_queue_1_current",
1533 "tx_queue_1_current",
1536 "rx_queue_1_packets",
1537 "tx_queue_1_packets",
1540 "rx_queue_1_mcast_packets",
1541 "rx_queue_1_errors",
1542 "rx_queue_1_crc_errors",
1543 "rx_queue_1_frame_errors",
1544 "rx_queue_1_length_errors",
1545 "rx_queue_1_missed_errors",
1546 "rx_queue_1_over_errors",
1549 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1551 struct ravb_private *priv = netdev_priv(netdev);
1552 const struct ravb_hw_info *info = priv->info;
1556 return info->stats_len;
1562 static void ravb_get_ethtool_stats(struct net_device *ndev,
1563 struct ethtool_stats *estats, u64 *data)
1565 struct ravb_private *priv = netdev_priv(ndev);
1566 const struct ravb_hw_info *info = priv->info;
1571 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1572 /* Device-specific stats */
1573 for (q = RAVB_BE; q < num_rx_q; q++) {
1574 struct net_device_stats *stats = &priv->stats[q];
1576 data[i++] = priv->cur_rx[q];
1577 data[i++] = priv->cur_tx[q];
1578 data[i++] = priv->dirty_rx[q];
1579 data[i++] = priv->dirty_tx[q];
1580 data[i++] = stats->rx_packets;
1581 data[i++] = stats->tx_packets;
1582 data[i++] = stats->rx_bytes;
1583 data[i++] = stats->tx_bytes;
1584 data[i++] = stats->multicast;
1585 data[i++] = stats->rx_errors;
1586 data[i++] = stats->rx_crc_errors;
1587 data[i++] = stats->rx_frame_errors;
1588 data[i++] = stats->rx_length_errors;
1589 data[i++] = stats->rx_missed_errors;
1590 data[i++] = stats->rx_over_errors;
1594 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1596 struct ravb_private *priv = netdev_priv(ndev);
1597 const struct ravb_hw_info *info = priv->info;
1599 switch (stringset) {
1601 memcpy(data, info->gstrings_stats, info->gstrings_size);
1606 static void ravb_get_ringparam(struct net_device *ndev,
1607 struct ethtool_ringparam *ring,
1608 struct kernel_ethtool_ringparam *kernel_ring,
1609 struct netlink_ext_ack *extack)
1611 struct ravb_private *priv = netdev_priv(ndev);
1613 ring->rx_max_pending = BE_RX_RING_MAX;
1614 ring->tx_max_pending = BE_TX_RING_MAX;
1615 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1616 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1619 static int ravb_set_ringparam(struct net_device *ndev,
1620 struct ethtool_ringparam *ring,
1621 struct kernel_ethtool_ringparam *kernel_ring,
1622 struct netlink_ext_ack *extack)
1624 struct ravb_private *priv = netdev_priv(ndev);
1625 const struct ravb_hw_info *info = priv->info;
1628 if (ring->tx_pending > BE_TX_RING_MAX ||
1629 ring->rx_pending > BE_RX_RING_MAX ||
1630 ring->tx_pending < BE_TX_RING_MIN ||
1631 ring->rx_pending < BE_RX_RING_MIN)
1633 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1636 if (netif_running(ndev)) {
1637 netif_device_detach(ndev);
1638 /* Stop PTP Clock driver */
1640 ravb_ptp_stop(ndev);
1641 /* Wait for DMA stopping */
1642 error = ravb_stop_dma(ndev);
1645 "cannot set ringparam! Any AVB processes are still running?\n");
1648 synchronize_irq(ndev->irq);
1650 /* Free all the skb's in the RX queue and the DMA buffers. */
1651 ravb_ring_free(ndev, RAVB_BE);
1652 if (info->nc_queues)
1653 ravb_ring_free(ndev, RAVB_NC);
1656 /* Set new parameters */
1657 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1658 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1660 if (netif_running(ndev)) {
1661 error = ravb_dmac_init(ndev);
1664 "%s: ravb_dmac_init() failed, error %d\n",
1669 ravb_emac_init(ndev);
1671 /* Initialise PTP Clock driver */
1673 ravb_ptp_init(ndev, priv->pdev);
1675 netif_device_attach(ndev);
1681 static int ravb_get_ts_info(struct net_device *ndev,
1682 struct ethtool_ts_info *info)
1684 struct ravb_private *priv = netdev_priv(ndev);
1685 const struct ravb_hw_info *hw_info = priv->info;
1687 info->so_timestamping =
1688 SOF_TIMESTAMPING_TX_SOFTWARE |
1689 SOF_TIMESTAMPING_RX_SOFTWARE |
1690 SOF_TIMESTAMPING_SOFTWARE |
1691 SOF_TIMESTAMPING_TX_HARDWARE |
1692 SOF_TIMESTAMPING_RX_HARDWARE |
1693 SOF_TIMESTAMPING_RAW_HARDWARE;
1694 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1696 (1 << HWTSTAMP_FILTER_NONE) |
1697 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1698 (1 << HWTSTAMP_FILTER_ALL);
1699 if (hw_info->gptp || hw_info->ccc_gac)
1700 info->phc_index = ptp_clock_index(priv->ptp.clock);
1705 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1707 struct ravb_private *priv = netdev_priv(ndev);
1709 wol->supported = WAKE_MAGIC;
1710 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1713 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1715 struct ravb_private *priv = netdev_priv(ndev);
1716 const struct ravb_hw_info *info = priv->info;
1718 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1721 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1723 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1728 static const struct ethtool_ops ravb_ethtool_ops = {
1729 .nway_reset = phy_ethtool_nway_reset,
1730 .get_msglevel = ravb_get_msglevel,
1731 .set_msglevel = ravb_set_msglevel,
1732 .get_link = ethtool_op_get_link,
1733 .get_strings = ravb_get_strings,
1734 .get_ethtool_stats = ravb_get_ethtool_stats,
1735 .get_sset_count = ravb_get_sset_count,
1736 .get_ringparam = ravb_get_ringparam,
1737 .set_ringparam = ravb_set_ringparam,
1738 .get_ts_info = ravb_get_ts_info,
1739 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1740 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1741 .get_wol = ravb_get_wol,
1742 .set_wol = ravb_set_wol,
1745 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1746 struct net_device *ndev, struct device *dev,
1752 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1755 error = request_irq(irq, handler, 0, name, ndev);
1757 netdev_err(ndev, "cannot request IRQ %s\n", name);
1762 /* Network device open function for Ethernet AVB */
1763 static int ravb_open(struct net_device *ndev)
1765 struct ravb_private *priv = netdev_priv(ndev);
1766 const struct ravb_hw_info *info = priv->info;
1767 struct platform_device *pdev = priv->pdev;
1768 struct device *dev = &pdev->dev;
1771 napi_enable(&priv->napi[RAVB_BE]);
1772 if (info->nc_queues)
1773 napi_enable(&priv->napi[RAVB_NC]);
1775 if (!info->multi_irqs) {
1776 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1779 netdev_err(ndev, "cannot request IRQ\n");
1783 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1787 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1791 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1792 ndev, dev, "ch0:rx_be");
1794 goto out_free_irq_emac;
1795 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1796 ndev, dev, "ch18:tx_be");
1798 goto out_free_irq_be_rx;
1799 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1800 ndev, dev, "ch1:rx_nc");
1802 goto out_free_irq_be_tx;
1803 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1804 ndev, dev, "ch19:tx_nc");
1806 goto out_free_irq_nc_rx;
1808 if (info->err_mgmt_irqs) {
1809 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1810 ndev, dev, "err_a");
1812 goto out_free_irq_nc_tx;
1813 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1814 ndev, dev, "mgmt_a");
1816 goto out_free_irq_erra;
1821 error = ravb_dmac_init(ndev);
1823 goto out_free_irq_mgmta;
1824 ravb_emac_init(ndev);
1826 /* Initialise PTP Clock driver */
1828 ravb_ptp_init(ndev, priv->pdev);
1830 netif_tx_start_all_queues(ndev);
1832 /* PHY control start */
1833 error = ravb_phy_start(ndev);
1840 /* Stop PTP Clock driver */
1842 ravb_ptp_stop(ndev);
1844 if (!info->multi_irqs)
1846 if (info->err_mgmt_irqs)
1847 free_irq(priv->mgmta_irq, ndev);
1849 if (info->err_mgmt_irqs)
1850 free_irq(priv->erra_irq, ndev);
1852 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1854 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1856 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1858 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1860 free_irq(priv->emac_irq, ndev);
1862 free_irq(ndev->irq, ndev);
1864 if (info->nc_queues)
1865 napi_disable(&priv->napi[RAVB_NC]);
1866 napi_disable(&priv->napi[RAVB_BE]);
1870 /* Timeout function for Ethernet AVB */
1871 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1873 struct ravb_private *priv = netdev_priv(ndev);
1875 netif_err(priv, tx_err, ndev,
1876 "transmit timed out, status %08x, resetting...\n",
1877 ravb_read(ndev, ISS));
1879 /* tx_errors count up */
1880 ndev->stats.tx_errors++;
1882 schedule_work(&priv->work);
1885 static void ravb_tx_timeout_work(struct work_struct *work)
1887 struct ravb_private *priv = container_of(work, struct ravb_private,
1889 const struct ravb_hw_info *info = priv->info;
1890 struct net_device *ndev = priv->ndev;
1893 netif_tx_stop_all_queues(ndev);
1895 /* Stop PTP Clock driver */
1897 ravb_ptp_stop(ndev);
1899 /* Wait for DMA stopping */
1900 if (ravb_stop_dma(ndev)) {
1901 /* If ravb_stop_dma() fails, the hardware is still operating
1902 * for TX and/or RX. So, this should not call the following
1903 * functions because ravb_dmac_init() is possible to fail too.
1904 * Also, this should not retry ravb_stop_dma() again and again
1905 * here because it's possible to wait forever. So, this just
1906 * re-enables the TX and RX and skip the following
1907 * re-initialization procedure.
1909 ravb_rcv_snd_enable(ndev);
1913 ravb_ring_free(ndev, RAVB_BE);
1914 if (info->nc_queues)
1915 ravb_ring_free(ndev, RAVB_NC);
1918 error = ravb_dmac_init(ndev);
1920 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1921 * should return here to avoid re-enabling the TX and RX in
1924 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1928 ravb_emac_init(ndev);
1931 /* Initialise PTP Clock driver */
1933 ravb_ptp_init(ndev, priv->pdev);
1935 netif_tx_start_all_queues(ndev);
1938 /* Packet transmit function for Ethernet AVB */
1939 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1941 struct ravb_private *priv = netdev_priv(ndev);
1942 const struct ravb_hw_info *info = priv->info;
1943 unsigned int num_tx_desc = priv->num_tx_desc;
1944 u16 q = skb_get_queue_mapping(skb);
1945 struct ravb_tstamp_skb *ts_skb;
1946 struct ravb_tx_desc *desc;
1947 unsigned long flags;
1953 spin_lock_irqsave(&priv->lock, flags);
1954 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1956 netif_err(priv, tx_queued, ndev,
1957 "still transmitting with the full ring!\n");
1958 netif_stop_subqueue(ndev, q);
1959 spin_unlock_irqrestore(&priv->lock, flags);
1960 return NETDEV_TX_BUSY;
1963 if (skb_put_padto(skb, ETH_ZLEN))
1966 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1967 priv->tx_skb[q][entry / num_tx_desc] = skb;
1969 if (num_tx_desc > 1) {
1970 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1971 entry / num_tx_desc * DPTR_ALIGN;
1972 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1974 /* Zero length DMA descriptors are problematic as they seem
1975 * to terminate DMA transfers. Avoid them by simply using a
1976 * length of DPTR_ALIGN (4) when skb data is aligned to
1979 * As skb is guaranteed to have at least ETH_ZLEN (60)
1980 * bytes of data by the call to skb_put_padto() above this
1981 * is safe with respect to both the length of the first DMA
1982 * descriptor (len) overflowing the available data and the
1983 * length of the second DMA descriptor (skb->len - len)
1989 memcpy(buffer, skb->data, len);
1990 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1992 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1995 desc = &priv->tx_ring[q][entry];
1996 desc->ds_tagl = cpu_to_le16(len);
1997 desc->dptr = cpu_to_le32(dma_addr);
1999 buffer = skb->data + len;
2000 len = skb->len - len;
2001 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
2003 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2008 desc = &priv->tx_ring[q][entry];
2010 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2012 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2015 desc->ds_tagl = cpu_to_le16(len);
2016 desc->dptr = cpu_to_le32(dma_addr);
2018 /* TX timestamp required */
2019 if (info->gptp || info->ccc_gac) {
2021 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2023 if (num_tx_desc > 1) {
2025 dma_unmap_single(ndev->dev.parent, dma_addr,
2026 len, DMA_TO_DEVICE);
2030 ts_skb->skb = skb_get(skb);
2031 ts_skb->tag = priv->ts_skb_tag++;
2032 priv->ts_skb_tag &= 0x3ff;
2033 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2035 /* TAG and timestamp required flag */
2036 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2037 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2038 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2041 skb_tx_timestamp(skb);
2043 /* Descriptor type must be set after all the above writes */
2045 if (num_tx_desc > 1) {
2046 desc->die_dt = DT_FEND;
2048 desc->die_dt = DT_FSTART;
2050 desc->die_dt = DT_FSINGLE;
2052 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2054 priv->cur_tx[q] += num_tx_desc;
2055 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2056 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2057 !ravb_tx_free(ndev, q, true))
2058 netif_stop_subqueue(ndev, q);
2061 spin_unlock_irqrestore(&priv->lock, flags);
2062 return NETDEV_TX_OK;
2065 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2066 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2068 dev_kfree_skb_any(skb);
2069 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2073 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2074 struct net_device *sb_dev)
2076 /* If skb needs TX timestamp, it is handled in network control queue */
2077 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2082 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2084 struct ravb_private *priv = netdev_priv(ndev);
2085 const struct ravb_hw_info *info = priv->info;
2086 struct net_device_stats *nstats, *stats0, *stats1;
2088 nstats = &ndev->stats;
2089 stats0 = &priv->stats[RAVB_BE];
2091 if (info->tx_counters) {
2092 nstats->tx_dropped += ravb_read(ndev, TROCR);
2093 ravb_write(ndev, 0, TROCR); /* (write clear) */
2096 if (info->carrier_counters) {
2097 nstats->collisions += ravb_read(ndev, CXR41);
2098 ravb_write(ndev, 0, CXR41); /* (write clear) */
2099 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2100 ravb_write(ndev, 0, CXR42); /* (write clear) */
2103 nstats->rx_packets = stats0->rx_packets;
2104 nstats->tx_packets = stats0->tx_packets;
2105 nstats->rx_bytes = stats0->rx_bytes;
2106 nstats->tx_bytes = stats0->tx_bytes;
2107 nstats->multicast = stats0->multicast;
2108 nstats->rx_errors = stats0->rx_errors;
2109 nstats->rx_crc_errors = stats0->rx_crc_errors;
2110 nstats->rx_frame_errors = stats0->rx_frame_errors;
2111 nstats->rx_length_errors = stats0->rx_length_errors;
2112 nstats->rx_missed_errors = stats0->rx_missed_errors;
2113 nstats->rx_over_errors = stats0->rx_over_errors;
2114 if (info->nc_queues) {
2115 stats1 = &priv->stats[RAVB_NC];
2117 nstats->rx_packets += stats1->rx_packets;
2118 nstats->tx_packets += stats1->tx_packets;
2119 nstats->rx_bytes += stats1->rx_bytes;
2120 nstats->tx_bytes += stats1->tx_bytes;
2121 nstats->multicast += stats1->multicast;
2122 nstats->rx_errors += stats1->rx_errors;
2123 nstats->rx_crc_errors += stats1->rx_crc_errors;
2124 nstats->rx_frame_errors += stats1->rx_frame_errors;
2125 nstats->rx_length_errors += stats1->rx_length_errors;
2126 nstats->rx_missed_errors += stats1->rx_missed_errors;
2127 nstats->rx_over_errors += stats1->rx_over_errors;
2133 /* Update promiscuous bit */
2134 static void ravb_set_rx_mode(struct net_device *ndev)
2136 struct ravb_private *priv = netdev_priv(ndev);
2137 unsigned long flags;
2139 spin_lock_irqsave(&priv->lock, flags);
2140 ravb_modify(ndev, ECMR, ECMR_PRM,
2141 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2142 spin_unlock_irqrestore(&priv->lock, flags);
2145 /* Device close function for Ethernet AVB */
2146 static int ravb_close(struct net_device *ndev)
2148 struct device_node *np = ndev->dev.parent->of_node;
2149 struct ravb_private *priv = netdev_priv(ndev);
2150 const struct ravb_hw_info *info = priv->info;
2151 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2153 netif_tx_stop_all_queues(ndev);
2155 /* Disable interrupts by clearing the interrupt masks. */
2156 ravb_write(ndev, 0, RIC0);
2157 ravb_write(ndev, 0, RIC2);
2158 ravb_write(ndev, 0, TIC);
2160 /* Stop PTP Clock driver */
2162 ravb_ptp_stop(ndev);
2164 /* Set the config mode to stop the AVB-DMAC's processes */
2165 if (ravb_stop_dma(ndev) < 0)
2167 "device will be stopped after h/w processes are done.\n");
2169 /* Clear the timestamp list */
2170 if (info->gptp || info->ccc_gac) {
2171 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2172 list_del(&ts_skb->list);
2173 kfree_skb(ts_skb->skb);
2178 /* PHY disconnect */
2180 phy_stop(ndev->phydev);
2181 phy_disconnect(ndev->phydev);
2182 if (of_phy_is_fixed_link(np))
2183 of_phy_deregister_fixed_link(np);
2186 if (info->multi_irqs) {
2187 free_irq(priv->tx_irqs[RAVB_NC], ndev);
2188 free_irq(priv->rx_irqs[RAVB_NC], ndev);
2189 free_irq(priv->tx_irqs[RAVB_BE], ndev);
2190 free_irq(priv->rx_irqs[RAVB_BE], ndev);
2191 free_irq(priv->emac_irq, ndev);
2192 if (info->err_mgmt_irqs) {
2193 free_irq(priv->erra_irq, ndev);
2194 free_irq(priv->mgmta_irq, ndev);
2197 free_irq(ndev->irq, ndev);
2199 if (info->nc_queues)
2200 napi_disable(&priv->napi[RAVB_NC]);
2201 napi_disable(&priv->napi[RAVB_BE]);
2203 /* Free all the skb's in the RX queue and the DMA buffers. */
2204 ravb_ring_free(ndev, RAVB_BE);
2205 if (info->nc_queues)
2206 ravb_ring_free(ndev, RAVB_NC);
2211 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2213 struct ravb_private *priv = netdev_priv(ndev);
2214 struct hwtstamp_config config;
2217 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2219 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2220 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2221 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2223 case RAVB_RXTSTAMP_TYPE_ALL:
2224 config.rx_filter = HWTSTAMP_FILTER_ALL;
2227 config.rx_filter = HWTSTAMP_FILTER_NONE;
2230 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2234 /* Control hardware time stamping */
2235 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2237 struct ravb_private *priv = netdev_priv(ndev);
2238 struct hwtstamp_config config;
2239 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2242 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2245 switch (config.tx_type) {
2246 case HWTSTAMP_TX_OFF:
2249 case HWTSTAMP_TX_ON:
2250 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2256 switch (config.rx_filter) {
2257 case HWTSTAMP_FILTER_NONE:
2260 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2261 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2264 config.rx_filter = HWTSTAMP_FILTER_ALL;
2265 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2268 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2269 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2271 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2275 /* ioctl to device function */
2276 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2278 struct phy_device *phydev = ndev->phydev;
2280 if (!netif_running(ndev))
2288 return ravb_hwtstamp_get(ndev, req);
2290 return ravb_hwtstamp_set(ndev, req);
2293 return phy_mii_ioctl(phydev, req, cmd);
2296 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2298 struct ravb_private *priv = netdev_priv(ndev);
2300 ndev->mtu = new_mtu;
2302 if (netif_running(ndev)) {
2303 synchronize_irq(priv->emac_irq);
2304 ravb_emac_init(ndev);
2307 netdev_update_features(ndev);
2312 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2314 struct ravb_private *priv = netdev_priv(ndev);
2315 unsigned long flags;
2317 spin_lock_irqsave(&priv->lock, flags);
2319 /* Disable TX and RX */
2320 ravb_rcv_snd_disable(ndev);
2322 /* Modify RX Checksum setting */
2323 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2325 /* Enable TX and RX */
2326 ravb_rcv_snd_enable(ndev);
2328 spin_unlock_irqrestore(&priv->lock, flags);
2331 static int ravb_set_features_gbeth(struct net_device *ndev,
2332 netdev_features_t features)
2338 static int ravb_set_features_rcar(struct net_device *ndev,
2339 netdev_features_t features)
2341 netdev_features_t changed = ndev->features ^ features;
2343 if (changed & NETIF_F_RXCSUM)
2344 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2346 ndev->features = features;
2351 static int ravb_set_features(struct net_device *ndev,
2352 netdev_features_t features)
2354 struct ravb_private *priv = netdev_priv(ndev);
2355 const struct ravb_hw_info *info = priv->info;
2357 return info->set_feature(ndev, features);
2360 static const struct net_device_ops ravb_netdev_ops = {
2361 .ndo_open = ravb_open,
2362 .ndo_stop = ravb_close,
2363 .ndo_start_xmit = ravb_start_xmit,
2364 .ndo_select_queue = ravb_select_queue,
2365 .ndo_get_stats = ravb_get_stats,
2366 .ndo_set_rx_mode = ravb_set_rx_mode,
2367 .ndo_tx_timeout = ravb_tx_timeout,
2368 .ndo_eth_ioctl = ravb_do_ioctl,
2369 .ndo_change_mtu = ravb_change_mtu,
2370 .ndo_validate_addr = eth_validate_addr,
2371 .ndo_set_mac_address = eth_mac_addr,
2372 .ndo_set_features = ravb_set_features,
2375 /* MDIO bus init function */
2376 static int ravb_mdio_init(struct ravb_private *priv)
2378 struct platform_device *pdev = priv->pdev;
2379 struct device *dev = &pdev->dev;
2383 priv->mdiobb.ops = &bb_ops;
2385 /* MII controller setting */
2386 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2390 /* Hook up MII support for ethtool */
2391 priv->mii_bus->name = "ravb_mii";
2392 priv->mii_bus->parent = dev;
2393 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2394 pdev->name, pdev->id);
2396 /* Register MDIO bus */
2397 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2404 free_mdio_bitbang(priv->mii_bus);
2408 /* MDIO bus release function */
2409 static int ravb_mdio_release(struct ravb_private *priv)
2411 /* Unregister mdio bus */
2412 mdiobus_unregister(priv->mii_bus);
2414 /* Free bitbang info */
2415 free_mdio_bitbang(priv->mii_bus);
2420 static const struct ravb_hw_info ravb_gen3_hw_info = {
2421 .rx_ring_free = ravb_rx_ring_free_rcar,
2422 .rx_ring_format = ravb_rx_ring_format_rcar,
2423 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2424 .receive = ravb_rx_rcar,
2425 .set_rate = ravb_set_rate_rcar,
2426 .set_feature = ravb_set_features_rcar,
2427 .dmac_init = ravb_dmac_init_rcar,
2428 .emac_init = ravb_emac_init_rcar,
2429 .gstrings_stats = ravb_gstrings_stats,
2430 .gstrings_size = sizeof(ravb_gstrings_stats),
2431 .net_hw_features = NETIF_F_RXCSUM,
2432 .net_features = NETIF_F_RXCSUM,
2433 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2434 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2435 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2436 .rx_max_buf_size = SZ_2K,
2437 .internal_delay = 1,
2446 static const struct ravb_hw_info ravb_gen2_hw_info = {
2447 .rx_ring_free = ravb_rx_ring_free_rcar,
2448 .rx_ring_format = ravb_rx_ring_format_rcar,
2449 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2450 .receive = ravb_rx_rcar,
2451 .set_rate = ravb_set_rate_rcar,
2452 .set_feature = ravb_set_features_rcar,
2453 .dmac_init = ravb_dmac_init_rcar,
2454 .emac_init = ravb_emac_init_rcar,
2455 .gstrings_stats = ravb_gstrings_stats,
2456 .gstrings_size = sizeof(ravb_gstrings_stats),
2457 .net_hw_features = NETIF_F_RXCSUM,
2458 .net_features = NETIF_F_RXCSUM,
2459 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2460 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2461 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2462 .rx_max_buf_size = SZ_2K,
2469 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2470 .rx_ring_free = ravb_rx_ring_free_rcar,
2471 .rx_ring_format = ravb_rx_ring_format_rcar,
2472 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2473 .receive = ravb_rx_rcar,
2474 .set_rate = ravb_set_rate_rcar,
2475 .set_feature = ravb_set_features_rcar,
2476 .dmac_init = ravb_dmac_init_rcar,
2477 .emac_init = ravb_emac_init_rcar,
2478 .gstrings_stats = ravb_gstrings_stats,
2479 .gstrings_size = sizeof(ravb_gstrings_stats),
2480 .net_hw_features = NETIF_F_RXCSUM,
2481 .net_features = NETIF_F_RXCSUM,
2482 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2483 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2484 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2485 .rx_max_buf_size = SZ_2K,
2494 static const struct ravb_hw_info gbeth_hw_info = {
2495 .rx_ring_free = ravb_rx_ring_free_gbeth,
2496 .rx_ring_format = ravb_rx_ring_format_gbeth,
2497 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2498 .receive = ravb_rx_gbeth,
2499 .set_rate = ravb_set_rate_gbeth,
2500 .set_feature = ravb_set_features_gbeth,
2501 .dmac_init = ravb_dmac_init_gbeth,
2502 .emac_init = ravb_emac_init_gbeth,
2503 .gstrings_stats = ravb_gstrings_stats_gbeth,
2504 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2505 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2506 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2507 .tccr_mask = TCCR_TSRQ0,
2508 .rx_max_buf_size = SZ_8K,
2511 .carrier_counters = 1,
2515 static const struct of_device_id ravb_match_table[] = {
2516 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2517 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2518 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2519 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2520 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2521 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2522 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2523 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2526 MODULE_DEVICE_TABLE(of, ravb_match_table);
2528 static int ravb_set_gti(struct net_device *ndev)
2530 struct ravb_private *priv = netdev_priv(ndev);
2531 const struct ravb_hw_info *info = priv->info;
2532 struct device *dev = ndev->dev.parent;
2536 if (info->gptp_ref_clk)
2537 rate = clk_get_rate(priv->gptp_clk);
2539 rate = clk_get_rate(priv->clk);
2543 inc = div64_ul(1000000000ULL << 20, rate);
2545 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2546 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2547 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2551 ravb_write(ndev, inc, GTI);
2556 static void ravb_set_config_mode(struct net_device *ndev)
2558 struct ravb_private *priv = netdev_priv(ndev);
2559 const struct ravb_hw_info *info = priv->info;
2562 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2563 /* Set CSEL value */
2564 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2565 } else if (info->ccc_gac) {
2566 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2567 CCC_GAC | CCC_CSEL_HPB);
2569 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2573 /* Set tx and rx clock internal delay modes */
2574 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2576 struct ravb_private *priv = netdev_priv(ndev);
2577 bool explicit_delay = false;
2580 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2581 /* Valid values are 0 and 1800, according to DT bindings */
2582 priv->rxcidm = !!delay;
2583 explicit_delay = true;
2585 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2586 /* Valid values are 0 and 2000, according to DT bindings */
2587 priv->txcidm = !!delay;
2588 explicit_delay = true;
2594 /* Fall back to legacy rgmii-*id behavior */
2595 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2596 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2598 priv->rgmii_override = 1;
2601 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2602 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2604 priv->rgmii_override = 1;
2608 static void ravb_set_delay_mode(struct net_device *ndev)
2610 struct ravb_private *priv = netdev_priv(ndev);
2617 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2620 static int ravb_probe(struct platform_device *pdev)
2622 struct device_node *np = pdev->dev.of_node;
2623 const struct ravb_hw_info *info;
2624 struct reset_control *rstc;
2625 struct ravb_private *priv;
2626 struct net_device *ndev;
2628 struct resource *res;
2633 "this driver is required to be instantiated from device tree\n");
2637 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2639 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2640 "failed to get cpg reset\n");
2642 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2643 NUM_TX_QUEUE, NUM_RX_QUEUE);
2647 info = of_device_get_match_data(&pdev->dev);
2649 ndev->features = info->net_features;
2650 ndev->hw_features = info->net_hw_features;
2652 reset_control_deassert(rstc);
2653 pm_runtime_enable(&pdev->dev);
2654 pm_runtime_get_sync(&pdev->dev);
2656 if (info->multi_irqs) {
2657 if (info->err_mgmt_irqs)
2658 irq = platform_get_irq_byname(pdev, "dia");
2660 irq = platform_get_irq_byname(pdev, "ch22");
2662 irq = platform_get_irq(pdev, 0);
2670 SET_NETDEV_DEV(ndev, &pdev->dev);
2672 priv = netdev_priv(ndev);
2677 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2678 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2679 if (info->nc_queues) {
2680 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2681 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2684 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2685 if (IS_ERR(priv->addr)) {
2686 error = PTR_ERR(priv->addr);
2690 /* The Ether-specific entries in the device structure. */
2691 ndev->base_addr = res->start;
2693 spin_lock_init(&priv->lock);
2694 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2696 error = of_get_phy_mode(np, &priv->phy_interface);
2697 if (error && error != -ENODEV)
2700 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2701 priv->avb_link_active_low =
2702 of_property_read_bool(np, "renesas,ether-link-active-low");
2704 if (info->multi_irqs) {
2705 if (info->err_mgmt_irqs)
2706 irq = platform_get_irq_byname(pdev, "line3");
2708 irq = platform_get_irq_byname(pdev, "ch24");
2713 priv->emac_irq = irq;
2714 for (i = 0; i < NUM_RX_QUEUE; i++) {
2715 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2720 priv->rx_irqs[i] = irq;
2722 for (i = 0; i < NUM_TX_QUEUE; i++) {
2723 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2728 priv->tx_irqs[i] = irq;
2731 if (info->err_mgmt_irqs) {
2732 irq = platform_get_irq_byname(pdev, "err_a");
2737 priv->erra_irq = irq;
2739 irq = platform_get_irq_byname(pdev, "mgmt_a");
2744 priv->mgmta_irq = irq;
2748 priv->clk = devm_clk_get(&pdev->dev, NULL);
2749 if (IS_ERR(priv->clk)) {
2750 error = PTR_ERR(priv->clk);
2754 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2755 if (IS_ERR(priv->refclk)) {
2756 error = PTR_ERR(priv->refclk);
2759 clk_prepare_enable(priv->refclk);
2761 if (info->gptp_ref_clk) {
2762 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2763 if (IS_ERR(priv->gptp_clk)) {
2764 error = PTR_ERR(priv->gptp_clk);
2765 goto out_disable_refclk;
2767 clk_prepare_enable(priv->gptp_clk);
2770 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2771 ndev->min_mtu = ETH_MIN_MTU;
2773 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2774 * Use two descriptor to handle such situation. First descriptor to
2775 * handle aligned data buffer and second descriptor to handle the
2776 * overflow data because of alignment.
2778 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2781 ndev->netdev_ops = &ravb_netdev_ops;
2782 ndev->ethtool_ops = &ravb_ethtool_ops;
2784 /* Set AVB config mode */
2785 ravb_set_config_mode(ndev);
2787 if (info->gptp || info->ccc_gac) {
2789 error = ravb_set_gti(ndev);
2791 goto out_disable_gptp_clk;
2793 /* Request GTI loading */
2794 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2797 if (info->internal_delay) {
2798 ravb_parse_delay_mode(np, ndev);
2799 ravb_set_delay_mode(ndev);
2802 /* Allocate descriptor base address table */
2803 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2804 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2805 &priv->desc_bat_dma, GFP_KERNEL);
2806 if (!priv->desc_bat) {
2808 "Cannot allocate desc base address table (size %d bytes)\n",
2809 priv->desc_bat_size);
2811 goto out_disable_gptp_clk;
2813 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2814 priv->desc_bat[q].die_dt = DT_EOS;
2815 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2817 /* Initialise HW timestamp list */
2818 INIT_LIST_HEAD(&priv->ts_skb_list);
2820 /* Initialise PTP Clock driver */
2822 ravb_ptp_init(ndev, pdev);
2824 /* Debug message level */
2825 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2827 /* Read and set MAC address */
2828 ravb_read_mac_address(np, ndev);
2829 if (!is_valid_ether_addr(ndev->dev_addr)) {
2830 dev_warn(&pdev->dev,
2831 "no valid MAC address supplied, using a random one\n");
2832 eth_hw_addr_random(ndev);
2836 error = ravb_mdio_init(priv);
2838 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2842 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2843 if (info->nc_queues)
2844 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2846 /* Network device register */
2847 error = register_netdev(ndev);
2851 device_set_wakeup_capable(&pdev->dev, 1);
2853 /* Print device information */
2854 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2855 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2857 platform_set_drvdata(pdev, ndev);
2862 if (info->nc_queues)
2863 netif_napi_del(&priv->napi[RAVB_NC]);
2865 netif_napi_del(&priv->napi[RAVB_BE]);
2866 ravb_mdio_release(priv);
2868 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2869 priv->desc_bat_dma);
2871 /* Stop PTP Clock driver */
2873 ravb_ptp_stop(ndev);
2874 out_disable_gptp_clk:
2875 clk_disable_unprepare(priv->gptp_clk);
2877 clk_disable_unprepare(priv->refclk);
2881 pm_runtime_put(&pdev->dev);
2882 pm_runtime_disable(&pdev->dev);
2883 reset_control_assert(rstc);
2887 static int ravb_remove(struct platform_device *pdev)
2889 struct net_device *ndev = platform_get_drvdata(pdev);
2890 struct ravb_private *priv = netdev_priv(ndev);
2891 const struct ravb_hw_info *info = priv->info;
2893 /* Stop PTP Clock driver */
2895 ravb_ptp_stop(ndev);
2897 clk_disable_unprepare(priv->gptp_clk);
2898 clk_disable_unprepare(priv->refclk);
2900 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2901 priv->desc_bat_dma);
2902 /* Set reset mode */
2903 ravb_write(ndev, CCC_OPC_RESET, CCC);
2904 pm_runtime_put_sync(&pdev->dev);
2905 unregister_netdev(ndev);
2906 if (info->nc_queues)
2907 netif_napi_del(&priv->napi[RAVB_NC]);
2908 netif_napi_del(&priv->napi[RAVB_BE]);
2909 ravb_mdio_release(priv);
2910 pm_runtime_disable(&pdev->dev);
2911 reset_control_assert(priv->rstc);
2913 platform_set_drvdata(pdev, NULL);
2918 static int ravb_wol_setup(struct net_device *ndev)
2920 struct ravb_private *priv = netdev_priv(ndev);
2921 const struct ravb_hw_info *info = priv->info;
2923 /* Disable interrupts by clearing the interrupt masks. */
2924 ravb_write(ndev, 0, RIC0);
2925 ravb_write(ndev, 0, RIC2);
2926 ravb_write(ndev, 0, TIC);
2928 /* Only allow ECI interrupts */
2929 synchronize_irq(priv->emac_irq);
2930 if (info->nc_queues)
2931 napi_disable(&priv->napi[RAVB_NC]);
2932 napi_disable(&priv->napi[RAVB_BE]);
2933 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2935 /* Enable MagicPacket */
2936 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2938 return enable_irq_wake(priv->emac_irq);
2941 static int ravb_wol_restore(struct net_device *ndev)
2943 struct ravb_private *priv = netdev_priv(ndev);
2944 const struct ravb_hw_info *info = priv->info;
2946 if (info->nc_queues)
2947 napi_enable(&priv->napi[RAVB_NC]);
2948 napi_enable(&priv->napi[RAVB_BE]);
2950 /* Disable MagicPacket */
2951 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2955 return disable_irq_wake(priv->emac_irq);
2958 static int __maybe_unused ravb_suspend(struct device *dev)
2960 struct net_device *ndev = dev_get_drvdata(dev);
2961 struct ravb_private *priv = netdev_priv(ndev);
2964 if (!netif_running(ndev))
2967 netif_device_detach(ndev);
2969 if (priv->wol_enabled)
2970 ret = ravb_wol_setup(ndev);
2972 ret = ravb_close(ndev);
2977 static int __maybe_unused ravb_resume(struct device *dev)
2979 struct net_device *ndev = dev_get_drvdata(dev);
2980 struct ravb_private *priv = netdev_priv(ndev);
2981 const struct ravb_hw_info *info = priv->info;
2984 /* If WoL is enabled set reset mode to rearm the WoL logic */
2985 if (priv->wol_enabled)
2986 ravb_write(ndev, CCC_OPC_RESET, CCC);
2988 /* All register have been reset to default values.
2989 * Restore all registers which where setup at probe time and
2990 * reopen device if it was running before system suspended.
2993 /* Set AVB config mode */
2994 ravb_set_config_mode(ndev);
2996 if (info->gptp || info->ccc_gac) {
2998 ret = ravb_set_gti(ndev);
3002 /* Request GTI loading */
3003 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3006 if (info->internal_delay)
3007 ravb_set_delay_mode(ndev);
3009 /* Restore descriptor base address table */
3010 ravb_write(ndev, priv->desc_bat_dma, DBAT);
3012 if (netif_running(ndev)) {
3013 if (priv->wol_enabled) {
3014 ret = ravb_wol_restore(ndev);
3018 ret = ravb_open(ndev);
3021 netif_device_attach(ndev);
3027 static int __maybe_unused ravb_runtime_nop(struct device *dev)
3029 /* Runtime PM callback shared between ->runtime_suspend()
3030 * and ->runtime_resume(). Simply returns success.
3032 * This driver re-initializes all registers after
3033 * pm_runtime_get_sync() anyway so there is no need
3034 * to save and restore registers here.
3039 static const struct dev_pm_ops ravb_dev_pm_ops = {
3040 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3041 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3044 static struct platform_driver ravb_driver = {
3045 .probe = ravb_probe,
3046 .remove = ravb_remove,
3049 .pm = &ravb_dev_pm_ops,
3050 .of_match_table = ravb_match_table,
3054 module_platform_driver(ravb_driver);
3056 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3057 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3058 MODULE_LICENSE("GPL v2");