1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/reset.h>
31 #include <linux/math64.h>
35 #define RAVB_DEF_MSG_ENABLE \
41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
61 for (i = 0; i < 10000; i++) {
62 if ((ravb_read(ndev, reg) & mask) == value)
69 static int ravb_config(struct net_device *ndev)
74 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
75 /* Check if the operating mode is changed to the config mode */
76 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
78 netdev_err(ndev, "failed to switch device to config mode\n");
83 static void ravb_set_rate_gbeth(struct net_device *ndev)
85 struct ravb_private *priv = netdev_priv(ndev);
87 switch (priv->speed) {
89 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
91 case 100: /* 100BASE */
92 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
94 case 1000: /* 1000BASE */
95 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
100 static void ravb_set_rate_rcar(struct net_device *ndev)
102 struct ravb_private *priv = netdev_priv(ndev);
104 switch (priv->speed) {
105 case 100: /* 100BASE */
106 ravb_write(ndev, GECMR_SPEED_100, GECMR);
108 case 1000: /* 1000BASE */
109 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
114 static void ravb_set_buffer_align(struct sk_buff *skb)
116 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
119 skb_reserve(skb, RAVB_ALIGN - reserve);
122 /* Get MAC address from the MAC address registers
124 * Ethernet AVB device doesn't have ROM for MAC address.
125 * This function gets the MAC address that was used by a bootloader.
127 static void ravb_read_mac_address(struct device_node *np,
128 struct net_device *ndev)
132 ret = of_get_ethdev_address(np, ndev);
134 u32 mahr = ravb_read(ndev, MAHR);
135 u32 malr = ravb_read(ndev, MALR);
138 addr[0] = (mahr >> 24) & 0xFF;
139 addr[1] = (mahr >> 16) & 0xFF;
140 addr[2] = (mahr >> 8) & 0xFF;
141 addr[3] = (mahr >> 0) & 0xFF;
142 addr[4] = (malr >> 8) & 0xFF;
143 addr[5] = (malr >> 0) & 0xFF;
144 eth_hw_addr_set(ndev, addr);
148 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
150 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
153 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
156 /* MDC pin control */
157 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
159 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
162 /* Data I/O pin control */
163 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
165 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
169 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
171 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
175 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
177 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
180 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
183 /* MDIO bus control struct */
184 static const struct mdiobb_ops bb_ops = {
185 .owner = THIS_MODULE,
186 .set_mdc = ravb_set_mdc,
187 .set_mdio_dir = ravb_set_mdio_dir,
188 .set_mdio_data = ravb_set_mdio_data,
189 .get_mdio_data = ravb_get_mdio_data,
192 /* Free TX skb function for AVB-IP */
193 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
195 struct ravb_private *priv = netdev_priv(ndev);
196 struct net_device_stats *stats = &priv->stats[q];
197 unsigned int num_tx_desc = priv->num_tx_desc;
198 struct ravb_tx_desc *desc;
203 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
206 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
208 desc = &priv->tx_ring[q][entry];
209 txed = desc->die_dt == DT_FEMPTY;
210 if (free_txed_only && !txed)
212 /* Descriptor type must be checked before all other reads */
214 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
215 /* Free the original skb. */
216 if (priv->tx_skb[q][entry / num_tx_desc]) {
217 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
218 size, DMA_TO_DEVICE);
219 /* Last packet descriptor? */
220 if (entry % num_tx_desc == num_tx_desc - 1) {
221 entry /= num_tx_desc;
222 dev_kfree_skb_any(priv->tx_skb[q][entry]);
223 priv->tx_skb[q][entry] = NULL;
230 stats->tx_bytes += size;
231 desc->die_dt = DT_EEMPTY;
236 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
238 struct ravb_private *priv = netdev_priv(ndev);
239 unsigned int ring_size;
242 if (!priv->gbeth_rx_ring)
245 for (i = 0; i < priv->num_rx_ring[q]; i++) {
246 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
248 if (!dma_mapping_error(ndev->dev.parent,
249 le32_to_cpu(desc->dptr)))
250 dma_unmap_single(ndev->dev.parent,
251 le32_to_cpu(desc->dptr),
255 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
256 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
257 priv->rx_desc_dma[q]);
258 priv->gbeth_rx_ring = NULL;
261 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
263 struct ravb_private *priv = netdev_priv(ndev);
264 unsigned int ring_size;
267 if (!priv->rx_ring[q])
270 for (i = 0; i < priv->num_rx_ring[q]; i++) {
271 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
273 if (!dma_mapping_error(ndev->dev.parent,
274 le32_to_cpu(desc->dptr)))
275 dma_unmap_single(ndev->dev.parent,
276 le32_to_cpu(desc->dptr),
280 ring_size = sizeof(struct ravb_ex_rx_desc) *
281 (priv->num_rx_ring[q] + 1);
282 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
283 priv->rx_desc_dma[q]);
284 priv->rx_ring[q] = NULL;
287 /* Free skb's and DMA buffers for Ethernet AVB */
288 static void ravb_ring_free(struct net_device *ndev, int q)
290 struct ravb_private *priv = netdev_priv(ndev);
291 const struct ravb_hw_info *info = priv->info;
292 unsigned int num_tx_desc = priv->num_tx_desc;
293 unsigned int ring_size;
296 info->rx_ring_free(ndev, q);
298 if (priv->tx_ring[q]) {
299 ravb_tx_free(ndev, q, false);
301 ring_size = sizeof(struct ravb_tx_desc) *
302 (priv->num_tx_ring[q] * num_tx_desc + 1);
303 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
304 priv->tx_desc_dma[q]);
305 priv->tx_ring[q] = NULL;
308 /* Free RX skb ringbuffer */
309 if (priv->rx_skb[q]) {
310 for (i = 0; i < priv->num_rx_ring[q]; i++)
311 dev_kfree_skb(priv->rx_skb[q][i]);
313 kfree(priv->rx_skb[q]);
314 priv->rx_skb[q] = NULL;
316 /* Free aligned TX buffers */
317 kfree(priv->tx_align[q]);
318 priv->tx_align[q] = NULL;
320 /* Free TX skb ringbuffer.
321 * SKBs are freed by ravb_tx_free() call above.
323 kfree(priv->tx_skb[q]);
324 priv->tx_skb[q] = NULL;
327 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
329 struct ravb_private *priv = netdev_priv(ndev);
330 struct ravb_rx_desc *rx_desc;
331 unsigned int rx_ring_size;
335 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
336 memset(priv->gbeth_rx_ring, 0, rx_ring_size);
337 /* Build RX ring buffer */
338 for (i = 0; i < priv->num_rx_ring[q]; i++) {
340 rx_desc = &priv->gbeth_rx_ring[i];
341 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
342 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
345 /* We just set the data size to 0 for a failed mapping which
346 * should prevent DMA from happening...
348 if (dma_mapping_error(ndev->dev.parent, dma_addr))
349 rx_desc->ds_cc = cpu_to_le16(0);
350 rx_desc->dptr = cpu_to_le32(dma_addr);
351 rx_desc->die_dt = DT_FEMPTY;
353 rx_desc = &priv->gbeth_rx_ring[i];
354 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
355 rx_desc->die_dt = DT_LINKFIX; /* type */
358 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
360 struct ravb_private *priv = netdev_priv(ndev);
361 struct ravb_ex_rx_desc *rx_desc;
362 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
366 memset(priv->rx_ring[q], 0, rx_ring_size);
367 /* Build RX ring buffer */
368 for (i = 0; i < priv->num_rx_ring[q]; i++) {
370 rx_desc = &priv->rx_ring[q][i];
371 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
372 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
375 /* We just set the data size to 0 for a failed mapping which
376 * should prevent DMA from happening...
378 if (dma_mapping_error(ndev->dev.parent, dma_addr))
379 rx_desc->ds_cc = cpu_to_le16(0);
380 rx_desc->dptr = cpu_to_le32(dma_addr);
381 rx_desc->die_dt = DT_FEMPTY;
383 rx_desc = &priv->rx_ring[q][i];
384 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
385 rx_desc->die_dt = DT_LINKFIX; /* type */
388 /* Format skb and descriptor buffer for Ethernet AVB */
389 static void ravb_ring_format(struct net_device *ndev, int q)
391 struct ravb_private *priv = netdev_priv(ndev);
392 const struct ravb_hw_info *info = priv->info;
393 unsigned int num_tx_desc = priv->num_tx_desc;
394 struct ravb_tx_desc *tx_desc;
395 struct ravb_desc *desc;
396 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
402 priv->dirty_rx[q] = 0;
403 priv->dirty_tx[q] = 0;
405 info->rx_ring_format(ndev, q);
407 memset(priv->tx_ring[q], 0, tx_ring_size);
408 /* Build TX ring buffer */
409 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
411 tx_desc->die_dt = DT_EEMPTY;
412 if (num_tx_desc > 1) {
414 tx_desc->die_dt = DT_EEMPTY;
417 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
418 tx_desc->die_dt = DT_LINKFIX; /* type */
420 /* RX descriptor base address for best effort */
421 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
422 desc->die_dt = DT_LINKFIX; /* type */
423 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
425 /* TX descriptor base address for best effort */
426 desc = &priv->desc_bat[q];
427 desc->die_dt = DT_LINKFIX; /* type */
428 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
431 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
433 struct ravb_private *priv = netdev_priv(ndev);
434 unsigned int ring_size;
436 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
438 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
439 &priv->rx_desc_dma[q],
441 return priv->gbeth_rx_ring;
444 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
446 struct ravb_private *priv = netdev_priv(ndev);
447 unsigned int ring_size;
449 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
451 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
452 &priv->rx_desc_dma[q],
454 return priv->rx_ring[q];
457 /* Init skb and descriptor buffer for Ethernet AVB */
458 static int ravb_ring_init(struct net_device *ndev, int q)
460 struct ravb_private *priv = netdev_priv(ndev);
461 const struct ravb_hw_info *info = priv->info;
462 unsigned int num_tx_desc = priv->num_tx_desc;
463 unsigned int ring_size;
467 /* Allocate RX and TX skb rings */
468 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
469 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
470 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
471 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
472 if (!priv->rx_skb[q] || !priv->tx_skb[q])
475 for (i = 0; i < priv->num_rx_ring[q]; i++) {
476 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
479 ravb_set_buffer_align(skb);
480 priv->rx_skb[q][i] = skb;
483 if (num_tx_desc > 1) {
484 /* Allocate rings for the aligned buffers */
485 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
486 DPTR_ALIGN - 1, GFP_KERNEL);
487 if (!priv->tx_align[q])
491 /* Allocate all RX descriptors. */
492 if (!info->alloc_rx_desc(ndev, q))
495 priv->dirty_rx[q] = 0;
497 /* Allocate all TX descriptors. */
498 ring_size = sizeof(struct ravb_tx_desc) *
499 (priv->num_tx_ring[q] * num_tx_desc + 1);
500 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
501 &priv->tx_desc_dma[q],
503 if (!priv->tx_ring[q])
509 ravb_ring_free(ndev, q);
514 static void ravb_emac_init_gbeth(struct net_device *ndev)
516 struct ravb_private *priv = netdev_priv(ndev);
518 /* Receive frame limit set register */
519 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
521 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
522 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
523 ECMR_TE | ECMR_RE | ECMR_RCPT |
524 ECMR_TXF | ECMR_RXF, ECMR);
526 ravb_set_rate_gbeth(ndev);
528 /* Set MAC address */
530 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
531 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
532 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
534 /* E-MAC status register clear */
535 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
536 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
538 /* E-MAC interrupt enable register */
539 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
541 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
542 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
543 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
545 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
550 static void ravb_emac_init_rcar(struct net_device *ndev)
552 /* Receive frame limit set register */
553 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
555 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
556 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
557 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
558 ECMR_TE | ECMR_RE, ECMR);
560 ravb_set_rate_rcar(ndev);
562 /* Set MAC address */
564 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
565 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
567 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
569 /* E-MAC status register clear */
570 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
572 /* E-MAC interrupt enable register */
573 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
576 /* E-MAC init function */
577 static void ravb_emac_init(struct net_device *ndev)
579 struct ravb_private *priv = netdev_priv(ndev);
580 const struct ravb_hw_info *info = priv->info;
582 info->emac_init(ndev);
585 static int ravb_dmac_init_gbeth(struct net_device *ndev)
589 error = ravb_ring_init(ndev, RAVB_BE);
593 /* Descriptor format */
594 ravb_ring_format(ndev, RAVB_BE);
597 ravb_write(ndev, 0x60000000, RCR);
599 /* Set Max Frame Length (RTC) */
600 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
603 ravb_write(ndev, 0x00222200, TGC);
605 ravb_write(ndev, 0, TCCR);
608 ravb_write(ndev, RIC0_FRE0, RIC0);
609 /* Disable FIFO full warning */
610 ravb_write(ndev, 0x0, RIC1);
611 /* Receive FIFO full error, descriptor empty */
612 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
614 ravb_write(ndev, TIC_FTE0, TIC);
619 static int ravb_dmac_init_rcar(struct net_device *ndev)
621 struct ravb_private *priv = netdev_priv(ndev);
622 const struct ravb_hw_info *info = priv->info;
625 error = ravb_ring_init(ndev, RAVB_BE);
628 error = ravb_ring_init(ndev, RAVB_NC);
630 ravb_ring_free(ndev, RAVB_BE);
634 /* Descriptor format */
635 ravb_ring_format(ndev, RAVB_BE);
636 ravb_ring_format(ndev, RAVB_NC);
640 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
643 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
645 /* Timestamp enable */
646 ravb_write(ndev, TCCR_TFEN, TCCR);
648 /* Interrupt init: */
649 if (info->multi_irqs) {
651 ravb_write(ndev, 0, DIL);
652 /* Set queue specific interrupt */
653 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
656 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
657 /* Disable FIFO full warning */
658 ravb_write(ndev, 0, RIC1);
659 /* Receive FIFO full error, descriptor empty */
660 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
661 /* Frame transmitted, timestamp FIFO updated */
662 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
667 /* Device init function for Ethernet AVB */
668 static int ravb_dmac_init(struct net_device *ndev)
670 struct ravb_private *priv = netdev_priv(ndev);
671 const struct ravb_hw_info *info = priv->info;
674 /* Set CONFIG mode */
675 error = ravb_config(ndev);
679 error = info->dmac_init(ndev);
683 /* Setting the control will start the AVB-DMAC process. */
684 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
689 static void ravb_get_tx_tstamp(struct net_device *ndev)
691 struct ravb_private *priv = netdev_priv(ndev);
692 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
693 struct skb_shared_hwtstamps shhwtstamps;
695 struct timespec64 ts;
700 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
702 tfa2 = ravb_read(ndev, TFA2);
703 tfa_tag = (tfa2 & TFA2_TST) >> 16;
704 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
705 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
706 ravb_read(ndev, TFA1);
707 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
708 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
709 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
713 list_del(&ts_skb->list);
715 if (tag == tfa_tag) {
716 skb_tstamp_tx(skb, &shhwtstamps);
717 dev_consume_skb_any(skb);
720 dev_kfree_skb_any(skb);
723 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
727 static void ravb_rx_csum(struct sk_buff *skb)
731 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
732 * appended to packet data
734 if (unlikely(skb->len < sizeof(__sum16)))
736 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
737 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
738 skb->ip_summed = CHECKSUM_COMPLETE;
739 skb_trim(skb, skb->len - sizeof(__sum16));
742 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
743 struct ravb_rx_desc *desc)
745 struct ravb_private *priv = netdev_priv(ndev);
748 skb = priv->rx_skb[RAVB_BE][entry];
749 priv->rx_skb[RAVB_BE][entry] = NULL;
750 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
751 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
756 /* Packet receive function for Gigabit Ethernet */
757 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
759 struct ravb_private *priv = netdev_priv(ndev);
760 const struct ravb_hw_info *info = priv->info;
761 struct net_device_stats *stats;
762 struct ravb_rx_desc *desc;
772 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
773 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
774 stats = &priv->stats[q];
776 boguscnt = min(boguscnt, *quota);
778 desc = &priv->gbeth_rx_ring[entry];
779 while (desc->die_dt != DT_FEMPTY) {
780 /* Descriptor type must be checked before all other reads */
782 desc_status = desc->msc;
783 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
788 /* We use 0-byte descriptors to mark the DMA mapping errors */
792 if (desc_status & MSC_MC)
795 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
797 if (desc_status & MSC_CRC)
798 stats->rx_crc_errors++;
799 if (desc_status & MSC_RFE)
800 stats->rx_frame_errors++;
801 if (desc_status & (MSC_RTLF | MSC_RTSF))
802 stats->rx_length_errors++;
803 if (desc_status & MSC_CEEF)
804 stats->rx_missed_errors++;
806 die_dt = desc->die_dt & 0xF0;
809 skb = ravb_get_skb_gbeth(ndev, entry, desc);
810 skb_put(skb, pkt_len);
811 skb->protocol = eth_type_trans(skb, ndev);
812 napi_gro_receive(&priv->napi[q], skb);
814 stats->rx_bytes += pkt_len;
817 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
818 skb_put(priv->rx_1st_skb, pkt_len);
821 skb = ravb_get_skb_gbeth(ndev, entry, desc);
822 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
823 priv->rx_1st_skb->len,
826 skb_put(priv->rx_1st_skb, pkt_len);
830 skb = ravb_get_skb_gbeth(ndev, entry, desc);
831 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
832 priv->rx_1st_skb->len,
835 skb_put(priv->rx_1st_skb, pkt_len);
837 priv->rx_1st_skb->protocol =
838 eth_type_trans(priv->rx_1st_skb, ndev);
839 napi_gro_receive(&priv->napi[q],
842 stats->rx_bytes += pkt_len;
847 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
848 desc = &priv->gbeth_rx_ring[entry];
851 /* Refill the RX ring buffers. */
852 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
853 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
854 desc = &priv->gbeth_rx_ring[entry];
855 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
857 if (!priv->rx_skb[q][entry]) {
858 skb = netdev_alloc_skb(ndev, info->max_rx_len);
861 ravb_set_buffer_align(skb);
862 dma_addr = dma_map_single(ndev->dev.parent,
866 skb_checksum_none_assert(skb);
867 /* We just set the data size to 0 for a failed mapping
868 * which should prevent DMA from happening...
870 if (dma_mapping_error(ndev->dev.parent, dma_addr))
871 desc->ds_cc = cpu_to_le16(0);
872 desc->dptr = cpu_to_le32(dma_addr);
873 priv->rx_skb[q][entry] = skb;
875 /* Descriptor type must be set after all the above writes */
877 desc->die_dt = DT_FEMPTY;
880 *quota -= limit - (++boguscnt);
882 return boguscnt <= 0;
885 /* Packet receive function for Ethernet AVB */
886 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
888 struct ravb_private *priv = netdev_priv(ndev);
889 const struct ravb_hw_info *info = priv->info;
890 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
891 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
893 struct net_device_stats *stats = &priv->stats[q];
894 struct ravb_ex_rx_desc *desc;
897 struct timespec64 ts;
902 boguscnt = min(boguscnt, *quota);
904 desc = &priv->rx_ring[q][entry];
905 while (desc->die_dt != DT_FEMPTY) {
906 /* Descriptor type must be checked before all other reads */
908 desc_status = desc->msc;
909 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
914 /* We use 0-byte descriptors to mark the DMA mapping errors */
918 if (desc_status & MSC_MC)
921 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
924 if (desc_status & MSC_CRC)
925 stats->rx_crc_errors++;
926 if (desc_status & MSC_RFE)
927 stats->rx_frame_errors++;
928 if (desc_status & (MSC_RTLF | MSC_RTSF))
929 stats->rx_length_errors++;
930 if (desc_status & MSC_CEEF)
931 stats->rx_missed_errors++;
933 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
935 skb = priv->rx_skb[q][entry];
936 priv->rx_skb[q][entry] = NULL;
937 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
940 get_ts &= (q == RAVB_NC) ?
941 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
942 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
944 struct skb_shared_hwtstamps *shhwtstamps;
946 shhwtstamps = skb_hwtstamps(skb);
947 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
948 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
949 32) | le32_to_cpu(desc->ts_sl);
950 ts.tv_nsec = le32_to_cpu(desc->ts_n);
951 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
954 skb_put(skb, pkt_len);
955 skb->protocol = eth_type_trans(skb, ndev);
956 if (ndev->features & NETIF_F_RXCSUM)
958 napi_gro_receive(&priv->napi[q], skb);
960 stats->rx_bytes += pkt_len;
963 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
964 desc = &priv->rx_ring[q][entry];
967 /* Refill the RX ring buffers. */
968 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
969 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
970 desc = &priv->rx_ring[q][entry];
971 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
973 if (!priv->rx_skb[q][entry]) {
974 skb = netdev_alloc_skb(ndev, info->max_rx_len);
976 break; /* Better luck next round. */
977 ravb_set_buffer_align(skb);
978 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
979 le16_to_cpu(desc->ds_cc),
981 skb_checksum_none_assert(skb);
982 /* We just set the data size to 0 for a failed mapping
983 * which should prevent DMA from happening...
985 if (dma_mapping_error(ndev->dev.parent, dma_addr))
986 desc->ds_cc = cpu_to_le16(0);
987 desc->dptr = cpu_to_le32(dma_addr);
988 priv->rx_skb[q][entry] = skb;
990 /* Descriptor type must be set after all the above writes */
992 desc->die_dt = DT_FEMPTY;
995 *quota -= limit - (++boguscnt);
997 return boguscnt <= 0;
1000 /* Packet receive function for Ethernet AVB */
1001 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1003 struct ravb_private *priv = netdev_priv(ndev);
1004 const struct ravb_hw_info *info = priv->info;
1006 return info->receive(ndev, quota, q);
1009 static void ravb_rcv_snd_disable(struct net_device *ndev)
1011 /* Disable TX and RX */
1012 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1015 static void ravb_rcv_snd_enable(struct net_device *ndev)
1017 /* Enable TX and RX */
1018 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1021 /* function for waiting dma process finished */
1022 static int ravb_stop_dma(struct net_device *ndev)
1024 struct ravb_private *priv = netdev_priv(ndev);
1025 const struct ravb_hw_info *info = priv->info;
1028 /* Wait for stopping the hardware TX process */
1029 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1034 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1039 /* Stop the E-MAC's RX/TX processes. */
1040 ravb_rcv_snd_disable(ndev);
1042 /* Wait for stopping the RX DMA process */
1043 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1047 /* Stop AVB-DMAC process */
1048 return ravb_config(ndev);
1051 /* E-MAC interrupt handler */
1052 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1054 struct ravb_private *priv = netdev_priv(ndev);
1057 ecsr = ravb_read(ndev, ECSR);
1058 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1060 if (ecsr & ECSR_MPD)
1061 pm_wakeup_event(&priv->pdev->dev, 0);
1062 if (ecsr & ECSR_ICD)
1063 ndev->stats.tx_carrier_errors++;
1064 if (ecsr & ECSR_LCHNG) {
1066 if (priv->no_avb_link)
1068 psr = ravb_read(ndev, PSR);
1069 if (priv->avb_link_active_low)
1071 if (!(psr & PSR_LMON)) {
1072 /* DIsable RX and TX */
1073 ravb_rcv_snd_disable(ndev);
1075 /* Enable RX and TX */
1076 ravb_rcv_snd_enable(ndev);
1081 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1083 struct net_device *ndev = dev_id;
1084 struct ravb_private *priv = netdev_priv(ndev);
1086 spin_lock(&priv->lock);
1087 ravb_emac_interrupt_unlocked(ndev);
1088 spin_unlock(&priv->lock);
1092 /* Error interrupt handler */
1093 static void ravb_error_interrupt(struct net_device *ndev)
1095 struct ravb_private *priv = netdev_priv(ndev);
1098 eis = ravb_read(ndev, EIS);
1099 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1100 if (eis & EIS_QFS) {
1101 ris2 = ravb_read(ndev, RIS2);
1102 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
1105 /* Receive Descriptor Empty int */
1106 if (ris2 & RIS2_QFF0)
1107 priv->stats[RAVB_BE].rx_over_errors++;
1109 /* Receive Descriptor Empty int */
1110 if (ris2 & RIS2_QFF1)
1111 priv->stats[RAVB_NC].rx_over_errors++;
1113 /* Receive FIFO Overflow int */
1114 if (ris2 & RIS2_RFFF)
1115 priv->rx_fifo_errors++;
1119 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1121 struct ravb_private *priv = netdev_priv(ndev);
1122 const struct ravb_hw_info *info = priv->info;
1123 u32 ris0 = ravb_read(ndev, RIS0);
1124 u32 ric0 = ravb_read(ndev, RIC0);
1125 u32 tis = ravb_read(ndev, TIS);
1126 u32 tic = ravb_read(ndev, TIC);
1128 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1129 if (napi_schedule_prep(&priv->napi[q])) {
1130 /* Mask RX and TX interrupts */
1131 if (!info->irq_en_dis) {
1132 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1133 ravb_write(ndev, tic & ~BIT(q), TIC);
1135 ravb_write(ndev, BIT(q), RID0);
1136 ravb_write(ndev, BIT(q), TID);
1138 __napi_schedule(&priv->napi[q]);
1141 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1144 " tx status 0x%08x, tx mask 0x%08x.\n",
1152 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1154 u32 tis = ravb_read(ndev, TIS);
1156 if (tis & TIS_TFUF) {
1157 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1158 ravb_get_tx_tstamp(ndev);
1164 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1166 struct net_device *ndev = dev_id;
1167 struct ravb_private *priv = netdev_priv(ndev);
1168 const struct ravb_hw_info *info = priv->info;
1169 irqreturn_t result = IRQ_NONE;
1172 spin_lock(&priv->lock);
1173 /* Get interrupt status */
1174 iss = ravb_read(ndev, ISS);
1176 /* Received and transmitted interrupts */
1177 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1180 /* Timestamp updated */
1181 if (ravb_timestamp_interrupt(ndev))
1182 result = IRQ_HANDLED;
1184 /* Network control and best effort queue RX/TX */
1185 if (info->nc_queues) {
1186 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1187 if (ravb_queue_interrupt(ndev, q))
1188 result = IRQ_HANDLED;
1191 if (ravb_queue_interrupt(ndev, RAVB_BE))
1192 result = IRQ_HANDLED;
1196 /* E-MAC status summary */
1198 ravb_emac_interrupt_unlocked(ndev);
1199 result = IRQ_HANDLED;
1202 /* Error status summary */
1204 ravb_error_interrupt(ndev);
1205 result = IRQ_HANDLED;
1208 /* gPTP interrupt status summary */
1209 if (iss & ISS_CGIS) {
1210 ravb_ptp_interrupt(ndev);
1211 result = IRQ_HANDLED;
1214 spin_unlock(&priv->lock);
1218 /* Timestamp/Error/gPTP interrupt handler */
1219 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1221 struct net_device *ndev = dev_id;
1222 struct ravb_private *priv = netdev_priv(ndev);
1223 irqreturn_t result = IRQ_NONE;
1226 spin_lock(&priv->lock);
1227 /* Get interrupt status */
1228 iss = ravb_read(ndev, ISS);
1230 /* Timestamp updated */
1231 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1232 result = IRQ_HANDLED;
1234 /* Error status summary */
1236 ravb_error_interrupt(ndev);
1237 result = IRQ_HANDLED;
1240 /* gPTP interrupt status summary */
1241 if (iss & ISS_CGIS) {
1242 ravb_ptp_interrupt(ndev);
1243 result = IRQ_HANDLED;
1246 spin_unlock(&priv->lock);
1250 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1252 struct net_device *ndev = dev_id;
1253 struct ravb_private *priv = netdev_priv(ndev);
1254 irqreturn_t result = IRQ_NONE;
1256 spin_lock(&priv->lock);
1258 /* Network control/Best effort queue RX/TX */
1259 if (ravb_queue_interrupt(ndev, q))
1260 result = IRQ_HANDLED;
1262 spin_unlock(&priv->lock);
1266 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1268 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1271 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1273 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1276 static int ravb_poll(struct napi_struct *napi, int budget)
1278 struct net_device *ndev = napi->dev;
1279 struct ravb_private *priv = netdev_priv(ndev);
1280 const struct ravb_hw_info *info = priv->info;
1281 bool gptp = info->gptp || info->ccc_gac;
1282 struct ravb_rx_desc *desc;
1283 unsigned long flags;
1284 int q = napi - priv->napi;
1290 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
1291 desc = &priv->gbeth_rx_ring[entry];
1293 /* Processing RX Descriptor Ring */
1294 /* Clear RX interrupt */
1295 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1296 if (gptp || desc->die_dt != DT_FEMPTY) {
1297 if (ravb_rx(ndev, "a, q))
1301 /* Processing TX Descriptor Ring */
1302 spin_lock_irqsave(&priv->lock, flags);
1303 /* Clear TX interrupt */
1304 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1305 ravb_tx_free(ndev, q, true);
1306 netif_wake_subqueue(ndev, q);
1307 spin_unlock_irqrestore(&priv->lock, flags);
1309 napi_complete(napi);
1311 /* Re-enable RX/TX interrupts */
1312 spin_lock_irqsave(&priv->lock, flags);
1313 if (!info->irq_en_dis) {
1314 ravb_modify(ndev, RIC0, mask, mask);
1315 ravb_modify(ndev, TIC, mask, mask);
1317 ravb_write(ndev, mask, RIE0);
1318 ravb_write(ndev, mask, TIE);
1320 spin_unlock_irqrestore(&priv->lock, flags);
1322 /* Receive error message handling */
1323 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1324 if (info->nc_queues)
1325 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1326 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1327 ndev->stats.rx_over_errors = priv->rx_over_errors;
1328 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1329 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1331 return budget - quota;
1334 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1336 struct ravb_private *priv = netdev_priv(ndev);
1338 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1341 /* PHY state control function */
1342 static void ravb_adjust_link(struct net_device *ndev)
1344 struct ravb_private *priv = netdev_priv(ndev);
1345 const struct ravb_hw_info *info = priv->info;
1346 struct phy_device *phydev = ndev->phydev;
1347 bool new_state = false;
1348 unsigned long flags;
1350 spin_lock_irqsave(&priv->lock, flags);
1352 /* Disable TX and RX right over here, if E-MAC change is ignored */
1353 if (priv->no_avb_link)
1354 ravb_rcv_snd_disable(ndev);
1357 if (info->half_duplex && phydev->duplex != priv->duplex) {
1359 priv->duplex = phydev->duplex;
1360 ravb_set_duplex_gbeth(ndev);
1363 if (phydev->speed != priv->speed) {
1365 priv->speed = phydev->speed;
1366 info->set_rate(ndev);
1369 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1371 priv->link = phydev->link;
1373 } else if (priv->link) {
1377 if (info->half_duplex)
1381 /* Enable TX and RX right over here, if E-MAC change is ignored */
1382 if (priv->no_avb_link && phydev->link)
1383 ravb_rcv_snd_enable(ndev);
1385 spin_unlock_irqrestore(&priv->lock, flags);
1387 if (new_state && netif_msg_link(priv))
1388 phy_print_status(phydev);
1391 /* PHY init function */
1392 static int ravb_phy_init(struct net_device *ndev)
1394 struct device_node *np = ndev->dev.parent->of_node;
1395 struct ravb_private *priv = netdev_priv(ndev);
1396 const struct ravb_hw_info *info = priv->info;
1397 struct phy_device *phydev;
1398 struct device_node *pn;
1399 phy_interface_t iface;
1406 /* Try connecting to PHY */
1407 pn = of_parse_phandle(np, "phy-handle", 0);
1409 /* In the case of a fixed PHY, the DT node associated
1410 * to the PHY is the Ethernet MAC DT node.
1412 if (of_phy_is_fixed_link(np)) {
1413 err = of_phy_register_fixed_link(np);
1417 pn = of_node_get(np);
1420 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1421 : priv->phy_interface;
1422 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1425 netdev_err(ndev, "failed to connect PHY\n");
1427 goto err_deregister_fixed_link;
1430 if (!info->half_duplex) {
1431 /* 10BASE, Pause and Asym Pause is not supported */
1432 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1435 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1437 /* Half Duplex is not supported */
1438 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1442 phy_attached_info(phydev);
1446 err_deregister_fixed_link:
1447 if (of_phy_is_fixed_link(np))
1448 of_phy_deregister_fixed_link(np);
1453 /* PHY control start function */
1454 static int ravb_phy_start(struct net_device *ndev)
1458 error = ravb_phy_init(ndev);
1462 phy_start(ndev->phydev);
1467 static u32 ravb_get_msglevel(struct net_device *ndev)
1469 struct ravb_private *priv = netdev_priv(ndev);
1471 return priv->msg_enable;
1474 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1476 struct ravb_private *priv = netdev_priv(ndev);
1478 priv->msg_enable = value;
1481 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1482 "rx_queue_0_current",
1483 "tx_queue_0_current",
1486 "rx_queue_0_packets",
1487 "tx_queue_0_packets",
1490 "rx_queue_0_mcast_packets",
1491 "rx_queue_0_errors",
1492 "rx_queue_0_crc_errors",
1493 "rx_queue_0_frame_errors",
1494 "rx_queue_0_length_errors",
1495 "rx_queue_0_csum_offload_errors",
1496 "rx_queue_0_over_errors",
1499 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1500 "rx_queue_0_current",
1501 "tx_queue_0_current",
1504 "rx_queue_0_packets",
1505 "tx_queue_0_packets",
1508 "rx_queue_0_mcast_packets",
1509 "rx_queue_0_errors",
1510 "rx_queue_0_crc_errors",
1511 "rx_queue_0_frame_errors",
1512 "rx_queue_0_length_errors",
1513 "rx_queue_0_missed_errors",
1514 "rx_queue_0_over_errors",
1516 "rx_queue_1_current",
1517 "tx_queue_1_current",
1520 "rx_queue_1_packets",
1521 "tx_queue_1_packets",
1524 "rx_queue_1_mcast_packets",
1525 "rx_queue_1_errors",
1526 "rx_queue_1_crc_errors",
1527 "rx_queue_1_frame_errors",
1528 "rx_queue_1_length_errors",
1529 "rx_queue_1_missed_errors",
1530 "rx_queue_1_over_errors",
1533 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1535 struct ravb_private *priv = netdev_priv(netdev);
1536 const struct ravb_hw_info *info = priv->info;
1540 return info->stats_len;
1546 static void ravb_get_ethtool_stats(struct net_device *ndev,
1547 struct ethtool_stats *estats, u64 *data)
1549 struct ravb_private *priv = netdev_priv(ndev);
1550 const struct ravb_hw_info *info = priv->info;
1555 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1556 /* Device-specific stats */
1557 for (q = RAVB_BE; q < num_rx_q; q++) {
1558 struct net_device_stats *stats = &priv->stats[q];
1560 data[i++] = priv->cur_rx[q];
1561 data[i++] = priv->cur_tx[q];
1562 data[i++] = priv->dirty_rx[q];
1563 data[i++] = priv->dirty_tx[q];
1564 data[i++] = stats->rx_packets;
1565 data[i++] = stats->tx_packets;
1566 data[i++] = stats->rx_bytes;
1567 data[i++] = stats->tx_bytes;
1568 data[i++] = stats->multicast;
1569 data[i++] = stats->rx_errors;
1570 data[i++] = stats->rx_crc_errors;
1571 data[i++] = stats->rx_frame_errors;
1572 data[i++] = stats->rx_length_errors;
1573 data[i++] = stats->rx_missed_errors;
1574 data[i++] = stats->rx_over_errors;
1578 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1580 struct ravb_private *priv = netdev_priv(ndev);
1581 const struct ravb_hw_info *info = priv->info;
1583 switch (stringset) {
1585 memcpy(data, info->gstrings_stats, info->gstrings_size);
1590 static void ravb_get_ringparam(struct net_device *ndev,
1591 struct ethtool_ringparam *ring,
1592 struct kernel_ethtool_ringparam *kernel_ring,
1593 struct netlink_ext_ack *extack)
1595 struct ravb_private *priv = netdev_priv(ndev);
1597 ring->rx_max_pending = BE_RX_RING_MAX;
1598 ring->tx_max_pending = BE_TX_RING_MAX;
1599 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1600 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1603 static int ravb_set_ringparam(struct net_device *ndev,
1604 struct ethtool_ringparam *ring,
1605 struct kernel_ethtool_ringparam *kernel_ring,
1606 struct netlink_ext_ack *extack)
1608 struct ravb_private *priv = netdev_priv(ndev);
1609 const struct ravb_hw_info *info = priv->info;
1612 if (ring->tx_pending > BE_TX_RING_MAX ||
1613 ring->rx_pending > BE_RX_RING_MAX ||
1614 ring->tx_pending < BE_TX_RING_MIN ||
1615 ring->rx_pending < BE_RX_RING_MIN)
1617 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1620 if (netif_running(ndev)) {
1621 netif_device_detach(ndev);
1622 /* Stop PTP Clock driver */
1624 ravb_ptp_stop(ndev);
1625 /* Wait for DMA stopping */
1626 error = ravb_stop_dma(ndev);
1629 "cannot set ringparam! Any AVB processes are still running?\n");
1632 synchronize_irq(ndev->irq);
1634 /* Free all the skb's in the RX queue and the DMA buffers. */
1635 ravb_ring_free(ndev, RAVB_BE);
1636 if (info->nc_queues)
1637 ravb_ring_free(ndev, RAVB_NC);
1640 /* Set new parameters */
1641 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1642 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1644 if (netif_running(ndev)) {
1645 error = ravb_dmac_init(ndev);
1648 "%s: ravb_dmac_init() failed, error %d\n",
1653 ravb_emac_init(ndev);
1655 /* Initialise PTP Clock driver */
1657 ravb_ptp_init(ndev, priv->pdev);
1659 netif_device_attach(ndev);
1665 static int ravb_get_ts_info(struct net_device *ndev,
1666 struct ethtool_ts_info *info)
1668 struct ravb_private *priv = netdev_priv(ndev);
1669 const struct ravb_hw_info *hw_info = priv->info;
1671 info->so_timestamping =
1672 SOF_TIMESTAMPING_TX_SOFTWARE |
1673 SOF_TIMESTAMPING_RX_SOFTWARE |
1674 SOF_TIMESTAMPING_SOFTWARE |
1675 SOF_TIMESTAMPING_TX_HARDWARE |
1676 SOF_TIMESTAMPING_RX_HARDWARE |
1677 SOF_TIMESTAMPING_RAW_HARDWARE;
1678 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1680 (1 << HWTSTAMP_FILTER_NONE) |
1681 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1682 (1 << HWTSTAMP_FILTER_ALL);
1683 if (hw_info->gptp || hw_info->ccc_gac)
1684 info->phc_index = ptp_clock_index(priv->ptp.clock);
1689 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1691 struct ravb_private *priv = netdev_priv(ndev);
1693 wol->supported = WAKE_MAGIC;
1694 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1697 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1699 struct ravb_private *priv = netdev_priv(ndev);
1700 const struct ravb_hw_info *info = priv->info;
1702 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1705 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1707 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1712 static const struct ethtool_ops ravb_ethtool_ops = {
1713 .nway_reset = phy_ethtool_nway_reset,
1714 .get_msglevel = ravb_get_msglevel,
1715 .set_msglevel = ravb_set_msglevel,
1716 .get_link = ethtool_op_get_link,
1717 .get_strings = ravb_get_strings,
1718 .get_ethtool_stats = ravb_get_ethtool_stats,
1719 .get_sset_count = ravb_get_sset_count,
1720 .get_ringparam = ravb_get_ringparam,
1721 .set_ringparam = ravb_set_ringparam,
1722 .get_ts_info = ravb_get_ts_info,
1723 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1724 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1725 .get_wol = ravb_get_wol,
1726 .set_wol = ravb_set_wol,
1729 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1730 struct net_device *ndev, struct device *dev,
1736 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1739 error = request_irq(irq, handler, 0, name, ndev);
1741 netdev_err(ndev, "cannot request IRQ %s\n", name);
1746 /* Network device open function for Ethernet AVB */
1747 static int ravb_open(struct net_device *ndev)
1749 struct ravb_private *priv = netdev_priv(ndev);
1750 const struct ravb_hw_info *info = priv->info;
1751 struct platform_device *pdev = priv->pdev;
1752 struct device *dev = &pdev->dev;
1755 napi_enable(&priv->napi[RAVB_BE]);
1756 if (info->nc_queues)
1757 napi_enable(&priv->napi[RAVB_NC]);
1759 if (!info->multi_irqs) {
1760 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1763 netdev_err(ndev, "cannot request IRQ\n");
1767 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1771 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1775 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1776 ndev, dev, "ch0:rx_be");
1778 goto out_free_irq_emac;
1779 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1780 ndev, dev, "ch18:tx_be");
1782 goto out_free_irq_be_rx;
1783 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1784 ndev, dev, "ch1:rx_nc");
1786 goto out_free_irq_be_tx;
1787 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1788 ndev, dev, "ch19:tx_nc");
1790 goto out_free_irq_nc_rx;
1792 if (info->err_mgmt_irqs) {
1793 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1794 ndev, dev, "err_a");
1796 goto out_free_irq_nc_tx;
1797 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1798 ndev, dev, "mgmt_a");
1800 goto out_free_irq_erra;
1805 error = ravb_dmac_init(ndev);
1807 goto out_free_irq_mgmta;
1808 ravb_emac_init(ndev);
1810 /* Initialise PTP Clock driver */
1812 ravb_ptp_init(ndev, priv->pdev);
1814 netif_tx_start_all_queues(ndev);
1816 /* PHY control start */
1817 error = ravb_phy_start(ndev);
1824 /* Stop PTP Clock driver */
1826 ravb_ptp_stop(ndev);
1828 if (!info->multi_irqs)
1830 if (info->err_mgmt_irqs)
1831 free_irq(priv->mgmta_irq, ndev);
1833 if (info->err_mgmt_irqs)
1834 free_irq(priv->erra_irq, ndev);
1836 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1838 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1840 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1842 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1844 free_irq(priv->emac_irq, ndev);
1846 free_irq(ndev->irq, ndev);
1848 if (info->nc_queues)
1849 napi_disable(&priv->napi[RAVB_NC]);
1850 napi_disable(&priv->napi[RAVB_BE]);
1854 /* Timeout function for Ethernet AVB */
1855 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1857 struct ravb_private *priv = netdev_priv(ndev);
1859 netif_err(priv, tx_err, ndev,
1860 "transmit timed out, status %08x, resetting...\n",
1861 ravb_read(ndev, ISS));
1863 /* tx_errors count up */
1864 ndev->stats.tx_errors++;
1866 schedule_work(&priv->work);
1869 static void ravb_tx_timeout_work(struct work_struct *work)
1871 struct ravb_private *priv = container_of(work, struct ravb_private,
1873 const struct ravb_hw_info *info = priv->info;
1874 struct net_device *ndev = priv->ndev;
1877 netif_tx_stop_all_queues(ndev);
1879 /* Stop PTP Clock driver */
1881 ravb_ptp_stop(ndev);
1883 /* Wait for DMA stopping */
1884 if (ravb_stop_dma(ndev)) {
1885 /* If ravb_stop_dma() fails, the hardware is still operating
1886 * for TX and/or RX. So, this should not call the following
1887 * functions because ravb_dmac_init() is possible to fail too.
1888 * Also, this should not retry ravb_stop_dma() again and again
1889 * here because it's possible to wait forever. So, this just
1890 * re-enables the TX and RX and skip the following
1891 * re-initialization procedure.
1893 ravb_rcv_snd_enable(ndev);
1897 ravb_ring_free(ndev, RAVB_BE);
1898 if (info->nc_queues)
1899 ravb_ring_free(ndev, RAVB_NC);
1902 error = ravb_dmac_init(ndev);
1904 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1905 * should return here to avoid re-enabling the TX and RX in
1908 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1912 ravb_emac_init(ndev);
1915 /* Initialise PTP Clock driver */
1917 ravb_ptp_init(ndev, priv->pdev);
1919 netif_tx_start_all_queues(ndev);
1922 /* Packet transmit function for Ethernet AVB */
1923 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1925 struct ravb_private *priv = netdev_priv(ndev);
1926 const struct ravb_hw_info *info = priv->info;
1927 unsigned int num_tx_desc = priv->num_tx_desc;
1928 u16 q = skb_get_queue_mapping(skb);
1929 struct ravb_tstamp_skb *ts_skb;
1930 struct ravb_tx_desc *desc;
1931 unsigned long flags;
1937 spin_lock_irqsave(&priv->lock, flags);
1938 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1940 netif_err(priv, tx_queued, ndev,
1941 "still transmitting with the full ring!\n");
1942 netif_stop_subqueue(ndev, q);
1943 spin_unlock_irqrestore(&priv->lock, flags);
1944 return NETDEV_TX_BUSY;
1947 if (skb_put_padto(skb, ETH_ZLEN))
1950 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1951 priv->tx_skb[q][entry / num_tx_desc] = skb;
1953 if (num_tx_desc > 1) {
1954 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1955 entry / num_tx_desc * DPTR_ALIGN;
1956 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1958 /* Zero length DMA descriptors are problematic as they seem
1959 * to terminate DMA transfers. Avoid them by simply using a
1960 * length of DPTR_ALIGN (4) when skb data is aligned to
1963 * As skb is guaranteed to have at least ETH_ZLEN (60)
1964 * bytes of data by the call to skb_put_padto() above this
1965 * is safe with respect to both the length of the first DMA
1966 * descriptor (len) overflowing the available data and the
1967 * length of the second DMA descriptor (skb->len - len)
1973 memcpy(buffer, skb->data, len);
1974 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1976 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1979 desc = &priv->tx_ring[q][entry];
1980 desc->ds_tagl = cpu_to_le16(len);
1981 desc->dptr = cpu_to_le32(dma_addr);
1983 buffer = skb->data + len;
1984 len = skb->len - len;
1985 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1987 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1992 desc = &priv->tx_ring[q][entry];
1994 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1996 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1999 desc->ds_tagl = cpu_to_le16(len);
2000 desc->dptr = cpu_to_le32(dma_addr);
2002 /* TX timestamp required */
2003 if (info->gptp || info->ccc_gac) {
2005 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2007 if (num_tx_desc > 1) {
2009 dma_unmap_single(ndev->dev.parent, dma_addr,
2010 len, DMA_TO_DEVICE);
2014 ts_skb->skb = skb_get(skb);
2015 ts_skb->tag = priv->ts_skb_tag++;
2016 priv->ts_skb_tag &= 0x3ff;
2017 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2019 /* TAG and timestamp required flag */
2020 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2021 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2022 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2025 skb_tx_timestamp(skb);
2027 /* Descriptor type must be set after all the above writes */
2029 if (num_tx_desc > 1) {
2030 desc->die_dt = DT_FEND;
2032 desc->die_dt = DT_FSTART;
2034 desc->die_dt = DT_FSINGLE;
2036 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2038 priv->cur_tx[q] += num_tx_desc;
2039 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2040 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2041 !ravb_tx_free(ndev, q, true))
2042 netif_stop_subqueue(ndev, q);
2045 spin_unlock_irqrestore(&priv->lock, flags);
2046 return NETDEV_TX_OK;
2049 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2050 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2052 dev_kfree_skb_any(skb);
2053 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2057 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2058 struct net_device *sb_dev)
2060 /* If skb needs TX timestamp, it is handled in network control queue */
2061 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2066 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2068 struct ravb_private *priv = netdev_priv(ndev);
2069 const struct ravb_hw_info *info = priv->info;
2070 struct net_device_stats *nstats, *stats0, *stats1;
2072 nstats = &ndev->stats;
2073 stats0 = &priv->stats[RAVB_BE];
2075 if (info->tx_counters) {
2076 nstats->tx_dropped += ravb_read(ndev, TROCR);
2077 ravb_write(ndev, 0, TROCR); /* (write clear) */
2080 if (info->carrier_counters) {
2081 nstats->collisions += ravb_read(ndev, CXR41);
2082 ravb_write(ndev, 0, CXR41); /* (write clear) */
2083 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2084 ravb_write(ndev, 0, CXR42); /* (write clear) */
2087 nstats->rx_packets = stats0->rx_packets;
2088 nstats->tx_packets = stats0->tx_packets;
2089 nstats->rx_bytes = stats0->rx_bytes;
2090 nstats->tx_bytes = stats0->tx_bytes;
2091 nstats->multicast = stats0->multicast;
2092 nstats->rx_errors = stats0->rx_errors;
2093 nstats->rx_crc_errors = stats0->rx_crc_errors;
2094 nstats->rx_frame_errors = stats0->rx_frame_errors;
2095 nstats->rx_length_errors = stats0->rx_length_errors;
2096 nstats->rx_missed_errors = stats0->rx_missed_errors;
2097 nstats->rx_over_errors = stats0->rx_over_errors;
2098 if (info->nc_queues) {
2099 stats1 = &priv->stats[RAVB_NC];
2101 nstats->rx_packets += stats1->rx_packets;
2102 nstats->tx_packets += stats1->tx_packets;
2103 nstats->rx_bytes += stats1->rx_bytes;
2104 nstats->tx_bytes += stats1->tx_bytes;
2105 nstats->multicast += stats1->multicast;
2106 nstats->rx_errors += stats1->rx_errors;
2107 nstats->rx_crc_errors += stats1->rx_crc_errors;
2108 nstats->rx_frame_errors += stats1->rx_frame_errors;
2109 nstats->rx_length_errors += stats1->rx_length_errors;
2110 nstats->rx_missed_errors += stats1->rx_missed_errors;
2111 nstats->rx_over_errors += stats1->rx_over_errors;
2117 /* Update promiscuous bit */
2118 static void ravb_set_rx_mode(struct net_device *ndev)
2120 struct ravb_private *priv = netdev_priv(ndev);
2121 unsigned long flags;
2123 spin_lock_irqsave(&priv->lock, flags);
2124 ravb_modify(ndev, ECMR, ECMR_PRM,
2125 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2126 spin_unlock_irqrestore(&priv->lock, flags);
2129 /* Device close function for Ethernet AVB */
2130 static int ravb_close(struct net_device *ndev)
2132 struct device_node *np = ndev->dev.parent->of_node;
2133 struct ravb_private *priv = netdev_priv(ndev);
2134 const struct ravb_hw_info *info = priv->info;
2135 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2137 netif_tx_stop_all_queues(ndev);
2139 /* Disable interrupts by clearing the interrupt masks. */
2140 ravb_write(ndev, 0, RIC0);
2141 ravb_write(ndev, 0, RIC2);
2142 ravb_write(ndev, 0, TIC);
2144 /* Stop PTP Clock driver */
2146 ravb_ptp_stop(ndev);
2148 /* Set the config mode to stop the AVB-DMAC's processes */
2149 if (ravb_stop_dma(ndev) < 0)
2151 "device will be stopped after h/w processes are done.\n");
2153 /* Clear the timestamp list */
2154 if (info->gptp || info->ccc_gac) {
2155 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2156 list_del(&ts_skb->list);
2157 kfree_skb(ts_skb->skb);
2162 /* PHY disconnect */
2164 phy_stop(ndev->phydev);
2165 phy_disconnect(ndev->phydev);
2166 if (of_phy_is_fixed_link(np))
2167 of_phy_deregister_fixed_link(np);
2170 if (info->multi_irqs) {
2171 free_irq(priv->tx_irqs[RAVB_NC], ndev);
2172 free_irq(priv->rx_irqs[RAVB_NC], ndev);
2173 free_irq(priv->tx_irqs[RAVB_BE], ndev);
2174 free_irq(priv->rx_irqs[RAVB_BE], ndev);
2175 free_irq(priv->emac_irq, ndev);
2176 if (info->err_mgmt_irqs) {
2177 free_irq(priv->erra_irq, ndev);
2178 free_irq(priv->mgmta_irq, ndev);
2181 free_irq(ndev->irq, ndev);
2183 if (info->nc_queues)
2184 napi_disable(&priv->napi[RAVB_NC]);
2185 napi_disable(&priv->napi[RAVB_BE]);
2187 /* Free all the skb's in the RX queue and the DMA buffers. */
2188 ravb_ring_free(ndev, RAVB_BE);
2189 if (info->nc_queues)
2190 ravb_ring_free(ndev, RAVB_NC);
2195 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2197 struct ravb_private *priv = netdev_priv(ndev);
2198 struct hwtstamp_config config;
2201 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2203 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2204 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2205 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2207 case RAVB_RXTSTAMP_TYPE_ALL:
2208 config.rx_filter = HWTSTAMP_FILTER_ALL;
2211 config.rx_filter = HWTSTAMP_FILTER_NONE;
2214 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2218 /* Control hardware time stamping */
2219 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2221 struct ravb_private *priv = netdev_priv(ndev);
2222 struct hwtstamp_config config;
2223 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2226 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2229 switch (config.tx_type) {
2230 case HWTSTAMP_TX_OFF:
2233 case HWTSTAMP_TX_ON:
2234 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2240 switch (config.rx_filter) {
2241 case HWTSTAMP_FILTER_NONE:
2244 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2245 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2248 config.rx_filter = HWTSTAMP_FILTER_ALL;
2249 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2252 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2253 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2255 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2259 /* ioctl to device function */
2260 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2262 struct phy_device *phydev = ndev->phydev;
2264 if (!netif_running(ndev))
2272 return ravb_hwtstamp_get(ndev, req);
2274 return ravb_hwtstamp_set(ndev, req);
2277 return phy_mii_ioctl(phydev, req, cmd);
2280 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2282 struct ravb_private *priv = netdev_priv(ndev);
2284 ndev->mtu = new_mtu;
2286 if (netif_running(ndev)) {
2287 synchronize_irq(priv->emac_irq);
2288 ravb_emac_init(ndev);
2291 netdev_update_features(ndev);
2296 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2298 struct ravb_private *priv = netdev_priv(ndev);
2299 unsigned long flags;
2301 spin_lock_irqsave(&priv->lock, flags);
2303 /* Disable TX and RX */
2304 ravb_rcv_snd_disable(ndev);
2306 /* Modify RX Checksum setting */
2307 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2309 /* Enable TX and RX */
2310 ravb_rcv_snd_enable(ndev);
2312 spin_unlock_irqrestore(&priv->lock, flags);
2315 static int ravb_set_features_gbeth(struct net_device *ndev,
2316 netdev_features_t features)
2322 static int ravb_set_features_rcar(struct net_device *ndev,
2323 netdev_features_t features)
2325 netdev_features_t changed = ndev->features ^ features;
2327 if (changed & NETIF_F_RXCSUM)
2328 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2330 ndev->features = features;
2335 static int ravb_set_features(struct net_device *ndev,
2336 netdev_features_t features)
2338 struct ravb_private *priv = netdev_priv(ndev);
2339 const struct ravb_hw_info *info = priv->info;
2341 return info->set_feature(ndev, features);
2344 static const struct net_device_ops ravb_netdev_ops = {
2345 .ndo_open = ravb_open,
2346 .ndo_stop = ravb_close,
2347 .ndo_start_xmit = ravb_start_xmit,
2348 .ndo_select_queue = ravb_select_queue,
2349 .ndo_get_stats = ravb_get_stats,
2350 .ndo_set_rx_mode = ravb_set_rx_mode,
2351 .ndo_tx_timeout = ravb_tx_timeout,
2352 .ndo_eth_ioctl = ravb_do_ioctl,
2353 .ndo_change_mtu = ravb_change_mtu,
2354 .ndo_validate_addr = eth_validate_addr,
2355 .ndo_set_mac_address = eth_mac_addr,
2356 .ndo_set_features = ravb_set_features,
2359 /* MDIO bus init function */
2360 static int ravb_mdio_init(struct ravb_private *priv)
2362 struct platform_device *pdev = priv->pdev;
2363 struct device *dev = &pdev->dev;
2364 struct phy_device *phydev;
2365 struct device_node *pn;
2369 priv->mdiobb.ops = &bb_ops;
2371 /* MII controller setting */
2372 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2376 /* Hook up MII support for ethtool */
2377 priv->mii_bus->name = "ravb_mii";
2378 priv->mii_bus->parent = dev;
2379 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2380 pdev->name, pdev->id);
2382 /* Register MDIO bus */
2383 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2387 pn = of_parse_phandle(dev->of_node, "phy-handle", 0);
2388 phydev = of_phy_find_device(pn);
2390 phydev->mac_managed_pm = true;
2391 put_device(&phydev->mdio.dev);
2398 free_mdio_bitbang(priv->mii_bus);
2402 /* MDIO bus release function */
2403 static int ravb_mdio_release(struct ravb_private *priv)
2405 /* Unregister mdio bus */
2406 mdiobus_unregister(priv->mii_bus);
2408 /* Free bitbang info */
2409 free_mdio_bitbang(priv->mii_bus);
2414 static const struct ravb_hw_info ravb_gen3_hw_info = {
2415 .rx_ring_free = ravb_rx_ring_free_rcar,
2416 .rx_ring_format = ravb_rx_ring_format_rcar,
2417 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2418 .receive = ravb_rx_rcar,
2419 .set_rate = ravb_set_rate_rcar,
2420 .set_feature = ravb_set_features_rcar,
2421 .dmac_init = ravb_dmac_init_rcar,
2422 .emac_init = ravb_emac_init_rcar,
2423 .gstrings_stats = ravb_gstrings_stats,
2424 .gstrings_size = sizeof(ravb_gstrings_stats),
2425 .net_hw_features = NETIF_F_RXCSUM,
2426 .net_features = NETIF_F_RXCSUM,
2427 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2428 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2429 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2430 .rx_max_buf_size = SZ_2K,
2431 .internal_delay = 1,
2440 static const struct ravb_hw_info ravb_gen2_hw_info = {
2441 .rx_ring_free = ravb_rx_ring_free_rcar,
2442 .rx_ring_format = ravb_rx_ring_format_rcar,
2443 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2444 .receive = ravb_rx_rcar,
2445 .set_rate = ravb_set_rate_rcar,
2446 .set_feature = ravb_set_features_rcar,
2447 .dmac_init = ravb_dmac_init_rcar,
2448 .emac_init = ravb_emac_init_rcar,
2449 .gstrings_stats = ravb_gstrings_stats,
2450 .gstrings_size = sizeof(ravb_gstrings_stats),
2451 .net_hw_features = NETIF_F_RXCSUM,
2452 .net_features = NETIF_F_RXCSUM,
2453 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2454 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2455 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2456 .rx_max_buf_size = SZ_2K,
2463 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2464 .rx_ring_free = ravb_rx_ring_free_rcar,
2465 .rx_ring_format = ravb_rx_ring_format_rcar,
2466 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2467 .receive = ravb_rx_rcar,
2468 .set_rate = ravb_set_rate_rcar,
2469 .set_feature = ravb_set_features_rcar,
2470 .dmac_init = ravb_dmac_init_rcar,
2471 .emac_init = ravb_emac_init_rcar,
2472 .gstrings_stats = ravb_gstrings_stats,
2473 .gstrings_size = sizeof(ravb_gstrings_stats),
2474 .net_hw_features = NETIF_F_RXCSUM,
2475 .net_features = NETIF_F_RXCSUM,
2476 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2477 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2478 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2479 .rx_max_buf_size = SZ_2K,
2488 static const struct ravb_hw_info gbeth_hw_info = {
2489 .rx_ring_free = ravb_rx_ring_free_gbeth,
2490 .rx_ring_format = ravb_rx_ring_format_gbeth,
2491 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2492 .receive = ravb_rx_gbeth,
2493 .set_rate = ravb_set_rate_gbeth,
2494 .set_feature = ravb_set_features_gbeth,
2495 .dmac_init = ravb_dmac_init_gbeth,
2496 .emac_init = ravb_emac_init_gbeth,
2497 .gstrings_stats = ravb_gstrings_stats_gbeth,
2498 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2499 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2500 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2501 .tccr_mask = TCCR_TSRQ0,
2502 .rx_max_buf_size = SZ_8K,
2505 .carrier_counters = 1,
2509 static const struct of_device_id ravb_match_table[] = {
2510 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2511 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2512 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2513 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2514 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2515 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2516 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2517 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2520 MODULE_DEVICE_TABLE(of, ravb_match_table);
2522 static int ravb_set_gti(struct net_device *ndev)
2524 struct ravb_private *priv = netdev_priv(ndev);
2525 const struct ravb_hw_info *info = priv->info;
2526 struct device *dev = ndev->dev.parent;
2530 if (info->gptp_ref_clk)
2531 rate = clk_get_rate(priv->gptp_clk);
2533 rate = clk_get_rate(priv->clk);
2537 inc = div64_ul(1000000000ULL << 20, rate);
2539 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2540 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2541 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2545 ravb_write(ndev, inc, GTI);
2550 static void ravb_set_config_mode(struct net_device *ndev)
2552 struct ravb_private *priv = netdev_priv(ndev);
2553 const struct ravb_hw_info *info = priv->info;
2556 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2557 /* Set CSEL value */
2558 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2559 } else if (info->ccc_gac) {
2560 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2561 CCC_GAC | CCC_CSEL_HPB);
2563 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2567 /* Set tx and rx clock internal delay modes */
2568 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2570 struct ravb_private *priv = netdev_priv(ndev);
2571 bool explicit_delay = false;
2574 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2575 /* Valid values are 0 and 1800, according to DT bindings */
2576 priv->rxcidm = !!delay;
2577 explicit_delay = true;
2579 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2580 /* Valid values are 0 and 2000, according to DT bindings */
2581 priv->txcidm = !!delay;
2582 explicit_delay = true;
2588 /* Fall back to legacy rgmii-*id behavior */
2589 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2590 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2592 priv->rgmii_override = 1;
2595 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2596 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2598 priv->rgmii_override = 1;
2602 static void ravb_set_delay_mode(struct net_device *ndev)
2604 struct ravb_private *priv = netdev_priv(ndev);
2611 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2614 static int ravb_probe(struct platform_device *pdev)
2616 struct device_node *np = pdev->dev.of_node;
2617 const struct ravb_hw_info *info;
2618 struct reset_control *rstc;
2619 struct ravb_private *priv;
2620 struct net_device *ndev;
2622 struct resource *res;
2627 "this driver is required to be instantiated from device tree\n");
2631 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2633 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2634 "failed to get cpg reset\n");
2636 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2637 NUM_TX_QUEUE, NUM_RX_QUEUE);
2641 info = of_device_get_match_data(&pdev->dev);
2643 ndev->features = info->net_features;
2644 ndev->hw_features = info->net_hw_features;
2646 reset_control_deassert(rstc);
2647 pm_runtime_enable(&pdev->dev);
2648 pm_runtime_get_sync(&pdev->dev);
2650 if (info->multi_irqs) {
2651 if (info->err_mgmt_irqs)
2652 irq = platform_get_irq_byname(pdev, "dia");
2654 irq = platform_get_irq_byname(pdev, "ch22");
2656 irq = platform_get_irq(pdev, 0);
2664 SET_NETDEV_DEV(ndev, &pdev->dev);
2666 priv = netdev_priv(ndev);
2671 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2672 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2673 if (info->nc_queues) {
2674 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2675 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2678 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2679 if (IS_ERR(priv->addr)) {
2680 error = PTR_ERR(priv->addr);
2684 /* The Ether-specific entries in the device structure. */
2685 ndev->base_addr = res->start;
2687 spin_lock_init(&priv->lock);
2688 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2690 error = of_get_phy_mode(np, &priv->phy_interface);
2691 if (error && error != -ENODEV)
2694 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2695 priv->avb_link_active_low =
2696 of_property_read_bool(np, "renesas,ether-link-active-low");
2698 if (info->multi_irqs) {
2699 if (info->err_mgmt_irqs)
2700 irq = platform_get_irq_byname(pdev, "line3");
2702 irq = platform_get_irq_byname(pdev, "ch24");
2707 priv->emac_irq = irq;
2708 for (i = 0; i < NUM_RX_QUEUE; i++) {
2709 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2714 priv->rx_irqs[i] = irq;
2716 for (i = 0; i < NUM_TX_QUEUE; i++) {
2717 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2722 priv->tx_irqs[i] = irq;
2725 if (info->err_mgmt_irqs) {
2726 irq = platform_get_irq_byname(pdev, "err_a");
2731 priv->erra_irq = irq;
2733 irq = platform_get_irq_byname(pdev, "mgmt_a");
2738 priv->mgmta_irq = irq;
2742 priv->clk = devm_clk_get(&pdev->dev, NULL);
2743 if (IS_ERR(priv->clk)) {
2744 error = PTR_ERR(priv->clk);
2748 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2749 if (IS_ERR(priv->refclk)) {
2750 error = PTR_ERR(priv->refclk);
2753 clk_prepare_enable(priv->refclk);
2755 if (info->gptp_ref_clk) {
2756 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2757 if (IS_ERR(priv->gptp_clk)) {
2758 error = PTR_ERR(priv->gptp_clk);
2759 goto out_disable_refclk;
2761 clk_prepare_enable(priv->gptp_clk);
2764 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2765 ndev->min_mtu = ETH_MIN_MTU;
2767 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2768 * Use two descriptor to handle such situation. First descriptor to
2769 * handle aligned data buffer and second descriptor to handle the
2770 * overflow data because of alignment.
2772 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2775 ndev->netdev_ops = &ravb_netdev_ops;
2776 ndev->ethtool_ops = &ravb_ethtool_ops;
2778 /* Set AVB config mode */
2779 ravb_set_config_mode(ndev);
2781 if (info->gptp || info->ccc_gac) {
2783 error = ravb_set_gti(ndev);
2785 goto out_disable_gptp_clk;
2787 /* Request GTI loading */
2788 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2791 if (info->internal_delay) {
2792 ravb_parse_delay_mode(np, ndev);
2793 ravb_set_delay_mode(ndev);
2796 /* Allocate descriptor base address table */
2797 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2798 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2799 &priv->desc_bat_dma, GFP_KERNEL);
2800 if (!priv->desc_bat) {
2802 "Cannot allocate desc base address table (size %d bytes)\n",
2803 priv->desc_bat_size);
2805 goto out_disable_gptp_clk;
2807 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2808 priv->desc_bat[q].die_dt = DT_EOS;
2809 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2811 /* Initialise HW timestamp list */
2812 INIT_LIST_HEAD(&priv->ts_skb_list);
2814 /* Initialise PTP Clock driver */
2816 ravb_ptp_init(ndev, pdev);
2818 /* Debug message level */
2819 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2821 /* Read and set MAC address */
2822 ravb_read_mac_address(np, ndev);
2823 if (!is_valid_ether_addr(ndev->dev_addr)) {
2824 dev_warn(&pdev->dev,
2825 "no valid MAC address supplied, using a random one\n");
2826 eth_hw_addr_random(ndev);
2830 error = ravb_mdio_init(priv);
2832 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2836 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll);
2837 if (info->nc_queues)
2838 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll);
2840 /* Network device register */
2841 error = register_netdev(ndev);
2845 device_set_wakeup_capable(&pdev->dev, 1);
2847 /* Print device information */
2848 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2849 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2851 platform_set_drvdata(pdev, ndev);
2856 if (info->nc_queues)
2857 netif_napi_del(&priv->napi[RAVB_NC]);
2859 netif_napi_del(&priv->napi[RAVB_BE]);
2860 ravb_mdio_release(priv);
2862 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2863 priv->desc_bat_dma);
2865 /* Stop PTP Clock driver */
2867 ravb_ptp_stop(ndev);
2868 out_disable_gptp_clk:
2869 clk_disable_unprepare(priv->gptp_clk);
2871 clk_disable_unprepare(priv->refclk);
2875 pm_runtime_put(&pdev->dev);
2876 pm_runtime_disable(&pdev->dev);
2877 reset_control_assert(rstc);
2881 static int ravb_remove(struct platform_device *pdev)
2883 struct net_device *ndev = platform_get_drvdata(pdev);
2884 struct ravb_private *priv = netdev_priv(ndev);
2885 const struct ravb_hw_info *info = priv->info;
2887 /* Stop PTP Clock driver */
2889 ravb_ptp_stop(ndev);
2891 clk_disable_unprepare(priv->gptp_clk);
2892 clk_disable_unprepare(priv->refclk);
2894 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2895 priv->desc_bat_dma);
2896 /* Set reset mode */
2897 ravb_write(ndev, CCC_OPC_RESET, CCC);
2898 unregister_netdev(ndev);
2899 if (info->nc_queues)
2900 netif_napi_del(&priv->napi[RAVB_NC]);
2901 netif_napi_del(&priv->napi[RAVB_BE]);
2902 ravb_mdio_release(priv);
2903 pm_runtime_put_sync(&pdev->dev);
2904 pm_runtime_disable(&pdev->dev);
2905 reset_control_assert(priv->rstc);
2907 platform_set_drvdata(pdev, NULL);
2912 static int ravb_wol_setup(struct net_device *ndev)
2914 struct ravb_private *priv = netdev_priv(ndev);
2915 const struct ravb_hw_info *info = priv->info;
2917 /* Disable interrupts by clearing the interrupt masks. */
2918 ravb_write(ndev, 0, RIC0);
2919 ravb_write(ndev, 0, RIC2);
2920 ravb_write(ndev, 0, TIC);
2922 /* Only allow ECI interrupts */
2923 synchronize_irq(priv->emac_irq);
2924 if (info->nc_queues)
2925 napi_disable(&priv->napi[RAVB_NC]);
2926 napi_disable(&priv->napi[RAVB_BE]);
2927 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2929 /* Enable MagicPacket */
2930 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2932 return enable_irq_wake(priv->emac_irq);
2935 static int ravb_wol_restore(struct net_device *ndev)
2937 struct ravb_private *priv = netdev_priv(ndev);
2938 const struct ravb_hw_info *info = priv->info;
2940 if (info->nc_queues)
2941 napi_enable(&priv->napi[RAVB_NC]);
2942 napi_enable(&priv->napi[RAVB_BE]);
2944 /* Disable MagicPacket */
2945 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2949 return disable_irq_wake(priv->emac_irq);
2952 static int __maybe_unused ravb_suspend(struct device *dev)
2954 struct net_device *ndev = dev_get_drvdata(dev);
2955 struct ravb_private *priv = netdev_priv(ndev);
2958 if (!netif_running(ndev))
2961 netif_device_detach(ndev);
2963 if (priv->wol_enabled)
2964 ret = ravb_wol_setup(ndev);
2966 ret = ravb_close(ndev);
2968 if (priv->info->ccc_gac)
2969 ravb_ptp_stop(ndev);
2974 static int __maybe_unused ravb_resume(struct device *dev)
2976 struct net_device *ndev = dev_get_drvdata(dev);
2977 struct ravb_private *priv = netdev_priv(ndev);
2978 const struct ravb_hw_info *info = priv->info;
2981 /* If WoL is enabled set reset mode to rearm the WoL logic */
2982 if (priv->wol_enabled)
2983 ravb_write(ndev, CCC_OPC_RESET, CCC);
2985 /* All register have been reset to default values.
2986 * Restore all registers which where setup at probe time and
2987 * reopen device if it was running before system suspended.
2990 /* Set AVB config mode */
2991 ravb_set_config_mode(ndev);
2993 if (info->gptp || info->ccc_gac) {
2995 ret = ravb_set_gti(ndev);
2999 /* Request GTI loading */
3000 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3003 if (info->internal_delay)
3004 ravb_set_delay_mode(ndev);
3006 /* Restore descriptor base address table */
3007 ravb_write(ndev, priv->desc_bat_dma, DBAT);
3009 if (priv->info->ccc_gac)
3010 ravb_ptp_init(ndev, priv->pdev);
3012 if (netif_running(ndev)) {
3013 if (priv->wol_enabled) {
3014 ret = ravb_wol_restore(ndev);
3018 ret = ravb_open(ndev);
3021 ravb_set_rx_mode(ndev);
3022 netif_device_attach(ndev);
3028 static int __maybe_unused ravb_runtime_nop(struct device *dev)
3030 /* Runtime PM callback shared between ->runtime_suspend()
3031 * and ->runtime_resume(). Simply returns success.
3033 * This driver re-initializes all registers after
3034 * pm_runtime_get_sync() anyway so there is no need
3035 * to save and restore registers here.
3040 static const struct dev_pm_ops ravb_dev_pm_ops = {
3041 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3042 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3045 static struct platform_driver ravb_driver = {
3046 .probe = ravb_probe,
3047 .remove = ravb_remove,
3050 .pm = &ravb_dev_pm_ops,
3051 .of_match_table = ravb_match_table,
3055 module_platform_driver(ravb_driver);
3057 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3058 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3059 MODULE_LICENSE("GPL v2");