1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
8 * Based on the SuperH Ethernet driver
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/slab.h>
29 #include <linux/spinlock.h>
30 #include <linux/reset.h>
31 #include <linux/math64.h>
35 #define RAVB_DEF_MSG_ENABLE \
41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
61 for (i = 0; i < 10000; i++) {
62 if ((ravb_read(ndev, reg) & mask) == value)
69 static int ravb_config(struct net_device *ndev)
74 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
75 /* Check if the operating mode is changed to the config mode */
76 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
78 netdev_err(ndev, "failed to switch device to config mode\n");
83 static void ravb_set_rate_gbeth(struct net_device *ndev)
85 struct ravb_private *priv = netdev_priv(ndev);
87 switch (priv->speed) {
89 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
91 case 100: /* 100BASE */
92 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
94 case 1000: /* 1000BASE */
95 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
100 static void ravb_set_rate_rcar(struct net_device *ndev)
102 struct ravb_private *priv = netdev_priv(ndev);
104 switch (priv->speed) {
105 case 100: /* 100BASE */
106 ravb_write(ndev, GECMR_SPEED_100, GECMR);
108 case 1000: /* 1000BASE */
109 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
114 static void ravb_set_buffer_align(struct sk_buff *skb)
116 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
119 skb_reserve(skb, RAVB_ALIGN - reserve);
122 /* Get MAC address from the MAC address registers
124 * Ethernet AVB device doesn't have ROM for MAC address.
125 * This function gets the MAC address that was used by a bootloader.
127 static void ravb_read_mac_address(struct device_node *np,
128 struct net_device *ndev)
132 ret = of_get_ethdev_address(np, ndev);
134 u32 mahr = ravb_read(ndev, MAHR);
135 u32 malr = ravb_read(ndev, MALR);
138 addr[0] = (mahr >> 24) & 0xFF;
139 addr[1] = (mahr >> 16) & 0xFF;
140 addr[2] = (mahr >> 8) & 0xFF;
141 addr[3] = (mahr >> 0) & 0xFF;
142 addr[4] = (malr >> 8) & 0xFF;
143 addr[5] = (malr >> 0) & 0xFF;
144 eth_hw_addr_set(ndev, addr);
148 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
150 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
153 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
156 /* MDC pin control */
157 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
159 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
162 /* Data I/O pin control */
163 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
165 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
169 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
171 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
175 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
177 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
180 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
183 /* MDIO bus control struct */
184 static const struct mdiobb_ops bb_ops = {
185 .owner = THIS_MODULE,
186 .set_mdc = ravb_set_mdc,
187 .set_mdio_dir = ravb_set_mdio_dir,
188 .set_mdio_data = ravb_set_mdio_data,
189 .get_mdio_data = ravb_get_mdio_data,
192 /* Free TX skb function for AVB-IP */
193 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
195 struct ravb_private *priv = netdev_priv(ndev);
196 struct net_device_stats *stats = &priv->stats[q];
197 unsigned int num_tx_desc = priv->num_tx_desc;
198 struct ravb_tx_desc *desc;
203 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
206 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
208 desc = &priv->tx_ring[q][entry];
209 txed = desc->die_dt == DT_FEMPTY;
210 if (free_txed_only && !txed)
212 /* Descriptor type must be checked before all other reads */
214 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
215 /* Free the original skb. */
216 if (priv->tx_skb[q][entry / num_tx_desc]) {
217 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
218 size, DMA_TO_DEVICE);
219 /* Last packet descriptor? */
220 if (entry % num_tx_desc == num_tx_desc - 1) {
221 entry /= num_tx_desc;
222 dev_kfree_skb_any(priv->tx_skb[q][entry]);
223 priv->tx_skb[q][entry] = NULL;
230 stats->tx_bytes += size;
231 desc->die_dt = DT_EEMPTY;
236 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
238 struct ravb_private *priv = netdev_priv(ndev);
239 unsigned int ring_size;
242 if (!priv->gbeth_rx_ring)
245 for (i = 0; i < priv->num_rx_ring[q]; i++) {
246 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
248 if (!dma_mapping_error(ndev->dev.parent,
249 le32_to_cpu(desc->dptr)))
250 dma_unmap_single(ndev->dev.parent,
251 le32_to_cpu(desc->dptr),
255 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
256 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
257 priv->rx_desc_dma[q]);
258 priv->gbeth_rx_ring = NULL;
261 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
263 struct ravb_private *priv = netdev_priv(ndev);
264 unsigned int ring_size;
267 if (!priv->rx_ring[q])
270 for (i = 0; i < priv->num_rx_ring[q]; i++) {
271 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
273 if (!dma_mapping_error(ndev->dev.parent,
274 le32_to_cpu(desc->dptr)))
275 dma_unmap_single(ndev->dev.parent,
276 le32_to_cpu(desc->dptr),
280 ring_size = sizeof(struct ravb_ex_rx_desc) *
281 (priv->num_rx_ring[q] + 1);
282 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
283 priv->rx_desc_dma[q]);
284 priv->rx_ring[q] = NULL;
287 /* Free skb's and DMA buffers for Ethernet AVB */
288 static void ravb_ring_free(struct net_device *ndev, int q)
290 struct ravb_private *priv = netdev_priv(ndev);
291 const struct ravb_hw_info *info = priv->info;
292 unsigned int num_tx_desc = priv->num_tx_desc;
293 unsigned int ring_size;
296 info->rx_ring_free(ndev, q);
298 if (priv->tx_ring[q]) {
299 ravb_tx_free(ndev, q, false);
301 ring_size = sizeof(struct ravb_tx_desc) *
302 (priv->num_tx_ring[q] * num_tx_desc + 1);
303 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
304 priv->tx_desc_dma[q]);
305 priv->tx_ring[q] = NULL;
308 /* Free RX skb ringbuffer */
309 if (priv->rx_skb[q]) {
310 for (i = 0; i < priv->num_rx_ring[q]; i++)
311 dev_kfree_skb(priv->rx_skb[q][i]);
313 kfree(priv->rx_skb[q]);
314 priv->rx_skb[q] = NULL;
316 /* Free aligned TX buffers */
317 kfree(priv->tx_align[q]);
318 priv->tx_align[q] = NULL;
320 /* Free TX skb ringbuffer.
321 * SKBs are freed by ravb_tx_free() call above.
323 kfree(priv->tx_skb[q]);
324 priv->tx_skb[q] = NULL;
327 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
329 struct ravb_private *priv = netdev_priv(ndev);
330 struct ravb_rx_desc *rx_desc;
331 unsigned int rx_ring_size;
335 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
336 memset(priv->gbeth_rx_ring, 0, rx_ring_size);
337 /* Build RX ring buffer */
338 for (i = 0; i < priv->num_rx_ring[q]; i++) {
340 rx_desc = &priv->gbeth_rx_ring[i];
341 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
342 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
345 /* We just set the data size to 0 for a failed mapping which
346 * should prevent DMA from happening...
348 if (dma_mapping_error(ndev->dev.parent, dma_addr))
349 rx_desc->ds_cc = cpu_to_le16(0);
350 rx_desc->dptr = cpu_to_le32(dma_addr);
351 rx_desc->die_dt = DT_FEMPTY;
353 rx_desc = &priv->gbeth_rx_ring[i];
354 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
355 rx_desc->die_dt = DT_LINKFIX; /* type */
358 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
360 struct ravb_private *priv = netdev_priv(ndev);
361 struct ravb_ex_rx_desc *rx_desc;
362 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
366 memset(priv->rx_ring[q], 0, rx_ring_size);
367 /* Build RX ring buffer */
368 for (i = 0; i < priv->num_rx_ring[q]; i++) {
370 rx_desc = &priv->rx_ring[q][i];
371 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
372 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
375 /* We just set the data size to 0 for a failed mapping which
376 * should prevent DMA from happening...
378 if (dma_mapping_error(ndev->dev.parent, dma_addr))
379 rx_desc->ds_cc = cpu_to_le16(0);
380 rx_desc->dptr = cpu_to_le32(dma_addr);
381 rx_desc->die_dt = DT_FEMPTY;
383 rx_desc = &priv->rx_ring[q][i];
384 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
385 rx_desc->die_dt = DT_LINKFIX; /* type */
388 /* Format skb and descriptor buffer for Ethernet AVB */
389 static void ravb_ring_format(struct net_device *ndev, int q)
391 struct ravb_private *priv = netdev_priv(ndev);
392 const struct ravb_hw_info *info = priv->info;
393 unsigned int num_tx_desc = priv->num_tx_desc;
394 struct ravb_tx_desc *tx_desc;
395 struct ravb_desc *desc;
396 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
402 priv->dirty_rx[q] = 0;
403 priv->dirty_tx[q] = 0;
405 info->rx_ring_format(ndev, q);
407 memset(priv->tx_ring[q], 0, tx_ring_size);
408 /* Build TX ring buffer */
409 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
411 tx_desc->die_dt = DT_EEMPTY;
412 if (num_tx_desc > 1) {
414 tx_desc->die_dt = DT_EEMPTY;
417 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
418 tx_desc->die_dt = DT_LINKFIX; /* type */
420 /* RX descriptor base address for best effort */
421 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
422 desc->die_dt = DT_LINKFIX; /* type */
423 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
425 /* TX descriptor base address for best effort */
426 desc = &priv->desc_bat[q];
427 desc->die_dt = DT_LINKFIX; /* type */
428 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
431 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
433 struct ravb_private *priv = netdev_priv(ndev);
434 unsigned int ring_size;
436 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
438 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
439 &priv->rx_desc_dma[q],
441 return priv->gbeth_rx_ring;
444 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
446 struct ravb_private *priv = netdev_priv(ndev);
447 unsigned int ring_size;
449 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
451 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
452 &priv->rx_desc_dma[q],
454 return priv->rx_ring[q];
457 /* Init skb and descriptor buffer for Ethernet AVB */
458 static int ravb_ring_init(struct net_device *ndev, int q)
460 struct ravb_private *priv = netdev_priv(ndev);
461 const struct ravb_hw_info *info = priv->info;
462 unsigned int num_tx_desc = priv->num_tx_desc;
463 unsigned int ring_size;
467 /* Allocate RX and TX skb rings */
468 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
469 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
470 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
471 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
472 if (!priv->rx_skb[q] || !priv->tx_skb[q])
475 for (i = 0; i < priv->num_rx_ring[q]; i++) {
476 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
479 ravb_set_buffer_align(skb);
480 priv->rx_skb[q][i] = skb;
483 if (num_tx_desc > 1) {
484 /* Allocate rings for the aligned buffers */
485 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
486 DPTR_ALIGN - 1, GFP_KERNEL);
487 if (!priv->tx_align[q])
491 /* Allocate all RX descriptors. */
492 if (!info->alloc_rx_desc(ndev, q))
495 priv->dirty_rx[q] = 0;
497 /* Allocate all TX descriptors. */
498 ring_size = sizeof(struct ravb_tx_desc) *
499 (priv->num_tx_ring[q] * num_tx_desc + 1);
500 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
501 &priv->tx_desc_dma[q],
503 if (!priv->tx_ring[q])
509 ravb_ring_free(ndev, q);
514 static void ravb_emac_init_gbeth(struct net_device *ndev)
516 struct ravb_private *priv = netdev_priv(ndev);
518 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
519 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
520 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
522 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);
523 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
527 /* Receive frame limit set register */
528 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
530 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
531 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
532 ECMR_TE | ECMR_RE | ECMR_RCPT |
533 ECMR_TXF | ECMR_RXF, ECMR);
535 ravb_set_rate_gbeth(ndev);
537 /* Set MAC address */
539 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
540 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
541 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
543 /* E-MAC status register clear */
544 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
545 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
547 /* E-MAC interrupt enable register */
548 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
551 static void ravb_emac_init_rcar(struct net_device *ndev)
553 /* Receive frame limit set register */
554 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
556 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
557 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
558 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
559 ECMR_TE | ECMR_RE, ECMR);
561 ravb_set_rate_rcar(ndev);
563 /* Set MAC address */
565 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
566 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
568 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
570 /* E-MAC status register clear */
571 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
573 /* E-MAC interrupt enable register */
574 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
577 /* E-MAC init function */
578 static void ravb_emac_init(struct net_device *ndev)
580 struct ravb_private *priv = netdev_priv(ndev);
581 const struct ravb_hw_info *info = priv->info;
583 info->emac_init(ndev);
586 static int ravb_dmac_init_gbeth(struct net_device *ndev)
590 error = ravb_ring_init(ndev, RAVB_BE);
594 /* Descriptor format */
595 ravb_ring_format(ndev, RAVB_BE);
598 ravb_write(ndev, 0x60000000, RCR);
600 /* Set Max Frame Length (RTC) */
601 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
604 ravb_write(ndev, 0x00222200, TGC);
606 ravb_write(ndev, 0, TCCR);
609 ravb_write(ndev, RIC0_FRE0, RIC0);
610 /* Disable FIFO full warning */
611 ravb_write(ndev, 0x0, RIC1);
612 /* Receive FIFO full error, descriptor empty */
613 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
615 ravb_write(ndev, TIC_FTE0, TIC);
620 static int ravb_dmac_init_rcar(struct net_device *ndev)
622 struct ravb_private *priv = netdev_priv(ndev);
623 const struct ravb_hw_info *info = priv->info;
626 error = ravb_ring_init(ndev, RAVB_BE);
629 error = ravb_ring_init(ndev, RAVB_NC);
631 ravb_ring_free(ndev, RAVB_BE);
635 /* Descriptor format */
636 ravb_ring_format(ndev, RAVB_BE);
637 ravb_ring_format(ndev, RAVB_NC);
641 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
644 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
646 /* Timestamp enable */
647 ravb_write(ndev, TCCR_TFEN, TCCR);
649 /* Interrupt init: */
650 if (info->multi_irqs) {
652 ravb_write(ndev, 0, DIL);
653 /* Set queue specific interrupt */
654 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
657 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
658 /* Disable FIFO full warning */
659 ravb_write(ndev, 0, RIC1);
660 /* Receive FIFO full error, descriptor empty */
661 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
662 /* Frame transmitted, timestamp FIFO updated */
663 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
668 /* Device init function for Ethernet AVB */
669 static int ravb_dmac_init(struct net_device *ndev)
671 struct ravb_private *priv = netdev_priv(ndev);
672 const struct ravb_hw_info *info = priv->info;
675 /* Set CONFIG mode */
676 error = ravb_config(ndev);
680 error = info->dmac_init(ndev);
684 /* Setting the control will start the AVB-DMAC process. */
685 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
690 static void ravb_get_tx_tstamp(struct net_device *ndev)
692 struct ravb_private *priv = netdev_priv(ndev);
693 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
694 struct skb_shared_hwtstamps shhwtstamps;
696 struct timespec64 ts;
701 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
703 tfa2 = ravb_read(ndev, TFA2);
704 tfa_tag = (tfa2 & TFA2_TST) >> 16;
705 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
706 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
707 ravb_read(ndev, TFA1);
708 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
709 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
710 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
714 list_del(&ts_skb->list);
716 if (tag == tfa_tag) {
717 skb_tstamp_tx(skb, &shhwtstamps);
718 dev_consume_skb_any(skb);
721 dev_kfree_skb_any(skb);
724 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
728 static void ravb_rx_csum(struct sk_buff *skb)
732 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
733 * appended to packet data
735 if (unlikely(skb->len < sizeof(__sum16)))
737 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
738 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
739 skb->ip_summed = CHECKSUM_COMPLETE;
740 skb_trim(skb, skb->len - sizeof(__sum16));
743 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
744 struct ravb_rx_desc *desc)
746 struct ravb_private *priv = netdev_priv(ndev);
749 skb = priv->rx_skb[RAVB_BE][entry];
750 priv->rx_skb[RAVB_BE][entry] = NULL;
751 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
752 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
757 /* Packet receive function for Gigabit Ethernet */
758 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
760 struct ravb_private *priv = netdev_priv(ndev);
761 const struct ravb_hw_info *info = priv->info;
762 struct net_device_stats *stats;
763 struct ravb_rx_desc *desc;
773 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
774 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
775 stats = &priv->stats[q];
777 boguscnt = min(boguscnt, *quota);
779 desc = &priv->gbeth_rx_ring[entry];
780 while (desc->die_dt != DT_FEMPTY) {
781 /* Descriptor type must be checked before all other reads */
783 desc_status = desc->msc;
784 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
789 /* We use 0-byte descriptors to mark the DMA mapping errors */
793 if (desc_status & MSC_MC)
796 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
798 if (desc_status & MSC_CRC)
799 stats->rx_crc_errors++;
800 if (desc_status & MSC_RFE)
801 stats->rx_frame_errors++;
802 if (desc_status & (MSC_RTLF | MSC_RTSF))
803 stats->rx_length_errors++;
804 if (desc_status & MSC_CEEF)
805 stats->rx_missed_errors++;
807 die_dt = desc->die_dt & 0xF0;
810 skb = ravb_get_skb_gbeth(ndev, entry, desc);
811 skb_put(skb, pkt_len);
812 skb->protocol = eth_type_trans(skb, ndev);
813 napi_gro_receive(&priv->napi[q], skb);
815 stats->rx_bytes += pkt_len;
818 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
819 skb_put(priv->rx_1st_skb, pkt_len);
822 skb = ravb_get_skb_gbeth(ndev, entry, desc);
823 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
824 priv->rx_1st_skb->len,
827 skb_put(priv->rx_1st_skb, pkt_len);
831 skb = ravb_get_skb_gbeth(ndev, entry, desc);
832 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
833 priv->rx_1st_skb->len,
836 skb_put(priv->rx_1st_skb, pkt_len);
838 priv->rx_1st_skb->protocol =
839 eth_type_trans(priv->rx_1st_skb, ndev);
840 napi_gro_receive(&priv->napi[q],
843 stats->rx_bytes += pkt_len;
848 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
849 desc = &priv->gbeth_rx_ring[entry];
852 /* Refill the RX ring buffers. */
853 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
854 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
855 desc = &priv->gbeth_rx_ring[entry];
856 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
858 if (!priv->rx_skb[q][entry]) {
859 skb = netdev_alloc_skb(ndev, info->max_rx_len);
862 ravb_set_buffer_align(skb);
863 dma_addr = dma_map_single(ndev->dev.parent,
867 skb_checksum_none_assert(skb);
868 /* We just set the data size to 0 for a failed mapping
869 * which should prevent DMA from happening...
871 if (dma_mapping_error(ndev->dev.parent, dma_addr))
872 desc->ds_cc = cpu_to_le16(0);
873 desc->dptr = cpu_to_le32(dma_addr);
874 priv->rx_skb[q][entry] = skb;
876 /* Descriptor type must be set after all the above writes */
878 desc->die_dt = DT_FEMPTY;
881 *quota -= limit - (++boguscnt);
883 return boguscnt <= 0;
886 /* Packet receive function for Ethernet AVB */
887 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
889 struct ravb_private *priv = netdev_priv(ndev);
890 const struct ravb_hw_info *info = priv->info;
891 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
892 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
894 struct net_device_stats *stats = &priv->stats[q];
895 struct ravb_ex_rx_desc *desc;
898 struct timespec64 ts;
903 boguscnt = min(boguscnt, *quota);
905 desc = &priv->rx_ring[q][entry];
906 while (desc->die_dt != DT_FEMPTY) {
907 /* Descriptor type must be checked before all other reads */
909 desc_status = desc->msc;
910 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
915 /* We use 0-byte descriptors to mark the DMA mapping errors */
919 if (desc_status & MSC_MC)
922 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
925 if (desc_status & MSC_CRC)
926 stats->rx_crc_errors++;
927 if (desc_status & MSC_RFE)
928 stats->rx_frame_errors++;
929 if (desc_status & (MSC_RTLF | MSC_RTSF))
930 stats->rx_length_errors++;
931 if (desc_status & MSC_CEEF)
932 stats->rx_missed_errors++;
934 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
936 skb = priv->rx_skb[q][entry];
937 priv->rx_skb[q][entry] = NULL;
938 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
941 get_ts &= (q == RAVB_NC) ?
942 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
943 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
945 struct skb_shared_hwtstamps *shhwtstamps;
947 shhwtstamps = skb_hwtstamps(skb);
948 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
949 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
950 32) | le32_to_cpu(desc->ts_sl);
951 ts.tv_nsec = le32_to_cpu(desc->ts_n);
952 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
955 skb_put(skb, pkt_len);
956 skb->protocol = eth_type_trans(skb, ndev);
957 if (ndev->features & NETIF_F_RXCSUM)
959 napi_gro_receive(&priv->napi[q], skb);
961 stats->rx_bytes += pkt_len;
964 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
965 desc = &priv->rx_ring[q][entry];
968 /* Refill the RX ring buffers. */
969 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
970 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
971 desc = &priv->rx_ring[q][entry];
972 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
974 if (!priv->rx_skb[q][entry]) {
975 skb = netdev_alloc_skb(ndev, info->max_rx_len);
977 break; /* Better luck next round. */
978 ravb_set_buffer_align(skb);
979 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
980 le16_to_cpu(desc->ds_cc),
982 skb_checksum_none_assert(skb);
983 /* We just set the data size to 0 for a failed mapping
984 * which should prevent DMA from happening...
986 if (dma_mapping_error(ndev->dev.parent, dma_addr))
987 desc->ds_cc = cpu_to_le16(0);
988 desc->dptr = cpu_to_le32(dma_addr);
989 priv->rx_skb[q][entry] = skb;
991 /* Descriptor type must be set after all the above writes */
993 desc->die_dt = DT_FEMPTY;
996 *quota -= limit - (++boguscnt);
998 return boguscnt <= 0;
1001 /* Packet receive function for Ethernet AVB */
1002 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1004 struct ravb_private *priv = netdev_priv(ndev);
1005 const struct ravb_hw_info *info = priv->info;
1007 return info->receive(ndev, quota, q);
1010 static void ravb_rcv_snd_disable(struct net_device *ndev)
1012 /* Disable TX and RX */
1013 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1016 static void ravb_rcv_snd_enable(struct net_device *ndev)
1018 /* Enable TX and RX */
1019 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1022 /* function for waiting dma process finished */
1023 static int ravb_stop_dma(struct net_device *ndev)
1025 struct ravb_private *priv = netdev_priv(ndev);
1026 const struct ravb_hw_info *info = priv->info;
1029 /* Wait for stopping the hardware TX process */
1030 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1035 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1040 /* Stop the E-MAC's RX/TX processes. */
1041 ravb_rcv_snd_disable(ndev);
1043 /* Wait for stopping the RX DMA process */
1044 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1048 /* Stop AVB-DMAC process */
1049 return ravb_config(ndev);
1052 /* E-MAC interrupt handler */
1053 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1055 struct ravb_private *priv = netdev_priv(ndev);
1058 ecsr = ravb_read(ndev, ECSR);
1059 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1061 if (ecsr & ECSR_MPD)
1062 pm_wakeup_event(&priv->pdev->dev, 0);
1063 if (ecsr & ECSR_ICD)
1064 ndev->stats.tx_carrier_errors++;
1065 if (ecsr & ECSR_LCHNG) {
1067 if (priv->no_avb_link)
1069 psr = ravb_read(ndev, PSR);
1070 if (priv->avb_link_active_low)
1072 if (!(psr & PSR_LMON)) {
1073 /* DIsable RX and TX */
1074 ravb_rcv_snd_disable(ndev);
1076 /* Enable RX and TX */
1077 ravb_rcv_snd_enable(ndev);
1082 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1084 struct net_device *ndev = dev_id;
1085 struct ravb_private *priv = netdev_priv(ndev);
1087 spin_lock(&priv->lock);
1088 ravb_emac_interrupt_unlocked(ndev);
1089 spin_unlock(&priv->lock);
1093 /* Error interrupt handler */
1094 static void ravb_error_interrupt(struct net_device *ndev)
1096 struct ravb_private *priv = netdev_priv(ndev);
1099 eis = ravb_read(ndev, EIS);
1100 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1101 if (eis & EIS_QFS) {
1102 ris2 = ravb_read(ndev, RIS2);
1103 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
1106 /* Receive Descriptor Empty int */
1107 if (ris2 & RIS2_QFF0)
1108 priv->stats[RAVB_BE].rx_over_errors++;
1110 /* Receive Descriptor Empty int */
1111 if (ris2 & RIS2_QFF1)
1112 priv->stats[RAVB_NC].rx_over_errors++;
1114 /* Receive FIFO Overflow int */
1115 if (ris2 & RIS2_RFFF)
1116 priv->rx_fifo_errors++;
1120 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1122 struct ravb_private *priv = netdev_priv(ndev);
1123 const struct ravb_hw_info *info = priv->info;
1124 u32 ris0 = ravb_read(ndev, RIS0);
1125 u32 ric0 = ravb_read(ndev, RIC0);
1126 u32 tis = ravb_read(ndev, TIS);
1127 u32 tic = ravb_read(ndev, TIC);
1129 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1130 if (napi_schedule_prep(&priv->napi[q])) {
1131 /* Mask RX and TX interrupts */
1132 if (!info->irq_en_dis) {
1133 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1134 ravb_write(ndev, tic & ~BIT(q), TIC);
1136 ravb_write(ndev, BIT(q), RID0);
1137 ravb_write(ndev, BIT(q), TID);
1139 __napi_schedule(&priv->napi[q]);
1142 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1145 " tx status 0x%08x, tx mask 0x%08x.\n",
1153 static bool ravb_timestamp_interrupt(struct net_device *ndev)
1155 u32 tis = ravb_read(ndev, TIS);
1157 if (tis & TIS_TFUF) {
1158 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1159 ravb_get_tx_tstamp(ndev);
1165 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1167 struct net_device *ndev = dev_id;
1168 struct ravb_private *priv = netdev_priv(ndev);
1169 const struct ravb_hw_info *info = priv->info;
1170 irqreturn_t result = IRQ_NONE;
1173 spin_lock(&priv->lock);
1174 /* Get interrupt status */
1175 iss = ravb_read(ndev, ISS);
1177 /* Received and transmitted interrupts */
1178 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1181 /* Timestamp updated */
1182 if (ravb_timestamp_interrupt(ndev))
1183 result = IRQ_HANDLED;
1185 /* Network control and best effort queue RX/TX */
1186 if (info->nc_queues) {
1187 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1188 if (ravb_queue_interrupt(ndev, q))
1189 result = IRQ_HANDLED;
1192 if (ravb_queue_interrupt(ndev, RAVB_BE))
1193 result = IRQ_HANDLED;
1197 /* E-MAC status summary */
1199 ravb_emac_interrupt_unlocked(ndev);
1200 result = IRQ_HANDLED;
1203 /* Error status summary */
1205 ravb_error_interrupt(ndev);
1206 result = IRQ_HANDLED;
1209 /* gPTP interrupt status summary */
1210 if (iss & ISS_CGIS) {
1211 ravb_ptp_interrupt(ndev);
1212 result = IRQ_HANDLED;
1215 spin_unlock(&priv->lock);
1219 /* Timestamp/Error/gPTP interrupt handler */
1220 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1222 struct net_device *ndev = dev_id;
1223 struct ravb_private *priv = netdev_priv(ndev);
1224 irqreturn_t result = IRQ_NONE;
1227 spin_lock(&priv->lock);
1228 /* Get interrupt status */
1229 iss = ravb_read(ndev, ISS);
1231 /* Timestamp updated */
1232 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1233 result = IRQ_HANDLED;
1235 /* Error status summary */
1237 ravb_error_interrupt(ndev);
1238 result = IRQ_HANDLED;
1241 /* gPTP interrupt status summary */
1242 if (iss & ISS_CGIS) {
1243 ravb_ptp_interrupt(ndev);
1244 result = IRQ_HANDLED;
1247 spin_unlock(&priv->lock);
1251 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1253 struct net_device *ndev = dev_id;
1254 struct ravb_private *priv = netdev_priv(ndev);
1255 irqreturn_t result = IRQ_NONE;
1257 spin_lock(&priv->lock);
1259 /* Network control/Best effort queue RX/TX */
1260 if (ravb_queue_interrupt(ndev, q))
1261 result = IRQ_HANDLED;
1263 spin_unlock(&priv->lock);
1267 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1269 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1272 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1274 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1277 static int ravb_poll(struct napi_struct *napi, int budget)
1279 struct net_device *ndev = napi->dev;
1280 struct ravb_private *priv = netdev_priv(ndev);
1281 const struct ravb_hw_info *info = priv->info;
1282 bool gptp = info->gptp || info->ccc_gac;
1283 struct ravb_rx_desc *desc;
1284 unsigned long flags;
1285 int q = napi - priv->napi;
1291 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
1292 desc = &priv->gbeth_rx_ring[entry];
1294 /* Processing RX Descriptor Ring */
1295 /* Clear RX interrupt */
1296 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1297 if (gptp || desc->die_dt != DT_FEMPTY) {
1298 if (ravb_rx(ndev, "a, q))
1302 /* Processing TX Descriptor Ring */
1303 spin_lock_irqsave(&priv->lock, flags);
1304 /* Clear TX interrupt */
1305 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1306 ravb_tx_free(ndev, q, true);
1307 netif_wake_subqueue(ndev, q);
1308 spin_unlock_irqrestore(&priv->lock, flags);
1310 napi_complete(napi);
1312 /* Re-enable RX/TX interrupts */
1313 spin_lock_irqsave(&priv->lock, flags);
1314 if (!info->irq_en_dis) {
1315 ravb_modify(ndev, RIC0, mask, mask);
1316 ravb_modify(ndev, TIC, mask, mask);
1318 ravb_write(ndev, mask, RIE0);
1319 ravb_write(ndev, mask, TIE);
1321 spin_unlock_irqrestore(&priv->lock, flags);
1323 /* Receive error message handling */
1324 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1325 if (info->nc_queues)
1326 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1327 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1328 ndev->stats.rx_over_errors = priv->rx_over_errors;
1329 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1330 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1332 return budget - quota;
1335 static void ravb_set_duplex_gbeth(struct net_device *ndev)
1337 struct ravb_private *priv = netdev_priv(ndev);
1339 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1342 /* PHY state control function */
1343 static void ravb_adjust_link(struct net_device *ndev)
1345 struct ravb_private *priv = netdev_priv(ndev);
1346 const struct ravb_hw_info *info = priv->info;
1347 struct phy_device *phydev = ndev->phydev;
1348 bool new_state = false;
1349 unsigned long flags;
1351 spin_lock_irqsave(&priv->lock, flags);
1353 /* Disable TX and RX right over here, if E-MAC change is ignored */
1354 if (priv->no_avb_link)
1355 ravb_rcv_snd_disable(ndev);
1358 if (info->half_duplex && phydev->duplex != priv->duplex) {
1360 priv->duplex = phydev->duplex;
1361 ravb_set_duplex_gbeth(ndev);
1364 if (phydev->speed != priv->speed) {
1366 priv->speed = phydev->speed;
1367 info->set_rate(ndev);
1370 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1372 priv->link = phydev->link;
1374 } else if (priv->link) {
1378 if (info->half_duplex)
1382 /* Enable TX and RX right over here, if E-MAC change is ignored */
1383 if (priv->no_avb_link && phydev->link)
1384 ravb_rcv_snd_enable(ndev);
1386 spin_unlock_irqrestore(&priv->lock, flags);
1388 if (new_state && netif_msg_link(priv))
1389 phy_print_status(phydev);
1392 /* PHY init function */
1393 static int ravb_phy_init(struct net_device *ndev)
1395 struct device_node *np = ndev->dev.parent->of_node;
1396 struct ravb_private *priv = netdev_priv(ndev);
1397 const struct ravb_hw_info *info = priv->info;
1398 struct phy_device *phydev;
1399 struct device_node *pn;
1400 phy_interface_t iface;
1407 /* Try connecting to PHY */
1408 pn = of_parse_phandle(np, "phy-handle", 0);
1410 /* In the case of a fixed PHY, the DT node associated
1411 * to the PHY is the Ethernet MAC DT node.
1413 if (of_phy_is_fixed_link(np)) {
1414 err = of_phy_register_fixed_link(np);
1418 pn = of_node_get(np);
1421 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1422 : priv->phy_interface;
1423 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1426 netdev_err(ndev, "failed to connect PHY\n");
1428 goto err_deregister_fixed_link;
1431 if (!info->half_duplex) {
1432 /* 10BASE, Pause and Asym Pause is not supported */
1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1435 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1436 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1438 /* Half Duplex is not supported */
1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1440 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1443 phy_attached_info(phydev);
1447 err_deregister_fixed_link:
1448 if (of_phy_is_fixed_link(np))
1449 of_phy_deregister_fixed_link(np);
1454 /* PHY control start function */
1455 static int ravb_phy_start(struct net_device *ndev)
1459 error = ravb_phy_init(ndev);
1463 phy_start(ndev->phydev);
1468 static u32 ravb_get_msglevel(struct net_device *ndev)
1470 struct ravb_private *priv = netdev_priv(ndev);
1472 return priv->msg_enable;
1475 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1477 struct ravb_private *priv = netdev_priv(ndev);
1479 priv->msg_enable = value;
1482 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1483 "rx_queue_0_current",
1484 "tx_queue_0_current",
1487 "rx_queue_0_packets",
1488 "tx_queue_0_packets",
1491 "rx_queue_0_mcast_packets",
1492 "rx_queue_0_errors",
1493 "rx_queue_0_crc_errors",
1494 "rx_queue_0_frame_errors",
1495 "rx_queue_0_length_errors",
1496 "rx_queue_0_csum_offload_errors",
1497 "rx_queue_0_over_errors",
1500 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1501 "rx_queue_0_current",
1502 "tx_queue_0_current",
1505 "rx_queue_0_packets",
1506 "tx_queue_0_packets",
1509 "rx_queue_0_mcast_packets",
1510 "rx_queue_0_errors",
1511 "rx_queue_0_crc_errors",
1512 "rx_queue_0_frame_errors",
1513 "rx_queue_0_length_errors",
1514 "rx_queue_0_missed_errors",
1515 "rx_queue_0_over_errors",
1517 "rx_queue_1_current",
1518 "tx_queue_1_current",
1521 "rx_queue_1_packets",
1522 "tx_queue_1_packets",
1525 "rx_queue_1_mcast_packets",
1526 "rx_queue_1_errors",
1527 "rx_queue_1_crc_errors",
1528 "rx_queue_1_frame_errors",
1529 "rx_queue_1_length_errors",
1530 "rx_queue_1_missed_errors",
1531 "rx_queue_1_over_errors",
1534 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1536 struct ravb_private *priv = netdev_priv(netdev);
1537 const struct ravb_hw_info *info = priv->info;
1541 return info->stats_len;
1547 static void ravb_get_ethtool_stats(struct net_device *ndev,
1548 struct ethtool_stats *estats, u64 *data)
1550 struct ravb_private *priv = netdev_priv(ndev);
1551 const struct ravb_hw_info *info = priv->info;
1556 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1557 /* Device-specific stats */
1558 for (q = RAVB_BE; q < num_rx_q; q++) {
1559 struct net_device_stats *stats = &priv->stats[q];
1561 data[i++] = priv->cur_rx[q];
1562 data[i++] = priv->cur_tx[q];
1563 data[i++] = priv->dirty_rx[q];
1564 data[i++] = priv->dirty_tx[q];
1565 data[i++] = stats->rx_packets;
1566 data[i++] = stats->tx_packets;
1567 data[i++] = stats->rx_bytes;
1568 data[i++] = stats->tx_bytes;
1569 data[i++] = stats->multicast;
1570 data[i++] = stats->rx_errors;
1571 data[i++] = stats->rx_crc_errors;
1572 data[i++] = stats->rx_frame_errors;
1573 data[i++] = stats->rx_length_errors;
1574 data[i++] = stats->rx_missed_errors;
1575 data[i++] = stats->rx_over_errors;
1579 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1581 struct ravb_private *priv = netdev_priv(ndev);
1582 const struct ravb_hw_info *info = priv->info;
1584 switch (stringset) {
1586 memcpy(data, info->gstrings_stats, info->gstrings_size);
1591 static void ravb_get_ringparam(struct net_device *ndev,
1592 struct ethtool_ringparam *ring,
1593 struct kernel_ethtool_ringparam *kernel_ring,
1594 struct netlink_ext_ack *extack)
1596 struct ravb_private *priv = netdev_priv(ndev);
1598 ring->rx_max_pending = BE_RX_RING_MAX;
1599 ring->tx_max_pending = BE_TX_RING_MAX;
1600 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1601 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1604 static int ravb_set_ringparam(struct net_device *ndev,
1605 struct ethtool_ringparam *ring,
1606 struct kernel_ethtool_ringparam *kernel_ring,
1607 struct netlink_ext_ack *extack)
1609 struct ravb_private *priv = netdev_priv(ndev);
1610 const struct ravb_hw_info *info = priv->info;
1613 if (ring->tx_pending > BE_TX_RING_MAX ||
1614 ring->rx_pending > BE_RX_RING_MAX ||
1615 ring->tx_pending < BE_TX_RING_MIN ||
1616 ring->rx_pending < BE_RX_RING_MIN)
1618 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1621 if (netif_running(ndev)) {
1622 netif_device_detach(ndev);
1623 /* Stop PTP Clock driver */
1625 ravb_ptp_stop(ndev);
1626 /* Wait for DMA stopping */
1627 error = ravb_stop_dma(ndev);
1630 "cannot set ringparam! Any AVB processes are still running?\n");
1633 synchronize_irq(ndev->irq);
1635 /* Free all the skb's in the RX queue and the DMA buffers. */
1636 ravb_ring_free(ndev, RAVB_BE);
1637 if (info->nc_queues)
1638 ravb_ring_free(ndev, RAVB_NC);
1641 /* Set new parameters */
1642 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1643 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1645 if (netif_running(ndev)) {
1646 error = ravb_dmac_init(ndev);
1649 "%s: ravb_dmac_init() failed, error %d\n",
1654 ravb_emac_init(ndev);
1656 /* Initialise PTP Clock driver */
1658 ravb_ptp_init(ndev, priv->pdev);
1660 netif_device_attach(ndev);
1666 static int ravb_get_ts_info(struct net_device *ndev,
1667 struct ethtool_ts_info *info)
1669 struct ravb_private *priv = netdev_priv(ndev);
1670 const struct ravb_hw_info *hw_info = priv->info;
1672 info->so_timestamping =
1673 SOF_TIMESTAMPING_TX_SOFTWARE |
1674 SOF_TIMESTAMPING_RX_SOFTWARE |
1675 SOF_TIMESTAMPING_SOFTWARE |
1676 SOF_TIMESTAMPING_TX_HARDWARE |
1677 SOF_TIMESTAMPING_RX_HARDWARE |
1678 SOF_TIMESTAMPING_RAW_HARDWARE;
1679 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1681 (1 << HWTSTAMP_FILTER_NONE) |
1682 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1683 (1 << HWTSTAMP_FILTER_ALL);
1684 if (hw_info->gptp || hw_info->ccc_gac)
1685 info->phc_index = ptp_clock_index(priv->ptp.clock);
1690 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1692 struct ravb_private *priv = netdev_priv(ndev);
1694 wol->supported = WAKE_MAGIC;
1695 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1698 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1700 struct ravb_private *priv = netdev_priv(ndev);
1701 const struct ravb_hw_info *info = priv->info;
1703 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1706 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1708 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1713 static const struct ethtool_ops ravb_ethtool_ops = {
1714 .nway_reset = phy_ethtool_nway_reset,
1715 .get_msglevel = ravb_get_msglevel,
1716 .set_msglevel = ravb_set_msglevel,
1717 .get_link = ethtool_op_get_link,
1718 .get_strings = ravb_get_strings,
1719 .get_ethtool_stats = ravb_get_ethtool_stats,
1720 .get_sset_count = ravb_get_sset_count,
1721 .get_ringparam = ravb_get_ringparam,
1722 .set_ringparam = ravb_set_ringparam,
1723 .get_ts_info = ravb_get_ts_info,
1724 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1725 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1726 .get_wol = ravb_get_wol,
1727 .set_wol = ravb_set_wol,
1730 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1731 struct net_device *ndev, struct device *dev,
1737 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1740 error = request_irq(irq, handler, 0, name, ndev);
1742 netdev_err(ndev, "cannot request IRQ %s\n", name);
1747 /* Network device open function for Ethernet AVB */
1748 static int ravb_open(struct net_device *ndev)
1750 struct ravb_private *priv = netdev_priv(ndev);
1751 const struct ravb_hw_info *info = priv->info;
1752 struct platform_device *pdev = priv->pdev;
1753 struct device *dev = &pdev->dev;
1756 napi_enable(&priv->napi[RAVB_BE]);
1757 if (info->nc_queues)
1758 napi_enable(&priv->napi[RAVB_NC]);
1760 if (!info->multi_irqs) {
1761 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1764 netdev_err(ndev, "cannot request IRQ\n");
1768 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1772 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1776 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1777 ndev, dev, "ch0:rx_be");
1779 goto out_free_irq_emac;
1780 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1781 ndev, dev, "ch18:tx_be");
1783 goto out_free_irq_be_rx;
1784 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1785 ndev, dev, "ch1:rx_nc");
1787 goto out_free_irq_be_tx;
1788 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1789 ndev, dev, "ch19:tx_nc");
1791 goto out_free_irq_nc_rx;
1793 if (info->err_mgmt_irqs) {
1794 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1795 ndev, dev, "err_a");
1797 goto out_free_irq_nc_tx;
1798 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1799 ndev, dev, "mgmt_a");
1801 goto out_free_irq_erra;
1806 error = ravb_dmac_init(ndev);
1808 goto out_free_irq_mgmta;
1809 ravb_emac_init(ndev);
1811 /* Initialise PTP Clock driver */
1813 ravb_ptp_init(ndev, priv->pdev);
1815 /* PHY control start */
1816 error = ravb_phy_start(ndev);
1820 netif_tx_start_all_queues(ndev);
1825 /* Stop PTP Clock driver */
1827 ravb_ptp_stop(ndev);
1828 ravb_stop_dma(ndev);
1830 if (!info->multi_irqs)
1832 if (info->err_mgmt_irqs)
1833 free_irq(priv->mgmta_irq, ndev);
1835 if (info->err_mgmt_irqs)
1836 free_irq(priv->erra_irq, ndev);
1838 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1840 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1842 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1844 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1846 free_irq(priv->emac_irq, ndev);
1848 free_irq(ndev->irq, ndev);
1850 if (info->nc_queues)
1851 napi_disable(&priv->napi[RAVB_NC]);
1852 napi_disable(&priv->napi[RAVB_BE]);
1856 /* Timeout function for Ethernet AVB */
1857 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1859 struct ravb_private *priv = netdev_priv(ndev);
1861 netif_err(priv, tx_err, ndev,
1862 "transmit timed out, status %08x, resetting...\n",
1863 ravb_read(ndev, ISS));
1865 /* tx_errors count up */
1866 ndev->stats.tx_errors++;
1868 schedule_work(&priv->work);
1871 static void ravb_tx_timeout_work(struct work_struct *work)
1873 struct ravb_private *priv = container_of(work, struct ravb_private,
1875 const struct ravb_hw_info *info = priv->info;
1876 struct net_device *ndev = priv->ndev;
1879 if (!rtnl_trylock()) {
1880 usleep_range(1000, 2000);
1881 schedule_work(&priv->work);
1885 netif_tx_stop_all_queues(ndev);
1887 /* Stop PTP Clock driver */
1889 ravb_ptp_stop(ndev);
1891 /* Wait for DMA stopping */
1892 if (ravb_stop_dma(ndev)) {
1893 /* If ravb_stop_dma() fails, the hardware is still operating
1894 * for TX and/or RX. So, this should not call the following
1895 * functions because ravb_dmac_init() is possible to fail too.
1896 * Also, this should not retry ravb_stop_dma() again and again
1897 * here because it's possible to wait forever. So, this just
1898 * re-enables the TX and RX and skip the following
1899 * re-initialization procedure.
1901 ravb_rcv_snd_enable(ndev);
1905 ravb_ring_free(ndev, RAVB_BE);
1906 if (info->nc_queues)
1907 ravb_ring_free(ndev, RAVB_NC);
1910 error = ravb_dmac_init(ndev);
1912 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1913 * should return here to avoid re-enabling the TX and RX in
1916 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1920 ravb_emac_init(ndev);
1923 /* Initialise PTP Clock driver */
1925 ravb_ptp_init(ndev, priv->pdev);
1927 netif_tx_start_all_queues(ndev);
1933 /* Packet transmit function for Ethernet AVB */
1934 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1936 struct ravb_private *priv = netdev_priv(ndev);
1937 const struct ravb_hw_info *info = priv->info;
1938 unsigned int num_tx_desc = priv->num_tx_desc;
1939 u16 q = skb_get_queue_mapping(skb);
1940 struct ravb_tstamp_skb *ts_skb;
1941 struct ravb_tx_desc *desc;
1942 unsigned long flags;
1948 spin_lock_irqsave(&priv->lock, flags);
1949 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1951 netif_err(priv, tx_queued, ndev,
1952 "still transmitting with the full ring!\n");
1953 netif_stop_subqueue(ndev, q);
1954 spin_unlock_irqrestore(&priv->lock, flags);
1955 return NETDEV_TX_BUSY;
1958 if (skb_put_padto(skb, ETH_ZLEN))
1961 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1962 priv->tx_skb[q][entry / num_tx_desc] = skb;
1964 if (num_tx_desc > 1) {
1965 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1966 entry / num_tx_desc * DPTR_ALIGN;
1967 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1969 /* Zero length DMA descriptors are problematic as they seem
1970 * to terminate DMA transfers. Avoid them by simply using a
1971 * length of DPTR_ALIGN (4) when skb data is aligned to
1974 * As skb is guaranteed to have at least ETH_ZLEN (60)
1975 * bytes of data by the call to skb_put_padto() above this
1976 * is safe with respect to both the length of the first DMA
1977 * descriptor (len) overflowing the available data and the
1978 * length of the second DMA descriptor (skb->len - len)
1984 memcpy(buffer, skb->data, len);
1985 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1987 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1990 desc = &priv->tx_ring[q][entry];
1991 desc->ds_tagl = cpu_to_le16(len);
1992 desc->dptr = cpu_to_le32(dma_addr);
1994 buffer = skb->data + len;
1995 len = skb->len - len;
1996 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1998 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2003 desc = &priv->tx_ring[q][entry];
2005 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2007 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2010 desc->ds_tagl = cpu_to_le16(len);
2011 desc->dptr = cpu_to_le32(dma_addr);
2013 /* TX timestamp required */
2014 if (info->gptp || info->ccc_gac) {
2016 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2018 if (num_tx_desc > 1) {
2020 dma_unmap_single(ndev->dev.parent, dma_addr,
2021 len, DMA_TO_DEVICE);
2025 ts_skb->skb = skb_get(skb);
2026 ts_skb->tag = priv->ts_skb_tag++;
2027 priv->ts_skb_tag &= 0x3ff;
2028 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2030 /* TAG and timestamp required flag */
2031 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2032 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2033 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2036 skb_tx_timestamp(skb);
2038 /* Descriptor type must be set after all the above writes */
2040 if (num_tx_desc > 1) {
2041 desc->die_dt = DT_FEND;
2043 desc->die_dt = DT_FSTART;
2045 desc->die_dt = DT_FSINGLE;
2047 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2049 priv->cur_tx[q] += num_tx_desc;
2050 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2051 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2052 !ravb_tx_free(ndev, q, true))
2053 netif_stop_subqueue(ndev, q);
2056 spin_unlock_irqrestore(&priv->lock, flags);
2057 return NETDEV_TX_OK;
2060 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2061 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2063 dev_kfree_skb_any(skb);
2064 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2068 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2069 struct net_device *sb_dev)
2071 /* If skb needs TX timestamp, it is handled in network control queue */
2072 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2077 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2079 struct ravb_private *priv = netdev_priv(ndev);
2080 const struct ravb_hw_info *info = priv->info;
2081 struct net_device_stats *nstats, *stats0, *stats1;
2083 nstats = &ndev->stats;
2084 stats0 = &priv->stats[RAVB_BE];
2086 if (info->tx_counters) {
2087 nstats->tx_dropped += ravb_read(ndev, TROCR);
2088 ravb_write(ndev, 0, TROCR); /* (write clear) */
2091 if (info->carrier_counters) {
2092 nstats->collisions += ravb_read(ndev, CXR41);
2093 ravb_write(ndev, 0, CXR41); /* (write clear) */
2094 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2095 ravb_write(ndev, 0, CXR42); /* (write clear) */
2098 nstats->rx_packets = stats0->rx_packets;
2099 nstats->tx_packets = stats0->tx_packets;
2100 nstats->rx_bytes = stats0->rx_bytes;
2101 nstats->tx_bytes = stats0->tx_bytes;
2102 nstats->multicast = stats0->multicast;
2103 nstats->rx_errors = stats0->rx_errors;
2104 nstats->rx_crc_errors = stats0->rx_crc_errors;
2105 nstats->rx_frame_errors = stats0->rx_frame_errors;
2106 nstats->rx_length_errors = stats0->rx_length_errors;
2107 nstats->rx_missed_errors = stats0->rx_missed_errors;
2108 nstats->rx_over_errors = stats0->rx_over_errors;
2109 if (info->nc_queues) {
2110 stats1 = &priv->stats[RAVB_NC];
2112 nstats->rx_packets += stats1->rx_packets;
2113 nstats->tx_packets += stats1->tx_packets;
2114 nstats->rx_bytes += stats1->rx_bytes;
2115 nstats->tx_bytes += stats1->tx_bytes;
2116 nstats->multicast += stats1->multicast;
2117 nstats->rx_errors += stats1->rx_errors;
2118 nstats->rx_crc_errors += stats1->rx_crc_errors;
2119 nstats->rx_frame_errors += stats1->rx_frame_errors;
2120 nstats->rx_length_errors += stats1->rx_length_errors;
2121 nstats->rx_missed_errors += stats1->rx_missed_errors;
2122 nstats->rx_over_errors += stats1->rx_over_errors;
2128 /* Update promiscuous bit */
2129 static void ravb_set_rx_mode(struct net_device *ndev)
2131 struct ravb_private *priv = netdev_priv(ndev);
2132 unsigned long flags;
2134 spin_lock_irqsave(&priv->lock, flags);
2135 ravb_modify(ndev, ECMR, ECMR_PRM,
2136 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2137 spin_unlock_irqrestore(&priv->lock, flags);
2140 /* Device close function for Ethernet AVB */
2141 static int ravb_close(struct net_device *ndev)
2143 struct device_node *np = ndev->dev.parent->of_node;
2144 struct ravb_private *priv = netdev_priv(ndev);
2145 const struct ravb_hw_info *info = priv->info;
2146 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2148 netif_tx_stop_all_queues(ndev);
2150 /* Disable interrupts by clearing the interrupt masks. */
2151 ravb_write(ndev, 0, RIC0);
2152 ravb_write(ndev, 0, RIC2);
2153 ravb_write(ndev, 0, TIC);
2155 /* Stop PTP Clock driver */
2157 ravb_ptp_stop(ndev);
2159 /* Set the config mode to stop the AVB-DMAC's processes */
2160 if (ravb_stop_dma(ndev) < 0)
2162 "device will be stopped after h/w processes are done.\n");
2164 /* Clear the timestamp list */
2165 if (info->gptp || info->ccc_gac) {
2166 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2167 list_del(&ts_skb->list);
2168 kfree_skb(ts_skb->skb);
2173 /* PHY disconnect */
2175 phy_stop(ndev->phydev);
2176 phy_disconnect(ndev->phydev);
2177 if (of_phy_is_fixed_link(np))
2178 of_phy_deregister_fixed_link(np);
2181 cancel_work_sync(&priv->work);
2183 if (info->multi_irqs) {
2184 free_irq(priv->tx_irqs[RAVB_NC], ndev);
2185 free_irq(priv->rx_irqs[RAVB_NC], ndev);
2186 free_irq(priv->tx_irqs[RAVB_BE], ndev);
2187 free_irq(priv->rx_irqs[RAVB_BE], ndev);
2188 free_irq(priv->emac_irq, ndev);
2189 if (info->err_mgmt_irqs) {
2190 free_irq(priv->erra_irq, ndev);
2191 free_irq(priv->mgmta_irq, ndev);
2194 free_irq(ndev->irq, ndev);
2196 if (info->nc_queues)
2197 napi_disable(&priv->napi[RAVB_NC]);
2198 napi_disable(&priv->napi[RAVB_BE]);
2200 /* Free all the skb's in the RX queue and the DMA buffers. */
2201 ravb_ring_free(ndev, RAVB_BE);
2202 if (info->nc_queues)
2203 ravb_ring_free(ndev, RAVB_NC);
2208 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2210 struct ravb_private *priv = netdev_priv(ndev);
2211 struct hwtstamp_config config;
2214 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2216 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2217 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2218 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2220 case RAVB_RXTSTAMP_TYPE_ALL:
2221 config.rx_filter = HWTSTAMP_FILTER_ALL;
2224 config.rx_filter = HWTSTAMP_FILTER_NONE;
2227 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2231 /* Control hardware time stamping */
2232 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2234 struct ravb_private *priv = netdev_priv(ndev);
2235 struct hwtstamp_config config;
2236 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2239 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2242 switch (config.tx_type) {
2243 case HWTSTAMP_TX_OFF:
2246 case HWTSTAMP_TX_ON:
2247 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2253 switch (config.rx_filter) {
2254 case HWTSTAMP_FILTER_NONE:
2257 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2258 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2261 config.rx_filter = HWTSTAMP_FILTER_ALL;
2262 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2265 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2266 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2268 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2272 /* ioctl to device function */
2273 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2275 struct phy_device *phydev = ndev->phydev;
2277 if (!netif_running(ndev))
2285 return ravb_hwtstamp_get(ndev, req);
2287 return ravb_hwtstamp_set(ndev, req);
2290 return phy_mii_ioctl(phydev, req, cmd);
2293 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2295 struct ravb_private *priv = netdev_priv(ndev);
2297 ndev->mtu = new_mtu;
2299 if (netif_running(ndev)) {
2300 synchronize_irq(priv->emac_irq);
2301 ravb_emac_init(ndev);
2304 netdev_update_features(ndev);
2309 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2311 struct ravb_private *priv = netdev_priv(ndev);
2312 unsigned long flags;
2314 spin_lock_irqsave(&priv->lock, flags);
2316 /* Disable TX and RX */
2317 ravb_rcv_snd_disable(ndev);
2319 /* Modify RX Checksum setting */
2320 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2322 /* Enable TX and RX */
2323 ravb_rcv_snd_enable(ndev);
2325 spin_unlock_irqrestore(&priv->lock, flags);
2328 static int ravb_set_features_gbeth(struct net_device *ndev,
2329 netdev_features_t features)
2335 static int ravb_set_features_rcar(struct net_device *ndev,
2336 netdev_features_t features)
2338 netdev_features_t changed = ndev->features ^ features;
2340 if (changed & NETIF_F_RXCSUM)
2341 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2343 ndev->features = features;
2348 static int ravb_set_features(struct net_device *ndev,
2349 netdev_features_t features)
2351 struct ravb_private *priv = netdev_priv(ndev);
2352 const struct ravb_hw_info *info = priv->info;
2354 return info->set_feature(ndev, features);
2357 static const struct net_device_ops ravb_netdev_ops = {
2358 .ndo_open = ravb_open,
2359 .ndo_stop = ravb_close,
2360 .ndo_start_xmit = ravb_start_xmit,
2361 .ndo_select_queue = ravb_select_queue,
2362 .ndo_get_stats = ravb_get_stats,
2363 .ndo_set_rx_mode = ravb_set_rx_mode,
2364 .ndo_tx_timeout = ravb_tx_timeout,
2365 .ndo_eth_ioctl = ravb_do_ioctl,
2366 .ndo_change_mtu = ravb_change_mtu,
2367 .ndo_validate_addr = eth_validate_addr,
2368 .ndo_set_mac_address = eth_mac_addr,
2369 .ndo_set_features = ravb_set_features,
2372 /* MDIO bus init function */
2373 static int ravb_mdio_init(struct ravb_private *priv)
2375 struct platform_device *pdev = priv->pdev;
2376 struct device *dev = &pdev->dev;
2377 struct phy_device *phydev;
2378 struct device_node *pn;
2382 priv->mdiobb.ops = &bb_ops;
2384 /* MII controller setting */
2385 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2389 /* Hook up MII support for ethtool */
2390 priv->mii_bus->name = "ravb_mii";
2391 priv->mii_bus->parent = dev;
2392 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2393 pdev->name, pdev->id);
2395 /* Register MDIO bus */
2396 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2400 pn = of_parse_phandle(dev->of_node, "phy-handle", 0);
2401 phydev = of_phy_find_device(pn);
2403 phydev->mac_managed_pm = true;
2404 put_device(&phydev->mdio.dev);
2411 free_mdio_bitbang(priv->mii_bus);
2415 /* MDIO bus release function */
2416 static int ravb_mdio_release(struct ravb_private *priv)
2418 /* Unregister mdio bus */
2419 mdiobus_unregister(priv->mii_bus);
2421 /* Free bitbang info */
2422 free_mdio_bitbang(priv->mii_bus);
2427 static const struct ravb_hw_info ravb_gen3_hw_info = {
2428 .rx_ring_free = ravb_rx_ring_free_rcar,
2429 .rx_ring_format = ravb_rx_ring_format_rcar,
2430 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2431 .receive = ravb_rx_rcar,
2432 .set_rate = ravb_set_rate_rcar,
2433 .set_feature = ravb_set_features_rcar,
2434 .dmac_init = ravb_dmac_init_rcar,
2435 .emac_init = ravb_emac_init_rcar,
2436 .gstrings_stats = ravb_gstrings_stats,
2437 .gstrings_size = sizeof(ravb_gstrings_stats),
2438 .net_hw_features = NETIF_F_RXCSUM,
2439 .net_features = NETIF_F_RXCSUM,
2440 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2441 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2442 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2443 .rx_max_buf_size = SZ_2K,
2444 .internal_delay = 1,
2453 static const struct ravb_hw_info ravb_gen2_hw_info = {
2454 .rx_ring_free = ravb_rx_ring_free_rcar,
2455 .rx_ring_format = ravb_rx_ring_format_rcar,
2456 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2457 .receive = ravb_rx_rcar,
2458 .set_rate = ravb_set_rate_rcar,
2459 .set_feature = ravb_set_features_rcar,
2460 .dmac_init = ravb_dmac_init_rcar,
2461 .emac_init = ravb_emac_init_rcar,
2462 .gstrings_stats = ravb_gstrings_stats,
2463 .gstrings_size = sizeof(ravb_gstrings_stats),
2464 .net_hw_features = NETIF_F_RXCSUM,
2465 .net_features = NETIF_F_RXCSUM,
2466 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2467 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2468 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2469 .rx_max_buf_size = SZ_2K,
2476 static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2477 .rx_ring_free = ravb_rx_ring_free_rcar,
2478 .rx_ring_format = ravb_rx_ring_format_rcar,
2479 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2480 .receive = ravb_rx_rcar,
2481 .set_rate = ravb_set_rate_rcar,
2482 .set_feature = ravb_set_features_rcar,
2483 .dmac_init = ravb_dmac_init_rcar,
2484 .emac_init = ravb_emac_init_rcar,
2485 .gstrings_stats = ravb_gstrings_stats,
2486 .gstrings_size = sizeof(ravb_gstrings_stats),
2487 .net_hw_features = NETIF_F_RXCSUM,
2488 .net_features = NETIF_F_RXCSUM,
2489 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2490 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2491 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2492 .rx_max_buf_size = SZ_2K,
2501 static const struct ravb_hw_info gbeth_hw_info = {
2502 .rx_ring_free = ravb_rx_ring_free_gbeth,
2503 .rx_ring_format = ravb_rx_ring_format_gbeth,
2504 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2505 .receive = ravb_rx_gbeth,
2506 .set_rate = ravb_set_rate_gbeth,
2507 .set_feature = ravb_set_features_gbeth,
2508 .dmac_init = ravb_dmac_init_gbeth,
2509 .emac_init = ravb_emac_init_gbeth,
2510 .gstrings_stats = ravb_gstrings_stats_gbeth,
2511 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2512 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2513 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2514 .tccr_mask = TCCR_TSRQ0,
2515 .rx_max_buf_size = SZ_8K,
2518 .carrier_counters = 1,
2522 static const struct of_device_id ravb_match_table[] = {
2523 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2524 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2525 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2526 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2527 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2528 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2529 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2530 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2533 MODULE_DEVICE_TABLE(of, ravb_match_table);
2535 static int ravb_set_gti(struct net_device *ndev)
2537 struct ravb_private *priv = netdev_priv(ndev);
2538 const struct ravb_hw_info *info = priv->info;
2539 struct device *dev = ndev->dev.parent;
2543 if (info->gptp_ref_clk)
2544 rate = clk_get_rate(priv->gptp_clk);
2546 rate = clk_get_rate(priv->clk);
2550 inc = div64_ul(1000000000ULL << 20, rate);
2552 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2553 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2554 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2558 ravb_write(ndev, inc, GTI);
2563 static void ravb_set_config_mode(struct net_device *ndev)
2565 struct ravb_private *priv = netdev_priv(ndev);
2566 const struct ravb_hw_info *info = priv->info;
2569 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2570 /* Set CSEL value */
2571 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2572 } else if (info->ccc_gac) {
2573 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2574 CCC_GAC | CCC_CSEL_HPB);
2576 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2580 /* Set tx and rx clock internal delay modes */
2581 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2583 struct ravb_private *priv = netdev_priv(ndev);
2584 bool explicit_delay = false;
2587 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2588 /* Valid values are 0 and 1800, according to DT bindings */
2589 priv->rxcidm = !!delay;
2590 explicit_delay = true;
2592 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2593 /* Valid values are 0 and 2000, according to DT bindings */
2594 priv->txcidm = !!delay;
2595 explicit_delay = true;
2601 /* Fall back to legacy rgmii-*id behavior */
2602 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2603 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2605 priv->rgmii_override = 1;
2608 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2609 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2611 priv->rgmii_override = 1;
2615 static void ravb_set_delay_mode(struct net_device *ndev)
2617 struct ravb_private *priv = netdev_priv(ndev);
2624 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2627 static int ravb_probe(struct platform_device *pdev)
2629 struct device_node *np = pdev->dev.of_node;
2630 const struct ravb_hw_info *info;
2631 struct reset_control *rstc;
2632 struct ravb_private *priv;
2633 struct net_device *ndev;
2635 struct resource *res;
2640 "this driver is required to be instantiated from device tree\n");
2644 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2646 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2647 "failed to get cpg reset\n");
2649 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2650 NUM_TX_QUEUE, NUM_RX_QUEUE);
2654 info = of_device_get_match_data(&pdev->dev);
2656 ndev->features = info->net_features;
2657 ndev->hw_features = info->net_hw_features;
2659 error = reset_control_deassert(rstc);
2661 goto out_free_netdev;
2663 pm_runtime_enable(&pdev->dev);
2664 error = pm_runtime_resume_and_get(&pdev->dev);
2666 goto out_rpm_disable;
2668 if (info->multi_irqs) {
2669 if (info->err_mgmt_irqs)
2670 irq = platform_get_irq_byname(pdev, "dia");
2672 irq = platform_get_irq_byname(pdev, "ch22");
2674 irq = platform_get_irq(pdev, 0);
2682 SET_NETDEV_DEV(ndev, &pdev->dev);
2684 priv = netdev_priv(ndev);
2689 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2690 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2691 if (info->nc_queues) {
2692 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2693 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2696 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2697 if (IS_ERR(priv->addr)) {
2698 error = PTR_ERR(priv->addr);
2702 /* The Ether-specific entries in the device structure. */
2703 ndev->base_addr = res->start;
2705 spin_lock_init(&priv->lock);
2706 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2708 error = of_get_phy_mode(np, &priv->phy_interface);
2709 if (error && error != -ENODEV)
2712 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2713 priv->avb_link_active_low =
2714 of_property_read_bool(np, "renesas,ether-link-active-low");
2716 if (info->multi_irqs) {
2717 if (info->err_mgmt_irqs)
2718 irq = platform_get_irq_byname(pdev, "line3");
2720 irq = platform_get_irq_byname(pdev, "ch24");
2725 priv->emac_irq = irq;
2726 for (i = 0; i < NUM_RX_QUEUE; i++) {
2727 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2732 priv->rx_irqs[i] = irq;
2734 for (i = 0; i < NUM_TX_QUEUE; i++) {
2735 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2740 priv->tx_irqs[i] = irq;
2743 if (info->err_mgmt_irqs) {
2744 irq = platform_get_irq_byname(pdev, "err_a");
2749 priv->erra_irq = irq;
2751 irq = platform_get_irq_byname(pdev, "mgmt_a");
2756 priv->mgmta_irq = irq;
2760 priv->clk = devm_clk_get(&pdev->dev, NULL);
2761 if (IS_ERR(priv->clk)) {
2762 error = PTR_ERR(priv->clk);
2766 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2767 if (IS_ERR(priv->refclk)) {
2768 error = PTR_ERR(priv->refclk);
2771 clk_prepare_enable(priv->refclk);
2773 if (info->gptp_ref_clk) {
2774 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2775 if (IS_ERR(priv->gptp_clk)) {
2776 error = PTR_ERR(priv->gptp_clk);
2777 goto out_disable_refclk;
2779 clk_prepare_enable(priv->gptp_clk);
2782 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2783 ndev->min_mtu = ETH_MIN_MTU;
2785 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2786 * Use two descriptor to handle such situation. First descriptor to
2787 * handle aligned data buffer and second descriptor to handle the
2788 * overflow data because of alignment.
2790 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2793 ndev->netdev_ops = &ravb_netdev_ops;
2794 ndev->ethtool_ops = &ravb_ethtool_ops;
2796 /* Set AVB config mode */
2797 ravb_set_config_mode(ndev);
2799 if (info->gptp || info->ccc_gac) {
2801 error = ravb_set_gti(ndev);
2803 goto out_disable_gptp_clk;
2805 /* Request GTI loading */
2806 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2809 if (info->internal_delay) {
2810 ravb_parse_delay_mode(np, ndev);
2811 ravb_set_delay_mode(ndev);
2814 /* Allocate descriptor base address table */
2815 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2816 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2817 &priv->desc_bat_dma, GFP_KERNEL);
2818 if (!priv->desc_bat) {
2820 "Cannot allocate desc base address table (size %d bytes)\n",
2821 priv->desc_bat_size);
2823 goto out_disable_gptp_clk;
2825 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2826 priv->desc_bat[q].die_dt = DT_EOS;
2827 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2829 /* Initialise HW timestamp list */
2830 INIT_LIST_HEAD(&priv->ts_skb_list);
2832 /* Initialise PTP Clock driver */
2834 ravb_ptp_init(ndev, pdev);
2836 /* Debug message level */
2837 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2839 /* Read and set MAC address */
2840 ravb_read_mac_address(np, ndev);
2841 if (!is_valid_ether_addr(ndev->dev_addr)) {
2842 dev_warn(&pdev->dev,
2843 "no valid MAC address supplied, using a random one\n");
2844 eth_hw_addr_random(ndev);
2848 error = ravb_mdio_init(priv);
2850 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2854 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll);
2855 if (info->nc_queues)
2856 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll);
2858 /* Network device register */
2859 error = register_netdev(ndev);
2863 device_set_wakeup_capable(&pdev->dev, 1);
2865 /* Print device information */
2866 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2867 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2869 platform_set_drvdata(pdev, ndev);
2874 if (info->nc_queues)
2875 netif_napi_del(&priv->napi[RAVB_NC]);
2877 netif_napi_del(&priv->napi[RAVB_BE]);
2878 ravb_mdio_release(priv);
2880 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2881 priv->desc_bat_dma);
2883 /* Stop PTP Clock driver */
2885 ravb_ptp_stop(ndev);
2886 out_disable_gptp_clk:
2887 clk_disable_unprepare(priv->gptp_clk);
2889 clk_disable_unprepare(priv->refclk);
2891 pm_runtime_put(&pdev->dev);
2893 pm_runtime_disable(&pdev->dev);
2894 reset_control_assert(rstc);
2900 static int ravb_remove(struct platform_device *pdev)
2902 struct net_device *ndev = platform_get_drvdata(pdev);
2903 struct ravb_private *priv = netdev_priv(ndev);
2904 const struct ravb_hw_info *info = priv->info;
2906 /* Stop PTP Clock driver */
2908 ravb_ptp_stop(ndev);
2910 clk_disable_unprepare(priv->gptp_clk);
2911 clk_disable_unprepare(priv->refclk);
2913 /* Set reset mode */
2914 ravb_write(ndev, CCC_OPC_RESET, CCC);
2915 unregister_netdev(ndev);
2916 if (info->nc_queues)
2917 netif_napi_del(&priv->napi[RAVB_NC]);
2918 netif_napi_del(&priv->napi[RAVB_BE]);
2919 ravb_mdio_release(priv);
2920 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2921 priv->desc_bat_dma);
2922 pm_runtime_put_sync(&pdev->dev);
2923 pm_runtime_disable(&pdev->dev);
2924 reset_control_assert(priv->rstc);
2926 platform_set_drvdata(pdev, NULL);
2931 static int ravb_wol_setup(struct net_device *ndev)
2933 struct ravb_private *priv = netdev_priv(ndev);
2934 const struct ravb_hw_info *info = priv->info;
2936 /* Disable interrupts by clearing the interrupt masks. */
2937 ravb_write(ndev, 0, RIC0);
2938 ravb_write(ndev, 0, RIC2);
2939 ravb_write(ndev, 0, TIC);
2941 /* Only allow ECI interrupts */
2942 synchronize_irq(priv->emac_irq);
2943 if (info->nc_queues)
2944 napi_disable(&priv->napi[RAVB_NC]);
2945 napi_disable(&priv->napi[RAVB_BE]);
2946 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2948 /* Enable MagicPacket */
2949 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2951 return enable_irq_wake(priv->emac_irq);
2954 static int ravb_wol_restore(struct net_device *ndev)
2956 struct ravb_private *priv = netdev_priv(ndev);
2957 const struct ravb_hw_info *info = priv->info;
2959 if (info->nc_queues)
2960 napi_enable(&priv->napi[RAVB_NC]);
2961 napi_enable(&priv->napi[RAVB_BE]);
2963 /* Disable MagicPacket */
2964 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2968 return disable_irq_wake(priv->emac_irq);
2971 static int __maybe_unused ravb_suspend(struct device *dev)
2973 struct net_device *ndev = dev_get_drvdata(dev);
2974 struct ravb_private *priv = netdev_priv(ndev);
2977 if (!netif_running(ndev))
2980 netif_device_detach(ndev);
2982 if (priv->wol_enabled)
2983 ret = ravb_wol_setup(ndev);
2985 ret = ravb_close(ndev);
2987 if (priv->info->ccc_gac)
2988 ravb_ptp_stop(ndev);
2993 static int __maybe_unused ravb_resume(struct device *dev)
2995 struct net_device *ndev = dev_get_drvdata(dev);
2996 struct ravb_private *priv = netdev_priv(ndev);
2997 const struct ravb_hw_info *info = priv->info;
3000 /* If WoL is enabled set reset mode to rearm the WoL logic */
3001 if (priv->wol_enabled)
3002 ravb_write(ndev, CCC_OPC_RESET, CCC);
3004 /* All register have been reset to default values.
3005 * Restore all registers which where setup at probe time and
3006 * reopen device if it was running before system suspended.
3009 /* Set AVB config mode */
3010 ravb_set_config_mode(ndev);
3012 if (info->gptp || info->ccc_gac) {
3014 ret = ravb_set_gti(ndev);
3018 /* Request GTI loading */
3019 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3022 if (info->internal_delay)
3023 ravb_set_delay_mode(ndev);
3025 /* Restore descriptor base address table */
3026 ravb_write(ndev, priv->desc_bat_dma, DBAT);
3028 if (priv->info->ccc_gac)
3029 ravb_ptp_init(ndev, priv->pdev);
3031 if (netif_running(ndev)) {
3032 if (priv->wol_enabled) {
3033 ret = ravb_wol_restore(ndev);
3037 ret = ravb_open(ndev);
3040 ravb_set_rx_mode(ndev);
3041 netif_device_attach(ndev);
3047 static int __maybe_unused ravb_runtime_nop(struct device *dev)
3049 /* Runtime PM callback shared between ->runtime_suspend()
3050 * and ->runtime_resume(). Simply returns success.
3052 * This driver re-initializes all registers after
3053 * pm_runtime_get_sync() anyway so there is no need
3054 * to save and restore registers here.
3059 static const struct dev_pm_ops ravb_dev_pm_ops = {
3060 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3061 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3064 static struct platform_driver ravb_driver = {
3065 .probe = ravb_probe,
3066 .remove = ravb_remove,
3069 .pm = &ravb_dev_pm_ops,
3070 .of_match_table = ravb_match_table,
3074 module_platform_driver(ravb_driver);
3076 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3077 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3078 MODULE_LICENSE("GPL v2");