drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include "r8169.h"
  34 #include "r8169_firmware.h"
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 #define MC_FILTER_LIMIT 32
  63
  64 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  65 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  66
  67 #define R8169_REGS_SIZE         256
  68 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  69 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  70 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  71 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  72 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  73
  74 #define OCP_STD_PHY_BASE        0xa400
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90
  91 static const struct {
  92         const char *name;
  93         const char *fw_name;
  94 } rtl_chip_infos[] = {
  95         /* PCI devices. */
  96         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  97         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  98         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  99         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 100         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 101         /* PCI-E devices. */
 102         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 103         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 105         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 106         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 109         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 110         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 111         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 112         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 113         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 118         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 119         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 120         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 121         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 122         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 124         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 125         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 126         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 127         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 128         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 129         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 130         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 131         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 132         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 133         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 134         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 135         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 136         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 137         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 138         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 139         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 140         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 141         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 142         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 143         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 144         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 145         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 146         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 147         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 148         [RTL_GIGA_MAC_VER_60] = {"RTL8125"                              },
 149         [RTL_GIGA_MAC_VER_61] = {"RTL8125",             FIRMWARE_8125A_3},
 150 };
 151
 152 static const struct pci_device_id rtl8169_pci_tbl[] = {
 153         { PCI_VDEVICE(REALTEK,  0x2502) },
 154         { PCI_VDEVICE(REALTEK,  0x2600) },
 155         { PCI_VDEVICE(REALTEK,  0x8129) },
 156         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 157         { PCI_VDEVICE(REALTEK,  0x8161) },
 158         { PCI_VDEVICE(REALTEK,  0x8167) },
 159         { PCI_VDEVICE(REALTEK,  0x8168) },
 160         { PCI_VDEVICE(NCUBE,    0x8168) },
 161         { PCI_VDEVICE(REALTEK,  0x8169) },
 162         { PCI_VENDOR_ID_DLINK,  0x4300,
 163                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 164         { PCI_VDEVICE(DLINK,    0x4300) },
 165         { PCI_VDEVICE(DLINK,    0x4302) },
 166         { PCI_VDEVICE(AT,       0xc107) },
 167         { PCI_VDEVICE(USR,      0x0116) },
 168         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 169         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 170         { PCI_VDEVICE(REALTEK,  0x8125) },
 171         { PCI_VDEVICE(REALTEK,  0x3000) },
 172         {}
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 enum rtl_registers {
 178         MAC0            = 0,    /* Ethernet hardware address. */
 179         MAC4            = 4,
 180         MAR0            = 8,    /* Multicast filter. */
 181         CounterAddrLow          = 0x10,
 182         CounterAddrHigh         = 0x14,
 183         TxDescStartAddrLow      = 0x20,
 184         TxDescStartAddrHigh     = 0x24,
 185         TxHDescStartAddrLow     = 0x28,
 186         TxHDescStartAddrHigh    = 0x2c,
 187         FLASH           = 0x30,
 188         ERSR            = 0x36,
 189         ChipCmd         = 0x37,
 190         TxPoll          = 0x38,
 191         IntrMask        = 0x3c,
 192         IntrStatus      = 0x3e,
 193
 194         TxConfig        = 0x40,
 195 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 196 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 197
 198         RxConfig        = 0x44,
 199 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 200 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 201 #define RXCFG_FIFO_SHIFT                13
 202                                         /* No threshold before first PCI xfer */
 203 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 204 #define RX_EARLY_OFF                    (1 << 11)
 205 #define RXCFG_DMA_SHIFT                 8
 206                                         /* Unlimited maximum PCI burst. */
 207 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 208
 209         Cfg9346         = 0x50,
 210         Config0         = 0x51,
 211         Config1         = 0x52,
 212         Config2         = 0x53,
 213 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 214
 215         Config3         = 0x54,
 216         Config4         = 0x55,
 217         Config5         = 0x56,
 218         PHYAR           = 0x60,
 219         PHYstatus       = 0x6c,
 220         RxMaxSize       = 0xda,
 221         CPlusCmd        = 0xe0,
 222         IntrMitigate    = 0xe2,
 223
 224 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 225 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 226 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 227 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 228
 229 #define RTL_COALESCE_T_MAX      0x0fU
 230 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 231
 232         RxDescAddrLow   = 0xe4,
 233         RxDescAddrHigh  = 0xe8,
 234         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 235
 236 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 237
 238         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 239
 240 #define TxPacketMax     (8064 >> 7)
 241 #define EarlySize       0x27
 242
 243         FuncEvent       = 0xf0,
 244         FuncEventMask   = 0xf4,
 245         FuncPresetState = 0xf8,
 246         IBCR0           = 0xf8,
 247         IBCR2           = 0xf9,
 248         IBIMR0          = 0xfa,
 249         IBISR0          = 0xfb,
 250         FuncForceEvent  = 0xfc,
 251 };
 252
 253 enum rtl8168_8101_registers {
 254         CSIDR                   = 0x64,
 255         CSIAR                   = 0x68,
 256 #define CSIAR_FLAG                      0x80000000
 257 #define CSIAR_WRITE_CMD                 0x80000000
 258 #define CSIAR_BYTE_ENABLE               0x0000f000
 259 #define CSIAR_ADDR_MASK                 0x00000fff
 260         PMCH                    = 0x6f,
 261         EPHYAR                  = 0x80,
 262 #define EPHYAR_FLAG                     0x80000000
 263 #define EPHYAR_WRITE_CMD                0x80000000
 264 #define EPHYAR_REG_MASK                 0x1f
 265 #define EPHYAR_REG_SHIFT                16
 266 #define EPHYAR_DATA_MASK                0xffff
 267         DLLPR                   = 0xd0,
 268 #define PFM_EN                          (1 << 6)
 269 #define TX_10M_PS_EN                    (1 << 7)
 270         DBG_REG                 = 0xd1,
 271 #define FIX_NAK_1                       (1 << 4)
 272 #define FIX_NAK_2                       (1 << 3)
 273         TWSI                    = 0xd2,
 274         MCU                     = 0xd3,
 275 #define NOW_IS_OOB                      (1 << 7)
 276 #define TX_EMPTY                        (1 << 5)
 277 #define RX_EMPTY                        (1 << 4)
 278 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 279 #define EN_NDP                          (1 << 3)
 280 #define EN_OOB_RESET                    (1 << 2)
 281 #define LINK_LIST_RDY                   (1 << 1)
 282         EFUSEAR                 = 0xdc,
 283 #define EFUSEAR_FLAG                    0x80000000
 284 #define EFUSEAR_WRITE_CMD               0x80000000
 285 #define EFUSEAR_READ_CMD                0x00000000
 286 #define EFUSEAR_REG_MASK                0x03ff
 287 #define EFUSEAR_REG_SHIFT               8
 288 #define EFUSEAR_DATA_MASK               0xff
 289         MISC_1                  = 0xf2,
 290 #define PFM_D3COLD_EN                   (1 << 6)
 291 };
 292
 293 enum rtl8168_registers {
 294         LED_FREQ                = 0x1a,
 295         EEE_LED                 = 0x1b,
 296         ERIDR                   = 0x70,
 297         ERIAR                   = 0x74,
 298 #define ERIAR_FLAG                      0x80000000
 299 #define ERIAR_WRITE_CMD                 0x80000000
 300 #define ERIAR_READ_CMD                  0x00000000
 301 #define ERIAR_ADDR_BYTE_ALIGN           4
 302 #define ERIAR_TYPE_SHIFT                16
 303 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 304 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 305 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 306 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 307 #define ERIAR_MASK_SHIFT                12
 308 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 309 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 310 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 311 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 312 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 313         EPHY_RXER_NUM           = 0x7c,
 314         OCPDR                   = 0xb0, /* OCP GPHY access */
 315 #define OCPDR_WRITE_CMD                 0x80000000
 316 #define OCPDR_READ_CMD                  0x00000000
 317 #define OCPDR_REG_MASK                  0x7f
 318 #define OCPDR_GPHY_REG_SHIFT            16
 319 #define OCPDR_DATA_MASK                 0xffff
 320         OCPAR                   = 0xb4,
 321 #define OCPAR_FLAG                      0x80000000
 322 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 323 #define OCPAR_GPHY_READ_CMD             0x0000f060
 324         GPHY_OCP                = 0xb8,
 325         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 326         MISC                    = 0xf0, /* 8168e only. */
 327 #define TXPLA_RST                       (1 << 29)
 328 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 329 #define PWM_EN                          (1 << 22)
 330 #define RXDV_GATED_EN                   (1 << 19)
 331 #define EARLY_TALLY_EN                  (1 << 16)
 332 };
 333
 334 enum rtl8125_registers {
 335         IntrMask_8125           = 0x38,
 336         IntrStatus_8125         = 0x3c,
 337         TxPoll_8125             = 0x90,
 338         MAC0_BKP                = 0x19e0,
 339 };
 340
 341 #define RX_VLAN_INNER_8125      BIT(22)
 342 #define RX_VLAN_OUTER_8125      BIT(23)
 343 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 344
 345 #define RX_FETCH_DFLT_8125      (8 << 27)
 346
 347 enum rtl_register_content {
 348         /* InterruptStatusBits */
 349         SYSErr          = 0x8000,
 350         PCSTimeout      = 0x4000,
 351         SWInt           = 0x0100,
 352         TxDescUnavail   = 0x0080,
 353         RxFIFOOver      = 0x0040,
 354         LinkChg         = 0x0020,
 355         RxOverflow      = 0x0010,
 356         TxErr           = 0x0008,
 357         TxOK            = 0x0004,
 358         RxErr           = 0x0002,
 359         RxOK            = 0x0001,
 360
 361         /* RxStatusDesc */
 362         RxRWT   = (1 << 22),
 363         RxRES   = (1 << 21),
 364         RxRUNT  = (1 << 20),
 365         RxCRC   = (1 << 19),
 366
 367         /* ChipCmdBits */
 368         StopReq         = 0x80,
 369         CmdReset        = 0x10,
 370         CmdRxEnb        = 0x08,
 371         CmdTxEnb        = 0x04,
 372         RxBufEmpty      = 0x01,
 373
 374         /* TXPoll register p.5 */
 375         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 376         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 377         FSWInt          = 0x01,         /* Forced software interrupt */
 378
 379         /* Cfg9346Bits */
 380         Cfg9346_Lock    = 0x00,
 381         Cfg9346_Unlock  = 0xc0,
 382
 383         /* rx_mode_bits */
 384         AcceptErr       = 0x20,
 385         AcceptRunt      = 0x10,
 386 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 387         AcceptBroadcast = 0x08,
 388         AcceptMulticast = 0x04,
 389         AcceptMyPhys    = 0x02,
 390         AcceptAllPhys   = 0x01,
 391 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 392 #define RX_CONFIG_ACCEPT_MASK           0x3f
 393
 394         /* TxConfigBits */
 395         TxInterFrameGapShift = 24,
 396         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 397
 398         /* Config1 register p.24 */
 399         LEDS1           = (1 << 7),
 400         LEDS0           = (1 << 6),
 401         Speed_down      = (1 << 4),
 402         MEMMAP          = (1 << 3),
 403         IOMAP           = (1 << 2),
 404         VPD             = (1 << 1),
 405         PMEnable        = (1 << 0),     /* Power Management Enable */
 406
 407         /* Config2 register p. 25 */
 408         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 409         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 410         PCI_Clock_66MHz = 0x01,
 411         PCI_Clock_33MHz = 0x00,
 412
 413         /* Config3 register p.25 */
 414         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 415         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 416         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 417         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 418         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 419
 420         /* Config4 register */
 421         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 422
 423         /* Config5 register p.27 */
 424         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 425         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 426         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 427         Spi_en          = (1 << 3),
 428         LanWake         = (1 << 1),     /* LanWake enable/disable */
 429         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 430         ASPM_en         = (1 << 0),     /* ASPM enable */
 431
 432         /* CPlusCmd p.31 */
 433         EnableBist      = (1 << 15),    // 8168 8101
 434         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 435         EnAnaPLL        = (1 << 14),    // 8169
 436         Normal_mode     = (1 << 13),    // unused
 437         Force_half_dup  = (1 << 12),    // 8168 8101
 438         Force_rxflow_en = (1 << 11),    // 8168 8101
 439         Force_txflow_en = (1 << 10),    // 8168 8101
 440         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 441         ASF             = (1 << 8),     // 8168 8101
 442         PktCntrDisable  = (1 << 7),     // 8168 8101
 443         Mac_dbgo_sel    = 0x001c,       // 8168
 444         RxVlan          = (1 << 6),
 445         RxChkSum        = (1 << 5),
 446         PCIDAC          = (1 << 4),
 447         PCIMulRW        = (1 << 3),
 448 #define INTT_MASK       GENMASK(1, 0)
 449 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 450
 451         /* rtl8169_PHYstatus */
 452         TBI_Enable      = 0x80,
 453         TxFlowCtrl      = 0x40,
 454         RxFlowCtrl      = 0x20,
 455         _1000bpsF       = 0x10,
 456         _100bps         = 0x08,
 457         _10bps          = 0x04,
 458         LinkStatus      = 0x02,
 459         FullDup         = 0x01,
 460
 461         /* ResetCounterCommand */
 462         CounterReset    = 0x1,
 463
 464         /* DumpCounterCommand */
 465         CounterDump     = 0x8,
 466
 467         /* magic enable v2 */
 468         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 469 };
 470
 471 enum rtl_desc_bit {
 472         /* First doubleword. */
 473         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 474         RingEnd         = (1 << 30), /* End of descriptor ring */
 475         FirstFrag       = (1 << 29), /* First segment of a packet */
 476         LastFrag        = (1 << 28), /* Final segment of a packet */
 477 };
 478
 479 /* Generic case. */
 480 enum rtl_tx_desc_bit {
 481         /* First doubleword. */
 482         TD_LSO          = (1 << 27),            /* Large Send Offload */
 483 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 484
 485         /* Second doubleword. */
 486         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 487 };
 488
 489 /* 8169, 8168b and 810x except 8102e. */
 490 enum rtl_tx_desc_bit_0 {
 491         /* First doubleword. */
 492 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 493         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 494         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 495         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 496 };
 497
 498 /* 8102e, 8168c and beyond. */
 499 enum rtl_tx_desc_bit_1 {
 500         /* First doubleword. */
 501         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 502         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 503 #define GTTCPHO_SHIFT                   18
 504 #define GTTCPHO_MAX                     0x7f
 505
 506         /* Second doubleword. */
 507 #define TCPHO_SHIFT                     18
 508 #define TCPHO_MAX                       0x3ff
 509 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 510         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 511         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 512         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 513         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 514 };
 515
 516 enum rtl_rx_desc_bit {
 517         /* Rx private */
 518         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 519         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 520
 521 #define RxProtoUDP      (PID1)
 522 #define RxProtoTCP      (PID0)
 523 #define RxProtoIP       (PID1 | PID0)
 524 #define RxProtoMask     RxProtoIP
 525
 526         IPFail          = (1 << 16), /* IP checksum failed */
 527         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 528         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 529         RxVlanTag       = (1 << 16), /* VLAN tag available */
 530 };
 531
 532 #define RTL_GSO_MAX_SIZE_V1     32000
 533 #define RTL_GSO_MAX_SEGS_V1     24
 534 #define RTL_GSO_MAX_SIZE_V2     64000
 535 #define RTL_GSO_MAX_SEGS_V2     64
 536
 537 struct TxDesc {
 538         __le32 opts1;
 539         __le32 opts2;
 540         __le64 addr;
 541 };
 542
 543 struct RxDesc {
 544         __le32 opts1;
 545         __le32 opts2;
 546         __le64 addr;
 547 };
 548
 549 struct ring_info {
 550         struct sk_buff  *skb;
 551         u32             len;
 552 };
 553
 554 struct rtl8169_counters {
 555         __le64  tx_packets;
 556         __le64  rx_packets;
 557         __le64  tx_errors;
 558         __le32  rx_errors;
 559         __le16  rx_missed;
 560         __le16  align_errors;
 561         __le32  tx_one_collision;
 562         __le32  tx_multi_collision;
 563         __le64  rx_unicast;
 564         __le64  rx_broadcast;
 565         __le32  rx_multicast;
 566         __le16  tx_aborted;
 567         __le16  tx_underun;
 568 };
 569
 570 struct rtl8169_tc_offsets {
 571         bool    inited;
 572         __le64  tx_errors;
 573         __le32  tx_multi_collision;
 574         __le16  tx_aborted;
 575         __le16  rx_missed;
 576 };
 577
 578 enum rtl_flag {
 579         RTL_FLAG_TASK_ENABLED = 0,
 580         RTL_FLAG_TASK_RESET_PENDING,
 581         RTL_FLAG_MAX
 582 };
 583
 584 struct rtl8169_stats {
 585         u64                     packets;
 586         u64                     bytes;
 587         struct u64_stats_sync   syncp;
 588 };
 589
 590 struct rtl8169_private {
 591         void __iomem *mmio_addr;        /* memory map physical address */
 592         struct pci_dev *pci_dev;
 593         struct net_device *dev;
 594         struct phy_device *phydev;
 595         struct napi_struct napi;
 596         enum mac_version mac_version;
 597         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 598         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 599         u32 dirty_tx;
 600         struct rtl8169_stats rx_stats;
 601         struct rtl8169_stats tx_stats;
 602         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 603         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 604         dma_addr_t TxPhyAddr;
 605         dma_addr_t RxPhyAddr;
 606         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 607         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 608         u16 cp_cmd;
 609         u32 irq_mask;
 610         struct clk *clk;
 611
 612         struct {
 613                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 614                 struct mutex mutex;
 615                 struct work_struct work;
 616         } wk;
 617
 618         unsigned irq_enabled:1;
 619         unsigned supports_gmii:1;
 620         unsigned aspm_manageable:1;
 621         dma_addr_t counters_phys_addr;
 622         struct rtl8169_counters *counters;
 623         struct rtl8169_tc_offsets tc_offset;
 624         u32 saved_wolopts;
 625         int eee_adv;
 626
 627         const char *fw_name;
 628         struct rtl_fw *rtl_fw;
 629
 630         u32 ocp_base;
 631 };
 632
 633 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 634
 635 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 636 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 637 MODULE_SOFTDEP("pre: realtek");
 638 MODULE_LICENSE("GPL");
 639 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 640 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 641 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 642 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 643 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 644 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 645 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 646 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 647 MODULE_FIRMWARE(FIRMWARE_8402_1);
 648 MODULE_FIRMWARE(FIRMWARE_8411_1);
 649 MODULE_FIRMWARE(FIRMWARE_8411_2);
 650 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 651 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 652 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 653 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 654 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 655 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 656 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 657 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 658 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 659 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 660
 661 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 662 {
 663         return &tp->pci_dev->dev;
 664 }
 665
 666 static void rtl_lock_work(struct rtl8169_private *tp)
 667 {
 668         mutex_lock(&tp->wk.mutex);
 669 }
 670
 671 static void rtl_unlock_work(struct rtl8169_private *tp)
 672 {
 673         mutex_unlock(&tp->wk.mutex);
 674 }
 675
 676 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 677 {
 678         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 679 }
 680
 681 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 682 {
 683         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 684 }
 685
 686 static void rtl_pci_commit(struct rtl8169_private *tp)
 687 {
 688         /* Read an arbitrary register to commit a preceding PCI write */
 689         RTL_R8(tp, ChipCmd);
 690 }
 691
 692 static bool rtl_is_8125(struct rtl8169_private *tp)
 693 {
 694         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 695 }
 696
 697 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 698 {
 699         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 700                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 701                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 702 }
 703
 704 static bool rtl_supports_eee(struct rtl8169_private *tp)
 705 {
 706         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 707                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 708                tp->mac_version != RTL_GIGA_MAC_VER_39;
 709 }
 710
 711 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 712 {
 713         int i;
 714
 715         for (i = 0; i < ETH_ALEN; i++)
 716                 mac[i] = RTL_R8(tp, reg + i);
 717 }
 718
 719 struct rtl_cond {
 720         bool (*check)(struct rtl8169_private *);
 721         const char *msg;
 722 };
 723
 724 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 725                           unsigned long usecs, int n, bool high)
 726 {
 727         int i;
 728
 729         for (i = 0; i < n; i++) {
 730                 if (c->check(tp) == high)
 731                         return true;
 732                 fsleep(usecs);
 733         }
 734
 735         if (net_ratelimit())
 736                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 737                            c->msg, !high, n, usecs);
 738         return false;
 739 }
 740
 741 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 742                                const struct rtl_cond *c,
 743                                unsigned long d, int n)
 744 {
 745         return rtl_loop_wait(tp, c, d, n, true);
 746 }
 747
 748 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 749                               const struct rtl_cond *c,
 750                               unsigned long d, int n)
 751 {
 752         return rtl_loop_wait(tp, c, d, n, false);
 753 }
 754
 755 #define DECLARE_RTL_COND(name)                          \
 756 static bool name ## _check(struct rtl8169_private *);   \
 757                                                         \
 758 static const struct rtl_cond name = {                   \
 759         .check  = name ## _check,                       \
 760         .msg    = #name                                 \
 761 };                                                      \
 762                                                         \
 763 static bool name ## _check(struct rtl8169_private *tp)
 764
 765 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 766 {
 767         if (reg & 0xffff0001) {
 768                 if (net_ratelimit())
 769                         netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
 770                 return true;
 771         }
 772         return false;
 773 }
 774
 775 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 776 {
 777         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 778 }
 779
 780 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 781 {
 782         if (rtl_ocp_reg_failure(tp, reg))
 783                 return;
 784
 785         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 786
 787         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 788 }
 789
 790 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 791 {
 792         if (rtl_ocp_reg_failure(tp, reg))
 793                 return 0;
 794
 795         RTL_W32(tp, GPHY_OCP, reg << 15);
 796
 797         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 798                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 799 }
 800
 801 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 802 {
 803         if (rtl_ocp_reg_failure(tp, reg))
 804                 return;
 805
 806         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 807 }
 808
 809 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 810 {
 811         if (rtl_ocp_reg_failure(tp, reg))
 812                 return 0;
 813
 814         RTL_W32(tp, OCPDR, reg << 15);
 815
 816         return RTL_R32(tp, OCPDR);
 817 }
 818
 819 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 820                                  u16 set)
 821 {
 822         u16 data = r8168_mac_ocp_read(tp, reg);
 823
 824         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 825 }
 826
 827 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 828 {
 829         if (reg == 0x1f) {
 830                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 831                 return;
 832         }
 833
 834         if (tp->ocp_base != OCP_STD_PHY_BASE)
 835                 reg -= 0x10;
 836
 837         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 838 }
 839
 840 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 841 {
 842         if (reg == 0x1f)
 843                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 844
 845         if (tp->ocp_base != OCP_STD_PHY_BASE)
 846                 reg -= 0x10;
 847
 848         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 849 }
 850
 851 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 852 {
 853         if (reg == 0x1f) {
 854                 tp->ocp_base = value << 4;
 855                 return;
 856         }
 857
 858         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 859 }
 860
 861 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 862 {
 863         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 864 }
 865
 866 DECLARE_RTL_COND(rtl_phyar_cond)
 867 {
 868         return RTL_R32(tp, PHYAR) & 0x80000000;
 869 }
 870
 871 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 872 {
 873         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 874
 875         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 876         /*
 877          * According to hardware specs a 20us delay is required after write
 878          * complete indication, but before sending next command.
 879          */
 880         udelay(20);
 881 }
 882
 883 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 884 {
 885         int value;
 886
 887         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 888
 889         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 890                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 891
 892         /*
 893          * According to hardware specs a 20us delay is required after read
 894          * complete indication, but before sending next command.
 895          */
 896         udelay(20);
 897
 898         return value;
 899 }
 900
 901 DECLARE_RTL_COND(rtl_ocpar_cond)
 902 {
 903         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 904 }
 905
 906 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 907 {
 908         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 909         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 910         RTL_W32(tp, EPHY_RXER_NUM, 0);
 911
 912         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 913 }
 914
 915 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 916 {
 917         r8168dp_1_mdio_access(tp, reg,
 918                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 919 }
 920
 921 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 922 {
 923         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 924
 925         mdelay(1);
 926         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 927         RTL_W32(tp, EPHY_RXER_NUM, 0);
 928
 929         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 930                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 931 }
 932
 933 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 934
 935 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 936 {
 937         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 938 }
 939
 940 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 941 {
 942         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 943 }
 944
 945 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 946 {
 947         r8168dp_2_mdio_start(tp);
 948
 949         r8169_mdio_write(tp, reg, value);
 950
 951         r8168dp_2_mdio_stop(tp);
 952 }
 953
 954 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 955 {
 956         int value;
 957
 958         /* Work around issue with chip reporting wrong PHY ID */
 959         if (reg == MII_PHYSID2)
 960                 return 0xc912;
 961
 962         r8168dp_2_mdio_start(tp);
 963
 964         value = r8169_mdio_read(tp, reg);
 965
 966         r8168dp_2_mdio_stop(tp);
 967
 968         return value;
 969 }
 970
 971 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 972 {
 973         switch (tp->mac_version) {
 974         case RTL_GIGA_MAC_VER_27:
 975                 r8168dp_1_mdio_write(tp, location, val);
 976                 break;
 977         case RTL_GIGA_MAC_VER_28:
 978         case RTL_GIGA_MAC_VER_31:
 979                 r8168dp_2_mdio_write(tp, location, val);
 980                 break;
 981         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
 982                 r8168g_mdio_write(tp, location, val);
 983                 break;
 984         default:
 985                 r8169_mdio_write(tp, location, val);
 986                 break;
 987         }
 988 }
 989
 990 static int rtl_readphy(struct rtl8169_private *tp, int location)
 991 {
 992         switch (tp->mac_version) {
 993         case RTL_GIGA_MAC_VER_27:
 994                 return r8168dp_1_mdio_read(tp, location);
 995         case RTL_GIGA_MAC_VER_28:
 996         case RTL_GIGA_MAC_VER_31:
 997                 return r8168dp_2_mdio_read(tp, location);
 998         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
 999                 return r8168g_mdio_read(tp, location);
1000         default:
1001                 return r8169_mdio_read(tp, location);
1002         }
1003 }
1004
1005 DECLARE_RTL_COND(rtl_ephyar_cond)
1006 {
1007         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1008 }
1009
1010 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1011 {
1012         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1013                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1014
1015         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1016
1017         udelay(10);
1018 }
1019
1020 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1021 {
1022         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1023
1024         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1025                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1026 }
1027
1028 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1029 {
1030         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1031         if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1032                 *cmd |= 0x7f0 << 18;
1033 }
1034
1035 DECLARE_RTL_COND(rtl_eriar_cond)
1036 {
1037         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1038 }
1039
1040 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1041                            u32 val, int type)
1042 {
1043         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1044
1045         BUG_ON((addr & 3) || (mask == 0));
1046         RTL_W32(tp, ERIDR, val);
1047         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1048         RTL_W32(tp, ERIAR, cmd);
1049
1050         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1051 }
1052
1053 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1054                           u32 val)
1055 {
1056         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1057 }
1058
1059 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1060 {
1061         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1062
1063         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1064         RTL_W32(tp, ERIAR, cmd);
1065
1066         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1067                 RTL_R32(tp, ERIDR) : ~0;
1068 }
1069
1070 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1071 {
1072         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1073 }
1074
1075 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1076 {
1077         u32 val = rtl_eri_read(tp, addr);
1078
1079         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1080 }
1081
1082 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1083 {
1084         rtl_w0w1_eri(tp, addr, p, 0);
1085 }
1086
1087 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1088 {
1089         rtl_w0w1_eri(tp, addr, 0, m);
1090 }
1091
1092 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1093 {
1094         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1095         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1096                 RTL_R32(tp, OCPDR) : ~0;
1097 }
1098
1099 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1100 {
1101         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1102 }
1103
1104 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1105                               u32 data)
1106 {
1107         RTL_W32(tp, OCPDR, data);
1108         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1109         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1110 }
1111
1112 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1113                               u32 data)
1114 {
1115         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1116                        data, ERIAR_OOB);
1117 }
1118
1119 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1120 {
1121         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1122
1123         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1124 }
1125
1126 #define OOB_CMD_RESET           0x00
1127 #define OOB_CMD_DRIVER_START    0x05
1128 #define OOB_CMD_DRIVER_STOP     0x06
1129
1130 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1131 {
1132         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1133 }
1134
1135 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1136 {
1137         u16 reg;
1138
1139         reg = rtl8168_get_ocp_reg(tp);
1140
1141         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1142 }
1143
1144 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1145 {
1146         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1147 }
1148
1149 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1150 {
1151         return RTL_R8(tp, IBISR0) & 0x20;
1152 }
1153
1154 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1155 {
1156         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1157         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1158         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1159         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1160 }
1161
1162 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1163 {
1164         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1165         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1166 }
1167
1168 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1169 {
1170         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1171         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1172         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1173 }
1174
1175 static void rtl8168_driver_start(struct rtl8169_private *tp)
1176 {
1177         switch (tp->mac_version) {
1178         case RTL_GIGA_MAC_VER_27:
1179         case RTL_GIGA_MAC_VER_28:
1180         case RTL_GIGA_MAC_VER_31:
1181                 rtl8168dp_driver_start(tp);
1182                 break;
1183         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1184                 rtl8168ep_driver_start(tp);
1185                 break;
1186         default:
1187                 BUG();
1188                 break;
1189         }
1190 }
1191
1192 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1193 {
1194         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1195         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1196 }
1197
1198 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1199 {
1200         rtl8168ep_stop_cmac(tp);
1201         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1202         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1203         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1204 }
1205
1206 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1207 {
1208         switch (tp->mac_version) {
1209         case RTL_GIGA_MAC_VER_27:
1210         case RTL_GIGA_MAC_VER_28:
1211         case RTL_GIGA_MAC_VER_31:
1212                 rtl8168dp_driver_stop(tp);
1213                 break;
1214         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1215                 rtl8168ep_driver_stop(tp);
1216                 break;
1217         default:
1218                 BUG();
1219                 break;
1220         }
1221 }
1222
1223 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1224 {
1225         u16 reg = rtl8168_get_ocp_reg(tp);
1226
1227         return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1228 }
1229
1230 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1231 {
1232         return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1233 }
1234
1235 static bool r8168_check_dash(struct rtl8169_private *tp)
1236 {
1237         switch (tp->mac_version) {
1238         case RTL_GIGA_MAC_VER_27:
1239         case RTL_GIGA_MAC_VER_28:
1240         case RTL_GIGA_MAC_VER_31:
1241                 return r8168dp_check_dash(tp);
1242         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1243                 return r8168ep_check_dash(tp);
1244         default:
1245                 return false;
1246         }
1247 }
1248
1249 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1250 {
1251         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1252         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1253 }
1254
1255 DECLARE_RTL_COND(rtl_efusear_cond)
1256 {
1257         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1258 }
1259
1260 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1261 {
1262         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1263
1264         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1265                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1266 }
1267
1268 static u32 rtl_get_events(struct rtl8169_private *tp)
1269 {
1270         if (rtl_is_8125(tp))
1271                 return RTL_R32(tp, IntrStatus_8125);
1272         else
1273                 return RTL_R16(tp, IntrStatus);
1274 }
1275
1276 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1277 {
1278         if (rtl_is_8125(tp))
1279                 RTL_W32(tp, IntrStatus_8125, bits);
1280         else
1281                 RTL_W16(tp, IntrStatus, bits);
1282 }
1283
1284 static void rtl_irq_disable(struct rtl8169_private *tp)
1285 {
1286         if (rtl_is_8125(tp))
1287                 RTL_W32(tp, IntrMask_8125, 0);
1288         else
1289                 RTL_W16(tp, IntrMask, 0);
1290         tp->irq_enabled = 0;
1291 }
1292
1293 static void rtl_irq_enable(struct rtl8169_private *tp)
1294 {
1295         tp->irq_enabled = 1;
1296         if (rtl_is_8125(tp))
1297                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1298         else
1299                 RTL_W16(tp, IntrMask, tp->irq_mask);
1300 }
1301
1302 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1303 {
1304         rtl_irq_disable(tp);
1305         rtl_ack_events(tp, 0xffffffff);
1306         rtl_pci_commit(tp);
1307 }
1308
1309 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1310 {
1311         struct phy_device *phydev = tp->phydev;
1312
1313         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1314             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1315                 if (phydev->speed == SPEED_1000) {
1316                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1317                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1318                 } else if (phydev->speed == SPEED_100) {
1319                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1320                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1321                 } else {
1322                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1323                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1324                 }
1325                 rtl_reset_packet_filter(tp);
1326         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1327                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1328                 if (phydev->speed == SPEED_1000) {
1329                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1330                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1331                 } else {
1332                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1333                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1334                 }
1335         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1336                 if (phydev->speed == SPEED_10) {
1337                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1338                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1339                 } else {
1340                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1341                 }
1342         }
1343 }
1344
1345 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1346
1347 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1348 {
1349         struct rtl8169_private *tp = netdev_priv(dev);
1350
1351         rtl_lock_work(tp);
1352         wol->supported = WAKE_ANY;
1353         wol->wolopts = tp->saved_wolopts;
1354         rtl_unlock_work(tp);
1355 }
1356
1357 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1358 {
1359         static const struct {
1360                 u32 opt;
1361                 u16 reg;
1362                 u8  mask;
1363         } cfg[] = {
1364                 { WAKE_PHY,   Config3, LinkUp },
1365                 { WAKE_UCAST, Config5, UWF },
1366                 { WAKE_BCAST, Config5, BWF },
1367                 { WAKE_MCAST, Config5, MWF },
1368                 { WAKE_ANY,   Config5, LanWake },
1369                 { WAKE_MAGIC, Config3, MagicPacket }
1370         };
1371         unsigned int i, tmp = ARRAY_SIZE(cfg);
1372         u8 options;
1373
1374         rtl_unlock_config_regs(tp);
1375
1376         if (rtl_is_8168evl_up(tp)) {
1377                 tmp--;
1378                 if (wolopts & WAKE_MAGIC)
1379                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1380                 else
1381                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1382         } else if (rtl_is_8125(tp)) {
1383                 tmp--;
1384                 if (wolopts & WAKE_MAGIC)
1385                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1386                 else
1387                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1388         }
1389
1390         for (i = 0; i < tmp; i++) {
1391                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1392                 if (wolopts & cfg[i].opt)
1393                         options |= cfg[i].mask;
1394                 RTL_W8(tp, cfg[i].reg, options);
1395         }
1396
1397         switch (tp->mac_version) {
1398         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1399                 options = RTL_R8(tp, Config1) & ~PMEnable;
1400                 if (wolopts)
1401                         options |= PMEnable;
1402                 RTL_W8(tp, Config1, options);
1403                 break;
1404         case RTL_GIGA_MAC_VER_34:
1405         case RTL_GIGA_MAC_VER_37:
1406         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_61:
1407                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1408                 if (wolopts)
1409                         options |= PME_SIGNAL;
1410                 RTL_W8(tp, Config2, options);
1411                 break;
1412         default:
1413                 break;
1414         }
1415
1416         rtl_lock_config_regs(tp);
1417
1418         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1419         tp->dev->wol_enabled = wolopts ? 1 : 0;
1420 }
1421
1422 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1423 {
1424         struct rtl8169_private *tp = netdev_priv(dev);
1425         struct device *d = tp_to_dev(tp);
1426
1427         if (wol->wolopts & ~WAKE_ANY)
1428                 return -EINVAL;
1429
1430         pm_runtime_get_noresume(d);
1431
1432         rtl_lock_work(tp);
1433
1434         tp->saved_wolopts = wol->wolopts;
1435
1436         if (pm_runtime_active(d))
1437                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1438
1439         rtl_unlock_work(tp);
1440
1441         pm_runtime_put_noidle(d);
1442
1443         return 0;
1444 }
1445
1446 static void rtl8169_get_drvinfo(struct net_device *dev,
1447                                 struct ethtool_drvinfo *info)
1448 {
1449         struct rtl8169_private *tp = netdev_priv(dev);
1450         struct rtl_fw *rtl_fw = tp->rtl_fw;
1451
1452         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1453         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1454         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1455         if (rtl_fw)
1456                 strlcpy(info->fw_version, rtl_fw->version,
1457                         sizeof(info->fw_version));
1458 }
1459
1460 static int rtl8169_get_regs_len(struct net_device *dev)
1461 {
1462         return R8169_REGS_SIZE;
1463 }
1464
1465 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1466         netdev_features_t features)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469
1470         if (dev->mtu > TD_MSS_MAX)
1471                 features &= ~NETIF_F_ALL_TSO;
1472
1473         if (dev->mtu > ETH_DATA_LEN &&
1474             tp->mac_version > RTL_GIGA_MAC_VER_06)
1475                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1476
1477         return features;
1478 }
1479
1480 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1481                                        netdev_features_t features)
1482 {
1483         u32 rx_config = RTL_R32(tp, RxConfig);
1484
1485         if (features & NETIF_F_RXALL)
1486                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1487         else
1488                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1489
1490         if (rtl_is_8125(tp)) {
1491                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1492                         rx_config |= RX_VLAN_8125;
1493                 else
1494                         rx_config &= ~RX_VLAN_8125;
1495         }
1496
1497         RTL_W32(tp, RxConfig, rx_config);
1498 }
1499
1500 static int rtl8169_set_features(struct net_device *dev,
1501                                 netdev_features_t features)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         rtl_lock_work(tp);
1506
1507         rtl_set_rx_config_features(tp, features);
1508
1509         if (features & NETIF_F_RXCSUM)
1510                 tp->cp_cmd |= RxChkSum;
1511         else
1512                 tp->cp_cmd &= ~RxChkSum;
1513
1514         if (!rtl_is_8125(tp)) {
1515                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1516                         tp->cp_cmd |= RxVlan;
1517                 else
1518                         tp->cp_cmd &= ~RxVlan;
1519         }
1520
1521         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1522         rtl_pci_commit(tp);
1523
1524         rtl_unlock_work(tp);
1525
1526         return 0;
1527 }
1528
1529 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1530 {
1531         return (skb_vlan_tag_present(skb)) ?
1532                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1533 }
1534
1535 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1536 {
1537         u32 opts2 = le32_to_cpu(desc->opts2);
1538
1539         if (opts2 & RxVlanTag)
1540                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1541 }
1542
1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1544                              void *p)
1545 {
1546         struct rtl8169_private *tp = netdev_priv(dev);
1547         u32 __iomem *data = tp->mmio_addr;
1548         u32 *dw = p;
1549         int i;
1550
1551         rtl_lock_work(tp);
1552         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1553                 memcpy_fromio(dw++, data++, 4);
1554         rtl_unlock_work(tp);
1555 }
1556
1557 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1558         "tx_packets",
1559         "rx_packets",
1560         "tx_errors",
1561         "rx_errors",
1562         "rx_missed",
1563         "align_errors",
1564         "tx_single_collisions",
1565         "tx_multi_collisions",
1566         "unicast",
1567         "broadcast",
1568         "multicast",
1569         "tx_aborted",
1570         "tx_underrun",
1571 };
1572
1573 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1574 {
1575         switch (sset) {
1576         case ETH_SS_STATS:
1577                 return ARRAY_SIZE(rtl8169_gstrings);
1578         default:
1579                 return -EOPNOTSUPP;
1580         }
1581 }
1582
1583 DECLARE_RTL_COND(rtl_counters_cond)
1584 {
1585         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1586 }
1587
1588 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1589 {
1590         dma_addr_t paddr = tp->counters_phys_addr;
1591         u32 cmd;
1592
1593         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1594         rtl_pci_commit(tp);
1595         cmd = (u64)paddr & DMA_BIT_MASK(32);
1596         RTL_W32(tp, CounterAddrLow, cmd);
1597         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1598
1599         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1600 }
1601
1602 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1603 {
1604         /*
1605          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1606          * tally counters.
1607          */
1608         if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1609                 rtl8169_do_counters(tp, CounterReset);
1610 }
1611
1612 static void rtl8169_update_counters(struct rtl8169_private *tp)
1613 {
1614         u8 val = RTL_R8(tp, ChipCmd);
1615
1616         /*
1617          * Some chips are unable to dump tally counters when the receiver
1618          * is disabled. If 0xff chip may be in a PCI power-save state.
1619          */
1620         if (val & CmdRxEnb && val != 0xff)
1621                 rtl8169_do_counters(tp, CounterDump);
1622 }
1623
1624 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1625 {
1626         struct rtl8169_counters *counters = tp->counters;
1627
1628         /*
1629          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1630          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1631          * reset by a power cycle, while the counter values collected by the
1632          * driver are reset at every driver unload/load cycle.
1633          *
1634          * To make sure the HW values returned by @get_stats64 match the SW
1635          * values, we collect the initial values at first open(*) and use them
1636          * as offsets to normalize the values returned by @get_stats64.
1637          *
1638          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1639          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1640          * set at open time by rtl_hw_start.
1641          */
1642
1643         if (tp->tc_offset.inited)
1644                 return;
1645
1646         rtl8169_reset_counters(tp);
1647         rtl8169_update_counters(tp);
1648
1649         tp->tc_offset.tx_errors = counters->tx_errors;
1650         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1651         tp->tc_offset.tx_aborted = counters->tx_aborted;
1652         tp->tc_offset.rx_missed = counters->rx_missed;
1653         tp->tc_offset.inited = true;
1654 }
1655
1656 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1657                                       struct ethtool_stats *stats, u64 *data)
1658 {
1659         struct rtl8169_private *tp = netdev_priv(dev);
1660         struct device *d = tp_to_dev(tp);
1661         struct rtl8169_counters *counters = tp->counters;
1662
1663         ASSERT_RTNL();
1664
1665         pm_runtime_get_noresume(d);
1666
1667         if (pm_runtime_active(d))
1668                 rtl8169_update_counters(tp);
1669
1670         pm_runtime_put_noidle(d);
1671
1672         data[0] = le64_to_cpu(counters->tx_packets);
1673         data[1] = le64_to_cpu(counters->rx_packets);
1674         data[2] = le64_to_cpu(counters->tx_errors);
1675         data[3] = le32_to_cpu(counters->rx_errors);
1676         data[4] = le16_to_cpu(counters->rx_missed);
1677         data[5] = le16_to_cpu(counters->align_errors);
1678         data[6] = le32_to_cpu(counters->tx_one_collision);
1679         data[7] = le32_to_cpu(counters->tx_multi_collision);
1680         data[8] = le64_to_cpu(counters->rx_unicast);
1681         data[9] = le64_to_cpu(counters->rx_broadcast);
1682         data[10] = le32_to_cpu(counters->rx_multicast);
1683         data[11] = le16_to_cpu(counters->tx_aborted);
1684         data[12] = le16_to_cpu(counters->tx_underun);
1685 }
1686
1687 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1688 {
1689         switch(stringset) {
1690         case ETH_SS_STATS:
1691                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1692                 break;
1693         }
1694 }
1695
1696 /*
1697  * Interrupt coalescing
1698  *
1699  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1700  * >     8169, 8168 and 810x line of chipsets
1701  *
1702  * 8169, 8168, and 8136(810x) serial chipsets support it.
1703  *
1704  * > 2 - the Tx timer unit at gigabit speed
1705  *
1706  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1707  * (0xe0) bit 1 and bit 0.
1708  *
1709  * For 8169
1710  * bit[1:0] \ speed        1000M           100M            10M
1711  * 0 0                     320ns           2.56us          40.96us
1712  * 0 1                     2.56us          20.48us         327.7us
1713  * 1 0                     5.12us          40.96us         655.4us
1714  * 1 1                     10.24us         81.92us         1.31ms
1715  *
1716  * For the other
1717  * bit[1:0] \ speed        1000M           100M            10M
1718  * 0 0                     5us             2.56us          40.96us
1719  * 0 1                     40us            20.48us         327.7us
1720  * 1 0                     80us            40.96us         655.4us
1721  * 1 1                     160us           81.92us         1.31ms
1722  */
1723
1724 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1725 struct rtl_coalesce_info {
1726         u32 speed;
1727         u32 scale_nsecs[4];
1728 };
1729
1730 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1731 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1732
1733 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1734         { SPEED_1000,   COALESCE_DELAY(320) },
1735         { SPEED_100,    COALESCE_DELAY(2560) },
1736         { SPEED_10,     COALESCE_DELAY(40960) },
1737         { 0 },
1738 };
1739
1740 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1741         { SPEED_1000,   COALESCE_DELAY(5000) },
1742         { SPEED_100,    COALESCE_DELAY(2560) },
1743         { SPEED_10,     COALESCE_DELAY(40960) },
1744         { 0 },
1745 };
1746 #undef COALESCE_DELAY
1747
1748 /* get rx/tx scale vector corresponding to current speed */
1749 static const struct rtl_coalesce_info *
1750 rtl_coalesce_info(struct rtl8169_private *tp)
1751 {
1752         const struct rtl_coalesce_info *ci;
1753
1754         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1755                 ci = rtl_coalesce_info_8169;
1756         else
1757                 ci = rtl_coalesce_info_8168_8136;
1758
1759         /* if speed is unknown assume highest one */
1760         if (tp->phydev->speed == SPEED_UNKNOWN)
1761                 return ci;
1762
1763         for (; ci->speed; ci++) {
1764                 if (tp->phydev->speed == ci->speed)
1765                         return ci;
1766         }
1767
1768         return ERR_PTR(-ELNRNG);
1769 }
1770
1771 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1772 {
1773         struct rtl8169_private *tp = netdev_priv(dev);
1774         const struct rtl_coalesce_info *ci;
1775         u32 scale, c_us, c_fr;
1776         u16 intrmit;
1777
1778         if (rtl_is_8125(tp))
1779                 return -EOPNOTSUPP;
1780
1781         memset(ec, 0, sizeof(*ec));
1782
1783         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1784         ci = rtl_coalesce_info(tp);
1785         if (IS_ERR(ci))
1786                 return PTR_ERR(ci);
1787
1788         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1789
1790         intrmit = RTL_R16(tp, IntrMitigate);
1791
1792         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1793         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1794
1795         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1796         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1797         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1798
1799         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1800         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1801
1802         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1803         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1804
1805         return 0;
1806 }
1807
1808 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1809 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1810                                      u16 *cp01)
1811 {
1812         const struct rtl_coalesce_info *ci;
1813         u16 i;
1814
1815         ci = rtl_coalesce_info(tp);
1816         if (IS_ERR(ci))
1817                 return PTR_ERR(ci);
1818
1819         for (i = 0; i < 4; i++) {
1820                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1821                         *cp01 = i;
1822                         return ci->scale_nsecs[i];
1823                 }
1824         }
1825
1826         return -ERANGE;
1827 }
1828
1829 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1830 {
1831         struct rtl8169_private *tp = netdev_priv(dev);
1832         u32 tx_fr = ec->tx_max_coalesced_frames;
1833         u32 rx_fr = ec->rx_max_coalesced_frames;
1834         u32 coal_usec_max, units;
1835         u16 w = 0, cp01 = 0;
1836         int scale;
1837
1838         if (rtl_is_8125(tp))
1839                 return -EOPNOTSUPP;
1840
1841         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1842                 return -ERANGE;
1843
1844         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1845         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1846         if (scale < 0)
1847                 return scale;
1848
1849         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1850          * not only when usecs=0 because of e.g. the following scenario:
1851          *
1852          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1853          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1854          * - then user does `ethtool -C eth0 rx-usecs 100`
1855          *
1856          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1857          * if we want to ignore rx_frames then it has to be set to 0.
1858          */
1859         if (rx_fr == 1)
1860                 rx_fr = 0;
1861         if (tx_fr == 1)
1862                 tx_fr = 0;
1863
1864         /* HW requires time limit to be set if frame limit is set */
1865         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1866             (rx_fr && !ec->rx_coalesce_usecs))
1867                 return -EINVAL;
1868
1869         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1870         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1871
1872         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1873         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1874         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1875         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1876
1877         rtl_lock_work(tp);
1878
1879         RTL_W16(tp, IntrMitigate, w);
1880
1881         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1882         if (rtl_is_8168evl_up(tp)) {
1883                 if (!rx_fr && !tx_fr)
1884                         /* disable packet counter */
1885                         tp->cp_cmd |= PktCntrDisable;
1886                 else
1887                         tp->cp_cmd &= ~PktCntrDisable;
1888         }
1889
1890         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1891         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1892         rtl_pci_commit(tp);
1893
1894         rtl_unlock_work(tp);
1895
1896         return 0;
1897 }
1898
1899 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1900 {
1901         struct rtl8169_private *tp = netdev_priv(dev);
1902         struct device *d = tp_to_dev(tp);
1903         int ret;
1904
1905         if (!rtl_supports_eee(tp))
1906                 return -EOPNOTSUPP;
1907
1908         pm_runtime_get_noresume(d);
1909
1910         if (!pm_runtime_active(d)) {
1911                 ret = -EOPNOTSUPP;
1912         } else {
1913                 ret = phy_ethtool_get_eee(tp->phydev, data);
1914         }
1915
1916         pm_runtime_put_noidle(d);
1917
1918         return ret;
1919 }
1920
1921 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1922 {
1923         struct rtl8169_private *tp = netdev_priv(dev);
1924         struct device *d = tp_to_dev(tp);
1925         int ret;
1926
1927         if (!rtl_supports_eee(tp))
1928                 return -EOPNOTSUPP;
1929
1930         pm_runtime_get_noresume(d);
1931
1932         if (!pm_runtime_active(d)) {
1933                 ret = -EOPNOTSUPP;
1934                 goto out;
1935         }
1936
1937         ret = phy_ethtool_set_eee(tp->phydev, data);
1938
1939         if (!ret)
1940                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1941                                            MDIO_AN_EEE_ADV);
1942 out:
1943         pm_runtime_put_noidle(d);
1944         return ret;
1945 }
1946
1947 static const struct ethtool_ops rtl8169_ethtool_ops = {
1948         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1949                                      ETHTOOL_COALESCE_MAX_FRAMES,
1950         .get_drvinfo            = rtl8169_get_drvinfo,
1951         .get_regs_len           = rtl8169_get_regs_len,
1952         .get_link               = ethtool_op_get_link,
1953         .get_coalesce           = rtl_get_coalesce,
1954         .set_coalesce           = rtl_set_coalesce,
1955         .get_regs               = rtl8169_get_regs,
1956         .get_wol                = rtl8169_get_wol,
1957         .set_wol                = rtl8169_set_wol,
1958         .get_strings            = rtl8169_get_strings,
1959         .get_sset_count         = rtl8169_get_sset_count,
1960         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1961         .get_ts_info            = ethtool_op_get_ts_info,
1962         .nway_reset             = phy_ethtool_nway_reset,
1963         .get_eee                = rtl8169_get_eee,
1964         .set_eee                = rtl8169_set_eee,
1965         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1966         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1967 };
1968
1969 static void rtl_enable_eee(struct rtl8169_private *tp)
1970 {
1971         struct phy_device *phydev = tp->phydev;
1972         int adv;
1973
1974         /* respect EEE advertisement the user may have set */
1975         if (tp->eee_adv >= 0)
1976                 adv = tp->eee_adv;
1977         else
1978                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1979
1980         if (adv >= 0)
1981                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1982 }
1983
1984 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1985 {
1986         /*
1987          * The driver currently handles the 8168Bf and the 8168Be identically
1988          * but they can be identified more specifically through the test below
1989          * if needed:
1990          *
1991          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1992          *
1993          * Same thing for the 8101Eb and the 8101Ec:
1994          *
1995          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1996          */
1997         static const struct rtl_mac_info {
1998                 u16 mask;
1999                 u16 val;
2000                 enum mac_version ver;
2001         } mac_info[] = {
2002                 /* 8125 family. */
2003                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2004                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2005
2006                 /* RTL8117 */
2007                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2008
2009                 /* 8168EP family. */
2010                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2011                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2012                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2013
2014                 /* 8168H family. */
2015                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2016                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2017
2018                 /* 8168G family. */
2019                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2020                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2021                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2022                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2023
2024                 /* 8168F family. */
2025                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2026                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2027                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2028
2029                 /* 8168E family. */
2030                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2031                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2032                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2033
2034                 /* 8168D family. */
2035                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2036                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2037
2038                 /* 8168DP family. */
2039                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2040                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2041                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2042
2043                 /* 8168C family. */
2044                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2045                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2046                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2047                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2048                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2049                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2050                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2051
2052                 /* 8168B family. */
2053                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2054                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2055                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2056
2057                 /* 8101 family. */
2058                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2059                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2060                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2061                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2062                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2063                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2064                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2065                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2066                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2067                 /* RTL8401, reportedly works if treated as RTL8101e */
2068                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 },
2069                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2070                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2071                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2072                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2073                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2074                 /* FIXME: where did these entries come from ? -- FR */
2075                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2076                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2077
2078                 /* 8110 family. */
2079                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2080                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2081                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2082                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2083                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2084
2085                 /* Catch-all */
2086                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2087         };
2088         const struct rtl_mac_info *p = mac_info;
2089         enum mac_version ver;
2090
2091         while ((xid & p->mask) != p->val)
2092                 p++;
2093         ver = p->ver;
2094
2095         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2096                 if (ver == RTL_GIGA_MAC_VER_42)
2097                         ver = RTL_GIGA_MAC_VER_43;
2098                 else if (ver == RTL_GIGA_MAC_VER_45)
2099                         ver = RTL_GIGA_MAC_VER_47;
2100                 else if (ver == RTL_GIGA_MAC_VER_46)
2101                         ver = RTL_GIGA_MAC_VER_48;
2102         }
2103
2104         return ver;
2105 }
2106
2107 static void rtl_release_firmware(struct rtl8169_private *tp)
2108 {
2109         if (tp->rtl_fw) {
2110                 rtl_fw_release_firmware(tp->rtl_fw);
2111                 kfree(tp->rtl_fw);
2112                 tp->rtl_fw = NULL;
2113         }
2114 }
2115
2116 void r8169_apply_firmware(struct rtl8169_private *tp)
2117 {
2118         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2119         if (tp->rtl_fw)
2120                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2121 }
2122
2123 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2124 {
2125         /* Adjust EEE LED frequency */
2126         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2127                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2128
2129         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2130 }
2131
2132 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2133 {
2134         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2135         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2136 }
2137
2138 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2139 {
2140         const u16 w[] = {
2141                 addr[0] | (addr[1] << 8),
2142                 addr[2] | (addr[3] << 8),
2143                 addr[4] | (addr[5] << 8)
2144         };
2145
2146         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2147         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2148         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2149         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2150 }
2151
2152 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2153 {
2154         u16 data1, data2, ioffset;
2155
2156         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2157         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2158         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2159
2160         ioffset = (data2 >> 1) & 0x7ff8;
2161         ioffset |= data2 & 0x0007;
2162         if (data1 & BIT(7))
2163                 ioffset |= BIT(15);
2164
2165         return ioffset;
2166 }
2167
2168 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2169 {
2170         set_bit(flag, tp->wk.flags);
2171         schedule_work(&tp->wk.work);
2172 }
2173
2174 static void rtl8169_init_phy(struct rtl8169_private *tp)
2175 {
2176         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2177
2178         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2179                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2180                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2181                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2182                 RTL_W8(tp, 0x82, 0x01);
2183         }
2184
2185         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2186             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2187             tp->pci_dev->subsystem_device == 0xe000)
2188                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2189
2190         /* We may have called phy_speed_down before */
2191         phy_speed_up(tp->phydev);
2192
2193         if (rtl_supports_eee(tp))
2194                 rtl_enable_eee(tp);
2195
2196         genphy_soft_reset(tp->phydev);
2197 }
2198
2199 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2200 {
2201         rtl_lock_work(tp);
2202
2203         rtl_unlock_config_regs(tp);
2204
2205         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2206         rtl_pci_commit(tp);
2207
2208         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2209         rtl_pci_commit(tp);
2210
2211         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2212                 rtl_rar_exgmac_set(tp, addr);
2213
2214         rtl_lock_config_regs(tp);
2215
2216         rtl_unlock_work(tp);
2217 }
2218
2219 static int rtl_set_mac_address(struct net_device *dev, void *p)
2220 {
2221         struct rtl8169_private *tp = netdev_priv(dev);
2222         struct device *d = tp_to_dev(tp);
2223         int ret;
2224
2225         ret = eth_mac_addr(dev, p);
2226         if (ret)
2227                 return ret;
2228
2229         pm_runtime_get_noresume(d);
2230
2231         if (pm_runtime_active(d))
2232                 rtl_rar_set(tp, dev->dev_addr);
2233
2234         pm_runtime_put_noidle(d);
2235
2236         return 0;
2237 }
2238
2239 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2240 {
2241         switch (tp->mac_version) {
2242         case RTL_GIGA_MAC_VER_25:
2243         case RTL_GIGA_MAC_VER_26:
2244         case RTL_GIGA_MAC_VER_29:
2245         case RTL_GIGA_MAC_VER_30:
2246         case RTL_GIGA_MAC_VER_32:
2247         case RTL_GIGA_MAC_VER_33:
2248         case RTL_GIGA_MAC_VER_34:
2249         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
2250                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2251                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2252                 break;
2253         default:
2254                 break;
2255         }
2256 }
2257
2258 static void rtl_pll_power_down(struct rtl8169_private *tp)
2259 {
2260         if (r8168_check_dash(tp))
2261                 return;
2262
2263         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2264             tp->mac_version == RTL_GIGA_MAC_VER_33)
2265                 rtl_ephy_write(tp, 0x19, 0xff64);
2266
2267         if (device_may_wakeup(tp_to_dev(tp))) {
2268                 phy_speed_down(tp->phydev, false);
2269                 rtl_wol_suspend_quirk(tp);
2270                 return;
2271         }
2272
2273         switch (tp->mac_version) {
2274         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2275         case RTL_GIGA_MAC_VER_37:
2276         case RTL_GIGA_MAC_VER_39:
2277         case RTL_GIGA_MAC_VER_43:
2278         case RTL_GIGA_MAC_VER_44:
2279         case RTL_GIGA_MAC_VER_45:
2280         case RTL_GIGA_MAC_VER_46:
2281         case RTL_GIGA_MAC_VER_47:
2282         case RTL_GIGA_MAC_VER_48:
2283         case RTL_GIGA_MAC_VER_50:
2284         case RTL_GIGA_MAC_VER_51:
2285         case RTL_GIGA_MAC_VER_52:
2286         case RTL_GIGA_MAC_VER_60:
2287         case RTL_GIGA_MAC_VER_61:
2288                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2289                 break;
2290         case RTL_GIGA_MAC_VER_40:
2291         case RTL_GIGA_MAC_VER_41:
2292         case RTL_GIGA_MAC_VER_49:
2293                 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2294                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2295                 break;
2296         default:
2297                 break;
2298         }
2299
2300         clk_disable_unprepare(tp->clk);
2301 }
2302
2303 static void rtl_pll_power_up(struct rtl8169_private *tp)
2304 {
2305         clk_prepare_enable(tp->clk);
2306
2307         switch (tp->mac_version) {
2308         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2309         case RTL_GIGA_MAC_VER_37:
2310         case RTL_GIGA_MAC_VER_39:
2311         case RTL_GIGA_MAC_VER_43:
2312                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2313                 break;
2314         case RTL_GIGA_MAC_VER_44:
2315         case RTL_GIGA_MAC_VER_45:
2316         case RTL_GIGA_MAC_VER_46:
2317         case RTL_GIGA_MAC_VER_47:
2318         case RTL_GIGA_MAC_VER_48:
2319         case RTL_GIGA_MAC_VER_50:
2320         case RTL_GIGA_MAC_VER_51:
2321         case RTL_GIGA_MAC_VER_52:
2322         case RTL_GIGA_MAC_VER_60:
2323         case RTL_GIGA_MAC_VER_61:
2324                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2325                 break;
2326         case RTL_GIGA_MAC_VER_40:
2327         case RTL_GIGA_MAC_VER_41:
2328         case RTL_GIGA_MAC_VER_49:
2329                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2330                 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2331                 break;
2332         default:
2333                 break;
2334         }
2335
2336         phy_resume(tp->phydev);
2337 }
2338
2339 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2340 {
2341         switch (tp->mac_version) {
2342         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2343         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2344                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2345                 break;
2346         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2347         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2348         case RTL_GIGA_MAC_VER_38:
2349                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2350                 break;
2351         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2352                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2353                 break;
2354         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2355                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2356                 break;
2357         default:
2358                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2359                 break;
2360         }
2361 }
2362
2363 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2364 {
2365         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2366 }
2367
2368 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2369 {
2370         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2371         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2372 }
2373
2374 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2375 {
2376         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2377         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2378 }
2379
2380 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2381 {
2382         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2383 }
2384
2385 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2386 {
2387         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2388 }
2389
2390 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2391 {
2392         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2393         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2394         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2395 }
2396
2397 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2398 {
2399         RTL_W8(tp, MaxTxPacketSize, 0x0c);
2400         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2401         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2402 }
2403
2404 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2405 {
2406         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2407 }
2408
2409 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2410 {
2411         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2412 }
2413
2414 static void rtl_jumbo_config(struct rtl8169_private *tp)
2415 {
2416         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2417
2418         rtl_unlock_config_regs(tp);
2419         switch (tp->mac_version) {
2420         case RTL_GIGA_MAC_VER_12:
2421         case RTL_GIGA_MAC_VER_17:
2422                 if (jumbo) {
2423                         pcie_set_readrq(tp->pci_dev, 512);
2424                         r8168b_1_hw_jumbo_enable(tp);
2425                 } else {
2426                         r8168b_1_hw_jumbo_disable(tp);
2427                 }
2428                 break;
2429         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2430                 if (jumbo) {
2431                         pcie_set_readrq(tp->pci_dev, 512);
2432                         r8168c_hw_jumbo_enable(tp);
2433                 } else {
2434                         r8168c_hw_jumbo_disable(tp);
2435                 }
2436                 break;
2437         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2438                 if (jumbo)
2439                         r8168dp_hw_jumbo_enable(tp);
2440                 else
2441                         r8168dp_hw_jumbo_disable(tp);
2442                 break;
2443         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2444                 if (jumbo) {
2445                         pcie_set_readrq(tp->pci_dev, 512);
2446                         r8168e_hw_jumbo_enable(tp);
2447                 } else {
2448                         r8168e_hw_jumbo_disable(tp);
2449                 }
2450                 break;
2451         default:
2452                 break;
2453         }
2454         rtl_lock_config_regs(tp);
2455
2456         if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2457                 pcie_set_readrq(tp->pci_dev, 4096);
2458 }
2459
2460 DECLARE_RTL_COND(rtl_chipcmd_cond)
2461 {
2462         return RTL_R8(tp, ChipCmd) & CmdReset;
2463 }
2464
2465 static void rtl_hw_reset(struct rtl8169_private *tp)
2466 {
2467         RTL_W8(tp, ChipCmd, CmdReset);
2468
2469         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2470 }
2471
2472 static void rtl_request_firmware(struct rtl8169_private *tp)
2473 {
2474         struct rtl_fw *rtl_fw;
2475
2476         /* firmware loaded already or no firmware available */
2477         if (tp->rtl_fw || !tp->fw_name)
2478                 return;
2479
2480         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2481         if (!rtl_fw)
2482                 return;
2483
2484         rtl_fw->phy_write = rtl_writephy;
2485         rtl_fw->phy_read = rtl_readphy;
2486         rtl_fw->mac_mcu_write = mac_mcu_write;
2487         rtl_fw->mac_mcu_read = mac_mcu_read;
2488         rtl_fw->fw_name = tp->fw_name;
2489         rtl_fw->dev = tp_to_dev(tp);
2490
2491         if (rtl_fw_request_firmware(rtl_fw))
2492                 kfree(rtl_fw);
2493         else
2494                 tp->rtl_fw = rtl_fw;
2495 }
2496
2497 static void rtl_rx_close(struct rtl8169_private *tp)
2498 {
2499         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2500 }
2501
2502 DECLARE_RTL_COND(rtl_npq_cond)
2503 {
2504         return RTL_R8(tp, TxPoll) & NPQ;
2505 }
2506
2507 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2508 {
2509         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2510 }
2511
2512 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2513 {
2514         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2515 }
2516
2517 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2518 {
2519         switch (tp->mac_version) {
2520         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2521                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2522                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2523                 break;
2524         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2525                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2526                 break;
2527         default:
2528                 break;
2529         }
2530 }
2531
2532 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2533 {
2534         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2535         fsleep(2000);
2536         rtl_wait_txrx_fifo_empty(tp);
2537 }
2538
2539 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2540 {
2541         u32 val = TX_DMA_BURST << TxDMAShift |
2542                   InterFrameGap << TxInterFrameGapShift;
2543
2544         if (rtl_is_8168evl_up(tp))
2545                 val |= TXCFG_AUTO_FIFO;
2546
2547         RTL_W32(tp, TxConfig, val);
2548 }
2549
2550 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2551 {
2552         /* Low hurts. Let's disable the filtering. */
2553         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2554 }
2555
2556 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2557 {
2558         /*
2559          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2560          * register to be written before TxDescAddrLow to work.
2561          * Switching from MMIO to I/O access fixes the issue as well.
2562          */
2563         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2564         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2565         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2566         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2567 }
2568
2569 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2570 {
2571         u32 val;
2572
2573         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2574                 val = 0x000fff00;
2575         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2576                 val = 0x00ffff00;
2577         else
2578                 return;
2579
2580         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2581                 val |= 0xff;
2582
2583         RTL_W32(tp, 0x7c, val);
2584 }
2585
2586 static void rtl_set_rx_mode(struct net_device *dev)
2587 {
2588         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2589         /* Multicast hash filter */
2590         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2591         struct rtl8169_private *tp = netdev_priv(dev);
2592         u32 tmp;
2593
2594         if (dev->flags & IFF_PROMISC) {
2595                 rx_mode |= AcceptAllPhys;
2596         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2597                    dev->flags & IFF_ALLMULTI ||
2598                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2599                 /* accept all multicasts */
2600         } else if (netdev_mc_empty(dev)) {
2601                 rx_mode &= ~AcceptMulticast;
2602         } else {
2603                 struct netdev_hw_addr *ha;
2604
2605                 mc_filter[1] = mc_filter[0] = 0;
2606                 netdev_for_each_mc_addr(ha, dev) {
2607                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2608                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2609                 }
2610
2611                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2612                         tmp = mc_filter[0];
2613                         mc_filter[0] = swab32(mc_filter[1]);
2614                         mc_filter[1] = swab32(tmp);
2615                 }
2616         }
2617
2618         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2619         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2620
2621         tmp = RTL_R32(tp, RxConfig);
2622         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2623 }
2624
2625 DECLARE_RTL_COND(rtl_csiar_cond)
2626 {
2627         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2628 }
2629
2630 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2631 {
2632         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2633
2634         RTL_W32(tp, CSIDR, value);
2635         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2636                 CSIAR_BYTE_ENABLE | func << 16);
2637
2638         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2639 }
2640
2641 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2642 {
2643         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2644
2645         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2646                 CSIAR_BYTE_ENABLE);
2647
2648         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2649                 RTL_R32(tp, CSIDR) : ~0;
2650 }
2651
2652 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2653 {
2654         struct pci_dev *pdev = tp->pci_dev;
2655         u32 csi;
2656
2657         /* According to Realtek the value at config space address 0x070f
2658          * controls the L0s/L1 entrance latency. We try standard ECAM access
2659          * first and if it fails fall back to CSI.
2660          */
2661         if (pdev->cfg_size > 0x070f &&
2662             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2663                 return;
2664
2665         netdev_notice_once(tp->dev,
2666                 "No native access to PCI extended config space, falling back to CSI\n");
2667         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2668         rtl_csi_write(tp, 0x070c, csi | val << 24);
2669 }
2670
2671 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2672 {
2673         rtl_csi_access_enable(tp, 0x27);
2674 }
2675
2676 struct ephy_info {
2677         unsigned int offset;
2678         u16 mask;
2679         u16 bits;
2680 };
2681
2682 static void __rtl_ephy_init(struct rtl8169_private *tp,
2683                             const struct ephy_info *e, int len)
2684 {
2685         u16 w;
2686
2687         while (len-- > 0) {
2688                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2689                 rtl_ephy_write(tp, e->offset, w);
2690                 e++;
2691         }
2692 }
2693
2694 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2695
2696 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2697 {
2698         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2699                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2700 }
2701
2702 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2703 {
2704         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2705                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2706 }
2707
2708 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2709 {
2710         /* work around an issue when PCI reset occurs during L2/L3 state */
2711         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2712 }
2713
2714 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2715 {
2716         /* Don't enable ASPM in the chip if OS can't control ASPM */
2717         if (enable && tp->aspm_manageable) {
2718                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2719                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2720         } else {
2721                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2722                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2723         }
2724
2725         udelay(10);
2726 }
2727
2728 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2729                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2730 {
2731         /* Usage of dynamic vs. static FIFO is controlled by bit
2732          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2733          */
2734         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2735         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2736 }
2737
2738 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2739                                           u8 low, u8 high)
2740 {
2741         /* FIFO thresholds for pause flow control */
2742         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2743         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2744 }
2745
2746 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2747 {
2748         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2749 }
2750
2751 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2752 {
2753         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2754
2755         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2756
2757         rtl_disable_clock_request(tp);
2758 }
2759
2760 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2761 {
2762         static const struct ephy_info e_info_8168cp[] = {
2763                 { 0x01, 0,      0x0001 },
2764                 { 0x02, 0x0800, 0x1000 },
2765                 { 0x03, 0,      0x0042 },
2766                 { 0x06, 0x0080, 0x0000 },
2767                 { 0x07, 0,      0x2000 }
2768         };
2769
2770         rtl_set_def_aspm_entry_latency(tp);
2771
2772         rtl_ephy_init(tp, e_info_8168cp);
2773
2774         __rtl_hw_start_8168cp(tp);
2775 }
2776
2777 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2778 {
2779         rtl_set_def_aspm_entry_latency(tp);
2780
2781         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2782 }
2783
2784 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2785 {
2786         rtl_set_def_aspm_entry_latency(tp);
2787
2788         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2789
2790         /* Magic. */
2791         RTL_W8(tp, DBG_REG, 0x20);
2792 }
2793
2794 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2795 {
2796         static const struct ephy_info e_info_8168c_1[] = {
2797                 { 0x02, 0x0800, 0x1000 },
2798                 { 0x03, 0,      0x0002 },
2799                 { 0x06, 0x0080, 0x0000 }
2800         };
2801
2802         rtl_set_def_aspm_entry_latency(tp);
2803
2804         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2805
2806         rtl_ephy_init(tp, e_info_8168c_1);
2807
2808         __rtl_hw_start_8168cp(tp);
2809 }
2810
2811 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2812 {
2813         static const struct ephy_info e_info_8168c_2[] = {
2814                 { 0x01, 0,      0x0001 },
2815                 { 0x03, 0x0400, 0x0020 }
2816         };
2817
2818         rtl_set_def_aspm_entry_latency(tp);
2819
2820         rtl_ephy_init(tp, e_info_8168c_2);
2821
2822         __rtl_hw_start_8168cp(tp);
2823 }
2824
2825 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2826 {
2827         rtl_hw_start_8168c_2(tp);
2828 }
2829
2830 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2831 {
2832         rtl_set_def_aspm_entry_latency(tp);
2833
2834         __rtl_hw_start_8168cp(tp);
2835 }
2836
2837 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2838 {
2839         rtl_set_def_aspm_entry_latency(tp);
2840
2841         rtl_disable_clock_request(tp);
2842 }
2843
2844 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2845 {
2846         static const struct ephy_info e_info_8168d_4[] = {
2847                 { 0x0b, 0x0000, 0x0048 },
2848                 { 0x19, 0x0020, 0x0050 },
2849                 { 0x0c, 0x0100, 0x0020 },
2850                 { 0x10, 0x0004, 0x0000 },
2851         };
2852
2853         rtl_set_def_aspm_entry_latency(tp);
2854
2855         rtl_ephy_init(tp, e_info_8168d_4);
2856
2857         rtl_enable_clock_request(tp);
2858 }
2859
2860 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2861 {
2862         static const struct ephy_info e_info_8168e_1[] = {
2863                 { 0x00, 0x0200, 0x0100 },
2864                 { 0x00, 0x0000, 0x0004 },
2865                 { 0x06, 0x0002, 0x0001 },
2866                 { 0x06, 0x0000, 0x0030 },
2867                 { 0x07, 0x0000, 0x2000 },
2868                 { 0x00, 0x0000, 0x0020 },
2869                 { 0x03, 0x5800, 0x2000 },
2870                 { 0x03, 0x0000, 0x0001 },
2871                 { 0x01, 0x0800, 0x1000 },
2872                 { 0x07, 0x0000, 0x4000 },
2873                 { 0x1e, 0x0000, 0x2000 },
2874                 { 0x19, 0xffff, 0xfe6c },
2875                 { 0x0a, 0x0000, 0x0040 }
2876         };
2877
2878         rtl_set_def_aspm_entry_latency(tp);
2879
2880         rtl_ephy_init(tp, e_info_8168e_1);
2881
2882         rtl_disable_clock_request(tp);
2883
2884         /* Reset tx FIFO pointer */
2885         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2886         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2887
2888         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2889 }
2890
2891 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2892 {
2893         static const struct ephy_info e_info_8168e_2[] = {
2894                 { 0x09, 0x0000, 0x0080 },
2895                 { 0x19, 0x0000, 0x0224 },
2896                 { 0x00, 0x0000, 0x0004 },
2897                 { 0x0c, 0x3df0, 0x0200 },
2898         };
2899
2900         rtl_set_def_aspm_entry_latency(tp);
2901
2902         rtl_ephy_init(tp, e_info_8168e_2);
2903
2904         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2905         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2906         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2907         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2908         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2909         rtl_reset_packet_filter(tp);
2910         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2911         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2912         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2913
2914         rtl_disable_clock_request(tp);
2915
2916         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2917
2918         rtl8168_config_eee_mac(tp);
2919
2920         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2921         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2922         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2923
2924         rtl_hw_aspm_clkreq_enable(tp, true);
2925 }
2926
2927 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2928 {
2929         rtl_set_def_aspm_entry_latency(tp);
2930
2931         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2932         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2933         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2934         rtl_reset_packet_filter(tp);
2935         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2936         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2937         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2938         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2939
2940         rtl_disable_clock_request(tp);
2941
2942         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2943         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2944         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2945         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2946
2947         rtl8168_config_eee_mac(tp);
2948 }
2949
2950 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2951 {
2952         static const struct ephy_info e_info_8168f_1[] = {
2953                 { 0x06, 0x00c0, 0x0020 },
2954                 { 0x08, 0x0001, 0x0002 },
2955                 { 0x09, 0x0000, 0x0080 },
2956                 { 0x19, 0x0000, 0x0224 },
2957                 { 0x00, 0x0000, 0x0004 },
2958                 { 0x0c, 0x3df0, 0x0200 },
2959         };
2960
2961         rtl_hw_start_8168f(tp);
2962
2963         rtl_ephy_init(tp, e_info_8168f_1);
2964
2965         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2966 }
2967
2968 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2969 {
2970         static const struct ephy_info e_info_8168f_1[] = {
2971                 { 0x06, 0x00c0, 0x0020 },
2972                 { 0x0f, 0xffff, 0x5200 },
2973                 { 0x19, 0x0000, 0x0224 },
2974                 { 0x00, 0x0000, 0x0004 },
2975                 { 0x0c, 0x3df0, 0x0200 },
2976         };
2977
2978         rtl_hw_start_8168f(tp);
2979         rtl_pcie_state_l2l3_disable(tp);
2980
2981         rtl_ephy_init(tp, e_info_8168f_1);
2982
2983         rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2984 }
2985
2986 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2987 {
2988         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2989         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2990
2991         rtl_set_def_aspm_entry_latency(tp);
2992
2993         rtl_reset_packet_filter(tp);
2994         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2995
2996         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2997
2998         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2999         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3000         rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
3001
3002         rtl8168_config_eee_mac(tp);
3003
3004         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3005         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3006
3007         rtl_pcie_state_l2l3_disable(tp);
3008 }
3009
3010 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3011 {
3012         static const struct ephy_info e_info_8168g_1[] = {
3013                 { 0x00, 0x0008, 0x0000 },
3014                 { 0x0c, 0x3ff0, 0x0820 },
3015                 { 0x1e, 0x0000, 0x0001 },
3016                 { 0x19, 0x8000, 0x0000 }
3017         };
3018
3019         rtl_hw_start_8168g(tp);
3020
3021         /* disable aspm and clock request before access ephy */
3022         rtl_hw_aspm_clkreq_enable(tp, false);
3023         rtl_ephy_init(tp, e_info_8168g_1);
3024         rtl_hw_aspm_clkreq_enable(tp, true);
3025 }
3026
3027 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3028 {
3029         static const struct ephy_info e_info_8168g_2[] = {
3030                 { 0x00, 0x0008, 0x0000 },
3031                 { 0x0c, 0x3ff0, 0x0820 },
3032                 { 0x19, 0xffff, 0x7c00 },
3033                 { 0x1e, 0xffff, 0x20eb },
3034                 { 0x0d, 0xffff, 0x1666 },
3035                 { 0x00, 0xffff, 0x10a3 },
3036                 { 0x06, 0xffff, 0xf050 },
3037                 { 0x04, 0x0000, 0x0010 },
3038                 { 0x1d, 0x4000, 0x0000 },
3039         };
3040
3041         rtl_hw_start_8168g(tp);
3042
3043         /* disable aspm and clock request before access ephy */
3044         rtl_hw_aspm_clkreq_enable(tp, false);
3045         rtl_ephy_init(tp, e_info_8168g_2);
3046 }
3047
3048 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3049 {
3050         static const struct ephy_info e_info_8411_2[] = {
3051                 { 0x00, 0x0008, 0x0000 },
3052                 { 0x0c, 0x37d0, 0x0820 },
3053                 { 0x1e, 0x0000, 0x0001 },
3054                 { 0x19, 0x8021, 0x0000 },
3055                 { 0x1e, 0x0000, 0x2000 },
3056                 { 0x0d, 0x0100, 0x0200 },
3057                 { 0x00, 0x0000, 0x0080 },
3058                 { 0x06, 0x0000, 0x0010 },
3059                 { 0x04, 0x0000, 0x0010 },
3060                 { 0x1d, 0x0000, 0x4000 },
3061         };
3062
3063         rtl_hw_start_8168g(tp);
3064
3065         /* disable aspm and clock request before access ephy */
3066         rtl_hw_aspm_clkreq_enable(tp, false);
3067         rtl_ephy_init(tp, e_info_8411_2);
3068
3069         /* The following Realtek-provided magic fixes an issue with the RX unit
3070          * getting confused after the PHY having been powered-down.
3071          */
3072         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3073         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3074         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3075         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3076         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3077         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3078         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3079         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3080         mdelay(3);
3081         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3082
3083         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3084         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3085         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3086         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3087         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3088         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3089         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3090         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3091         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3092         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3093         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3094         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3095         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3096         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3097         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3098         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3099         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3100         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3101         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3102         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3103         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3104         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3105         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3106         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3107         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3108         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3109         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3110         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3111         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3112         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3113         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3114         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3115         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3116         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3117         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3118         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3119         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3120         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3121         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3122         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3123         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3124         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3125         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3126         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3127         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3128         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3129         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3130         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3131         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3132         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3133         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3134         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3135         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3136         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3137         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3138         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3139         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3140         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3141         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3142         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3143         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3144         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3145         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3146         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3147         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3148         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3149         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3150         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3151         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3152         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3153         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3154         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3155         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3156         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3157         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3158         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3159         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3160         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3161         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3162         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3163         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3164         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3165         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3166         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3167         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3168         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3169         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3170         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3171         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3172         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3173         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3174         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3175         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3176         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3177         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3178         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3179         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3180         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3181         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3182         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3183         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3184         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3185         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3186         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3187         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3188         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3189         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3190         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3191         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3192         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3193         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3194
3195         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3196
3197         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3198         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3199         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3200         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3201         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3202         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3203         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3204
3205         rtl_hw_aspm_clkreq_enable(tp, true);
3206 }
3207
3208 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3209 {
3210         static const struct ephy_info e_info_8168h_1[] = {
3211                 { 0x1e, 0x0800, 0x0001 },
3212                 { 0x1d, 0x0000, 0x0800 },
3213                 { 0x05, 0xffff, 0x2089 },
3214                 { 0x06, 0xffff, 0x5881 },
3215                 { 0x04, 0xffff, 0x854a },
3216                 { 0x01, 0xffff, 0x068b }
3217         };
3218         int rg_saw_cnt;
3219
3220         /* disable aspm and clock request before access ephy */
3221         rtl_hw_aspm_clkreq_enable(tp, false);
3222         rtl_ephy_init(tp, e_info_8168h_1);
3223
3224         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3225         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3226
3227         rtl_set_def_aspm_entry_latency(tp);
3228
3229         rtl_reset_packet_filter(tp);
3230
3231         rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3232         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3233
3234         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3235
3236         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3237
3238         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3239         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3240
3241         rtl8168_config_eee_mac(tp);
3242
3243         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3244         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3245
3246         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3247
3248         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3249
3250         rtl_pcie_state_l2l3_disable(tp);
3251
3252         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3253         if (rg_saw_cnt > 0) {
3254                 u16 sw_cnt_1ms_ini;
3255
3256                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3257                 sw_cnt_1ms_ini &= 0x0fff;
3258                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3259         }
3260
3261         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3262         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3263         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3264         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3265
3266         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3267         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3268         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3269         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3270
3271         rtl_hw_aspm_clkreq_enable(tp, true);
3272 }
3273
3274 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3275 {
3276         rtl8168ep_stop_cmac(tp);
3277
3278         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3279         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3280
3281         rtl_set_def_aspm_entry_latency(tp);
3282
3283         rtl_reset_packet_filter(tp);
3284
3285         rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3286
3287         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3288
3289         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3290
3291         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3292         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3293
3294         rtl8168_config_eee_mac(tp);
3295
3296         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3297
3298         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3299
3300         rtl_pcie_state_l2l3_disable(tp);
3301 }
3302
3303 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3304 {
3305         static const struct ephy_info e_info_8168ep_1[] = {
3306                 { 0x00, 0xffff, 0x10ab },
3307                 { 0x06, 0xffff, 0xf030 },
3308                 { 0x08, 0xffff, 0x2006 },
3309                 { 0x0d, 0xffff, 0x1666 },
3310                 { 0x0c, 0x3ff0, 0x0000 }
3311         };
3312
3313         /* disable aspm and clock request before access ephy */
3314         rtl_hw_aspm_clkreq_enable(tp, false);
3315         rtl_ephy_init(tp, e_info_8168ep_1);
3316
3317         rtl_hw_start_8168ep(tp);
3318
3319         rtl_hw_aspm_clkreq_enable(tp, true);
3320 }
3321
3322 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3323 {
3324         static const struct ephy_info e_info_8168ep_2[] = {
3325                 { 0x00, 0xffff, 0x10a3 },
3326                 { 0x19, 0xffff, 0xfc00 },
3327                 { 0x1e, 0xffff, 0x20ea }
3328         };
3329
3330         /* disable aspm and clock request before access ephy */
3331         rtl_hw_aspm_clkreq_enable(tp, false);
3332         rtl_ephy_init(tp, e_info_8168ep_2);
3333
3334         rtl_hw_start_8168ep(tp);
3335
3336         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3337         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3338
3339         rtl_hw_aspm_clkreq_enable(tp, true);
3340 }
3341
3342 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3343 {
3344         static const struct ephy_info e_info_8168ep_3[] = {
3345                 { 0x00, 0x0000, 0x0080 },
3346                 { 0x0d, 0x0100, 0x0200 },
3347                 { 0x19, 0x8021, 0x0000 },
3348                 { 0x1e, 0x0000, 0x2000 },
3349         };
3350
3351         /* disable aspm and clock request before access ephy */
3352         rtl_hw_aspm_clkreq_enable(tp, false);
3353         rtl_ephy_init(tp, e_info_8168ep_3);
3354
3355         rtl_hw_start_8168ep(tp);
3356
3357         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3358         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3359
3360         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3361         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3362         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3363
3364         rtl_hw_aspm_clkreq_enable(tp, true);
3365 }
3366
3367 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3368 {
3369         static const struct ephy_info e_info_8117[] = {
3370                 { 0x19, 0x0040, 0x1100 },
3371                 { 0x59, 0x0040, 0x1100 },
3372         };
3373         int rg_saw_cnt;
3374
3375         rtl8168ep_stop_cmac(tp);
3376
3377         /* disable aspm and clock request before access ephy */
3378         rtl_hw_aspm_clkreq_enable(tp, false);
3379         rtl_ephy_init(tp, e_info_8117);
3380
3381         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3382         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3383
3384         rtl_set_def_aspm_entry_latency(tp);
3385
3386         rtl_reset_packet_filter(tp);
3387
3388         rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3389
3390         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3391
3392         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3393
3394         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3395         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3396
3397         rtl8168_config_eee_mac(tp);
3398
3399         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3400         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3401
3402         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3403
3404         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3405
3406         rtl_pcie_state_l2l3_disable(tp);
3407
3408         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3409         if (rg_saw_cnt > 0) {
3410                 u16 sw_cnt_1ms_ini;
3411
3412                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3413                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3414         }
3415
3416         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3417         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3418         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3419         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3420
3421         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3422         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3423         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3424         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3425
3426         /* firmware is for MAC only */
3427         r8169_apply_firmware(tp);
3428
3429         rtl_hw_aspm_clkreq_enable(tp, true);
3430 }
3431
3432 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3433 {
3434         static const struct ephy_info e_info_8102e_1[] = {
3435                 { 0x01, 0, 0x6e65 },
3436                 { 0x02, 0, 0x091f },
3437                 { 0x03, 0, 0xc2f9 },
3438                 { 0x06, 0, 0xafb5 },
3439                 { 0x07, 0, 0x0e00 },
3440                 { 0x19, 0, 0xec80 },
3441                 { 0x01, 0, 0x2e65 },
3442                 { 0x01, 0, 0x6e65 }
3443         };
3444         u8 cfg1;
3445
3446         rtl_set_def_aspm_entry_latency(tp);
3447
3448         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3449
3450         RTL_W8(tp, Config1,
3451                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3452         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3453
3454         cfg1 = RTL_R8(tp, Config1);
3455         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3456                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3457
3458         rtl_ephy_init(tp, e_info_8102e_1);
3459 }
3460
3461 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3462 {
3463         rtl_set_def_aspm_entry_latency(tp);
3464
3465         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3466         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3467 }
3468
3469 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3470 {
3471         rtl_hw_start_8102e_2(tp);
3472
3473         rtl_ephy_write(tp, 0x03, 0xc2f9);
3474 }
3475
3476 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3477 {
3478         static const struct ephy_info e_info_8105e_1[] = {
3479                 { 0x07, 0, 0x4000 },
3480                 { 0x19, 0, 0x0200 },
3481                 { 0x19, 0, 0x0020 },
3482                 { 0x1e, 0, 0x2000 },
3483                 { 0x03, 0, 0x0001 },
3484                 { 0x19, 0, 0x0100 },
3485                 { 0x19, 0, 0x0004 },
3486                 { 0x0a, 0, 0x0020 }
3487         };
3488
3489         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3490         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3491
3492         /* Disable Early Tally Counter */
3493         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3494
3495         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3496         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3497
3498         rtl_ephy_init(tp, e_info_8105e_1);
3499
3500         rtl_pcie_state_l2l3_disable(tp);
3501 }
3502
3503 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3504 {
3505         rtl_hw_start_8105e_1(tp);
3506         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3507 }
3508
3509 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3510 {
3511         static const struct ephy_info e_info_8402[] = {
3512                 { 0x19, 0xffff, 0xff64 },
3513                 { 0x1e, 0, 0x4000 }
3514         };
3515
3516         rtl_set_def_aspm_entry_latency(tp);
3517
3518         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3519         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3520
3521         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3522
3523         rtl_ephy_init(tp, e_info_8402);
3524
3525         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3526         rtl_reset_packet_filter(tp);
3527         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3528         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3529         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3530
3531         /* disable EEE */
3532         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3533
3534         rtl_pcie_state_l2l3_disable(tp);
3535 }
3536
3537 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3538 {
3539         rtl_hw_aspm_clkreq_enable(tp, false);
3540
3541         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3542         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3543
3544         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3545         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3546         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3547
3548         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3549
3550         /* disable EEE */
3551         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3552
3553         rtl_pcie_state_l2l3_disable(tp);
3554         rtl_hw_aspm_clkreq_enable(tp, true);
3555 }
3556
3557 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3558 {
3559         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3560 }
3561
3562 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3563 {
3564         rtl_pcie_state_l2l3_disable(tp);
3565
3566         RTL_W16(tp, 0x382, 0x221b);
3567         RTL_W8(tp, 0x4500, 0);
3568         RTL_W16(tp, 0x4800, 0);
3569
3570         /* disable UPS */
3571         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3572
3573         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3574
3575         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3576         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3577
3578         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3579         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3580         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3581
3582         /* disable new tx descriptor format */
3583         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3584
3585         r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3586         r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3587         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3588         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3589         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3590         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3591         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3592         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3593         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
3594         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3595         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3596         r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
3597         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3598         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3599         udelay(1);
3600         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3601         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3602
3603         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3604
3605         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3606
3607         rtl8125_config_eee_mac(tp);
3608
3609         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3610         udelay(10);
3611 }
3612
3613 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
3614 {
3615         static const struct ephy_info e_info_8125_1[] = {
3616                 { 0x01, 0xffff, 0xa812 },
3617                 { 0x09, 0xffff, 0x520c },
3618                 { 0x04, 0xffff, 0xd000 },
3619                 { 0x0d, 0xffff, 0xf702 },
3620                 { 0x0a, 0xffff, 0x8653 },
3621                 { 0x06, 0xffff, 0x001e },
3622                 { 0x08, 0xffff, 0x3595 },
3623                 { 0x20, 0xffff, 0x9455 },
3624                 { 0x21, 0xffff, 0x99ff },
3625                 { 0x02, 0xffff, 0x6046 },
3626                 { 0x29, 0xffff, 0xfe00 },
3627                 { 0x23, 0xffff, 0xab62 },
3628
3629                 { 0x41, 0xffff, 0xa80c },
3630                 { 0x49, 0xffff, 0x520c },
3631                 { 0x44, 0xffff, 0xd000 },
3632                 { 0x4d, 0xffff, 0xf702 },
3633                 { 0x4a, 0xffff, 0x8653 },
3634                 { 0x46, 0xffff, 0x001e },
3635                 { 0x48, 0xffff, 0x3595 },
3636                 { 0x60, 0xffff, 0x9455 },
3637                 { 0x61, 0xffff, 0x99ff },
3638                 { 0x42, 0xffff, 0x6046 },
3639                 { 0x69, 0xffff, 0xfe00 },
3640                 { 0x63, 0xffff, 0xab62 },
3641         };
3642
3643         rtl_set_def_aspm_entry_latency(tp);
3644
3645         /* disable aspm and clock request before access ephy */
3646         rtl_hw_aspm_clkreq_enable(tp, false);
3647         rtl_ephy_init(tp, e_info_8125_1);
3648
3649         rtl_hw_start_8125_common(tp);
3650 }
3651
3652 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
3653 {
3654         static const struct ephy_info e_info_8125_2[] = {
3655                 { 0x04, 0xffff, 0xd000 },
3656                 { 0x0a, 0xffff, 0x8653 },
3657                 { 0x23, 0xffff, 0xab66 },
3658                 { 0x20, 0xffff, 0x9455 },
3659                 { 0x21, 0xffff, 0x99ff },
3660                 { 0x29, 0xffff, 0xfe04 },
3661
3662                 { 0x44, 0xffff, 0xd000 },
3663                 { 0x4a, 0xffff, 0x8653 },
3664                 { 0x63, 0xffff, 0xab66 },
3665                 { 0x60, 0xffff, 0x9455 },
3666                 { 0x61, 0xffff, 0x99ff },
3667                 { 0x69, 0xffff, 0xfe04 },
3668         };
3669
3670         rtl_set_def_aspm_entry_latency(tp);
3671
3672         /* disable aspm and clock request before access ephy */
3673         rtl_hw_aspm_clkreq_enable(tp, false);
3674         rtl_ephy_init(tp, e_info_8125_2);
3675
3676         rtl_hw_start_8125_common(tp);
3677 }
3678
3679 static void rtl_hw_config(struct rtl8169_private *tp)
3680 {
3681         static const rtl_generic_fct hw_configs[] = {
3682                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3683                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3684                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3685                 [RTL_GIGA_MAC_VER_10] = NULL,
3686                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3687                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3688                 [RTL_GIGA_MAC_VER_13] = NULL,
3689                 [RTL_GIGA_MAC_VER_14] = NULL,
3690                 [RTL_GIGA_MAC_VER_15] = NULL,
3691                 [RTL_GIGA_MAC_VER_16] = NULL,
3692                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3693                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3694                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3695                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3696                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3697                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3698                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3699                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3700                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3701                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3702                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3703                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3704                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3705                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3706                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3707                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3708                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3709                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3710                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3711                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3712                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3713                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3714                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3715                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3716                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3717                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3718                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3719                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3720                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3721                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3722                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3723                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3724                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3725                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3726                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3727                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3728                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
3729                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
3730         };
3731
3732         if (hw_configs[tp->mac_version])
3733                 hw_configs[tp->mac_version](tp);
3734 }
3735
3736 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3737 {
3738         int i;
3739
3740         /* disable interrupt coalescing */
3741         for (i = 0xa00; i < 0xb00; i += 4)
3742                 RTL_W32(tp, i, 0);
3743
3744         rtl_hw_config(tp);
3745 }
3746
3747 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3748 {
3749         if (rtl_is_8168evl_up(tp))
3750                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3751         else
3752                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3753
3754         rtl_hw_config(tp);
3755
3756         /* disable interrupt coalescing */
3757         RTL_W16(tp, IntrMitigate, 0x0000);
3758 }
3759
3760 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3761 {
3762         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3763
3764         tp->cp_cmd |= PCIMulRW;
3765
3766         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3767             tp->mac_version == RTL_GIGA_MAC_VER_03)
3768                 tp->cp_cmd |= EnAnaPLL;
3769
3770         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3771
3772         rtl8169_set_magic_reg(tp);
3773
3774         /* disable interrupt coalescing */
3775         RTL_W16(tp, IntrMitigate, 0x0000);
3776 }
3777
3778 static void rtl_hw_start(struct  rtl8169_private *tp)
3779 {
3780         rtl_unlock_config_regs(tp);
3781
3782         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3783
3784         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3785                 rtl_hw_start_8169(tp);
3786         else if (rtl_is_8125(tp))
3787                 rtl_hw_start_8125(tp);
3788         else
3789                 rtl_hw_start_8168(tp);
3790
3791         rtl_set_rx_max_size(tp);
3792         rtl_set_rx_tx_desc_registers(tp);
3793         rtl_lock_config_regs(tp);
3794
3795         rtl_jumbo_config(tp);
3796
3797         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3798         rtl_pci_commit(tp);
3799
3800         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3801         rtl_init_rxcfg(tp);
3802         rtl_set_tx_config_registers(tp);
3803         rtl_set_rx_config_features(tp, tp->dev->features);
3804         rtl_set_rx_mode(tp->dev);
3805         rtl_irq_enable(tp);
3806 }
3807
3808 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3809 {
3810         struct rtl8169_private *tp = netdev_priv(dev);
3811
3812         dev->mtu = new_mtu;
3813         netdev_update_features(dev);
3814         rtl_jumbo_config(tp);
3815
3816         return 0;
3817 }
3818
3819 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3820 {
3821         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3822
3823         desc->opts2 = 0;
3824         /* Force memory writes to complete before releasing descriptor */
3825         dma_wmb();
3826         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3827 }
3828
3829 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3830                                           struct RxDesc *desc)
3831 {
3832         struct device *d = tp_to_dev(tp);
3833         int node = dev_to_node(d);
3834         dma_addr_t mapping;
3835         struct page *data;
3836
3837         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3838         if (!data)
3839                 return NULL;
3840
3841         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3842         if (unlikely(dma_mapping_error(d, mapping))) {
3843                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3844                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3845                 return NULL;
3846         }
3847
3848         desc->addr = cpu_to_le64(mapping);
3849         rtl8169_mark_to_asic(desc);
3850
3851         return data;
3852 }
3853
3854 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3855 {
3856         unsigned int i;
3857
3858         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3859                 dma_unmap_page(tp_to_dev(tp),
3860                                le64_to_cpu(tp->RxDescArray[i].addr),
3861                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3862                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3863                 tp->Rx_databuff[i] = NULL;
3864                 tp->RxDescArray[i].addr = 0;
3865                 tp->RxDescArray[i].opts1 = 0;
3866         }
3867 }
3868
3869 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3870 {
3871         unsigned int i;
3872
3873         for (i = 0; i < NUM_RX_DESC; i++) {
3874                 struct page *data;
3875
3876                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3877                 if (!data) {
3878                         rtl8169_rx_clear(tp);
3879                         return -ENOMEM;
3880                 }
3881                 tp->Rx_databuff[i] = data;
3882         }
3883
3884         /* mark as last descriptor in the ring */
3885         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3886
3887         return 0;
3888 }
3889
3890 static int rtl8169_init_ring(struct rtl8169_private *tp)
3891 {
3892         rtl8169_init_ring_indexes(tp);
3893
3894         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3895         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3896
3897         return rtl8169_rx_fill(tp);
3898 }
3899
3900 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3901 {
3902         struct ring_info *tx_skb = tp->tx_skb + entry;
3903         struct TxDesc *desc = tp->TxDescArray + entry;
3904
3905         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3906                          DMA_TO_DEVICE);
3907         memset(desc, 0, sizeof(*desc));
3908         memset(tx_skb, 0, sizeof(*tx_skb));
3909 }
3910
3911 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3912                                    unsigned int n)
3913 {
3914         unsigned int i;
3915
3916         for (i = 0; i < n; i++) {
3917                 unsigned int entry = (start + i) % NUM_TX_DESC;
3918                 struct ring_info *tx_skb = tp->tx_skb + entry;
3919                 unsigned int len = tx_skb->len;
3920
3921                 if (len) {
3922                         struct sk_buff *skb = tx_skb->skb;
3923
3924                         rtl8169_unmap_tx_skb(tp, entry);
3925                         if (skb)
3926                                 dev_consume_skb_any(skb);
3927                 }
3928         }
3929 }
3930
3931 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3932 {
3933         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3934         netdev_reset_queue(tp->dev);
3935 }
3936
3937 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3938 {
3939         napi_disable(&tp->napi);
3940
3941         /* Give a racing hard_start_xmit a few cycles to complete. */
3942         synchronize_net();
3943
3944         /* Disable interrupts */
3945         rtl8169_irq_mask_and_ack(tp);
3946
3947         rtl_rx_close(tp);
3948
3949         if (going_down && tp->dev->wol_enabled)
3950                 goto no_reset;
3951
3952         switch (tp->mac_version) {
3953         case RTL_GIGA_MAC_VER_27:
3954         case RTL_GIGA_MAC_VER_28:
3955         case RTL_GIGA_MAC_VER_31:
3956                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3957                 break;
3958         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3959                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3960                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3961                 break;
3962         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
3963                 rtl_enable_rxdvgate(tp);
3964                 fsleep(2000);
3965                 break;
3966         default:
3967                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3968                 fsleep(100);
3969                 break;
3970         }
3971
3972         rtl_hw_reset(tp);
3973 no_reset:
3974         rtl8169_tx_clear(tp);
3975         rtl8169_init_ring_indexes(tp);
3976 }
3977
3978 static void rtl_reset_work(struct rtl8169_private *tp)
3979 {
3980         int i;
3981
3982         netif_stop_queue(tp->dev);
3983
3984         rtl8169_cleanup(tp, false);
3985
3986         for (i = 0; i < NUM_RX_DESC; i++)
3987                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3988
3989         napi_enable(&tp->napi);
3990         rtl_hw_start(tp);
3991 }
3992
3993 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3994 {
3995         struct rtl8169_private *tp = netdev_priv(dev);
3996
3997         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
3998 }
3999
4000 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4001                           void *addr, unsigned int entry, bool desc_own)
4002 {
4003         struct TxDesc *txd = tp->TxDescArray + entry;
4004         struct device *d = tp_to_dev(tp);
4005         dma_addr_t mapping;
4006         u32 opts1;
4007         int ret;
4008
4009         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4010         ret = dma_mapping_error(d, mapping);
4011         if (unlikely(ret)) {
4012                 if (net_ratelimit())
4013                         netdev_err(tp->dev, "Failed to map TX data!\n");
4014                 return ret;
4015         }
4016
4017         txd->addr = cpu_to_le64(mapping);
4018         txd->opts2 = cpu_to_le32(opts[1]);
4019
4020         opts1 = opts[0] | len;
4021         if (entry == NUM_TX_DESC - 1)
4022                 opts1 |= RingEnd;
4023         if (desc_own)
4024                 opts1 |= DescOwn;
4025         txd->opts1 = cpu_to_le32(opts1);
4026
4027         tp->tx_skb[entry].len = len;
4028
4029         return 0;
4030 }
4031
4032 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4033                               const u32 *opts, unsigned int entry)
4034 {
4035         struct skb_shared_info *info = skb_shinfo(skb);
4036         unsigned int cur_frag;
4037
4038         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4039                 const skb_frag_t *frag = info->frags + cur_frag;
4040                 void *addr = skb_frag_address(frag);
4041                 u32 len = skb_frag_size(frag);
4042
4043                 entry = (entry + 1) % NUM_TX_DESC;
4044
4045                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4046                         goto err_out;
4047         }
4048
4049         return 0;
4050
4051 err_out:
4052         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4053         return -EIO;
4054 }
4055
4056 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4057 {
4058         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4059 }
4060
4061 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4062 {
4063         u32 mss = skb_shinfo(skb)->gso_size;
4064
4065         if (mss) {
4066                 opts[0] |= TD_LSO;
4067                 opts[0] |= mss << TD0_MSS_SHIFT;
4068         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4069                 const struct iphdr *ip = ip_hdr(skb);
4070
4071                 if (ip->protocol == IPPROTO_TCP)
4072                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4073                 else if (ip->protocol == IPPROTO_UDP)
4074                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4075                 else
4076                         WARN_ON_ONCE(1);
4077         }
4078 }
4079
4080 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4081                                 struct sk_buff *skb, u32 *opts)
4082 {
4083         u32 transport_offset = (u32)skb_transport_offset(skb);
4084         struct skb_shared_info *shinfo = skb_shinfo(skb);
4085         u32 mss = shinfo->gso_size;
4086
4087         if (mss) {
4088                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4089                         opts[0] |= TD1_GTSENV4;
4090                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4091                         if (skb_cow_head(skb, 0))
4092                                 return false;
4093
4094                         tcp_v6_gso_csum_prep(skb);
4095                         opts[0] |= TD1_GTSENV6;
4096                 } else {
4097                         WARN_ON_ONCE(1);
4098                 }
4099
4100                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4101                 opts[1] |= mss << TD1_MSS_SHIFT;
4102         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4103                 u8 ip_protocol;
4104
4105                 switch (vlan_get_protocol(skb)) {
4106                 case htons(ETH_P_IP):
4107                         opts[1] |= TD1_IPv4_CS;
4108                         ip_protocol = ip_hdr(skb)->protocol;
4109                         break;
4110
4111                 case htons(ETH_P_IPV6):
4112                         opts[1] |= TD1_IPv6_CS;
4113                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4114                         break;
4115
4116                 default:
4117                         ip_protocol = IPPROTO_RAW;
4118                         break;
4119                 }
4120
4121                 if (ip_protocol == IPPROTO_TCP)
4122                         opts[1] |= TD1_TCP_CS;
4123                 else if (ip_protocol == IPPROTO_UDP)
4124                         opts[1] |= TD1_UDP_CS;
4125                 else
4126                         WARN_ON_ONCE(1);
4127
4128                 opts[1] |= transport_offset << TCPHO_SHIFT;
4129         } else {
4130                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4131                         return !eth_skb_pad(skb);
4132         }
4133
4134         return true;
4135 }
4136
4137 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4138                                unsigned int nr_frags)
4139 {
4140         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4141
4142         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4143         return slots_avail > nr_frags;
4144 }
4145
4146 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4147 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4148 {
4149         switch (tp->mac_version) {
4150         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4151         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4152                 return false;
4153         default:
4154                 return true;
4155         }
4156 }
4157
4158 static void rtl8169_doorbell(struct rtl8169_private *tp)
4159 {
4160         if (rtl_is_8125(tp))
4161                 RTL_W16(tp, TxPoll_8125, BIT(0));
4162         else
4163                 RTL_W8(tp, TxPoll, NPQ);
4164 }
4165
4166 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4167                                       struct net_device *dev)
4168 {
4169         unsigned int frags = skb_shinfo(skb)->nr_frags;
4170         struct rtl8169_private *tp = netdev_priv(dev);
4171         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4172         struct TxDesc *txd_first, *txd_last;
4173         bool stop_queue, door_bell;
4174         u32 opts[2];
4175
4176         txd_first = tp->TxDescArray + entry;
4177
4178         if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4179                 if (net_ratelimit())
4180                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4181                 goto err_stop_0;
4182         }
4183
4184         if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4185                 goto err_stop_0;
4186
4187         opts[1] = rtl8169_tx_vlan_tag(skb);
4188         opts[0] = 0;
4189
4190         if (!rtl_chip_supports_csum_v2(tp))
4191                 rtl8169_tso_csum_v1(skb, opts);
4192         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4193                 goto err_dma_0;
4194
4195         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4196                                     entry, false)))
4197                 goto err_dma_0;
4198
4199         if (frags) {
4200                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4201                         goto err_dma_1;
4202                 entry = (entry + frags) % NUM_TX_DESC;
4203         }
4204
4205         txd_last = tp->TxDescArray + entry;
4206         txd_last->opts1 |= cpu_to_le32(LastFrag);
4207         tp->tx_skb[entry].skb = skb;
4208
4209         skb_tx_timestamp(skb);
4210
4211         /* Force memory writes to complete before releasing descriptor */
4212         dma_wmb();
4213
4214         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4215
4216         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4217
4218         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4219         smp_wmb();
4220
4221         tp->cur_tx += frags + 1;
4222
4223         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4224         if (unlikely(stop_queue)) {
4225                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4226                  * not miss a ring update when it notices a stopped queue.
4227                  */
4228                 smp_wmb();
4229                 netif_stop_queue(dev);
4230                 door_bell = true;
4231         }
4232
4233         if (door_bell)
4234                 rtl8169_doorbell(tp);
4235
4236         if (unlikely(stop_queue)) {
4237                 /* Sync with rtl_tx:
4238                  * - publish queue status and cur_tx ring index (write barrier)
4239                  * - refresh dirty_tx ring index (read barrier).
4240                  * May the current thread have a pessimistic view of the ring
4241                  * status and forget to wake up queue, a racing rtl_tx thread
4242                  * can't.
4243                  */
4244                 smp_mb();
4245                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4246                         netif_start_queue(dev);
4247         }
4248
4249         return NETDEV_TX_OK;
4250
4251 err_dma_1:
4252         rtl8169_unmap_tx_skb(tp, entry);
4253 err_dma_0:
4254         dev_kfree_skb_any(skb);
4255         dev->stats.tx_dropped++;
4256         return NETDEV_TX_OK;
4257
4258 err_stop_0:
4259         netif_stop_queue(dev);
4260         dev->stats.tx_dropped++;
4261         return NETDEV_TX_BUSY;
4262 }
4263
4264 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4265 {
4266         struct skb_shared_info *info = skb_shinfo(skb);
4267         unsigned int nr_frags = info->nr_frags;
4268
4269         if (!nr_frags)
4270                 return UINT_MAX;
4271
4272         return skb_frag_size(info->frags + nr_frags - 1);
4273 }
4274
4275 /* Workaround for hw issues with TSO on RTL8168evl */
4276 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4277                                             netdev_features_t features)
4278 {
4279         /* IPv4 header has options field */
4280         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4281             ip_hdrlen(skb) > sizeof(struct iphdr))
4282                 features &= ~NETIF_F_ALL_TSO;
4283
4284         /* IPv4 TCP header has options field */
4285         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4286                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4287                 features &= ~NETIF_F_ALL_TSO;
4288
4289         else if (rtl_last_frag_len(skb) <= 6)
4290                 features &= ~NETIF_F_ALL_TSO;
4291
4292         return features;
4293 }
4294
4295 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4296                                                 struct net_device *dev,
4297                                                 netdev_features_t features)
4298 {
4299         int transport_offset = skb_transport_offset(skb);
4300         struct rtl8169_private *tp = netdev_priv(dev);
4301
4302         if (skb_is_gso(skb)) {
4303                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4304                         features = rtl8168evl_fix_tso(skb, features);
4305
4306                 if (transport_offset > GTTCPHO_MAX &&
4307                     rtl_chip_supports_csum_v2(tp))
4308                         features &= ~NETIF_F_ALL_TSO;
4309         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4310                 if (skb->len < ETH_ZLEN) {
4311                         switch (tp->mac_version) {
4312                         case RTL_GIGA_MAC_VER_11:
4313                         case RTL_GIGA_MAC_VER_12:
4314                         case RTL_GIGA_MAC_VER_17:
4315                         case RTL_GIGA_MAC_VER_34:
4316                                 features &= ~NETIF_F_CSUM_MASK;
4317                                 break;
4318                         default:
4319                                 break;
4320                         }
4321                 }
4322
4323                 if (transport_offset > TCPHO_MAX &&
4324                     rtl_chip_supports_csum_v2(tp))
4325                         features &= ~NETIF_F_CSUM_MASK;
4326         }
4327
4328         return vlan_features_check(skb, features);
4329 }
4330
4331 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4332 {
4333         struct rtl8169_private *tp = netdev_priv(dev);
4334         struct pci_dev *pdev = tp->pci_dev;
4335         int pci_status_errs;
4336         u16 pci_cmd;
4337
4338         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4339
4340         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4341
4342         if (net_ratelimit())
4343                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4344                            pci_cmd, pci_status_errs);
4345         /*
4346          * The recovery sequence below admits a very elaborated explanation:
4347          * - it seems to work;
4348          * - I did not see what else could be done;
4349          * - it makes iop3xx happy.
4350          *
4351          * Feel free to adjust to your needs.
4352          */
4353         if (pdev->broken_parity_status)
4354                 pci_cmd &= ~PCI_COMMAND_PARITY;
4355         else
4356                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4357
4358         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4359
4360         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4361 }
4362
4363 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4364                    int budget)
4365 {
4366         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4367
4368         dirty_tx = tp->dirty_tx;
4369         smp_rmb();
4370
4371         for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4372                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4373                 struct sk_buff *skb = tp->tx_skb[entry].skb;
4374                 u32 status;
4375
4376                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4377                 if (status & DescOwn)
4378                         break;
4379
4380                 rtl8169_unmap_tx_skb(tp, entry);
4381
4382                 if (skb) {
4383                         pkts_compl++;
4384                         bytes_compl += skb->len;
4385                         napi_consume_skb(skb, budget);
4386                 }
4387                 dirty_tx++;
4388         }
4389
4390         if (tp->dirty_tx != dirty_tx) {
4391                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4392
4393                 u64_stats_update_begin(&tp->tx_stats.syncp);
4394                 tp->tx_stats.packets += pkts_compl;
4395                 tp->tx_stats.bytes += bytes_compl;
4396                 u64_stats_update_end(&tp->tx_stats.syncp);
4397
4398                 tp->dirty_tx = dirty_tx;
4399                 /* Sync with rtl8169_start_xmit:
4400                  * - publish dirty_tx ring index (write barrier)
4401                  * - refresh cur_tx ring index and queue status (read barrier)
4402                  * May the current thread miss the stopped queue condition,
4403                  * a racing xmit thread can only have a right view of the
4404                  * ring status.
4405                  */
4406                 smp_mb();
4407                 if (netif_queue_stopped(dev) &&
4408                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4409                         netif_wake_queue(dev);
4410                 }
4411                 /*
4412                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4413                  * too close. Let's kick an extra TxPoll request when a burst
4414                  * of start_xmit activity is detected (if it is not detected,
4415                  * it is slow enough). -- FR
4416                  */
4417                 if (tp->cur_tx != dirty_tx)
4418                         rtl8169_doorbell(tp);
4419         }
4420 }
4421
4422 static inline int rtl8169_fragmented_frame(u32 status)
4423 {
4424         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4425 }
4426
4427 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4428 {
4429         u32 status = opts1 & RxProtoMask;
4430
4431         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4432             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4433                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4434         else
4435                 skb_checksum_none_assert(skb);
4436 }
4437
4438 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4439 {
4440         unsigned int cur_rx, rx_left, count;
4441         struct device *d = tp_to_dev(tp);
4442
4443         cur_rx = tp->cur_rx;
4444
4445         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4446                 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4447                 struct RxDesc *desc = tp->RxDescArray + entry;
4448                 struct sk_buff *skb;
4449                 const void *rx_buf;
4450                 dma_addr_t addr;
4451                 u32 status;
4452
4453                 status = le32_to_cpu(desc->opts1);
4454                 if (status & DescOwn)
4455                         break;
4456
4457                 /* This barrier is needed to keep us from reading
4458                  * any other fields out of the Rx descriptor until
4459                  * we know the status of DescOwn
4460                  */
4461                 dma_rmb();
4462
4463                 if (unlikely(status & RxRES)) {
4464                         if (net_ratelimit())
4465                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4466                                             status);
4467                         dev->stats.rx_errors++;
4468                         if (status & (RxRWT | RxRUNT))
4469                                 dev->stats.rx_length_errors++;
4470                         if (status & RxCRC)
4471                                 dev->stats.rx_crc_errors++;
4472
4473                         if (!(dev->features & NETIF_F_RXALL))
4474                                 goto release_descriptor;
4475                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4476                                 goto release_descriptor;
4477                 }
4478
4479                 pkt_size = status & GENMASK(13, 0);
4480                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4481                         pkt_size -= ETH_FCS_LEN;
4482
4483                 /* The driver does not support incoming fragmented frames.
4484                  * They are seen as a symptom of over-mtu sized frames.
4485                  */
4486                 if (unlikely(rtl8169_fragmented_frame(status))) {
4487                         dev->stats.rx_dropped++;
4488                         dev->stats.rx_length_errors++;
4489                         goto release_descriptor;
4490                 }
4491
4492                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4493                 if (unlikely(!skb)) {
4494                         dev->stats.rx_dropped++;
4495                         goto release_descriptor;
4496                 }
4497
4498                 addr = le64_to_cpu(desc->addr);
4499                 rx_buf = page_address(tp->Rx_databuff[entry]);
4500
4501                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4502                 prefetch(rx_buf);
4503                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4504                 skb->tail += pkt_size;
4505                 skb->len = pkt_size;
4506                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4507
4508                 rtl8169_rx_csum(skb, status);
4509                 skb->protocol = eth_type_trans(skb, dev);
4510
4511                 rtl8169_rx_vlan_tag(desc, skb);
4512
4513                 if (skb->pkt_type == PACKET_MULTICAST)
4514                         dev->stats.multicast++;
4515
4516                 napi_gro_receive(&tp->napi, skb);
4517
4518                 u64_stats_update_begin(&tp->rx_stats.syncp);
4519                 tp->rx_stats.packets++;
4520                 tp->rx_stats.bytes += pkt_size;
4521                 u64_stats_update_end(&tp->rx_stats.syncp);
4522
4523 release_descriptor:
4524                 rtl8169_mark_to_asic(desc);
4525         }
4526
4527         count = cur_rx - tp->cur_rx;
4528         tp->cur_rx = cur_rx;
4529
4530         return count;
4531 }
4532
4533 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4534 {
4535         struct rtl8169_private *tp = dev_instance;
4536         u32 status = rtl_get_events(tp);
4537
4538         if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
4539             !(status & tp->irq_mask))
4540                 return IRQ_NONE;
4541
4542         if (unlikely(status & SYSErr)) {
4543                 rtl8169_pcierr_interrupt(tp->dev);
4544                 goto out;
4545         }
4546
4547         if (status & LinkChg)
4548                 phy_mac_interrupt(tp->phydev);
4549
4550         if (unlikely(status & RxFIFOOver &&
4551             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4552                 netif_stop_queue(tp->dev);
4553                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4554         }
4555
4556         rtl_irq_disable(tp);
4557         napi_schedule_irqoff(&tp->napi);
4558 out:
4559         rtl_ack_events(tp, status);
4560
4561         return IRQ_HANDLED;
4562 }
4563
4564 static void rtl_task(struct work_struct *work)
4565 {
4566         struct rtl8169_private *tp =
4567                 container_of(work, struct rtl8169_private, wk.work);
4568
4569         rtl_lock_work(tp);
4570
4571         if (!netif_running(tp->dev) ||
4572             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4573                 goto out_unlock;
4574
4575         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4576                 rtl_reset_work(tp);
4577                 netif_wake_queue(tp->dev);
4578         }
4579 out_unlock:
4580         rtl_unlock_work(tp);
4581 }
4582
4583 static int rtl8169_poll(struct napi_struct *napi, int budget)
4584 {
4585         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4586         struct net_device *dev = tp->dev;
4587         int work_done;
4588
4589         work_done = rtl_rx(dev, tp, (u32) budget);
4590
4591         rtl_tx(dev, tp, budget);
4592
4593         if (work_done < budget) {
4594                 napi_complete_done(napi, work_done);
4595                 rtl_irq_enable(tp);
4596         }
4597
4598         return work_done;
4599 }
4600
4601 static void r8169_phylink_handler(struct net_device *ndev)
4602 {
4603         struct rtl8169_private *tp = netdev_priv(ndev);
4604
4605         if (netif_carrier_ok(ndev)) {
4606                 rtl_link_chg_patch(tp);
4607                 pm_request_resume(&tp->pci_dev->dev);
4608         } else {
4609                 pm_runtime_idle(&tp->pci_dev->dev);
4610         }
4611
4612         if (net_ratelimit())
4613                 phy_print_status(tp->phydev);
4614 }
4615
4616 static int r8169_phy_connect(struct rtl8169_private *tp)
4617 {
4618         struct phy_device *phydev = tp->phydev;
4619         phy_interface_t phy_mode;
4620         int ret;
4621
4622         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4623                    PHY_INTERFACE_MODE_MII;
4624
4625         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4626                                  phy_mode);
4627         if (ret)
4628                 return ret;
4629
4630         if (!tp->supports_gmii)
4631                 phy_set_max_speed(phydev, SPEED_100);
4632
4633         phy_support_asym_pause(phydev);
4634
4635         phy_attached_info(phydev);
4636
4637         return 0;
4638 }
4639
4640 static void rtl8169_down(struct rtl8169_private *tp)
4641 {
4642         rtl_lock_work(tp);
4643
4644         /* Clear all task flags */
4645         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4646
4647         phy_stop(tp->phydev);
4648
4649         rtl8169_update_counters(tp);
4650
4651         rtl8169_cleanup(tp, true);
4652
4653         rtl_pll_power_down(tp);
4654
4655         rtl_unlock_work(tp);
4656 }
4657
4658 static int rtl8169_close(struct net_device *dev)
4659 {
4660         struct rtl8169_private *tp = netdev_priv(dev);
4661         struct pci_dev *pdev = tp->pci_dev;
4662
4663         pm_runtime_get_sync(&pdev->dev);
4664
4665         netif_stop_queue(dev);
4666         rtl8169_down(tp);
4667         rtl8169_rx_clear(tp);
4668
4669         cancel_work_sync(&tp->wk.work);
4670
4671         phy_disconnect(tp->phydev);
4672
4673         pci_free_irq(pdev, 0, tp);
4674
4675         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4676                           tp->RxPhyAddr);
4677         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4678                           tp->TxPhyAddr);
4679         tp->TxDescArray = NULL;
4680         tp->RxDescArray = NULL;
4681
4682         pm_runtime_put_sync(&pdev->dev);
4683
4684         return 0;
4685 }
4686
4687 #ifdef CONFIG_NET_POLL_CONTROLLER
4688 static void rtl8169_netpoll(struct net_device *dev)
4689 {
4690         struct rtl8169_private *tp = netdev_priv(dev);
4691
4692         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4693 }
4694 #endif
4695
4696 static int rtl_open(struct net_device *dev)
4697 {
4698         struct rtl8169_private *tp = netdev_priv(dev);
4699         struct pci_dev *pdev = tp->pci_dev;
4700         int retval = -ENOMEM;
4701
4702         pm_runtime_get_sync(&pdev->dev);
4703
4704         /*
4705          * Rx and Tx descriptors needs 256 bytes alignment.
4706          * dma_alloc_coherent provides more.
4707          */
4708         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4709                                              &tp->TxPhyAddr, GFP_KERNEL);
4710         if (!tp->TxDescArray)
4711                 goto err_pm_runtime_put;
4712
4713         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4714                                              &tp->RxPhyAddr, GFP_KERNEL);
4715         if (!tp->RxDescArray)
4716                 goto err_free_tx_0;
4717
4718         retval = rtl8169_init_ring(tp);
4719         if (retval < 0)
4720                 goto err_free_rx_1;
4721
4722         rtl_request_firmware(tp);
4723
4724         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
4725                                  dev->name);
4726         if (retval < 0)
4727                 goto err_release_fw_2;
4728
4729         retval = r8169_phy_connect(tp);
4730         if (retval)
4731                 goto err_free_irq;
4732
4733         rtl_lock_work(tp);
4734
4735         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4736
4737         napi_enable(&tp->napi);
4738
4739         rtl8169_init_phy(tp);
4740
4741         rtl_pll_power_up(tp);
4742
4743         rtl_hw_start(tp);
4744
4745         rtl8169_init_counter_offsets(tp);
4746
4747         phy_start(tp->phydev);
4748         netif_start_queue(dev);
4749
4750         rtl_unlock_work(tp);
4751
4752         pm_runtime_put_sync(&pdev->dev);
4753 out:
4754         return retval;
4755
4756 err_free_irq:
4757         pci_free_irq(pdev, 0, tp);
4758 err_release_fw_2:
4759         rtl_release_firmware(tp);
4760         rtl8169_rx_clear(tp);
4761 err_free_rx_1:
4762         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4763                           tp->RxPhyAddr);
4764         tp->RxDescArray = NULL;
4765 err_free_tx_0:
4766         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4767                           tp->TxPhyAddr);
4768         tp->TxDescArray = NULL;
4769 err_pm_runtime_put:
4770         pm_runtime_put_noidle(&pdev->dev);
4771         goto out;
4772 }
4773
4774 static void
4775 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4776 {
4777         struct rtl8169_private *tp = netdev_priv(dev);
4778         struct pci_dev *pdev = tp->pci_dev;
4779         struct rtl8169_counters *counters = tp->counters;
4780         unsigned int start;
4781
4782         pm_runtime_get_noresume(&pdev->dev);
4783
4784         netdev_stats_to_stats64(stats, &dev->stats);
4785
4786         do {
4787                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
4788                 stats->rx_packets = tp->rx_stats.packets;
4789                 stats->rx_bytes = tp->rx_stats.bytes;
4790         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
4791
4792         do {
4793                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
4794                 stats->tx_packets = tp->tx_stats.packets;
4795                 stats->tx_bytes = tp->tx_stats.bytes;
4796         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
4797
4798         /*
4799          * Fetch additional counter values missing in stats collected by driver
4800          * from tally counters.
4801          */
4802         if (pm_runtime_active(&pdev->dev))
4803                 rtl8169_update_counters(tp);
4804
4805         /*
4806          * Subtract values fetched during initalization.
4807          * See rtl8169_init_counter_offsets for a description why we do that.
4808          */
4809         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4810                 le64_to_cpu(tp->tc_offset.tx_errors);
4811         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4812                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4813         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4814                 le16_to_cpu(tp->tc_offset.tx_aborted);
4815         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4816                 le16_to_cpu(tp->tc_offset.rx_missed);
4817
4818         pm_runtime_put_noidle(&pdev->dev);
4819 }
4820
4821 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4822 {
4823         netif_device_detach(tp->dev);
4824
4825         if (netif_running(tp->dev))
4826                 rtl8169_down(tp);
4827 }
4828
4829 #ifdef CONFIG_PM
4830
4831 static int __maybe_unused rtl8169_suspend(struct device *device)
4832 {
4833         struct rtl8169_private *tp = dev_get_drvdata(device);
4834
4835         rtl8169_net_suspend(tp);
4836
4837         return 0;
4838 }
4839
4840 static void __rtl8169_resume(struct rtl8169_private *tp)
4841 {
4842         rtl_pll_power_up(tp);
4843         rtl8169_init_phy(tp);
4844
4845         phy_start(tp->phydev);
4846
4847         rtl_lock_work(tp);
4848         napi_enable(&tp->napi);
4849         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4850         rtl_reset_work(tp);
4851         rtl_unlock_work(tp);
4852 }
4853
4854 static int __maybe_unused rtl8169_resume(struct device *device)
4855 {
4856         struct rtl8169_private *tp = dev_get_drvdata(device);
4857
4858         rtl_rar_set(tp, tp->dev->dev_addr);
4859
4860         if (netif_running(tp->dev))
4861                 __rtl8169_resume(tp);
4862
4863         netif_device_attach(tp->dev);
4864
4865         return 0;
4866 }
4867
4868 static int rtl8169_runtime_suspend(struct device *device)
4869 {
4870         struct rtl8169_private *tp = dev_get_drvdata(device);
4871
4872         if (!tp->TxDescArray) {
4873                 netif_device_detach(tp->dev);
4874                 return 0;
4875         }
4876
4877         rtl_lock_work(tp);
4878         __rtl8169_set_wol(tp, WAKE_PHY);
4879         rtl_unlock_work(tp);
4880
4881         rtl8169_net_suspend(tp);
4882
4883         return 0;
4884 }
4885
4886 static int rtl8169_runtime_resume(struct device *device)
4887 {
4888         struct rtl8169_private *tp = dev_get_drvdata(device);
4889
4890         rtl_rar_set(tp, tp->dev->dev_addr);
4891
4892         rtl_lock_work(tp);
4893         __rtl8169_set_wol(tp, tp->saved_wolopts);
4894         rtl_unlock_work(tp);
4895
4896         if (tp->TxDescArray)
4897                 __rtl8169_resume(tp);
4898
4899         netif_device_attach(tp->dev);
4900
4901         return 0;
4902 }
4903
4904 static int rtl8169_runtime_idle(struct device *device)
4905 {
4906         struct rtl8169_private *tp = dev_get_drvdata(device);
4907
4908         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4909                 pm_schedule_suspend(device, 10000);
4910
4911         return -EBUSY;
4912 }
4913
4914 static const struct dev_pm_ops rtl8169_pm_ops = {
4915         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4916         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4917                            rtl8169_runtime_idle)
4918 };
4919
4920 #endif /* CONFIG_PM */
4921
4922 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4923 {
4924         /* WoL fails with 8168b when the receiver is disabled. */
4925         switch (tp->mac_version) {
4926         case RTL_GIGA_MAC_VER_11:
4927         case RTL_GIGA_MAC_VER_12:
4928         case RTL_GIGA_MAC_VER_17:
4929                 pci_clear_master(tp->pci_dev);
4930
4931                 RTL_W8(tp, ChipCmd, CmdRxEnb);
4932                 rtl_pci_commit(tp);
4933                 break;
4934         default:
4935                 break;
4936         }
4937 }
4938
4939 static void rtl_shutdown(struct pci_dev *pdev)
4940 {
4941         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4942
4943         rtl8169_net_suspend(tp);
4944
4945         /* Restore original MAC address */
4946         rtl_rar_set(tp, tp->dev->perm_addr);
4947
4948         if (system_state == SYSTEM_POWER_OFF) {
4949                 if (tp->saved_wolopts) {
4950                         rtl_wol_suspend_quirk(tp);
4951                         rtl_wol_shutdown_quirk(tp);
4952                 }
4953
4954                 pci_wake_from_d3(pdev, true);
4955                 pci_set_power_state(pdev, PCI_D3hot);
4956         }
4957 }
4958
4959 static void rtl_remove_one(struct pci_dev *pdev)
4960 {
4961         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4962
4963         if (pci_dev_run_wake(pdev))
4964                 pm_runtime_get_noresume(&pdev->dev);
4965
4966         unregister_netdev(tp->dev);
4967
4968         if (r8168_check_dash(tp))
4969                 rtl8168_driver_stop(tp);
4970
4971         rtl_release_firmware(tp);
4972
4973         /* restore original MAC address */
4974         rtl_rar_set(tp, tp->dev->perm_addr);
4975 }
4976
4977 static const struct net_device_ops rtl_netdev_ops = {
4978         .ndo_open               = rtl_open,
4979         .ndo_stop               = rtl8169_close,
4980         .ndo_get_stats64        = rtl8169_get_stats64,
4981         .ndo_start_xmit         = rtl8169_start_xmit,
4982         .ndo_features_check     = rtl8169_features_check,
4983         .ndo_tx_timeout         = rtl8169_tx_timeout,
4984         .ndo_validate_addr      = eth_validate_addr,
4985         .ndo_change_mtu         = rtl8169_change_mtu,
4986         .ndo_fix_features       = rtl8169_fix_features,
4987         .ndo_set_features       = rtl8169_set_features,
4988         .ndo_set_mac_address    = rtl_set_mac_address,
4989         .ndo_do_ioctl           = phy_do_ioctl_running,
4990         .ndo_set_rx_mode        = rtl_set_rx_mode,
4991 #ifdef CONFIG_NET_POLL_CONTROLLER
4992         .ndo_poll_controller    = rtl8169_netpoll,
4993 #endif
4994
4995 };
4996
4997 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4998 {
4999         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5000
5001         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5002                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5003         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5004                 /* special workaround needed */
5005                 tp->irq_mask |= RxFIFOOver;
5006         else
5007                 tp->irq_mask |= RxOverflow;
5008 }
5009
5010 static int rtl_alloc_irq(struct rtl8169_private *tp)
5011 {
5012         unsigned int flags;
5013
5014         switch (tp->mac_version) {
5015         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5016                 rtl_unlock_config_regs(tp);
5017                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5018                 rtl_lock_config_regs(tp);
5019                 /* fall through */
5020         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5021                 flags = PCI_IRQ_LEGACY;
5022                 break;
5023         default:
5024                 flags = PCI_IRQ_ALL_TYPES;
5025                 break;
5026         }
5027
5028         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5029 }
5030
5031 static void rtl_read_mac_address(struct rtl8169_private *tp,
5032                                  u8 mac_addr[ETH_ALEN])
5033 {
5034         /* Get MAC address */
5035         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5036                 u32 value = rtl_eri_read(tp, 0xe0);
5037
5038                 mac_addr[0] = (value >>  0) & 0xff;
5039                 mac_addr[1] = (value >>  8) & 0xff;
5040                 mac_addr[2] = (value >> 16) & 0xff;
5041                 mac_addr[3] = (value >> 24) & 0xff;
5042
5043                 value = rtl_eri_read(tp, 0xe4);
5044                 mac_addr[4] = (value >>  0) & 0xff;
5045                 mac_addr[5] = (value >>  8) & 0xff;
5046         } else if (rtl_is_8125(tp)) {
5047                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5048         }
5049 }
5050
5051 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5052 {
5053         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5054 }
5055
5056 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5057 {
5058         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5059 }
5060
5061 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5062 {
5063         struct rtl8169_private *tp = mii_bus->priv;
5064
5065         if (phyaddr > 0)
5066                 return -ENODEV;
5067
5068         return rtl_readphy(tp, phyreg);
5069 }
5070
5071 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5072                                 int phyreg, u16 val)
5073 {
5074         struct rtl8169_private *tp = mii_bus->priv;
5075
5076         if (phyaddr > 0)
5077                 return -ENODEV;
5078
5079         rtl_writephy(tp, phyreg, val);
5080
5081         return 0;
5082 }
5083
5084 static int r8169_mdio_register(struct rtl8169_private *tp)
5085 {
5086         struct pci_dev *pdev = tp->pci_dev;
5087         struct mii_bus *new_bus;
5088         int ret;
5089
5090         new_bus = devm_mdiobus_alloc(&pdev->dev);
5091         if (!new_bus)
5092                 return -ENOMEM;
5093
5094         new_bus->name = "r8169";
5095         new_bus->priv = tp;
5096         new_bus->parent = &pdev->dev;
5097         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5098         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5099
5100         new_bus->read = r8169_mdio_read_reg;
5101         new_bus->write = r8169_mdio_write_reg;
5102
5103         ret = devm_mdiobus_register(new_bus);
5104         if (ret)
5105                 return ret;
5106
5107         tp->phydev = mdiobus_get_phy(new_bus, 0);
5108         if (!tp->phydev) {
5109                 return -ENODEV;
5110         } else if (!tp->phydev->drv) {
5111                 /* Most chip versions fail with the genphy driver.
5112                  * Therefore ensure that the dedicated PHY driver is loaded.
5113                  */
5114                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5115                         tp->phydev->phy_id);
5116                 return -EUNATCH;
5117         }
5118
5119         /* PHY will be woken up in rtl_open() */
5120         phy_suspend(tp->phydev);
5121
5122         return 0;
5123 }
5124
5125 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5126 {
5127         rtl_enable_rxdvgate(tp);
5128
5129         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5130         msleep(1);
5131         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5132
5133         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5134         r8168g_wait_ll_share_fifo_ready(tp);
5135
5136         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5137         r8168g_wait_ll_share_fifo_ready(tp);
5138 }
5139
5140 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5141 {
5142         rtl_enable_rxdvgate(tp);
5143
5144         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5145         msleep(1);
5146         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5147
5148         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5149         r8168g_wait_ll_share_fifo_ready(tp);
5150
5151         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5152         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5153         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5154         r8168g_wait_ll_share_fifo_ready(tp);
5155 }
5156
5157 static void rtl_hw_initialize(struct rtl8169_private *tp)
5158 {
5159         switch (tp->mac_version) {
5160         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5161                 rtl8168ep_stop_cmac(tp);
5162                 /* fall through */
5163         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5164                 rtl_hw_init_8168g(tp);
5165                 break;
5166         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
5167                 rtl_hw_init_8125(tp);
5168                 break;
5169         default:
5170                 break;
5171         }
5172 }
5173
5174 static int rtl_jumbo_max(struct rtl8169_private *tp)
5175 {
5176         /* Non-GBit versions don't support jumbo frames */
5177         if (!tp->supports_gmii)
5178                 return 0;
5179
5180         switch (tp->mac_version) {
5181         /* RTL8169 */
5182         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5183                 return JUMBO_7K;
5184         /* RTL8168b */
5185         case RTL_GIGA_MAC_VER_11:
5186         case RTL_GIGA_MAC_VER_12:
5187         case RTL_GIGA_MAC_VER_17:
5188                 return JUMBO_4K;
5189         /* RTL8168c */
5190         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5191                 return JUMBO_6K;
5192         default:
5193                 return JUMBO_9K;
5194         }
5195 }
5196
5197 static void rtl_disable_clk(void *data)
5198 {
5199         clk_disable_unprepare(data);
5200 }
5201
5202 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5203 {
5204         struct device *d = tp_to_dev(tp);
5205         struct clk *clk;
5206         int rc;
5207
5208         clk = devm_clk_get(d, "ether_clk");
5209         if (IS_ERR(clk)) {
5210                 rc = PTR_ERR(clk);
5211                 if (rc == -ENOENT)
5212                         /* clk-core allows NULL (for suspend / resume) */
5213                         rc = 0;
5214                 else if (rc != -EPROBE_DEFER)
5215                         dev_err(d, "failed to get clk: %d\n", rc);
5216         } else {
5217                 tp->clk = clk;
5218                 rc = clk_prepare_enable(clk);
5219                 if (rc)
5220                         dev_err(d, "failed to enable clk: %d\n", rc);
5221                 else
5222                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5223         }
5224
5225         return rc;
5226 }
5227
5228 static void rtl_init_mac_address(struct rtl8169_private *tp)
5229 {
5230         struct net_device *dev = tp->dev;
5231         u8 *mac_addr = dev->dev_addr;
5232         int rc;
5233
5234         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5235         if (!rc)
5236                 goto done;
5237
5238         rtl_read_mac_address(tp, mac_addr);
5239         if (is_valid_ether_addr(mac_addr))
5240                 goto done;
5241
5242         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5243         if (is_valid_ether_addr(mac_addr))
5244                 goto done;
5245
5246         eth_hw_addr_random(dev);
5247         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5248 done:
5249         rtl_rar_set(tp, mac_addr);
5250 }
5251
5252 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5253 {
5254         struct rtl8169_private *tp;
5255         int jumbo_max, region, rc;
5256         enum mac_version chipset;
5257         struct net_device *dev;
5258         u16 xid;
5259
5260         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5261         if (!dev)
5262                 return -ENOMEM;
5263
5264         SET_NETDEV_DEV(dev, &pdev->dev);
5265         dev->netdev_ops = &rtl_netdev_ops;
5266         tp = netdev_priv(dev);
5267         tp->dev = dev;
5268         tp->pci_dev = pdev;
5269         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5270         tp->eee_adv = -1;
5271         tp->ocp_base = OCP_STD_PHY_BASE;
5272
5273         /* Get the *optional* external "ether_clk" used on some boards */
5274         rc = rtl_get_ether_clk(tp);
5275         if (rc)
5276                 return rc;
5277
5278         /* Disable ASPM completely as that cause random device stop working
5279          * problems as well as full system hangs for some PCIe devices users.
5280          */
5281         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5282                                           PCIE_LINK_STATE_L1);
5283         tp->aspm_manageable = !rc;
5284
5285         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5286         rc = pcim_enable_device(pdev);
5287         if (rc < 0) {
5288                 dev_err(&pdev->dev, "enable failure\n");
5289                 return rc;
5290         }
5291
5292         if (pcim_set_mwi(pdev) < 0)
5293                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5294
5295         /* use first MMIO region */
5296         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5297         if (region < 0) {
5298                 dev_err(&pdev->dev, "no MMIO resource found\n");
5299                 return -ENODEV;
5300         }
5301
5302         /* check for weird/broken PCI region reporting */
5303         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5304                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5305                 return -ENODEV;
5306         }
5307
5308         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5309         if (rc < 0) {
5310                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5311                 return rc;
5312         }
5313
5314         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5315
5316         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5317
5318         /* Identify chip attached to board */
5319         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5320         if (chipset == RTL_GIGA_MAC_NONE) {
5321                 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5322                 return -ENODEV;
5323         }
5324
5325         tp->mac_version = chipset;
5326
5327         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5328
5329         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5330             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5331                 dev->features |= NETIF_F_HIGHDMA;
5332
5333         rtl_init_rxcfg(tp);
5334
5335         rtl8169_irq_mask_and_ack(tp);
5336
5337         rtl_hw_initialize(tp);
5338
5339         rtl_hw_reset(tp);
5340
5341         pci_set_master(pdev);
5342
5343         rc = rtl_alloc_irq(tp);
5344         if (rc < 0) {
5345                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5346                 return rc;
5347         }
5348
5349         mutex_init(&tp->wk.mutex);
5350         INIT_WORK(&tp->wk.work, rtl_task);
5351         u64_stats_init(&tp->rx_stats.syncp);
5352         u64_stats_init(&tp->tx_stats.syncp);
5353
5354         rtl_init_mac_address(tp);
5355
5356         dev->ethtool_ops = &rtl8169_ethtool_ops;
5357
5358         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5359
5360         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5361                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5362         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5363         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5364
5365         /*
5366          * Pretend we are using VLANs; This bypasses a nasty bug where
5367          * Interrupts stop flowing on high load on 8110SCd controllers.
5368          */
5369         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5370                 /* Disallow toggling */
5371                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5372
5373         if (rtl_chip_supports_csum_v2(tp))
5374                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5375
5376         dev->features |= dev->hw_features;
5377
5378         /* There has been a number of reports that using SG/TSO results in
5379          * tx timeouts. However for a lot of people SG/TSO works fine.
5380          * Therefore disable both features by default, but allow users to
5381          * enable them. Use at own risk!
5382          */
5383         if (rtl_chip_supports_csum_v2(tp)) {
5384                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5385                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5386                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5387         } else {
5388                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5389                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5390                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5391         }
5392
5393         dev->hw_features |= NETIF_F_RXALL;
5394         dev->hw_features |= NETIF_F_RXFCS;
5395
5396         /* configure chip for default features */
5397         rtl8169_set_features(dev, dev->features);
5398
5399         jumbo_max = rtl_jumbo_max(tp);
5400         if (jumbo_max)
5401                 dev->max_mtu = jumbo_max;
5402
5403         rtl_set_irq_mask(tp);
5404
5405         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5406
5407         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5408                                             &tp->counters_phys_addr,
5409                                             GFP_KERNEL);
5410         if (!tp->counters)
5411                 return -ENOMEM;
5412
5413         pci_set_drvdata(pdev, tp);
5414
5415         rc = r8169_mdio_register(tp);
5416         if (rc)
5417                 return rc;
5418
5419         /* chip gets powered up in rtl_open() */
5420         rtl_pll_power_down(tp);
5421
5422         rc = register_netdev(dev);
5423         if (rc)
5424                 return rc;
5425
5426         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5427                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5428                     pci_irq_vector(pdev, 0));
5429
5430         if (jumbo_max)
5431                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5432                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5433                             "ok" : "ko");
5434
5435         if (r8168_check_dash(tp)) {
5436                 netdev_info(dev, "DASH enabled\n");
5437                 rtl8168_driver_start(tp);
5438         }
5439
5440         if (pci_dev_run_wake(pdev))
5441                 pm_runtime_put_sync(&pdev->dev);
5442
5443         return 0;
5444 }
5445
5446 static struct pci_driver rtl8169_pci_driver = {
5447         .name           = MODULENAME,
5448         .id_table       = rtl8169_pci_tbl,
5449         .probe          = rtl_init_one,
5450         .remove         = rtl_remove_one,
5451         .shutdown       = rtl_shutdown,
5452 #ifdef CONFIG_PM
5453         .driver.pm      = &rtl8169_pm_ops,
5454 #endif
5455 };
5456
5457 module_pci_driver(rtl8169_pci_driver);