drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #include "r8169.h"
  35 #include "r8169_firmware.h"
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  40 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  41 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  42 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  43 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  46 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  47 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  48 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  49 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  50 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  51 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  52 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  58 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 #define MC_FILTER_LIMIT 32
  63
  64 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  65 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  66
  67 #define R8169_REGS_SIZE         256
  68 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  69 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  70 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  71 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  72 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  73
  74 #define OCP_STD_PHY_BASE        0xa400
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  87 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90
  91 static const struct {
  92         const char *name;
  93         const char *fw_name;
  94 } rtl_chip_infos[] = {
  95         /* PCI devices. */
  96         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  97         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  98         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
  99         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 100         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 101         /* PCI-E devices. */
 102         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 103         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 105         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 106         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 107         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 109         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 110         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 111         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 112         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 113         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 114         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 118         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 119         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 120         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 121         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 122         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 123         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 124         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 125         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 126         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 127         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 128         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 129         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 130         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 131         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 132         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 133         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 134         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 135         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 136         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 137         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 138         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 139         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 140         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 141         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 142         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 143         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 144         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 145         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 146         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 147         [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 148         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 149         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 150         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 151 };
 152
 153 static const struct pci_device_id rtl8169_pci_tbl[] = {
 154         { PCI_VDEVICE(REALTEK,  0x2502) },
 155         { PCI_VDEVICE(REALTEK,  0x2600) },
 156         { PCI_VDEVICE(REALTEK,  0x8129) },
 157         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 158         { PCI_VDEVICE(REALTEK,  0x8161) },
 159         { PCI_VDEVICE(REALTEK,  0x8162) },
 160         { PCI_VDEVICE(REALTEK,  0x8167) },
 161         { PCI_VDEVICE(REALTEK,  0x8168) },
 162         { PCI_VDEVICE(NCUBE,    0x8168) },
 163         { PCI_VDEVICE(REALTEK,  0x8169) },
 164         { PCI_VENDOR_ID_DLINK,  0x4300,
 165                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 166         { PCI_VDEVICE(DLINK,    0x4300) },
 167         { PCI_VDEVICE(DLINK,    0x4302) },
 168         { PCI_VDEVICE(AT,       0xc107) },
 169         { PCI_VDEVICE(USR,      0x0116) },
 170         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 171         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 172         { PCI_VDEVICE(REALTEK,  0x8125) },
 173         { PCI_VDEVICE(REALTEK,  0x3000) },
 174         {}
 175 };
 176
 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 178
 179 enum rtl_registers {
 180         MAC0            = 0,    /* Ethernet hardware address. */
 181         MAC4            = 4,
 182         MAR0            = 8,    /* Multicast filter. */
 183         CounterAddrLow          = 0x10,
 184         CounterAddrHigh         = 0x14,
 185         TxDescStartAddrLow      = 0x20,
 186         TxDescStartAddrHigh     = 0x24,
 187         TxHDescStartAddrLow     = 0x28,
 188         TxHDescStartAddrHigh    = 0x2c,
 189         FLASH           = 0x30,
 190         ERSR            = 0x36,
 191         ChipCmd         = 0x37,
 192         TxPoll          = 0x38,
 193         IntrMask        = 0x3c,
 194         IntrStatus      = 0x3e,
 195
 196         TxConfig        = 0x40,
 197 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 198 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 199
 200         RxConfig        = 0x44,
 201 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 202 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 203 #define RXCFG_FIFO_SHIFT                13
 204                                         /* No threshold before first PCI xfer */
 205 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 206 #define RX_EARLY_OFF                    (1 << 11)
 207 #define RXCFG_DMA_SHIFT                 8
 208                                         /* Unlimited maximum PCI burst. */
 209 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 210
 211         Cfg9346         = 0x50,
 212         Config0         = 0x51,
 213         Config1         = 0x52,
 214         Config2         = 0x53,
 215 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 216
 217         Config3         = 0x54,
 218         Config4         = 0x55,
 219         Config5         = 0x56,
 220         PHYAR           = 0x60,
 221         PHYstatus       = 0x6c,
 222         RxMaxSize       = 0xda,
 223         CPlusCmd        = 0xe0,
 224         IntrMitigate    = 0xe2,
 225
 226 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 227 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 228 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 229 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 230
 231 #define RTL_COALESCE_T_MAX      0x0fU
 232 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 233
 234         RxDescAddrLow   = 0xe4,
 235         RxDescAddrHigh  = 0xe8,
 236         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 237
 238 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 239
 240         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 241
 242 #define TxPacketMax     (8064 >> 7)
 243 #define EarlySize       0x27
 244
 245         FuncEvent       = 0xf0,
 246         FuncEventMask   = 0xf4,
 247         FuncPresetState = 0xf8,
 248         IBCR0           = 0xf8,
 249         IBCR2           = 0xf9,
 250         IBIMR0          = 0xfa,
 251         IBISR0          = 0xfb,
 252         FuncForceEvent  = 0xfc,
 253 };
 254
 255 enum rtl8168_8101_registers {
 256         CSIDR                   = 0x64,
 257         CSIAR                   = 0x68,
 258 #define CSIAR_FLAG                      0x80000000
 259 #define CSIAR_WRITE_CMD                 0x80000000
 260 #define CSIAR_BYTE_ENABLE               0x0000f000
 261 #define CSIAR_ADDR_MASK                 0x00000fff
 262         PMCH                    = 0x6f,
 263 #define D3COLD_NO_PLL_DOWN              BIT(7)
 264 #define D3HOT_NO_PLL_DOWN               BIT(6)
 265 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 266         EPHYAR                  = 0x80,
 267 #define EPHYAR_FLAG                     0x80000000
 268 #define EPHYAR_WRITE_CMD                0x80000000
 269 #define EPHYAR_REG_MASK                 0x1f
 270 #define EPHYAR_REG_SHIFT                16
 271 #define EPHYAR_DATA_MASK                0xffff
 272         DLLPR                   = 0xd0,
 273 #define PFM_EN                          (1 << 6)
 274 #define TX_10M_PS_EN                    (1 << 7)
 275         DBG_REG                 = 0xd1,
 276 #define FIX_NAK_1                       (1 << 4)
 277 #define FIX_NAK_2                       (1 << 3)
 278         TWSI                    = 0xd2,
 279         MCU                     = 0xd3,
 280 #define NOW_IS_OOB                      (1 << 7)
 281 #define TX_EMPTY                        (1 << 5)
 282 #define RX_EMPTY                        (1 << 4)
 283 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 284 #define EN_NDP                          (1 << 3)
 285 #define EN_OOB_RESET                    (1 << 2)
 286 #define LINK_LIST_RDY                   (1 << 1)
 287         EFUSEAR                 = 0xdc,
 288 #define EFUSEAR_FLAG                    0x80000000
 289 #define EFUSEAR_WRITE_CMD               0x80000000
 290 #define EFUSEAR_READ_CMD                0x00000000
 291 #define EFUSEAR_REG_MASK                0x03ff
 292 #define EFUSEAR_REG_SHIFT               8
 293 #define EFUSEAR_DATA_MASK               0xff
 294         MISC_1                  = 0xf2,
 295 #define PFM_D3COLD_EN                   (1 << 6)
 296 };
 297
 298 enum rtl8168_registers {
 299         LED_FREQ                = 0x1a,
 300         EEE_LED                 = 0x1b,
 301         ERIDR                   = 0x70,
 302         ERIAR                   = 0x74,
 303 #define ERIAR_FLAG                      0x80000000
 304 #define ERIAR_WRITE_CMD                 0x80000000
 305 #define ERIAR_READ_CMD                  0x00000000
 306 #define ERIAR_ADDR_BYTE_ALIGN           4
 307 #define ERIAR_TYPE_SHIFT                16
 308 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 309 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 310 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 311 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 312 #define ERIAR_MASK_SHIFT                12
 313 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 314 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 315 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 316 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 317 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 318         EPHY_RXER_NUM           = 0x7c,
 319         OCPDR                   = 0xb0, /* OCP GPHY access */
 320 #define OCPDR_WRITE_CMD                 0x80000000
 321 #define OCPDR_READ_CMD                  0x00000000
 322 #define OCPDR_REG_MASK                  0x7f
 323 #define OCPDR_GPHY_REG_SHIFT            16
 324 #define OCPDR_DATA_MASK                 0xffff
 325         OCPAR                   = 0xb4,
 326 #define OCPAR_FLAG                      0x80000000
 327 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 328 #define OCPAR_GPHY_READ_CMD             0x0000f060
 329         GPHY_OCP                = 0xb8,
 330         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 331         MISC                    = 0xf0, /* 8168e only. */
 332 #define TXPLA_RST                       (1 << 29)
 333 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 334 #define PWM_EN                          (1 << 22)
 335 #define RXDV_GATED_EN                   (1 << 19)
 336 #define EARLY_TALLY_EN                  (1 << 16)
 337 };
 338
 339 enum rtl8125_registers {
 340         IntrMask_8125           = 0x38,
 341         IntrStatus_8125         = 0x3c,
 342         TxPoll_8125             = 0x90,
 343         MAC0_BKP                = 0x19e0,
 344         EEE_TXIDLE_TIMER_8125   = 0x6048,
 345 };
 346
 347 #define RX_VLAN_INNER_8125      BIT(22)
 348 #define RX_VLAN_OUTER_8125      BIT(23)
 349 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 350
 351 #define RX_FETCH_DFLT_8125      (8 << 27)
 352
 353 enum rtl_register_content {
 354         /* InterruptStatusBits */
 355         SYSErr          = 0x8000,
 356         PCSTimeout      = 0x4000,
 357         SWInt           = 0x0100,
 358         TxDescUnavail   = 0x0080,
 359         RxFIFOOver      = 0x0040,
 360         LinkChg         = 0x0020,
 361         RxOverflow      = 0x0010,
 362         TxErr           = 0x0008,
 363         TxOK            = 0x0004,
 364         RxErr           = 0x0002,
 365         RxOK            = 0x0001,
 366
 367         /* RxStatusDesc */
 368         RxRWT   = (1 << 22),
 369         RxRES   = (1 << 21),
 370         RxRUNT  = (1 << 20),
 371         RxCRC   = (1 << 19),
 372
 373         /* ChipCmdBits */
 374         StopReq         = 0x80,
 375         CmdReset        = 0x10,
 376         CmdRxEnb        = 0x08,
 377         CmdTxEnb        = 0x04,
 378         RxBufEmpty      = 0x01,
 379
 380         /* TXPoll register p.5 */
 381         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 382         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 383         FSWInt          = 0x01,         /* Forced software interrupt */
 384
 385         /* Cfg9346Bits */
 386         Cfg9346_Lock    = 0x00,
 387         Cfg9346_Unlock  = 0xc0,
 388
 389         /* rx_mode_bits */
 390         AcceptErr       = 0x20,
 391         AcceptRunt      = 0x10,
 392 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 393         AcceptBroadcast = 0x08,
 394         AcceptMulticast = 0x04,
 395         AcceptMyPhys    = 0x02,
 396         AcceptAllPhys   = 0x01,
 397 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 398 #define RX_CONFIG_ACCEPT_MASK           0x3f
 399
 400         /* TxConfigBits */
 401         TxInterFrameGapShift = 24,
 402         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 403
 404         /* Config1 register p.24 */
 405         LEDS1           = (1 << 7),
 406         LEDS0           = (1 << 6),
 407         Speed_down      = (1 << 4),
 408         MEMMAP          = (1 << 3),
 409         IOMAP           = (1 << 2),
 410         VPD             = (1 << 1),
 411         PMEnable        = (1 << 0),     /* Power Management Enable */
 412
 413         /* Config2 register p. 25 */
 414         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 415         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 416         PCI_Clock_66MHz = 0x01,
 417         PCI_Clock_33MHz = 0x00,
 418
 419         /* Config3 register p.25 */
 420         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 421         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 422         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 423         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 424         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 425
 426         /* Config4 register */
 427         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 428
 429         /* Config5 register p.27 */
 430         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 431         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 432         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 433         Spi_en          = (1 << 3),
 434         LanWake         = (1 << 1),     /* LanWake enable/disable */
 435         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 436         ASPM_en         = (1 << 0),     /* ASPM enable */
 437
 438         /* CPlusCmd p.31 */
 439         EnableBist      = (1 << 15),    // 8168 8101
 440         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 441         EnAnaPLL        = (1 << 14),    // 8169
 442         Normal_mode     = (1 << 13),    // unused
 443         Force_half_dup  = (1 << 12),    // 8168 8101
 444         Force_rxflow_en = (1 << 11),    // 8168 8101
 445         Force_txflow_en = (1 << 10),    // 8168 8101
 446         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 447         ASF             = (1 << 8),     // 8168 8101
 448         PktCntrDisable  = (1 << 7),     // 8168 8101
 449         Mac_dbgo_sel    = 0x001c,       // 8168
 450         RxVlan          = (1 << 6),
 451         RxChkSum        = (1 << 5),
 452         PCIDAC          = (1 << 4),
 453         PCIMulRW        = (1 << 3),
 454 #define INTT_MASK       GENMASK(1, 0)
 455 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 456
 457         /* rtl8169_PHYstatus */
 458         TBI_Enable      = 0x80,
 459         TxFlowCtrl      = 0x40,
 460         RxFlowCtrl      = 0x20,
 461         _1000bpsF       = 0x10,
 462         _100bps         = 0x08,
 463         _10bps          = 0x04,
 464         LinkStatus      = 0x02,
 465         FullDup         = 0x01,
 466
 467         /* ResetCounterCommand */
 468         CounterReset    = 0x1,
 469
 470         /* DumpCounterCommand */
 471         CounterDump     = 0x8,
 472
 473         /* magic enable v2 */
 474         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 475 };
 476
 477 enum rtl_desc_bit {
 478         /* First doubleword. */
 479         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 480         RingEnd         = (1 << 30), /* End of descriptor ring */
 481         FirstFrag       = (1 << 29), /* First segment of a packet */
 482         LastFrag        = (1 << 28), /* Final segment of a packet */
 483 };
 484
 485 /* Generic case. */
 486 enum rtl_tx_desc_bit {
 487         /* First doubleword. */
 488         TD_LSO          = (1 << 27),            /* Large Send Offload */
 489 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 490
 491         /* Second doubleword. */
 492         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 493 };
 494
 495 /* 8169, 8168b and 810x except 8102e. */
 496 enum rtl_tx_desc_bit_0 {
 497         /* First doubleword. */
 498 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 499         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 500         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 501         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 502 };
 503
 504 /* 8102e, 8168c and beyond. */
 505 enum rtl_tx_desc_bit_1 {
 506         /* First doubleword. */
 507         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 508         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 509 #define GTTCPHO_SHIFT                   18
 510 #define GTTCPHO_MAX                     0x7f
 511
 512         /* Second doubleword. */
 513 #define TCPHO_SHIFT                     18
 514 #define TCPHO_MAX                       0x3ff
 515 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 516         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 517         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 518         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 519         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 520 };
 521
 522 enum rtl_rx_desc_bit {
 523         /* Rx private */
 524         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 525         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 526
 527 #define RxProtoUDP      (PID1)
 528 #define RxProtoTCP      (PID0)
 529 #define RxProtoIP       (PID1 | PID0)
 530 #define RxProtoMask     RxProtoIP
 531
 532         IPFail          = (1 << 16), /* IP checksum failed */
 533         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 534         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 535
 536 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 537
 538         RxVlanTag       = (1 << 16), /* VLAN tag available */
 539 };
 540
 541 #define RTL_GSO_MAX_SIZE_V1     32000
 542 #define RTL_GSO_MAX_SEGS_V1     24
 543 #define RTL_GSO_MAX_SIZE_V2     64000
 544 #define RTL_GSO_MAX_SEGS_V2     64
 545
 546 struct TxDesc {
 547         __le32 opts1;
 548         __le32 opts2;
 549         __le64 addr;
 550 };
 551
 552 struct RxDesc {
 553         __le32 opts1;
 554         __le32 opts2;
 555         __le64 addr;
 556 };
 557
 558 struct ring_info {
 559         struct sk_buff  *skb;
 560         u32             len;
 561 };
 562
 563 struct rtl8169_counters {
 564         __le64  tx_packets;
 565         __le64  rx_packets;
 566         __le64  tx_errors;
 567         __le32  rx_errors;
 568         __le16  rx_missed;
 569         __le16  align_errors;
 570         __le32  tx_one_collision;
 571         __le32  tx_multi_collision;
 572         __le64  rx_unicast;
 573         __le64  rx_broadcast;
 574         __le32  rx_multicast;
 575         __le16  tx_aborted;
 576         __le16  tx_underun;
 577 };
 578
 579 struct rtl8169_tc_offsets {
 580         bool    inited;
 581         __le64  tx_errors;
 582         __le32  tx_multi_collision;
 583         __le16  tx_aborted;
 584         __le16  rx_missed;
 585 };
 586
 587 enum rtl_flag {
 588         RTL_FLAG_TASK_ENABLED = 0,
 589         RTL_FLAG_TASK_RESET_PENDING,
 590         RTL_FLAG_MAX
 591 };
 592
 593 enum rtl_dash_type {
 594         RTL_DASH_NONE,
 595         RTL_DASH_DP,
 596         RTL_DASH_EP,
 597 };
 598
 599 struct rtl8169_private {
 600         void __iomem *mmio_addr;        /* memory map physical address */
 601         struct pci_dev *pci_dev;
 602         struct net_device *dev;
 603         struct phy_device *phydev;
 604         struct napi_struct napi;
 605         enum mac_version mac_version;
 606         enum rtl_dash_type dash_type;
 607         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 608         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 609         u32 dirty_tx;
 610         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 611         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 612         dma_addr_t TxPhyAddr;
 613         dma_addr_t RxPhyAddr;
 614         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 615         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 616         u16 cp_cmd;
 617         u32 irq_mask;
 618         struct clk *clk;
 619
 620         struct {
 621                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 622                 struct work_struct work;
 623         } wk;
 624
 625         unsigned supports_gmii:1;
 626         unsigned aspm_manageable:1;
 627         dma_addr_t counters_phys_addr;
 628         struct rtl8169_counters *counters;
 629         struct rtl8169_tc_offsets tc_offset;
 630         u32 saved_wolopts;
 631         int eee_adv;
 632
 633         const char *fw_name;
 634         struct rtl_fw *rtl_fw;
 635
 636         u32 ocp_base;
 637 };
 638
 639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 640
 641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 643 MODULE_SOFTDEP("pre: realtek");
 644 MODULE_LICENSE("GPL");
 645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 653 MODULE_FIRMWARE(FIRMWARE_8402_1);
 654 MODULE_FIRMWARE(FIRMWARE_8411_1);
 655 MODULE_FIRMWARE(FIRMWARE_8411_2);
 656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 660 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 663 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 664 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 665 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 666 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 667
 668 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 669 {
 670         return &tp->pci_dev->dev;
 671 }
 672
 673 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 674 {
 675         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 676 }
 677
 678 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 679 {
 680         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 681 }
 682
 683 static void rtl_pci_commit(struct rtl8169_private *tp)
 684 {
 685         /* Read an arbitrary register to commit a preceding PCI write */
 686         RTL_R8(tp, ChipCmd);
 687 }
 688
 689 static bool rtl_is_8125(struct rtl8169_private *tp)
 690 {
 691         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 692 }
 693
 694 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 695 {
 696         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 697                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 698                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 699 }
 700
 701 static bool rtl_supports_eee(struct rtl8169_private *tp)
 702 {
 703         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 704                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 705                tp->mac_version != RTL_GIGA_MAC_VER_39;
 706 }
 707
 708 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 709 {
 710         int i;
 711
 712         for (i = 0; i < ETH_ALEN; i++)
 713                 mac[i] = RTL_R8(tp, reg + i);
 714 }
 715
 716 struct rtl_cond {
 717         bool (*check)(struct rtl8169_private *);
 718         const char *msg;
 719 };
 720
 721 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 722                           unsigned long usecs, int n, bool high)
 723 {
 724         int i;
 725
 726         for (i = 0; i < n; i++) {
 727                 if (c->check(tp) == high)
 728                         return true;
 729                 fsleep(usecs);
 730         }
 731
 732         if (net_ratelimit())
 733                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 734                            c->msg, !high, n, usecs);
 735         return false;
 736 }
 737
 738 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 739                                const struct rtl_cond *c,
 740                                unsigned long d, int n)
 741 {
 742         return rtl_loop_wait(tp, c, d, n, true);
 743 }
 744
 745 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 746                               const struct rtl_cond *c,
 747                               unsigned long d, int n)
 748 {
 749         return rtl_loop_wait(tp, c, d, n, false);
 750 }
 751
 752 #define DECLARE_RTL_COND(name)                          \
 753 static bool name ## _check(struct rtl8169_private *);   \
 754                                                         \
 755 static const struct rtl_cond name = {                   \
 756         .check  = name ## _check,                       \
 757         .msg    = #name                                 \
 758 };                                                      \
 759                                                         \
 760 static bool name ## _check(struct rtl8169_private *tp)
 761
 762 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 763 {
 764         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 765         if (type == ERIAR_OOB &&
 766             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 767              tp->mac_version == RTL_GIGA_MAC_VER_53))
 768                 *cmd |= 0xf70 << 18;
 769 }
 770
 771 DECLARE_RTL_COND(rtl_eriar_cond)
 772 {
 773         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 774 }
 775
 776 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 777                            u32 val, int type)
 778 {
 779         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 780
 781         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 782                 return;
 783
 784         RTL_W32(tp, ERIDR, val);
 785         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 786         RTL_W32(tp, ERIAR, cmd);
 787
 788         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 789 }
 790
 791 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 792                           u32 val)
 793 {
 794         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 795 }
 796
 797 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 798 {
 799         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 800
 801         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 802         RTL_W32(tp, ERIAR, cmd);
 803
 804         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 805                 RTL_R32(tp, ERIDR) : ~0;
 806 }
 807
 808 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 809 {
 810         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 811 }
 812
 813 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 814 {
 815         u32 val = rtl_eri_read(tp, addr);
 816
 817         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 818 }
 819
 820 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 821 {
 822         rtl_w0w1_eri(tp, addr, p, 0);
 823 }
 824
 825 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 826 {
 827         rtl_w0w1_eri(tp, addr, 0, m);
 828 }
 829
 830 static bool rtl_ocp_reg_failure(u32 reg)
 831 {
 832         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 833 }
 834
 835 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 836 {
 837         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 838 }
 839
 840 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 841 {
 842         if (rtl_ocp_reg_failure(reg))
 843                 return;
 844
 845         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 846
 847         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 848 }
 849
 850 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 851 {
 852         if (rtl_ocp_reg_failure(reg))
 853                 return 0;
 854
 855         RTL_W32(tp, GPHY_OCP, reg << 15);
 856
 857         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 858                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 859 }
 860
 861 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 862 {
 863         if (rtl_ocp_reg_failure(reg))
 864                 return;
 865
 866         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 867 }
 868
 869 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 870 {
 871         if (rtl_ocp_reg_failure(reg))
 872                 return 0;
 873
 874         RTL_W32(tp, OCPDR, reg << 15);
 875
 876         return RTL_R32(tp, OCPDR);
 877 }
 878
 879 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 880                                  u16 set)
 881 {
 882         u16 data = r8168_mac_ocp_read(tp, reg);
 883
 884         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 885 }
 886
 887 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 888  * PHY MCU interrupts before PHY power-down.
 889  */
 890 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 891 {
 892         switch (tp->mac_version) {
 893         case RTL_GIGA_MAC_VER_40:
 894         case RTL_GIGA_MAC_VER_41:
 895         case RTL_GIGA_MAC_VER_49:
 896                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 897                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 898                 else
 899                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 900                 break;
 901         default:
 902                 break;
 903         }
 904 };
 905
 906 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 907 {
 908         if (reg == 0x1f) {
 909                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 910                 return;
 911         }
 912
 913         if (tp->ocp_base != OCP_STD_PHY_BASE)
 914                 reg -= 0x10;
 915
 916         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 917                 rtl8168g_phy_suspend_quirk(tp, value);
 918
 919         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 920 }
 921
 922 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 923 {
 924         if (reg == 0x1f)
 925                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 926
 927         if (tp->ocp_base != OCP_STD_PHY_BASE)
 928                 reg -= 0x10;
 929
 930         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 931 }
 932
 933 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 934 {
 935         if (reg == 0x1f) {
 936                 tp->ocp_base = value << 4;
 937                 return;
 938         }
 939
 940         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 941 }
 942
 943 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 944 {
 945         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 946 }
 947
 948 DECLARE_RTL_COND(rtl_phyar_cond)
 949 {
 950         return RTL_R32(tp, PHYAR) & 0x80000000;
 951 }
 952
 953 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 954 {
 955         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 956
 957         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 958         /*
 959          * According to hardware specs a 20us delay is required after write
 960          * complete indication, but before sending next command.
 961          */
 962         udelay(20);
 963 }
 964
 965 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 966 {
 967         int value;
 968
 969         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 970
 971         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 972                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 973
 974         /*
 975          * According to hardware specs a 20us delay is required after read
 976          * complete indication, but before sending next command.
 977          */
 978         udelay(20);
 979
 980         return value;
 981 }
 982
 983 DECLARE_RTL_COND(rtl_ocpar_cond)
 984 {
 985         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 986 }
 987
 988 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 989
 990 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 991 {
 992         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 996 {
 997         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 998 }
 999
1000 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1001 {
1002         r8168dp_2_mdio_start(tp);
1003
1004         r8169_mdio_write(tp, reg, value);
1005
1006         r8168dp_2_mdio_stop(tp);
1007 }
1008
1009 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1010 {
1011         int value;
1012
1013         /* Work around issue with chip reporting wrong PHY ID */
1014         if (reg == MII_PHYSID2)
1015                 return 0xc912;
1016
1017         r8168dp_2_mdio_start(tp);
1018
1019         value = r8169_mdio_read(tp, reg);
1020
1021         r8168dp_2_mdio_stop(tp);
1022
1023         return value;
1024 }
1025
1026 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1027 {
1028         switch (tp->mac_version) {
1029         case RTL_GIGA_MAC_VER_28:
1030         case RTL_GIGA_MAC_VER_31:
1031                 r8168dp_2_mdio_write(tp, location, val);
1032                 break;
1033         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1034                 r8168g_mdio_write(tp, location, val);
1035                 break;
1036         default:
1037                 r8169_mdio_write(tp, location, val);
1038                 break;
1039         }
1040 }
1041
1042 static int rtl_readphy(struct rtl8169_private *tp, int location)
1043 {
1044         switch (tp->mac_version) {
1045         case RTL_GIGA_MAC_VER_28:
1046         case RTL_GIGA_MAC_VER_31:
1047                 return r8168dp_2_mdio_read(tp, location);
1048         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1049                 return r8168g_mdio_read(tp, location);
1050         default:
1051                 return r8169_mdio_read(tp, location);
1052         }
1053 }
1054
1055 DECLARE_RTL_COND(rtl_ephyar_cond)
1056 {
1057         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1058 }
1059
1060 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1061 {
1062         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1063                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1064
1065         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1066
1067         udelay(10);
1068 }
1069
1070 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1071 {
1072         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1073
1074         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1075                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1076 }
1077
1078 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1079 {
1080         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1081         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1082                 RTL_R32(tp, OCPDR) : ~0;
1083 }
1084
1085 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1086 {
1087         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1088 }
1089
1090 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1091                               u32 data)
1092 {
1093         RTL_W32(tp, OCPDR, data);
1094         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1095         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1096 }
1097
1098 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1099                               u32 data)
1100 {
1101         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1102                        data, ERIAR_OOB);
1103 }
1104
1105 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1106 {
1107         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1108
1109         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1110 }
1111
1112 #define OOB_CMD_RESET           0x00
1113 #define OOB_CMD_DRIVER_START    0x05
1114 #define OOB_CMD_DRIVER_STOP     0x06
1115
1116 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1117 {
1118         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1119 }
1120
1121 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1122 {
1123         u16 reg;
1124
1125         reg = rtl8168_get_ocp_reg(tp);
1126
1127         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1128 }
1129
1130 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1131 {
1132         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1133 }
1134
1135 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1136 {
1137         return RTL_R8(tp, IBISR0) & 0x20;
1138 }
1139
1140 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1141 {
1142         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1143         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1144         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1145         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1146 }
1147
1148 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1149 {
1150         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1151         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1152 }
1153
1154 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1155 {
1156         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1157         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1158         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1159 }
1160
1161 static void rtl8168_driver_start(struct rtl8169_private *tp)
1162 {
1163         if (tp->dash_type == RTL_DASH_DP)
1164                 rtl8168dp_driver_start(tp);
1165         else
1166                 rtl8168ep_driver_start(tp);
1167 }
1168
1169 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1170 {
1171         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1172         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1173 }
1174
1175 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1176 {
1177         rtl8168ep_stop_cmac(tp);
1178         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1179         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1180         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1181 }
1182
1183 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1184 {
1185         if (tp->dash_type == RTL_DASH_DP)
1186                 rtl8168dp_driver_stop(tp);
1187         else
1188                 rtl8168ep_driver_stop(tp);
1189 }
1190
1191 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1192 {
1193         u16 reg = rtl8168_get_ocp_reg(tp);
1194
1195         return r8168dp_ocp_read(tp, reg) & BIT(15);
1196 }
1197
1198 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1199 {
1200         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1201 }
1202
1203 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1204 {
1205         switch (tp->mac_version) {
1206         case RTL_GIGA_MAC_VER_28:
1207         case RTL_GIGA_MAC_VER_31:
1208                 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1209         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
1210                 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1211         default:
1212                 return RTL_DASH_NONE;
1213         }
1214 }
1215
1216 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1217 {
1218         switch (tp->mac_version) {
1219         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1220         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1221         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1222         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1223                 if (enable)
1224                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1225                 else
1226                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1227                 break;
1228         default:
1229                 break;
1230         }
1231 }
1232
1233 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1234 {
1235         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1236         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1237 }
1238
1239 DECLARE_RTL_COND(rtl_efusear_cond)
1240 {
1241         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1242 }
1243
1244 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1245 {
1246         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1247
1248         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1249                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1250 }
1251
1252 static u32 rtl_get_events(struct rtl8169_private *tp)
1253 {
1254         if (rtl_is_8125(tp))
1255                 return RTL_R32(tp, IntrStatus_8125);
1256         else
1257                 return RTL_R16(tp, IntrStatus);
1258 }
1259
1260 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1261 {
1262         if (rtl_is_8125(tp))
1263                 RTL_W32(tp, IntrStatus_8125, bits);
1264         else
1265                 RTL_W16(tp, IntrStatus, bits);
1266 }
1267
1268 static void rtl_irq_disable(struct rtl8169_private *tp)
1269 {
1270         if (rtl_is_8125(tp))
1271                 RTL_W32(tp, IntrMask_8125, 0);
1272         else
1273                 RTL_W16(tp, IntrMask, 0);
1274 }
1275
1276 static void rtl_irq_enable(struct rtl8169_private *tp)
1277 {
1278         if (rtl_is_8125(tp))
1279                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1280         else
1281                 RTL_W16(tp, IntrMask, tp->irq_mask);
1282 }
1283
1284 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1285 {
1286         rtl_irq_disable(tp);
1287         rtl_ack_events(tp, 0xffffffff);
1288         rtl_pci_commit(tp);
1289 }
1290
1291 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1292 {
1293         struct phy_device *phydev = tp->phydev;
1294
1295         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1296             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1297                 if (phydev->speed == SPEED_1000) {
1298                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1299                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1300                 } else if (phydev->speed == SPEED_100) {
1301                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1302                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1303                 } else {
1304                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1305                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1306                 }
1307                 rtl_reset_packet_filter(tp);
1308         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1309                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1310                 if (phydev->speed == SPEED_1000) {
1311                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1312                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1313                 } else {
1314                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1315                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1316                 }
1317         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1318                 if (phydev->speed == SPEED_10) {
1319                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1320                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1321                 } else {
1322                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1323                 }
1324         }
1325 }
1326
1327 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1328
1329 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1330 {
1331         struct rtl8169_private *tp = netdev_priv(dev);
1332
1333         wol->supported = WAKE_ANY;
1334         wol->wolopts = tp->saved_wolopts;
1335 }
1336
1337 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1338 {
1339         static const struct {
1340                 u32 opt;
1341                 u16 reg;
1342                 u8  mask;
1343         } cfg[] = {
1344                 { WAKE_PHY,   Config3, LinkUp },
1345                 { WAKE_UCAST, Config5, UWF },
1346                 { WAKE_BCAST, Config5, BWF },
1347                 { WAKE_MCAST, Config5, MWF },
1348                 { WAKE_ANY,   Config5, LanWake },
1349                 { WAKE_MAGIC, Config3, MagicPacket }
1350         };
1351         unsigned int i, tmp = ARRAY_SIZE(cfg);
1352         u8 options;
1353
1354         rtl_unlock_config_regs(tp);
1355
1356         if (rtl_is_8168evl_up(tp)) {
1357                 tmp--;
1358                 if (wolopts & WAKE_MAGIC)
1359                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1360                 else
1361                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1362         } else if (rtl_is_8125(tp)) {
1363                 tmp--;
1364                 if (wolopts & WAKE_MAGIC)
1365                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1366                 else
1367                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1368         }
1369
1370         for (i = 0; i < tmp; i++) {
1371                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1372                 if (wolopts & cfg[i].opt)
1373                         options |= cfg[i].mask;
1374                 RTL_W8(tp, cfg[i].reg, options);
1375         }
1376
1377         switch (tp->mac_version) {
1378         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1379                 options = RTL_R8(tp, Config1) & ~PMEnable;
1380                 if (wolopts)
1381                         options |= PMEnable;
1382                 RTL_W8(tp, Config1, options);
1383                 break;
1384         case RTL_GIGA_MAC_VER_34:
1385         case RTL_GIGA_MAC_VER_37:
1386         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1387                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1388                 if (wolopts)
1389                         options |= PME_SIGNAL;
1390                 RTL_W8(tp, Config2, options);
1391                 break;
1392         default:
1393                 break;
1394         }
1395
1396         rtl_lock_config_regs(tp);
1397
1398         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1399         rtl_set_d3_pll_down(tp, !wolopts);
1400         tp->dev->wol_enabled = wolopts ? 1 : 0;
1401 }
1402
1403 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1404 {
1405         struct rtl8169_private *tp = netdev_priv(dev);
1406
1407         if (wol->wolopts & ~WAKE_ANY)
1408                 return -EINVAL;
1409
1410         tp->saved_wolopts = wol->wolopts;
1411         __rtl8169_set_wol(tp, tp->saved_wolopts);
1412
1413         return 0;
1414 }
1415
1416 static void rtl8169_get_drvinfo(struct net_device *dev,
1417                                 struct ethtool_drvinfo *info)
1418 {
1419         struct rtl8169_private *tp = netdev_priv(dev);
1420         struct rtl_fw *rtl_fw = tp->rtl_fw;
1421
1422         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1423         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1424         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1425         if (rtl_fw)
1426                 strlcpy(info->fw_version, rtl_fw->version,
1427                         sizeof(info->fw_version));
1428 }
1429
1430 static int rtl8169_get_regs_len(struct net_device *dev)
1431 {
1432         return R8169_REGS_SIZE;
1433 }
1434
1435 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1436         netdev_features_t features)
1437 {
1438         struct rtl8169_private *tp = netdev_priv(dev);
1439
1440         if (dev->mtu > TD_MSS_MAX)
1441                 features &= ~NETIF_F_ALL_TSO;
1442
1443         if (dev->mtu > ETH_DATA_LEN &&
1444             tp->mac_version > RTL_GIGA_MAC_VER_06)
1445                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1446
1447         return features;
1448 }
1449
1450 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1451                                        netdev_features_t features)
1452 {
1453         u32 rx_config = RTL_R32(tp, RxConfig);
1454
1455         if (features & NETIF_F_RXALL)
1456                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1457         else
1458                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1459
1460         if (rtl_is_8125(tp)) {
1461                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1462                         rx_config |= RX_VLAN_8125;
1463                 else
1464                         rx_config &= ~RX_VLAN_8125;
1465         }
1466
1467         RTL_W32(tp, RxConfig, rx_config);
1468 }
1469
1470 static int rtl8169_set_features(struct net_device *dev,
1471                                 netdev_features_t features)
1472 {
1473         struct rtl8169_private *tp = netdev_priv(dev);
1474
1475         rtl_set_rx_config_features(tp, features);
1476
1477         if (features & NETIF_F_RXCSUM)
1478                 tp->cp_cmd |= RxChkSum;
1479         else
1480                 tp->cp_cmd &= ~RxChkSum;
1481
1482         if (!rtl_is_8125(tp)) {
1483                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1484                         tp->cp_cmd |= RxVlan;
1485                 else
1486                         tp->cp_cmd &= ~RxVlan;
1487         }
1488
1489         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1490         rtl_pci_commit(tp);
1491
1492         return 0;
1493 }
1494
1495 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1496 {
1497         return (skb_vlan_tag_present(skb)) ?
1498                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1499 }
1500
1501 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1502 {
1503         u32 opts2 = le32_to_cpu(desc->opts2);
1504
1505         if (opts2 & RxVlanTag)
1506                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1507 }
1508
1509 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1510                              void *p)
1511 {
1512         struct rtl8169_private *tp = netdev_priv(dev);
1513         u32 __iomem *data = tp->mmio_addr;
1514         u32 *dw = p;
1515         int i;
1516
1517         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1518                 memcpy_fromio(dw++, data++, 4);
1519 }
1520
1521 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1522         "tx_packets",
1523         "rx_packets",
1524         "tx_errors",
1525         "rx_errors",
1526         "rx_missed",
1527         "align_errors",
1528         "tx_single_collisions",
1529         "tx_multi_collisions",
1530         "unicast",
1531         "broadcast",
1532         "multicast",
1533         "tx_aborted",
1534         "tx_underrun",
1535 };
1536
1537 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1538 {
1539         switch (sset) {
1540         case ETH_SS_STATS:
1541                 return ARRAY_SIZE(rtl8169_gstrings);
1542         default:
1543                 return -EOPNOTSUPP;
1544         }
1545 }
1546
1547 DECLARE_RTL_COND(rtl_counters_cond)
1548 {
1549         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1550 }
1551
1552 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1553 {
1554         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1555
1556         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1557         rtl_pci_commit(tp);
1558         RTL_W32(tp, CounterAddrLow, cmd);
1559         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1560
1561         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1562 }
1563
1564 static void rtl8169_update_counters(struct rtl8169_private *tp)
1565 {
1566         u8 val = RTL_R8(tp, ChipCmd);
1567
1568         /*
1569          * Some chips are unable to dump tally counters when the receiver
1570          * is disabled. If 0xff chip may be in a PCI power-save state.
1571          */
1572         if (val & CmdRxEnb && val != 0xff)
1573                 rtl8169_do_counters(tp, CounterDump);
1574 }
1575
1576 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1577 {
1578         struct rtl8169_counters *counters = tp->counters;
1579
1580         /*
1581          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1582          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1583          * reset by a power cycle, while the counter values collected by the
1584          * driver are reset at every driver unload/load cycle.
1585          *
1586          * To make sure the HW values returned by @get_stats64 match the SW
1587          * values, we collect the initial values at first open(*) and use them
1588          * as offsets to normalize the values returned by @get_stats64.
1589          *
1590          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1591          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1592          * set at open time by rtl_hw_start.
1593          */
1594
1595         if (tp->tc_offset.inited)
1596                 return;
1597
1598         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1599                 rtl8169_do_counters(tp, CounterReset);
1600         } else {
1601                 rtl8169_update_counters(tp);
1602                 tp->tc_offset.tx_errors = counters->tx_errors;
1603                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1604                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1605                 tp->tc_offset.rx_missed = counters->rx_missed;
1606         }
1607
1608         tp->tc_offset.inited = true;
1609 }
1610
1611 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1612                                       struct ethtool_stats *stats, u64 *data)
1613 {
1614         struct rtl8169_private *tp = netdev_priv(dev);
1615         struct rtl8169_counters *counters;
1616
1617         counters = tp->counters;
1618         rtl8169_update_counters(tp);
1619
1620         data[0] = le64_to_cpu(counters->tx_packets);
1621         data[1] = le64_to_cpu(counters->rx_packets);
1622         data[2] = le64_to_cpu(counters->tx_errors);
1623         data[3] = le32_to_cpu(counters->rx_errors);
1624         data[4] = le16_to_cpu(counters->rx_missed);
1625         data[5] = le16_to_cpu(counters->align_errors);
1626         data[6] = le32_to_cpu(counters->tx_one_collision);
1627         data[7] = le32_to_cpu(counters->tx_multi_collision);
1628         data[8] = le64_to_cpu(counters->rx_unicast);
1629         data[9] = le64_to_cpu(counters->rx_broadcast);
1630         data[10] = le32_to_cpu(counters->rx_multicast);
1631         data[11] = le16_to_cpu(counters->tx_aborted);
1632         data[12] = le16_to_cpu(counters->tx_underun);
1633 }
1634
1635 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1636 {
1637         switch(stringset) {
1638         case ETH_SS_STATS:
1639                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1640                 break;
1641         }
1642 }
1643
1644 /*
1645  * Interrupt coalescing
1646  *
1647  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1648  * >     8169, 8168 and 810x line of chipsets
1649  *
1650  * 8169, 8168, and 8136(810x) serial chipsets support it.
1651  *
1652  * > 2 - the Tx timer unit at gigabit speed
1653  *
1654  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1655  * (0xe0) bit 1 and bit 0.
1656  *
1657  * For 8169
1658  * bit[1:0] \ speed        1000M           100M            10M
1659  * 0 0                     320ns           2.56us          40.96us
1660  * 0 1                     2.56us          20.48us         327.7us
1661  * 1 0                     5.12us          40.96us         655.4us
1662  * 1 1                     10.24us         81.92us         1.31ms
1663  *
1664  * For the other
1665  * bit[1:0] \ speed        1000M           100M            10M
1666  * 0 0                     5us             2.56us          40.96us
1667  * 0 1                     40us            20.48us         327.7us
1668  * 1 0                     80us            40.96us         655.4us
1669  * 1 1                     160us           81.92us         1.31ms
1670  */
1671
1672 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1673 struct rtl_coalesce_info {
1674         u32 speed;
1675         u32 scale_nsecs[4];
1676 };
1677
1678 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1679 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1680
1681 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1682         { SPEED_1000,   COALESCE_DELAY(320) },
1683         { SPEED_100,    COALESCE_DELAY(2560) },
1684         { SPEED_10,     COALESCE_DELAY(40960) },
1685         { 0 },
1686 };
1687
1688 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1689         { SPEED_1000,   COALESCE_DELAY(5000) },
1690         { SPEED_100,    COALESCE_DELAY(2560) },
1691         { SPEED_10,     COALESCE_DELAY(40960) },
1692         { 0 },
1693 };
1694 #undef COALESCE_DELAY
1695
1696 /* get rx/tx scale vector corresponding to current speed */
1697 static const struct rtl_coalesce_info *
1698 rtl_coalesce_info(struct rtl8169_private *tp)
1699 {
1700         const struct rtl_coalesce_info *ci;
1701
1702         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1703                 ci = rtl_coalesce_info_8169;
1704         else
1705                 ci = rtl_coalesce_info_8168_8136;
1706
1707         /* if speed is unknown assume highest one */
1708         if (tp->phydev->speed == SPEED_UNKNOWN)
1709                 return ci;
1710
1711         for (; ci->speed; ci++) {
1712                 if (tp->phydev->speed == ci->speed)
1713                         return ci;
1714         }
1715
1716         return ERR_PTR(-ELNRNG);
1717 }
1718
1719 static int rtl_get_coalesce(struct net_device *dev,
1720                             struct ethtool_coalesce *ec,
1721                             struct kernel_ethtool_coalesce *kernel_coal,
1722                             struct netlink_ext_ack *extack)
1723 {
1724         struct rtl8169_private *tp = netdev_priv(dev);
1725         const struct rtl_coalesce_info *ci;
1726         u32 scale, c_us, c_fr;
1727         u16 intrmit;
1728
1729         if (rtl_is_8125(tp))
1730                 return -EOPNOTSUPP;
1731
1732         memset(ec, 0, sizeof(*ec));
1733
1734         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1735         ci = rtl_coalesce_info(tp);
1736         if (IS_ERR(ci))
1737                 return PTR_ERR(ci);
1738
1739         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1740
1741         intrmit = RTL_R16(tp, IntrMitigate);
1742
1743         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1744         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1745
1746         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1747         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1748         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1749
1750         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1751         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1752
1753         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1754         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1755
1756         return 0;
1757 }
1758
1759 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1760 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1761                                      u16 *cp01)
1762 {
1763         const struct rtl_coalesce_info *ci;
1764         u16 i;
1765
1766         ci = rtl_coalesce_info(tp);
1767         if (IS_ERR(ci))
1768                 return PTR_ERR(ci);
1769
1770         for (i = 0; i < 4; i++) {
1771                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1772                         *cp01 = i;
1773                         return ci->scale_nsecs[i];
1774                 }
1775         }
1776
1777         return -ERANGE;
1778 }
1779
1780 static int rtl_set_coalesce(struct net_device *dev,
1781                             struct ethtool_coalesce *ec,
1782                             struct kernel_ethtool_coalesce *kernel_coal,
1783                             struct netlink_ext_ack *extack)
1784 {
1785         struct rtl8169_private *tp = netdev_priv(dev);
1786         u32 tx_fr = ec->tx_max_coalesced_frames;
1787         u32 rx_fr = ec->rx_max_coalesced_frames;
1788         u32 coal_usec_max, units;
1789         u16 w = 0, cp01 = 0;
1790         int scale;
1791
1792         if (rtl_is_8125(tp))
1793                 return -EOPNOTSUPP;
1794
1795         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1796                 return -ERANGE;
1797
1798         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1799         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1800         if (scale < 0)
1801                 return scale;
1802
1803         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1804          * not only when usecs=0 because of e.g. the following scenario:
1805          *
1806          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1807          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1808          * - then user does `ethtool -C eth0 rx-usecs 100`
1809          *
1810          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1811          * if we want to ignore rx_frames then it has to be set to 0.
1812          */
1813         if (rx_fr == 1)
1814                 rx_fr = 0;
1815         if (tx_fr == 1)
1816                 tx_fr = 0;
1817
1818         /* HW requires time limit to be set if frame limit is set */
1819         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1820             (rx_fr && !ec->rx_coalesce_usecs))
1821                 return -EINVAL;
1822
1823         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1824         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1825
1826         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1827         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1828         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1829         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1830
1831         RTL_W16(tp, IntrMitigate, w);
1832
1833         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1834         if (rtl_is_8168evl_up(tp)) {
1835                 if (!rx_fr && !tx_fr)
1836                         /* disable packet counter */
1837                         tp->cp_cmd |= PktCntrDisable;
1838                 else
1839                         tp->cp_cmd &= ~PktCntrDisable;
1840         }
1841
1842         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1843         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1844         rtl_pci_commit(tp);
1845
1846         return 0;
1847 }
1848
1849 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1850 {
1851         struct rtl8169_private *tp = netdev_priv(dev);
1852
1853         if (!rtl_supports_eee(tp))
1854                 return -EOPNOTSUPP;
1855
1856         return phy_ethtool_get_eee(tp->phydev, data);
1857 }
1858
1859 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1860 {
1861         struct rtl8169_private *tp = netdev_priv(dev);
1862         int ret;
1863
1864         if (!rtl_supports_eee(tp))
1865                 return -EOPNOTSUPP;
1866
1867         ret = phy_ethtool_set_eee(tp->phydev, data);
1868
1869         if (!ret)
1870                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1871                                            MDIO_AN_EEE_ADV);
1872         return ret;
1873 }
1874
1875 static void rtl8169_get_ringparam(struct net_device *dev,
1876                                   struct ethtool_ringparam *data)
1877 {
1878         data->rx_max_pending = NUM_RX_DESC;
1879         data->rx_pending = NUM_RX_DESC;
1880         data->tx_max_pending = NUM_TX_DESC;
1881         data->tx_pending = NUM_TX_DESC;
1882 }
1883
1884 static void rtl8169_get_pauseparam(struct net_device *dev,
1885                                    struct ethtool_pauseparam *data)
1886 {
1887         struct rtl8169_private *tp = netdev_priv(dev);
1888         bool tx_pause, rx_pause;
1889
1890         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1891
1892         data->autoneg = tp->phydev->autoneg;
1893         data->tx_pause = tx_pause ? 1 : 0;
1894         data->rx_pause = rx_pause ? 1 : 0;
1895 }
1896
1897 static int rtl8169_set_pauseparam(struct net_device *dev,
1898                                   struct ethtool_pauseparam *data)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901
1902         if (dev->mtu > ETH_DATA_LEN)
1903                 return -EOPNOTSUPP;
1904
1905         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1906
1907         return 0;
1908 }
1909
1910 static const struct ethtool_ops rtl8169_ethtool_ops = {
1911         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1912                                      ETHTOOL_COALESCE_MAX_FRAMES,
1913         .get_drvinfo            = rtl8169_get_drvinfo,
1914         .get_regs_len           = rtl8169_get_regs_len,
1915         .get_link               = ethtool_op_get_link,
1916         .get_coalesce           = rtl_get_coalesce,
1917         .set_coalesce           = rtl_set_coalesce,
1918         .get_regs               = rtl8169_get_regs,
1919         .get_wol                = rtl8169_get_wol,
1920         .set_wol                = rtl8169_set_wol,
1921         .get_strings            = rtl8169_get_strings,
1922         .get_sset_count         = rtl8169_get_sset_count,
1923         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1924         .get_ts_info            = ethtool_op_get_ts_info,
1925         .nway_reset             = phy_ethtool_nway_reset,
1926         .get_eee                = rtl8169_get_eee,
1927         .set_eee                = rtl8169_set_eee,
1928         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1929         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1930         .get_ringparam          = rtl8169_get_ringparam,
1931         .get_pauseparam         = rtl8169_get_pauseparam,
1932         .set_pauseparam         = rtl8169_set_pauseparam,
1933 };
1934
1935 static void rtl_enable_eee(struct rtl8169_private *tp)
1936 {
1937         struct phy_device *phydev = tp->phydev;
1938         int adv;
1939
1940         /* respect EEE advertisement the user may have set */
1941         if (tp->eee_adv >= 0)
1942                 adv = tp->eee_adv;
1943         else
1944                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1945
1946         if (adv >= 0)
1947                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1948 }
1949
1950 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1951 {
1952         /*
1953          * The driver currently handles the 8168Bf and the 8168Be identically
1954          * but they can be identified more specifically through the test below
1955          * if needed:
1956          *
1957          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1958          *
1959          * Same thing for the 8101Eb and the 8101Ec:
1960          *
1961          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1962          */
1963         static const struct rtl_mac_info {
1964                 u16 mask;
1965                 u16 val;
1966                 enum mac_version ver;
1967         } mac_info[] = {
1968                 /* 8125B family. */
1969                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1970
1971                 /* 8125A family. */
1972                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1973                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1974
1975                 /* RTL8117 */
1976                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
1977                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1978
1979                 /* 8168EP family. */
1980                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1981                 /* It seems this chip version never made it to
1982                  * the wild. Let's disable detection.
1983                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
1984                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
1985                  */
1986
1987                 /* 8168H family. */
1988                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1989                 /* It seems this chip version never made it to
1990                  * the wild. Let's disable detection.
1991                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
1992                  */
1993
1994                 /* 8168G family. */
1995                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1996                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1997                 /* It seems this chip version never made it to
1998                  * the wild. Let's disable detection.
1999                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
2000                  */
2001                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2002
2003                 /* 8168F family. */
2004                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2005                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2006                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2007
2008                 /* 8168E family. */
2009                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2010                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2011                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2012
2013                 /* 8168D family. */
2014                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2015                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2016
2017                 /* 8168DP family. */
2018                 /* It seems this early RTL8168dp version never made it to
2019                  * the wild. Support has been removed.
2020                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2021                  */
2022                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2023                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2024
2025                 /* 8168C family. */
2026                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2027                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2028                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2029                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2030                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2031                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2032                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2033
2034                 /* 8168B family. */
2035                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2036                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2037                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2038
2039                 /* 8101 family. */
2040                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2041                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2042                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2043                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2044                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2045                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2046                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2047                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2048                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2049                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2050                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2051                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2052                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2053                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2054                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2055                 /* FIXME: where did these entries come from ? -- FR
2056                  * Not even r8101 vendor driver knows these id's,
2057                  * so let's disable detection for now. -- HK
2058                  * { 0xfc8, 0x388,      RTL_GIGA_MAC_VER_13 },
2059                  * { 0xfc8, 0x308,      RTL_GIGA_MAC_VER_13 },
2060                  */
2061
2062                 /* 8110 family. */
2063                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2064                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2065                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2066                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2067                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2068
2069                 /* Catch-all */
2070                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2071         };
2072         const struct rtl_mac_info *p = mac_info;
2073         enum mac_version ver;
2074
2075         while ((xid & p->mask) != p->val)
2076                 p++;
2077         ver = p->ver;
2078
2079         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2080                 if (ver == RTL_GIGA_MAC_VER_42)
2081                         ver = RTL_GIGA_MAC_VER_43;
2082                 else if (ver == RTL_GIGA_MAC_VER_45)
2083                         ver = RTL_GIGA_MAC_VER_47;
2084                 else if (ver == RTL_GIGA_MAC_VER_46)
2085                         ver = RTL_GIGA_MAC_VER_48;
2086         }
2087
2088         return ver;
2089 }
2090
2091 static void rtl_release_firmware(struct rtl8169_private *tp)
2092 {
2093         if (tp->rtl_fw) {
2094                 rtl_fw_release_firmware(tp->rtl_fw);
2095                 kfree(tp->rtl_fw);
2096                 tp->rtl_fw = NULL;
2097         }
2098 }
2099
2100 void r8169_apply_firmware(struct rtl8169_private *tp)
2101 {
2102         int val;
2103
2104         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2105         if (tp->rtl_fw) {
2106                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2107                 /* At least one firmware doesn't reset tp->ocp_base. */
2108                 tp->ocp_base = OCP_STD_PHY_BASE;
2109
2110                 /* PHY soft reset may still be in progress */
2111                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2112                                       !(val & BMCR_RESET),
2113                                       50000, 600000, true);
2114         }
2115 }
2116
2117 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2118 {
2119         /* Adjust EEE LED frequency */
2120         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2121                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2122
2123         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2124 }
2125
2126 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2127 {
2128         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2129         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2130 }
2131
2132 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2133 {
2134         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2135 }
2136
2137 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2138 {
2139         rtl8125_set_eee_txidle_timer(tp);
2140         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2141 }
2142
2143 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2144 {
2145         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2146         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2147         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2148         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2149 }
2150
2151 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2152 {
2153         u16 data1, data2, ioffset;
2154
2155         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2156         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2157         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2158
2159         ioffset = (data2 >> 1) & 0x7ff8;
2160         ioffset |= data2 & 0x0007;
2161         if (data1 & BIT(7))
2162                 ioffset |= BIT(15);
2163
2164         return ioffset;
2165 }
2166
2167 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2168 {
2169         set_bit(flag, tp->wk.flags);
2170         schedule_work(&tp->wk.work);
2171 }
2172
2173 static void rtl8169_init_phy(struct rtl8169_private *tp)
2174 {
2175         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2176
2177         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2178                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2179                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2180                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2181                 RTL_W8(tp, 0x82, 0x01);
2182         }
2183
2184         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2185             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2186             tp->pci_dev->subsystem_device == 0xe000)
2187                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2188
2189         /* We may have called phy_speed_down before */
2190         phy_speed_up(tp->phydev);
2191
2192         if (rtl_supports_eee(tp))
2193                 rtl_enable_eee(tp);
2194
2195         genphy_soft_reset(tp->phydev);
2196 }
2197
2198 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2199 {
2200         rtl_unlock_config_regs(tp);
2201
2202         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2203         rtl_pci_commit(tp);
2204
2205         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2206         rtl_pci_commit(tp);
2207
2208         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2209                 rtl_rar_exgmac_set(tp, addr);
2210
2211         rtl_lock_config_regs(tp);
2212 }
2213
2214 static int rtl_set_mac_address(struct net_device *dev, void *p)
2215 {
2216         struct rtl8169_private *tp = netdev_priv(dev);
2217         int ret;
2218
2219         ret = eth_mac_addr(dev, p);
2220         if (ret)
2221                 return ret;
2222
2223         rtl_rar_set(tp, dev->dev_addr);
2224
2225         return 0;
2226 }
2227
2228 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2229 {
2230         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2231                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2232                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2233 }
2234
2235 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2236 {
2237         if (tp->dash_type != RTL_DASH_NONE)
2238                 return;
2239
2240         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2241             tp->mac_version == RTL_GIGA_MAC_VER_33)
2242                 rtl_ephy_write(tp, 0x19, 0xff64);
2243
2244         if (device_may_wakeup(tp_to_dev(tp))) {
2245                 phy_speed_down(tp->phydev, false);
2246                 rtl_wol_enable_rx(tp);
2247         }
2248 }
2249
2250 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2251 {
2252         switch (tp->mac_version) {
2253         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2254         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2255                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2256                 break;
2257         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2258         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2259         case RTL_GIGA_MAC_VER_38:
2260                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2261                 break;
2262         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2263                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2264                 break;
2265         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2266                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2267                 break;
2268         default:
2269                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2270                 break;
2271         }
2272 }
2273
2274 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2275 {
2276         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2277 }
2278
2279 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2280 {
2281         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2282         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2283 }
2284
2285 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2286 {
2287         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2288         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2289 }
2290
2291 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2292 {
2293         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2294 }
2295
2296 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2297 {
2298         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2299 }
2300
2301 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2302 {
2303         RTL_W8(tp, MaxTxPacketSize, 0x24);
2304         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2305         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2306 }
2307
2308 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2309 {
2310         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2311         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2312         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2313 }
2314
2315 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2316 {
2317         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2318 }
2319
2320 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2321 {
2322         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2323 }
2324
2325 static void rtl_jumbo_config(struct rtl8169_private *tp)
2326 {
2327         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2328         int readrq = 4096;
2329
2330         rtl_unlock_config_regs(tp);
2331         switch (tp->mac_version) {
2332         case RTL_GIGA_MAC_VER_12:
2333         case RTL_GIGA_MAC_VER_17:
2334                 if (jumbo) {
2335                         readrq = 512;
2336                         r8168b_1_hw_jumbo_enable(tp);
2337                 } else {
2338                         r8168b_1_hw_jumbo_disable(tp);
2339                 }
2340                 break;
2341         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2342                 if (jumbo) {
2343                         readrq = 512;
2344                         r8168c_hw_jumbo_enable(tp);
2345                 } else {
2346                         r8168c_hw_jumbo_disable(tp);
2347                 }
2348                 break;
2349         case RTL_GIGA_MAC_VER_28:
2350                 if (jumbo)
2351                         r8168dp_hw_jumbo_enable(tp);
2352                 else
2353                         r8168dp_hw_jumbo_disable(tp);
2354                 break;
2355         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2356                 if (jumbo)
2357                         r8168e_hw_jumbo_enable(tp);
2358                 else
2359                         r8168e_hw_jumbo_disable(tp);
2360                 break;
2361         default:
2362                 break;
2363         }
2364         rtl_lock_config_regs(tp);
2365
2366         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2367                 pcie_set_readrq(tp->pci_dev, readrq);
2368
2369         /* Chip doesn't support pause in jumbo mode */
2370         if (jumbo) {
2371                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2372                                    tp->phydev->advertising);
2373                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2374                                    tp->phydev->advertising);
2375                 phy_start_aneg(tp->phydev);
2376         }
2377 }
2378
2379 DECLARE_RTL_COND(rtl_chipcmd_cond)
2380 {
2381         return RTL_R8(tp, ChipCmd) & CmdReset;
2382 }
2383
2384 static void rtl_hw_reset(struct rtl8169_private *tp)
2385 {
2386         RTL_W8(tp, ChipCmd, CmdReset);
2387
2388         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2389 }
2390
2391 static void rtl_request_firmware(struct rtl8169_private *tp)
2392 {
2393         struct rtl_fw *rtl_fw;
2394
2395         /* firmware loaded already or no firmware available */
2396         if (tp->rtl_fw || !tp->fw_name)
2397                 return;
2398
2399         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2400         if (!rtl_fw)
2401                 return;
2402
2403         rtl_fw->phy_write = rtl_writephy;
2404         rtl_fw->phy_read = rtl_readphy;
2405         rtl_fw->mac_mcu_write = mac_mcu_write;
2406         rtl_fw->mac_mcu_read = mac_mcu_read;
2407         rtl_fw->fw_name = tp->fw_name;
2408         rtl_fw->dev = tp_to_dev(tp);
2409
2410         if (rtl_fw_request_firmware(rtl_fw))
2411                 kfree(rtl_fw);
2412         else
2413                 tp->rtl_fw = rtl_fw;
2414 }
2415
2416 static void rtl_rx_close(struct rtl8169_private *tp)
2417 {
2418         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2419 }
2420
2421 DECLARE_RTL_COND(rtl_npq_cond)
2422 {
2423         return RTL_R8(tp, TxPoll) & NPQ;
2424 }
2425
2426 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2427 {
2428         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2429 }
2430
2431 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2432 {
2433         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2434 }
2435
2436 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2437 {
2438         /* IntrMitigate has new functionality on RTL8125 */
2439         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2440 }
2441
2442 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2443 {
2444         switch (tp->mac_version) {
2445         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2446                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2447                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2448                 break;
2449         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2450                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2451                 break;
2452         case RTL_GIGA_MAC_VER_63:
2453                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2454                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2455                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2456                 break;
2457         default:
2458                 break;
2459         }
2460 }
2461
2462 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2463 {
2464         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2465         fsleep(2000);
2466         rtl_wait_txrx_fifo_empty(tp);
2467 }
2468
2469 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2470 {
2471         u32 val = TX_DMA_BURST << TxDMAShift |
2472                   InterFrameGap << TxInterFrameGapShift;
2473
2474         if (rtl_is_8168evl_up(tp))
2475                 val |= TXCFG_AUTO_FIFO;
2476
2477         RTL_W32(tp, TxConfig, val);
2478 }
2479
2480 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2481 {
2482         /* Low hurts. Let's disable the filtering. */
2483         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2484 }
2485
2486 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2487 {
2488         /*
2489          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2490          * register to be written before TxDescAddrLow to work.
2491          * Switching from MMIO to I/O access fixes the issue as well.
2492          */
2493         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2494         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2495         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2496         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2497 }
2498
2499 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2500 {
2501         u32 val;
2502
2503         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2504                 val = 0x000fff00;
2505         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2506                 val = 0x00ffff00;
2507         else
2508                 return;
2509
2510         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2511                 val |= 0xff;
2512
2513         RTL_W32(tp, 0x7c, val);
2514 }
2515
2516 static void rtl_set_rx_mode(struct net_device *dev)
2517 {
2518         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2519         /* Multicast hash filter */
2520         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2521         struct rtl8169_private *tp = netdev_priv(dev);
2522         u32 tmp;
2523
2524         if (dev->flags & IFF_PROMISC) {
2525                 rx_mode |= AcceptAllPhys;
2526         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2527                    dev->flags & IFF_ALLMULTI ||
2528                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2529                 /* accept all multicasts */
2530         } else if (netdev_mc_empty(dev)) {
2531                 rx_mode &= ~AcceptMulticast;
2532         } else {
2533                 struct netdev_hw_addr *ha;
2534
2535                 mc_filter[1] = mc_filter[0] = 0;
2536                 netdev_for_each_mc_addr(ha, dev) {
2537                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2538                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2539                 }
2540
2541                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2542                         tmp = mc_filter[0];
2543                         mc_filter[0] = swab32(mc_filter[1]);
2544                         mc_filter[1] = swab32(tmp);
2545                 }
2546         }
2547
2548         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2549         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2550
2551         tmp = RTL_R32(tp, RxConfig);
2552         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2553 }
2554
2555 DECLARE_RTL_COND(rtl_csiar_cond)
2556 {
2557         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2558 }
2559
2560 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2561 {
2562         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2563
2564         RTL_W32(tp, CSIDR, value);
2565         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2566                 CSIAR_BYTE_ENABLE | func << 16);
2567
2568         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2569 }
2570
2571 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2572 {
2573         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2574
2575         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2576                 CSIAR_BYTE_ENABLE);
2577
2578         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2579                 RTL_R32(tp, CSIDR) : ~0;
2580 }
2581
2582 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2583 {
2584         struct pci_dev *pdev = tp->pci_dev;
2585         u32 csi;
2586
2587         /* According to Realtek the value at config space address 0x070f
2588          * controls the L0s/L1 entrance latency. We try standard ECAM access
2589          * first and if it fails fall back to CSI.
2590          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2591          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2592          */
2593         if (pdev->cfg_size > 0x070f &&
2594             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2595                 return;
2596
2597         netdev_notice_once(tp->dev,
2598                 "No native access to PCI extended config space, falling back to CSI\n");
2599         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2600         rtl_csi_write(tp, 0x070c, csi | val << 24);
2601 }
2602
2603 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2604 {
2605         /* L0 7us, L1 16us */
2606         rtl_set_aspm_entry_latency(tp, 0x27);
2607 }
2608
2609 struct ephy_info {
2610         unsigned int offset;
2611         u16 mask;
2612         u16 bits;
2613 };
2614
2615 static void __rtl_ephy_init(struct rtl8169_private *tp,
2616                             const struct ephy_info *e, int len)
2617 {
2618         u16 w;
2619
2620         while (len-- > 0) {
2621                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2622                 rtl_ephy_write(tp, e->offset, w);
2623                 e++;
2624         }
2625 }
2626
2627 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2628
2629 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2630 {
2631         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2632                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2633 }
2634
2635 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2636 {
2637         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2638                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2639 }
2640
2641 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2642 {
2643         /* work around an issue when PCI reset occurs during L2/L3 state */
2644         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2645 }
2646
2647 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2648 {
2649         /* Bits control which events trigger ASPM L1 exit:
2650          * Bit 12: rxdv
2651          * Bit 11: ltr_msg
2652          * Bit 10: txdma_poll
2653          * Bit  9: xadm
2654          * Bit  8: pktavi
2655          * Bit  7: txpla
2656          */
2657         switch (tp->mac_version) {
2658         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2659                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2660                 break;
2661         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2662                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2663                 break;
2664         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2665                 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
2666                 break;
2667         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2668                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2669                 break;
2670         default:
2671                 break;
2672         }
2673 }
2674
2675 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2676 {
2677         /* Don't enable ASPM in the chip if OS can't control ASPM */
2678         if (enable && tp->aspm_manageable) {
2679                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2680                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2681         } else {
2682                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2683                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2684         }
2685
2686         udelay(10);
2687 }
2688
2689 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2690                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2691 {
2692         /* Usage of dynamic vs. static FIFO is controlled by bit
2693          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2694          */
2695         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2696         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2697 }
2698
2699 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2700                                           u8 low, u8 high)
2701 {
2702         /* FIFO thresholds for pause flow control */
2703         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2704         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2705 }
2706
2707 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2708 {
2709         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2710 }
2711
2712 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2713 {
2714         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2715
2716         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2717
2718         rtl_disable_clock_request(tp);
2719 }
2720
2721 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2722 {
2723         static const struct ephy_info e_info_8168cp[] = {
2724                 { 0x01, 0,      0x0001 },
2725                 { 0x02, 0x0800, 0x1000 },
2726                 { 0x03, 0,      0x0042 },
2727                 { 0x06, 0x0080, 0x0000 },
2728                 { 0x07, 0,      0x2000 }
2729         };
2730
2731         rtl_set_def_aspm_entry_latency(tp);
2732
2733         rtl_ephy_init(tp, e_info_8168cp);
2734
2735         __rtl_hw_start_8168cp(tp);
2736 }
2737
2738 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2739 {
2740         rtl_set_def_aspm_entry_latency(tp);
2741
2742         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2743 }
2744
2745 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2746 {
2747         rtl_set_def_aspm_entry_latency(tp);
2748
2749         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2750
2751         /* Magic. */
2752         RTL_W8(tp, DBG_REG, 0x20);
2753 }
2754
2755 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2756 {
2757         static const struct ephy_info e_info_8168c_1[] = {
2758                 { 0x02, 0x0800, 0x1000 },
2759                 { 0x03, 0,      0x0002 },
2760                 { 0x06, 0x0080, 0x0000 }
2761         };
2762
2763         rtl_set_def_aspm_entry_latency(tp);
2764
2765         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2766
2767         rtl_ephy_init(tp, e_info_8168c_1);
2768
2769         __rtl_hw_start_8168cp(tp);
2770 }
2771
2772 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2773 {
2774         static const struct ephy_info e_info_8168c_2[] = {
2775                 { 0x01, 0,      0x0001 },
2776                 { 0x03, 0x0400, 0x0020 }
2777         };
2778
2779         rtl_set_def_aspm_entry_latency(tp);
2780
2781         rtl_ephy_init(tp, e_info_8168c_2);
2782
2783         __rtl_hw_start_8168cp(tp);
2784 }
2785
2786 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2787 {
2788         rtl_set_def_aspm_entry_latency(tp);
2789
2790         __rtl_hw_start_8168cp(tp);
2791 }
2792
2793 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2794 {
2795         rtl_set_def_aspm_entry_latency(tp);
2796
2797         rtl_disable_clock_request(tp);
2798 }
2799
2800 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2801 {
2802         static const struct ephy_info e_info_8168d_4[] = {
2803                 { 0x0b, 0x0000, 0x0048 },
2804                 { 0x19, 0x0020, 0x0050 },
2805                 { 0x0c, 0x0100, 0x0020 },
2806                 { 0x10, 0x0004, 0x0000 },
2807         };
2808
2809         rtl_set_def_aspm_entry_latency(tp);
2810
2811         rtl_ephy_init(tp, e_info_8168d_4);
2812
2813         rtl_enable_clock_request(tp);
2814 }
2815
2816 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2817 {
2818         static const struct ephy_info e_info_8168e_1[] = {
2819                 { 0x00, 0x0200, 0x0100 },
2820                 { 0x00, 0x0000, 0x0004 },
2821                 { 0x06, 0x0002, 0x0001 },
2822                 { 0x06, 0x0000, 0x0030 },
2823                 { 0x07, 0x0000, 0x2000 },
2824                 { 0x00, 0x0000, 0x0020 },
2825                 { 0x03, 0x5800, 0x2000 },
2826                 { 0x03, 0x0000, 0x0001 },
2827                 { 0x01, 0x0800, 0x1000 },
2828                 { 0x07, 0x0000, 0x4000 },
2829                 { 0x1e, 0x0000, 0x2000 },
2830                 { 0x19, 0xffff, 0xfe6c },
2831                 { 0x0a, 0x0000, 0x0040 }
2832         };
2833
2834         rtl_set_def_aspm_entry_latency(tp);
2835
2836         rtl_ephy_init(tp, e_info_8168e_1);
2837
2838         rtl_disable_clock_request(tp);
2839
2840         /* Reset tx FIFO pointer */
2841         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2842         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2843
2844         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2845 }
2846
2847 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2848 {
2849         static const struct ephy_info e_info_8168e_2[] = {
2850                 { 0x09, 0x0000, 0x0080 },
2851                 { 0x19, 0x0000, 0x0224 },
2852                 { 0x00, 0x0000, 0x0004 },
2853                 { 0x0c, 0x3df0, 0x0200 },
2854         };
2855
2856         rtl_set_def_aspm_entry_latency(tp);
2857
2858         rtl_ephy_init(tp, e_info_8168e_2);
2859
2860         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2861         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2862         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2863         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2864         rtl_reset_packet_filter(tp);
2865         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2866         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2867         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2868
2869         rtl_disable_clock_request(tp);
2870
2871         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2872
2873         rtl8168_config_eee_mac(tp);
2874
2875         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2876         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2877         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2878
2879         rtl_hw_aspm_clkreq_enable(tp, true);
2880 }
2881
2882 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2883 {
2884         rtl_set_def_aspm_entry_latency(tp);
2885
2886         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2887         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2888         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2889         rtl_reset_packet_filter(tp);
2890         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2891         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2892         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2893         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2894
2895         rtl_disable_clock_request(tp);
2896
2897         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2898         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2899         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2900         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2901
2902         rtl8168_config_eee_mac(tp);
2903 }
2904
2905 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2906 {
2907         static const struct ephy_info e_info_8168f_1[] = {
2908                 { 0x06, 0x00c0, 0x0020 },
2909                 { 0x08, 0x0001, 0x0002 },
2910                 { 0x09, 0x0000, 0x0080 },
2911                 { 0x19, 0x0000, 0x0224 },
2912                 { 0x00, 0x0000, 0x0008 },
2913                 { 0x0c, 0x3df0, 0x0200 },
2914         };
2915
2916         rtl_hw_start_8168f(tp);
2917
2918         rtl_ephy_init(tp, e_info_8168f_1);
2919 }
2920
2921 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2922 {
2923         static const struct ephy_info e_info_8168f_1[] = {
2924                 { 0x06, 0x00c0, 0x0020 },
2925                 { 0x0f, 0xffff, 0x5200 },
2926                 { 0x19, 0x0000, 0x0224 },
2927                 { 0x00, 0x0000, 0x0008 },
2928                 { 0x0c, 0x3df0, 0x0200 },
2929         };
2930
2931         rtl_hw_start_8168f(tp);
2932         rtl_pcie_state_l2l3_disable(tp);
2933
2934         rtl_ephy_init(tp, e_info_8168f_1);
2935 }
2936
2937 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2938 {
2939         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2940         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2941
2942         rtl_set_def_aspm_entry_latency(tp);
2943
2944         rtl_reset_packet_filter(tp);
2945         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2946
2947         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2948
2949         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2950         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2951
2952         rtl8168_config_eee_mac(tp);
2953
2954         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2955         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2956
2957         rtl_pcie_state_l2l3_disable(tp);
2958 }
2959
2960 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2961 {
2962         static const struct ephy_info e_info_8168g_1[] = {
2963                 { 0x00, 0x0008, 0x0000 },
2964                 { 0x0c, 0x3ff0, 0x0820 },
2965                 { 0x1e, 0x0000, 0x0001 },
2966                 { 0x19, 0x8000, 0x0000 }
2967         };
2968
2969         rtl_hw_start_8168g(tp);
2970
2971         /* disable aspm and clock request before access ephy */
2972         rtl_hw_aspm_clkreq_enable(tp, false);
2973         rtl_ephy_init(tp, e_info_8168g_1);
2974         rtl_hw_aspm_clkreq_enable(tp, true);
2975 }
2976
2977 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2978 {
2979         static const struct ephy_info e_info_8168g_2[] = {
2980                 { 0x00, 0x0008, 0x0000 },
2981                 { 0x0c, 0x3ff0, 0x0820 },
2982                 { 0x19, 0xffff, 0x7c00 },
2983                 { 0x1e, 0xffff, 0x20eb },
2984                 { 0x0d, 0xffff, 0x1666 },
2985                 { 0x00, 0xffff, 0x10a3 },
2986                 { 0x06, 0xffff, 0xf050 },
2987                 { 0x04, 0x0000, 0x0010 },
2988                 { 0x1d, 0x4000, 0x0000 },
2989         };
2990
2991         rtl_hw_start_8168g(tp);
2992
2993         /* disable aspm and clock request before access ephy */
2994         rtl_hw_aspm_clkreq_enable(tp, false);
2995         rtl_ephy_init(tp, e_info_8168g_2);
2996 }
2997
2998 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
2999 {
3000         static const struct ephy_info e_info_8411_2[] = {
3001                 { 0x00, 0x0008, 0x0000 },
3002                 { 0x0c, 0x37d0, 0x0820 },
3003                 { 0x1e, 0x0000, 0x0001 },
3004                 { 0x19, 0x8021, 0x0000 },
3005                 { 0x1e, 0x0000, 0x2000 },
3006                 { 0x0d, 0x0100, 0x0200 },
3007                 { 0x00, 0x0000, 0x0080 },
3008                 { 0x06, 0x0000, 0x0010 },
3009                 { 0x04, 0x0000, 0x0010 },
3010                 { 0x1d, 0x0000, 0x4000 },
3011         };
3012
3013         rtl_hw_start_8168g(tp);
3014
3015         /* disable aspm and clock request before access ephy */
3016         rtl_hw_aspm_clkreq_enable(tp, false);
3017         rtl_ephy_init(tp, e_info_8411_2);
3018
3019         /* The following Realtek-provided magic fixes an issue with the RX unit
3020          * getting confused after the PHY having been powered-down.
3021          */
3022         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3023         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3024         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3025         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3026         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3027         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3028         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3029         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3030         mdelay(3);
3031         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3032
3033         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3034         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3035         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3036         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3037         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3038         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3039         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3040         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3041         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3042         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3043         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3044         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3045         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3046         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3047         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3048         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3049         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3050         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3051         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3052         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3053         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3054         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3055         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3056         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3057         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3058         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3059         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3060         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3061         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3062         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3063         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3064         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3065         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3066         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3067         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3068         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3069         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3070         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3071         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3072         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3073         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3074         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3075         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3076         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3077         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3078         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3079         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3080         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3081         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3082         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3083         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3084         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3085         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3086         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3087         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3088         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3089         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3090         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3091         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3092         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3093         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3094         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3095         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3096         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3097         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3098         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3099         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3100         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3101         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3102         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3103         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3104         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3105         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3106         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3107         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3108         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3109         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3110         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3111         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3112         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3113         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3114         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3115         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3116         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3117         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3118         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3119         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3120         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3121         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3122         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3123         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3124         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3125         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3126         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3127         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3128         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3129         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3130         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3131         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3132         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3133         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3134         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3135         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3136         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3137         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3138         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3139         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3140         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3141         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3142         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3143         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3144
3145         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3146
3147         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3148         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3149         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3150         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3151         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3152         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3153         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3154
3155         rtl_hw_aspm_clkreq_enable(tp, true);
3156 }
3157
3158 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3159 {
3160         static const struct ephy_info e_info_8168h_1[] = {
3161                 { 0x1e, 0x0800, 0x0001 },
3162                 { 0x1d, 0x0000, 0x0800 },
3163                 { 0x05, 0xffff, 0x2089 },
3164                 { 0x06, 0xffff, 0x5881 },
3165                 { 0x04, 0xffff, 0x854a },
3166                 { 0x01, 0xffff, 0x068b }
3167         };
3168         int rg_saw_cnt;
3169
3170         /* disable aspm and clock request before access ephy */
3171         rtl_hw_aspm_clkreq_enable(tp, false);
3172         rtl_ephy_init(tp, e_info_8168h_1);
3173
3174         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3175         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3176
3177         rtl_set_def_aspm_entry_latency(tp);
3178
3179         rtl_reset_packet_filter(tp);
3180
3181         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3182
3183         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3184
3185         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3186
3187         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3188         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3189
3190         rtl8168_config_eee_mac(tp);
3191
3192         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3193         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3194
3195         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3196
3197         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3198
3199         rtl_pcie_state_l2l3_disable(tp);
3200
3201         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3202         if (rg_saw_cnt > 0) {
3203                 u16 sw_cnt_1ms_ini;
3204
3205                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3206                 sw_cnt_1ms_ini &= 0x0fff;
3207                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3208         }
3209
3210         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3211         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3212         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3213         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3214
3215         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3216         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3217         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3218         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3219
3220         rtl_hw_aspm_clkreq_enable(tp, true);
3221 }
3222
3223 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3224 {
3225         rtl8168ep_stop_cmac(tp);
3226
3227         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3228         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3229
3230         rtl_set_def_aspm_entry_latency(tp);
3231
3232         rtl_reset_packet_filter(tp);
3233
3234         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3235
3236         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3237
3238         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3239         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3240
3241         rtl8168_config_eee_mac(tp);
3242
3243         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3244
3245         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3246
3247         rtl_pcie_state_l2l3_disable(tp);
3248 }
3249
3250 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3251 {
3252         static const struct ephy_info e_info_8168ep_1[] = {
3253                 { 0x00, 0xffff, 0x10ab },
3254                 { 0x06, 0xffff, 0xf030 },
3255                 { 0x08, 0xffff, 0x2006 },
3256                 { 0x0d, 0xffff, 0x1666 },
3257                 { 0x0c, 0x3ff0, 0x0000 }
3258         };
3259
3260         /* disable aspm and clock request before access ephy */
3261         rtl_hw_aspm_clkreq_enable(tp, false);
3262         rtl_ephy_init(tp, e_info_8168ep_1);
3263
3264         rtl_hw_start_8168ep(tp);
3265
3266         rtl_hw_aspm_clkreq_enable(tp, true);
3267 }
3268
3269 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3270 {
3271         static const struct ephy_info e_info_8168ep_2[] = {
3272                 { 0x00, 0xffff, 0x10a3 },
3273                 { 0x19, 0xffff, 0xfc00 },
3274                 { 0x1e, 0xffff, 0x20ea }
3275         };
3276
3277         /* disable aspm and clock request before access ephy */
3278         rtl_hw_aspm_clkreq_enable(tp, false);
3279         rtl_ephy_init(tp, e_info_8168ep_2);
3280
3281         rtl_hw_start_8168ep(tp);
3282
3283         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3284         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3285
3286         rtl_hw_aspm_clkreq_enable(tp, true);
3287 }
3288
3289 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3290 {
3291         static const struct ephy_info e_info_8168ep_3[] = {
3292                 { 0x00, 0x0000, 0x0080 },
3293                 { 0x0d, 0x0100, 0x0200 },
3294                 { 0x19, 0x8021, 0x0000 },
3295                 { 0x1e, 0x0000, 0x2000 },
3296         };
3297
3298         /* disable aspm and clock request before access ephy */
3299         rtl_hw_aspm_clkreq_enable(tp, false);
3300         rtl_ephy_init(tp, e_info_8168ep_3);
3301
3302         rtl_hw_start_8168ep(tp);
3303
3304         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3305         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3306
3307         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3308         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3309         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3310
3311         rtl_hw_aspm_clkreq_enable(tp, true);
3312 }
3313
3314 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3315 {
3316         static const struct ephy_info e_info_8117[] = {
3317                 { 0x19, 0x0040, 0x1100 },
3318                 { 0x59, 0x0040, 0x1100 },
3319         };
3320         int rg_saw_cnt;
3321
3322         rtl8168ep_stop_cmac(tp);
3323
3324         /* disable aspm and clock request before access ephy */
3325         rtl_hw_aspm_clkreq_enable(tp, false);
3326         rtl_ephy_init(tp, e_info_8117);
3327
3328         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3329         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3330
3331         rtl_set_def_aspm_entry_latency(tp);
3332
3333         rtl_reset_packet_filter(tp);
3334
3335         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3336
3337         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3338
3339         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3340
3341         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3342         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3343
3344         rtl8168_config_eee_mac(tp);
3345
3346         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3347         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3348
3349         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3350
3351         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3352
3353         rtl_pcie_state_l2l3_disable(tp);
3354
3355         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3356         if (rg_saw_cnt > 0) {
3357                 u16 sw_cnt_1ms_ini;
3358
3359                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3360                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3361         }
3362
3363         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3364         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3365         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3366         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3367
3368         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3369         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3370         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3371         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3372
3373         /* firmware is for MAC only */
3374         r8169_apply_firmware(tp);
3375
3376         rtl_hw_aspm_clkreq_enable(tp, true);
3377 }
3378
3379 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3380 {
3381         static const struct ephy_info e_info_8102e_1[] = {
3382                 { 0x01, 0, 0x6e65 },
3383                 { 0x02, 0, 0x091f },
3384                 { 0x03, 0, 0xc2f9 },
3385                 { 0x06, 0, 0xafb5 },
3386                 { 0x07, 0, 0x0e00 },
3387                 { 0x19, 0, 0xec80 },
3388                 { 0x01, 0, 0x2e65 },
3389                 { 0x01, 0, 0x6e65 }
3390         };
3391         u8 cfg1;
3392
3393         rtl_set_def_aspm_entry_latency(tp);
3394
3395         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3396
3397         RTL_W8(tp, Config1,
3398                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3399         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3400
3401         cfg1 = RTL_R8(tp, Config1);
3402         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3403                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3404
3405         rtl_ephy_init(tp, e_info_8102e_1);
3406 }
3407
3408 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3409 {
3410         rtl_set_def_aspm_entry_latency(tp);
3411
3412         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3413         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3414 }
3415
3416 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3417 {
3418         rtl_hw_start_8102e_2(tp);
3419
3420         rtl_ephy_write(tp, 0x03, 0xc2f9);
3421 }
3422
3423 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3424 {
3425         static const struct ephy_info e_info_8401[] = {
3426                 { 0x01, 0xffff, 0x6fe5 },
3427                 { 0x03, 0xffff, 0x0599 },
3428                 { 0x06, 0xffff, 0xaf25 },
3429                 { 0x07, 0xffff, 0x8e68 },
3430         };
3431
3432         rtl_ephy_init(tp, e_info_8401);
3433         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3434 }
3435
3436 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3437 {
3438         static const struct ephy_info e_info_8105e_1[] = {
3439                 { 0x07, 0, 0x4000 },
3440                 { 0x19, 0, 0x0200 },
3441                 { 0x19, 0, 0x0020 },
3442                 { 0x1e, 0, 0x2000 },
3443                 { 0x03, 0, 0x0001 },
3444                 { 0x19, 0, 0x0100 },
3445                 { 0x19, 0, 0x0004 },
3446                 { 0x0a, 0, 0x0020 }
3447         };
3448
3449         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3450         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3451
3452         /* Disable Early Tally Counter */
3453         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3454
3455         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3456         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3457
3458         rtl_ephy_init(tp, e_info_8105e_1);
3459
3460         rtl_pcie_state_l2l3_disable(tp);
3461 }
3462
3463 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3464 {
3465         rtl_hw_start_8105e_1(tp);
3466         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3467 }
3468
3469 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3470 {
3471         static const struct ephy_info e_info_8402[] = {
3472                 { 0x19, 0xffff, 0xff64 },
3473                 { 0x1e, 0, 0x4000 }
3474         };
3475
3476         rtl_set_def_aspm_entry_latency(tp);
3477
3478         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3479         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3480
3481         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3482
3483         rtl_ephy_init(tp, e_info_8402);
3484
3485         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3486         rtl_reset_packet_filter(tp);
3487         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3488         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3489         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3490
3491         /* disable EEE */
3492         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3493
3494         rtl_pcie_state_l2l3_disable(tp);
3495 }
3496
3497 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3498 {
3499         rtl_hw_aspm_clkreq_enable(tp, false);
3500
3501         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3502         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3503
3504         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3505         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3506         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3507
3508         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3509         rtl_set_aspm_entry_latency(tp, 0x2f);
3510
3511         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3512
3513         /* disable EEE */
3514         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3515
3516         rtl_pcie_state_l2l3_disable(tp);
3517         rtl_hw_aspm_clkreq_enable(tp, true);
3518 }
3519
3520 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3521 {
3522         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3523 }
3524
3525 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3526 {
3527         rtl_pcie_state_l2l3_disable(tp);
3528
3529         RTL_W16(tp, 0x382, 0x221b);
3530         RTL_W8(tp, 0x4500, 0);
3531         RTL_W16(tp, 0x4800, 0);
3532
3533         /* disable UPS */
3534         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3535
3536         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3537
3538         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3539         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3540
3541         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3542         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3543         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3544
3545         /* disable new tx descriptor format */
3546         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3547
3548         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3549                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3550         else
3551                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3552
3553         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3554                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3555         else
3556                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3557
3558         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3559         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3560         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3561         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3562         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3563         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3564         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3565         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3566         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3567
3568         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3569         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3570         udelay(1);
3571         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3572         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3573
3574         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3575
3576         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3577
3578         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3579                 rtl8125b_config_eee_mac(tp);
3580         else
3581                 rtl8125a_config_eee_mac(tp);
3582
3583         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3584         udelay(10);
3585 }
3586
3587 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3588 {
3589         static const struct ephy_info e_info_8125a_1[] = {
3590                 { 0x01, 0xffff, 0xa812 },
3591                 { 0x09, 0xffff, 0x520c },
3592                 { 0x04, 0xffff, 0xd000 },
3593                 { 0x0d, 0xffff, 0xf702 },
3594                 { 0x0a, 0xffff, 0x8653 },
3595                 { 0x06, 0xffff, 0x001e },
3596                 { 0x08, 0xffff, 0x3595 },
3597                 { 0x20, 0xffff, 0x9455 },
3598                 { 0x21, 0xffff, 0x99ff },
3599                 { 0x02, 0xffff, 0x6046 },
3600                 { 0x29, 0xffff, 0xfe00 },
3601                 { 0x23, 0xffff, 0xab62 },
3602
3603                 { 0x41, 0xffff, 0xa80c },
3604                 { 0x49, 0xffff, 0x520c },
3605                 { 0x44, 0xffff, 0xd000 },
3606                 { 0x4d, 0xffff, 0xf702 },
3607                 { 0x4a, 0xffff, 0x8653 },
3608                 { 0x46, 0xffff, 0x001e },
3609                 { 0x48, 0xffff, 0x3595 },
3610                 { 0x60, 0xffff, 0x9455 },
3611                 { 0x61, 0xffff, 0x99ff },
3612                 { 0x42, 0xffff, 0x6046 },
3613                 { 0x69, 0xffff, 0xfe00 },
3614                 { 0x63, 0xffff, 0xab62 },
3615         };
3616
3617         rtl_set_def_aspm_entry_latency(tp);
3618
3619         /* disable aspm and clock request before access ephy */
3620         rtl_hw_aspm_clkreq_enable(tp, false);
3621         rtl_ephy_init(tp, e_info_8125a_1);
3622
3623         rtl_hw_start_8125_common(tp);
3624         rtl_hw_aspm_clkreq_enable(tp, true);
3625 }
3626
3627 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3628 {
3629         static const struct ephy_info e_info_8125a_2[] = {
3630                 { 0x04, 0xffff, 0xd000 },
3631                 { 0x0a, 0xffff, 0x8653 },
3632                 { 0x23, 0xffff, 0xab66 },
3633                 { 0x20, 0xffff, 0x9455 },
3634                 { 0x21, 0xffff, 0x99ff },
3635                 { 0x29, 0xffff, 0xfe04 },
3636
3637                 { 0x44, 0xffff, 0xd000 },
3638                 { 0x4a, 0xffff, 0x8653 },
3639                 { 0x63, 0xffff, 0xab66 },
3640                 { 0x60, 0xffff, 0x9455 },
3641                 { 0x61, 0xffff, 0x99ff },
3642                 { 0x69, 0xffff, 0xfe04 },
3643         };
3644
3645         rtl_set_def_aspm_entry_latency(tp);
3646
3647         /* disable aspm and clock request before access ephy */
3648         rtl_hw_aspm_clkreq_enable(tp, false);
3649         rtl_ephy_init(tp, e_info_8125a_2);
3650
3651         rtl_hw_start_8125_common(tp);
3652         rtl_hw_aspm_clkreq_enable(tp, true);
3653 }
3654
3655 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3656 {
3657         static const struct ephy_info e_info_8125b[] = {
3658                 { 0x0b, 0xffff, 0xa908 },
3659                 { 0x1e, 0xffff, 0x20eb },
3660                 { 0x4b, 0xffff, 0xa908 },
3661                 { 0x5e, 0xffff, 0x20eb },
3662                 { 0x22, 0x0030, 0x0020 },
3663                 { 0x62, 0x0030, 0x0020 },
3664         };
3665
3666         rtl_set_def_aspm_entry_latency(tp);
3667         rtl_hw_aspm_clkreq_enable(tp, false);
3668
3669         rtl_ephy_init(tp, e_info_8125b);
3670         rtl_hw_start_8125_common(tp);
3671
3672         rtl_hw_aspm_clkreq_enable(tp, true);
3673 }
3674
3675 static void rtl_hw_config(struct rtl8169_private *tp)
3676 {
3677         static const rtl_generic_fct hw_configs[] = {
3678                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3679                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3680                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3681                 [RTL_GIGA_MAC_VER_10] = NULL,
3682                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3683                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3684                 [RTL_GIGA_MAC_VER_13] = NULL,
3685                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3686                 [RTL_GIGA_MAC_VER_16] = NULL,
3687                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3688                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3689                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3690                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3691                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3692                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3693                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3694                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3695                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3696                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3697                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3698                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3699                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3700                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3701                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3702                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3703                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3704                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3705                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3706                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3707                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3708                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3709                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3710                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3711                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3712                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3713                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3714                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3715                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3716                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3717                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3718                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3719                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3720                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3721                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3722                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3723                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3724                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3725                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3726         };
3727
3728         if (hw_configs[tp->mac_version])
3729                 hw_configs[tp->mac_version](tp);
3730 }
3731
3732 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3733 {
3734         int i;
3735
3736         /* disable interrupt coalescing */
3737         for (i = 0xa00; i < 0xb00; i += 4)
3738                 RTL_W32(tp, i, 0);
3739
3740         rtl_hw_config(tp);
3741 }
3742
3743 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3744 {
3745         if (rtl_is_8168evl_up(tp))
3746                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3747         else
3748                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3749
3750         rtl_hw_config(tp);
3751
3752         /* disable interrupt coalescing */
3753         RTL_W16(tp, IntrMitigate, 0x0000);
3754 }
3755
3756 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3757 {
3758         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3759
3760         tp->cp_cmd |= PCIMulRW;
3761
3762         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3763             tp->mac_version == RTL_GIGA_MAC_VER_03)
3764                 tp->cp_cmd |= EnAnaPLL;
3765
3766         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3767
3768         rtl8169_set_magic_reg(tp);
3769
3770         /* disable interrupt coalescing */
3771         RTL_W16(tp, IntrMitigate, 0x0000);
3772 }
3773
3774 static void rtl_hw_start(struct  rtl8169_private *tp)
3775 {
3776         rtl_unlock_config_regs(tp);
3777
3778         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3779
3780         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3781                 rtl_hw_start_8169(tp);
3782         else if (rtl_is_8125(tp))
3783                 rtl_hw_start_8125(tp);
3784         else
3785                 rtl_hw_start_8168(tp);
3786
3787         rtl_enable_exit_l1(tp);
3788         rtl_set_rx_max_size(tp);
3789         rtl_set_rx_tx_desc_registers(tp);
3790         rtl_lock_config_regs(tp);
3791
3792         rtl_jumbo_config(tp);
3793
3794         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3795         rtl_pci_commit(tp);
3796
3797         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3798         rtl_init_rxcfg(tp);
3799         rtl_set_tx_config_registers(tp);
3800         rtl_set_rx_config_features(tp, tp->dev->features);
3801         rtl_set_rx_mode(tp->dev);
3802         rtl_irq_enable(tp);
3803 }
3804
3805 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3806 {
3807         struct rtl8169_private *tp = netdev_priv(dev);
3808
3809         dev->mtu = new_mtu;
3810         netdev_update_features(dev);
3811         rtl_jumbo_config(tp);
3812
3813         switch (tp->mac_version) {
3814         case RTL_GIGA_MAC_VER_61:
3815         case RTL_GIGA_MAC_VER_63:
3816                 rtl8125_set_eee_txidle_timer(tp);
3817                 break;
3818         default:
3819                 break;
3820         }
3821
3822         return 0;
3823 }
3824
3825 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3826 {
3827         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3828
3829         desc->opts2 = 0;
3830         /* Force memory writes to complete before releasing descriptor */
3831         dma_wmb();
3832         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3833 }
3834
3835 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3836                                           struct RxDesc *desc)
3837 {
3838         struct device *d = tp_to_dev(tp);
3839         int node = dev_to_node(d);
3840         dma_addr_t mapping;
3841         struct page *data;
3842
3843         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3844         if (!data)
3845                 return NULL;
3846
3847         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3848         if (unlikely(dma_mapping_error(d, mapping))) {
3849                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3850                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3851                 return NULL;
3852         }
3853
3854         desc->addr = cpu_to_le64(mapping);
3855         rtl8169_mark_to_asic(desc);
3856
3857         return data;
3858 }
3859
3860 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3861 {
3862         int i;
3863
3864         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3865                 dma_unmap_page(tp_to_dev(tp),
3866                                le64_to_cpu(tp->RxDescArray[i].addr),
3867                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3868                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3869                 tp->Rx_databuff[i] = NULL;
3870                 tp->RxDescArray[i].addr = 0;
3871                 tp->RxDescArray[i].opts1 = 0;
3872         }
3873 }
3874
3875 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3876 {
3877         int i;
3878
3879         for (i = 0; i < NUM_RX_DESC; i++) {
3880                 struct page *data;
3881
3882                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3883                 if (!data) {
3884                         rtl8169_rx_clear(tp);
3885                         return -ENOMEM;
3886                 }
3887                 tp->Rx_databuff[i] = data;
3888         }
3889
3890         /* mark as last descriptor in the ring */
3891         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3892
3893         return 0;
3894 }
3895
3896 static int rtl8169_init_ring(struct rtl8169_private *tp)
3897 {
3898         rtl8169_init_ring_indexes(tp);
3899
3900         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3901         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3902
3903         return rtl8169_rx_fill(tp);
3904 }
3905
3906 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3907 {
3908         struct ring_info *tx_skb = tp->tx_skb + entry;
3909         struct TxDesc *desc = tp->TxDescArray + entry;
3910
3911         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3912                          DMA_TO_DEVICE);
3913         memset(desc, 0, sizeof(*desc));
3914         memset(tx_skb, 0, sizeof(*tx_skb));
3915 }
3916
3917 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3918                                    unsigned int n)
3919 {
3920         unsigned int i;
3921
3922         for (i = 0; i < n; i++) {
3923                 unsigned int entry = (start + i) % NUM_TX_DESC;
3924                 struct ring_info *tx_skb = tp->tx_skb + entry;
3925                 unsigned int len = tx_skb->len;
3926
3927                 if (len) {
3928                         struct sk_buff *skb = tx_skb->skb;
3929
3930                         rtl8169_unmap_tx_skb(tp, entry);
3931                         if (skb)
3932                                 dev_consume_skb_any(skb);
3933                 }
3934         }
3935 }
3936
3937 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3938 {
3939         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3940         netdev_reset_queue(tp->dev);
3941 }
3942
3943 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3944 {
3945         napi_disable(&tp->napi);
3946
3947         /* Give a racing hard_start_xmit a few cycles to complete. */
3948         synchronize_net();
3949
3950         /* Disable interrupts */
3951         rtl8169_irq_mask_and_ack(tp);
3952
3953         rtl_rx_close(tp);
3954
3955         if (going_down && tp->dev->wol_enabled)
3956                 goto no_reset;
3957
3958         switch (tp->mac_version) {
3959         case RTL_GIGA_MAC_VER_28:
3960         case RTL_GIGA_MAC_VER_31:
3961                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3962                 break;
3963         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3964                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3965                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3966                 break;
3967         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3968                 rtl_enable_rxdvgate(tp);
3969                 fsleep(2000);
3970                 break;
3971         default:
3972                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3973                 fsleep(100);
3974                 break;
3975         }
3976
3977         rtl_hw_reset(tp);
3978 no_reset:
3979         rtl8169_tx_clear(tp);
3980         rtl8169_init_ring_indexes(tp);
3981 }
3982
3983 static void rtl_reset_work(struct rtl8169_private *tp)
3984 {
3985         int i;
3986
3987         netif_stop_queue(tp->dev);
3988
3989         rtl8169_cleanup(tp, false);
3990
3991         for (i = 0; i < NUM_RX_DESC; i++)
3992                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3993
3994         napi_enable(&tp->napi);
3995         rtl_hw_start(tp);
3996 }
3997
3998 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3999 {
4000         struct rtl8169_private *tp = netdev_priv(dev);
4001
4002         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4003 }
4004
4005 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4006                           void *addr, unsigned int entry, bool desc_own)
4007 {
4008         struct TxDesc *txd = tp->TxDescArray + entry;
4009         struct device *d = tp_to_dev(tp);
4010         dma_addr_t mapping;
4011         u32 opts1;
4012         int ret;
4013
4014         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4015         ret = dma_mapping_error(d, mapping);
4016         if (unlikely(ret)) {
4017                 if (net_ratelimit())
4018                         netdev_err(tp->dev, "Failed to map TX data!\n");
4019                 return ret;
4020         }
4021
4022         txd->addr = cpu_to_le64(mapping);
4023         txd->opts2 = cpu_to_le32(opts[1]);
4024
4025         opts1 = opts[0] | len;
4026         if (entry == NUM_TX_DESC - 1)
4027                 opts1 |= RingEnd;
4028         if (desc_own)
4029                 opts1 |= DescOwn;
4030         txd->opts1 = cpu_to_le32(opts1);
4031
4032         tp->tx_skb[entry].len = len;
4033
4034         return 0;
4035 }
4036
4037 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4038                               const u32 *opts, unsigned int entry)
4039 {
4040         struct skb_shared_info *info = skb_shinfo(skb);
4041         unsigned int cur_frag;
4042
4043         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4044                 const skb_frag_t *frag = info->frags + cur_frag;
4045                 void *addr = skb_frag_address(frag);
4046                 u32 len = skb_frag_size(frag);
4047
4048                 entry = (entry + 1) % NUM_TX_DESC;
4049
4050                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4051                         goto err_out;
4052         }
4053
4054         return 0;
4055
4056 err_out:
4057         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4058         return -EIO;
4059 }
4060
4061 static bool rtl_skb_is_udp(struct sk_buff *skb)
4062 {
4063         int no = skb_network_offset(skb);
4064         struct ipv6hdr *i6h, _i6h;
4065         struct iphdr *ih, _ih;
4066
4067         switch (vlan_get_protocol(skb)) {
4068         case htons(ETH_P_IP):
4069                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4070                 return ih && ih->protocol == IPPROTO_UDP;
4071         case htons(ETH_P_IPV6):
4072                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4073                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4074         default:
4075                 return false;
4076         }
4077 }
4078
4079 #define RTL_MIN_PATCH_LEN       47
4080
4081 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4082 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4083                                             struct sk_buff *skb)
4084 {
4085         unsigned int padto = 0, len = skb->len;
4086
4087         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4088             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4089                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4090                                               skb_transport_header(skb);
4091
4092                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4093                     trans_data_len < RTL_MIN_PATCH_LEN) {
4094                         u16 dest = ntohs(udp_hdr(skb)->dest);
4095
4096                         /* dest is a standard PTP port */
4097                         if (dest == 319 || dest == 320)
4098                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4099                 }
4100
4101                 if (trans_data_len < sizeof(struct udphdr))
4102                         padto = max_t(unsigned int, padto,
4103                                       len + sizeof(struct udphdr) - trans_data_len);
4104         }
4105
4106         return padto;
4107 }
4108
4109 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4110                                            struct sk_buff *skb)
4111 {
4112         unsigned int padto;
4113
4114         padto = rtl8125_quirk_udp_padto(tp, skb);
4115
4116         switch (tp->mac_version) {
4117         case RTL_GIGA_MAC_VER_34:
4118         case RTL_GIGA_MAC_VER_60:
4119         case RTL_GIGA_MAC_VER_61:
4120         case RTL_GIGA_MAC_VER_63:
4121                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4122                 break;
4123         default:
4124                 break;
4125         }
4126
4127         return padto;
4128 }
4129
4130 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4131 {
4132         u32 mss = skb_shinfo(skb)->gso_size;
4133
4134         if (mss) {
4135                 opts[0] |= TD_LSO;
4136                 opts[0] |= mss << TD0_MSS_SHIFT;
4137         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4138                 const struct iphdr *ip = ip_hdr(skb);
4139
4140                 if (ip->protocol == IPPROTO_TCP)
4141                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4142                 else if (ip->protocol == IPPROTO_UDP)
4143                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4144                 else
4145                         WARN_ON_ONCE(1);
4146         }
4147 }
4148
4149 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4150                                 struct sk_buff *skb, u32 *opts)
4151 {
4152         u32 transport_offset = (u32)skb_transport_offset(skb);
4153         struct skb_shared_info *shinfo = skb_shinfo(skb);
4154         u32 mss = shinfo->gso_size;
4155
4156         if (mss) {
4157                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4158                         opts[0] |= TD1_GTSENV4;
4159                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4160                         if (skb_cow_head(skb, 0))
4161                                 return false;
4162
4163                         tcp_v6_gso_csum_prep(skb);
4164                         opts[0] |= TD1_GTSENV6;
4165                 } else {
4166                         WARN_ON_ONCE(1);
4167                 }
4168
4169                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4170                 opts[1] |= mss << TD1_MSS_SHIFT;
4171         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4172                 u8 ip_protocol;
4173
4174                 switch (vlan_get_protocol(skb)) {
4175                 case htons(ETH_P_IP):
4176                         opts[1] |= TD1_IPv4_CS;
4177                         ip_protocol = ip_hdr(skb)->protocol;
4178                         break;
4179
4180                 case htons(ETH_P_IPV6):
4181                         opts[1] |= TD1_IPv6_CS;
4182                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4183                         break;
4184
4185                 default:
4186                         ip_protocol = IPPROTO_RAW;
4187                         break;
4188                 }
4189
4190                 if (ip_protocol == IPPROTO_TCP)
4191                         opts[1] |= TD1_TCP_CS;
4192                 else if (ip_protocol == IPPROTO_UDP)
4193                         opts[1] |= TD1_UDP_CS;
4194                 else
4195                         WARN_ON_ONCE(1);
4196
4197                 opts[1] |= transport_offset << TCPHO_SHIFT;
4198         } else {
4199                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4200
4201                 /* skb_padto would free the skb on error */
4202                 return !__skb_put_padto(skb, padto, false);
4203         }
4204
4205         return true;
4206 }
4207
4208 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4209 {
4210         unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4211                                         - READ_ONCE(tp->cur_tx);
4212
4213         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4214         return slots_avail > MAX_SKB_FRAGS;
4215 }
4216
4217 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4218 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4219 {
4220         switch (tp->mac_version) {
4221         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4222         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4223                 return false;
4224         default:
4225                 return true;
4226         }
4227 }
4228
4229 static void rtl8169_doorbell(struct rtl8169_private *tp)
4230 {
4231         if (rtl_is_8125(tp))
4232                 RTL_W16(tp, TxPoll_8125, BIT(0));
4233         else
4234                 RTL_W8(tp, TxPoll, NPQ);
4235 }
4236
4237 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4238                                       struct net_device *dev)
4239 {
4240         unsigned int frags = skb_shinfo(skb)->nr_frags;
4241         struct rtl8169_private *tp = netdev_priv(dev);
4242         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4243         struct TxDesc *txd_first, *txd_last;
4244         bool stop_queue, door_bell;
4245         u32 opts[2];
4246
4247         if (unlikely(!rtl_tx_slots_avail(tp))) {
4248                 if (net_ratelimit())
4249                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4250                 goto err_stop_0;
4251         }
4252
4253         opts[1] = rtl8169_tx_vlan_tag(skb);
4254         opts[0] = 0;
4255
4256         if (!rtl_chip_supports_csum_v2(tp))
4257                 rtl8169_tso_csum_v1(skb, opts);
4258         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4259                 goto err_dma_0;
4260
4261         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4262                                     entry, false)))
4263                 goto err_dma_0;
4264
4265         txd_first = tp->TxDescArray + entry;
4266
4267         if (frags) {
4268                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4269                         goto err_dma_1;
4270                 entry = (entry + frags) % NUM_TX_DESC;
4271         }
4272
4273         txd_last = tp->TxDescArray + entry;
4274         txd_last->opts1 |= cpu_to_le32(LastFrag);
4275         tp->tx_skb[entry].skb = skb;
4276
4277         skb_tx_timestamp(skb);
4278
4279         /* Force memory writes to complete before releasing descriptor */
4280         dma_wmb();
4281
4282         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4283
4284         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4285
4286         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4287         smp_wmb();
4288
4289         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4290
4291         stop_queue = !rtl_tx_slots_avail(tp);
4292         if (unlikely(stop_queue)) {
4293                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4294                  * not miss a ring update when it notices a stopped queue.
4295                  */
4296                 smp_wmb();
4297                 netif_stop_queue(dev);
4298                 /* Sync with rtl_tx:
4299                  * - publish queue status and cur_tx ring index (write barrier)
4300                  * - refresh dirty_tx ring index (read barrier).
4301                  * May the current thread have a pessimistic view of the ring
4302                  * status and forget to wake up queue, a racing rtl_tx thread
4303                  * can't.
4304                  */
4305                 smp_mb__after_atomic();
4306                 if (rtl_tx_slots_avail(tp))
4307                         netif_start_queue(dev);
4308                 door_bell = true;
4309         }
4310
4311         if (door_bell)
4312                 rtl8169_doorbell(tp);
4313
4314         return NETDEV_TX_OK;
4315
4316 err_dma_1:
4317         rtl8169_unmap_tx_skb(tp, entry);
4318 err_dma_0:
4319         dev_kfree_skb_any(skb);
4320         dev->stats.tx_dropped++;
4321         return NETDEV_TX_OK;
4322
4323 err_stop_0:
4324         netif_stop_queue(dev);
4325         dev->stats.tx_dropped++;
4326         return NETDEV_TX_BUSY;
4327 }
4328
4329 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4330 {
4331         struct skb_shared_info *info = skb_shinfo(skb);
4332         unsigned int nr_frags = info->nr_frags;
4333
4334         if (!nr_frags)
4335                 return UINT_MAX;
4336
4337         return skb_frag_size(info->frags + nr_frags - 1);
4338 }
4339
4340 /* Workaround for hw issues with TSO on RTL8168evl */
4341 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4342                                             netdev_features_t features)
4343 {
4344         /* IPv4 header has options field */
4345         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4346             ip_hdrlen(skb) > sizeof(struct iphdr))
4347                 features &= ~NETIF_F_ALL_TSO;
4348
4349         /* IPv4 TCP header has options field */
4350         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4351                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4352                 features &= ~NETIF_F_ALL_TSO;
4353
4354         else if (rtl_last_frag_len(skb) <= 6)
4355                 features &= ~NETIF_F_ALL_TSO;
4356
4357         return features;
4358 }
4359
4360 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4361                                                 struct net_device *dev,
4362                                                 netdev_features_t features)
4363 {
4364         int transport_offset = skb_transport_offset(skb);
4365         struct rtl8169_private *tp = netdev_priv(dev);
4366
4367         if (skb_is_gso(skb)) {
4368                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4369                         features = rtl8168evl_fix_tso(skb, features);
4370
4371                 if (transport_offset > GTTCPHO_MAX &&
4372                     rtl_chip_supports_csum_v2(tp))
4373                         features &= ~NETIF_F_ALL_TSO;
4374         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4375                 /* work around hw bug on some chip versions */
4376                 if (skb->len < ETH_ZLEN)
4377                         features &= ~NETIF_F_CSUM_MASK;
4378
4379                 if (rtl_quirk_packet_padto(tp, skb))
4380                         features &= ~NETIF_F_CSUM_MASK;
4381
4382                 if (transport_offset > TCPHO_MAX &&
4383                     rtl_chip_supports_csum_v2(tp))
4384                         features &= ~NETIF_F_CSUM_MASK;
4385         }
4386
4387         return vlan_features_check(skb, features);
4388 }
4389
4390 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4391 {
4392         struct rtl8169_private *tp = netdev_priv(dev);
4393         struct pci_dev *pdev = tp->pci_dev;
4394         int pci_status_errs;
4395         u16 pci_cmd;
4396
4397         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4398
4399         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4400
4401         if (net_ratelimit())
4402                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4403                            pci_cmd, pci_status_errs);
4404
4405         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4406 }
4407
4408 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4409                    int budget)
4410 {
4411         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4412         struct sk_buff *skb;
4413
4414         dirty_tx = tp->dirty_tx;
4415
4416         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4417                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4418                 u32 status;
4419
4420                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4421                 if (status & DescOwn)
4422                         break;
4423
4424                 skb = tp->tx_skb[entry].skb;
4425                 rtl8169_unmap_tx_skb(tp, entry);
4426
4427                 if (skb) {
4428                         pkts_compl++;
4429                         bytes_compl += skb->len;
4430                         napi_consume_skb(skb, budget);
4431                 }
4432                 dirty_tx++;
4433         }
4434
4435         if (tp->dirty_tx != dirty_tx) {
4436                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4437                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4438
4439                 /* Sync with rtl8169_start_xmit:
4440                  * - publish dirty_tx ring index (write barrier)
4441                  * - refresh cur_tx ring index and queue status (read barrier)
4442                  * May the current thread miss the stopped queue condition,
4443                  * a racing xmit thread can only have a right view of the
4444                  * ring status.
4445                  */
4446                 smp_store_mb(tp->dirty_tx, dirty_tx);
4447                 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4448                         netif_wake_queue(dev);
4449                 /*
4450                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4451                  * too close. Let's kick an extra TxPoll request when a burst
4452                  * of start_xmit activity is detected (if it is not detected,
4453                  * it is slow enough). -- FR
4454                  * If skb is NULL then we come here again once a tx irq is
4455                  * triggered after the last fragment is marked transmitted.
4456                  */
4457                 if (tp->cur_tx != dirty_tx && skb)
4458                         rtl8169_doorbell(tp);
4459         }
4460 }
4461
4462 static inline int rtl8169_fragmented_frame(u32 status)
4463 {
4464         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4465 }
4466
4467 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4468 {
4469         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4470
4471         if (status == RxProtoTCP || status == RxProtoUDP)
4472                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4473         else
4474                 skb_checksum_none_assert(skb);
4475 }
4476
4477 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4478 {
4479         struct device *d = tp_to_dev(tp);
4480         int count;
4481
4482         for (count = 0; count < budget; count++, tp->cur_rx++) {
4483                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4484                 struct RxDesc *desc = tp->RxDescArray + entry;
4485                 struct sk_buff *skb;
4486                 const void *rx_buf;
4487                 dma_addr_t addr;
4488                 u32 status;
4489
4490                 status = le32_to_cpu(desc->opts1);
4491                 if (status & DescOwn)
4492                         break;
4493
4494                 /* This barrier is needed to keep us from reading
4495                  * any other fields out of the Rx descriptor until
4496                  * we know the status of DescOwn
4497                  */
4498                 dma_rmb();
4499
4500                 if (unlikely(status & RxRES)) {
4501                         if (net_ratelimit())
4502                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4503                                             status);
4504                         dev->stats.rx_errors++;
4505                         if (status & (RxRWT | RxRUNT))
4506                                 dev->stats.rx_length_errors++;
4507                         if (status & RxCRC)
4508                                 dev->stats.rx_crc_errors++;
4509
4510                         if (!(dev->features & NETIF_F_RXALL))
4511                                 goto release_descriptor;
4512                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4513                                 goto release_descriptor;
4514                 }
4515
4516                 pkt_size = status & GENMASK(13, 0);
4517                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4518                         pkt_size -= ETH_FCS_LEN;
4519
4520                 /* The driver does not support incoming fragmented frames.
4521                  * They are seen as a symptom of over-mtu sized frames.
4522                  */
4523                 if (unlikely(rtl8169_fragmented_frame(status))) {
4524                         dev->stats.rx_dropped++;
4525                         dev->stats.rx_length_errors++;
4526                         goto release_descriptor;
4527                 }
4528
4529                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4530                 if (unlikely(!skb)) {
4531                         dev->stats.rx_dropped++;
4532                         goto release_descriptor;
4533                 }
4534
4535                 addr = le64_to_cpu(desc->addr);
4536                 rx_buf = page_address(tp->Rx_databuff[entry]);
4537
4538                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4539                 prefetch(rx_buf);
4540                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4541                 skb->tail += pkt_size;
4542                 skb->len = pkt_size;
4543                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4544
4545                 rtl8169_rx_csum(skb, status);
4546                 skb->protocol = eth_type_trans(skb, dev);
4547
4548                 rtl8169_rx_vlan_tag(desc, skb);
4549
4550                 if (skb->pkt_type == PACKET_MULTICAST)
4551                         dev->stats.multicast++;
4552
4553                 napi_gro_receive(&tp->napi, skb);
4554
4555                 dev_sw_netstats_rx_add(dev, pkt_size);
4556 release_descriptor:
4557                 rtl8169_mark_to_asic(desc);
4558         }
4559
4560         return count;
4561 }
4562
4563 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4564 {
4565         struct rtl8169_private *tp = dev_instance;
4566         u32 status = rtl_get_events(tp);
4567
4568         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4569                 return IRQ_NONE;
4570
4571         if (unlikely(status & SYSErr)) {
4572                 rtl8169_pcierr_interrupt(tp->dev);
4573                 goto out;
4574         }
4575
4576         if (status & LinkChg)
4577                 phy_mac_interrupt(tp->phydev);
4578
4579         if (unlikely(status & RxFIFOOver &&
4580             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4581                 netif_stop_queue(tp->dev);
4582                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4583         }
4584
4585         if (napi_schedule_prep(&tp->napi)) {
4586                 rtl_irq_disable(tp);
4587                 __napi_schedule(&tp->napi);
4588         }
4589 out:
4590         rtl_ack_events(tp, status);
4591
4592         return IRQ_HANDLED;
4593 }
4594
4595 static void rtl_task(struct work_struct *work)
4596 {
4597         struct rtl8169_private *tp =
4598                 container_of(work, struct rtl8169_private, wk.work);
4599
4600         rtnl_lock();
4601
4602         if (!netif_running(tp->dev) ||
4603             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4604                 goto out_unlock;
4605
4606         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4607                 rtl_reset_work(tp);
4608                 netif_wake_queue(tp->dev);
4609         }
4610 out_unlock:
4611         rtnl_unlock();
4612 }
4613
4614 static int rtl8169_poll(struct napi_struct *napi, int budget)
4615 {
4616         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4617         struct net_device *dev = tp->dev;
4618         int work_done;
4619
4620         rtl_tx(dev, tp, budget);
4621
4622         work_done = rtl_rx(dev, tp, budget);
4623
4624         if (work_done < budget && napi_complete_done(napi, work_done))
4625                 rtl_irq_enable(tp);
4626
4627         return work_done;
4628 }
4629
4630 static void r8169_phylink_handler(struct net_device *ndev)
4631 {
4632         struct rtl8169_private *tp = netdev_priv(ndev);
4633
4634         if (netif_carrier_ok(ndev)) {
4635                 rtl_link_chg_patch(tp);
4636                 pm_request_resume(&tp->pci_dev->dev);
4637         } else {
4638                 pm_runtime_idle(&tp->pci_dev->dev);
4639         }
4640
4641         if (net_ratelimit())
4642                 phy_print_status(tp->phydev);
4643 }
4644
4645 static int r8169_phy_connect(struct rtl8169_private *tp)
4646 {
4647         struct phy_device *phydev = tp->phydev;
4648         phy_interface_t phy_mode;
4649         int ret;
4650
4651         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4652                    PHY_INTERFACE_MODE_MII;
4653
4654         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4655                                  phy_mode);
4656         if (ret)
4657                 return ret;
4658
4659         if (!tp->supports_gmii)
4660                 phy_set_max_speed(phydev, SPEED_100);
4661
4662         phy_attached_info(phydev);
4663
4664         return 0;
4665 }
4666
4667 static void rtl8169_down(struct rtl8169_private *tp)
4668 {
4669         /* Clear all task flags */
4670         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4671
4672         phy_stop(tp->phydev);
4673
4674         rtl8169_update_counters(tp);
4675
4676         pci_clear_master(tp->pci_dev);
4677         rtl_pci_commit(tp);
4678
4679         rtl8169_cleanup(tp, true);
4680
4681         rtl_prepare_power_down(tp);
4682 }
4683
4684 static void rtl8169_up(struct rtl8169_private *tp)
4685 {
4686         pci_set_master(tp->pci_dev);
4687         phy_init_hw(tp->phydev);
4688         phy_resume(tp->phydev);
4689         rtl8169_init_phy(tp);
4690         napi_enable(&tp->napi);
4691         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4692         rtl_reset_work(tp);
4693
4694         phy_start(tp->phydev);
4695 }
4696
4697 static int rtl8169_close(struct net_device *dev)
4698 {
4699         struct rtl8169_private *tp = netdev_priv(dev);
4700         struct pci_dev *pdev = tp->pci_dev;
4701
4702         pm_runtime_get_sync(&pdev->dev);
4703
4704         netif_stop_queue(dev);
4705         rtl8169_down(tp);
4706         rtl8169_rx_clear(tp);
4707
4708         cancel_work_sync(&tp->wk.work);
4709
4710         free_irq(pci_irq_vector(pdev, 0), tp);
4711
4712         phy_disconnect(tp->phydev);
4713
4714         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4715                           tp->RxPhyAddr);
4716         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4717                           tp->TxPhyAddr);
4718         tp->TxDescArray = NULL;
4719         tp->RxDescArray = NULL;
4720
4721         pm_runtime_put_sync(&pdev->dev);
4722
4723         return 0;
4724 }
4725
4726 #ifdef CONFIG_NET_POLL_CONTROLLER
4727 static void rtl8169_netpoll(struct net_device *dev)
4728 {
4729         struct rtl8169_private *tp = netdev_priv(dev);
4730
4731         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4732 }
4733 #endif
4734
4735 static int rtl_open(struct net_device *dev)
4736 {
4737         struct rtl8169_private *tp = netdev_priv(dev);
4738         struct pci_dev *pdev = tp->pci_dev;
4739         unsigned long irqflags;
4740         int retval = -ENOMEM;
4741
4742         pm_runtime_get_sync(&pdev->dev);
4743
4744         /*
4745          * Rx and Tx descriptors needs 256 bytes alignment.
4746          * dma_alloc_coherent provides more.
4747          */
4748         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4749                                              &tp->TxPhyAddr, GFP_KERNEL);
4750         if (!tp->TxDescArray)
4751                 goto out;
4752
4753         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4754                                              &tp->RxPhyAddr, GFP_KERNEL);
4755         if (!tp->RxDescArray)
4756                 goto err_free_tx_0;
4757
4758         retval = rtl8169_init_ring(tp);
4759         if (retval < 0)
4760                 goto err_free_rx_1;
4761
4762         rtl_request_firmware(tp);
4763
4764         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4765         retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4766                              irqflags, dev->name, tp);
4767         if (retval < 0)
4768                 goto err_release_fw_2;
4769
4770         retval = r8169_phy_connect(tp);
4771         if (retval)
4772                 goto err_free_irq;
4773
4774         rtl8169_up(tp);
4775         rtl8169_init_counter_offsets(tp);
4776         netif_start_queue(dev);
4777 out:
4778         pm_runtime_put_sync(&pdev->dev);
4779
4780         return retval;
4781
4782 err_free_irq:
4783         free_irq(pci_irq_vector(pdev, 0), tp);
4784 err_release_fw_2:
4785         rtl_release_firmware(tp);
4786         rtl8169_rx_clear(tp);
4787 err_free_rx_1:
4788         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4789                           tp->RxPhyAddr);
4790         tp->RxDescArray = NULL;
4791 err_free_tx_0:
4792         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4793                           tp->TxPhyAddr);
4794         tp->TxDescArray = NULL;
4795         goto out;
4796 }
4797
4798 static void
4799 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4800 {
4801         struct rtl8169_private *tp = netdev_priv(dev);
4802         struct pci_dev *pdev = tp->pci_dev;
4803         struct rtl8169_counters *counters = tp->counters;
4804
4805         pm_runtime_get_noresume(&pdev->dev);
4806
4807         netdev_stats_to_stats64(stats, &dev->stats);
4808         dev_fetch_sw_netstats(stats, dev->tstats);
4809
4810         /*
4811          * Fetch additional counter values missing in stats collected by driver
4812          * from tally counters.
4813          */
4814         if (pm_runtime_active(&pdev->dev))
4815                 rtl8169_update_counters(tp);
4816
4817         /*
4818          * Subtract values fetched during initalization.
4819          * See rtl8169_init_counter_offsets for a description why we do that.
4820          */
4821         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4822                 le64_to_cpu(tp->tc_offset.tx_errors);
4823         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4824                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4825         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4826                 le16_to_cpu(tp->tc_offset.tx_aborted);
4827         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4828                 le16_to_cpu(tp->tc_offset.rx_missed);
4829
4830         pm_runtime_put_noidle(&pdev->dev);
4831 }
4832
4833 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4834 {
4835         netif_device_detach(tp->dev);
4836
4837         if (netif_running(tp->dev))
4838                 rtl8169_down(tp);
4839 }
4840
4841 #ifdef CONFIG_PM
4842
4843 static int rtl8169_runtime_resume(struct device *dev)
4844 {
4845         struct rtl8169_private *tp = dev_get_drvdata(dev);
4846
4847         rtl_rar_set(tp, tp->dev->dev_addr);
4848         __rtl8169_set_wol(tp, tp->saved_wolopts);
4849
4850         if (tp->TxDescArray)
4851                 rtl8169_up(tp);
4852
4853         netif_device_attach(tp->dev);
4854
4855         return 0;
4856 }
4857
4858 static int __maybe_unused rtl8169_suspend(struct device *device)
4859 {
4860         struct rtl8169_private *tp = dev_get_drvdata(device);
4861
4862         rtnl_lock();
4863         rtl8169_net_suspend(tp);
4864         if (!device_may_wakeup(tp_to_dev(tp)))
4865                 clk_disable_unprepare(tp->clk);
4866         rtnl_unlock();
4867
4868         return 0;
4869 }
4870
4871 static int __maybe_unused rtl8169_resume(struct device *device)
4872 {
4873         struct rtl8169_private *tp = dev_get_drvdata(device);
4874
4875         if (!device_may_wakeup(tp_to_dev(tp)))
4876                 clk_prepare_enable(tp->clk);
4877
4878         /* Reportedly at least Asus X453MA truncates packets otherwise */
4879         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4880                 rtl_init_rxcfg(tp);
4881
4882         return rtl8169_runtime_resume(device);
4883 }
4884
4885 static int rtl8169_runtime_suspend(struct device *device)
4886 {
4887         struct rtl8169_private *tp = dev_get_drvdata(device);
4888
4889         if (!tp->TxDescArray) {
4890                 netif_device_detach(tp->dev);
4891                 return 0;
4892         }
4893
4894         rtnl_lock();
4895         __rtl8169_set_wol(tp, WAKE_PHY);
4896         rtl8169_net_suspend(tp);
4897         rtnl_unlock();
4898
4899         return 0;
4900 }
4901
4902 static int rtl8169_runtime_idle(struct device *device)
4903 {
4904         struct rtl8169_private *tp = dev_get_drvdata(device);
4905
4906         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4907                 pm_schedule_suspend(device, 10000);
4908
4909         return -EBUSY;
4910 }
4911
4912 static const struct dev_pm_ops rtl8169_pm_ops = {
4913         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4914         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4915                            rtl8169_runtime_idle)
4916 };
4917
4918 #endif /* CONFIG_PM */
4919
4920 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4921 {
4922         /* WoL fails with 8168b when the receiver is disabled. */
4923         switch (tp->mac_version) {
4924         case RTL_GIGA_MAC_VER_11:
4925         case RTL_GIGA_MAC_VER_12:
4926         case RTL_GIGA_MAC_VER_17:
4927                 pci_clear_master(tp->pci_dev);
4928
4929                 RTL_W8(tp, ChipCmd, CmdRxEnb);
4930                 rtl_pci_commit(tp);
4931                 break;
4932         default:
4933                 break;
4934         }
4935 }
4936
4937 static void rtl_shutdown(struct pci_dev *pdev)
4938 {
4939         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4940
4941         rtnl_lock();
4942         rtl8169_net_suspend(tp);
4943         rtnl_unlock();
4944
4945         /* Restore original MAC address */
4946         rtl_rar_set(tp, tp->dev->perm_addr);
4947
4948         if (system_state == SYSTEM_POWER_OFF) {
4949                 if (tp->saved_wolopts)
4950                         rtl_wol_shutdown_quirk(tp);
4951
4952                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4953                 pci_set_power_state(pdev, PCI_D3hot);
4954         }
4955 }
4956
4957 static void rtl_remove_one(struct pci_dev *pdev)
4958 {
4959         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4960
4961         if (pci_dev_run_wake(pdev))
4962                 pm_runtime_get_noresume(&pdev->dev);
4963
4964         unregister_netdev(tp->dev);
4965
4966         if (tp->dash_type != RTL_DASH_NONE)
4967                 rtl8168_driver_stop(tp);
4968
4969         rtl_release_firmware(tp);
4970
4971         /* restore original MAC address */
4972         rtl_rar_set(tp, tp->dev->perm_addr);
4973 }
4974
4975 static const struct net_device_ops rtl_netdev_ops = {
4976         .ndo_open               = rtl_open,
4977         .ndo_stop               = rtl8169_close,
4978         .ndo_get_stats64        = rtl8169_get_stats64,
4979         .ndo_start_xmit         = rtl8169_start_xmit,
4980         .ndo_features_check     = rtl8169_features_check,
4981         .ndo_tx_timeout         = rtl8169_tx_timeout,
4982         .ndo_validate_addr      = eth_validate_addr,
4983         .ndo_change_mtu         = rtl8169_change_mtu,
4984         .ndo_fix_features       = rtl8169_fix_features,
4985         .ndo_set_features       = rtl8169_set_features,
4986         .ndo_set_mac_address    = rtl_set_mac_address,
4987         .ndo_eth_ioctl          = phy_do_ioctl_running,
4988         .ndo_set_rx_mode        = rtl_set_rx_mode,
4989 #ifdef CONFIG_NET_POLL_CONTROLLER
4990         .ndo_poll_controller    = rtl8169_netpoll,
4991 #endif
4992
4993 };
4994
4995 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4996 {
4997         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4998
4999         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5000                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5001         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5002                 /* special workaround needed */
5003                 tp->irq_mask |= RxFIFOOver;
5004         else
5005                 tp->irq_mask |= RxOverflow;
5006 }
5007
5008 static int rtl_alloc_irq(struct rtl8169_private *tp)
5009 {
5010         unsigned int flags;
5011
5012         switch (tp->mac_version) {
5013         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5014                 rtl_unlock_config_regs(tp);
5015                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5016                 rtl_lock_config_regs(tp);
5017                 fallthrough;
5018         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5019                 flags = PCI_IRQ_LEGACY;
5020                 break;
5021         default:
5022                 flags = PCI_IRQ_ALL_TYPES;
5023                 break;
5024         }
5025
5026         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5027 }
5028
5029 static void rtl_read_mac_address(struct rtl8169_private *tp,
5030                                  u8 mac_addr[ETH_ALEN])
5031 {
5032         /* Get MAC address */
5033         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5034                 u32 value;
5035
5036                 value = rtl_eri_read(tp, 0xe0);
5037                 put_unaligned_le32(value, mac_addr);
5038                 value = rtl_eri_read(tp, 0xe4);
5039                 put_unaligned_le16(value, mac_addr + 4);
5040         } else if (rtl_is_8125(tp)) {
5041                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5042         }
5043 }
5044
5045 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5046 {
5047         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5048 }
5049
5050 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5051 {
5052         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5053 }
5054
5055 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5056 {
5057         struct rtl8169_private *tp = mii_bus->priv;
5058
5059         if (phyaddr > 0)
5060                 return -ENODEV;
5061
5062         return rtl_readphy(tp, phyreg);
5063 }
5064
5065 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5066                                 int phyreg, u16 val)
5067 {
5068         struct rtl8169_private *tp = mii_bus->priv;
5069
5070         if (phyaddr > 0)
5071                 return -ENODEV;
5072
5073         rtl_writephy(tp, phyreg, val);
5074
5075         return 0;
5076 }
5077
5078 static int r8169_mdio_register(struct rtl8169_private *tp)
5079 {
5080         struct pci_dev *pdev = tp->pci_dev;
5081         struct mii_bus *new_bus;
5082         int ret;
5083
5084         new_bus = devm_mdiobus_alloc(&pdev->dev);
5085         if (!new_bus)
5086                 return -ENOMEM;
5087
5088         new_bus->name = "r8169";
5089         new_bus->priv = tp;
5090         new_bus->parent = &pdev->dev;
5091         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5092         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5093                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5094
5095         new_bus->read = r8169_mdio_read_reg;
5096         new_bus->write = r8169_mdio_write_reg;
5097
5098         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5099         if (ret)
5100                 return ret;
5101
5102         tp->phydev = mdiobus_get_phy(new_bus, 0);
5103         if (!tp->phydev) {
5104                 return -ENODEV;
5105         } else if (!tp->phydev->drv) {
5106                 /* Most chip versions fail with the genphy driver.
5107                  * Therefore ensure that the dedicated PHY driver is loaded.
5108                  */
5109                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5110                         tp->phydev->phy_id);
5111                 return -EUNATCH;
5112         }
5113
5114         tp->phydev->mac_managed_pm = 1;
5115
5116         phy_support_asym_pause(tp->phydev);
5117
5118         /* PHY will be woken up in rtl_open() */
5119         phy_suspend(tp->phydev);
5120
5121         return 0;
5122 }
5123
5124 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5125 {
5126         rtl_enable_rxdvgate(tp);
5127
5128         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5129         msleep(1);
5130         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5131
5132         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5133         r8168g_wait_ll_share_fifo_ready(tp);
5134
5135         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5136         r8168g_wait_ll_share_fifo_ready(tp);
5137 }
5138
5139 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5140 {
5141         rtl_enable_rxdvgate(tp);
5142
5143         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5144         msleep(1);
5145         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5146
5147         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5148         r8168g_wait_ll_share_fifo_ready(tp);
5149
5150         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5151         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5152         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5153         r8168g_wait_ll_share_fifo_ready(tp);
5154 }
5155
5156 static void rtl_hw_initialize(struct rtl8169_private *tp)
5157 {
5158         switch (tp->mac_version) {
5159         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
5160                 rtl8168ep_stop_cmac(tp);
5161                 fallthrough;
5162         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5163                 rtl_hw_init_8168g(tp);
5164                 break;
5165         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5166                 rtl_hw_init_8125(tp);
5167                 break;
5168         default:
5169                 break;
5170         }
5171 }
5172
5173 static int rtl_jumbo_max(struct rtl8169_private *tp)
5174 {
5175         /* Non-GBit versions don't support jumbo frames */
5176         if (!tp->supports_gmii)
5177                 return 0;
5178
5179         switch (tp->mac_version) {
5180         /* RTL8169 */
5181         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5182                 return JUMBO_7K;
5183         /* RTL8168b */
5184         case RTL_GIGA_MAC_VER_11:
5185         case RTL_GIGA_MAC_VER_12:
5186         case RTL_GIGA_MAC_VER_17:
5187                 return JUMBO_4K;
5188         /* RTL8168c */
5189         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5190                 return JUMBO_6K;
5191         default:
5192                 return JUMBO_9K;
5193         }
5194 }
5195
5196 static void rtl_disable_clk(void *data)
5197 {
5198         clk_disable_unprepare(data);
5199 }
5200
5201 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5202 {
5203         struct device *d = tp_to_dev(tp);
5204         struct clk *clk;
5205         int rc;
5206
5207         clk = devm_clk_get(d, "ether_clk");
5208         if (IS_ERR(clk)) {
5209                 rc = PTR_ERR(clk);
5210                 if (rc == -ENOENT)
5211                         /* clk-core allows NULL (for suspend / resume) */
5212                         rc = 0;
5213                 else
5214                         dev_err_probe(d, rc, "failed to get clk\n");
5215         } else {
5216                 tp->clk = clk;
5217                 rc = clk_prepare_enable(clk);
5218                 if (rc)
5219                         dev_err(d, "failed to enable clk: %d\n", rc);
5220                 else
5221                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5222         }
5223
5224         return rc;
5225 }
5226
5227 static void rtl_init_mac_address(struct rtl8169_private *tp)
5228 {
5229         struct net_device *dev = tp->dev;
5230         u8 mac_addr[ETH_ALEN];
5231         int rc;
5232
5233         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5234         if (!rc)
5235                 goto done;
5236
5237         rtl_read_mac_address(tp, mac_addr);
5238         if (is_valid_ether_addr(mac_addr))
5239                 goto done;
5240
5241         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5242         if (is_valid_ether_addr(mac_addr))
5243                 goto done;
5244
5245         eth_hw_addr_random(dev);
5246         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5247 done:
5248         eth_hw_addr_set(dev, mac_addr);
5249         rtl_rar_set(tp, mac_addr);
5250 }
5251
5252 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5253 {
5254         struct rtl8169_private *tp;
5255         int jumbo_max, region, rc;
5256         enum mac_version chipset;
5257         struct net_device *dev;
5258         u16 xid;
5259
5260         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5261         if (!dev)
5262                 return -ENOMEM;
5263
5264         SET_NETDEV_DEV(dev, &pdev->dev);
5265         dev->netdev_ops = &rtl_netdev_ops;
5266         tp = netdev_priv(dev);
5267         tp->dev = dev;
5268         tp->pci_dev = pdev;
5269         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5270         tp->eee_adv = -1;
5271         tp->ocp_base = OCP_STD_PHY_BASE;
5272
5273         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5274                                                    struct pcpu_sw_netstats);
5275         if (!dev->tstats)
5276                 return -ENOMEM;
5277
5278         /* Get the *optional* external "ether_clk" used on some boards */
5279         rc = rtl_get_ether_clk(tp);
5280         if (rc)
5281                 return rc;
5282
5283         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5284         rc = pcim_enable_device(pdev);
5285         if (rc < 0) {
5286                 dev_err(&pdev->dev, "enable failure\n");
5287                 return rc;
5288         }
5289
5290         if (pcim_set_mwi(pdev) < 0)
5291                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5292
5293         /* use first MMIO region */
5294         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5295         if (region < 0) {
5296                 dev_err(&pdev->dev, "no MMIO resource found\n");
5297                 return -ENODEV;
5298         }
5299
5300         /* check for weird/broken PCI region reporting */
5301         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5302                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5303                 return -ENODEV;
5304         }
5305
5306         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5307         if (rc < 0) {
5308                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5309                 return rc;
5310         }
5311
5312         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5313
5314         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5315
5316         /* Identify chip attached to board */
5317         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5318         if (chipset == RTL_GIGA_MAC_NONE) {
5319                 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5320                 return -ENODEV;
5321         }
5322
5323         tp->mac_version = chipset;
5324
5325         /* Disable ASPM L1 as that cause random device stop working
5326          * problems as well as full system hangs for some PCIe devices users.
5327          * Chips from RTL8168h partially have issues with L1.2, but seem
5328          * to work fine with L1 and L1.1.
5329          */
5330         if (tp->mac_version >= RTL_GIGA_MAC_VER_45)
5331                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
5332         else
5333                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5334         tp->aspm_manageable = !rc;
5335
5336         tp->dash_type = rtl_check_dash(tp);
5337
5338         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5339
5340         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5341             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5342                 dev->features |= NETIF_F_HIGHDMA;
5343
5344         rtl_init_rxcfg(tp);
5345
5346         rtl8169_irq_mask_and_ack(tp);
5347
5348         rtl_hw_initialize(tp);
5349
5350         rtl_hw_reset(tp);
5351
5352         rc = rtl_alloc_irq(tp);
5353         if (rc < 0) {
5354                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5355                 return rc;
5356         }
5357
5358         INIT_WORK(&tp->wk.work, rtl_task);
5359
5360         rtl_init_mac_address(tp);
5361
5362         dev->ethtool_ops = &rtl8169_ethtool_ops;
5363
5364         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5365
5366         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5367                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5368         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5369         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5370
5371         /*
5372          * Pretend we are using VLANs; This bypasses a nasty bug where
5373          * Interrupts stop flowing on high load on 8110SCd controllers.
5374          */
5375         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5376                 /* Disallow toggling */
5377                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5378
5379         if (rtl_chip_supports_csum_v2(tp))
5380                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5381
5382         dev->features |= dev->hw_features;
5383
5384         /* There has been a number of reports that using SG/TSO results in
5385          * tx timeouts. However for a lot of people SG/TSO works fine.
5386          * Therefore disable both features by default, but allow users to
5387          * enable them. Use at own risk!
5388          */
5389         if (rtl_chip_supports_csum_v2(tp)) {
5390                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5391                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5392                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5393         } else {
5394                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5395                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5396                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5397         }
5398
5399         dev->hw_features |= NETIF_F_RXALL;
5400         dev->hw_features |= NETIF_F_RXFCS;
5401
5402         /* configure chip for default features */
5403         rtl8169_set_features(dev, dev->features);
5404
5405         rtl_set_d3_pll_down(tp, true);
5406
5407         jumbo_max = rtl_jumbo_max(tp);
5408         if (jumbo_max)
5409                 dev->max_mtu = jumbo_max;
5410
5411         rtl_set_irq_mask(tp);
5412
5413         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5414
5415         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5416                                             &tp->counters_phys_addr,
5417                                             GFP_KERNEL);
5418         if (!tp->counters)
5419                 return -ENOMEM;
5420
5421         pci_set_drvdata(pdev, tp);
5422
5423         rc = r8169_mdio_register(tp);
5424         if (rc)
5425                 return rc;
5426
5427         rc = register_netdev(dev);
5428         if (rc)
5429                 return rc;
5430
5431         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5432                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5433                     pci_irq_vector(pdev, 0));
5434
5435         if (jumbo_max)
5436                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5437                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5438                             "ok" : "ko");
5439
5440         if (tp->dash_type != RTL_DASH_NONE) {
5441                 netdev_info(dev, "DASH enabled\n");
5442                 rtl8168_driver_start(tp);
5443         }
5444
5445         if (pci_dev_run_wake(pdev))
5446                 pm_runtime_put_sync(&pdev->dev);
5447
5448         return 0;
5449 }
5450
5451 static struct pci_driver rtl8169_pci_driver = {
5452         .name           = KBUILD_MODNAME,
5453         .id_table       = rtl8169_pci_tbl,
5454         .probe          = rtl_init_one,
5455         .remove         = rtl_remove_one,
5456         .shutdown       = rtl_shutdown,
5457         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5458 };
5459
5460 module_pci_driver(rtl8169_pci_driver);