drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #include "r8169_firmware.h"
  36
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64 #define MC_FILTER_LIMIT 32
  65
  66 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  73 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 enum mac_version {
  87         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  88         RTL_GIGA_MAC_VER_02,
  89         RTL_GIGA_MAC_VER_03,
  90         RTL_GIGA_MAC_VER_04,
  91         RTL_GIGA_MAC_VER_05,
  92         RTL_GIGA_MAC_VER_06,
  93         RTL_GIGA_MAC_VER_07,
  94         RTL_GIGA_MAC_VER_08,
  95         RTL_GIGA_MAC_VER_09,
  96         RTL_GIGA_MAC_VER_10,
  97         RTL_GIGA_MAC_VER_11,
  98         RTL_GIGA_MAC_VER_12,
  99         RTL_GIGA_MAC_VER_13,
 100         RTL_GIGA_MAC_VER_14,
 101         RTL_GIGA_MAC_VER_15,
 102         RTL_GIGA_MAC_VER_16,
 103         RTL_GIGA_MAC_VER_17,
 104         RTL_GIGA_MAC_VER_18,
 105         RTL_GIGA_MAC_VER_19,
 106         RTL_GIGA_MAC_VER_20,
 107         RTL_GIGA_MAC_VER_21,
 108         RTL_GIGA_MAC_VER_22,
 109         RTL_GIGA_MAC_VER_23,
 110         RTL_GIGA_MAC_VER_24,
 111         RTL_GIGA_MAC_VER_25,
 112         RTL_GIGA_MAC_VER_26,
 113         RTL_GIGA_MAC_VER_27,
 114         RTL_GIGA_MAC_VER_28,
 115         RTL_GIGA_MAC_VER_29,
 116         RTL_GIGA_MAC_VER_30,
 117         RTL_GIGA_MAC_VER_31,
 118         RTL_GIGA_MAC_VER_32,
 119         RTL_GIGA_MAC_VER_33,
 120         RTL_GIGA_MAC_VER_34,
 121         RTL_GIGA_MAC_VER_35,
 122         RTL_GIGA_MAC_VER_36,
 123         RTL_GIGA_MAC_VER_37,
 124         RTL_GIGA_MAC_VER_38,
 125         RTL_GIGA_MAC_VER_39,
 126         RTL_GIGA_MAC_VER_40,
 127         RTL_GIGA_MAC_VER_41,
 128         RTL_GIGA_MAC_VER_42,
 129         RTL_GIGA_MAC_VER_43,
 130         RTL_GIGA_MAC_VER_44,
 131         RTL_GIGA_MAC_VER_45,
 132         RTL_GIGA_MAC_VER_46,
 133         RTL_GIGA_MAC_VER_47,
 134         RTL_GIGA_MAC_VER_48,
 135         RTL_GIGA_MAC_VER_49,
 136         RTL_GIGA_MAC_VER_50,
 137         RTL_GIGA_MAC_VER_51,
 138         RTL_GIGA_MAC_NONE
 139 };
 140
 141 #define JUMBO_1K        ETH_DATA_LEN
 142 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 143 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 144 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 145 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 146
 147 static const struct {
 148         const char *name;
 149         const char *fw_name;
 150 } rtl_chip_infos[] = {
 151         /* PCI devices. */
 152         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 153         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 154         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 155         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 156         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 157         /* PCI-E devices. */
 158         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 159         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 160         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 161         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 163         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 164         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 166         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 167         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 169         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 170         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 172         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 173         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 175         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 176         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 177         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 178         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 179         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 181         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 182         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 184         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 185         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 186         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 187         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 188         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 189         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 190         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 191         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 192         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 193         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 194         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 195         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 196         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 197         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 198         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 199         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 200         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 201         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 202         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 203 };
 204
 205 static const struct pci_device_id rtl8169_pci_tbl[] = {
 206         { PCI_VDEVICE(REALTEK,  0x2502) },
 207         { PCI_VDEVICE(REALTEK,  0x2600) },
 208         { PCI_VDEVICE(REALTEK,  0x8129) },
 209         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 210         { PCI_VDEVICE(REALTEK,  0x8161) },
 211         { PCI_VDEVICE(REALTEK,  0x8167) },
 212         { PCI_VDEVICE(REALTEK,  0x8168) },
 213         { PCI_VDEVICE(NCUBE,    0x8168) },
 214         { PCI_VDEVICE(REALTEK,  0x8169) },
 215         { PCI_VENDOR_ID_DLINK,  0x4300,
 216                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 217         { PCI_VDEVICE(DLINK,    0x4300) },
 218         { PCI_VDEVICE(DLINK,    0x4302) },
 219         { PCI_VDEVICE(AT,       0xc107) },
 220         { PCI_VDEVICE(USR,      0x0116) },
 221         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 222         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 223         {}
 224 };
 225
 226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 227
 228 static struct {
 229         u32 msg_enable;
 230 } debug = { -1 };
 231
 232 enum rtl_registers {
 233         MAC0            = 0,    /* Ethernet hardware address. */
 234         MAC4            = 4,
 235         MAR0            = 8,    /* Multicast filter. */
 236         CounterAddrLow          = 0x10,
 237         CounterAddrHigh         = 0x14,
 238         TxDescStartAddrLow      = 0x20,
 239         TxDescStartAddrHigh     = 0x24,
 240         TxHDescStartAddrLow     = 0x28,
 241         TxHDescStartAddrHigh    = 0x2c,
 242         FLASH           = 0x30,
 243         ERSR            = 0x36,
 244         ChipCmd         = 0x37,
 245         TxPoll          = 0x38,
 246         IntrMask        = 0x3c,
 247         IntrStatus      = 0x3e,
 248
 249         TxConfig        = 0x40,
 250 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 251 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 252
 253         RxConfig        = 0x44,
 254 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 255 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 256 #define RXCFG_FIFO_SHIFT                13
 257                                         /* No threshold before first PCI xfer */
 258 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 259 #define RX_EARLY_OFF                    (1 << 11)
 260 #define RXCFG_DMA_SHIFT                 8
 261                                         /* Unlimited maximum PCI burst. */
 262 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 263
 264         RxMissed        = 0x4c,
 265         Cfg9346         = 0x50,
 266         Config0         = 0x51,
 267         Config1         = 0x52,
 268         Config2         = 0x53,
 269 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 270
 271         Config3         = 0x54,
 272         Config4         = 0x55,
 273         Config5         = 0x56,
 274         PHYAR           = 0x60,
 275         PHYstatus       = 0x6c,
 276         RxMaxSize       = 0xda,
 277         CPlusCmd        = 0xe0,
 278         IntrMitigate    = 0xe2,
 279
 280 #define RTL_COALESCE_MASK       0x0f
 281 #define RTL_COALESCE_SHIFT      4
 282 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 283 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 284
 285         RxDescAddrLow   = 0xe4,
 286         RxDescAddrHigh  = 0xe8,
 287         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 288
 289 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 290
 291         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 292
 293 #define TxPacketMax     (8064 >> 7)
 294 #define EarlySize       0x27
 295
 296         FuncEvent       = 0xf0,
 297         FuncEventMask   = 0xf4,
 298         FuncPresetState = 0xf8,
 299         IBCR0           = 0xf8,
 300         IBCR2           = 0xf9,
 301         IBIMR0          = 0xfa,
 302         IBISR0          = 0xfb,
 303         FuncForceEvent  = 0xfc,
 304 };
 305
 306 enum rtl8168_8101_registers {
 307         CSIDR                   = 0x64,
 308         CSIAR                   = 0x68,
 309 #define CSIAR_FLAG                      0x80000000
 310 #define CSIAR_WRITE_CMD                 0x80000000
 311 #define CSIAR_BYTE_ENABLE               0x0000f000
 312 #define CSIAR_ADDR_MASK                 0x00000fff
 313         PMCH                    = 0x6f,
 314         EPHYAR                  = 0x80,
 315 #define EPHYAR_FLAG                     0x80000000
 316 #define EPHYAR_WRITE_CMD                0x80000000
 317 #define EPHYAR_REG_MASK                 0x1f
 318 #define EPHYAR_REG_SHIFT                16
 319 #define EPHYAR_DATA_MASK                0xffff
 320         DLLPR                   = 0xd0,
 321 #define PFM_EN                          (1 << 6)
 322 #define TX_10M_PS_EN                    (1 << 7)
 323         DBG_REG                 = 0xd1,
 324 #define FIX_NAK_1                       (1 << 4)
 325 #define FIX_NAK_2                       (1 << 3)
 326         TWSI                    = 0xd2,
 327         MCU                     = 0xd3,
 328 #define NOW_IS_OOB                      (1 << 7)
 329 #define TX_EMPTY                        (1 << 5)
 330 #define RX_EMPTY                        (1 << 4)
 331 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 332 #define EN_NDP                          (1 << 3)
 333 #define EN_OOB_RESET                    (1 << 2)
 334 #define LINK_LIST_RDY                   (1 << 1)
 335         EFUSEAR                 = 0xdc,
 336 #define EFUSEAR_FLAG                    0x80000000
 337 #define EFUSEAR_WRITE_CMD               0x80000000
 338 #define EFUSEAR_READ_CMD                0x00000000
 339 #define EFUSEAR_REG_MASK                0x03ff
 340 #define EFUSEAR_REG_SHIFT               8
 341 #define EFUSEAR_DATA_MASK               0xff
 342         MISC_1                  = 0xf2,
 343 #define PFM_D3COLD_EN                   (1 << 6)
 344 };
 345
 346 enum rtl8168_registers {
 347         LED_FREQ                = 0x1a,
 348         EEE_LED                 = 0x1b,
 349         ERIDR                   = 0x70,
 350         ERIAR                   = 0x74,
 351 #define ERIAR_FLAG                      0x80000000
 352 #define ERIAR_WRITE_CMD                 0x80000000
 353 #define ERIAR_READ_CMD                  0x00000000
 354 #define ERIAR_ADDR_BYTE_ALIGN           4
 355 #define ERIAR_TYPE_SHIFT                16
 356 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 357 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 358 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 359 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 360 #define ERIAR_MASK_SHIFT                12
 361 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 362 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 363 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 364 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 365 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 366         EPHY_RXER_NUM           = 0x7c,
 367         OCPDR                   = 0xb0, /* OCP GPHY access */
 368 #define OCPDR_WRITE_CMD                 0x80000000
 369 #define OCPDR_READ_CMD                  0x00000000
 370 #define OCPDR_REG_MASK                  0x7f
 371 #define OCPDR_GPHY_REG_SHIFT            16
 372 #define OCPDR_DATA_MASK                 0xffff
 373         OCPAR                   = 0xb4,
 374 #define OCPAR_FLAG                      0x80000000
 375 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 376 #define OCPAR_GPHY_READ_CMD             0x0000f060
 377         GPHY_OCP                = 0xb8,
 378         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 379         MISC                    = 0xf0, /* 8168e only. */
 380 #define TXPLA_RST                       (1 << 29)
 381 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 382 #define PWM_EN                          (1 << 22)
 383 #define RXDV_GATED_EN                   (1 << 19)
 384 #define EARLY_TALLY_EN                  (1 << 16)
 385 };
 386
 387 enum rtl_register_content {
 388         /* InterruptStatusBits */
 389         SYSErr          = 0x8000,
 390         PCSTimeout      = 0x4000,
 391         SWInt           = 0x0100,
 392         TxDescUnavail   = 0x0080,
 393         RxFIFOOver      = 0x0040,
 394         LinkChg         = 0x0020,
 395         RxOverflow      = 0x0010,
 396         TxErr           = 0x0008,
 397         TxOK            = 0x0004,
 398         RxErr           = 0x0002,
 399         RxOK            = 0x0001,
 400
 401         /* RxStatusDesc */
 402         RxRWT   = (1 << 22),
 403         RxRES   = (1 << 21),
 404         RxRUNT  = (1 << 20),
 405         RxCRC   = (1 << 19),
 406
 407         /* ChipCmdBits */
 408         StopReq         = 0x80,
 409         CmdReset        = 0x10,
 410         CmdRxEnb        = 0x08,
 411         CmdTxEnb        = 0x04,
 412         RxBufEmpty      = 0x01,
 413
 414         /* TXPoll register p.5 */
 415         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 416         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 417         FSWInt          = 0x01,         /* Forced software interrupt */
 418
 419         /* Cfg9346Bits */
 420         Cfg9346_Lock    = 0x00,
 421         Cfg9346_Unlock  = 0xc0,
 422
 423         /* rx_mode_bits */
 424         AcceptErr       = 0x20,
 425         AcceptRunt      = 0x10,
 426         AcceptBroadcast = 0x08,
 427         AcceptMulticast = 0x04,
 428         AcceptMyPhys    = 0x02,
 429         AcceptAllPhys   = 0x01,
 430 #define RX_CONFIG_ACCEPT_MASK           0x3f
 431
 432         /* TxConfigBits */
 433         TxInterFrameGapShift = 24,
 434         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 435
 436         /* Config1 register p.24 */
 437         LEDS1           = (1 << 7),
 438         LEDS0           = (1 << 6),
 439         Speed_down      = (1 << 4),
 440         MEMMAP          = (1 << 3),
 441         IOMAP           = (1 << 2),
 442         VPD             = (1 << 1),
 443         PMEnable        = (1 << 0),     /* Power Management Enable */
 444
 445         /* Config2 register p. 25 */
 446         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 447         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 448         PCI_Clock_66MHz = 0x01,
 449         PCI_Clock_33MHz = 0x00,
 450
 451         /* Config3 register p.25 */
 452         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 453         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 454         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 455         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 456         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 457
 458         /* Config4 register */
 459         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 460
 461         /* Config5 register p.27 */
 462         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 463         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 464         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 465         Spi_en          = (1 << 3),
 466         LanWake         = (1 << 1),     /* LanWake enable/disable */
 467         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 468         ASPM_en         = (1 << 0),     /* ASPM enable */
 469
 470         /* CPlusCmd p.31 */
 471         EnableBist      = (1 << 15),    // 8168 8101
 472         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 473         Normal_mode     = (1 << 13),    // unused
 474         Force_half_dup  = (1 << 12),    // 8168 8101
 475         Force_rxflow_en = (1 << 11),    // 8168 8101
 476         Force_txflow_en = (1 << 10),    // 8168 8101
 477         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 478         ASF             = (1 << 8),     // 8168 8101
 479         PktCntrDisable  = (1 << 7),     // 8168 8101
 480         Mac_dbgo_sel    = 0x001c,       // 8168
 481         RxVlan          = (1 << 6),
 482         RxChkSum        = (1 << 5),
 483         PCIDAC          = (1 << 4),
 484         PCIMulRW        = (1 << 3),
 485 #define INTT_MASK       GENMASK(1, 0)
 486 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 487
 488         /* rtl8169_PHYstatus */
 489         TBI_Enable      = 0x80,
 490         TxFlowCtrl      = 0x40,
 491         RxFlowCtrl      = 0x20,
 492         _1000bpsF       = 0x10,
 493         _100bps         = 0x08,
 494         _10bps          = 0x04,
 495         LinkStatus      = 0x02,
 496         FullDup         = 0x01,
 497
 498         /* ResetCounterCommand */
 499         CounterReset    = 0x1,
 500
 501         /* DumpCounterCommand */
 502         CounterDump     = 0x8,
 503
 504         /* magic enable v2 */
 505         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 506 };
 507
 508 enum rtl_desc_bit {
 509         /* First doubleword. */
 510         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 511         RingEnd         = (1 << 30), /* End of descriptor ring */
 512         FirstFrag       = (1 << 29), /* First segment of a packet */
 513         LastFrag        = (1 << 28), /* Final segment of a packet */
 514 };
 515
 516 /* Generic case. */
 517 enum rtl_tx_desc_bit {
 518         /* First doubleword. */
 519         TD_LSO          = (1 << 27),            /* Large Send Offload */
 520 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 521
 522         /* Second doubleword. */
 523         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 524 };
 525
 526 /* 8169, 8168b and 810x except 8102e. */
 527 enum rtl_tx_desc_bit_0 {
 528         /* First doubleword. */
 529 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 530         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 531         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 532         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 533 };
 534
 535 /* 8102e, 8168c and beyond. */
 536 enum rtl_tx_desc_bit_1 {
 537         /* First doubleword. */
 538         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 539         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 540 #define GTTCPHO_SHIFT                   18
 541 #define GTTCPHO_MAX                     0x7f
 542
 543         /* Second doubleword. */
 544 #define TCPHO_SHIFT                     18
 545 #define TCPHO_MAX                       0x3ff
 546 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 547         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 548         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 549         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 550         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 551 };
 552
 553 enum rtl_rx_desc_bit {
 554         /* Rx private */
 555         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 556         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 557
 558 #define RxProtoUDP      (PID1)
 559 #define RxProtoTCP      (PID0)
 560 #define RxProtoIP       (PID1 | PID0)
 561 #define RxProtoMask     RxProtoIP
 562
 563         IPFail          = (1 << 16), /* IP checksum failed */
 564         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 565         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 566         RxVlanTag       = (1 << 16), /* VLAN tag available */
 567 };
 568
 569 #define RsvdMask        0x3fffc000
 570
 571 #define RTL_GSO_MAX_SIZE_V1     32000
 572 #define RTL_GSO_MAX_SEGS_V1     24
 573 #define RTL_GSO_MAX_SIZE_V2     64000
 574 #define RTL_GSO_MAX_SEGS_V2     64
 575
 576 struct TxDesc {
 577         __le32 opts1;
 578         __le32 opts2;
 579         __le64 addr;
 580 };
 581
 582 struct RxDesc {
 583         __le32 opts1;
 584         __le32 opts2;
 585         __le64 addr;
 586 };
 587
 588 struct ring_info {
 589         struct sk_buff  *skb;
 590         u32             len;
 591 };
 592
 593 struct rtl8169_counters {
 594         __le64  tx_packets;
 595         __le64  rx_packets;
 596         __le64  tx_errors;
 597         __le32  rx_errors;
 598         __le16  rx_missed;
 599         __le16  align_errors;
 600         __le32  tx_one_collision;
 601         __le32  tx_multi_collision;
 602         __le64  rx_unicast;
 603         __le64  rx_broadcast;
 604         __le32  rx_multicast;
 605         __le16  tx_aborted;
 606         __le16  tx_underun;
 607 };
 608
 609 struct rtl8169_tc_offsets {
 610         bool    inited;
 611         __le64  tx_errors;
 612         __le32  tx_multi_collision;
 613         __le16  tx_aborted;
 614 };
 615
 616 enum rtl_flag {
 617         RTL_FLAG_TASK_ENABLED = 0,
 618         RTL_FLAG_TASK_RESET_PENDING,
 619         RTL_FLAG_MAX
 620 };
 621
 622 struct rtl8169_stats {
 623         u64                     packets;
 624         u64                     bytes;
 625         struct u64_stats_sync   syncp;
 626 };
 627
 628 struct rtl8169_private {
 629         void __iomem *mmio_addr;        /* memory map physical address */
 630         struct pci_dev *pci_dev;
 631         struct net_device *dev;
 632         struct phy_device *phydev;
 633         struct napi_struct napi;
 634         u32 msg_enable;
 635         enum mac_version mac_version;
 636         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 637         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 638         u32 dirty_tx;
 639         struct rtl8169_stats rx_stats;
 640         struct rtl8169_stats tx_stats;
 641         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 642         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 643         dma_addr_t TxPhyAddr;
 644         dma_addr_t RxPhyAddr;
 645         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 646         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 647         u16 cp_cmd;
 648         u32 irq_mask;
 649         struct clk *clk;
 650
 651         struct {
 652                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 653                 struct mutex mutex;
 654                 struct work_struct work;
 655         } wk;
 656
 657         unsigned irq_enabled:1;
 658         unsigned supports_gmii:1;
 659         unsigned aspm_manageable:1;
 660         dma_addr_t counters_phys_addr;
 661         struct rtl8169_counters *counters;
 662         struct rtl8169_tc_offsets tc_offset;
 663         u32 saved_wolopts;
 664
 665         const char *fw_name;
 666         struct rtl_fw *rtl_fw;
 667
 668         u32 ocp_base;
 669 };
 670
 671 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 672
 673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 675 module_param_named(debug, debug.msg_enable, int, 0);
 676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 677 MODULE_SOFTDEP("pre: realtek");
 678 MODULE_LICENSE("GPL");
 679 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 680 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 681 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 682 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 683 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 684 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 685 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 686 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 687 MODULE_FIRMWARE(FIRMWARE_8402_1);
 688 MODULE_FIRMWARE(FIRMWARE_8411_1);
 689 MODULE_FIRMWARE(FIRMWARE_8411_2);
 690 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 691 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 692 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 693 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 694 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 695 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 696 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 697 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 698
 699 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 700 {
 701         return &tp->pci_dev->dev;
 702 }
 703
 704 static void rtl_lock_work(struct rtl8169_private *tp)
 705 {
 706         mutex_lock(&tp->wk.mutex);
 707 }
 708
 709 static void rtl_unlock_work(struct rtl8169_private *tp)
 710 {
 711         mutex_unlock(&tp->wk.mutex);
 712 }
 713
 714 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 715 {
 716         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 717 }
 718
 719 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 720 {
 721         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 722 }
 723
 724 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 725 {
 726         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 727                                            PCI_EXP_DEVCTL_READRQ, force);
 728 }
 729
 730 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 731 {
 732         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 733                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 734                tp->mac_version <= RTL_GIGA_MAC_VER_51;
 735 }
 736
 737 static bool rtl_supports_eee(struct rtl8169_private *tp)
 738 {
 739         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 740                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 741                tp->mac_version != RTL_GIGA_MAC_VER_39;
 742 }
 743
 744 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 745 {
 746         int i;
 747
 748         for (i = 0; i < ETH_ALEN; i++)
 749                 mac[i] = RTL_R8(tp, reg + i);
 750 }
 751
 752 struct rtl_cond {
 753         bool (*check)(struct rtl8169_private *);
 754         const char *msg;
 755 };
 756
 757 static void rtl_udelay(unsigned int d)
 758 {
 759         udelay(d);
 760 }
 761
 762 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 763                           void (*delay)(unsigned int), unsigned int d, int n,
 764                           bool high)
 765 {
 766         int i;
 767
 768         for (i = 0; i < n; i++) {
 769                 if (c->check(tp) == high)
 770                         return true;
 771                 delay(d);
 772         }
 773         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 774                   c->msg, !high, n, d);
 775         return false;
 776 }
 777
 778 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 779                                       const struct rtl_cond *c,
 780                                       unsigned int d, int n)
 781 {
 782         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 783 }
 784
 785 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 786                                      const struct rtl_cond *c,
 787                                      unsigned int d, int n)
 788 {
 789         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 790 }
 791
 792 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 793                                       const struct rtl_cond *c,
 794                                       unsigned int d, int n)
 795 {
 796         return rtl_loop_wait(tp, c, msleep, d, n, true);
 797 }
 798
 799 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 800                                      const struct rtl_cond *c,
 801                                      unsigned int d, int n)
 802 {
 803         return rtl_loop_wait(tp, c, msleep, d, n, false);
 804 }
 805
 806 #define DECLARE_RTL_COND(name)                          \
 807 static bool name ## _check(struct rtl8169_private *);   \
 808                                                         \
 809 static const struct rtl_cond name = {                   \
 810         .check  = name ## _check,                       \
 811         .msg    = #name                                 \
 812 };                                                      \
 813                                                         \
 814 static bool name ## _check(struct rtl8169_private *tp)
 815
 816 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 817 {
 818         if (reg & 0xffff0001) {
 819                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 820                 return true;
 821         }
 822         return false;
 823 }
 824
 825 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 826 {
 827         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 828 }
 829
 830 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 831 {
 832         if (rtl_ocp_reg_failure(tp, reg))
 833                 return;
 834
 835         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 836
 837         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 838 }
 839
 840 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 841 {
 842         if (rtl_ocp_reg_failure(tp, reg))
 843                 return 0;
 844
 845         RTL_W32(tp, GPHY_OCP, reg << 15);
 846
 847         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 848                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 849 }
 850
 851 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 852 {
 853         if (rtl_ocp_reg_failure(tp, reg))
 854                 return;
 855
 856         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 857 }
 858
 859 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 860 {
 861         if (rtl_ocp_reg_failure(tp, reg))
 862                 return 0;
 863
 864         RTL_W32(tp, OCPDR, reg << 15);
 865
 866         return RTL_R32(tp, OCPDR);
 867 }
 868
 869 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 870                                  u16 set)
 871 {
 872         u16 data = r8168_mac_ocp_read(tp, reg);
 873
 874         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 875 }
 876
 877 #define OCP_STD_PHY_BASE        0xa400
 878
 879 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 880 {
 881         if (reg == 0x1f) {
 882                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 883                 return;
 884         }
 885
 886         if (tp->ocp_base != OCP_STD_PHY_BASE)
 887                 reg -= 0x10;
 888
 889         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 890 }
 891
 892 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 893 {
 894         if (tp->ocp_base != OCP_STD_PHY_BASE)
 895                 reg -= 0x10;
 896
 897         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 898 }
 899
 900 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 901 {
 902         if (reg == 0x1f) {
 903                 tp->ocp_base = value << 4;
 904                 return;
 905         }
 906
 907         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 908 }
 909
 910 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 911 {
 912         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 913 }
 914
 915 DECLARE_RTL_COND(rtl_phyar_cond)
 916 {
 917         return RTL_R32(tp, PHYAR) & 0x80000000;
 918 }
 919
 920 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 921 {
 922         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 923
 924         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 925         /*
 926          * According to hardware specs a 20us delay is required after write
 927          * complete indication, but before sending next command.
 928          */
 929         udelay(20);
 930 }
 931
 932 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 933 {
 934         int value;
 935
 936         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 937
 938         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 939                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 940
 941         /*
 942          * According to hardware specs a 20us delay is required after read
 943          * complete indication, but before sending next command.
 944          */
 945         udelay(20);
 946
 947         return value;
 948 }
 949
 950 DECLARE_RTL_COND(rtl_ocpar_cond)
 951 {
 952         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 953 }
 954
 955 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 956 {
 957         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 958         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 959         RTL_W32(tp, EPHY_RXER_NUM, 0);
 960
 961         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 962 }
 963
 964 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 965 {
 966         r8168dp_1_mdio_access(tp, reg,
 967                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 968 }
 969
 970 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 971 {
 972         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 973
 974         mdelay(1);
 975         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 976         RTL_W32(tp, EPHY_RXER_NUM, 0);
 977
 978         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 979                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 980 }
 981
 982 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 983
 984 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 985 {
 986         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 987 }
 988
 989 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 990 {
 991         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 992 }
 993
 994 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 995 {
 996         r8168dp_2_mdio_start(tp);
 997
 998         r8169_mdio_write(tp, reg, value);
 999
1000         r8168dp_2_mdio_stop(tp);
1001 }
1002
1003 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1004 {
1005         int value;
1006
1007         r8168dp_2_mdio_start(tp);
1008
1009         value = r8169_mdio_read(tp, reg);
1010
1011         r8168dp_2_mdio_stop(tp);
1012
1013         return value;
1014 }
1015
1016 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1017 {
1018         switch (tp->mac_version) {
1019         case RTL_GIGA_MAC_VER_27:
1020                 r8168dp_1_mdio_write(tp, location, val);
1021                 break;
1022         case RTL_GIGA_MAC_VER_28:
1023         case RTL_GIGA_MAC_VER_31:
1024                 r8168dp_2_mdio_write(tp, location, val);
1025                 break;
1026         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1027                 r8168g_mdio_write(tp, location, val);
1028                 break;
1029         default:
1030                 r8169_mdio_write(tp, location, val);
1031                 break;
1032         }
1033 }
1034
1035 static int rtl_readphy(struct rtl8169_private *tp, int location)
1036 {
1037         switch (tp->mac_version) {
1038         case RTL_GIGA_MAC_VER_27:
1039                 return r8168dp_1_mdio_read(tp, location);
1040         case RTL_GIGA_MAC_VER_28:
1041         case RTL_GIGA_MAC_VER_31:
1042                 return r8168dp_2_mdio_read(tp, location);
1043         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1044                 return r8168g_mdio_read(tp, location);
1045         default:
1046                 return r8169_mdio_read(tp, location);
1047         }
1048 }
1049
1050 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1051 {
1052         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1053 }
1054
1055 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1056 {
1057         int val;
1058
1059         val = rtl_readphy(tp, reg_addr);
1060         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1061 }
1062
1063 DECLARE_RTL_COND(rtl_ephyar_cond)
1064 {
1065         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1066 }
1067
1068 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1069 {
1070         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1071                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1072
1073         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1074
1075         udelay(10);
1076 }
1077
1078 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1079 {
1080         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1081
1082         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1083                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1084 }
1085
1086 DECLARE_RTL_COND(rtl_eriar_cond)
1087 {
1088         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1089 }
1090
1091 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1092                            u32 val, int type)
1093 {
1094         BUG_ON((addr & 3) || (mask == 0));
1095         RTL_W32(tp, ERIDR, val);
1096         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1097
1098         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1099 }
1100
1101 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1102                           u32 val)
1103 {
1104         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1105 }
1106
1107 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1108 {
1109         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1110
1111         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1112                 RTL_R32(tp, ERIDR) : ~0;
1113 }
1114
1115 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1116 {
1117         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1118 }
1119
1120 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1121                          u32 m)
1122 {
1123         u32 val;
1124
1125         val = rtl_eri_read(tp, addr);
1126         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1127 }
1128
1129 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1130                              u32 p)
1131 {
1132         rtl_w0w1_eri(tp, addr, mask, p, 0);
1133 }
1134
1135 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1136                                u32 m)
1137 {
1138         rtl_w0w1_eri(tp, addr, mask, 0, m);
1139 }
1140
1141 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1142 {
1143         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1144         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1145                 RTL_R32(tp, OCPDR) : ~0;
1146 }
1147
1148 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1149 {
1150         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1151 }
1152
1153 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1154                               u32 data)
1155 {
1156         RTL_W32(tp, OCPDR, data);
1157         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1158         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1159 }
1160
1161 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1162                               u32 data)
1163 {
1164         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1165                        data, ERIAR_OOB);
1166 }
1167
1168 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1169 {
1170         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1171
1172         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1173 }
1174
1175 #define OOB_CMD_RESET           0x00
1176 #define OOB_CMD_DRIVER_START    0x05
1177 #define OOB_CMD_DRIVER_STOP     0x06
1178
1179 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1180 {
1181         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1182 }
1183
1184 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1185 {
1186         u16 reg;
1187
1188         reg = rtl8168_get_ocp_reg(tp);
1189
1190         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1191 }
1192
1193 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1194 {
1195         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1196 }
1197
1198 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1199 {
1200         return RTL_R8(tp, IBISR0) & 0x20;
1201 }
1202
1203 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1204 {
1205         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1206         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1207         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1208         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1209 }
1210
1211 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1212 {
1213         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1214         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1215 }
1216
1217 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1218 {
1219         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1220         r8168ep_ocp_write(tp, 0x01, 0x30,
1221                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1222         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1223 }
1224
1225 static void rtl8168_driver_start(struct rtl8169_private *tp)
1226 {
1227         switch (tp->mac_version) {
1228         case RTL_GIGA_MAC_VER_27:
1229         case RTL_GIGA_MAC_VER_28:
1230         case RTL_GIGA_MAC_VER_31:
1231                 rtl8168dp_driver_start(tp);
1232                 break;
1233         case RTL_GIGA_MAC_VER_49:
1234         case RTL_GIGA_MAC_VER_50:
1235         case RTL_GIGA_MAC_VER_51:
1236                 rtl8168ep_driver_start(tp);
1237                 break;
1238         default:
1239                 BUG();
1240                 break;
1241         }
1242 }
1243
1244 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1245 {
1246         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1247         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1248 }
1249
1250 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1251 {
1252         rtl8168ep_stop_cmac(tp);
1253         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1254         r8168ep_ocp_write(tp, 0x01, 0x30,
1255                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1256         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1257 }
1258
1259 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1260 {
1261         switch (tp->mac_version) {
1262         case RTL_GIGA_MAC_VER_27:
1263         case RTL_GIGA_MAC_VER_28:
1264         case RTL_GIGA_MAC_VER_31:
1265                 rtl8168dp_driver_stop(tp);
1266                 break;
1267         case RTL_GIGA_MAC_VER_49:
1268         case RTL_GIGA_MAC_VER_50:
1269         case RTL_GIGA_MAC_VER_51:
1270                 rtl8168ep_driver_stop(tp);
1271                 break;
1272         default:
1273                 BUG();
1274                 break;
1275         }
1276 }
1277
1278 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1279 {
1280         u16 reg = rtl8168_get_ocp_reg(tp);
1281
1282         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1283 }
1284
1285 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1286 {
1287         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1288 }
1289
1290 static bool r8168_check_dash(struct rtl8169_private *tp)
1291 {
1292         switch (tp->mac_version) {
1293         case RTL_GIGA_MAC_VER_27:
1294         case RTL_GIGA_MAC_VER_28:
1295         case RTL_GIGA_MAC_VER_31:
1296                 return r8168dp_check_dash(tp);
1297         case RTL_GIGA_MAC_VER_49:
1298         case RTL_GIGA_MAC_VER_50:
1299         case RTL_GIGA_MAC_VER_51:
1300                 return r8168ep_check_dash(tp);
1301         default:
1302                 return false;
1303         }
1304 }
1305
1306 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1307 {
1308         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1309         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1310 }
1311
1312 DECLARE_RTL_COND(rtl_efusear_cond)
1313 {
1314         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1315 }
1316
1317 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1318 {
1319         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1320
1321         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1322                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1323 }
1324
1325 static u32 rtl_get_events(struct rtl8169_private *tp)
1326 {
1327         return RTL_R16(tp, IntrStatus);
1328 }
1329
1330 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1331 {
1332         RTL_W16(tp, IntrStatus, bits);
1333 }
1334
1335 static void rtl_irq_disable(struct rtl8169_private *tp)
1336 {
1337         RTL_W16(tp, IntrMask, 0);
1338         tp->irq_enabled = 0;
1339 }
1340
1341 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1342 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1343 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1344
1345 static void rtl_irq_enable(struct rtl8169_private *tp)
1346 {
1347         tp->irq_enabled = 1;
1348         RTL_W16(tp, IntrMask, tp->irq_mask);
1349 }
1350
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1352 {
1353         rtl_irq_disable(tp);
1354         rtl_ack_events(tp, 0xffffffff);
1355         /* PCI commit */
1356         RTL_R8(tp, ChipCmd);
1357 }
1358
1359 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360 {
1361         struct net_device *dev = tp->dev;
1362         struct phy_device *phydev = tp->phydev;
1363
1364         if (!netif_running(dev))
1365                 return;
1366
1367         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1368             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1369                 if (phydev->speed == SPEED_1000) {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1372                 } else if (phydev->speed == SPEED_100) {
1373                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1374                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1375                 } else {
1376                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1377                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1378                 }
1379                 rtl_reset_packet_filter(tp);
1380         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1381                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1382                 if (phydev->speed == SPEED_1000) {
1383                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1384                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1385                 } else {
1386                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1387                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1388                 }
1389         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1390                 if (phydev->speed == SPEED_10) {
1391                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1392                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1393                 } else {
1394                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1395                 }
1396         }
1397 }
1398
1399 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1400
1401 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1402 {
1403         struct rtl8169_private *tp = netdev_priv(dev);
1404
1405         rtl_lock_work(tp);
1406         wol->supported = WAKE_ANY;
1407         wol->wolopts = tp->saved_wolopts;
1408         rtl_unlock_work(tp);
1409 }
1410
1411 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1412 {
1413         unsigned int i, tmp;
1414         static const struct {
1415                 u32 opt;
1416                 u16 reg;
1417                 u8  mask;
1418         } cfg[] = {
1419                 { WAKE_PHY,   Config3, LinkUp },
1420                 { WAKE_UCAST, Config5, UWF },
1421                 { WAKE_BCAST, Config5, BWF },
1422                 { WAKE_MCAST, Config5, MWF },
1423                 { WAKE_ANY,   Config5, LanWake },
1424                 { WAKE_MAGIC, Config3, MagicPacket }
1425         };
1426         u8 options;
1427
1428         rtl_unlock_config_regs(tp);
1429
1430         if (rtl_is_8168evl_up(tp)) {
1431                 tmp = ARRAY_SIZE(cfg) - 1;
1432                 if (wolopts & WAKE_MAGIC)
1433                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1434                                          MagicPacket_v2);
1435                 else
1436                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1437                                            MagicPacket_v2);
1438         } else {
1439                 tmp = ARRAY_SIZE(cfg);
1440         }
1441
1442         for (i = 0; i < tmp; i++) {
1443                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1444                 if (wolopts & cfg[i].opt)
1445                         options |= cfg[i].mask;
1446                 RTL_W8(tp, cfg[i].reg, options);
1447         }
1448
1449         switch (tp->mac_version) {
1450         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1451                 options = RTL_R8(tp, Config1) & ~PMEnable;
1452                 if (wolopts)
1453                         options |= PMEnable;
1454                 RTL_W8(tp, Config1, options);
1455                 break;
1456         case RTL_GIGA_MAC_VER_34:
1457         case RTL_GIGA_MAC_VER_37:
1458         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1459                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1460                 if (wolopts)
1461                         options |= PME_SIGNAL;
1462                 RTL_W8(tp, Config2, options);
1463                 break;
1464         default:
1465                 break;
1466         }
1467
1468         rtl_lock_config_regs(tp);
1469
1470         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1471 }
1472
1473 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1474 {
1475         struct rtl8169_private *tp = netdev_priv(dev);
1476         struct device *d = tp_to_dev(tp);
1477
1478         if (wol->wolopts & ~WAKE_ANY)
1479                 return -EINVAL;
1480
1481         pm_runtime_get_noresume(d);
1482
1483         rtl_lock_work(tp);
1484
1485         tp->saved_wolopts = wol->wolopts;
1486
1487         if (pm_runtime_active(d))
1488                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1489
1490         rtl_unlock_work(tp);
1491
1492         pm_runtime_put_noidle(d);
1493
1494         return 0;
1495 }
1496
1497 static void rtl8169_get_drvinfo(struct net_device *dev,
1498                                 struct ethtool_drvinfo *info)
1499 {
1500         struct rtl8169_private *tp = netdev_priv(dev);
1501         struct rtl_fw *rtl_fw = tp->rtl_fw;
1502
1503         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1504         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1505         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1506         if (rtl_fw)
1507                 strlcpy(info->fw_version, rtl_fw->version,
1508                         sizeof(info->fw_version));
1509 }
1510
1511 static int rtl8169_get_regs_len(struct net_device *dev)
1512 {
1513         return R8169_REGS_SIZE;
1514 }
1515
1516 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1517         netdev_features_t features)
1518 {
1519         struct rtl8169_private *tp = netdev_priv(dev);
1520
1521         if (dev->mtu > TD_MSS_MAX)
1522                 features &= ~NETIF_F_ALL_TSO;
1523
1524         if (dev->mtu > JUMBO_1K &&
1525             tp->mac_version > RTL_GIGA_MAC_VER_06)
1526                 features &= ~NETIF_F_IP_CSUM;
1527
1528         return features;
1529 }
1530
1531 static int rtl8169_set_features(struct net_device *dev,
1532                                 netdev_features_t features)
1533 {
1534         struct rtl8169_private *tp = netdev_priv(dev);
1535         u32 rx_config;
1536
1537         rtl_lock_work(tp);
1538
1539         rx_config = RTL_R32(tp, RxConfig);
1540         if (features & NETIF_F_RXALL)
1541                 rx_config |= (AcceptErr | AcceptRunt);
1542         else
1543                 rx_config &= ~(AcceptErr | AcceptRunt);
1544
1545         RTL_W32(tp, RxConfig, rx_config);
1546
1547         if (features & NETIF_F_RXCSUM)
1548                 tp->cp_cmd |= RxChkSum;
1549         else
1550                 tp->cp_cmd &= ~RxChkSum;
1551
1552         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1553                 tp->cp_cmd |= RxVlan;
1554         else
1555                 tp->cp_cmd &= ~RxVlan;
1556
1557         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1558         RTL_R16(tp, CPlusCmd);
1559
1560         rtl_unlock_work(tp);
1561
1562         return 0;
1563 }
1564
1565 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1566 {
1567         return (skb_vlan_tag_present(skb)) ?
1568                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1569 }
1570
1571 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1572 {
1573         u32 opts2 = le32_to_cpu(desc->opts2);
1574
1575         if (opts2 & RxVlanTag)
1576                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1577 }
1578
1579 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1580                              void *p)
1581 {
1582         struct rtl8169_private *tp = netdev_priv(dev);
1583         u32 __iomem *data = tp->mmio_addr;
1584         u32 *dw = p;
1585         int i;
1586
1587         rtl_lock_work(tp);
1588         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1589                 memcpy_fromio(dw++, data++, 4);
1590         rtl_unlock_work(tp);
1591 }
1592
1593 static u32 rtl8169_get_msglevel(struct net_device *dev)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596
1597         return tp->msg_enable;
1598 }
1599
1600 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1601 {
1602         struct rtl8169_private *tp = netdev_priv(dev);
1603
1604         tp->msg_enable = value;
1605 }
1606
1607 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1608         "tx_packets",
1609         "rx_packets",
1610         "tx_errors",
1611         "rx_errors",
1612         "rx_missed",
1613         "align_errors",
1614         "tx_single_collisions",
1615         "tx_multi_collisions",
1616         "unicast",
1617         "broadcast",
1618         "multicast",
1619         "tx_aborted",
1620         "tx_underrun",
1621 };
1622
1623 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1624 {
1625         switch (sset) {
1626         case ETH_SS_STATS:
1627                 return ARRAY_SIZE(rtl8169_gstrings);
1628         default:
1629                 return -EOPNOTSUPP;
1630         }
1631 }
1632
1633 DECLARE_RTL_COND(rtl_counters_cond)
1634 {
1635         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1636 }
1637
1638 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1639 {
1640         dma_addr_t paddr = tp->counters_phys_addr;
1641         u32 cmd;
1642
1643         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1644         RTL_R32(tp, CounterAddrHigh);
1645         cmd = (u64)paddr & DMA_BIT_MASK(32);
1646         RTL_W32(tp, CounterAddrLow, cmd);
1647         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1648
1649         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1650 }
1651
1652 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1653 {
1654         /*
1655          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1656          * tally counters.
1657          */
1658         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1659                 return true;
1660
1661         return rtl8169_do_counters(tp, CounterReset);
1662 }
1663
1664 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1665 {
1666         u8 val = RTL_R8(tp, ChipCmd);
1667
1668         /*
1669          * Some chips are unable to dump tally counters when the receiver
1670          * is disabled. If 0xff chip may be in a PCI power-save state.
1671          */
1672         if (!(val & CmdRxEnb) || val == 0xff)
1673                 return true;
1674
1675         return rtl8169_do_counters(tp, CounterDump);
1676 }
1677
1678 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1679 {
1680         struct rtl8169_counters *counters = tp->counters;
1681         bool ret = false;
1682
1683         /*
1684          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1685          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1686          * reset by a power cycle, while the counter values collected by the
1687          * driver are reset at every driver unload/load cycle.
1688          *
1689          * To make sure the HW values returned by @get_stats64 match the SW
1690          * values, we collect the initial values at first open(*) and use them
1691          * as offsets to normalize the values returned by @get_stats64.
1692          *
1693          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1694          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1695          * set at open time by rtl_hw_start.
1696          */
1697
1698         if (tp->tc_offset.inited)
1699                 return true;
1700
1701         /* If both, reset and update fail, propagate to caller. */
1702         if (rtl8169_reset_counters(tp))
1703                 ret = true;
1704
1705         if (rtl8169_update_counters(tp))
1706                 ret = true;
1707
1708         tp->tc_offset.tx_errors = counters->tx_errors;
1709         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1710         tp->tc_offset.tx_aborted = counters->tx_aborted;
1711         tp->tc_offset.inited = true;
1712
1713         return ret;
1714 }
1715
1716 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1717                                       struct ethtool_stats *stats, u64 *data)
1718 {
1719         struct rtl8169_private *tp = netdev_priv(dev);
1720         struct device *d = tp_to_dev(tp);
1721         struct rtl8169_counters *counters = tp->counters;
1722
1723         ASSERT_RTNL();
1724
1725         pm_runtime_get_noresume(d);
1726
1727         if (pm_runtime_active(d))
1728                 rtl8169_update_counters(tp);
1729
1730         pm_runtime_put_noidle(d);
1731
1732         data[0] = le64_to_cpu(counters->tx_packets);
1733         data[1] = le64_to_cpu(counters->rx_packets);
1734         data[2] = le64_to_cpu(counters->tx_errors);
1735         data[3] = le32_to_cpu(counters->rx_errors);
1736         data[4] = le16_to_cpu(counters->rx_missed);
1737         data[5] = le16_to_cpu(counters->align_errors);
1738         data[6] = le32_to_cpu(counters->tx_one_collision);
1739         data[7] = le32_to_cpu(counters->tx_multi_collision);
1740         data[8] = le64_to_cpu(counters->rx_unicast);
1741         data[9] = le64_to_cpu(counters->rx_broadcast);
1742         data[10] = le32_to_cpu(counters->rx_multicast);
1743         data[11] = le16_to_cpu(counters->tx_aborted);
1744         data[12] = le16_to_cpu(counters->tx_underun);
1745 }
1746
1747 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1748 {
1749         switch(stringset) {
1750         case ETH_SS_STATS:
1751                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1752                 break;
1753         }
1754 }
1755
1756 /*
1757  * Interrupt coalescing
1758  *
1759  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1760  * >     8169, 8168 and 810x line of chipsets
1761  *
1762  * 8169, 8168, and 8136(810x) serial chipsets support it.
1763  *
1764  * > 2 - the Tx timer unit at gigabit speed
1765  *
1766  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1767  * (0xe0) bit 1 and bit 0.
1768  *
1769  * For 8169
1770  * bit[1:0] \ speed        1000M           100M            10M
1771  * 0 0                     320ns           2.56us          40.96us
1772  * 0 1                     2.56us          20.48us         327.7us
1773  * 1 0                     5.12us          40.96us         655.4us
1774  * 1 1                     10.24us         81.92us         1.31ms
1775  *
1776  * For the other
1777  * bit[1:0] \ speed        1000M           100M            10M
1778  * 0 0                     5us             2.56us          40.96us
1779  * 0 1                     40us            20.48us         327.7us
1780  * 1 0                     80us            40.96us         655.4us
1781  * 1 1                     160us           81.92us         1.31ms
1782  */
1783
1784 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1785 struct rtl_coalesce_scale {
1786         /* Rx / Tx */
1787         u32 nsecs[2];
1788 };
1789
1790 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1791 struct rtl_coalesce_info {
1792         u32 speed;
1793         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1794 };
1795
1796 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1797 #define rxtx_x1822(r, t) {              \
1798         {{(r),          (t)}},          \
1799         {{(r)*8,        (t)*8}},        \
1800         {{(r)*8*2,      (t)*8*2}},      \
1801         {{(r)*8*2*2,    (t)*8*2*2}},    \
1802 }
1803 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1804         /* speed        delays:     rx00   tx00 */
1805         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1806         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1807         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1808         { 0 },
1809 };
1810
1811 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1812         /* speed        delays:     rx00   tx00 */
1813         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1814         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1815         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1816         { 0 },
1817 };
1818 #undef rxtx_x1822
1819
1820 /* get rx/tx scale vector corresponding to current speed */
1821 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1822 {
1823         struct rtl8169_private *tp = netdev_priv(dev);
1824         const struct rtl_coalesce_info *ci;
1825
1826         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1827                 ci = rtl_coalesce_info_8169;
1828         else
1829                 ci = rtl_coalesce_info_8168_8136;
1830
1831         for (; ci->speed; ci++) {
1832                 if (tp->phydev->speed == ci->speed)
1833                         return ci;
1834         }
1835
1836         return ERR_PTR(-ELNRNG);
1837 }
1838
1839 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1840 {
1841         struct rtl8169_private *tp = netdev_priv(dev);
1842         const struct rtl_coalesce_info *ci;
1843         const struct rtl_coalesce_scale *scale;
1844         struct {
1845                 u32 *max_frames;
1846                 u32 *usecs;
1847         } coal_settings [] = {
1848                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1849                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1850         }, *p = coal_settings;
1851         int i;
1852         u16 w;
1853
1854         memset(ec, 0, sizeof(*ec));
1855
1856         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1857         ci = rtl_coalesce_info(dev);
1858         if (IS_ERR(ci))
1859                 return PTR_ERR(ci);
1860
1861         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1862
1863         /* read IntrMitigate and adjust according to scale */
1864         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1865                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1866                 w >>= RTL_COALESCE_SHIFT;
1867                 *p->usecs = w & RTL_COALESCE_MASK;
1868         }
1869
1870         for (i = 0; i < 2; i++) {
1871                 p = coal_settings + i;
1872                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1873
1874                 /*
1875                  * ethtool_coalesce says it is illegal to set both usecs and
1876                  * max_frames to 0.
1877                  */
1878                 if (!*p->usecs && !*p->max_frames)
1879                         *p->max_frames = 1;
1880         }
1881
1882         return 0;
1883 }
1884
1885 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1886 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1887                         struct net_device *dev, u32 nsec, u16 *cp01)
1888 {
1889         const struct rtl_coalesce_info *ci;
1890         u16 i;
1891
1892         ci = rtl_coalesce_info(dev);
1893         if (IS_ERR(ci))
1894                 return ERR_CAST(ci);
1895
1896         for (i = 0; i < 4; i++) {
1897                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1898                                         ci->scalev[i].nsecs[1]);
1899                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1900                         *cp01 = i;
1901                         return &ci->scalev[i];
1902                 }
1903         }
1904
1905         return ERR_PTR(-EINVAL);
1906 }
1907
1908 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1909 {
1910         struct rtl8169_private *tp = netdev_priv(dev);
1911         const struct rtl_coalesce_scale *scale;
1912         struct {
1913                 u32 frames;
1914                 u32 usecs;
1915         } coal_settings [] = {
1916                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1917                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1918         }, *p = coal_settings;
1919         u16 w = 0, cp01;
1920         int i;
1921
1922         scale = rtl_coalesce_choose_scale(dev,
1923                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1924         if (IS_ERR(scale))
1925                 return PTR_ERR(scale);
1926
1927         for (i = 0; i < 2; i++, p++) {
1928                 u32 units;
1929
1930                 /*
1931                  * accept max_frames=1 we returned in rtl_get_coalesce.
1932                  * accept it not only when usecs=0 because of e.g. the following scenario:
1933                  *
1934                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1935                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1936                  * - then user does `ethtool -C eth0 rx-usecs 100`
1937                  *
1938                  * since ethtool sends to kernel whole ethtool_coalesce
1939                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1940                  * we'll reject it below in `frames % 4 != 0`.
1941                  */
1942                 if (p->frames == 1) {
1943                         p->frames = 0;
1944                 }
1945
1946                 units = p->usecs * 1000 / scale->nsecs[i];
1947                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1948                         return -EINVAL;
1949
1950                 w <<= RTL_COALESCE_SHIFT;
1951                 w |= units;
1952                 w <<= RTL_COALESCE_SHIFT;
1953                 w |= p->frames >> 2;
1954         }
1955
1956         rtl_lock_work(tp);
1957
1958         RTL_W16(tp, IntrMitigate, swab16(w));
1959
1960         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1961         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1962         RTL_R16(tp, CPlusCmd);
1963
1964         rtl_unlock_work(tp);
1965
1966         return 0;
1967 }
1968
1969 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1970 {
1971         struct rtl8169_private *tp = netdev_priv(dev);
1972         struct device *d = tp_to_dev(tp);
1973         int ret;
1974
1975         if (!rtl_supports_eee(tp))
1976                 return -EOPNOTSUPP;
1977
1978         pm_runtime_get_noresume(d);
1979
1980         if (!pm_runtime_active(d)) {
1981                 ret = -EOPNOTSUPP;
1982         } else {
1983                 ret = phy_ethtool_get_eee(tp->phydev, data);
1984         }
1985
1986         pm_runtime_put_noidle(d);
1987
1988         return ret;
1989 }
1990
1991 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1992 {
1993         struct rtl8169_private *tp = netdev_priv(dev);
1994         struct device *d = tp_to_dev(tp);
1995         int ret;
1996
1997         if (!rtl_supports_eee(tp))
1998                 return -EOPNOTSUPP;
1999
2000         pm_runtime_get_noresume(d);
2001
2002         if (!pm_runtime_active(d)) {
2003                 ret = -EOPNOTSUPP;
2004                 goto out;
2005         }
2006
2007         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2008             dev->phydev->duplex != DUPLEX_FULL) {
2009                 ret = -EPROTONOSUPPORT;
2010                 goto out;
2011         }
2012
2013         ret = phy_ethtool_set_eee(tp->phydev, data);
2014 out:
2015         pm_runtime_put_noidle(d);
2016         return ret;
2017 }
2018
2019 static const struct ethtool_ops rtl8169_ethtool_ops = {
2020         .get_drvinfo            = rtl8169_get_drvinfo,
2021         .get_regs_len           = rtl8169_get_regs_len,
2022         .get_link               = ethtool_op_get_link,
2023         .get_coalesce           = rtl_get_coalesce,
2024         .set_coalesce           = rtl_set_coalesce,
2025         .get_msglevel           = rtl8169_get_msglevel,
2026         .set_msglevel           = rtl8169_set_msglevel,
2027         .get_regs               = rtl8169_get_regs,
2028         .get_wol                = rtl8169_get_wol,
2029         .set_wol                = rtl8169_set_wol,
2030         .get_strings            = rtl8169_get_strings,
2031         .get_sset_count         = rtl8169_get_sset_count,
2032         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2033         .get_ts_info            = ethtool_op_get_ts_info,
2034         .nway_reset             = phy_ethtool_nway_reset,
2035         .get_eee                = rtl8169_get_eee,
2036         .set_eee                = rtl8169_set_eee,
2037         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2038         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2039 };
2040
2041 static void rtl_enable_eee(struct rtl8169_private *tp)
2042 {
2043         struct phy_device *phydev = tp->phydev;
2044         int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2045
2046         if (supported > 0)
2047                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2048 }
2049
2050 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2051 {
2052         /*
2053          * The driver currently handles the 8168Bf and the 8168Be identically
2054          * but they can be identified more specifically through the test below
2055          * if needed:
2056          *
2057          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2058          *
2059          * Same thing for the 8101Eb and the 8101Ec:
2060          *
2061          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2062          */
2063         static const struct rtl_mac_info {
2064                 u16 mask;
2065                 u16 val;
2066                 u16 mac_version;
2067         } mac_info[] = {
2068                 /* 8168EP family. */
2069                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2070                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2071                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2072
2073                 /* 8168H family. */
2074                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2075                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2076
2077                 /* 8168G family. */
2078                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2079                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2080                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2081                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2082
2083                 /* 8168F family. */
2084                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2085                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2086                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2087
2088                 /* 8168E family. */
2089                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2090                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2091                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2092
2093                 /* 8168D family. */
2094                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2095                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2096
2097                 /* 8168DP family. */
2098                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2099                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2100                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2101
2102                 /* 8168C family. */
2103                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2104                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2105                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2106                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2107                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2108                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2109                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2110
2111                 /* 8168B family. */
2112                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2113                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2114                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2115
2116                 /* 8101 family. */
2117                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2118                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2119                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2120                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2121                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2122                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2123                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2124                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2125                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2126                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2127                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2128                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2129                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2130                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2131                 /* FIXME: where did these entries come from ? -- FR */
2132                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2133                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2134
2135                 /* 8110 family. */
2136                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2137                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2138                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2139                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2140                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2141
2142                 /* Catch-all */
2143                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2144         };
2145         const struct rtl_mac_info *p = mac_info;
2146         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2147
2148         while ((reg & p->mask) != p->val)
2149                 p++;
2150         tp->mac_version = p->mac_version;
2151
2152         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2153                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2154         } else if (!tp->supports_gmii) {
2155                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2156                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2157                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2158                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2159                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2160                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2161         }
2162 }
2163
2164 struct phy_reg {
2165         u16 reg;
2166         u16 val;
2167 };
2168
2169 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2170                                  const struct phy_reg *regs, int len)
2171 {
2172         while (len-- > 0) {
2173                 rtl_writephy(tp, regs->reg, regs->val);
2174                 regs++;
2175         }
2176 }
2177
2178 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2179
2180 static void rtl_release_firmware(struct rtl8169_private *tp)
2181 {
2182         if (tp->rtl_fw) {
2183                 rtl_fw_release_firmware(tp->rtl_fw);
2184                 kfree(tp->rtl_fw);
2185                 tp->rtl_fw = NULL;
2186         }
2187 }
2188
2189 static void rtl_apply_firmware(struct rtl8169_private *tp)
2190 {
2191         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2192         if (tp->rtl_fw)
2193                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2194 }
2195
2196 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2197 {
2198         if (rtl_readphy(tp, reg) != val)
2199                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2200         else
2201                 rtl_apply_firmware(tp);
2202 }
2203
2204 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2205 {
2206         /* Adjust EEE LED frequency */
2207         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2208                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2209
2210         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2211 }
2212
2213 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2214 {
2215         struct phy_device *phydev = tp->phydev;
2216
2217         phy_write(phydev, 0x1f, 0x0007);
2218         phy_write(phydev, 0x1e, 0x0020);
2219         phy_set_bits(phydev, 0x15, BIT(8));
2220
2221         phy_write(phydev, 0x1f, 0x0005);
2222         phy_write(phydev, 0x05, 0x8b85);
2223         phy_set_bits(phydev, 0x06, BIT(13));
2224
2225         phy_write(phydev, 0x1f, 0x0000);
2226 }
2227
2228 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2229 {
2230         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2231 }
2232
2233 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2234 {
2235         struct phy_device *phydev = tp->phydev;
2236
2237         rtl8168g_config_eee_phy(tp);
2238
2239         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2240         phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2241 }
2242
2243 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2244 {
2245         static const struct phy_reg phy_reg_init[] = {
2246                 { 0x1f, 0x0001 },
2247                 { 0x06, 0x006e },
2248                 { 0x08, 0x0708 },
2249                 { 0x15, 0x4000 },
2250                 { 0x18, 0x65c7 },
2251
2252                 { 0x1f, 0x0001 },
2253                 { 0x03, 0x00a1 },
2254                 { 0x02, 0x0008 },
2255                 { 0x01, 0x0120 },
2256                 { 0x00, 0x1000 },
2257                 { 0x04, 0x0800 },
2258                 { 0x04, 0x0000 },
2259
2260                 { 0x03, 0xff41 },
2261                 { 0x02, 0xdf60 },
2262                 { 0x01, 0x0140 },
2263                 { 0x00, 0x0077 },
2264                 { 0x04, 0x7800 },
2265                 { 0x04, 0x7000 },
2266
2267                 { 0x03, 0x802f },
2268                 { 0x02, 0x4f02 },
2269                 { 0x01, 0x0409 },
2270                 { 0x00, 0xf0f9 },
2271                 { 0x04, 0x9800 },
2272                 { 0x04, 0x9000 },
2273
2274                 { 0x03, 0xdf01 },
2275                 { 0x02, 0xdf20 },
2276                 { 0x01, 0xff95 },
2277                 { 0x00, 0xba00 },
2278                 { 0x04, 0xa800 },
2279                 { 0x04, 0xa000 },
2280
2281                 { 0x03, 0xff41 },
2282                 { 0x02, 0xdf20 },
2283                 { 0x01, 0x0140 },
2284                 { 0x00, 0x00bb },
2285                 { 0x04, 0xb800 },
2286                 { 0x04, 0xb000 },
2287
2288                 { 0x03, 0xdf41 },
2289                 { 0x02, 0xdc60 },
2290                 { 0x01, 0x6340 },
2291                 { 0x00, 0x007d },
2292                 { 0x04, 0xd800 },
2293                 { 0x04, 0xd000 },
2294
2295                 { 0x03, 0xdf01 },
2296                 { 0x02, 0xdf20 },
2297                 { 0x01, 0x100a },
2298                 { 0x00, 0xa0ff },
2299                 { 0x04, 0xf800 },
2300                 { 0x04, 0xf000 },
2301
2302                 { 0x1f, 0x0000 },
2303                 { 0x0b, 0x0000 },
2304                 { 0x00, 0x9200 }
2305         };
2306
2307         rtl_writephy_batch(tp, phy_reg_init);
2308 }
2309
2310 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2311 {
2312         static const struct phy_reg phy_reg_init[] = {
2313                 { 0x1f, 0x0002 },
2314                 { 0x01, 0x90d0 },
2315                 { 0x1f, 0x0000 }
2316         };
2317
2318         rtl_writephy_batch(tp, phy_reg_init);
2319 }
2320
2321 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2322 {
2323         struct pci_dev *pdev = tp->pci_dev;
2324
2325         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2326             (pdev->subsystem_device != 0xe000))
2327                 return;
2328
2329         rtl_writephy(tp, 0x1f, 0x0001);
2330         rtl_writephy(tp, 0x10, 0xf01b);
2331         rtl_writephy(tp, 0x1f, 0x0000);
2332 }
2333
2334 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2335 {
2336         static const struct phy_reg phy_reg_init[] = {
2337                 { 0x1f, 0x0001 },
2338                 { 0x04, 0x0000 },
2339                 { 0x03, 0x00a1 },
2340                 { 0x02, 0x0008 },
2341                 { 0x01, 0x0120 },
2342                 { 0x00, 0x1000 },
2343                 { 0x04, 0x0800 },
2344                 { 0x04, 0x9000 },
2345                 { 0x03, 0x802f },
2346                 { 0x02, 0x4f02 },
2347                 { 0x01, 0x0409 },
2348                 { 0x00, 0xf099 },
2349                 { 0x04, 0x9800 },
2350                 { 0x04, 0xa000 },
2351                 { 0x03, 0xdf01 },
2352                 { 0x02, 0xdf20 },
2353                 { 0x01, 0xff95 },
2354                 { 0x00, 0xba00 },
2355                 { 0x04, 0xa800 },
2356                 { 0x04, 0xf000 },
2357                 { 0x03, 0xdf01 },
2358                 { 0x02, 0xdf20 },
2359                 { 0x01, 0x101a },
2360                 { 0x00, 0xa0ff },
2361                 { 0x04, 0xf800 },
2362                 { 0x04, 0x0000 },
2363                 { 0x1f, 0x0000 },
2364
2365                 { 0x1f, 0x0001 },
2366                 { 0x10, 0xf41b },
2367                 { 0x14, 0xfb54 },
2368                 { 0x18, 0xf5c7 },
2369                 { 0x1f, 0x0000 },
2370
2371                 { 0x1f, 0x0001 },
2372                 { 0x17, 0x0cc0 },
2373                 { 0x1f, 0x0000 }
2374         };
2375
2376         rtl_writephy_batch(tp, phy_reg_init);
2377
2378         rtl8169scd_hw_phy_config_quirk(tp);
2379 }
2380
2381 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2382 {
2383         static const struct phy_reg phy_reg_init[] = {
2384                 { 0x1f, 0x0001 },
2385                 { 0x04, 0x0000 },
2386                 { 0x03, 0x00a1 },
2387                 { 0x02, 0x0008 },
2388                 { 0x01, 0x0120 },
2389                 { 0x00, 0x1000 },
2390                 { 0x04, 0x0800 },
2391                 { 0x04, 0x9000 },
2392                 { 0x03, 0x802f },
2393                 { 0x02, 0x4f02 },
2394                 { 0x01, 0x0409 },
2395                 { 0x00, 0xf099 },
2396                 { 0x04, 0x9800 },
2397                 { 0x04, 0xa000 },
2398                 { 0x03, 0xdf01 },
2399                 { 0x02, 0xdf20 },
2400                 { 0x01, 0xff95 },
2401                 { 0x00, 0xba00 },
2402                 { 0x04, 0xa800 },
2403                 { 0x04, 0xf000 },
2404                 { 0x03, 0xdf01 },
2405                 { 0x02, 0xdf20 },
2406                 { 0x01, 0x101a },
2407                 { 0x00, 0xa0ff },
2408                 { 0x04, 0xf800 },
2409                 { 0x04, 0x0000 },
2410                 { 0x1f, 0x0000 },
2411
2412                 { 0x1f, 0x0001 },
2413                 { 0x0b, 0x8480 },
2414                 { 0x1f, 0x0000 },
2415
2416                 { 0x1f, 0x0001 },
2417                 { 0x18, 0x67c7 },
2418                 { 0x04, 0x2000 },
2419                 { 0x03, 0x002f },
2420                 { 0x02, 0x4360 },
2421                 { 0x01, 0x0109 },
2422                 { 0x00, 0x3022 },
2423                 { 0x04, 0x2800 },
2424                 { 0x1f, 0x0000 },
2425
2426                 { 0x1f, 0x0001 },
2427                 { 0x17, 0x0cc0 },
2428                 { 0x1f, 0x0000 }
2429         };
2430
2431         rtl_writephy_batch(tp, phy_reg_init);
2432 }
2433
2434 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2435 {
2436         static const struct phy_reg phy_reg_init[] = {
2437                 { 0x10, 0xf41b },
2438                 { 0x1f, 0x0000 }
2439         };
2440
2441         rtl_writephy(tp, 0x1f, 0x0001);
2442         rtl_patchphy(tp, 0x16, 1 << 0);
2443
2444         rtl_writephy_batch(tp, phy_reg_init);
2445 }
2446
2447 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2448 {
2449         static const struct phy_reg phy_reg_init[] = {
2450                 { 0x1f, 0x0001 },
2451                 { 0x10, 0xf41b },
2452                 { 0x1f, 0x0000 }
2453         };
2454
2455         rtl_writephy_batch(tp, phy_reg_init);
2456 }
2457
2458 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2459 {
2460         static const struct phy_reg phy_reg_init[] = {
2461                 { 0x1f, 0x0000 },
2462                 { 0x1d, 0x0f00 },
2463                 { 0x1f, 0x0002 },
2464                 { 0x0c, 0x1ec8 },
2465                 { 0x1f, 0x0000 }
2466         };
2467
2468         rtl_writephy_batch(tp, phy_reg_init);
2469 }
2470
2471 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2472 {
2473         static const struct phy_reg phy_reg_init[] = {
2474                 { 0x1f, 0x0001 },
2475                 { 0x1d, 0x3d98 },
2476                 { 0x1f, 0x0000 }
2477         };
2478
2479         rtl_writephy(tp, 0x1f, 0x0000);
2480         rtl_patchphy(tp, 0x14, 1 << 5);
2481         rtl_patchphy(tp, 0x0d, 1 << 5);
2482
2483         rtl_writephy_batch(tp, phy_reg_init);
2484 }
2485
2486 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2487 {
2488         static const struct phy_reg phy_reg_init[] = {
2489                 { 0x1f, 0x0001 },
2490                 { 0x12, 0x2300 },
2491                 { 0x1f, 0x0002 },
2492                 { 0x00, 0x88d4 },
2493                 { 0x01, 0x82b1 },
2494                 { 0x03, 0x7002 },
2495                 { 0x08, 0x9e30 },
2496                 { 0x09, 0x01f0 },
2497                 { 0x0a, 0x5500 },
2498                 { 0x0c, 0x00c8 },
2499                 { 0x1f, 0x0003 },
2500                 { 0x12, 0xc096 },
2501                 { 0x16, 0x000a },
2502                 { 0x1f, 0x0000 },
2503                 { 0x1f, 0x0000 },
2504                 { 0x09, 0x2000 },
2505                 { 0x09, 0x0000 }
2506         };
2507
2508         rtl_writephy_batch(tp, phy_reg_init);
2509
2510         rtl_patchphy(tp, 0x14, 1 << 5);
2511         rtl_patchphy(tp, 0x0d, 1 << 5);
2512         rtl_writephy(tp, 0x1f, 0x0000);
2513 }
2514
2515 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2516 {
2517         static const struct phy_reg phy_reg_init[] = {
2518                 { 0x1f, 0x0001 },
2519                 { 0x12, 0x2300 },
2520                 { 0x03, 0x802f },
2521                 { 0x02, 0x4f02 },
2522                 { 0x01, 0x0409 },
2523                 { 0x00, 0xf099 },
2524                 { 0x04, 0x9800 },
2525                 { 0x04, 0x9000 },
2526                 { 0x1d, 0x3d98 },
2527                 { 0x1f, 0x0002 },
2528                 { 0x0c, 0x7eb8 },
2529                 { 0x06, 0x0761 },
2530                 { 0x1f, 0x0003 },
2531                 { 0x16, 0x0f0a },
2532                 { 0x1f, 0x0000 }
2533         };
2534
2535         rtl_writephy_batch(tp, phy_reg_init);
2536
2537         rtl_patchphy(tp, 0x16, 1 << 0);
2538         rtl_patchphy(tp, 0x14, 1 << 5);
2539         rtl_patchphy(tp, 0x0d, 1 << 5);
2540         rtl_writephy(tp, 0x1f, 0x0000);
2541 }
2542
2543 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2544 {
2545         static const struct phy_reg phy_reg_init[] = {
2546                 { 0x1f, 0x0001 },
2547                 { 0x12, 0x2300 },
2548                 { 0x1d, 0x3d98 },
2549                 { 0x1f, 0x0002 },
2550                 { 0x0c, 0x7eb8 },
2551                 { 0x06, 0x5461 },
2552                 { 0x1f, 0x0003 },
2553                 { 0x16, 0x0f0a },
2554                 { 0x1f, 0x0000 }
2555         };
2556
2557         rtl_writephy_batch(tp, phy_reg_init);
2558
2559         rtl_patchphy(tp, 0x16, 1 << 0);
2560         rtl_patchphy(tp, 0x14, 1 << 5);
2561         rtl_patchphy(tp, 0x0d, 1 << 5);
2562         rtl_writephy(tp, 0x1f, 0x0000);
2563 }
2564
2565 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2566 {
2567         rtl8168c_3_hw_phy_config(tp);
2568 }
2569
2570 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2571         /* Channel Estimation */
2572         { 0x1f, 0x0001 },
2573         { 0x06, 0x4064 },
2574         { 0x07, 0x2863 },
2575         { 0x08, 0x059c },
2576         { 0x09, 0x26b4 },
2577         { 0x0a, 0x6a19 },
2578         { 0x0b, 0xdcc8 },
2579         { 0x10, 0xf06d },
2580         { 0x14, 0x7f68 },
2581         { 0x18, 0x7fd9 },
2582         { 0x1c, 0xf0ff },
2583         { 0x1d, 0x3d9c },
2584         { 0x1f, 0x0003 },
2585         { 0x12, 0xf49f },
2586         { 0x13, 0x070b },
2587         { 0x1a, 0x05ad },
2588         { 0x14, 0x94c0 },
2589
2590         /*
2591          * Tx Error Issue
2592          * Enhance line driver power
2593          */
2594         { 0x1f, 0x0002 },
2595         { 0x06, 0x5561 },
2596         { 0x1f, 0x0005 },
2597         { 0x05, 0x8332 },
2598         { 0x06, 0x5561 },
2599
2600         /*
2601          * Can not link to 1Gbps with bad cable
2602          * Decrease SNR threshold form 21.07dB to 19.04dB
2603          */
2604         { 0x1f, 0x0001 },
2605         { 0x17, 0x0cc0 },
2606
2607         { 0x1f, 0x0000 },
2608         { 0x0d, 0xf880 }
2609 };
2610
2611 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2612         { 0x1f, 0x0002 },
2613         { 0x05, 0x669a },
2614         { 0x1f, 0x0005 },
2615         { 0x05, 0x8330 },
2616         { 0x06, 0x669a },
2617         { 0x1f, 0x0002 }
2618 };
2619
2620 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2621 {
2622         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2623
2624         /*
2625          * Rx Error Issue
2626          * Fine Tune Switching regulator parameter
2627          */
2628         rtl_writephy(tp, 0x1f, 0x0002);
2629         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2630         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2631
2632         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2633                 int val;
2634
2635                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2636
2637                 val = rtl_readphy(tp, 0x0d);
2638
2639                 if ((val & 0x00ff) != 0x006c) {
2640                         static const u32 set[] = {
2641                                 0x0065, 0x0066, 0x0067, 0x0068,
2642                                 0x0069, 0x006a, 0x006b, 0x006c
2643                         };
2644                         int i;
2645
2646                         rtl_writephy(tp, 0x1f, 0x0002);
2647
2648                         val &= 0xff00;
2649                         for (i = 0; i < ARRAY_SIZE(set); i++)
2650                                 rtl_writephy(tp, 0x0d, val | set[i]);
2651                 }
2652         } else {
2653                 static const struct phy_reg phy_reg_init[] = {
2654                         { 0x1f, 0x0002 },
2655                         { 0x05, 0x6662 },
2656                         { 0x1f, 0x0005 },
2657                         { 0x05, 0x8330 },
2658                         { 0x06, 0x6662 }
2659                 };
2660
2661                 rtl_writephy_batch(tp, phy_reg_init);
2662         }
2663
2664         /* RSET couple improve */
2665         rtl_writephy(tp, 0x1f, 0x0002);
2666         rtl_patchphy(tp, 0x0d, 0x0300);
2667         rtl_patchphy(tp, 0x0f, 0x0010);
2668
2669         /* Fine tune PLL performance */
2670         rtl_writephy(tp, 0x1f, 0x0002);
2671         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2672         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2673
2674         rtl_writephy(tp, 0x1f, 0x0005);
2675         rtl_writephy(tp, 0x05, 0x001b);
2676
2677         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2678
2679         rtl_writephy(tp, 0x1f, 0x0000);
2680 }
2681
2682 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2685
2686         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2687                 int val;
2688
2689                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2690
2691                 val = rtl_readphy(tp, 0x0d);
2692                 if ((val & 0x00ff) != 0x006c) {
2693                         static const u32 set[] = {
2694                                 0x0065, 0x0066, 0x0067, 0x0068,
2695                                 0x0069, 0x006a, 0x006b, 0x006c
2696                         };
2697                         int i;
2698
2699                         rtl_writephy(tp, 0x1f, 0x0002);
2700
2701                         val &= 0xff00;
2702                         for (i = 0; i < ARRAY_SIZE(set); i++)
2703                                 rtl_writephy(tp, 0x0d, val | set[i]);
2704                 }
2705         } else {
2706                 static const struct phy_reg phy_reg_init[] = {
2707                         { 0x1f, 0x0002 },
2708                         { 0x05, 0x2642 },
2709                         { 0x1f, 0x0005 },
2710                         { 0x05, 0x8330 },
2711                         { 0x06, 0x2642 }
2712                 };
2713
2714                 rtl_writephy_batch(tp, phy_reg_init);
2715         }
2716
2717         /* Fine tune PLL performance */
2718         rtl_writephy(tp, 0x1f, 0x0002);
2719         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2720         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2721
2722         /* Switching regulator Slew rate */
2723         rtl_writephy(tp, 0x1f, 0x0002);
2724         rtl_patchphy(tp, 0x0f, 0x0017);
2725
2726         rtl_writephy(tp, 0x1f, 0x0005);
2727         rtl_writephy(tp, 0x05, 0x001b);
2728
2729         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2730
2731         rtl_writephy(tp, 0x1f, 0x0000);
2732 }
2733
2734 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2735 {
2736         static const struct phy_reg phy_reg_init[] = {
2737                 { 0x1f, 0x0002 },
2738                 { 0x10, 0x0008 },
2739                 { 0x0d, 0x006c },
2740
2741                 { 0x1f, 0x0000 },
2742                 { 0x0d, 0xf880 },
2743
2744                 { 0x1f, 0x0001 },
2745                 { 0x17, 0x0cc0 },
2746
2747                 { 0x1f, 0x0001 },
2748                 { 0x0b, 0xa4d8 },
2749                 { 0x09, 0x281c },
2750                 { 0x07, 0x2883 },
2751                 { 0x0a, 0x6b35 },
2752                 { 0x1d, 0x3da4 },
2753                 { 0x1c, 0xeffd },
2754                 { 0x14, 0x7f52 },
2755                 { 0x18, 0x7fc6 },
2756                 { 0x08, 0x0601 },
2757                 { 0x06, 0x4063 },
2758                 { 0x10, 0xf074 },
2759                 { 0x1f, 0x0003 },
2760                 { 0x13, 0x0789 },
2761                 { 0x12, 0xf4bd },
2762                 { 0x1a, 0x04fd },
2763                 { 0x14, 0x84b0 },
2764                 { 0x1f, 0x0000 },
2765                 { 0x00, 0x9200 },
2766
2767                 { 0x1f, 0x0005 },
2768                 { 0x01, 0x0340 },
2769                 { 0x1f, 0x0001 },
2770                 { 0x04, 0x4000 },
2771                 { 0x03, 0x1d21 },
2772                 { 0x02, 0x0c32 },
2773                 { 0x01, 0x0200 },
2774                 { 0x00, 0x5554 },
2775                 { 0x04, 0x4800 },
2776                 { 0x04, 0x4000 },
2777                 { 0x04, 0xf000 },
2778                 { 0x03, 0xdf01 },
2779                 { 0x02, 0xdf20 },
2780                 { 0x01, 0x101a },
2781                 { 0x00, 0xa0ff },
2782                 { 0x04, 0xf800 },
2783                 { 0x04, 0xf000 },
2784                 { 0x1f, 0x0000 },
2785
2786                 { 0x1f, 0x0007 },
2787                 { 0x1e, 0x0023 },
2788                 { 0x16, 0x0000 },
2789                 { 0x1f, 0x0000 }
2790         };
2791
2792         rtl_writephy_batch(tp, phy_reg_init);
2793 }
2794
2795 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2796 {
2797         static const struct phy_reg phy_reg_init[] = {
2798                 { 0x1f, 0x0001 },
2799                 { 0x17, 0x0cc0 },
2800
2801                 { 0x1f, 0x0007 },
2802                 { 0x1e, 0x002d },
2803                 { 0x18, 0x0040 },
2804                 { 0x1f, 0x0000 }
2805         };
2806
2807         rtl_writephy_batch(tp, phy_reg_init);
2808         rtl_patchphy(tp, 0x0d, 1 << 5);
2809 }
2810
2811 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2812 {
2813         static const struct phy_reg phy_reg_init[] = {
2814                 /* Enable Delay cap */
2815                 { 0x1f, 0x0005 },
2816                 { 0x05, 0x8b80 },
2817                 { 0x06, 0xc896 },
2818                 { 0x1f, 0x0000 },
2819
2820                 /* Channel estimation fine tune */
2821                 { 0x1f, 0x0001 },
2822                 { 0x0b, 0x6c20 },
2823                 { 0x07, 0x2872 },
2824                 { 0x1c, 0xefff },
2825                 { 0x1f, 0x0003 },
2826                 { 0x14, 0x6420 },
2827                 { 0x1f, 0x0000 },
2828
2829                 /* Update PFM & 10M TX idle timer */
2830                 { 0x1f, 0x0007 },
2831                 { 0x1e, 0x002f },
2832                 { 0x15, 0x1919 },
2833                 { 0x1f, 0x0000 },
2834
2835                 { 0x1f, 0x0007 },
2836                 { 0x1e, 0x00ac },
2837                 { 0x18, 0x0006 },
2838                 { 0x1f, 0x0000 }
2839         };
2840
2841         rtl_apply_firmware(tp);
2842
2843         rtl_writephy_batch(tp, phy_reg_init);
2844
2845         /* DCO enable for 10M IDLE Power */
2846         rtl_writephy(tp, 0x1f, 0x0007);
2847         rtl_writephy(tp, 0x1e, 0x0023);
2848         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2849         rtl_writephy(tp, 0x1f, 0x0000);
2850
2851         /* For impedance matching */
2852         rtl_writephy(tp, 0x1f, 0x0002);
2853         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2854         rtl_writephy(tp, 0x1f, 0x0000);
2855
2856         /* PHY auto speed down */
2857         rtl_writephy(tp, 0x1f, 0x0007);
2858         rtl_writephy(tp, 0x1e, 0x002d);
2859         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2860         rtl_writephy(tp, 0x1f, 0x0000);
2861         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2862
2863         rtl_writephy(tp, 0x1f, 0x0005);
2864         rtl_writephy(tp, 0x05, 0x8b86);
2865         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2866         rtl_writephy(tp, 0x1f, 0x0000);
2867
2868         rtl_writephy(tp, 0x1f, 0x0005);
2869         rtl_writephy(tp, 0x05, 0x8b85);
2870         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2871         rtl_writephy(tp, 0x1f, 0x0007);
2872         rtl_writephy(tp, 0x1e, 0x0020);
2873         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2874         rtl_writephy(tp, 0x1f, 0x0006);
2875         rtl_writephy(tp, 0x00, 0x5a00);
2876         rtl_writephy(tp, 0x1f, 0x0000);
2877         rtl_writephy(tp, 0x0d, 0x0007);
2878         rtl_writephy(tp, 0x0e, 0x003c);
2879         rtl_writephy(tp, 0x0d, 0x4007);
2880         rtl_writephy(tp, 0x0e, 0x0000);
2881         rtl_writephy(tp, 0x0d, 0x0000);
2882 }
2883
2884 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2885 {
2886         const u16 w[] = {
2887                 addr[0] | (addr[1] << 8),
2888                 addr[2] | (addr[3] << 8),
2889                 addr[4] | (addr[5] << 8)
2890         };
2891
2892         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2893         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2894         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2895         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2896 }
2897
2898 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2899 {
2900         static const struct phy_reg phy_reg_init[] = {
2901                 /* Enable Delay cap */
2902                 { 0x1f, 0x0004 },
2903                 { 0x1f, 0x0007 },
2904                 { 0x1e, 0x00ac },
2905                 { 0x18, 0x0006 },
2906                 { 0x1f, 0x0002 },
2907                 { 0x1f, 0x0000 },
2908                 { 0x1f, 0x0000 },
2909
2910                 /* Channel estimation fine tune */
2911                 { 0x1f, 0x0003 },
2912                 { 0x09, 0xa20f },
2913                 { 0x1f, 0x0000 },
2914                 { 0x1f, 0x0000 },
2915
2916                 /* Green Setting */
2917                 { 0x1f, 0x0005 },
2918                 { 0x05, 0x8b5b },
2919                 { 0x06, 0x9222 },
2920                 { 0x05, 0x8b6d },
2921                 { 0x06, 0x8000 },
2922                 { 0x05, 0x8b76 },
2923                 { 0x06, 0x8000 },
2924                 { 0x1f, 0x0000 }
2925         };
2926
2927         rtl_apply_firmware(tp);
2928
2929         rtl_writephy_batch(tp, phy_reg_init);
2930
2931         /* For 4-corner performance improve */
2932         rtl_writephy(tp, 0x1f, 0x0005);
2933         rtl_writephy(tp, 0x05, 0x8b80);
2934         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2935         rtl_writephy(tp, 0x1f, 0x0000);
2936
2937         /* PHY auto speed down */
2938         rtl_writephy(tp, 0x1f, 0x0004);
2939         rtl_writephy(tp, 0x1f, 0x0007);
2940         rtl_writephy(tp, 0x1e, 0x002d);
2941         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2942         rtl_writephy(tp, 0x1f, 0x0002);
2943         rtl_writephy(tp, 0x1f, 0x0000);
2944         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2945
2946         /* improve 10M EEE waveform */
2947         rtl_writephy(tp, 0x1f, 0x0005);
2948         rtl_writephy(tp, 0x05, 0x8b86);
2949         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2950         rtl_writephy(tp, 0x1f, 0x0000);
2951
2952         /* Improve 2-pair detection performance */
2953         rtl_writephy(tp, 0x1f, 0x0005);
2954         rtl_writephy(tp, 0x05, 0x8b85);
2955         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
2956         rtl_writephy(tp, 0x1f, 0x0000);
2957
2958         rtl8168f_config_eee_phy(tp);
2959         rtl_enable_eee(tp);
2960
2961         /* Green feature */
2962         rtl_writephy(tp, 0x1f, 0x0003);
2963         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
2964         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
2965         rtl_writephy(tp, 0x1f, 0x0000);
2966         rtl_writephy(tp, 0x1f, 0x0005);
2967         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
2968         rtl_writephy(tp, 0x1f, 0x0000);
2969
2970         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2971         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
2972 }
2973
2974 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
2975 {
2976         /* For 4-corner performance improve */
2977         rtl_writephy(tp, 0x1f, 0x0005);
2978         rtl_writephy(tp, 0x05, 0x8b80);
2979         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
2980         rtl_writephy(tp, 0x1f, 0x0000);
2981
2982         /* PHY auto speed down */
2983         rtl_writephy(tp, 0x1f, 0x0007);
2984         rtl_writephy(tp, 0x1e, 0x002d);
2985         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
2986         rtl_writephy(tp, 0x1f, 0x0000);
2987         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2988
2989         /* Improve 10M EEE waveform */
2990         rtl_writephy(tp, 0x1f, 0x0005);
2991         rtl_writephy(tp, 0x05, 0x8b86);
2992         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2993         rtl_writephy(tp, 0x1f, 0x0000);
2994
2995         rtl8168f_config_eee_phy(tp);
2996         rtl_enable_eee(tp);
2997 }
2998
2999 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3000 {
3001         static const struct phy_reg phy_reg_init[] = {
3002                 /* Channel estimation fine tune */
3003                 { 0x1f, 0x0003 },
3004                 { 0x09, 0xa20f },
3005                 { 0x1f, 0x0000 },
3006
3007                 /* Modify green table for giga & fnet */
3008                 { 0x1f, 0x0005 },
3009                 { 0x05, 0x8b55 },
3010                 { 0x06, 0x0000 },
3011                 { 0x05, 0x8b5e },
3012                 { 0x06, 0x0000 },
3013                 { 0x05, 0x8b67 },
3014                 { 0x06, 0x0000 },
3015                 { 0x05, 0x8b70 },
3016                 { 0x06, 0x0000 },
3017                 { 0x1f, 0x0000 },
3018                 { 0x1f, 0x0007 },
3019                 { 0x1e, 0x0078 },
3020                 { 0x17, 0x0000 },
3021                 { 0x19, 0x00fb },
3022                 { 0x1f, 0x0000 },
3023
3024                 /* Modify green table for 10M */
3025                 { 0x1f, 0x0005 },
3026                 { 0x05, 0x8b79 },
3027                 { 0x06, 0xaa00 },
3028                 { 0x1f, 0x0000 },
3029
3030                 /* Disable hiimpedance detection (RTCT) */
3031                 { 0x1f, 0x0003 },
3032                 { 0x01, 0x328a },
3033                 { 0x1f, 0x0000 }
3034         };
3035
3036         rtl_apply_firmware(tp);
3037
3038         rtl_writephy_batch(tp, phy_reg_init);
3039
3040         rtl8168f_hw_phy_config(tp);
3041
3042         /* Improve 2-pair detection performance */
3043         rtl_writephy(tp, 0x1f, 0x0005);
3044         rtl_writephy(tp, 0x05, 0x8b85);
3045         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3046         rtl_writephy(tp, 0x1f, 0x0000);
3047 }
3048
3049 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3050 {
3051         rtl_apply_firmware(tp);
3052
3053         rtl8168f_hw_phy_config(tp);
3054 }
3055
3056 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3057 {
3058         static const struct phy_reg phy_reg_init[] = {
3059                 /* Channel estimation fine tune */
3060                 { 0x1f, 0x0003 },
3061                 { 0x09, 0xa20f },
3062                 { 0x1f, 0x0000 },
3063
3064                 /* Modify green table for giga & fnet */
3065                 { 0x1f, 0x0005 },
3066                 { 0x05, 0x8b55 },
3067                 { 0x06, 0x0000 },
3068                 { 0x05, 0x8b5e },
3069                 { 0x06, 0x0000 },
3070                 { 0x05, 0x8b67 },
3071                 { 0x06, 0x0000 },
3072                 { 0x05, 0x8b70 },
3073                 { 0x06, 0x0000 },
3074                 { 0x1f, 0x0000 },
3075                 { 0x1f, 0x0007 },
3076                 { 0x1e, 0x0078 },
3077                 { 0x17, 0x0000 },
3078                 { 0x19, 0x00aa },
3079                 { 0x1f, 0x0000 },
3080
3081                 /* Modify green table for 10M */
3082                 { 0x1f, 0x0005 },
3083                 { 0x05, 0x8b79 },
3084                 { 0x06, 0xaa00 },
3085                 { 0x1f, 0x0000 },
3086
3087                 /* Disable hiimpedance detection (RTCT) */
3088                 { 0x1f, 0x0003 },
3089                 { 0x01, 0x328a },
3090                 { 0x1f, 0x0000 }
3091         };
3092
3093
3094         rtl_apply_firmware(tp);
3095
3096         rtl8168f_hw_phy_config(tp);
3097
3098         /* Improve 2-pair detection performance */
3099         rtl_writephy(tp, 0x1f, 0x0005);
3100         rtl_writephy(tp, 0x05, 0x8b85);
3101         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3102         rtl_writephy(tp, 0x1f, 0x0000);
3103
3104         rtl_writephy_batch(tp, phy_reg_init);
3105
3106         /* Modify green table for giga */
3107         rtl_writephy(tp, 0x1f, 0x0005);
3108         rtl_writephy(tp, 0x05, 0x8b54);
3109         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3110         rtl_writephy(tp, 0x05, 0x8b5d);
3111         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3112         rtl_writephy(tp, 0x05, 0x8a7c);
3113         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3114         rtl_writephy(tp, 0x05, 0x8a7f);
3115         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3116         rtl_writephy(tp, 0x05, 0x8a82);
3117         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3118         rtl_writephy(tp, 0x05, 0x8a85);
3119         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3120         rtl_writephy(tp, 0x05, 0x8a88);
3121         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3122         rtl_writephy(tp, 0x1f, 0x0000);
3123
3124         /* uc same-seed solution */
3125         rtl_writephy(tp, 0x1f, 0x0005);
3126         rtl_writephy(tp, 0x05, 0x8b85);
3127         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3128         rtl_writephy(tp, 0x1f, 0x0000);
3129
3130         /* Green feature */
3131         rtl_writephy(tp, 0x1f, 0x0003);
3132         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3133         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3134         rtl_writephy(tp, 0x1f, 0x0000);
3135 }
3136
3137 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3138 {
3139         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3140 }
3141
3142 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3143 {
3144         struct phy_device *phydev = tp->phydev;
3145
3146         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3147         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3148         phy_write(phydev, 0x1f, 0x0a43);
3149         phy_write(phydev, 0x13, 0x8084);
3150         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3151         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3152
3153         phy_write(phydev, 0x1f, 0x0000);
3154 }
3155
3156 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3157 {
3158         int ret;
3159
3160         rtl_apply_firmware(tp);
3161
3162         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3163         if (ret & BIT(8))
3164                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3165         else
3166                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3167
3168         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3169         if (ret & BIT(8))
3170                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3171         else
3172                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3173
3174         /* Enable PHY auto speed down */
3175         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3176
3177         rtl8168g_phy_adjust_10m_aldps(tp);
3178
3179         /* EEE auto-fallback function */
3180         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3181
3182         /* Enable UC LPF tune function */
3183         rtl_writephy(tp, 0x1f, 0x0a43);
3184         rtl_writephy(tp, 0x13, 0x8012);
3185         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3186
3187         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3188
3189         /* Improve SWR Efficiency */
3190         rtl_writephy(tp, 0x1f, 0x0bcd);
3191         rtl_writephy(tp, 0x14, 0x5065);
3192         rtl_writephy(tp, 0x14, 0xd065);
3193         rtl_writephy(tp, 0x1f, 0x0bc8);
3194         rtl_writephy(tp, 0x11, 0x5655);
3195         rtl_writephy(tp, 0x1f, 0x0bcd);
3196         rtl_writephy(tp, 0x14, 0x1065);
3197         rtl_writephy(tp, 0x14, 0x9065);
3198         rtl_writephy(tp, 0x14, 0x1065);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200
3201         rtl8168g_disable_aldps(tp);
3202         rtl8168g_config_eee_phy(tp);
3203         rtl_enable_eee(tp);
3204 }
3205
3206 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3207 {
3208         rtl_apply_firmware(tp);
3209         rtl8168g_config_eee_phy(tp);
3210         rtl_enable_eee(tp);
3211 }
3212
3213 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3214 {
3215         u16 dout_tapbin;
3216         u32 data;
3217
3218         rtl_apply_firmware(tp);
3219
3220         /* CHN EST parameters adjust - giga master */
3221         rtl_writephy(tp, 0x1f, 0x0a43);
3222         rtl_writephy(tp, 0x13, 0x809b);
3223         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3224         rtl_writephy(tp, 0x13, 0x80a2);
3225         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3226         rtl_writephy(tp, 0x13, 0x80a4);
3227         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3228         rtl_writephy(tp, 0x13, 0x809c);
3229         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3230         rtl_writephy(tp, 0x1f, 0x0000);
3231
3232         /* CHN EST parameters adjust - giga slave */
3233         rtl_writephy(tp, 0x1f, 0x0a43);
3234         rtl_writephy(tp, 0x13, 0x80ad);
3235         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3236         rtl_writephy(tp, 0x13, 0x80b4);
3237         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3238         rtl_writephy(tp, 0x13, 0x80ac);
3239         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3240         rtl_writephy(tp, 0x1f, 0x0000);
3241
3242         /* CHN EST parameters adjust - fnet */
3243         rtl_writephy(tp, 0x1f, 0x0a43);
3244         rtl_writephy(tp, 0x13, 0x808e);
3245         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3246         rtl_writephy(tp, 0x13, 0x8090);
3247         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3248         rtl_writephy(tp, 0x13, 0x8092);
3249         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3250         rtl_writephy(tp, 0x1f, 0x0000);
3251
3252         /* enable R-tune & PGA-retune function */
3253         dout_tapbin = 0;
3254         rtl_writephy(tp, 0x1f, 0x0a46);
3255         data = rtl_readphy(tp, 0x13);
3256         data &= 3;
3257         data <<= 2;
3258         dout_tapbin |= data;
3259         data = rtl_readphy(tp, 0x12);
3260         data &= 0xc000;
3261         data >>= 14;
3262         dout_tapbin |= data;
3263         dout_tapbin = ~(dout_tapbin^0x08);
3264         dout_tapbin <<= 12;
3265         dout_tapbin &= 0xf000;
3266         rtl_writephy(tp, 0x1f, 0x0a43);
3267         rtl_writephy(tp, 0x13, 0x827a);
3268         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3269         rtl_writephy(tp, 0x13, 0x827b);
3270         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3271         rtl_writephy(tp, 0x13, 0x827c);
3272         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3273         rtl_writephy(tp, 0x13, 0x827d);
3274         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3275
3276         rtl_writephy(tp, 0x1f, 0x0a43);
3277         rtl_writephy(tp, 0x13, 0x0811);
3278         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3279         rtl_writephy(tp, 0x1f, 0x0a42);
3280         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3281         rtl_writephy(tp, 0x1f, 0x0000);
3282
3283         /* enable GPHY 10M */
3284         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3285
3286         /* SAR ADC performance */
3287         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3288
3289         rtl_writephy(tp, 0x1f, 0x0a43);
3290         rtl_writephy(tp, 0x13, 0x803f);
3291         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3292         rtl_writephy(tp, 0x13, 0x8047);
3293         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3294         rtl_writephy(tp, 0x13, 0x804f);
3295         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3296         rtl_writephy(tp, 0x13, 0x8057);
3297         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3298         rtl_writephy(tp, 0x13, 0x805f);
3299         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3300         rtl_writephy(tp, 0x13, 0x8067);
3301         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3302         rtl_writephy(tp, 0x13, 0x806f);
3303         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3304         rtl_writephy(tp, 0x1f, 0x0000);
3305
3306         /* disable phy pfm mode */
3307         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3308
3309         rtl8168g_disable_aldps(tp);
3310         rtl8168h_config_eee_phy(tp);
3311         rtl_enable_eee(tp);
3312 }
3313
3314 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3315 {
3316         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3317         u16 rlen;
3318         u32 data;
3319
3320         rtl_apply_firmware(tp);
3321
3322         /* CHIN EST parameter update */
3323         rtl_writephy(tp, 0x1f, 0x0a43);
3324         rtl_writephy(tp, 0x13, 0x808a);
3325         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3326         rtl_writephy(tp, 0x1f, 0x0000);
3327
3328         /* enable R-tune & PGA-retune function */
3329         rtl_writephy(tp, 0x1f, 0x0a43);
3330         rtl_writephy(tp, 0x13, 0x0811);
3331         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3332         rtl_writephy(tp, 0x1f, 0x0a42);
3333         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3334         rtl_writephy(tp, 0x1f, 0x0000);
3335
3336         /* enable GPHY 10M */
3337         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3338
3339         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3340         data = r8168_mac_ocp_read(tp, 0xdd02);
3341         ioffset_p3 = ((data & 0x80)>>7);
3342         ioffset_p3 <<= 3;
3343
3344         data = r8168_mac_ocp_read(tp, 0xdd00);
3345         ioffset_p3 |= ((data & (0xe000))>>13);
3346         ioffset_p2 = ((data & (0x1e00))>>9);
3347         ioffset_p1 = ((data & (0x01e0))>>5);
3348         ioffset_p0 = ((data & 0x0010)>>4);
3349         ioffset_p0 <<= 3;
3350         ioffset_p0 |= (data & (0x07));
3351         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3352
3353         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3354             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3355                 rtl_writephy(tp, 0x1f, 0x0bcf);
3356                 rtl_writephy(tp, 0x16, data);
3357                 rtl_writephy(tp, 0x1f, 0x0000);
3358         }
3359
3360         /* Modify rlen (TX LPF corner frequency) level */
3361         rtl_writephy(tp, 0x1f, 0x0bcd);
3362         data = rtl_readphy(tp, 0x16);
3363         data &= 0x000f;
3364         rlen = 0;
3365         if (data > 3)
3366                 rlen = data - 3;
3367         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3368         rtl_writephy(tp, 0x17, data);
3369         rtl_writephy(tp, 0x1f, 0x0bcd);
3370         rtl_writephy(tp, 0x1f, 0x0000);
3371
3372         /* disable phy pfm mode */
3373         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3374
3375         rtl8168g_disable_aldps(tp);
3376         rtl8168g_config_eee_phy(tp);
3377         rtl_enable_eee(tp);
3378 }
3379
3380 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3381 {
3382         /* Enable PHY auto speed down */
3383         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3384
3385         rtl8168g_phy_adjust_10m_aldps(tp);
3386
3387         /* Enable EEE auto-fallback function */
3388         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3389
3390         /* Enable UC LPF tune function */
3391         rtl_writephy(tp, 0x1f, 0x0a43);
3392         rtl_writephy(tp, 0x13, 0x8012);
3393         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3394         rtl_writephy(tp, 0x1f, 0x0000);
3395
3396         /* set rg_sel_sdm_rate */
3397         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3398
3399         rtl8168g_disable_aldps(tp);
3400         rtl8168g_config_eee_phy(tp);
3401         rtl_enable_eee(tp);
3402 }
3403
3404 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3405 {
3406         rtl8168g_phy_adjust_10m_aldps(tp);
3407
3408         /* Enable UC LPF tune function */
3409         rtl_writephy(tp, 0x1f, 0x0a43);
3410         rtl_writephy(tp, 0x13, 0x8012);
3411         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3412         rtl_writephy(tp, 0x1f, 0x0000);
3413
3414         /* Set rg_sel_sdm_rate */
3415         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3416
3417         /* Channel estimation parameters */
3418         rtl_writephy(tp, 0x1f, 0x0a43);
3419         rtl_writephy(tp, 0x13, 0x80f3);
3420         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3421         rtl_writephy(tp, 0x13, 0x80f0);
3422         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3423         rtl_writephy(tp, 0x13, 0x80ef);
3424         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3425         rtl_writephy(tp, 0x13, 0x80f6);
3426         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3427         rtl_writephy(tp, 0x13, 0x80ec);
3428         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3429         rtl_writephy(tp, 0x13, 0x80ed);
3430         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3431         rtl_writephy(tp, 0x13, 0x80f2);
3432         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3433         rtl_writephy(tp, 0x13, 0x80f4);
3434         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3435         rtl_writephy(tp, 0x1f, 0x0a43);
3436         rtl_writephy(tp, 0x13, 0x8110);
3437         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3438         rtl_writephy(tp, 0x13, 0x810f);
3439         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3440         rtl_writephy(tp, 0x13, 0x8111);
3441         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3442         rtl_writephy(tp, 0x13, 0x8113);
3443         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3444         rtl_writephy(tp, 0x13, 0x8115);
3445         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3446         rtl_writephy(tp, 0x13, 0x810e);
3447         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3448         rtl_writephy(tp, 0x13, 0x810c);
3449         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3450         rtl_writephy(tp, 0x13, 0x810b);
3451         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3452         rtl_writephy(tp, 0x1f, 0x0a43);
3453         rtl_writephy(tp, 0x13, 0x80d1);
3454         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3455         rtl_writephy(tp, 0x13, 0x80cd);
3456         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3457         rtl_writephy(tp, 0x13, 0x80d3);
3458         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3459         rtl_writephy(tp, 0x13, 0x80d5);
3460         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3461         rtl_writephy(tp, 0x13, 0x80d7);
3462         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3463
3464         /* Force PWM-mode */
3465         rtl_writephy(tp, 0x1f, 0x0bcd);
3466         rtl_writephy(tp, 0x14, 0x5065);
3467         rtl_writephy(tp, 0x14, 0xd065);
3468         rtl_writephy(tp, 0x1f, 0x0bc8);
3469         rtl_writephy(tp, 0x12, 0x00ed);
3470         rtl_writephy(tp, 0x1f, 0x0bcd);
3471         rtl_writephy(tp, 0x14, 0x1065);
3472         rtl_writephy(tp, 0x14, 0x9065);
3473         rtl_writephy(tp, 0x14, 0x1065);
3474         rtl_writephy(tp, 0x1f, 0x0000);
3475
3476         rtl8168g_disable_aldps(tp);
3477         rtl8168g_config_eee_phy(tp);
3478         rtl_enable_eee(tp);
3479 }
3480
3481 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3482 {
3483         static const struct phy_reg phy_reg_init[] = {
3484                 { 0x1f, 0x0003 },
3485                 { 0x08, 0x441d },
3486                 { 0x01, 0x9100 },
3487                 { 0x1f, 0x0000 }
3488         };
3489
3490         rtl_writephy(tp, 0x1f, 0x0000);
3491         rtl_patchphy(tp, 0x11, 1 << 12);
3492         rtl_patchphy(tp, 0x19, 1 << 13);
3493         rtl_patchphy(tp, 0x10, 1 << 15);
3494
3495         rtl_writephy_batch(tp, phy_reg_init);
3496 }
3497
3498 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3499 {
3500         static const struct phy_reg phy_reg_init[] = {
3501                 { 0x1f, 0x0005 },
3502                 { 0x1a, 0x0000 },
3503                 { 0x1f, 0x0000 },
3504
3505                 { 0x1f, 0x0004 },
3506                 { 0x1c, 0x0000 },
3507                 { 0x1f, 0x0000 },
3508
3509                 { 0x1f, 0x0001 },
3510                 { 0x15, 0x7701 },
3511                 { 0x1f, 0x0000 }
3512         };
3513
3514         /* Disable ALDPS before ram code */
3515         rtl_writephy(tp, 0x1f, 0x0000);
3516         rtl_writephy(tp, 0x18, 0x0310);
3517         msleep(100);
3518
3519         rtl_apply_firmware(tp);
3520
3521         rtl_writephy_batch(tp, phy_reg_init);
3522 }
3523
3524 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3525 {
3526         /* Disable ALDPS before setting firmware */
3527         rtl_writephy(tp, 0x1f, 0x0000);
3528         rtl_writephy(tp, 0x18, 0x0310);
3529         msleep(20);
3530
3531         rtl_apply_firmware(tp);
3532
3533         /* EEE setting */
3534         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3535         rtl_writephy(tp, 0x1f, 0x0004);
3536         rtl_writephy(tp, 0x10, 0x401f);
3537         rtl_writephy(tp, 0x19, 0x7030);
3538         rtl_writephy(tp, 0x1f, 0x0000);
3539 }
3540
3541 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3542 {
3543         static const struct phy_reg phy_reg_init[] = {
3544                 { 0x1f, 0x0004 },
3545                 { 0x10, 0xc07f },
3546                 { 0x19, 0x7030 },
3547                 { 0x1f, 0x0000 }
3548         };
3549
3550         /* Disable ALDPS before ram code */
3551         rtl_writephy(tp, 0x1f, 0x0000);
3552         rtl_writephy(tp, 0x18, 0x0310);
3553         msleep(100);
3554
3555         rtl_apply_firmware(tp);
3556
3557         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3558         rtl_writephy_batch(tp, phy_reg_init);
3559
3560         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3561 }
3562
3563 static void rtl_hw_phy_config(struct net_device *dev)
3564 {
3565         static const rtl_generic_fct phy_configs[] = {
3566                 /* PCI devices. */
3567                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3568                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3569                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3570                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3571                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3572                 /* PCI-E devices. */
3573                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3574                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3575                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3576                 [RTL_GIGA_MAC_VER_10] = NULL,
3577                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3578                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3579                 [RTL_GIGA_MAC_VER_13] = NULL,
3580                 [RTL_GIGA_MAC_VER_14] = NULL,
3581                 [RTL_GIGA_MAC_VER_15] = NULL,
3582                 [RTL_GIGA_MAC_VER_16] = NULL,
3583                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3584                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3585                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3586                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3587                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3588                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3589                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3590                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3591                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3592                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3593                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3594                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3595                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3596                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3597                 [RTL_GIGA_MAC_VER_31] = NULL,
3598                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3599                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3600                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3601                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3602                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3603                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3604                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3605                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3606                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3607                 [RTL_GIGA_MAC_VER_41] = NULL,
3608                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3609                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3610                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3611                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3612                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3613                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3614                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3615                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3616                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3617                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3618         };
3619         struct rtl8169_private *tp = netdev_priv(dev);
3620
3621         if (phy_configs[tp->mac_version])
3622                 phy_configs[tp->mac_version](tp);
3623 }
3624
3625 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3626 {
3627         if (!test_and_set_bit(flag, tp->wk.flags))
3628                 schedule_work(&tp->wk.work);
3629 }
3630
3631 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3632 {
3633         rtl_hw_phy_config(dev);
3634
3635         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3636                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3637                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3638                 netif_dbg(tp, drv, dev,
3639                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3640                 RTL_W8(tp, 0x82, 0x01);
3641         }
3642
3643         /* We may have called phy_speed_down before */
3644         phy_speed_up(tp->phydev);
3645
3646         genphy_soft_reset(tp->phydev);
3647 }
3648
3649 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3650 {
3651         rtl_lock_work(tp);
3652
3653         rtl_unlock_config_regs(tp);
3654
3655         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3656         RTL_R32(tp, MAC4);
3657
3658         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3659         RTL_R32(tp, MAC0);
3660
3661         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3662                 rtl_rar_exgmac_set(tp, addr);
3663
3664         rtl_lock_config_regs(tp);
3665
3666         rtl_unlock_work(tp);
3667 }
3668
3669 static int rtl_set_mac_address(struct net_device *dev, void *p)
3670 {
3671         struct rtl8169_private *tp = netdev_priv(dev);
3672         struct device *d = tp_to_dev(tp);
3673         int ret;
3674
3675         ret = eth_mac_addr(dev, p);
3676         if (ret)
3677                 return ret;
3678
3679         pm_runtime_get_noresume(d);
3680
3681         if (pm_runtime_active(d))
3682                 rtl_rar_set(tp, dev->dev_addr);
3683
3684         pm_runtime_put_noidle(d);
3685
3686         return 0;
3687 }
3688
3689 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3690 {
3691         struct rtl8169_private *tp = netdev_priv(dev);
3692
3693         if (!netif_running(dev))
3694                 return -ENODEV;
3695
3696         return phy_mii_ioctl(tp->phydev, ifr, cmd);
3697 }
3698
3699 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3700 {
3701         switch (tp->mac_version) {
3702         case RTL_GIGA_MAC_VER_25:
3703         case RTL_GIGA_MAC_VER_26:
3704         case RTL_GIGA_MAC_VER_29:
3705         case RTL_GIGA_MAC_VER_30:
3706         case RTL_GIGA_MAC_VER_32:
3707         case RTL_GIGA_MAC_VER_33:
3708         case RTL_GIGA_MAC_VER_34:
3709         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3710                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3711                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3712                 break;
3713         default:
3714                 break;
3715         }
3716 }
3717
3718 static void rtl_pll_power_down(struct rtl8169_private *tp)
3719 {
3720         if (r8168_check_dash(tp))
3721                 return;
3722
3723         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3724             tp->mac_version == RTL_GIGA_MAC_VER_33)
3725                 rtl_ephy_write(tp, 0x19, 0xff64);
3726
3727         if (device_may_wakeup(tp_to_dev(tp))) {
3728                 phy_speed_down(tp->phydev, false);
3729                 rtl_wol_suspend_quirk(tp);
3730                 return;
3731         }
3732
3733         switch (tp->mac_version) {
3734         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3735         case RTL_GIGA_MAC_VER_37:
3736         case RTL_GIGA_MAC_VER_39:
3737         case RTL_GIGA_MAC_VER_43:
3738         case RTL_GIGA_MAC_VER_44:
3739         case RTL_GIGA_MAC_VER_45:
3740         case RTL_GIGA_MAC_VER_46:
3741         case RTL_GIGA_MAC_VER_47:
3742         case RTL_GIGA_MAC_VER_48:
3743         case RTL_GIGA_MAC_VER_50:
3744         case RTL_GIGA_MAC_VER_51:
3745                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3746                 break;
3747         case RTL_GIGA_MAC_VER_40:
3748         case RTL_GIGA_MAC_VER_41:
3749         case RTL_GIGA_MAC_VER_49:
3750                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3751                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3752                 break;
3753         default:
3754                 break;
3755         }
3756 }
3757
3758 static void rtl_pll_power_up(struct rtl8169_private *tp)
3759 {
3760         switch (tp->mac_version) {
3761         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3762         case RTL_GIGA_MAC_VER_37:
3763         case RTL_GIGA_MAC_VER_39:
3764         case RTL_GIGA_MAC_VER_43:
3765                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3766                 break;
3767         case RTL_GIGA_MAC_VER_44:
3768         case RTL_GIGA_MAC_VER_45:
3769         case RTL_GIGA_MAC_VER_46:
3770         case RTL_GIGA_MAC_VER_47:
3771         case RTL_GIGA_MAC_VER_48:
3772         case RTL_GIGA_MAC_VER_50:
3773         case RTL_GIGA_MAC_VER_51:
3774                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3775                 break;
3776         case RTL_GIGA_MAC_VER_40:
3777         case RTL_GIGA_MAC_VER_41:
3778         case RTL_GIGA_MAC_VER_49:
3779                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3780                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3781                 break;
3782         default:
3783                 break;
3784         }
3785
3786         phy_resume(tp->phydev);
3787         /* give MAC/PHY some time to resume */
3788         msleep(20);
3789 }
3790
3791 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3792 {
3793         switch (tp->mac_version) {
3794         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3795         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3796                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3797                 break;
3798         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3799         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3800         case RTL_GIGA_MAC_VER_38:
3801                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3802                 break;
3803         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3804                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3805                 break;
3806         default:
3807                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3808                 break;
3809         }
3810 }
3811
3812 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3813 {
3814         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3815 }
3816
3817 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3818 {
3819         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3820         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3821         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3822 }
3823
3824 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3825 {
3826         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3827         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3828         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3829 }
3830
3831 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3832 {
3833         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3834 }
3835
3836 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3837 {
3838         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3839 }
3840
3841 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3842 {
3843         RTL_W8(tp, MaxTxPacketSize, 0x3f);
3844         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3845         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3846         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3847 }
3848
3849 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3850 {
3851         RTL_W8(tp, MaxTxPacketSize, 0x0c);
3852         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3853         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3854         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3855 }
3856
3857 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3858 {
3859         rtl_tx_performance_tweak(tp,
3860                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3861 }
3862
3863 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3864 {
3865         rtl_tx_performance_tweak(tp,
3866                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3867 }
3868
3869 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3870 {
3871         r8168b_0_hw_jumbo_enable(tp);
3872
3873         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3874 }
3875
3876 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3877 {
3878         r8168b_0_hw_jumbo_disable(tp);
3879
3880         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3881 }
3882
3883 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3884 {
3885         rtl_unlock_config_regs(tp);
3886         switch (tp->mac_version) {
3887         case RTL_GIGA_MAC_VER_11:
3888                 r8168b_0_hw_jumbo_enable(tp);
3889                 break;
3890         case RTL_GIGA_MAC_VER_12:
3891         case RTL_GIGA_MAC_VER_17:
3892                 r8168b_1_hw_jumbo_enable(tp);
3893                 break;
3894         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3895                 r8168c_hw_jumbo_enable(tp);
3896                 break;
3897         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3898                 r8168dp_hw_jumbo_enable(tp);
3899                 break;
3900         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3901                 r8168e_hw_jumbo_enable(tp);
3902                 break;
3903         default:
3904                 break;
3905         }
3906         rtl_lock_config_regs(tp);
3907 }
3908
3909 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3910 {
3911         rtl_unlock_config_regs(tp);
3912         switch (tp->mac_version) {
3913         case RTL_GIGA_MAC_VER_11:
3914                 r8168b_0_hw_jumbo_disable(tp);
3915                 break;
3916         case RTL_GIGA_MAC_VER_12:
3917         case RTL_GIGA_MAC_VER_17:
3918                 r8168b_1_hw_jumbo_disable(tp);
3919                 break;
3920         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3921                 r8168c_hw_jumbo_disable(tp);
3922                 break;
3923         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3924                 r8168dp_hw_jumbo_disable(tp);
3925                 break;
3926         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3927                 r8168e_hw_jumbo_disable(tp);
3928                 break;
3929         default:
3930                 break;
3931         }
3932         rtl_lock_config_regs(tp);
3933 }
3934
3935 DECLARE_RTL_COND(rtl_chipcmd_cond)
3936 {
3937         return RTL_R8(tp, ChipCmd) & CmdReset;
3938 }
3939
3940 static void rtl_hw_reset(struct rtl8169_private *tp)
3941 {
3942         RTL_W8(tp, ChipCmd, CmdReset);
3943
3944         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
3945 }
3946
3947 static void rtl_request_firmware(struct rtl8169_private *tp)
3948 {
3949         struct rtl_fw *rtl_fw;
3950
3951         /* firmware loaded already or no firmware available */
3952         if (tp->rtl_fw || !tp->fw_name)
3953                 return;
3954
3955         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3956         if (!rtl_fw) {
3957                 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
3958                 return;
3959         }
3960
3961         rtl_fw->phy_write = rtl_writephy;
3962         rtl_fw->phy_read = rtl_readphy;
3963         rtl_fw->mac_mcu_write = mac_mcu_write;
3964         rtl_fw->mac_mcu_read = mac_mcu_read;
3965         rtl_fw->fw_name = tp->fw_name;
3966         rtl_fw->dev = tp_to_dev(tp);
3967
3968         if (rtl_fw_request_firmware(rtl_fw))
3969                 kfree(rtl_fw);
3970         else
3971                 tp->rtl_fw = rtl_fw;
3972 }
3973
3974 static void rtl_rx_close(struct rtl8169_private *tp)
3975 {
3976         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3977 }
3978
3979 DECLARE_RTL_COND(rtl_npq_cond)
3980 {
3981         return RTL_R8(tp, TxPoll) & NPQ;
3982 }
3983
3984 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
3985 {
3986         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
3987 }
3988
3989 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3990 {
3991         /* Disable interrupts */
3992         rtl8169_irq_mask_and_ack(tp);
3993
3994         rtl_rx_close(tp);
3995
3996         switch (tp->mac_version) {
3997         case RTL_GIGA_MAC_VER_27:
3998         case RTL_GIGA_MAC_VER_28:
3999         case RTL_GIGA_MAC_VER_31:
4000                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4001                 break;
4002         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4003         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4004                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4005                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4006                 break;
4007         default:
4008                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4009                 udelay(100);
4010                 break;
4011         }
4012
4013         rtl_hw_reset(tp);
4014 }
4015
4016 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4017 {
4018         u32 val = TX_DMA_BURST << TxDMAShift |
4019                   InterFrameGap << TxInterFrameGapShift;
4020
4021         if (rtl_is_8168evl_up(tp))
4022                 val |= TXCFG_AUTO_FIFO;
4023
4024         RTL_W32(tp, TxConfig, val);
4025 }
4026
4027 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4028 {
4029         /* Low hurts. Let's disable the filtering. */
4030         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4031 }
4032
4033 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4034 {
4035         /*
4036          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4037          * register to be written before TxDescAddrLow to work.
4038          * Switching from MMIO to I/O access fixes the issue as well.
4039          */
4040         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4041         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4042         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4043         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4044 }
4045
4046 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4047 {
4048         u32 val;
4049
4050         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4051                 val = 0x000fff00;
4052         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4053                 val = 0x00ffff00;
4054         else
4055                 return;
4056
4057         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4058                 val |= 0xff;
4059
4060         RTL_W32(tp, 0x7c, val);
4061 }
4062
4063 static void rtl_set_rx_mode(struct net_device *dev)
4064 {
4065         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4066         /* Multicast hash filter */
4067         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4068         struct rtl8169_private *tp = netdev_priv(dev);
4069         u32 tmp;
4070
4071         if (dev->flags & IFF_PROMISC) {
4072                 /* Unconditionally log net taps. */
4073                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4074                 rx_mode |= AcceptAllPhys;
4075         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4076                    dev->flags & IFF_ALLMULTI ||
4077                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
4078                 /* accept all multicasts */
4079         } else if (netdev_mc_empty(dev)) {
4080                 rx_mode &= ~AcceptMulticast;
4081         } else {
4082                 struct netdev_hw_addr *ha;
4083
4084                 mc_filter[1] = mc_filter[0] = 0;
4085                 netdev_for_each_mc_addr(ha, dev) {
4086                         u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4087                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4088                 }
4089
4090                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4091                         tmp = mc_filter[0];
4092                         mc_filter[0] = swab32(mc_filter[1]);
4093                         mc_filter[1] = swab32(tmp);
4094                 }
4095         }
4096
4097         if (dev->features & NETIF_F_RXALL)
4098                 rx_mode |= (AcceptErr | AcceptRunt);
4099
4100         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4101         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4102
4103         tmp = RTL_R32(tp, RxConfig);
4104         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4105 }
4106
4107 DECLARE_RTL_COND(rtl_csiar_cond)
4108 {
4109         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4110 }
4111
4112 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4113 {
4114         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4115
4116         RTL_W32(tp, CSIDR, value);
4117         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4118                 CSIAR_BYTE_ENABLE | func << 16);
4119
4120         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4121 }
4122
4123 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4124 {
4125         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4126
4127         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4128                 CSIAR_BYTE_ENABLE);
4129
4130         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4131                 RTL_R32(tp, CSIDR) : ~0;
4132 }
4133
4134 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4135 {
4136         struct pci_dev *pdev = tp->pci_dev;
4137         u32 csi;
4138
4139         /* According to Realtek the value at config space address 0x070f
4140          * controls the L0s/L1 entrance latency. We try standard ECAM access
4141          * first and if it fails fall back to CSI.
4142          */
4143         if (pdev->cfg_size > 0x070f &&
4144             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4145                 return;
4146
4147         netdev_notice_once(tp->dev,
4148                 "No native access to PCI extended config space, falling back to CSI\n");
4149         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4150         rtl_csi_write(tp, 0x070c, csi | val << 24);
4151 }
4152
4153 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4154 {
4155         rtl_csi_access_enable(tp, 0x27);
4156 }
4157
4158 struct ephy_info {
4159         unsigned int offset;
4160         u16 mask;
4161         u16 bits;
4162 };
4163
4164 static void __rtl_ephy_init(struct rtl8169_private *tp,
4165                             const struct ephy_info *e, int len)
4166 {
4167         u16 w;
4168
4169         while (len-- > 0) {
4170                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4171                 rtl_ephy_write(tp, e->offset, w);
4172                 e++;
4173         }
4174 }
4175
4176 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4177
4178 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4179 {
4180         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4181                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4182 }
4183
4184 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4185 {
4186         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4187                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4188 }
4189
4190 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4191 {
4192         /* work around an issue when PCI reset occurs during L2/L3 state */
4193         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4194 }
4195
4196 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4197 {
4198         /* Don't enable ASPM in the chip if OS can't control ASPM */
4199         if (enable && tp->aspm_manageable) {
4200                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4201                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4202         } else {
4203                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4204                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4205         }
4206
4207         udelay(10);
4208 }
4209
4210 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4211                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4212 {
4213         /* Usage of dynamic vs. static FIFO is controlled by bit
4214          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4215          */
4216         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4217         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4218 }
4219
4220 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4221                                           u8 low, u8 high)
4222 {
4223         /* FIFO thresholds for pause flow control */
4224         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4225         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4226 }
4227
4228 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4229 {
4230         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4231
4232         if (tp->dev->mtu <= ETH_DATA_LEN) {
4233                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4234                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4235         }
4236 }
4237
4238 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4239 {
4240         rtl_hw_start_8168bb(tp);
4241
4242         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4243 }
4244
4245 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4246 {
4247         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4248
4249         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4250
4251         if (tp->dev->mtu <= ETH_DATA_LEN)
4252                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4253
4254         rtl_disable_clock_request(tp);
4255 }
4256
4257 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4258 {
4259         static const struct ephy_info e_info_8168cp[] = {
4260                 { 0x01, 0,      0x0001 },
4261                 { 0x02, 0x0800, 0x1000 },
4262                 { 0x03, 0,      0x0042 },
4263                 { 0x06, 0x0080, 0x0000 },
4264                 { 0x07, 0,      0x2000 }
4265         };
4266
4267         rtl_set_def_aspm_entry_latency(tp);
4268
4269         rtl_ephy_init(tp, e_info_8168cp);
4270
4271         __rtl_hw_start_8168cp(tp);
4272 }
4273
4274 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4275 {
4276         rtl_set_def_aspm_entry_latency(tp);
4277
4278         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4279
4280         if (tp->dev->mtu <= ETH_DATA_LEN)
4281                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4282 }
4283
4284 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4285 {
4286         rtl_set_def_aspm_entry_latency(tp);
4287
4288         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4289
4290         /* Magic. */
4291         RTL_W8(tp, DBG_REG, 0x20);
4292
4293         if (tp->dev->mtu <= ETH_DATA_LEN)
4294                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4295 }
4296
4297 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4298 {
4299         static const struct ephy_info e_info_8168c_1[] = {
4300                 { 0x02, 0x0800, 0x1000 },
4301                 { 0x03, 0,      0x0002 },
4302                 { 0x06, 0x0080, 0x0000 }
4303         };
4304
4305         rtl_set_def_aspm_entry_latency(tp);
4306
4307         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4308
4309         rtl_ephy_init(tp, e_info_8168c_1);
4310
4311         __rtl_hw_start_8168cp(tp);
4312 }
4313
4314 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4315 {
4316         static const struct ephy_info e_info_8168c_2[] = {
4317                 { 0x01, 0,      0x0001 },
4318                 { 0x03, 0x0400, 0x0020 }
4319         };
4320
4321         rtl_set_def_aspm_entry_latency(tp);
4322
4323         rtl_ephy_init(tp, e_info_8168c_2);
4324
4325         __rtl_hw_start_8168cp(tp);
4326 }
4327
4328 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4329 {
4330         rtl_hw_start_8168c_2(tp);
4331 }
4332
4333 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4334 {
4335         rtl_set_def_aspm_entry_latency(tp);
4336
4337         __rtl_hw_start_8168cp(tp);
4338 }
4339
4340 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4341 {
4342         rtl_set_def_aspm_entry_latency(tp);
4343
4344         rtl_disable_clock_request(tp);
4345
4346         if (tp->dev->mtu <= ETH_DATA_LEN)
4347                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4348 }
4349
4350 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4351 {
4352         rtl_set_def_aspm_entry_latency(tp);
4353
4354         if (tp->dev->mtu <= ETH_DATA_LEN)
4355                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4356
4357         rtl_disable_clock_request(tp);
4358 }
4359
4360 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4361 {
4362         static const struct ephy_info e_info_8168d_4[] = {
4363                 { 0x0b, 0x0000, 0x0048 },
4364                 { 0x19, 0x0020, 0x0050 },
4365                 { 0x0c, 0x0100, 0x0020 },
4366                 { 0x10, 0x0004, 0x0000 },
4367         };
4368
4369         rtl_set_def_aspm_entry_latency(tp);
4370
4371         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4372
4373         rtl_ephy_init(tp, e_info_8168d_4);
4374
4375         rtl_enable_clock_request(tp);
4376 }
4377
4378 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4379 {
4380         static const struct ephy_info e_info_8168e_1[] = {
4381                 { 0x00, 0x0200, 0x0100 },
4382                 { 0x00, 0x0000, 0x0004 },
4383                 { 0x06, 0x0002, 0x0001 },
4384                 { 0x06, 0x0000, 0x0030 },
4385                 { 0x07, 0x0000, 0x2000 },
4386                 { 0x00, 0x0000, 0x0020 },
4387                 { 0x03, 0x5800, 0x2000 },
4388                 { 0x03, 0x0000, 0x0001 },
4389                 { 0x01, 0x0800, 0x1000 },
4390                 { 0x07, 0x0000, 0x4000 },
4391                 { 0x1e, 0x0000, 0x2000 },
4392                 { 0x19, 0xffff, 0xfe6c },
4393                 { 0x0a, 0x0000, 0x0040 }
4394         };
4395
4396         rtl_set_def_aspm_entry_latency(tp);
4397
4398         rtl_ephy_init(tp, e_info_8168e_1);
4399
4400         if (tp->dev->mtu <= ETH_DATA_LEN)
4401                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4402
4403         rtl_disable_clock_request(tp);
4404
4405         /* Reset tx FIFO pointer */
4406         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4407         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4408
4409         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4410 }
4411
4412 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4413 {
4414         static const struct ephy_info e_info_8168e_2[] = {
4415                 { 0x09, 0x0000, 0x0080 },
4416                 { 0x19, 0x0000, 0x0224 },
4417                 { 0x00, 0x0000, 0x0004 },
4418                 { 0x0c, 0x3df0, 0x0200 },
4419         };
4420
4421         rtl_set_def_aspm_entry_latency(tp);
4422
4423         rtl_ephy_init(tp, e_info_8168e_2);
4424
4425         if (tp->dev->mtu <= ETH_DATA_LEN)
4426                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4427
4428         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4429         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4430         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4431         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4432         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4433         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4434         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4435
4436         rtl_disable_clock_request(tp);
4437
4438         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4439
4440         rtl8168_config_eee_mac(tp);
4441
4442         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4443         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4444         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4445
4446         rtl_hw_aspm_clkreq_enable(tp, true);
4447 }
4448
4449 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4450 {
4451         rtl_set_def_aspm_entry_latency(tp);
4452
4453         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4454
4455         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4456         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4457         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4458         rtl_reset_packet_filter(tp);
4459         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4460         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4461         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4462         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4463
4464         rtl_disable_clock_request(tp);
4465
4466         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4467         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4468         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4469         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4470
4471         rtl8168_config_eee_mac(tp);
4472 }
4473
4474 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4475 {
4476         static const struct ephy_info e_info_8168f_1[] = {
4477                 { 0x06, 0x00c0, 0x0020 },
4478                 { 0x08, 0x0001, 0x0002 },
4479                 { 0x09, 0x0000, 0x0080 },
4480                 { 0x19, 0x0000, 0x0224 },
4481                 { 0x00, 0x0000, 0x0004 },
4482                 { 0x0c, 0x3df0, 0x0200 },
4483         };
4484
4485         rtl_hw_start_8168f(tp);
4486
4487         rtl_ephy_init(tp, e_info_8168f_1);
4488
4489         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4490 }
4491
4492 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4493 {
4494         static const struct ephy_info e_info_8168f_1[] = {
4495                 { 0x06, 0x00c0, 0x0020 },
4496                 { 0x0f, 0xffff, 0x5200 },
4497                 { 0x19, 0x0000, 0x0224 },
4498                 { 0x00, 0x0000, 0x0004 },
4499                 { 0x0c, 0x3df0, 0x0200 },
4500         };
4501
4502         rtl_hw_start_8168f(tp);
4503         rtl_pcie_state_l2l3_disable(tp);
4504
4505         rtl_ephy_init(tp, e_info_8168f_1);
4506
4507         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4508 }
4509
4510 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4511 {
4512         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4513         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4514
4515         rtl_set_def_aspm_entry_latency(tp);
4516
4517         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4518
4519         rtl_reset_packet_filter(tp);
4520         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4521
4522         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4523
4524         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4525         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4526
4527         rtl8168_config_eee_mac(tp);
4528
4529         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4530         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4531
4532         rtl_pcie_state_l2l3_disable(tp);
4533 }
4534
4535 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4536 {
4537         static const struct ephy_info e_info_8168g_1[] = {
4538                 { 0x00, 0x0008, 0x0000 },
4539                 { 0x0c, 0x3ff0, 0x0820 },
4540                 { 0x1e, 0x0000, 0x0001 },
4541                 { 0x19, 0x8000, 0x0000 }
4542         };
4543
4544         rtl_hw_start_8168g(tp);
4545
4546         /* disable aspm and clock request before access ephy */
4547         rtl_hw_aspm_clkreq_enable(tp, false);
4548         rtl_ephy_init(tp, e_info_8168g_1);
4549         rtl_hw_aspm_clkreq_enable(tp, true);
4550 }
4551
4552 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4553 {
4554         static const struct ephy_info e_info_8168g_2[] = {
4555                 { 0x00, 0x0008, 0x0000 },
4556                 { 0x0c, 0x3ff0, 0x0820 },
4557                 { 0x19, 0xffff, 0x7c00 },
4558                 { 0x1e, 0xffff, 0x20eb },
4559                 { 0x0d, 0xffff, 0x1666 },
4560                 { 0x00, 0xffff, 0x10a3 },
4561                 { 0x06, 0xffff, 0xf050 },
4562                 { 0x04, 0x0000, 0x0010 },
4563                 { 0x1d, 0x4000, 0x0000 },
4564         };
4565
4566         rtl_hw_start_8168g(tp);
4567
4568         /* disable aspm and clock request before access ephy */
4569         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4570         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4571         rtl_ephy_init(tp, e_info_8168g_2);
4572 }
4573
4574 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4575 {
4576         static const struct ephy_info e_info_8411_2[] = {
4577                 { 0x00, 0x0008, 0x0000 },
4578                 { 0x0c, 0x37d0, 0x0820 },
4579                 { 0x1e, 0x0000, 0x0001 },
4580                 { 0x19, 0x8021, 0x0000 },
4581                 { 0x1e, 0x0000, 0x2000 },
4582                 { 0x0d, 0x0100, 0x0200 },
4583                 { 0x00, 0x0000, 0x0080 },
4584                 { 0x06, 0x0000, 0x0010 },
4585                 { 0x04, 0x0000, 0x0010 },
4586                 { 0x1d, 0x0000, 0x4000 },
4587         };
4588
4589         rtl_hw_start_8168g(tp);
4590
4591         /* disable aspm and clock request before access ephy */
4592         rtl_hw_aspm_clkreq_enable(tp, false);
4593         rtl_ephy_init(tp, e_info_8411_2);
4594
4595         /* The following Realtek-provided magic fixes an issue with the RX unit
4596          * getting confused after the PHY having been powered-down.
4597          */
4598         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4599         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4600         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4601         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4602         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4603         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4604         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4605         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4606         mdelay(3);
4607         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4608
4609         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4610         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4611         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4612         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4613         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4614         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4615         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4616         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4617         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4618         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4619         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4620         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4621         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4622         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4623         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4624         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4625         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4626         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4627         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4628         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4629         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4630         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4631         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4632         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4633         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4634         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4635         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4636         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4637         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4638         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4639         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4640         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4641         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4642         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4643         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4644         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4645         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4646         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4647         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4648         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4649         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4650         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4651         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4652         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4653         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4654         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4655         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4656         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4657         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4658         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4659         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4660         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4661         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4662         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4663         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4664         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4665         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4666         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4667         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4668         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4669         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4670         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4671         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4672         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4673         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4674         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4675         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4676         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4677         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4678         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4679         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4680         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4681         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4682         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4683         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4684         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4685         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4686         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4687         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4688         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4689         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4690         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4691         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4692         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4693         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4694         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4695         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4696         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4697         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4698         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4699         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4700         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4701         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4702         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4703         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4704         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4705         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4706         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4707         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4708         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4709         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4710         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4711         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4712         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4713         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4714         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4715         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4716         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4717         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4718         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4719         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4720
4721         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4722
4723         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4724         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4725         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4726         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4727         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4728         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4729         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4730
4731         rtl_hw_aspm_clkreq_enable(tp, true);
4732 }
4733
4734 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4735 {
4736         static const struct ephy_info e_info_8168h_1[] = {
4737                 { 0x1e, 0x0800, 0x0001 },
4738                 { 0x1d, 0x0000, 0x0800 },
4739                 { 0x05, 0xffff, 0x2089 },
4740                 { 0x06, 0xffff, 0x5881 },
4741                 { 0x04, 0xffff, 0x854a },
4742                 { 0x01, 0xffff, 0x068b }
4743         };
4744         int rg_saw_cnt;
4745
4746         /* disable aspm and clock request before access ephy */
4747         rtl_hw_aspm_clkreq_enable(tp, false);
4748         rtl_ephy_init(tp, e_info_8168h_1);
4749
4750         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4751         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4752
4753         rtl_set_def_aspm_entry_latency(tp);
4754
4755         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4756
4757         rtl_reset_packet_filter(tp);
4758
4759         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4760
4761         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4762
4763         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4764
4765         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4766
4767         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4768         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4769
4770         rtl8168_config_eee_mac(tp);
4771
4772         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4773         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4774
4775         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4776
4777         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4778
4779         rtl_pcie_state_l2l3_disable(tp);
4780
4781         rtl_writephy(tp, 0x1f, 0x0c42);
4782         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4783         rtl_writephy(tp, 0x1f, 0x0000);
4784         if (rg_saw_cnt > 0) {
4785                 u16 sw_cnt_1ms_ini;
4786
4787                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4788                 sw_cnt_1ms_ini &= 0x0fff;
4789                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4790         }
4791
4792         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4793         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4794         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4795         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4796
4797         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4798         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4799         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4800         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4801
4802         rtl_hw_aspm_clkreq_enable(tp, true);
4803 }
4804
4805 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4806 {
4807         rtl8168ep_stop_cmac(tp);
4808
4809         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4810         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4811
4812         rtl_set_def_aspm_entry_latency(tp);
4813
4814         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4815
4816         rtl_reset_packet_filter(tp);
4817
4818         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4819
4820         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4821
4822         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4823
4824         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4825         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4826
4827         rtl8168_config_eee_mac(tp);
4828
4829         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4830
4831         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4832
4833         rtl_pcie_state_l2l3_disable(tp);
4834 }
4835
4836 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4837 {
4838         static const struct ephy_info e_info_8168ep_1[] = {
4839                 { 0x00, 0xffff, 0x10ab },
4840                 { 0x06, 0xffff, 0xf030 },
4841                 { 0x08, 0xffff, 0x2006 },
4842                 { 0x0d, 0xffff, 0x1666 },
4843                 { 0x0c, 0x3ff0, 0x0000 }
4844         };
4845
4846         /* disable aspm and clock request before access ephy */
4847         rtl_hw_aspm_clkreq_enable(tp, false);
4848         rtl_ephy_init(tp, e_info_8168ep_1);
4849
4850         rtl_hw_start_8168ep(tp);
4851
4852         rtl_hw_aspm_clkreq_enable(tp, true);
4853 }
4854
4855 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4856 {
4857         static const struct ephy_info e_info_8168ep_2[] = {
4858                 { 0x00, 0xffff, 0x10a3 },
4859                 { 0x19, 0xffff, 0xfc00 },
4860                 { 0x1e, 0xffff, 0x20ea }
4861         };
4862
4863         /* disable aspm and clock request before access ephy */
4864         rtl_hw_aspm_clkreq_enable(tp, false);
4865         rtl_ephy_init(tp, e_info_8168ep_2);
4866
4867         rtl_hw_start_8168ep(tp);
4868
4869         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4870         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4871
4872         rtl_hw_aspm_clkreq_enable(tp, true);
4873 }
4874
4875 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4876 {
4877         static const struct ephy_info e_info_8168ep_3[] = {
4878                 { 0x00, 0x0000, 0x0080 },
4879                 { 0x0d, 0x0100, 0x0200 },
4880                 { 0x19, 0x8021, 0x0000 },
4881                 { 0x1e, 0x0000, 0x2000 },
4882         };
4883
4884         /* disable aspm and clock request before access ephy */
4885         rtl_hw_aspm_clkreq_enable(tp, false);
4886         rtl_ephy_init(tp, e_info_8168ep_3);
4887
4888         rtl_hw_start_8168ep(tp);
4889
4890         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4891         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4892
4893         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4894         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4895         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4896
4897         rtl_hw_aspm_clkreq_enable(tp, true);
4898 }
4899
4900 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4901 {
4902         static const struct ephy_info e_info_8102e_1[] = {
4903                 { 0x01, 0, 0x6e65 },
4904                 { 0x02, 0, 0x091f },
4905                 { 0x03, 0, 0xc2f9 },
4906                 { 0x06, 0, 0xafb5 },
4907                 { 0x07, 0, 0x0e00 },
4908                 { 0x19, 0, 0xec80 },
4909                 { 0x01, 0, 0x2e65 },
4910                 { 0x01, 0, 0x6e65 }
4911         };
4912         u8 cfg1;
4913
4914         rtl_set_def_aspm_entry_latency(tp);
4915
4916         RTL_W8(tp, DBG_REG, FIX_NAK_1);
4917
4918         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4919
4920         RTL_W8(tp, Config1,
4921                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4922         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4923
4924         cfg1 = RTL_R8(tp, Config1);
4925         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4926                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4927
4928         rtl_ephy_init(tp, e_info_8102e_1);
4929 }
4930
4931 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4932 {
4933         rtl_set_def_aspm_entry_latency(tp);
4934
4935         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4936
4937         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4938         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4939 }
4940
4941 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4942 {
4943         rtl_hw_start_8102e_2(tp);
4944
4945         rtl_ephy_write(tp, 0x03, 0xc2f9);
4946 }
4947
4948 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4949 {
4950         static const struct ephy_info e_info_8105e_1[] = {
4951                 { 0x07, 0, 0x4000 },
4952                 { 0x19, 0, 0x0200 },
4953                 { 0x19, 0, 0x0020 },
4954                 { 0x1e, 0, 0x2000 },
4955                 { 0x03, 0, 0x0001 },
4956                 { 0x19, 0, 0x0100 },
4957                 { 0x19, 0, 0x0004 },
4958                 { 0x0a, 0, 0x0020 }
4959         };
4960
4961         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4962         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4963
4964         /* Disable Early Tally Counter */
4965         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4966
4967         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4968         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4969
4970         rtl_ephy_init(tp, e_info_8105e_1);
4971
4972         rtl_pcie_state_l2l3_disable(tp);
4973 }
4974
4975 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4976 {
4977         rtl_hw_start_8105e_1(tp);
4978         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4979 }
4980
4981 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4982 {
4983         static const struct ephy_info e_info_8402[] = {
4984                 { 0x19, 0xffff, 0xff64 },
4985                 { 0x1e, 0, 0x4000 }
4986         };
4987
4988         rtl_set_def_aspm_entry_latency(tp);
4989
4990         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4991         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4992
4993         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4994
4995         rtl_ephy_init(tp, e_info_8402);
4996
4997         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4998
4999         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5000         rtl_reset_packet_filter(tp);
5001         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5002         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5003         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5004
5005         rtl_pcie_state_l2l3_disable(tp);
5006 }
5007
5008 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5009 {
5010         rtl_hw_aspm_clkreq_enable(tp, false);
5011
5012         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5013         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5014
5015         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5016         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5017         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5018
5019         rtl_pcie_state_l2l3_disable(tp);
5020         rtl_hw_aspm_clkreq_enable(tp, true);
5021 }
5022
5023 static void rtl_hw_config(struct rtl8169_private *tp)
5024 {
5025         static const rtl_generic_fct hw_configs[] = {
5026                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5027                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5028                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5029                 [RTL_GIGA_MAC_VER_10] = NULL,
5030                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5031                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5032                 [RTL_GIGA_MAC_VER_13] = NULL,
5033                 [RTL_GIGA_MAC_VER_14] = NULL,
5034                 [RTL_GIGA_MAC_VER_15] = NULL,
5035                 [RTL_GIGA_MAC_VER_16] = NULL,
5036                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5037                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5038                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5039                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5040                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5041                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5042                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5043                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5044                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5045                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5046                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5047                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5048                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5049                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5050                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5051                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5052                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5053                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5054                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5055                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5056                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5057                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5058                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5059                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5060                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5061                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5062                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5063                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5064                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5065                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5066                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5067                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5068                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5069                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5070                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5071         };
5072
5073         if (hw_configs[tp->mac_version])
5074                 hw_configs[tp->mac_version](tp);
5075 }
5076
5077 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5078 {
5079         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5080             tp->mac_version == RTL_GIGA_MAC_VER_16)
5081                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5082                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5083
5084         if (rtl_is_8168evl_up(tp))
5085                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5086         else
5087                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5088
5089         rtl_hw_config(tp);
5090
5091         /* disable interrupt coalescing */
5092         RTL_W16(tp, IntrMitigate, 0x0000);
5093 }
5094
5095 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5096 {
5097         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5098                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5099
5100         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5101
5102         tp->cp_cmd |= PCIMulRW;
5103
5104         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5105             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5106                 netif_dbg(tp, drv, tp->dev,
5107                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5108                 tp->cp_cmd |= (1 << 14);
5109         }
5110
5111         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5112
5113         rtl8169_set_magic_reg(tp, tp->mac_version);
5114
5115         RTL_W32(tp, RxMissed, 0);
5116
5117         /* disable interrupt coalescing */
5118         RTL_W16(tp, IntrMitigate, 0x0000);
5119 }
5120
5121 static void rtl_hw_start(struct  rtl8169_private *tp)
5122 {
5123         rtl_unlock_config_regs(tp);
5124
5125         tp->cp_cmd &= CPCMD_MASK;
5126         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5127
5128         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5129                 rtl_hw_start_8169(tp);
5130         else
5131                 rtl_hw_start_8168(tp);
5132
5133         rtl_set_rx_max_size(tp);
5134         rtl_set_rx_tx_desc_registers(tp);
5135         rtl_lock_config_regs(tp);
5136
5137         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5138         RTL_R16(tp, CPlusCmd);
5139         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5140         rtl_init_rxcfg(tp);
5141         rtl_set_tx_config_registers(tp);
5142         rtl_set_rx_mode(tp->dev);
5143         rtl_irq_enable(tp);
5144 }
5145
5146 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5147 {
5148         struct rtl8169_private *tp = netdev_priv(dev);
5149
5150         if (new_mtu > ETH_DATA_LEN)
5151                 rtl_hw_jumbo_enable(tp);
5152         else
5153                 rtl_hw_jumbo_disable(tp);
5154
5155         dev->mtu = new_mtu;
5156         netdev_update_features(dev);
5157
5158         return 0;
5159 }
5160
5161 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5162 {
5163         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5164         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5165 }
5166
5167 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5168 {
5169         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5170
5171         /* Force memory writes to complete before releasing descriptor */
5172         dma_wmb();
5173
5174         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5175 }
5176
5177 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5178                                           struct RxDesc *desc)
5179 {
5180         struct device *d = tp_to_dev(tp);
5181         int node = dev_to_node(d);
5182         dma_addr_t mapping;
5183         struct page *data;
5184
5185         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5186         if (!data)
5187                 return NULL;
5188
5189         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5190         if (unlikely(dma_mapping_error(d, mapping))) {
5191                 if (net_ratelimit())
5192                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5193                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5194                 return NULL;
5195         }
5196
5197         desc->addr = cpu_to_le64(mapping);
5198         rtl8169_mark_to_asic(desc);
5199
5200         return data;
5201 }
5202
5203 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5204 {
5205         unsigned int i;
5206
5207         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5208                 dma_unmap_page(tp_to_dev(tp),
5209                                le64_to_cpu(tp->RxDescArray[i].addr),
5210                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5211                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5212                 tp->Rx_databuff[i] = NULL;
5213                 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5214         }
5215 }
5216
5217 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5218 {
5219         desc->opts1 |= cpu_to_le32(RingEnd);
5220 }
5221
5222 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5223 {
5224         unsigned int i;
5225
5226         for (i = 0; i < NUM_RX_DESC; i++) {
5227                 struct page *data;
5228
5229                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5230                 if (!data) {
5231                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5232                         goto err_out;
5233                 }
5234                 tp->Rx_databuff[i] = data;
5235         }
5236
5237         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5238         return 0;
5239
5240 err_out:
5241         rtl8169_rx_clear(tp);
5242         return -ENOMEM;
5243 }
5244
5245 static int rtl8169_init_ring(struct rtl8169_private *tp)
5246 {
5247         rtl8169_init_ring_indexes(tp);
5248
5249         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5250         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5251
5252         return rtl8169_rx_fill(tp);
5253 }
5254
5255 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5256                                  struct TxDesc *desc)
5257 {
5258         unsigned int len = tx_skb->len;
5259
5260         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5261
5262         desc->opts1 = 0x00;
5263         desc->opts2 = 0x00;
5264         desc->addr = 0x00;
5265         tx_skb->len = 0;
5266 }
5267
5268 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5269                                    unsigned int n)
5270 {
5271         unsigned int i;
5272
5273         for (i = 0; i < n; i++) {
5274                 unsigned int entry = (start + i) % NUM_TX_DESC;
5275                 struct ring_info *tx_skb = tp->tx_skb + entry;
5276                 unsigned int len = tx_skb->len;
5277
5278                 if (len) {
5279                         struct sk_buff *skb = tx_skb->skb;
5280
5281                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5282                                              tp->TxDescArray + entry);
5283                         if (skb) {
5284                                 dev_consume_skb_any(skb);
5285                                 tx_skb->skb = NULL;
5286                         }
5287                 }
5288         }
5289 }
5290
5291 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5292 {
5293         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5294         tp->cur_tx = tp->dirty_tx = 0;
5295         netdev_reset_queue(tp->dev);
5296 }
5297
5298 static void rtl_reset_work(struct rtl8169_private *tp)
5299 {
5300         struct net_device *dev = tp->dev;
5301         int i;
5302
5303         napi_disable(&tp->napi);
5304         netif_stop_queue(dev);
5305         synchronize_rcu();
5306
5307         rtl8169_hw_reset(tp);
5308
5309         for (i = 0; i < NUM_RX_DESC; i++)
5310                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5311
5312         rtl8169_tx_clear(tp);
5313         rtl8169_init_ring_indexes(tp);
5314
5315         napi_enable(&tp->napi);
5316         rtl_hw_start(tp);
5317         netif_wake_queue(dev);
5318 }
5319
5320 static void rtl8169_tx_timeout(struct net_device *dev)
5321 {
5322         struct rtl8169_private *tp = netdev_priv(dev);
5323
5324         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5325 }
5326
5327 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5328 {
5329         u32 status = opts0 | len;
5330
5331         if (entry == NUM_TX_DESC - 1)
5332                 status |= RingEnd;
5333
5334         return cpu_to_le32(status);
5335 }
5336
5337 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5338                               u32 *opts)
5339 {
5340         struct skb_shared_info *info = skb_shinfo(skb);
5341         unsigned int cur_frag, entry;
5342         struct TxDesc *uninitialized_var(txd);
5343         struct device *d = tp_to_dev(tp);
5344
5345         entry = tp->cur_tx;
5346         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5347                 const skb_frag_t *frag = info->frags + cur_frag;
5348                 dma_addr_t mapping;
5349                 u32 len;
5350                 void *addr;
5351
5352                 entry = (entry + 1) % NUM_TX_DESC;
5353
5354                 txd = tp->TxDescArray + entry;
5355                 len = skb_frag_size(frag);
5356                 addr = skb_frag_address(frag);
5357                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5358                 if (unlikely(dma_mapping_error(d, mapping))) {
5359                         if (net_ratelimit())
5360                                 netif_err(tp, drv, tp->dev,
5361                                           "Failed to map TX fragments DMA!\n");
5362                         goto err_out;
5363                 }
5364
5365                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5366                 txd->opts2 = cpu_to_le32(opts[1]);
5367                 txd->addr = cpu_to_le64(mapping);
5368
5369                 tp->tx_skb[entry].len = len;
5370         }
5371
5372         if (cur_frag) {
5373                 tp->tx_skb[entry].skb = skb;
5374                 txd->opts1 |= cpu_to_le32(LastFrag);
5375         }
5376
5377         return cur_frag;
5378
5379 err_out:
5380         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5381         return -EIO;
5382 }
5383
5384 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5385 {
5386         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5387 }
5388
5389 /* msdn_giant_send_check()
5390  * According to the document of microsoft, the TCP Pseudo Header excludes the
5391  * packet length for IPv6 TCP large packets.
5392  */
5393 static int msdn_giant_send_check(struct sk_buff *skb)
5394 {
5395         const struct ipv6hdr *ipv6h;
5396         struct tcphdr *th;
5397         int ret;
5398
5399         ret = skb_cow_head(skb, 0);
5400         if (ret)
5401                 return ret;
5402
5403         ipv6h = ipv6_hdr(skb);
5404         th = tcp_hdr(skb);
5405
5406         th->check = 0;
5407         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5408
5409         return ret;
5410 }
5411
5412 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5413 {
5414         u32 mss = skb_shinfo(skb)->gso_size;
5415
5416         if (mss) {
5417                 opts[0] |= TD_LSO;
5418                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5419         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5420                 const struct iphdr *ip = ip_hdr(skb);
5421
5422                 if (ip->protocol == IPPROTO_TCP)
5423                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5424                 else if (ip->protocol == IPPROTO_UDP)
5425                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5426                 else
5427                         WARN_ON_ONCE(1);
5428         }
5429 }
5430
5431 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5432                                 struct sk_buff *skb, u32 *opts)
5433 {
5434         u32 transport_offset = (u32)skb_transport_offset(skb);
5435         u32 mss = skb_shinfo(skb)->gso_size;
5436
5437         if (mss) {
5438                 switch (vlan_get_protocol(skb)) {
5439                 case htons(ETH_P_IP):
5440                         opts[0] |= TD1_GTSENV4;
5441                         break;
5442
5443                 case htons(ETH_P_IPV6):
5444                         if (msdn_giant_send_check(skb))
5445                                 return false;
5446
5447                         opts[0] |= TD1_GTSENV6;
5448                         break;
5449
5450                 default:
5451                         WARN_ON_ONCE(1);
5452                         break;
5453                 }
5454
5455                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5456                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5457         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5458                 u8 ip_protocol;
5459
5460                 switch (vlan_get_protocol(skb)) {
5461                 case htons(ETH_P_IP):
5462                         opts[1] |= TD1_IPv4_CS;
5463                         ip_protocol = ip_hdr(skb)->protocol;
5464                         break;
5465
5466                 case htons(ETH_P_IPV6):
5467                         opts[1] |= TD1_IPv6_CS;
5468                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5469                         break;
5470
5471                 default:
5472                         ip_protocol = IPPROTO_RAW;
5473                         break;
5474                 }
5475
5476                 if (ip_protocol == IPPROTO_TCP)
5477                         opts[1] |= TD1_TCP_CS;
5478                 else if (ip_protocol == IPPROTO_UDP)
5479                         opts[1] |= TD1_UDP_CS;
5480                 else
5481                         WARN_ON_ONCE(1);
5482
5483                 opts[1] |= transport_offset << TCPHO_SHIFT;
5484         } else {
5485                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5486                         return !eth_skb_pad(skb);
5487         }
5488
5489         return true;
5490 }
5491
5492 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5493                                unsigned int nr_frags)
5494 {
5495         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5496
5497         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5498         return slots_avail > nr_frags;
5499 }
5500
5501 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5502 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5503 {
5504         switch (tp->mac_version) {
5505         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5506         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5507                 return false;
5508         default:
5509                 return true;
5510         }
5511 }
5512
5513 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5514                                       struct net_device *dev)
5515 {
5516         struct rtl8169_private *tp = netdev_priv(dev);
5517         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5518         struct TxDesc *txd = tp->TxDescArray + entry;
5519         struct device *d = tp_to_dev(tp);
5520         dma_addr_t mapping;
5521         u32 opts[2], len;
5522         bool stop_queue;
5523         bool door_bell;
5524         int frags;
5525
5526         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5527                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5528                 goto err_stop_0;
5529         }
5530
5531         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5532                 goto err_stop_0;
5533
5534         opts[1] = rtl8169_tx_vlan_tag(skb);
5535         opts[0] = DescOwn;
5536
5537         if (rtl_chip_supports_csum_v2(tp)) {
5538                 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5539                         goto err_dma_0;
5540         } else {
5541                 rtl8169_tso_csum_v1(skb, opts);
5542         }
5543
5544         len = skb_headlen(skb);
5545         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5546         if (unlikely(dma_mapping_error(d, mapping))) {
5547                 if (net_ratelimit())
5548                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5549                 goto err_dma_0;
5550         }
5551
5552         tp->tx_skb[entry].len = len;
5553         txd->addr = cpu_to_le64(mapping);
5554
5555         frags = rtl8169_xmit_frags(tp, skb, opts);
5556         if (frags < 0)
5557                 goto err_dma_1;
5558         else if (frags)
5559                 opts[0] |= FirstFrag;
5560         else {
5561                 opts[0] |= FirstFrag | LastFrag;
5562                 tp->tx_skb[entry].skb = skb;
5563         }
5564
5565         txd->opts2 = cpu_to_le32(opts[1]);
5566
5567         skb_tx_timestamp(skb);
5568
5569         /* Force memory writes to complete before releasing descriptor */
5570         dma_wmb();
5571
5572         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5573
5574         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5575
5576         /* Force all memory writes to complete before notifying device */
5577         wmb();
5578
5579         tp->cur_tx += frags + 1;
5580
5581         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5582         if (unlikely(stop_queue)) {
5583                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5584                  * not miss a ring update when it notices a stopped queue.
5585                  */
5586                 smp_wmb();
5587                 netif_stop_queue(dev);
5588                 door_bell = true;
5589         }
5590
5591         if (door_bell)
5592                 RTL_W8(tp, TxPoll, NPQ);
5593
5594         if (unlikely(stop_queue)) {
5595                 /* Sync with rtl_tx:
5596                  * - publish queue status and cur_tx ring index (write barrier)
5597                  * - refresh dirty_tx ring index (read barrier).
5598                  * May the current thread have a pessimistic view of the ring
5599                  * status and forget to wake up queue, a racing rtl_tx thread
5600                  * can't.
5601                  */
5602                 smp_mb();
5603                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5604                         netif_start_queue(dev);
5605         }
5606
5607         return NETDEV_TX_OK;
5608
5609 err_dma_1:
5610         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5611 err_dma_0:
5612         dev_kfree_skb_any(skb);
5613         dev->stats.tx_dropped++;
5614         return NETDEV_TX_OK;
5615
5616 err_stop_0:
5617         netif_stop_queue(dev);
5618         dev->stats.tx_dropped++;
5619         return NETDEV_TX_BUSY;
5620 }
5621
5622 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5623                                                 struct net_device *dev,
5624                                                 netdev_features_t features)
5625 {
5626         int transport_offset = skb_transport_offset(skb);
5627         struct rtl8169_private *tp = netdev_priv(dev);
5628
5629         if (skb_is_gso(skb)) {
5630                 if (transport_offset > GTTCPHO_MAX &&
5631                     rtl_chip_supports_csum_v2(tp))
5632                         features &= ~NETIF_F_ALL_TSO;
5633         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5634                 if (skb->len < ETH_ZLEN) {
5635                         switch (tp->mac_version) {
5636                         case RTL_GIGA_MAC_VER_11:
5637                         case RTL_GIGA_MAC_VER_12:
5638                         case RTL_GIGA_MAC_VER_17:
5639                         case RTL_GIGA_MAC_VER_34:
5640                                 features &= ~NETIF_F_CSUM_MASK;
5641                                 break;
5642                         default:
5643                                 break;
5644                         }
5645                 }
5646
5647                 if (transport_offset > TCPHO_MAX &&
5648                     rtl_chip_supports_csum_v2(tp))
5649                         features &= ~NETIF_F_CSUM_MASK;
5650         }
5651
5652         return vlan_features_check(skb, features);
5653 }
5654
5655 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5656 {
5657         struct rtl8169_private *tp = netdev_priv(dev);
5658         struct pci_dev *pdev = tp->pci_dev;
5659         u16 pci_status, pci_cmd;
5660
5661         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5662         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5663
5664         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5665                   pci_cmd, pci_status);
5666
5667         /*
5668          * The recovery sequence below admits a very elaborated explanation:
5669          * - it seems to work;
5670          * - I did not see what else could be done;
5671          * - it makes iop3xx happy.
5672          *
5673          * Feel free to adjust to your needs.
5674          */
5675         if (pdev->broken_parity_status)
5676                 pci_cmd &= ~PCI_COMMAND_PARITY;
5677         else
5678                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5679
5680         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5681
5682         pci_write_config_word(pdev, PCI_STATUS,
5683                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5684                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5685                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5686
5687         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5688 }
5689
5690 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5691                    int budget)
5692 {
5693         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5694
5695         dirty_tx = tp->dirty_tx;
5696         smp_rmb();
5697         tx_left = tp->cur_tx - dirty_tx;
5698
5699         while (tx_left > 0) {
5700                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5701                 struct ring_info *tx_skb = tp->tx_skb + entry;
5702                 u32 status;
5703
5704                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5705                 if (status & DescOwn)
5706                         break;
5707
5708                 /* This barrier is needed to keep us from reading
5709                  * any other fields out of the Tx descriptor until
5710                  * we know the status of DescOwn
5711                  */
5712                 dma_rmb();
5713
5714                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5715                                      tp->TxDescArray + entry);
5716                 if (status & LastFrag) {
5717                         pkts_compl++;
5718                         bytes_compl += tx_skb->skb->len;
5719                         napi_consume_skb(tx_skb->skb, budget);
5720                         tx_skb->skb = NULL;
5721                 }
5722                 dirty_tx++;
5723                 tx_left--;
5724         }
5725
5726         if (tp->dirty_tx != dirty_tx) {
5727                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5728
5729                 u64_stats_update_begin(&tp->tx_stats.syncp);
5730                 tp->tx_stats.packets += pkts_compl;
5731                 tp->tx_stats.bytes += bytes_compl;
5732                 u64_stats_update_end(&tp->tx_stats.syncp);
5733
5734                 tp->dirty_tx = dirty_tx;
5735                 /* Sync with rtl8169_start_xmit:
5736                  * - publish dirty_tx ring index (write barrier)
5737                  * - refresh cur_tx ring index and queue status (read barrier)
5738                  * May the current thread miss the stopped queue condition,
5739                  * a racing xmit thread can only have a right view of the
5740                  * ring status.
5741                  */
5742                 smp_mb();
5743                 if (netif_queue_stopped(dev) &&
5744                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5745                         netif_wake_queue(dev);
5746                 }
5747                 /*
5748                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5749                  * too close. Let's kick an extra TxPoll request when a burst
5750                  * of start_xmit activity is detected (if it is not detected,
5751                  * it is slow enough). -- FR
5752                  */
5753                 if (tp->cur_tx != dirty_tx)
5754                         RTL_W8(tp, TxPoll, NPQ);
5755         }
5756 }
5757
5758 static inline int rtl8169_fragmented_frame(u32 status)
5759 {
5760         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5761 }
5762
5763 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5764 {
5765         u32 status = opts1 & RxProtoMask;
5766
5767         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5768             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5769                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5770         else
5771                 skb_checksum_none_assert(skb);
5772 }
5773
5774 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5775 {
5776         unsigned int cur_rx, rx_left;
5777         unsigned int count;
5778
5779         cur_rx = tp->cur_rx;
5780
5781         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5782                 unsigned int entry = cur_rx % NUM_RX_DESC;
5783                 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
5784                 struct RxDesc *desc = tp->RxDescArray + entry;
5785                 u32 status;
5786
5787                 status = le32_to_cpu(desc->opts1);
5788                 if (status & DescOwn)
5789                         break;
5790
5791                 /* This barrier is needed to keep us from reading
5792                  * any other fields out of the Rx descriptor until
5793                  * we know the status of DescOwn
5794                  */
5795                 dma_rmb();
5796
5797                 if (unlikely(status & RxRES)) {
5798                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5799                                    status);
5800                         dev->stats.rx_errors++;
5801                         if (status & (RxRWT | RxRUNT))
5802                                 dev->stats.rx_length_errors++;
5803                         if (status & RxCRC)
5804                                 dev->stats.rx_crc_errors++;
5805                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5806                             dev->features & NETIF_F_RXALL) {
5807                                 goto process_pkt;
5808                         }
5809                 } else {
5810                         unsigned int pkt_size;
5811                         struct sk_buff *skb;
5812
5813 process_pkt:
5814                         pkt_size = status & GENMASK(13, 0);
5815                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5816                                 pkt_size -= ETH_FCS_LEN;
5817                         /*
5818                          * The driver does not support incoming fragmented
5819                          * frames. They are seen as a symptom of over-mtu
5820                          * sized frames.
5821                          */
5822                         if (unlikely(rtl8169_fragmented_frame(status))) {
5823                                 dev->stats.rx_dropped++;
5824                                 dev->stats.rx_length_errors++;
5825                                 goto release_descriptor;
5826                         }
5827
5828                         skb = napi_alloc_skb(&tp->napi, pkt_size);
5829                         if (unlikely(!skb)) {
5830                                 dev->stats.rx_dropped++;
5831                                 goto release_descriptor;
5832                         }
5833
5834                         dma_sync_single_for_cpu(tp_to_dev(tp),
5835                                                 le64_to_cpu(desc->addr),
5836                                                 pkt_size, DMA_FROM_DEVICE);
5837                         prefetch(rx_buf);
5838                         skb_copy_to_linear_data(skb, rx_buf, pkt_size);
5839                         skb->tail += pkt_size;
5840                         skb->len = pkt_size;
5841
5842                         dma_sync_single_for_device(tp_to_dev(tp),
5843                                                    le64_to_cpu(desc->addr),
5844                                                    pkt_size, DMA_FROM_DEVICE);
5845
5846                         rtl8169_rx_csum(skb, status);
5847                         skb->protocol = eth_type_trans(skb, dev);
5848
5849                         rtl8169_rx_vlan_tag(desc, skb);
5850
5851                         if (skb->pkt_type == PACKET_MULTICAST)
5852                                 dev->stats.multicast++;
5853
5854                         napi_gro_receive(&tp->napi, skb);
5855
5856                         u64_stats_update_begin(&tp->rx_stats.syncp);
5857                         tp->rx_stats.packets++;
5858                         tp->rx_stats.bytes += pkt_size;
5859                         u64_stats_update_end(&tp->rx_stats.syncp);
5860                 }
5861 release_descriptor:
5862                 desc->opts2 = 0;
5863                 rtl8169_mark_to_asic(desc);
5864         }
5865
5866         count = cur_rx - tp->cur_rx;
5867         tp->cur_rx = cur_rx;
5868
5869         return count;
5870 }
5871
5872 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5873 {
5874         struct rtl8169_private *tp = dev_instance;
5875         u32 status = rtl_get_events(tp);
5876
5877         if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
5878             !(status & tp->irq_mask))
5879                 return IRQ_NONE;
5880
5881         if (unlikely(status & SYSErr)) {
5882                 rtl8169_pcierr_interrupt(tp->dev);
5883                 goto out;
5884         }
5885
5886         if (status & LinkChg)
5887                 phy_mac_interrupt(tp->phydev);
5888
5889         if (unlikely(status & RxFIFOOver &&
5890             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
5891                 netif_stop_queue(tp->dev);
5892                 /* XXX - Hack alert. See rtl_task(). */
5893                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5894         }
5895
5896         rtl_irq_disable(tp);
5897         napi_schedule_irqoff(&tp->napi);
5898 out:
5899         rtl_ack_events(tp, status);
5900
5901         return IRQ_HANDLED;
5902 }
5903
5904 static void rtl_task(struct work_struct *work)
5905 {
5906         static const struct {
5907                 int bitnr;
5908                 void (*action)(struct rtl8169_private *);
5909         } rtl_work[] = {
5910                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5911         };
5912         struct rtl8169_private *tp =
5913                 container_of(work, struct rtl8169_private, wk.work);
5914         struct net_device *dev = tp->dev;
5915         int i;
5916
5917         rtl_lock_work(tp);
5918
5919         if (!netif_running(dev) ||
5920             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5921                 goto out_unlock;
5922
5923         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5924                 bool pending;
5925
5926                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5927                 if (pending)
5928                         rtl_work[i].action(tp);
5929         }
5930
5931 out_unlock:
5932         rtl_unlock_work(tp);
5933 }
5934
5935 static int rtl8169_poll(struct napi_struct *napi, int budget)
5936 {
5937         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5938         struct net_device *dev = tp->dev;
5939         int work_done;
5940
5941         work_done = rtl_rx(dev, tp, (u32) budget);
5942
5943         rtl_tx(dev, tp, budget);
5944
5945         if (work_done < budget) {
5946                 napi_complete_done(napi, work_done);
5947                 rtl_irq_enable(tp);
5948         }
5949
5950         return work_done;
5951 }
5952
5953 static void rtl8169_rx_missed(struct net_device *dev)
5954 {
5955         struct rtl8169_private *tp = netdev_priv(dev);
5956
5957         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5958                 return;
5959
5960         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
5961         RTL_W32(tp, RxMissed, 0);
5962 }
5963
5964 static void r8169_phylink_handler(struct net_device *ndev)
5965 {
5966         struct rtl8169_private *tp = netdev_priv(ndev);
5967
5968         if (netif_carrier_ok(ndev)) {
5969                 rtl_link_chg_patch(tp);
5970                 pm_request_resume(&tp->pci_dev->dev);
5971         } else {
5972                 pm_runtime_idle(&tp->pci_dev->dev);
5973         }
5974
5975         if (net_ratelimit())
5976                 phy_print_status(tp->phydev);
5977 }
5978
5979 static int r8169_phy_connect(struct rtl8169_private *tp)
5980 {
5981         struct phy_device *phydev = tp->phydev;
5982         phy_interface_t phy_mode;
5983         int ret;
5984
5985         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
5986                    PHY_INTERFACE_MODE_MII;
5987
5988         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
5989                                  phy_mode);
5990         if (ret)
5991                 return ret;
5992
5993         if (!tp->supports_gmii)
5994                 phy_set_max_speed(phydev, SPEED_100);
5995
5996         phy_support_asym_pause(phydev);
5997
5998         phy_attached_info(phydev);
5999
6000         return 0;
6001 }
6002
6003 static void rtl8169_down(struct net_device *dev)
6004 {
6005         struct rtl8169_private *tp = netdev_priv(dev);
6006
6007         phy_stop(tp->phydev);
6008
6009         napi_disable(&tp->napi);
6010         netif_stop_queue(dev);
6011
6012         rtl8169_hw_reset(tp);
6013         /*
6014          * At this point device interrupts can not be enabled in any function,
6015          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6016          * and napi is disabled (rtl8169_poll).
6017          */
6018         rtl8169_rx_missed(dev);
6019
6020         /* Give a racing hard_start_xmit a few cycles to complete. */
6021         synchronize_rcu();
6022
6023         rtl8169_tx_clear(tp);
6024
6025         rtl8169_rx_clear(tp);
6026
6027         rtl_pll_power_down(tp);
6028 }
6029
6030 static int rtl8169_close(struct net_device *dev)
6031 {
6032         struct rtl8169_private *tp = netdev_priv(dev);
6033         struct pci_dev *pdev = tp->pci_dev;
6034
6035         pm_runtime_get_sync(&pdev->dev);
6036
6037         /* Update counters before going down */
6038         rtl8169_update_counters(tp);
6039
6040         rtl_lock_work(tp);
6041         /* Clear all task flags */
6042         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6043
6044         rtl8169_down(dev);
6045         rtl_unlock_work(tp);
6046
6047         cancel_work_sync(&tp->wk.work);
6048
6049         phy_disconnect(tp->phydev);
6050
6051         pci_free_irq(pdev, 0, tp);
6052
6053         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6054                           tp->RxPhyAddr);
6055         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6056                           tp->TxPhyAddr);
6057         tp->TxDescArray = NULL;
6058         tp->RxDescArray = NULL;
6059
6060         pm_runtime_put_sync(&pdev->dev);
6061
6062         return 0;
6063 }
6064
6065 #ifdef CONFIG_NET_POLL_CONTROLLER
6066 static void rtl8169_netpoll(struct net_device *dev)
6067 {
6068         struct rtl8169_private *tp = netdev_priv(dev);
6069
6070         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6071 }
6072 #endif
6073
6074 static int rtl_open(struct net_device *dev)
6075 {
6076         struct rtl8169_private *tp = netdev_priv(dev);
6077         struct pci_dev *pdev = tp->pci_dev;
6078         int retval = -ENOMEM;
6079
6080         pm_runtime_get_sync(&pdev->dev);
6081
6082         /*
6083          * Rx and Tx descriptors needs 256 bytes alignment.
6084          * dma_alloc_coherent provides more.
6085          */
6086         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6087                                              &tp->TxPhyAddr, GFP_KERNEL);
6088         if (!tp->TxDescArray)
6089                 goto err_pm_runtime_put;
6090
6091         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6092                                              &tp->RxPhyAddr, GFP_KERNEL);
6093         if (!tp->RxDescArray)
6094                 goto err_free_tx_0;
6095
6096         retval = rtl8169_init_ring(tp);
6097         if (retval < 0)
6098                 goto err_free_rx_1;
6099
6100         rtl_request_firmware(tp);
6101
6102         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6103                                  dev->name);
6104         if (retval < 0)
6105                 goto err_release_fw_2;
6106
6107         retval = r8169_phy_connect(tp);
6108         if (retval)
6109                 goto err_free_irq;
6110
6111         rtl_lock_work(tp);
6112
6113         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6114
6115         napi_enable(&tp->napi);
6116
6117         rtl8169_init_phy(dev, tp);
6118
6119         rtl_pll_power_up(tp);
6120
6121         rtl_hw_start(tp);
6122
6123         if (!rtl8169_init_counter_offsets(tp))
6124                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6125
6126         phy_start(tp->phydev);
6127         netif_start_queue(dev);
6128
6129         rtl_unlock_work(tp);
6130
6131         pm_runtime_put_sync(&pdev->dev);
6132 out:
6133         return retval;
6134
6135 err_free_irq:
6136         pci_free_irq(pdev, 0, tp);
6137 err_release_fw_2:
6138         rtl_release_firmware(tp);
6139         rtl8169_rx_clear(tp);
6140 err_free_rx_1:
6141         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6142                           tp->RxPhyAddr);
6143         tp->RxDescArray = NULL;
6144 err_free_tx_0:
6145         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6146                           tp->TxPhyAddr);
6147         tp->TxDescArray = NULL;
6148 err_pm_runtime_put:
6149         pm_runtime_put_noidle(&pdev->dev);
6150         goto out;
6151 }
6152
6153 static void
6154 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6155 {
6156         struct rtl8169_private *tp = netdev_priv(dev);
6157         struct pci_dev *pdev = tp->pci_dev;
6158         struct rtl8169_counters *counters = tp->counters;
6159         unsigned int start;
6160
6161         pm_runtime_get_noresume(&pdev->dev);
6162
6163         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6164                 rtl8169_rx_missed(dev);
6165
6166         do {
6167                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6168                 stats->rx_packets = tp->rx_stats.packets;
6169                 stats->rx_bytes = tp->rx_stats.bytes;
6170         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6171
6172         do {
6173                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6174                 stats->tx_packets = tp->tx_stats.packets;
6175                 stats->tx_bytes = tp->tx_stats.bytes;
6176         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6177
6178         stats->rx_dropped       = dev->stats.rx_dropped;
6179         stats->tx_dropped       = dev->stats.tx_dropped;
6180         stats->rx_length_errors = dev->stats.rx_length_errors;
6181         stats->rx_errors        = dev->stats.rx_errors;
6182         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6183         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6184         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6185         stats->multicast        = dev->stats.multicast;
6186
6187         /*
6188          * Fetch additional counter values missing in stats collected by driver
6189          * from tally counters.
6190          */
6191         if (pm_runtime_active(&pdev->dev))
6192                 rtl8169_update_counters(tp);
6193
6194         /*
6195          * Subtract values fetched during initalization.
6196          * See rtl8169_init_counter_offsets for a description why we do that.
6197          */
6198         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6199                 le64_to_cpu(tp->tc_offset.tx_errors);
6200         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6201                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6202         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6203                 le16_to_cpu(tp->tc_offset.tx_aborted);
6204
6205         pm_runtime_put_noidle(&pdev->dev);
6206 }
6207
6208 static void rtl8169_net_suspend(struct net_device *dev)
6209 {
6210         struct rtl8169_private *tp = netdev_priv(dev);
6211
6212         if (!netif_running(dev))
6213                 return;
6214
6215         phy_stop(tp->phydev);
6216         netif_device_detach(dev);
6217
6218         rtl_lock_work(tp);
6219         napi_disable(&tp->napi);
6220         /* Clear all task flags */
6221         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6222
6223         rtl_unlock_work(tp);
6224
6225         rtl_pll_power_down(tp);
6226 }
6227
6228 #ifdef CONFIG_PM
6229
6230 static int rtl8169_suspend(struct device *device)
6231 {
6232         struct net_device *dev = dev_get_drvdata(device);
6233         struct rtl8169_private *tp = netdev_priv(dev);
6234
6235         rtl8169_net_suspend(dev);
6236         clk_disable_unprepare(tp->clk);
6237
6238         return 0;
6239 }
6240
6241 static void __rtl8169_resume(struct net_device *dev)
6242 {
6243         struct rtl8169_private *tp = netdev_priv(dev);
6244
6245         netif_device_attach(dev);
6246
6247         rtl_pll_power_up(tp);
6248         rtl8169_init_phy(dev, tp);
6249
6250         phy_start(tp->phydev);
6251
6252         rtl_lock_work(tp);
6253         napi_enable(&tp->napi);
6254         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6255         rtl_reset_work(tp);
6256         rtl_unlock_work(tp);
6257 }
6258
6259 static int rtl8169_resume(struct device *device)
6260 {
6261         struct net_device *dev = dev_get_drvdata(device);
6262         struct rtl8169_private *tp = netdev_priv(dev);
6263
6264         rtl_rar_set(tp, dev->dev_addr);
6265
6266         clk_prepare_enable(tp->clk);
6267
6268         if (netif_running(dev))
6269                 __rtl8169_resume(dev);
6270
6271         return 0;
6272 }
6273
6274 static int rtl8169_runtime_suspend(struct device *device)
6275 {
6276         struct net_device *dev = dev_get_drvdata(device);
6277         struct rtl8169_private *tp = netdev_priv(dev);
6278
6279         if (!tp->TxDescArray)
6280                 return 0;
6281
6282         rtl_lock_work(tp);
6283         __rtl8169_set_wol(tp, WAKE_ANY);
6284         rtl_unlock_work(tp);
6285
6286         rtl8169_net_suspend(dev);
6287
6288         /* Update counters before going runtime suspend */
6289         rtl8169_rx_missed(dev);
6290         rtl8169_update_counters(tp);
6291
6292         return 0;
6293 }
6294
6295 static int rtl8169_runtime_resume(struct device *device)
6296 {
6297         struct net_device *dev = dev_get_drvdata(device);
6298         struct rtl8169_private *tp = netdev_priv(dev);
6299
6300         rtl_rar_set(tp, dev->dev_addr);
6301
6302         if (!tp->TxDescArray)
6303                 return 0;
6304
6305         rtl_lock_work(tp);
6306         __rtl8169_set_wol(tp, tp->saved_wolopts);
6307         rtl_unlock_work(tp);
6308
6309         __rtl8169_resume(dev);
6310
6311         return 0;
6312 }
6313
6314 static int rtl8169_runtime_idle(struct device *device)
6315 {
6316         struct net_device *dev = dev_get_drvdata(device);
6317
6318         if (!netif_running(dev) || !netif_carrier_ok(dev))
6319                 pm_schedule_suspend(device, 10000);
6320
6321         return -EBUSY;
6322 }
6323
6324 static const struct dev_pm_ops rtl8169_pm_ops = {
6325         .suspend                = rtl8169_suspend,
6326         .resume                 = rtl8169_resume,
6327         .freeze                 = rtl8169_suspend,
6328         .thaw                   = rtl8169_resume,
6329         .poweroff               = rtl8169_suspend,
6330         .restore                = rtl8169_resume,
6331         .runtime_suspend        = rtl8169_runtime_suspend,
6332         .runtime_resume         = rtl8169_runtime_resume,
6333         .runtime_idle           = rtl8169_runtime_idle,
6334 };
6335
6336 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6337
6338 #else /* !CONFIG_PM */
6339
6340 #define RTL8169_PM_OPS  NULL
6341
6342 #endif /* !CONFIG_PM */
6343
6344 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6345 {
6346         /* WoL fails with 8168b when the receiver is disabled. */
6347         switch (tp->mac_version) {
6348         case RTL_GIGA_MAC_VER_11:
6349         case RTL_GIGA_MAC_VER_12:
6350         case RTL_GIGA_MAC_VER_17:
6351                 pci_clear_master(tp->pci_dev);
6352
6353                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6354                 /* PCI commit */
6355                 RTL_R8(tp, ChipCmd);
6356                 break;
6357         default:
6358                 break;
6359         }
6360 }
6361
6362 static void rtl_shutdown(struct pci_dev *pdev)
6363 {
6364         struct net_device *dev = pci_get_drvdata(pdev);
6365         struct rtl8169_private *tp = netdev_priv(dev);
6366
6367         rtl8169_net_suspend(dev);
6368
6369         /* Restore original MAC address */
6370         rtl_rar_set(tp, dev->perm_addr);
6371
6372         rtl8169_hw_reset(tp);
6373
6374         if (system_state == SYSTEM_POWER_OFF) {
6375                 if (tp->saved_wolopts) {
6376                         rtl_wol_suspend_quirk(tp);
6377                         rtl_wol_shutdown_quirk(tp);
6378                 }
6379
6380                 pci_wake_from_d3(pdev, true);
6381                 pci_set_power_state(pdev, PCI_D3hot);
6382         }
6383 }
6384
6385 static void rtl_remove_one(struct pci_dev *pdev)
6386 {
6387         struct net_device *dev = pci_get_drvdata(pdev);
6388         struct rtl8169_private *tp = netdev_priv(dev);
6389
6390         if (r8168_check_dash(tp))
6391                 rtl8168_driver_stop(tp);
6392
6393         netif_napi_del(&tp->napi);
6394
6395         unregister_netdev(dev);
6396         mdiobus_unregister(tp->phydev->mdio.bus);
6397
6398         rtl_release_firmware(tp);
6399
6400         if (pci_dev_run_wake(pdev))
6401                 pm_runtime_get_noresume(&pdev->dev);
6402
6403         /* restore original MAC address */
6404         rtl_rar_set(tp, dev->perm_addr);
6405 }
6406
6407 static const struct net_device_ops rtl_netdev_ops = {
6408         .ndo_open               = rtl_open,
6409         .ndo_stop               = rtl8169_close,
6410         .ndo_get_stats64        = rtl8169_get_stats64,
6411         .ndo_start_xmit         = rtl8169_start_xmit,
6412         .ndo_features_check     = rtl8169_features_check,
6413         .ndo_tx_timeout         = rtl8169_tx_timeout,
6414         .ndo_validate_addr      = eth_validate_addr,
6415         .ndo_change_mtu         = rtl8169_change_mtu,
6416         .ndo_fix_features       = rtl8169_fix_features,
6417         .ndo_set_features       = rtl8169_set_features,
6418         .ndo_set_mac_address    = rtl_set_mac_address,
6419         .ndo_do_ioctl           = rtl8169_ioctl,
6420         .ndo_set_rx_mode        = rtl_set_rx_mode,
6421 #ifdef CONFIG_NET_POLL_CONTROLLER
6422         .ndo_poll_controller    = rtl8169_netpoll,
6423 #endif
6424
6425 };
6426
6427 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6428 {
6429         tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6430
6431         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6432                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6433         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6434                 /* special workaround needed */
6435                 tp->irq_mask |= RxFIFOOver;
6436         else
6437                 tp->irq_mask |= RxOverflow;
6438 }
6439
6440 static int rtl_alloc_irq(struct rtl8169_private *tp)
6441 {
6442         unsigned int flags;
6443
6444         switch (tp->mac_version) {
6445         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6446                 rtl_unlock_config_regs(tp);
6447                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6448                 rtl_lock_config_regs(tp);
6449                 /* fall through */
6450         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6451                 flags = PCI_IRQ_LEGACY;
6452                 break;
6453         default:
6454                 flags = PCI_IRQ_ALL_TYPES;
6455                 break;
6456         }
6457
6458         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6459 }
6460
6461 static void rtl_read_mac_address(struct rtl8169_private *tp,
6462                                  u8 mac_addr[ETH_ALEN])
6463 {
6464         /* Get MAC address */
6465         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6466                 u32 value = rtl_eri_read(tp, 0xe0);
6467
6468                 mac_addr[0] = (value >>  0) & 0xff;
6469                 mac_addr[1] = (value >>  8) & 0xff;
6470                 mac_addr[2] = (value >> 16) & 0xff;
6471                 mac_addr[3] = (value >> 24) & 0xff;
6472
6473                 value = rtl_eri_read(tp, 0xe4);
6474                 mac_addr[4] = (value >>  0) & 0xff;
6475                 mac_addr[5] = (value >>  8) & 0xff;
6476         }
6477 }
6478
6479 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6480 {
6481         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6482 }
6483
6484 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6485 {
6486         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6487 }
6488
6489 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6490 {
6491         struct rtl8169_private *tp = mii_bus->priv;
6492
6493         if (phyaddr > 0)
6494                 return -ENODEV;
6495
6496         return rtl_readphy(tp, phyreg);
6497 }
6498
6499 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6500                                 int phyreg, u16 val)
6501 {
6502         struct rtl8169_private *tp = mii_bus->priv;
6503
6504         if (phyaddr > 0)
6505                 return -ENODEV;
6506
6507         rtl_writephy(tp, phyreg, val);
6508
6509         return 0;
6510 }
6511
6512 static int r8169_mdio_register(struct rtl8169_private *tp)
6513 {
6514         struct pci_dev *pdev = tp->pci_dev;
6515         struct mii_bus *new_bus;
6516         int ret;
6517
6518         new_bus = devm_mdiobus_alloc(&pdev->dev);
6519         if (!new_bus)
6520                 return -ENOMEM;
6521
6522         new_bus->name = "r8169";
6523         new_bus->priv = tp;
6524         new_bus->parent = &pdev->dev;
6525         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6526         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6527
6528         new_bus->read = r8169_mdio_read_reg;
6529         new_bus->write = r8169_mdio_write_reg;
6530
6531         ret = mdiobus_register(new_bus);
6532         if (ret)
6533                 return ret;
6534
6535         tp->phydev = mdiobus_get_phy(new_bus, 0);
6536         if (!tp->phydev) {
6537                 mdiobus_unregister(new_bus);
6538                 return -ENODEV;
6539         }
6540
6541         /* PHY will be woken up in rtl_open() */
6542         phy_suspend(tp->phydev);
6543
6544         return 0;
6545 }
6546
6547 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6548 {
6549         tp->ocp_base = OCP_STD_PHY_BASE;
6550
6551         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6552
6553         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6554                 return;
6555
6556         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6557                 return;
6558
6559         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6560         msleep(1);
6561         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6562
6563         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6564
6565         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6566                 return;
6567
6568         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6569
6570         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6571 }
6572
6573 static void rtl_hw_initialize(struct rtl8169_private *tp)
6574 {
6575         switch (tp->mac_version) {
6576         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6577                 rtl8168ep_stop_cmac(tp);
6578                 /* fall through */
6579         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6580                 rtl_hw_init_8168g(tp);
6581                 break;
6582         default:
6583                 break;
6584         }
6585 }
6586
6587 static int rtl_jumbo_max(struct rtl8169_private *tp)
6588 {
6589         /* Non-GBit versions don't support jumbo frames */
6590         if (!tp->supports_gmii)
6591                 return JUMBO_1K;
6592
6593         switch (tp->mac_version) {
6594         /* RTL8169 */
6595         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6596                 return JUMBO_7K;
6597         /* RTL8168b */
6598         case RTL_GIGA_MAC_VER_11:
6599         case RTL_GIGA_MAC_VER_12:
6600         case RTL_GIGA_MAC_VER_17:
6601                 return JUMBO_4K;
6602         /* RTL8168c */
6603         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6604                 return JUMBO_6K;
6605         default:
6606                 return JUMBO_9K;
6607         }
6608 }
6609
6610 static void rtl_disable_clk(void *data)
6611 {
6612         clk_disable_unprepare(data);
6613 }
6614
6615 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6616 {
6617         struct device *d = tp_to_dev(tp);
6618         struct clk *clk;
6619         int rc;
6620
6621         clk = devm_clk_get(d, "ether_clk");
6622         if (IS_ERR(clk)) {
6623                 rc = PTR_ERR(clk);
6624                 if (rc == -ENOENT)
6625                         /* clk-core allows NULL (for suspend / resume) */
6626                         rc = 0;
6627                 else if (rc != -EPROBE_DEFER)
6628                         dev_err(d, "failed to get clk: %d\n", rc);
6629         } else {
6630                 tp->clk = clk;
6631                 rc = clk_prepare_enable(clk);
6632                 if (rc)
6633                         dev_err(d, "failed to enable clk: %d\n", rc);
6634                 else
6635                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6636         }
6637
6638         return rc;
6639 }
6640
6641 static void rtl_init_mac_address(struct rtl8169_private *tp)
6642 {
6643         struct net_device *dev = tp->dev;
6644         u8 *mac_addr = dev->dev_addr;
6645         int rc;
6646
6647         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6648         if (!rc)
6649                 goto done;
6650
6651         rtl_read_mac_address(tp, mac_addr);
6652         if (is_valid_ether_addr(mac_addr))
6653                 goto done;
6654
6655         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
6656         if (is_valid_ether_addr(mac_addr))
6657                 goto done;
6658
6659         eth_hw_addr_random(dev);
6660         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6661 done:
6662         rtl_rar_set(tp, mac_addr);
6663 }
6664
6665 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6666 {
6667         struct rtl8169_private *tp;
6668         struct net_device *dev;
6669         int chipset, region;
6670         int jumbo_max, rc;
6671
6672         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6673         if (!dev)
6674                 return -ENOMEM;
6675
6676         SET_NETDEV_DEV(dev, &pdev->dev);
6677         dev->netdev_ops = &rtl_netdev_ops;
6678         tp = netdev_priv(dev);
6679         tp->dev = dev;
6680         tp->pci_dev = pdev;
6681         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6682         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6683
6684         /* Get the *optional* external "ether_clk" used on some boards */
6685         rc = rtl_get_ether_clk(tp);
6686         if (rc)
6687                 return rc;
6688
6689         /* Disable ASPM completely as that cause random device stop working
6690          * problems as well as full system hangs for some PCIe devices users.
6691          */
6692         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6693                                           PCIE_LINK_STATE_L1);
6694         tp->aspm_manageable = !rc;
6695
6696         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6697         rc = pcim_enable_device(pdev);
6698         if (rc < 0) {
6699                 dev_err(&pdev->dev, "enable failure\n");
6700                 return rc;
6701         }
6702
6703         if (pcim_set_mwi(pdev) < 0)
6704                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6705
6706         /* use first MMIO region */
6707         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6708         if (region < 0) {
6709                 dev_err(&pdev->dev, "no MMIO resource found\n");
6710                 return -ENODEV;
6711         }
6712
6713         /* check for weird/broken PCI region reporting */
6714         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6715                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6716                 return -ENODEV;
6717         }
6718
6719         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6720         if (rc < 0) {
6721                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6722                 return rc;
6723         }
6724
6725         tp->mmio_addr = pcim_iomap_table(pdev)[region];
6726
6727         /* Identify chip attached to board */
6728         rtl8169_get_mac_version(tp);
6729         if (tp->mac_version == RTL_GIGA_MAC_NONE)
6730                 return -ENODEV;
6731
6732         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6733
6734         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6735             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6736                 dev->features |= NETIF_F_HIGHDMA;
6737
6738         rtl_init_rxcfg(tp);
6739
6740         rtl8169_irq_mask_and_ack(tp);
6741
6742         rtl_hw_initialize(tp);
6743
6744         rtl_hw_reset(tp);
6745
6746         pci_set_master(pdev);
6747
6748         chipset = tp->mac_version;
6749
6750         rc = rtl_alloc_irq(tp);
6751         if (rc < 0) {
6752                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6753                 return rc;
6754         }
6755
6756         mutex_init(&tp->wk.mutex);
6757         INIT_WORK(&tp->wk.work, rtl_task);
6758         u64_stats_init(&tp->rx_stats.syncp);
6759         u64_stats_init(&tp->tx_stats.syncp);
6760
6761         rtl_init_mac_address(tp);
6762
6763         dev->ethtool_ops = &rtl8169_ethtool_ops;
6764
6765         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6766
6767         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6768                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6769                 NETIF_F_HW_VLAN_CTAG_RX;
6770         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6771                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6772                 NETIF_F_HW_VLAN_CTAG_RX;
6773         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6774                 NETIF_F_HIGHDMA;
6775         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6776
6777         tp->cp_cmd |= RxChkSum | RxVlan;
6778
6779         /*
6780          * Pretend we are using VLANs; This bypasses a nasty bug where
6781          * Interrupts stop flowing on high load on 8110SCd controllers.
6782          */
6783         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6784                 /* Disallow toggling */
6785                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6786
6787         if (rtl_chip_supports_csum_v2(tp)) {
6788                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6789                 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6790                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6791                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6792         } else {
6793                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6794                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6795         }
6796
6797         /* RTL8168e-vl has a HW issue with TSO */
6798         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
6799                 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6800                 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6801                 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6802         }
6803
6804         dev->hw_features |= NETIF_F_RXALL;
6805         dev->hw_features |= NETIF_F_RXFCS;
6806
6807         /* MTU range: 60 - hw-specific max */
6808         dev->min_mtu = ETH_ZLEN;
6809         jumbo_max = rtl_jumbo_max(tp);
6810         dev->max_mtu = jumbo_max;
6811
6812         rtl_set_irq_mask(tp);
6813
6814         tp->fw_name = rtl_chip_infos[chipset].fw_name;
6815
6816         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6817                                             &tp->counters_phys_addr,
6818                                             GFP_KERNEL);
6819         if (!tp->counters)
6820                 return -ENOMEM;
6821
6822         pci_set_drvdata(pdev, dev);
6823
6824         rc = r8169_mdio_register(tp);
6825         if (rc)
6826                 return rc;
6827
6828         /* chip gets powered up in rtl_open() */
6829         rtl_pll_power_down(tp);
6830
6831         rc = register_netdev(dev);
6832         if (rc)
6833                 goto err_mdio_unregister;
6834
6835         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6836                    rtl_chip_infos[chipset].name, dev->dev_addr,
6837                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6838                    pci_irq_vector(pdev, 0));
6839
6840         if (jumbo_max > JUMBO_1K)
6841                 netif_info(tp, probe, dev,
6842                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
6843                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
6844                            "ok" : "ko");
6845
6846         if (r8168_check_dash(tp))
6847                 rtl8168_driver_start(tp);
6848
6849         if (pci_dev_run_wake(pdev))
6850                 pm_runtime_put_sync(&pdev->dev);
6851
6852         return 0;
6853
6854 err_mdio_unregister:
6855         mdiobus_unregister(tp->phydev->mdio.bus);
6856         return rc;
6857 }
6858
6859 static struct pci_driver rtl8169_pci_driver = {
6860         .name           = MODULENAME,
6861         .id_table       = rtl8169_pci_tbl,
6862         .probe          = rtl_init_one,
6863         .remove         = rtl_remove_one,
6864         .shutdown       = rtl_shutdown,
6865         .driver.pm      = RTL8169_PM_OPS,
6866 };
6867
6868 module_pci_driver(rtl8169_pci_driver);