drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #include "r8169_firmware.h"
  36
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64 #define MC_FILTER_LIMIT 32
  65
  66 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69 #define R8169_REGS_SIZE         256
  70 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  73 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76 #define RTL_CFG_NO_GBIT 1
  77
  78 /* write/read MMIO register */
  79 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86 enum mac_version {
  87         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  88         RTL_GIGA_MAC_VER_02,
  89         RTL_GIGA_MAC_VER_03,
  90         RTL_GIGA_MAC_VER_04,
  91         RTL_GIGA_MAC_VER_05,
  92         RTL_GIGA_MAC_VER_06,
  93         RTL_GIGA_MAC_VER_07,
  94         RTL_GIGA_MAC_VER_08,
  95         RTL_GIGA_MAC_VER_09,
  96         RTL_GIGA_MAC_VER_10,
  97         RTL_GIGA_MAC_VER_11,
  98         RTL_GIGA_MAC_VER_12,
  99         RTL_GIGA_MAC_VER_13,
 100         RTL_GIGA_MAC_VER_14,
 101         RTL_GIGA_MAC_VER_15,
 102         RTL_GIGA_MAC_VER_16,
 103         RTL_GIGA_MAC_VER_17,
 104         RTL_GIGA_MAC_VER_18,
 105         RTL_GIGA_MAC_VER_19,
 106         RTL_GIGA_MAC_VER_20,
 107         RTL_GIGA_MAC_VER_21,
 108         RTL_GIGA_MAC_VER_22,
 109         RTL_GIGA_MAC_VER_23,
 110         RTL_GIGA_MAC_VER_24,
 111         RTL_GIGA_MAC_VER_25,
 112         RTL_GIGA_MAC_VER_26,
 113         RTL_GIGA_MAC_VER_27,
 114         RTL_GIGA_MAC_VER_28,
 115         RTL_GIGA_MAC_VER_29,
 116         RTL_GIGA_MAC_VER_30,
 117         RTL_GIGA_MAC_VER_31,
 118         RTL_GIGA_MAC_VER_32,
 119         RTL_GIGA_MAC_VER_33,
 120         RTL_GIGA_MAC_VER_34,
 121         RTL_GIGA_MAC_VER_35,
 122         RTL_GIGA_MAC_VER_36,
 123         RTL_GIGA_MAC_VER_37,
 124         RTL_GIGA_MAC_VER_38,
 125         RTL_GIGA_MAC_VER_39,
 126         RTL_GIGA_MAC_VER_40,
 127         RTL_GIGA_MAC_VER_41,
 128         RTL_GIGA_MAC_VER_42,
 129         RTL_GIGA_MAC_VER_43,
 130         RTL_GIGA_MAC_VER_44,
 131         RTL_GIGA_MAC_VER_45,
 132         RTL_GIGA_MAC_VER_46,
 133         RTL_GIGA_MAC_VER_47,
 134         RTL_GIGA_MAC_VER_48,
 135         RTL_GIGA_MAC_VER_49,
 136         RTL_GIGA_MAC_VER_50,
 137         RTL_GIGA_MAC_VER_51,
 138         RTL_GIGA_MAC_VER_60,
 139         RTL_GIGA_MAC_VER_61,
 140         RTL_GIGA_MAC_NONE
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 static const struct {
 150         const char *name;
 151         const char *fw_name;
 152 } rtl_chip_infos[] = {
 153         /* PCI devices. */
 154         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 155         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 156         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 157         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 158         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 159         /* PCI-E devices. */
 160         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 161         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 162         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 163         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 164         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 165         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 167         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 168         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 169         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 170         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 171         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 173         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 177         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 178         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 179         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 180         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 181         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 182         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 183         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 184         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 185         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 186         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 187         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 188         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 189         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 190         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 191         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 192         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 193         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 194         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 195         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 196         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 197         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 198         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 199         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 200         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 201         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 202         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 203         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 204         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_60] = {"RTL8125"                              },
 206         [RTL_GIGA_MAC_VER_61] = {"RTL8125"                              },
 207 };
 208
 209 static const struct pci_device_id rtl8169_pci_tbl[] = {
 210         { PCI_VDEVICE(REALTEK,  0x2502) },
 211         { PCI_VDEVICE(REALTEK,  0x2600) },
 212         { PCI_VDEVICE(REALTEK,  0x8129) },
 213         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 214         { PCI_VDEVICE(REALTEK,  0x8161) },
 215         { PCI_VDEVICE(REALTEK,  0x8167) },
 216         { PCI_VDEVICE(REALTEK,  0x8168) },
 217         { PCI_VDEVICE(NCUBE,    0x8168) },
 218         { PCI_VDEVICE(REALTEK,  0x8169) },
 219         { PCI_VENDOR_ID_DLINK,  0x4300,
 220                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 221         { PCI_VDEVICE(DLINK,    0x4300) },
 222         { PCI_VDEVICE(DLINK,    0x4302) },
 223         { PCI_VDEVICE(AT,       0xc107) },
 224         { PCI_VDEVICE(USR,      0x0116) },
 225         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 226         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 227         { PCI_VDEVICE(REALTEK,  0x8125) },
 228         { PCI_VDEVICE(REALTEK,  0x3000) },
 229         {}
 230 };
 231
 232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 233
 234 static struct {
 235         u32 msg_enable;
 236 } debug = { -1 };
 237
 238 enum rtl_registers {
 239         MAC0            = 0,    /* Ethernet hardware address. */
 240         MAC4            = 4,
 241         MAR0            = 8,    /* Multicast filter. */
 242         CounterAddrLow          = 0x10,
 243         CounterAddrHigh         = 0x14,
 244         TxDescStartAddrLow      = 0x20,
 245         TxDescStartAddrHigh     = 0x24,
 246         TxHDescStartAddrLow     = 0x28,
 247         TxHDescStartAddrHigh    = 0x2c,
 248         FLASH           = 0x30,
 249         ERSR            = 0x36,
 250         ChipCmd         = 0x37,
 251         TxPoll          = 0x38,
 252         IntrMask        = 0x3c,
 253         IntrStatus      = 0x3e,
 254
 255         TxConfig        = 0x40,
 256 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 257 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 258
 259         RxConfig        = 0x44,
 260 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 261 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 262 #define RXCFG_FIFO_SHIFT                13
 263                                         /* No threshold before first PCI xfer */
 264 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 265 #define RX_EARLY_OFF                    (1 << 11)
 266 #define RXCFG_DMA_SHIFT                 8
 267                                         /* Unlimited maximum PCI burst. */
 268 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 269
 270         RxMissed        = 0x4c,
 271         Cfg9346         = 0x50,
 272         Config0         = 0x51,
 273         Config1         = 0x52,
 274         Config2         = 0x53,
 275 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 276
 277         Config3         = 0x54,
 278         Config4         = 0x55,
 279         Config5         = 0x56,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl8125_registers {
 394         IntrMask_8125           = 0x38,
 395         IntrStatus_8125         = 0x3c,
 396         TxPoll_8125             = 0x90,
 397         MAC0_BKP                = 0x19e0,
 398 };
 399
 400 #define RX_VLAN_INNER_8125      BIT(22)
 401 #define RX_VLAN_OUTER_8125      BIT(23)
 402 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 403
 404 #define RX_FETCH_DFLT_8125      (8 << 27)
 405
 406 enum rtl_register_content {
 407         /* InterruptStatusBits */
 408         SYSErr          = 0x8000,
 409         PCSTimeout      = 0x4000,
 410         SWInt           = 0x0100,
 411         TxDescUnavail   = 0x0080,
 412         RxFIFOOver      = 0x0040,
 413         LinkChg         = 0x0020,
 414         RxOverflow      = 0x0010,
 415         TxErr           = 0x0008,
 416         TxOK            = 0x0004,
 417         RxErr           = 0x0002,
 418         RxOK            = 0x0001,
 419
 420         /* RxStatusDesc */
 421         RxRWT   = (1 << 22),
 422         RxRES   = (1 << 21),
 423         RxRUNT  = (1 << 20),
 424         RxCRC   = (1 << 19),
 425
 426         /* ChipCmdBits */
 427         StopReq         = 0x80,
 428         CmdReset        = 0x10,
 429         CmdRxEnb        = 0x08,
 430         CmdTxEnb        = 0x04,
 431         RxBufEmpty      = 0x01,
 432
 433         /* TXPoll register p.5 */
 434         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 435         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 436         FSWInt          = 0x01,         /* Forced software interrupt */
 437
 438         /* Cfg9346Bits */
 439         Cfg9346_Lock    = 0x00,
 440         Cfg9346_Unlock  = 0xc0,
 441
 442         /* rx_mode_bits */
 443         AcceptErr       = 0x20,
 444         AcceptRunt      = 0x10,
 445         AcceptBroadcast = 0x08,
 446         AcceptMulticast = 0x04,
 447         AcceptMyPhys    = 0x02,
 448         AcceptAllPhys   = 0x01,
 449 #define RX_CONFIG_ACCEPT_MASK           0x3f
 450
 451         /* TxConfigBits */
 452         TxInterFrameGapShift = 24,
 453         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 454
 455         /* Config1 register p.24 */
 456         LEDS1           = (1 << 7),
 457         LEDS0           = (1 << 6),
 458         Speed_down      = (1 << 4),
 459         MEMMAP          = (1 << 3),
 460         IOMAP           = (1 << 2),
 461         VPD             = (1 << 1),
 462         PMEnable        = (1 << 0),     /* Power Management Enable */
 463
 464         /* Config2 register p. 25 */
 465         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 466         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 467         PCI_Clock_66MHz = 0x01,
 468         PCI_Clock_33MHz = 0x00,
 469
 470         /* Config3 register p.25 */
 471         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 472         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 473         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 474         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 475         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 476
 477         /* Config4 register */
 478         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 479
 480         /* Config5 register p.27 */
 481         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 482         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 483         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 484         Spi_en          = (1 << 3),
 485         LanWake         = (1 << 1),     /* LanWake enable/disable */
 486         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 487         ASPM_en         = (1 << 0),     /* ASPM enable */
 488
 489         /* CPlusCmd p.31 */
 490         EnableBist      = (1 << 15),    // 8168 8101
 491         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 492         Normal_mode     = (1 << 13),    // unused
 493         Force_half_dup  = (1 << 12),    // 8168 8101
 494         Force_rxflow_en = (1 << 11),    // 8168 8101
 495         Force_txflow_en = (1 << 10),    // 8168 8101
 496         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 497         ASF             = (1 << 8),     // 8168 8101
 498         PktCntrDisable  = (1 << 7),     // 8168 8101
 499         Mac_dbgo_sel    = 0x001c,       // 8168
 500         RxVlan          = (1 << 6),
 501         RxChkSum        = (1 << 5),
 502         PCIDAC          = (1 << 4),
 503         PCIMulRW        = (1 << 3),
 504 #define INTT_MASK       GENMASK(1, 0)
 505 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 506
 507         /* rtl8169_PHYstatus */
 508         TBI_Enable      = 0x80,
 509         TxFlowCtrl      = 0x40,
 510         RxFlowCtrl      = 0x20,
 511         _1000bpsF       = 0x10,
 512         _100bps         = 0x08,
 513         _10bps          = 0x04,
 514         LinkStatus      = 0x02,
 515         FullDup         = 0x01,
 516
 517         /* ResetCounterCommand */
 518         CounterReset    = 0x1,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522
 523         /* magic enable v2 */
 524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* First doubleword. */
 557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559 #define GTTCPHO_SHIFT                   18
 560 #define GTTCPHO_MAX                     0x7f
 561
 562         /* Second doubleword. */
 563 #define TCPHO_SHIFT                     18
 564 #define TCPHO_MAX                       0x3ff
 565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570 };
 571
 572 enum rtl_rx_desc_bit {
 573         /* Rx private */
 574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577 #define RxProtoUDP      (PID1)
 578 #define RxProtoTCP      (PID0)
 579 #define RxProtoIP       (PID1 | PID0)
 580 #define RxProtoMask     RxProtoIP
 581
 582         IPFail          = (1 << 16), /* IP checksum failed */
 583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585         RxVlanTag       = (1 << 16), /* VLAN tag available */
 586 };
 587
 588 #define RsvdMask        0x3fffc000
 589
 590 #define RTL_GSO_MAX_SIZE_V1     32000
 591 #define RTL_GSO_MAX_SEGS_V1     24
 592 #define RTL_GSO_MAX_SIZE_V2     64000
 593 #define RTL_GSO_MAX_SEGS_V2     64
 594
 595 struct TxDesc {
 596         __le32 opts1;
 597         __le32 opts2;
 598         __le64 addr;
 599 };
 600
 601 struct RxDesc {
 602         __le32 opts1;
 603         __le32 opts2;
 604         __le64 addr;
 605 };
 606
 607 struct ring_info {
 608         struct sk_buff  *skb;
 609         u32             len;
 610 };
 611
 612 struct rtl8169_counters {
 613         __le64  tx_packets;
 614         __le64  rx_packets;
 615         __le64  tx_errors;
 616         __le32  rx_errors;
 617         __le16  rx_missed;
 618         __le16  align_errors;
 619         __le32  tx_one_collision;
 620         __le32  tx_multi_collision;
 621         __le64  rx_unicast;
 622         __le64  rx_broadcast;
 623         __le32  rx_multicast;
 624         __le16  tx_aborted;
 625         __le16  tx_underun;
 626 };
 627
 628 struct rtl8169_tc_offsets {
 629         bool    inited;
 630         __le64  tx_errors;
 631         __le32  tx_multi_collision;
 632         __le16  tx_aborted;
 633 };
 634
 635 enum rtl_flag {
 636         RTL_FLAG_TASK_ENABLED = 0,
 637         RTL_FLAG_TASK_RESET_PENDING,
 638         RTL_FLAG_MAX
 639 };
 640
 641 struct rtl8169_stats {
 642         u64                     packets;
 643         u64                     bytes;
 644         struct u64_stats_sync   syncp;
 645 };
 646
 647 struct rtl8169_private {
 648         void __iomem *mmio_addr;        /* memory map physical address */
 649         struct pci_dev *pci_dev;
 650         struct net_device *dev;
 651         struct phy_device *phydev;
 652         struct napi_struct napi;
 653         u32 msg_enable;
 654         enum mac_version mac_version;
 655         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 656         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 657         u32 dirty_tx;
 658         struct rtl8169_stats rx_stats;
 659         struct rtl8169_stats tx_stats;
 660         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 661         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 662         dma_addr_t TxPhyAddr;
 663         dma_addr_t RxPhyAddr;
 664         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 665         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 666         u16 cp_cmd;
 667         u32 irq_mask;
 668         struct clk *clk;
 669
 670         struct {
 671                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 672                 struct mutex mutex;
 673                 struct work_struct work;
 674         } wk;
 675
 676         unsigned irq_enabled:1;
 677         unsigned supports_gmii:1;
 678         unsigned aspm_manageable:1;
 679         dma_addr_t counters_phys_addr;
 680         struct rtl8169_counters *counters;
 681         struct rtl8169_tc_offsets tc_offset;
 682         u32 saved_wolopts;
 683
 684         const char *fw_name;
 685         struct rtl_fw *rtl_fw;
 686
 687         u32 ocp_base;
 688 };
 689
 690 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 691
 692 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 693 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 694 module_param_named(debug, debug.msg_enable, int, 0);
 695 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 696 MODULE_SOFTDEP("pre: realtek");
 697 MODULE_LICENSE("GPL");
 698 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 699 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 700 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 701 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 702 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 703 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 704 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 706 MODULE_FIRMWARE(FIRMWARE_8402_1);
 707 MODULE_FIRMWARE(FIRMWARE_8411_1);
 708 MODULE_FIRMWARE(FIRMWARE_8411_2);
 709 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 710 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 711 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 713 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 714 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 715 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 717
 718 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 719 {
 720         return &tp->pci_dev->dev;
 721 }
 722
 723 static void rtl_lock_work(struct rtl8169_private *tp)
 724 {
 725         mutex_lock(&tp->wk.mutex);
 726 }
 727
 728 static void rtl_unlock_work(struct rtl8169_private *tp)
 729 {
 730         mutex_unlock(&tp->wk.mutex);
 731 }
 732
 733 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 734 {
 735         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 736 }
 737
 738 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 739 {
 740         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 741 }
 742
 743 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 744 {
 745         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 746                                            PCI_EXP_DEVCTL_READRQ, force);
 747 }
 748
 749 static bool rtl_is_8125(struct rtl8169_private *tp)
 750 {
 751         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 752 }
 753
 754 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 755 {
 756         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 757                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 758                tp->mac_version <= RTL_GIGA_MAC_VER_51;
 759 }
 760
 761 static bool rtl_supports_eee(struct rtl8169_private *tp)
 762 {
 763         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 764                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 765                tp->mac_version != RTL_GIGA_MAC_VER_39;
 766 }
 767
 768 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 769 {
 770         int i;
 771
 772         for (i = 0; i < ETH_ALEN; i++)
 773                 mac[i] = RTL_R8(tp, reg + i);
 774 }
 775
 776 struct rtl_cond {
 777         bool (*check)(struct rtl8169_private *);
 778         const char *msg;
 779 };
 780
 781 static void rtl_udelay(unsigned int d)
 782 {
 783         udelay(d);
 784 }
 785
 786 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 787                           void (*delay)(unsigned int), unsigned int d, int n,
 788                           bool high)
 789 {
 790         int i;
 791
 792         for (i = 0; i < n; i++) {
 793                 if (c->check(tp) == high)
 794                         return true;
 795                 delay(d);
 796         }
 797         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 798                   c->msg, !high, n, d);
 799         return false;
 800 }
 801
 802 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 803                                       const struct rtl_cond *c,
 804                                       unsigned int d, int n)
 805 {
 806         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 807 }
 808
 809 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 810                                      const struct rtl_cond *c,
 811                                      unsigned int d, int n)
 812 {
 813         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 814 }
 815
 816 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 817                                       const struct rtl_cond *c,
 818                                       unsigned int d, int n)
 819 {
 820         return rtl_loop_wait(tp, c, msleep, d, n, true);
 821 }
 822
 823 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 824                                      const struct rtl_cond *c,
 825                                      unsigned int d, int n)
 826 {
 827         return rtl_loop_wait(tp, c, msleep, d, n, false);
 828 }
 829
 830 #define DECLARE_RTL_COND(name)                          \
 831 static bool name ## _check(struct rtl8169_private *);   \
 832                                                         \
 833 static const struct rtl_cond name = {                   \
 834         .check  = name ## _check,                       \
 835         .msg    = #name                                 \
 836 };                                                      \
 837                                                         \
 838 static bool name ## _check(struct rtl8169_private *tp)
 839
 840 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 841 {
 842         if (reg & 0xffff0001) {
 843                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 844                 return true;
 845         }
 846         return false;
 847 }
 848
 849 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 850 {
 851         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 852 }
 853
 854 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 855 {
 856         if (rtl_ocp_reg_failure(tp, reg))
 857                 return;
 858
 859         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 860
 861         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 862 }
 863
 864 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 865 {
 866         if (rtl_ocp_reg_failure(tp, reg))
 867                 return 0;
 868
 869         RTL_W32(tp, GPHY_OCP, reg << 15);
 870
 871         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 872                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 873 }
 874
 875 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 876 {
 877         if (rtl_ocp_reg_failure(tp, reg))
 878                 return;
 879
 880         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 881 }
 882
 883 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 884 {
 885         if (rtl_ocp_reg_failure(tp, reg))
 886                 return 0;
 887
 888         RTL_W32(tp, OCPDR, reg << 15);
 889
 890         return RTL_R32(tp, OCPDR);
 891 }
 892
 893 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 894                                  u16 set)
 895 {
 896         u16 data = r8168_mac_ocp_read(tp, reg);
 897
 898         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 899 }
 900
 901 #define OCP_STD_PHY_BASE        0xa400
 902
 903 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 904 {
 905         if (reg == 0x1f) {
 906                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 907                 return;
 908         }
 909
 910         if (tp->ocp_base != OCP_STD_PHY_BASE)
 911                 reg -= 0x10;
 912
 913         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 914 }
 915
 916 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 917 {
 918         if (tp->ocp_base != OCP_STD_PHY_BASE)
 919                 reg -= 0x10;
 920
 921         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 922 }
 923
 924 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 925 {
 926         if (reg == 0x1f) {
 927                 tp->ocp_base = value << 4;
 928                 return;
 929         }
 930
 931         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 932 }
 933
 934 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 935 {
 936         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 937 }
 938
 939 DECLARE_RTL_COND(rtl_phyar_cond)
 940 {
 941         return RTL_R32(tp, PHYAR) & 0x80000000;
 942 }
 943
 944 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 945 {
 946         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 947
 948         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 949         /*
 950          * According to hardware specs a 20us delay is required after write
 951          * complete indication, but before sending next command.
 952          */
 953         udelay(20);
 954 }
 955
 956 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 957 {
 958         int value;
 959
 960         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 961
 962         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 963                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 964
 965         /*
 966          * According to hardware specs a 20us delay is required after read
 967          * complete indication, but before sending next command.
 968          */
 969         udelay(20);
 970
 971         return value;
 972 }
 973
 974 DECLARE_RTL_COND(rtl_ocpar_cond)
 975 {
 976         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 977 }
 978
 979 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 980 {
 981         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 982         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 983         RTL_W32(tp, EPHY_RXER_NUM, 0);
 984
 985         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 986 }
 987
 988 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 989 {
 990         r8168dp_1_mdio_access(tp, reg,
 991                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 992 }
 993
 994 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 995 {
 996         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 997
 998         mdelay(1);
 999         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1000         RTL_W32(tp, EPHY_RXER_NUM, 0);
1001
1002         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1003                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1004 }
1005
1006 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1007
1008 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1009 {
1010         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1011 }
1012
1013 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1014 {
1015         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1016 }
1017
1018 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1019 {
1020         r8168dp_2_mdio_start(tp);
1021
1022         r8169_mdio_write(tp, reg, value);
1023
1024         r8168dp_2_mdio_stop(tp);
1025 }
1026
1027 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1028 {
1029         int value;
1030
1031         r8168dp_2_mdio_start(tp);
1032
1033         value = r8169_mdio_read(tp, reg);
1034
1035         r8168dp_2_mdio_stop(tp);
1036
1037         return value;
1038 }
1039
1040 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1041 {
1042         switch (tp->mac_version) {
1043         case RTL_GIGA_MAC_VER_27:
1044                 r8168dp_1_mdio_write(tp, location, val);
1045                 break;
1046         case RTL_GIGA_MAC_VER_28:
1047         case RTL_GIGA_MAC_VER_31:
1048                 r8168dp_2_mdio_write(tp, location, val);
1049                 break;
1050         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1051                 r8168g_mdio_write(tp, location, val);
1052                 break;
1053         default:
1054                 r8169_mdio_write(tp, location, val);
1055                 break;
1056         }
1057 }
1058
1059 static int rtl_readphy(struct rtl8169_private *tp, int location)
1060 {
1061         switch (tp->mac_version) {
1062         case RTL_GIGA_MAC_VER_27:
1063                 return r8168dp_1_mdio_read(tp, location);
1064         case RTL_GIGA_MAC_VER_28:
1065         case RTL_GIGA_MAC_VER_31:
1066                 return r8168dp_2_mdio_read(tp, location);
1067         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1068                 return r8168g_mdio_read(tp, location);
1069         default:
1070                 return r8169_mdio_read(tp, location);
1071         }
1072 }
1073
1074 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1075 {
1076         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1077 }
1078
1079 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1080 {
1081         int val;
1082
1083         val = rtl_readphy(tp, reg_addr);
1084         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1085 }
1086
1087 DECLARE_RTL_COND(rtl_ephyar_cond)
1088 {
1089         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1090 }
1091
1092 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1093 {
1094         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1095                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1096
1097         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1098
1099         udelay(10);
1100 }
1101
1102 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1103 {
1104         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1105
1106         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1107                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1108 }
1109
1110 DECLARE_RTL_COND(rtl_eriar_cond)
1111 {
1112         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1113 }
1114
1115 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1116                            u32 val, int type)
1117 {
1118         BUG_ON((addr & 3) || (mask == 0));
1119         RTL_W32(tp, ERIDR, val);
1120         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1121
1122         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1123 }
1124
1125 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1126                           u32 val)
1127 {
1128         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1129 }
1130
1131 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1132 {
1133         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1134
1135         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1136                 RTL_R32(tp, ERIDR) : ~0;
1137 }
1138
1139 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1140 {
1141         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1142 }
1143
1144 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1145                          u32 m)
1146 {
1147         u32 val;
1148
1149         val = rtl_eri_read(tp, addr);
1150         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1151 }
1152
1153 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1154                              u32 p)
1155 {
1156         rtl_w0w1_eri(tp, addr, mask, p, 0);
1157 }
1158
1159 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1160                                u32 m)
1161 {
1162         rtl_w0w1_eri(tp, addr, mask, 0, m);
1163 }
1164
1165 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1166 {
1167         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1168         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1169                 RTL_R32(tp, OCPDR) : ~0;
1170 }
1171
1172 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1173 {
1174         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1175 }
1176
1177 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1178                               u32 data)
1179 {
1180         RTL_W32(tp, OCPDR, data);
1181         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1182         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1183 }
1184
1185 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1186                               u32 data)
1187 {
1188         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1189                        data, ERIAR_OOB);
1190 }
1191
1192 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1193 {
1194         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1195
1196         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1197 }
1198
1199 #define OOB_CMD_RESET           0x00
1200 #define OOB_CMD_DRIVER_START    0x05
1201 #define OOB_CMD_DRIVER_STOP     0x06
1202
1203 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1204 {
1205         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1206 }
1207
1208 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1209 {
1210         u16 reg;
1211
1212         reg = rtl8168_get_ocp_reg(tp);
1213
1214         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1215 }
1216
1217 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1218 {
1219         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1220 }
1221
1222 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1223 {
1224         return RTL_R8(tp, IBISR0) & 0x20;
1225 }
1226
1227 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1228 {
1229         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1230         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1231         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1232         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1233 }
1234
1235 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1236 {
1237         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1238         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1239 }
1240
1241 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1242 {
1243         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1244         r8168ep_ocp_write(tp, 0x01, 0x30,
1245                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1246         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1247 }
1248
1249 static void rtl8168_driver_start(struct rtl8169_private *tp)
1250 {
1251         switch (tp->mac_version) {
1252         case RTL_GIGA_MAC_VER_27:
1253         case RTL_GIGA_MAC_VER_28:
1254         case RTL_GIGA_MAC_VER_31:
1255                 rtl8168dp_driver_start(tp);
1256                 break;
1257         case RTL_GIGA_MAC_VER_49:
1258         case RTL_GIGA_MAC_VER_50:
1259         case RTL_GIGA_MAC_VER_51:
1260                 rtl8168ep_driver_start(tp);
1261                 break;
1262         default:
1263                 BUG();
1264                 break;
1265         }
1266 }
1267
1268 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1269 {
1270         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1271         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1272 }
1273
1274 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1275 {
1276         rtl8168ep_stop_cmac(tp);
1277         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1278         r8168ep_ocp_write(tp, 0x01, 0x30,
1279                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1280         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1281 }
1282
1283 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1284 {
1285         switch (tp->mac_version) {
1286         case RTL_GIGA_MAC_VER_27:
1287         case RTL_GIGA_MAC_VER_28:
1288         case RTL_GIGA_MAC_VER_31:
1289                 rtl8168dp_driver_stop(tp);
1290                 break;
1291         case RTL_GIGA_MAC_VER_49:
1292         case RTL_GIGA_MAC_VER_50:
1293         case RTL_GIGA_MAC_VER_51:
1294                 rtl8168ep_driver_stop(tp);
1295                 break;
1296         default:
1297                 BUG();
1298                 break;
1299         }
1300 }
1301
1302 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1303 {
1304         u16 reg = rtl8168_get_ocp_reg(tp);
1305
1306         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1307 }
1308
1309 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1310 {
1311         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1312 }
1313
1314 static bool r8168_check_dash(struct rtl8169_private *tp)
1315 {
1316         switch (tp->mac_version) {
1317         case RTL_GIGA_MAC_VER_27:
1318         case RTL_GIGA_MAC_VER_28:
1319         case RTL_GIGA_MAC_VER_31:
1320                 return r8168dp_check_dash(tp);
1321         case RTL_GIGA_MAC_VER_49:
1322         case RTL_GIGA_MAC_VER_50:
1323         case RTL_GIGA_MAC_VER_51:
1324                 return r8168ep_check_dash(tp);
1325         default:
1326                 return false;
1327         }
1328 }
1329
1330 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1331 {
1332         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1333         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1334 }
1335
1336 DECLARE_RTL_COND(rtl_efusear_cond)
1337 {
1338         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1339 }
1340
1341 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1342 {
1343         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1344
1345         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1346                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1347 }
1348
1349 static u32 rtl_get_events(struct rtl8169_private *tp)
1350 {
1351         if (rtl_is_8125(tp))
1352                 return RTL_R32(tp, IntrStatus_8125);
1353         else
1354                 return RTL_R16(tp, IntrStatus);
1355 }
1356
1357 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1358 {
1359         if (rtl_is_8125(tp))
1360                 RTL_W32(tp, IntrStatus_8125, bits);
1361         else
1362                 RTL_W16(tp, IntrStatus, bits);
1363 }
1364
1365 static void rtl_irq_disable(struct rtl8169_private *tp)
1366 {
1367         if (rtl_is_8125(tp))
1368                 RTL_W32(tp, IntrMask_8125, 0);
1369         else
1370                 RTL_W16(tp, IntrMask, 0);
1371         tp->irq_enabled = 0;
1372 }
1373
1374 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1375 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1376 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1377
1378 static void rtl_irq_enable(struct rtl8169_private *tp)
1379 {
1380         tp->irq_enabled = 1;
1381         if (rtl_is_8125(tp))
1382                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1383         else
1384                 RTL_W16(tp, IntrMask, tp->irq_mask);
1385 }
1386
1387 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1388 {
1389         rtl_irq_disable(tp);
1390         rtl_ack_events(tp, 0xffffffff);
1391         /* PCI commit */
1392         RTL_R8(tp, ChipCmd);
1393 }
1394
1395 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1396 {
1397         struct net_device *dev = tp->dev;
1398         struct phy_device *phydev = tp->phydev;
1399
1400         if (!netif_running(dev))
1401                 return;
1402
1403         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1404             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1405                 if (phydev->speed == SPEED_1000) {
1406                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1407                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1408                 } else if (phydev->speed == SPEED_100) {
1409                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1410                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1411                 } else {
1412                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1413                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1414                 }
1415                 rtl_reset_packet_filter(tp);
1416         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1417                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1418                 if (phydev->speed == SPEED_1000) {
1419                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1420                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1421                 } else {
1422                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1423                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1424                 }
1425         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1426                 if (phydev->speed == SPEED_10) {
1427                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1428                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1429                 } else {
1430                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1431                 }
1432         }
1433 }
1434
1435 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1436
1437 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1438 {
1439         struct rtl8169_private *tp = netdev_priv(dev);
1440
1441         rtl_lock_work(tp);
1442         wol->supported = WAKE_ANY;
1443         wol->wolopts = tp->saved_wolopts;
1444         rtl_unlock_work(tp);
1445 }
1446
1447 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1448 {
1449         static const struct {
1450                 u32 opt;
1451                 u16 reg;
1452                 u8  mask;
1453         } cfg[] = {
1454                 { WAKE_PHY,   Config3, LinkUp },
1455                 { WAKE_UCAST, Config5, UWF },
1456                 { WAKE_BCAST, Config5, BWF },
1457                 { WAKE_MCAST, Config5, MWF },
1458                 { WAKE_ANY,   Config5, LanWake },
1459                 { WAKE_MAGIC, Config3, MagicPacket }
1460         };
1461         unsigned int i, tmp = ARRAY_SIZE(cfg);
1462         u8 options;
1463
1464         rtl_unlock_config_regs(tp);
1465
1466         if (rtl_is_8168evl_up(tp)) {
1467                 tmp--;
1468                 if (wolopts & WAKE_MAGIC)
1469                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1470                                          MagicPacket_v2);
1471                 else
1472                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1473                                            MagicPacket_v2);
1474         } else if (rtl_is_8125(tp)) {
1475                 tmp--;
1476                 if (wolopts & WAKE_MAGIC)
1477                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1478                 else
1479                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1480         }
1481
1482         for (i = 0; i < tmp; i++) {
1483                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1484                 if (wolopts & cfg[i].opt)
1485                         options |= cfg[i].mask;
1486                 RTL_W8(tp, cfg[i].reg, options);
1487         }
1488
1489         switch (tp->mac_version) {
1490         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1491                 options = RTL_R8(tp, Config1) & ~PMEnable;
1492                 if (wolopts)
1493                         options |= PMEnable;
1494                 RTL_W8(tp, Config1, options);
1495                 break;
1496         case RTL_GIGA_MAC_VER_34:
1497         case RTL_GIGA_MAC_VER_37:
1498         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1499                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1500                 if (wolopts)
1501                         options |= PME_SIGNAL;
1502                 RTL_W8(tp, Config2, options);
1503                 break;
1504         default:
1505                 break;
1506         }
1507
1508         rtl_lock_config_regs(tp);
1509
1510         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1511 }
1512
1513 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1514 {
1515         struct rtl8169_private *tp = netdev_priv(dev);
1516         struct device *d = tp_to_dev(tp);
1517
1518         if (wol->wolopts & ~WAKE_ANY)
1519                 return -EINVAL;
1520
1521         pm_runtime_get_noresume(d);
1522
1523         rtl_lock_work(tp);
1524
1525         tp->saved_wolopts = wol->wolopts;
1526
1527         if (pm_runtime_active(d))
1528                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1529
1530         rtl_unlock_work(tp);
1531
1532         pm_runtime_put_noidle(d);
1533
1534         return 0;
1535 }
1536
1537 static void rtl8169_get_drvinfo(struct net_device *dev,
1538                                 struct ethtool_drvinfo *info)
1539 {
1540         struct rtl8169_private *tp = netdev_priv(dev);
1541         struct rtl_fw *rtl_fw = tp->rtl_fw;
1542
1543         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1544         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1545         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1546         if (rtl_fw)
1547                 strlcpy(info->fw_version, rtl_fw->version,
1548                         sizeof(info->fw_version));
1549 }
1550
1551 static int rtl8169_get_regs_len(struct net_device *dev)
1552 {
1553         return R8169_REGS_SIZE;
1554 }
1555
1556 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1557         netdev_features_t features)
1558 {
1559         struct rtl8169_private *tp = netdev_priv(dev);
1560
1561         if (dev->mtu > TD_MSS_MAX)
1562                 features &= ~NETIF_F_ALL_TSO;
1563
1564         if (dev->mtu > JUMBO_1K &&
1565             tp->mac_version > RTL_GIGA_MAC_VER_06)
1566                 features &= ~NETIF_F_IP_CSUM;
1567
1568         return features;
1569 }
1570
1571 static int rtl8169_set_features(struct net_device *dev,
1572                                 netdev_features_t features)
1573 {
1574         struct rtl8169_private *tp = netdev_priv(dev);
1575         u32 rx_config;
1576
1577         rtl_lock_work(tp);
1578
1579         rx_config = RTL_R32(tp, RxConfig);
1580         if (features & NETIF_F_RXALL)
1581                 rx_config |= (AcceptErr | AcceptRunt);
1582         else
1583                 rx_config &= ~(AcceptErr | AcceptRunt);
1584
1585         if (rtl_is_8125(tp)) {
1586                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1587                         rx_config |= RX_VLAN_8125;
1588                 else
1589                         rx_config &= ~RX_VLAN_8125;
1590         }
1591
1592         RTL_W32(tp, RxConfig, rx_config);
1593
1594         if (features & NETIF_F_RXCSUM)
1595                 tp->cp_cmd |= RxChkSum;
1596         else
1597                 tp->cp_cmd &= ~RxChkSum;
1598
1599         if (!rtl_is_8125(tp)) {
1600                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1601                         tp->cp_cmd |= RxVlan;
1602                 else
1603                         tp->cp_cmd &= ~RxVlan;
1604         }
1605
1606         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1607         RTL_R16(tp, CPlusCmd);
1608
1609         rtl_unlock_work(tp);
1610
1611         return 0;
1612 }
1613
1614 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1615 {
1616         return (skb_vlan_tag_present(skb)) ?
1617                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1618 }
1619
1620 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1621 {
1622         u32 opts2 = le32_to_cpu(desc->opts2);
1623
1624         if (opts2 & RxVlanTag)
1625                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1626 }
1627
1628 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1629                              void *p)
1630 {
1631         struct rtl8169_private *tp = netdev_priv(dev);
1632         u32 __iomem *data = tp->mmio_addr;
1633         u32 *dw = p;
1634         int i;
1635
1636         rtl_lock_work(tp);
1637         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1638                 memcpy_fromio(dw++, data++, 4);
1639         rtl_unlock_work(tp);
1640 }
1641
1642 static u32 rtl8169_get_msglevel(struct net_device *dev)
1643 {
1644         struct rtl8169_private *tp = netdev_priv(dev);
1645
1646         return tp->msg_enable;
1647 }
1648
1649 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1650 {
1651         struct rtl8169_private *tp = netdev_priv(dev);
1652
1653         tp->msg_enable = value;
1654 }
1655
1656 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1657         "tx_packets",
1658         "rx_packets",
1659         "tx_errors",
1660         "rx_errors",
1661         "rx_missed",
1662         "align_errors",
1663         "tx_single_collisions",
1664         "tx_multi_collisions",
1665         "unicast",
1666         "broadcast",
1667         "multicast",
1668         "tx_aborted",
1669         "tx_underrun",
1670 };
1671
1672 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1673 {
1674         switch (sset) {
1675         case ETH_SS_STATS:
1676                 return ARRAY_SIZE(rtl8169_gstrings);
1677         default:
1678                 return -EOPNOTSUPP;
1679         }
1680 }
1681
1682 DECLARE_RTL_COND(rtl_counters_cond)
1683 {
1684         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1685 }
1686
1687 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1688 {
1689         dma_addr_t paddr = tp->counters_phys_addr;
1690         u32 cmd;
1691
1692         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1693         RTL_R32(tp, CounterAddrHigh);
1694         cmd = (u64)paddr & DMA_BIT_MASK(32);
1695         RTL_W32(tp, CounterAddrLow, cmd);
1696         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1697
1698         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1699 }
1700
1701 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1702 {
1703         /*
1704          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1705          * tally counters.
1706          */
1707         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1708                 return true;
1709
1710         return rtl8169_do_counters(tp, CounterReset);
1711 }
1712
1713 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1714 {
1715         u8 val = RTL_R8(tp, ChipCmd);
1716
1717         /*
1718          * Some chips are unable to dump tally counters when the receiver
1719          * is disabled. If 0xff chip may be in a PCI power-save state.
1720          */
1721         if (!(val & CmdRxEnb) || val == 0xff)
1722                 return true;
1723
1724         return rtl8169_do_counters(tp, CounterDump);
1725 }
1726
1727 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1728 {
1729         struct rtl8169_counters *counters = tp->counters;
1730         bool ret = false;
1731
1732         /*
1733          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1734          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1735          * reset by a power cycle, while the counter values collected by the
1736          * driver are reset at every driver unload/load cycle.
1737          *
1738          * To make sure the HW values returned by @get_stats64 match the SW
1739          * values, we collect the initial values at first open(*) and use them
1740          * as offsets to normalize the values returned by @get_stats64.
1741          *
1742          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1743          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1744          * set at open time by rtl_hw_start.
1745          */
1746
1747         if (tp->tc_offset.inited)
1748                 return true;
1749
1750         /* If both, reset and update fail, propagate to caller. */
1751         if (rtl8169_reset_counters(tp))
1752                 ret = true;
1753
1754         if (rtl8169_update_counters(tp))
1755                 ret = true;
1756
1757         tp->tc_offset.tx_errors = counters->tx_errors;
1758         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1759         tp->tc_offset.tx_aborted = counters->tx_aborted;
1760         tp->tc_offset.inited = true;
1761
1762         return ret;
1763 }
1764
1765 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1766                                       struct ethtool_stats *stats, u64 *data)
1767 {
1768         struct rtl8169_private *tp = netdev_priv(dev);
1769         struct device *d = tp_to_dev(tp);
1770         struct rtl8169_counters *counters = tp->counters;
1771
1772         ASSERT_RTNL();
1773
1774         pm_runtime_get_noresume(d);
1775
1776         if (pm_runtime_active(d))
1777                 rtl8169_update_counters(tp);
1778
1779         pm_runtime_put_noidle(d);
1780
1781         data[0] = le64_to_cpu(counters->tx_packets);
1782         data[1] = le64_to_cpu(counters->rx_packets);
1783         data[2] = le64_to_cpu(counters->tx_errors);
1784         data[3] = le32_to_cpu(counters->rx_errors);
1785         data[4] = le16_to_cpu(counters->rx_missed);
1786         data[5] = le16_to_cpu(counters->align_errors);
1787         data[6] = le32_to_cpu(counters->tx_one_collision);
1788         data[7] = le32_to_cpu(counters->tx_multi_collision);
1789         data[8] = le64_to_cpu(counters->rx_unicast);
1790         data[9] = le64_to_cpu(counters->rx_broadcast);
1791         data[10] = le32_to_cpu(counters->rx_multicast);
1792         data[11] = le16_to_cpu(counters->tx_aborted);
1793         data[12] = le16_to_cpu(counters->tx_underun);
1794 }
1795
1796 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1797 {
1798         switch(stringset) {
1799         case ETH_SS_STATS:
1800                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1801                 break;
1802         }
1803 }
1804
1805 /*
1806  * Interrupt coalescing
1807  *
1808  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1809  * >     8169, 8168 and 810x line of chipsets
1810  *
1811  * 8169, 8168, and 8136(810x) serial chipsets support it.
1812  *
1813  * > 2 - the Tx timer unit at gigabit speed
1814  *
1815  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1816  * (0xe0) bit 1 and bit 0.
1817  *
1818  * For 8169
1819  * bit[1:0] \ speed        1000M           100M            10M
1820  * 0 0                     320ns           2.56us          40.96us
1821  * 0 1                     2.56us          20.48us         327.7us
1822  * 1 0                     5.12us          40.96us         655.4us
1823  * 1 1                     10.24us         81.92us         1.31ms
1824  *
1825  * For the other
1826  * bit[1:0] \ speed        1000M           100M            10M
1827  * 0 0                     5us             2.56us          40.96us
1828  * 0 1                     40us            20.48us         327.7us
1829  * 1 0                     80us            40.96us         655.4us
1830  * 1 1                     160us           81.92us         1.31ms
1831  */
1832
1833 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1834 struct rtl_coalesce_scale {
1835         /* Rx / Tx */
1836         u32 nsecs[2];
1837 };
1838
1839 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1840 struct rtl_coalesce_info {
1841         u32 speed;
1842         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1843 };
1844
1845 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1846 #define rxtx_x1822(r, t) {              \
1847         {{(r),          (t)}},          \
1848         {{(r)*8,        (t)*8}},        \
1849         {{(r)*8*2,      (t)*8*2}},      \
1850         {{(r)*8*2*2,    (t)*8*2*2}},    \
1851 }
1852 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1853         /* speed        delays:     rx00   tx00 */
1854         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1855         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1856         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1857         { 0 },
1858 };
1859
1860 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1861         /* speed        delays:     rx00   tx00 */
1862         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1863         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1864         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1865         { 0 },
1866 };
1867 #undef rxtx_x1822
1868
1869 /* get rx/tx scale vector corresponding to current speed */
1870 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1871 {
1872         struct rtl8169_private *tp = netdev_priv(dev);
1873         const struct rtl_coalesce_info *ci;
1874
1875         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1876                 ci = rtl_coalesce_info_8169;
1877         else
1878                 ci = rtl_coalesce_info_8168_8136;
1879
1880         for (; ci->speed; ci++) {
1881                 if (tp->phydev->speed == ci->speed)
1882                         return ci;
1883         }
1884
1885         return ERR_PTR(-ELNRNG);
1886 }
1887
1888 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1889 {
1890         struct rtl8169_private *tp = netdev_priv(dev);
1891         const struct rtl_coalesce_info *ci;
1892         const struct rtl_coalesce_scale *scale;
1893         struct {
1894                 u32 *max_frames;
1895                 u32 *usecs;
1896         } coal_settings [] = {
1897                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1898                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1899         }, *p = coal_settings;
1900         int i;
1901         u16 w;
1902
1903         if (rtl_is_8125(tp))
1904                 return -EOPNOTSUPP;
1905
1906         memset(ec, 0, sizeof(*ec));
1907
1908         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1909         ci = rtl_coalesce_info(dev);
1910         if (IS_ERR(ci))
1911                 return PTR_ERR(ci);
1912
1913         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1914
1915         /* read IntrMitigate and adjust according to scale */
1916         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1917                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1918                 w >>= RTL_COALESCE_SHIFT;
1919                 *p->usecs = w & RTL_COALESCE_MASK;
1920         }
1921
1922         for (i = 0; i < 2; i++) {
1923                 p = coal_settings + i;
1924                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1925
1926                 /*
1927                  * ethtool_coalesce says it is illegal to set both usecs and
1928                  * max_frames to 0.
1929                  */
1930                 if (!*p->usecs && !*p->max_frames)
1931                         *p->max_frames = 1;
1932         }
1933
1934         return 0;
1935 }
1936
1937 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1938 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1939                         struct net_device *dev, u32 nsec, u16 *cp01)
1940 {
1941         const struct rtl_coalesce_info *ci;
1942         u16 i;
1943
1944         ci = rtl_coalesce_info(dev);
1945         if (IS_ERR(ci))
1946                 return ERR_CAST(ci);
1947
1948         for (i = 0; i < 4; i++) {
1949                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1950                                         ci->scalev[i].nsecs[1]);
1951                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1952                         *cp01 = i;
1953                         return &ci->scalev[i];
1954                 }
1955         }
1956
1957         return ERR_PTR(-EINVAL);
1958 }
1959
1960 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1961 {
1962         struct rtl8169_private *tp = netdev_priv(dev);
1963         const struct rtl_coalesce_scale *scale;
1964         struct {
1965                 u32 frames;
1966                 u32 usecs;
1967         } coal_settings [] = {
1968                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1969                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1970         }, *p = coal_settings;
1971         u16 w = 0, cp01;
1972         int i;
1973
1974         if (rtl_is_8125(tp))
1975                 return -EOPNOTSUPP;
1976
1977         scale = rtl_coalesce_choose_scale(dev,
1978                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1979         if (IS_ERR(scale))
1980                 return PTR_ERR(scale);
1981
1982         for (i = 0; i < 2; i++, p++) {
1983                 u32 units;
1984
1985                 /*
1986                  * accept max_frames=1 we returned in rtl_get_coalesce.
1987                  * accept it not only when usecs=0 because of e.g. the following scenario:
1988                  *
1989                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1990                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1991                  * - then user does `ethtool -C eth0 rx-usecs 100`
1992                  *
1993                  * since ethtool sends to kernel whole ethtool_coalesce
1994                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1995                  * we'll reject it below in `frames % 4 != 0`.
1996                  */
1997                 if (p->frames == 1) {
1998                         p->frames = 0;
1999                 }
2000
2001                 units = p->usecs * 1000 / scale->nsecs[i];
2002                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2003                         return -EINVAL;
2004
2005                 w <<= RTL_COALESCE_SHIFT;
2006                 w |= units;
2007                 w <<= RTL_COALESCE_SHIFT;
2008                 w |= p->frames >> 2;
2009         }
2010
2011         rtl_lock_work(tp);
2012
2013         RTL_W16(tp, IntrMitigate, swab16(w));
2014
2015         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2016         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2017         RTL_R16(tp, CPlusCmd);
2018
2019         rtl_unlock_work(tp);
2020
2021         return 0;
2022 }
2023
2024 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2025 {
2026         struct rtl8169_private *tp = netdev_priv(dev);
2027         struct device *d = tp_to_dev(tp);
2028         int ret;
2029
2030         if (!rtl_supports_eee(tp))
2031                 return -EOPNOTSUPP;
2032
2033         pm_runtime_get_noresume(d);
2034
2035         if (!pm_runtime_active(d)) {
2036                 ret = -EOPNOTSUPP;
2037         } else {
2038                 ret = phy_ethtool_get_eee(tp->phydev, data);
2039         }
2040
2041         pm_runtime_put_noidle(d);
2042
2043         return ret;
2044 }
2045
2046 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2047 {
2048         struct rtl8169_private *tp = netdev_priv(dev);
2049         struct device *d = tp_to_dev(tp);
2050         int ret;
2051
2052         if (!rtl_supports_eee(tp))
2053                 return -EOPNOTSUPP;
2054
2055         pm_runtime_get_noresume(d);
2056
2057         if (!pm_runtime_active(d)) {
2058                 ret = -EOPNOTSUPP;
2059                 goto out;
2060         }
2061
2062         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2063             dev->phydev->duplex != DUPLEX_FULL) {
2064                 ret = -EPROTONOSUPPORT;
2065                 goto out;
2066         }
2067
2068         ret = phy_ethtool_set_eee(tp->phydev, data);
2069 out:
2070         pm_runtime_put_noidle(d);
2071         return ret;
2072 }
2073
2074 static const struct ethtool_ops rtl8169_ethtool_ops = {
2075         .get_drvinfo            = rtl8169_get_drvinfo,
2076         .get_regs_len           = rtl8169_get_regs_len,
2077         .get_link               = ethtool_op_get_link,
2078         .get_coalesce           = rtl_get_coalesce,
2079         .set_coalesce           = rtl_set_coalesce,
2080         .get_msglevel           = rtl8169_get_msglevel,
2081         .set_msglevel           = rtl8169_set_msglevel,
2082         .get_regs               = rtl8169_get_regs,
2083         .get_wol                = rtl8169_get_wol,
2084         .set_wol                = rtl8169_set_wol,
2085         .get_strings            = rtl8169_get_strings,
2086         .get_sset_count         = rtl8169_get_sset_count,
2087         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2088         .get_ts_info            = ethtool_op_get_ts_info,
2089         .nway_reset             = phy_ethtool_nway_reset,
2090         .get_eee                = rtl8169_get_eee,
2091         .set_eee                = rtl8169_set_eee,
2092         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2093         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2094 };
2095
2096 static void rtl_enable_eee(struct rtl8169_private *tp)
2097 {
2098         struct phy_device *phydev = tp->phydev;
2099         int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2100
2101         if (supported > 0)
2102                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2103 }
2104
2105 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2106 {
2107         /*
2108          * The driver currently handles the 8168Bf and the 8168Be identically
2109          * but they can be identified more specifically through the test below
2110          * if needed:
2111          *
2112          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2113          *
2114          * Same thing for the 8101Eb and the 8101Ec:
2115          *
2116          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2117          */
2118         static const struct rtl_mac_info {
2119                 u16 mask;
2120                 u16 val;
2121                 u16 mac_version;
2122         } mac_info[] = {
2123                 /* 8125 family. */
2124                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2125                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2126
2127                 /* 8168EP family. */
2128                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2129                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2130                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2131
2132                 /* 8168H family. */
2133                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2134                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2135
2136                 /* 8168G family. */
2137                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2138                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2139                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2140                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2141
2142                 /* 8168F family. */
2143                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2144                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2145                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2146
2147                 /* 8168E family. */
2148                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2149                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2150                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2151
2152                 /* 8168D family. */
2153                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2154                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2155
2156                 /* 8168DP family. */
2157                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2158                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2159                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2160
2161                 /* 8168C family. */
2162                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2163                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2164                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2165                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2166                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2167                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2168                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2169
2170                 /* 8168B family. */
2171                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2172                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2173                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2174
2175                 /* 8101 family. */
2176                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2177                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2178                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2179                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2180                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2181                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2182                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2183                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2184                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2185                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2186                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2187                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2188                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2189                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2190                 /* FIXME: where did these entries come from ? -- FR */
2191                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2192                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2193
2194                 /* 8110 family. */
2195                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2196                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2197                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2198                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2199                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2200
2201                 /* Catch-all */
2202                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2203         };
2204         const struct rtl_mac_info *p = mac_info;
2205         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2206
2207         while ((reg & p->mask) != p->val)
2208                 p++;
2209         tp->mac_version = p->mac_version;
2210
2211         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2212                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2213         } else if (!tp->supports_gmii) {
2214                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2215                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2216                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2217                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2218                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2219                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2220         }
2221 }
2222
2223 struct phy_reg {
2224         u16 reg;
2225         u16 val;
2226 };
2227
2228 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2229                                  const struct phy_reg *regs, int len)
2230 {
2231         while (len-- > 0) {
2232                 rtl_writephy(tp, regs->reg, regs->val);
2233                 regs++;
2234         }
2235 }
2236
2237 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2238
2239 static void rtl_release_firmware(struct rtl8169_private *tp)
2240 {
2241         if (tp->rtl_fw) {
2242                 rtl_fw_release_firmware(tp->rtl_fw);
2243                 kfree(tp->rtl_fw);
2244                 tp->rtl_fw = NULL;
2245         }
2246 }
2247
2248 static void rtl_apply_firmware(struct rtl8169_private *tp)
2249 {
2250         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2251         if (tp->rtl_fw)
2252                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2253 }
2254
2255 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2256 {
2257         if (rtl_readphy(tp, reg) != val)
2258                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2259         else
2260                 rtl_apply_firmware(tp);
2261 }
2262
2263 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2264 {
2265         /* Adjust EEE LED frequency */
2266         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2267                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2268
2269         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2270 }
2271
2272 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2273 {
2274         struct phy_device *phydev = tp->phydev;
2275
2276         phy_write(phydev, 0x1f, 0x0007);
2277         phy_write(phydev, 0x1e, 0x0020);
2278         phy_set_bits(phydev, 0x15, BIT(8));
2279
2280         phy_write(phydev, 0x1f, 0x0005);
2281         phy_write(phydev, 0x05, 0x8b85);
2282         phy_set_bits(phydev, 0x06, BIT(13));
2283
2284         phy_write(phydev, 0x1f, 0x0000);
2285 }
2286
2287 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2288 {
2289         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2290 }
2291
2292 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2293 {
2294         struct phy_device *phydev = tp->phydev;
2295
2296         rtl8168g_config_eee_phy(tp);
2297
2298         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2299         phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2300 }
2301
2302 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2303 {
2304         static const struct phy_reg phy_reg_init[] = {
2305                 { 0x1f, 0x0001 },
2306                 { 0x06, 0x006e },
2307                 { 0x08, 0x0708 },
2308                 { 0x15, 0x4000 },
2309                 { 0x18, 0x65c7 },
2310
2311                 { 0x1f, 0x0001 },
2312                 { 0x03, 0x00a1 },
2313                 { 0x02, 0x0008 },
2314                 { 0x01, 0x0120 },
2315                 { 0x00, 0x1000 },
2316                 { 0x04, 0x0800 },
2317                 { 0x04, 0x0000 },
2318
2319                 { 0x03, 0xff41 },
2320                 { 0x02, 0xdf60 },
2321                 { 0x01, 0x0140 },
2322                 { 0x00, 0x0077 },
2323                 { 0x04, 0x7800 },
2324                 { 0x04, 0x7000 },
2325
2326                 { 0x03, 0x802f },
2327                 { 0x02, 0x4f02 },
2328                 { 0x01, 0x0409 },
2329                 { 0x00, 0xf0f9 },
2330                 { 0x04, 0x9800 },
2331                 { 0x04, 0x9000 },
2332
2333                 { 0x03, 0xdf01 },
2334                 { 0x02, 0xdf20 },
2335                 { 0x01, 0xff95 },
2336                 { 0x00, 0xba00 },
2337                 { 0x04, 0xa800 },
2338                 { 0x04, 0xa000 },
2339
2340                 { 0x03, 0xff41 },
2341                 { 0x02, 0xdf20 },
2342                 { 0x01, 0x0140 },
2343                 { 0x00, 0x00bb },
2344                 { 0x04, 0xb800 },
2345                 { 0x04, 0xb000 },
2346
2347                 { 0x03, 0xdf41 },
2348                 { 0x02, 0xdc60 },
2349                 { 0x01, 0x6340 },
2350                 { 0x00, 0x007d },
2351                 { 0x04, 0xd800 },
2352                 { 0x04, 0xd000 },
2353
2354                 { 0x03, 0xdf01 },
2355                 { 0x02, 0xdf20 },
2356                 { 0x01, 0x100a },
2357                 { 0x00, 0xa0ff },
2358                 { 0x04, 0xf800 },
2359                 { 0x04, 0xf000 },
2360
2361                 { 0x1f, 0x0000 },
2362                 { 0x0b, 0x0000 },
2363                 { 0x00, 0x9200 }
2364         };
2365
2366         rtl_writephy_batch(tp, phy_reg_init);
2367 }
2368
2369 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2370 {
2371         static const struct phy_reg phy_reg_init[] = {
2372                 { 0x1f, 0x0002 },
2373                 { 0x01, 0x90d0 },
2374                 { 0x1f, 0x0000 }
2375         };
2376
2377         rtl_writephy_batch(tp, phy_reg_init);
2378 }
2379
2380 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2381 {
2382         struct pci_dev *pdev = tp->pci_dev;
2383
2384         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2385             (pdev->subsystem_device != 0xe000))
2386                 return;
2387
2388         rtl_writephy(tp, 0x1f, 0x0001);
2389         rtl_writephy(tp, 0x10, 0xf01b);
2390         rtl_writephy(tp, 0x1f, 0x0000);
2391 }
2392
2393 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2394 {
2395         static const struct phy_reg phy_reg_init[] = {
2396                 { 0x1f, 0x0001 },
2397                 { 0x04, 0x0000 },
2398                 { 0x03, 0x00a1 },
2399                 { 0x02, 0x0008 },
2400                 { 0x01, 0x0120 },
2401                 { 0x00, 0x1000 },
2402                 { 0x04, 0x0800 },
2403                 { 0x04, 0x9000 },
2404                 { 0x03, 0x802f },
2405                 { 0x02, 0x4f02 },
2406                 { 0x01, 0x0409 },
2407                 { 0x00, 0xf099 },
2408                 { 0x04, 0x9800 },
2409                 { 0x04, 0xa000 },
2410                 { 0x03, 0xdf01 },
2411                 { 0x02, 0xdf20 },
2412                 { 0x01, 0xff95 },
2413                 { 0x00, 0xba00 },
2414                 { 0x04, 0xa800 },
2415                 { 0x04, 0xf000 },
2416                 { 0x03, 0xdf01 },
2417                 { 0x02, 0xdf20 },
2418                 { 0x01, 0x101a },
2419                 { 0x00, 0xa0ff },
2420                 { 0x04, 0xf800 },
2421                 { 0x04, 0x0000 },
2422                 { 0x1f, 0x0000 },
2423
2424                 { 0x1f, 0x0001 },
2425                 { 0x10, 0xf41b },
2426                 { 0x14, 0xfb54 },
2427                 { 0x18, 0xf5c7 },
2428                 { 0x1f, 0x0000 },
2429
2430                 { 0x1f, 0x0001 },
2431                 { 0x17, 0x0cc0 },
2432                 { 0x1f, 0x0000 }
2433         };
2434
2435         rtl_writephy_batch(tp, phy_reg_init);
2436
2437         rtl8169scd_hw_phy_config_quirk(tp);
2438 }
2439
2440 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2441 {
2442         static const struct phy_reg phy_reg_init[] = {
2443                 { 0x1f, 0x0001 },
2444                 { 0x04, 0x0000 },
2445                 { 0x03, 0x00a1 },
2446                 { 0x02, 0x0008 },
2447                 { 0x01, 0x0120 },
2448                 { 0x00, 0x1000 },
2449                 { 0x04, 0x0800 },
2450                 { 0x04, 0x9000 },
2451                 { 0x03, 0x802f },
2452                 { 0x02, 0x4f02 },
2453                 { 0x01, 0x0409 },
2454                 { 0x00, 0xf099 },
2455                 { 0x04, 0x9800 },
2456                 { 0x04, 0xa000 },
2457                 { 0x03, 0xdf01 },
2458                 { 0x02, 0xdf20 },
2459                 { 0x01, 0xff95 },
2460                 { 0x00, 0xba00 },
2461                 { 0x04, 0xa800 },
2462                 { 0x04, 0xf000 },
2463                 { 0x03, 0xdf01 },
2464                 { 0x02, 0xdf20 },
2465                 { 0x01, 0x101a },
2466                 { 0x00, 0xa0ff },
2467                 { 0x04, 0xf800 },
2468                 { 0x04, 0x0000 },
2469                 { 0x1f, 0x0000 },
2470
2471                 { 0x1f, 0x0001 },
2472                 { 0x0b, 0x8480 },
2473                 { 0x1f, 0x0000 },
2474
2475                 { 0x1f, 0x0001 },
2476                 { 0x18, 0x67c7 },
2477                 { 0x04, 0x2000 },
2478                 { 0x03, 0x002f },
2479                 { 0x02, 0x4360 },
2480                 { 0x01, 0x0109 },
2481                 { 0x00, 0x3022 },
2482                 { 0x04, 0x2800 },
2483                 { 0x1f, 0x0000 },
2484
2485                 { 0x1f, 0x0001 },
2486                 { 0x17, 0x0cc0 },
2487                 { 0x1f, 0x0000 }
2488         };
2489
2490         rtl_writephy_batch(tp, phy_reg_init);
2491 }
2492
2493 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2494 {
2495         static const struct phy_reg phy_reg_init[] = {
2496                 { 0x10, 0xf41b },
2497                 { 0x1f, 0x0000 }
2498         };
2499
2500         rtl_writephy(tp, 0x1f, 0x0001);
2501         rtl_patchphy(tp, 0x16, 1 << 0);
2502
2503         rtl_writephy_batch(tp, phy_reg_init);
2504 }
2505
2506 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2507 {
2508         static const struct phy_reg phy_reg_init[] = {
2509                 { 0x1f, 0x0001 },
2510                 { 0x10, 0xf41b },
2511                 { 0x1f, 0x0000 }
2512         };
2513
2514         rtl_writephy_batch(tp, phy_reg_init);
2515 }
2516
2517 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2518 {
2519         static const struct phy_reg phy_reg_init[] = {
2520                 { 0x1f, 0x0000 },
2521                 { 0x1d, 0x0f00 },
2522                 { 0x1f, 0x0002 },
2523                 { 0x0c, 0x1ec8 },
2524                 { 0x1f, 0x0000 }
2525         };
2526
2527         rtl_writephy_batch(tp, phy_reg_init);
2528 }
2529
2530 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2531 {
2532         static const struct phy_reg phy_reg_init[] = {
2533                 { 0x1f, 0x0001 },
2534                 { 0x1d, 0x3d98 },
2535                 { 0x1f, 0x0000 }
2536         };
2537
2538         rtl_writephy(tp, 0x1f, 0x0000);
2539         rtl_patchphy(tp, 0x14, 1 << 5);
2540         rtl_patchphy(tp, 0x0d, 1 << 5);
2541
2542         rtl_writephy_batch(tp, phy_reg_init);
2543 }
2544
2545 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2546 {
2547         static const struct phy_reg phy_reg_init[] = {
2548                 { 0x1f, 0x0001 },
2549                 { 0x12, 0x2300 },
2550                 { 0x1f, 0x0002 },
2551                 { 0x00, 0x88d4 },
2552                 { 0x01, 0x82b1 },
2553                 { 0x03, 0x7002 },
2554                 { 0x08, 0x9e30 },
2555                 { 0x09, 0x01f0 },
2556                 { 0x0a, 0x5500 },
2557                 { 0x0c, 0x00c8 },
2558                 { 0x1f, 0x0003 },
2559                 { 0x12, 0xc096 },
2560                 { 0x16, 0x000a },
2561                 { 0x1f, 0x0000 },
2562                 { 0x1f, 0x0000 },
2563                 { 0x09, 0x2000 },
2564                 { 0x09, 0x0000 }
2565         };
2566
2567         rtl_writephy_batch(tp, phy_reg_init);
2568
2569         rtl_patchphy(tp, 0x14, 1 << 5);
2570         rtl_patchphy(tp, 0x0d, 1 << 5);
2571         rtl_writephy(tp, 0x1f, 0x0000);
2572 }
2573
2574 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2575 {
2576         static const struct phy_reg phy_reg_init[] = {
2577                 { 0x1f, 0x0001 },
2578                 { 0x12, 0x2300 },
2579                 { 0x03, 0x802f },
2580                 { 0x02, 0x4f02 },
2581                 { 0x01, 0x0409 },
2582                 { 0x00, 0xf099 },
2583                 { 0x04, 0x9800 },
2584                 { 0x04, 0x9000 },
2585                 { 0x1d, 0x3d98 },
2586                 { 0x1f, 0x0002 },
2587                 { 0x0c, 0x7eb8 },
2588                 { 0x06, 0x0761 },
2589                 { 0x1f, 0x0003 },
2590                 { 0x16, 0x0f0a },
2591                 { 0x1f, 0x0000 }
2592         };
2593
2594         rtl_writephy_batch(tp, phy_reg_init);
2595
2596         rtl_patchphy(tp, 0x16, 1 << 0);
2597         rtl_patchphy(tp, 0x14, 1 << 5);
2598         rtl_patchphy(tp, 0x0d, 1 << 5);
2599         rtl_writephy(tp, 0x1f, 0x0000);
2600 }
2601
2602 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2603 {
2604         static const struct phy_reg phy_reg_init[] = {
2605                 { 0x1f, 0x0001 },
2606                 { 0x12, 0x2300 },
2607                 { 0x1d, 0x3d98 },
2608                 { 0x1f, 0x0002 },
2609                 { 0x0c, 0x7eb8 },
2610                 { 0x06, 0x5461 },
2611                 { 0x1f, 0x0003 },
2612                 { 0x16, 0x0f0a },
2613                 { 0x1f, 0x0000 }
2614         };
2615
2616         rtl_writephy_batch(tp, phy_reg_init);
2617
2618         rtl_patchphy(tp, 0x16, 1 << 0);
2619         rtl_patchphy(tp, 0x14, 1 << 5);
2620         rtl_patchphy(tp, 0x0d, 1 << 5);
2621         rtl_writephy(tp, 0x1f, 0x0000);
2622 }
2623
2624 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2625 {
2626         rtl8168c_3_hw_phy_config(tp);
2627 }
2628
2629 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2630         /* Channel Estimation */
2631         { 0x1f, 0x0001 },
2632         { 0x06, 0x4064 },
2633         { 0x07, 0x2863 },
2634         { 0x08, 0x059c },
2635         { 0x09, 0x26b4 },
2636         { 0x0a, 0x6a19 },
2637         { 0x0b, 0xdcc8 },
2638         { 0x10, 0xf06d },
2639         { 0x14, 0x7f68 },
2640         { 0x18, 0x7fd9 },
2641         { 0x1c, 0xf0ff },
2642         { 0x1d, 0x3d9c },
2643         { 0x1f, 0x0003 },
2644         { 0x12, 0xf49f },
2645         { 0x13, 0x070b },
2646         { 0x1a, 0x05ad },
2647         { 0x14, 0x94c0 },
2648
2649         /*
2650          * Tx Error Issue
2651          * Enhance line driver power
2652          */
2653         { 0x1f, 0x0002 },
2654         { 0x06, 0x5561 },
2655         { 0x1f, 0x0005 },
2656         { 0x05, 0x8332 },
2657         { 0x06, 0x5561 },
2658
2659         /*
2660          * Can not link to 1Gbps with bad cable
2661          * Decrease SNR threshold form 21.07dB to 19.04dB
2662          */
2663         { 0x1f, 0x0001 },
2664         { 0x17, 0x0cc0 },
2665
2666         { 0x1f, 0x0000 },
2667         { 0x0d, 0xf880 }
2668 };
2669
2670 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2671         { 0x1f, 0x0002 },
2672         { 0x05, 0x669a },
2673         { 0x1f, 0x0005 },
2674         { 0x05, 0x8330 },
2675         { 0x06, 0x669a },
2676         { 0x1f, 0x0002 }
2677 };
2678
2679 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2680 {
2681         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2682
2683         /*
2684          * Rx Error Issue
2685          * Fine Tune Switching regulator parameter
2686          */
2687         rtl_writephy(tp, 0x1f, 0x0002);
2688         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2689         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2690
2691         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2692                 int val;
2693
2694                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2695
2696                 val = rtl_readphy(tp, 0x0d);
2697
2698                 if ((val & 0x00ff) != 0x006c) {
2699                         static const u32 set[] = {
2700                                 0x0065, 0x0066, 0x0067, 0x0068,
2701                                 0x0069, 0x006a, 0x006b, 0x006c
2702                         };
2703                         int i;
2704
2705                         rtl_writephy(tp, 0x1f, 0x0002);
2706
2707                         val &= 0xff00;
2708                         for (i = 0; i < ARRAY_SIZE(set); i++)
2709                                 rtl_writephy(tp, 0x0d, val | set[i]);
2710                 }
2711         } else {
2712                 static const struct phy_reg phy_reg_init[] = {
2713                         { 0x1f, 0x0002 },
2714                         { 0x05, 0x6662 },
2715                         { 0x1f, 0x0005 },
2716                         { 0x05, 0x8330 },
2717                         { 0x06, 0x6662 }
2718                 };
2719
2720                 rtl_writephy_batch(tp, phy_reg_init);
2721         }
2722
2723         /* RSET couple improve */
2724         rtl_writephy(tp, 0x1f, 0x0002);
2725         rtl_patchphy(tp, 0x0d, 0x0300);
2726         rtl_patchphy(tp, 0x0f, 0x0010);
2727
2728         /* Fine tune PLL performance */
2729         rtl_writephy(tp, 0x1f, 0x0002);
2730         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2731         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2732
2733         rtl_writephy(tp, 0x1f, 0x0005);
2734         rtl_writephy(tp, 0x05, 0x001b);
2735
2736         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2737
2738         rtl_writephy(tp, 0x1f, 0x0000);
2739 }
2740
2741 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2742 {
2743         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2744
2745         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2746                 int val;
2747
2748                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2749
2750                 val = rtl_readphy(tp, 0x0d);
2751                 if ((val & 0x00ff) != 0x006c) {
2752                         static const u32 set[] = {
2753                                 0x0065, 0x0066, 0x0067, 0x0068,
2754                                 0x0069, 0x006a, 0x006b, 0x006c
2755                         };
2756                         int i;
2757
2758                         rtl_writephy(tp, 0x1f, 0x0002);
2759
2760                         val &= 0xff00;
2761                         for (i = 0; i < ARRAY_SIZE(set); i++)
2762                                 rtl_writephy(tp, 0x0d, val | set[i]);
2763                 }
2764         } else {
2765                 static const struct phy_reg phy_reg_init[] = {
2766                         { 0x1f, 0x0002 },
2767                         { 0x05, 0x2642 },
2768                         { 0x1f, 0x0005 },
2769                         { 0x05, 0x8330 },
2770                         { 0x06, 0x2642 }
2771                 };
2772
2773                 rtl_writephy_batch(tp, phy_reg_init);
2774         }
2775
2776         /* Fine tune PLL performance */
2777         rtl_writephy(tp, 0x1f, 0x0002);
2778         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2779         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2780
2781         /* Switching regulator Slew rate */
2782         rtl_writephy(tp, 0x1f, 0x0002);
2783         rtl_patchphy(tp, 0x0f, 0x0017);
2784
2785         rtl_writephy(tp, 0x1f, 0x0005);
2786         rtl_writephy(tp, 0x05, 0x001b);
2787
2788         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2789
2790         rtl_writephy(tp, 0x1f, 0x0000);
2791 }
2792
2793 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2794 {
2795         static const struct phy_reg phy_reg_init[] = {
2796                 { 0x1f, 0x0002 },
2797                 { 0x10, 0x0008 },
2798                 { 0x0d, 0x006c },
2799
2800                 { 0x1f, 0x0000 },
2801                 { 0x0d, 0xf880 },
2802
2803                 { 0x1f, 0x0001 },
2804                 { 0x17, 0x0cc0 },
2805
2806                 { 0x1f, 0x0001 },
2807                 { 0x0b, 0xa4d8 },
2808                 { 0x09, 0x281c },
2809                 { 0x07, 0x2883 },
2810                 { 0x0a, 0x6b35 },
2811                 { 0x1d, 0x3da4 },
2812                 { 0x1c, 0xeffd },
2813                 { 0x14, 0x7f52 },
2814                 { 0x18, 0x7fc6 },
2815                 { 0x08, 0x0601 },
2816                 { 0x06, 0x4063 },
2817                 { 0x10, 0xf074 },
2818                 { 0x1f, 0x0003 },
2819                 { 0x13, 0x0789 },
2820                 { 0x12, 0xf4bd },
2821                 { 0x1a, 0x04fd },
2822                 { 0x14, 0x84b0 },
2823                 { 0x1f, 0x0000 },
2824                 { 0x00, 0x9200 },
2825
2826                 { 0x1f, 0x0005 },
2827                 { 0x01, 0x0340 },
2828                 { 0x1f, 0x0001 },
2829                 { 0x04, 0x4000 },
2830                 { 0x03, 0x1d21 },
2831                 { 0x02, 0x0c32 },
2832                 { 0x01, 0x0200 },
2833                 { 0x00, 0x5554 },
2834                 { 0x04, 0x4800 },
2835                 { 0x04, 0x4000 },
2836                 { 0x04, 0xf000 },
2837                 { 0x03, 0xdf01 },
2838                 { 0x02, 0xdf20 },
2839                 { 0x01, 0x101a },
2840                 { 0x00, 0xa0ff },
2841                 { 0x04, 0xf800 },
2842                 { 0x04, 0xf000 },
2843                 { 0x1f, 0x0000 },
2844
2845                 { 0x1f, 0x0007 },
2846                 { 0x1e, 0x0023 },
2847                 { 0x16, 0x0000 },
2848                 { 0x1f, 0x0000 }
2849         };
2850
2851         rtl_writephy_batch(tp, phy_reg_init);
2852 }
2853
2854 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2855 {
2856         static const struct phy_reg phy_reg_init[] = {
2857                 { 0x1f, 0x0001 },
2858                 { 0x17, 0x0cc0 },
2859
2860                 { 0x1f, 0x0007 },
2861                 { 0x1e, 0x002d },
2862                 { 0x18, 0x0040 },
2863                 { 0x1f, 0x0000 }
2864         };
2865
2866         rtl_writephy_batch(tp, phy_reg_init);
2867         rtl_patchphy(tp, 0x0d, 1 << 5);
2868 }
2869
2870 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2871 {
2872         static const struct phy_reg phy_reg_init[] = {
2873                 /* Enable Delay cap */
2874                 { 0x1f, 0x0005 },
2875                 { 0x05, 0x8b80 },
2876                 { 0x06, 0xc896 },
2877                 { 0x1f, 0x0000 },
2878
2879                 /* Channel estimation fine tune */
2880                 { 0x1f, 0x0001 },
2881                 { 0x0b, 0x6c20 },
2882                 { 0x07, 0x2872 },
2883                 { 0x1c, 0xefff },
2884                 { 0x1f, 0x0003 },
2885                 { 0x14, 0x6420 },
2886                 { 0x1f, 0x0000 },
2887
2888                 /* Update PFM & 10M TX idle timer */
2889                 { 0x1f, 0x0007 },
2890                 { 0x1e, 0x002f },
2891                 { 0x15, 0x1919 },
2892                 { 0x1f, 0x0000 },
2893
2894                 { 0x1f, 0x0007 },
2895                 { 0x1e, 0x00ac },
2896                 { 0x18, 0x0006 },
2897                 { 0x1f, 0x0000 }
2898         };
2899
2900         rtl_apply_firmware(tp);
2901
2902         rtl_writephy_batch(tp, phy_reg_init);
2903
2904         /* DCO enable for 10M IDLE Power */
2905         rtl_writephy(tp, 0x1f, 0x0007);
2906         rtl_writephy(tp, 0x1e, 0x0023);
2907         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2908         rtl_writephy(tp, 0x1f, 0x0000);
2909
2910         /* For impedance matching */
2911         rtl_writephy(tp, 0x1f, 0x0002);
2912         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2913         rtl_writephy(tp, 0x1f, 0x0000);
2914
2915         /* PHY auto speed down */
2916         rtl_writephy(tp, 0x1f, 0x0007);
2917         rtl_writephy(tp, 0x1e, 0x002d);
2918         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2919         rtl_writephy(tp, 0x1f, 0x0000);
2920         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2921
2922         rtl_writephy(tp, 0x1f, 0x0005);
2923         rtl_writephy(tp, 0x05, 0x8b86);
2924         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2925         rtl_writephy(tp, 0x1f, 0x0000);
2926
2927         rtl_writephy(tp, 0x1f, 0x0005);
2928         rtl_writephy(tp, 0x05, 0x8b85);
2929         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2930         rtl_writephy(tp, 0x1f, 0x0007);
2931         rtl_writephy(tp, 0x1e, 0x0020);
2932         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2933         rtl_writephy(tp, 0x1f, 0x0006);
2934         rtl_writephy(tp, 0x00, 0x5a00);
2935         rtl_writephy(tp, 0x1f, 0x0000);
2936         rtl_writephy(tp, 0x0d, 0x0007);
2937         rtl_writephy(tp, 0x0e, 0x003c);
2938         rtl_writephy(tp, 0x0d, 0x4007);
2939         rtl_writephy(tp, 0x0e, 0x0000);
2940         rtl_writephy(tp, 0x0d, 0x0000);
2941 }
2942
2943 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2944 {
2945         const u16 w[] = {
2946                 addr[0] | (addr[1] << 8),
2947                 addr[2] | (addr[3] << 8),
2948                 addr[4] | (addr[5] << 8)
2949         };
2950
2951         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2952         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2953         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2954         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2955 }
2956
2957 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2958 {
2959         static const struct phy_reg phy_reg_init[] = {
2960                 /* Enable Delay cap */
2961                 { 0x1f, 0x0004 },
2962                 { 0x1f, 0x0007 },
2963                 { 0x1e, 0x00ac },
2964                 { 0x18, 0x0006 },
2965                 { 0x1f, 0x0002 },
2966                 { 0x1f, 0x0000 },
2967                 { 0x1f, 0x0000 },
2968
2969                 /* Channel estimation fine tune */
2970                 { 0x1f, 0x0003 },
2971                 { 0x09, 0xa20f },
2972                 { 0x1f, 0x0000 },
2973                 { 0x1f, 0x0000 },
2974
2975                 /* Green Setting */
2976                 { 0x1f, 0x0005 },
2977                 { 0x05, 0x8b5b },
2978                 { 0x06, 0x9222 },
2979                 { 0x05, 0x8b6d },
2980                 { 0x06, 0x8000 },
2981                 { 0x05, 0x8b76 },
2982                 { 0x06, 0x8000 },
2983                 { 0x1f, 0x0000 }
2984         };
2985
2986         rtl_apply_firmware(tp);
2987
2988         rtl_writephy_batch(tp, phy_reg_init);
2989
2990         /* For 4-corner performance improve */
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x8b80);
2993         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2994         rtl_writephy(tp, 0x1f, 0x0000);
2995
2996         /* PHY auto speed down */
2997         rtl_writephy(tp, 0x1f, 0x0004);
2998         rtl_writephy(tp, 0x1f, 0x0007);
2999         rtl_writephy(tp, 0x1e, 0x002d);
3000         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3001         rtl_writephy(tp, 0x1f, 0x0002);
3002         rtl_writephy(tp, 0x1f, 0x0000);
3003         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3004
3005         /* improve 10M EEE waveform */
3006         rtl_writephy(tp, 0x1f, 0x0005);
3007         rtl_writephy(tp, 0x05, 0x8b86);
3008         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3009         rtl_writephy(tp, 0x1f, 0x0000);
3010
3011         /* Improve 2-pair detection performance */
3012         rtl_writephy(tp, 0x1f, 0x0005);
3013         rtl_writephy(tp, 0x05, 0x8b85);
3014         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3015         rtl_writephy(tp, 0x1f, 0x0000);
3016
3017         rtl8168f_config_eee_phy(tp);
3018         rtl_enable_eee(tp);
3019
3020         /* Green feature */
3021         rtl_writephy(tp, 0x1f, 0x0003);
3022         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3023         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3024         rtl_writephy(tp, 0x1f, 0x0000);
3025         rtl_writephy(tp, 0x1f, 0x0005);
3026         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3027         rtl_writephy(tp, 0x1f, 0x0000);
3028
3029         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3030         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3031 }
3032
3033 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3034 {
3035         /* For 4-corner performance improve */
3036         rtl_writephy(tp, 0x1f, 0x0005);
3037         rtl_writephy(tp, 0x05, 0x8b80);
3038         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3039         rtl_writephy(tp, 0x1f, 0x0000);
3040
3041         /* PHY auto speed down */
3042         rtl_writephy(tp, 0x1f, 0x0007);
3043         rtl_writephy(tp, 0x1e, 0x002d);
3044         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3045         rtl_writephy(tp, 0x1f, 0x0000);
3046         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3047
3048         /* Improve 10M EEE waveform */
3049         rtl_writephy(tp, 0x1f, 0x0005);
3050         rtl_writephy(tp, 0x05, 0x8b86);
3051         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3052         rtl_writephy(tp, 0x1f, 0x0000);
3053
3054         rtl8168f_config_eee_phy(tp);
3055         rtl_enable_eee(tp);
3056 }
3057
3058 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3059 {
3060         static const struct phy_reg phy_reg_init[] = {
3061                 /* Channel estimation fine tune */
3062                 { 0x1f, 0x0003 },
3063                 { 0x09, 0xa20f },
3064                 { 0x1f, 0x0000 },
3065
3066                 /* Modify green table for giga & fnet */
3067                 { 0x1f, 0x0005 },
3068                 { 0x05, 0x8b55 },
3069                 { 0x06, 0x0000 },
3070                 { 0x05, 0x8b5e },
3071                 { 0x06, 0x0000 },
3072                 { 0x05, 0x8b67 },
3073                 { 0x06, 0x0000 },
3074                 { 0x05, 0x8b70 },
3075                 { 0x06, 0x0000 },
3076                 { 0x1f, 0x0000 },
3077                 { 0x1f, 0x0007 },
3078                 { 0x1e, 0x0078 },
3079                 { 0x17, 0x0000 },
3080                 { 0x19, 0x00fb },
3081                 { 0x1f, 0x0000 },
3082
3083                 /* Modify green table for 10M */
3084                 { 0x1f, 0x0005 },
3085                 { 0x05, 0x8b79 },
3086                 { 0x06, 0xaa00 },
3087                 { 0x1f, 0x0000 },
3088
3089                 /* Disable hiimpedance detection (RTCT) */
3090                 { 0x1f, 0x0003 },
3091                 { 0x01, 0x328a },
3092                 { 0x1f, 0x0000 }
3093         };
3094
3095         rtl_apply_firmware(tp);
3096
3097         rtl_writephy_batch(tp, phy_reg_init);
3098
3099         rtl8168f_hw_phy_config(tp);
3100
3101         /* Improve 2-pair detection performance */
3102         rtl_writephy(tp, 0x1f, 0x0005);
3103         rtl_writephy(tp, 0x05, 0x8b85);
3104         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106 }
3107
3108 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3109 {
3110         rtl_apply_firmware(tp);
3111
3112         rtl8168f_hw_phy_config(tp);
3113 }
3114
3115 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3116 {
3117         static const struct phy_reg phy_reg_init[] = {
3118                 /* Channel estimation fine tune */
3119                 { 0x1f, 0x0003 },
3120                 { 0x09, 0xa20f },
3121                 { 0x1f, 0x0000 },
3122
3123                 /* Modify green table for giga & fnet */
3124                 { 0x1f, 0x0005 },
3125                 { 0x05, 0x8b55 },
3126                 { 0x06, 0x0000 },
3127                 { 0x05, 0x8b5e },
3128                 { 0x06, 0x0000 },
3129                 { 0x05, 0x8b67 },
3130                 { 0x06, 0x0000 },
3131                 { 0x05, 0x8b70 },
3132                 { 0x06, 0x0000 },
3133                 { 0x1f, 0x0000 },
3134                 { 0x1f, 0x0007 },
3135                 { 0x1e, 0x0078 },
3136                 { 0x17, 0x0000 },
3137                 { 0x19, 0x00aa },
3138                 { 0x1f, 0x0000 },
3139
3140                 /* Modify green table for 10M */
3141                 { 0x1f, 0x0005 },
3142                 { 0x05, 0x8b79 },
3143                 { 0x06, 0xaa00 },
3144                 { 0x1f, 0x0000 },
3145
3146                 /* Disable hiimpedance detection (RTCT) */
3147                 { 0x1f, 0x0003 },
3148                 { 0x01, 0x328a },
3149                 { 0x1f, 0x0000 }
3150         };
3151
3152
3153         rtl_apply_firmware(tp);
3154
3155         rtl8168f_hw_phy_config(tp);
3156
3157         /* Improve 2-pair detection performance */
3158         rtl_writephy(tp, 0x1f, 0x0005);
3159         rtl_writephy(tp, 0x05, 0x8b85);
3160         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3161         rtl_writephy(tp, 0x1f, 0x0000);
3162
3163         rtl_writephy_batch(tp, phy_reg_init);
3164
3165         /* Modify green table for giga */
3166         rtl_writephy(tp, 0x1f, 0x0005);
3167         rtl_writephy(tp, 0x05, 0x8b54);
3168         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3169         rtl_writephy(tp, 0x05, 0x8b5d);
3170         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3171         rtl_writephy(tp, 0x05, 0x8a7c);
3172         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3173         rtl_writephy(tp, 0x05, 0x8a7f);
3174         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3175         rtl_writephy(tp, 0x05, 0x8a82);
3176         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3177         rtl_writephy(tp, 0x05, 0x8a85);
3178         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3179         rtl_writephy(tp, 0x05, 0x8a88);
3180         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3181         rtl_writephy(tp, 0x1f, 0x0000);
3182
3183         /* uc same-seed solution */
3184         rtl_writephy(tp, 0x1f, 0x0005);
3185         rtl_writephy(tp, 0x05, 0x8b85);
3186         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3187         rtl_writephy(tp, 0x1f, 0x0000);
3188
3189         /* Green feature */
3190         rtl_writephy(tp, 0x1f, 0x0003);
3191         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3192         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3193         rtl_writephy(tp, 0x1f, 0x0000);
3194 }
3195
3196 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3197 {
3198         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3199 }
3200
3201 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3202 {
3203         struct phy_device *phydev = tp->phydev;
3204
3205         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3206         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3207         phy_write(phydev, 0x1f, 0x0a43);
3208         phy_write(phydev, 0x13, 0x8084);
3209         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3210         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3211
3212         phy_write(phydev, 0x1f, 0x0000);
3213 }
3214
3215 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3216 {
3217         int ret;
3218
3219         rtl_apply_firmware(tp);
3220
3221         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3222         if (ret & BIT(8))
3223                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3224         else
3225                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3226
3227         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3228         if (ret & BIT(8))
3229                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3230         else
3231                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3232
3233         /* Enable PHY auto speed down */
3234         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3235
3236         rtl8168g_phy_adjust_10m_aldps(tp);
3237
3238         /* EEE auto-fallback function */
3239         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3240
3241         /* Enable UC LPF tune function */
3242         rtl_writephy(tp, 0x1f, 0x0a43);
3243         rtl_writephy(tp, 0x13, 0x8012);
3244         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3245
3246         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3247
3248         /* Improve SWR Efficiency */
3249         rtl_writephy(tp, 0x1f, 0x0bcd);
3250         rtl_writephy(tp, 0x14, 0x5065);
3251         rtl_writephy(tp, 0x14, 0xd065);
3252         rtl_writephy(tp, 0x1f, 0x0bc8);
3253         rtl_writephy(tp, 0x11, 0x5655);
3254         rtl_writephy(tp, 0x1f, 0x0bcd);
3255         rtl_writephy(tp, 0x14, 0x1065);
3256         rtl_writephy(tp, 0x14, 0x9065);
3257         rtl_writephy(tp, 0x14, 0x1065);
3258         rtl_writephy(tp, 0x1f, 0x0000);
3259
3260         rtl8168g_disable_aldps(tp);
3261         rtl8168g_config_eee_phy(tp);
3262         rtl_enable_eee(tp);
3263 }
3264
3265 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3266 {
3267         rtl_apply_firmware(tp);
3268         rtl8168g_config_eee_phy(tp);
3269         rtl_enable_eee(tp);
3270 }
3271
3272 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3273 {
3274         u16 dout_tapbin;
3275         u32 data;
3276
3277         rtl_apply_firmware(tp);
3278
3279         /* CHN EST parameters adjust - giga master */
3280         rtl_writephy(tp, 0x1f, 0x0a43);
3281         rtl_writephy(tp, 0x13, 0x809b);
3282         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3283         rtl_writephy(tp, 0x13, 0x80a2);
3284         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3285         rtl_writephy(tp, 0x13, 0x80a4);
3286         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3287         rtl_writephy(tp, 0x13, 0x809c);
3288         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3289         rtl_writephy(tp, 0x1f, 0x0000);
3290
3291         /* CHN EST parameters adjust - giga slave */
3292         rtl_writephy(tp, 0x1f, 0x0a43);
3293         rtl_writephy(tp, 0x13, 0x80ad);
3294         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3295         rtl_writephy(tp, 0x13, 0x80b4);
3296         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3297         rtl_writephy(tp, 0x13, 0x80ac);
3298         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3299         rtl_writephy(tp, 0x1f, 0x0000);
3300
3301         /* CHN EST parameters adjust - fnet */
3302         rtl_writephy(tp, 0x1f, 0x0a43);
3303         rtl_writephy(tp, 0x13, 0x808e);
3304         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3305         rtl_writephy(tp, 0x13, 0x8090);
3306         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3307         rtl_writephy(tp, 0x13, 0x8092);
3308         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3309         rtl_writephy(tp, 0x1f, 0x0000);
3310
3311         /* enable R-tune & PGA-retune function */
3312         dout_tapbin = 0;
3313         rtl_writephy(tp, 0x1f, 0x0a46);
3314         data = rtl_readphy(tp, 0x13);
3315         data &= 3;
3316         data <<= 2;
3317         dout_tapbin |= data;
3318         data = rtl_readphy(tp, 0x12);
3319         data &= 0xc000;
3320         data >>= 14;
3321         dout_tapbin |= data;
3322         dout_tapbin = ~(dout_tapbin^0x08);
3323         dout_tapbin <<= 12;
3324         dout_tapbin &= 0xf000;
3325         rtl_writephy(tp, 0x1f, 0x0a43);
3326         rtl_writephy(tp, 0x13, 0x827a);
3327         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3328         rtl_writephy(tp, 0x13, 0x827b);
3329         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3330         rtl_writephy(tp, 0x13, 0x827c);
3331         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3332         rtl_writephy(tp, 0x13, 0x827d);
3333         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3334
3335         rtl_writephy(tp, 0x1f, 0x0a43);
3336         rtl_writephy(tp, 0x13, 0x0811);
3337         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3338         rtl_writephy(tp, 0x1f, 0x0a42);
3339         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341
3342         /* enable GPHY 10M */
3343         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3344
3345         /* SAR ADC performance */
3346         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3347
3348         rtl_writephy(tp, 0x1f, 0x0a43);
3349         rtl_writephy(tp, 0x13, 0x803f);
3350         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3351         rtl_writephy(tp, 0x13, 0x8047);
3352         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3353         rtl_writephy(tp, 0x13, 0x804f);
3354         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3355         rtl_writephy(tp, 0x13, 0x8057);
3356         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3357         rtl_writephy(tp, 0x13, 0x805f);
3358         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3359         rtl_writephy(tp, 0x13, 0x8067);
3360         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3361         rtl_writephy(tp, 0x13, 0x806f);
3362         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3363         rtl_writephy(tp, 0x1f, 0x0000);
3364
3365         /* disable phy pfm mode */
3366         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3367
3368         rtl8168g_disable_aldps(tp);
3369         rtl8168h_config_eee_phy(tp);
3370         rtl_enable_eee(tp);
3371 }
3372
3373 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3374 {
3375         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3376         u16 rlen;
3377         u32 data;
3378
3379         rtl_apply_firmware(tp);
3380
3381         /* CHIN EST parameter update */
3382         rtl_writephy(tp, 0x1f, 0x0a43);
3383         rtl_writephy(tp, 0x13, 0x808a);
3384         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3385         rtl_writephy(tp, 0x1f, 0x0000);
3386
3387         /* enable R-tune & PGA-retune function */
3388         rtl_writephy(tp, 0x1f, 0x0a43);
3389         rtl_writephy(tp, 0x13, 0x0811);
3390         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3391         rtl_writephy(tp, 0x1f, 0x0a42);
3392         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3393         rtl_writephy(tp, 0x1f, 0x0000);
3394
3395         /* enable GPHY 10M */
3396         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3397
3398         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3399         data = r8168_mac_ocp_read(tp, 0xdd02);
3400         ioffset_p3 = ((data & 0x80)>>7);
3401         ioffset_p3 <<= 3;
3402
3403         data = r8168_mac_ocp_read(tp, 0xdd00);
3404         ioffset_p3 |= ((data & (0xe000))>>13);
3405         ioffset_p2 = ((data & (0x1e00))>>9);
3406         ioffset_p1 = ((data & (0x01e0))>>5);
3407         ioffset_p0 = ((data & 0x0010)>>4);
3408         ioffset_p0 <<= 3;
3409         ioffset_p0 |= (data & (0x07));
3410         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3411
3412         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3413             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3414                 rtl_writephy(tp, 0x1f, 0x0bcf);
3415                 rtl_writephy(tp, 0x16, data);
3416                 rtl_writephy(tp, 0x1f, 0x0000);
3417         }
3418
3419         /* Modify rlen (TX LPF corner frequency) level */
3420         rtl_writephy(tp, 0x1f, 0x0bcd);
3421         data = rtl_readphy(tp, 0x16);
3422         data &= 0x000f;
3423         rlen = 0;
3424         if (data > 3)
3425                 rlen = data - 3;
3426         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3427         rtl_writephy(tp, 0x17, data);
3428         rtl_writephy(tp, 0x1f, 0x0bcd);
3429         rtl_writephy(tp, 0x1f, 0x0000);
3430
3431         /* disable phy pfm mode */
3432         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3433
3434         rtl8168g_disable_aldps(tp);
3435         rtl8168g_config_eee_phy(tp);
3436         rtl_enable_eee(tp);
3437 }
3438
3439 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3440 {
3441         /* Enable PHY auto speed down */
3442         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3443
3444         rtl8168g_phy_adjust_10m_aldps(tp);
3445
3446         /* Enable EEE auto-fallback function */
3447         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3448
3449         /* Enable UC LPF tune function */
3450         rtl_writephy(tp, 0x1f, 0x0a43);
3451         rtl_writephy(tp, 0x13, 0x8012);
3452         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3453         rtl_writephy(tp, 0x1f, 0x0000);
3454
3455         /* set rg_sel_sdm_rate */
3456         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3457
3458         rtl8168g_disable_aldps(tp);
3459         rtl8168g_config_eee_phy(tp);
3460         rtl_enable_eee(tp);
3461 }
3462
3463 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3464 {
3465         rtl8168g_phy_adjust_10m_aldps(tp);
3466
3467         /* Enable UC LPF tune function */
3468         rtl_writephy(tp, 0x1f, 0x0a43);
3469         rtl_writephy(tp, 0x13, 0x8012);
3470         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3471         rtl_writephy(tp, 0x1f, 0x0000);
3472
3473         /* Set rg_sel_sdm_rate */
3474         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3475
3476         /* Channel estimation parameters */
3477         rtl_writephy(tp, 0x1f, 0x0a43);
3478         rtl_writephy(tp, 0x13, 0x80f3);
3479         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3480         rtl_writephy(tp, 0x13, 0x80f0);
3481         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3482         rtl_writephy(tp, 0x13, 0x80ef);
3483         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3484         rtl_writephy(tp, 0x13, 0x80f6);
3485         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3486         rtl_writephy(tp, 0x13, 0x80ec);
3487         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3488         rtl_writephy(tp, 0x13, 0x80ed);
3489         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3490         rtl_writephy(tp, 0x13, 0x80f2);
3491         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3492         rtl_writephy(tp, 0x13, 0x80f4);
3493         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3494         rtl_writephy(tp, 0x1f, 0x0a43);
3495         rtl_writephy(tp, 0x13, 0x8110);
3496         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3497         rtl_writephy(tp, 0x13, 0x810f);
3498         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3499         rtl_writephy(tp, 0x13, 0x8111);
3500         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3501         rtl_writephy(tp, 0x13, 0x8113);
3502         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3503         rtl_writephy(tp, 0x13, 0x8115);
3504         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3505         rtl_writephy(tp, 0x13, 0x810e);
3506         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3507         rtl_writephy(tp, 0x13, 0x810c);
3508         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3509         rtl_writephy(tp, 0x13, 0x810b);
3510         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3511         rtl_writephy(tp, 0x1f, 0x0a43);
3512         rtl_writephy(tp, 0x13, 0x80d1);
3513         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3514         rtl_writephy(tp, 0x13, 0x80cd);
3515         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3516         rtl_writephy(tp, 0x13, 0x80d3);
3517         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3518         rtl_writephy(tp, 0x13, 0x80d5);
3519         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3520         rtl_writephy(tp, 0x13, 0x80d7);
3521         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3522
3523         /* Force PWM-mode */
3524         rtl_writephy(tp, 0x1f, 0x0bcd);
3525         rtl_writephy(tp, 0x14, 0x5065);
3526         rtl_writephy(tp, 0x14, 0xd065);
3527         rtl_writephy(tp, 0x1f, 0x0bc8);
3528         rtl_writephy(tp, 0x12, 0x00ed);
3529         rtl_writephy(tp, 0x1f, 0x0bcd);
3530         rtl_writephy(tp, 0x14, 0x1065);
3531         rtl_writephy(tp, 0x14, 0x9065);
3532         rtl_writephy(tp, 0x14, 0x1065);
3533         rtl_writephy(tp, 0x1f, 0x0000);
3534
3535         rtl8168g_disable_aldps(tp);
3536         rtl8168g_config_eee_phy(tp);
3537         rtl_enable_eee(tp);
3538 }
3539
3540 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3541 {
3542         static const struct phy_reg phy_reg_init[] = {
3543                 { 0x1f, 0x0003 },
3544                 { 0x08, 0x441d },
3545                 { 0x01, 0x9100 },
3546                 { 0x1f, 0x0000 }
3547         };
3548
3549         rtl_writephy(tp, 0x1f, 0x0000);
3550         rtl_patchphy(tp, 0x11, 1 << 12);
3551         rtl_patchphy(tp, 0x19, 1 << 13);
3552         rtl_patchphy(tp, 0x10, 1 << 15);
3553
3554         rtl_writephy_batch(tp, phy_reg_init);
3555 }
3556
3557 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3558 {
3559         static const struct phy_reg phy_reg_init[] = {
3560                 { 0x1f, 0x0005 },
3561                 { 0x1a, 0x0000 },
3562                 { 0x1f, 0x0000 },
3563
3564                 { 0x1f, 0x0004 },
3565                 { 0x1c, 0x0000 },
3566                 { 0x1f, 0x0000 },
3567
3568                 { 0x1f, 0x0001 },
3569                 { 0x15, 0x7701 },
3570                 { 0x1f, 0x0000 }
3571         };
3572
3573         /* Disable ALDPS before ram code */
3574         rtl_writephy(tp, 0x1f, 0x0000);
3575         rtl_writephy(tp, 0x18, 0x0310);
3576         msleep(100);
3577
3578         rtl_apply_firmware(tp);
3579
3580         rtl_writephy_batch(tp, phy_reg_init);
3581 }
3582
3583 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3584 {
3585         /* Disable ALDPS before setting firmware */
3586         rtl_writephy(tp, 0x1f, 0x0000);
3587         rtl_writephy(tp, 0x18, 0x0310);
3588         msleep(20);
3589
3590         rtl_apply_firmware(tp);
3591
3592         /* EEE setting */
3593         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3594         rtl_writephy(tp, 0x1f, 0x0004);
3595         rtl_writephy(tp, 0x10, 0x401f);
3596         rtl_writephy(tp, 0x19, 0x7030);
3597         rtl_writephy(tp, 0x1f, 0x0000);
3598 }
3599
3600 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3601 {
3602         static const struct phy_reg phy_reg_init[] = {
3603                 { 0x1f, 0x0004 },
3604                 { 0x10, 0xc07f },
3605                 { 0x19, 0x7030 },
3606                 { 0x1f, 0x0000 }
3607         };
3608
3609         /* Disable ALDPS before ram code */
3610         rtl_writephy(tp, 0x1f, 0x0000);
3611         rtl_writephy(tp, 0x18, 0x0310);
3612         msleep(100);
3613
3614         rtl_apply_firmware(tp);
3615
3616         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3617         rtl_writephy_batch(tp, phy_reg_init);
3618
3619         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3620 }
3621
3622 static void rtl_hw_phy_config(struct net_device *dev)
3623 {
3624         static const rtl_generic_fct phy_configs[] = {
3625                 /* PCI devices. */
3626                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3627                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3628                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3629                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3630                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3631                 /* PCI-E devices. */
3632                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3633                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3634                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3635                 [RTL_GIGA_MAC_VER_10] = NULL,
3636                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3637                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3638                 [RTL_GIGA_MAC_VER_13] = NULL,
3639                 [RTL_GIGA_MAC_VER_14] = NULL,
3640                 [RTL_GIGA_MAC_VER_15] = NULL,
3641                 [RTL_GIGA_MAC_VER_16] = NULL,
3642                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3643                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3644                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3645                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3646                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3647                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3648                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3649                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3650                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3651                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3652                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3653                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3654                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3655                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3656                 [RTL_GIGA_MAC_VER_31] = NULL,
3657                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3658                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3659                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3660                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3661                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3662                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3663                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3664                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3665                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3666                 [RTL_GIGA_MAC_VER_41] = NULL,
3667                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3668                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3669                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3670                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3671                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3672                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3673                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3674                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3675                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3676                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3677                 [RTL_GIGA_MAC_VER_60] = NULL,
3678                 [RTL_GIGA_MAC_VER_61] = NULL,
3679         };
3680         struct rtl8169_private *tp = netdev_priv(dev);
3681
3682         if (phy_configs[tp->mac_version])
3683                 phy_configs[tp->mac_version](tp);
3684 }
3685
3686 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3687 {
3688         if (!test_and_set_bit(flag, tp->wk.flags))
3689                 schedule_work(&tp->wk.work);
3690 }
3691
3692 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3693 {
3694         rtl_hw_phy_config(dev);
3695
3696         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3697                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3698                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3699                 netif_dbg(tp, drv, dev,
3700                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3701                 RTL_W8(tp, 0x82, 0x01);
3702         }
3703
3704         /* We may have called phy_speed_down before */
3705         phy_speed_up(tp->phydev);
3706
3707         genphy_soft_reset(tp->phydev);
3708 }
3709
3710 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3711 {
3712         rtl_lock_work(tp);
3713
3714         rtl_unlock_config_regs(tp);
3715
3716         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3717         RTL_R32(tp, MAC4);
3718
3719         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3720         RTL_R32(tp, MAC0);
3721
3722         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3723                 rtl_rar_exgmac_set(tp, addr);
3724
3725         rtl_lock_config_regs(tp);
3726
3727         rtl_unlock_work(tp);
3728 }
3729
3730 static int rtl_set_mac_address(struct net_device *dev, void *p)
3731 {
3732         struct rtl8169_private *tp = netdev_priv(dev);
3733         struct device *d = tp_to_dev(tp);
3734         int ret;
3735
3736         ret = eth_mac_addr(dev, p);
3737         if (ret)
3738                 return ret;
3739
3740         pm_runtime_get_noresume(d);
3741
3742         if (pm_runtime_active(d))
3743                 rtl_rar_set(tp, dev->dev_addr);
3744
3745         pm_runtime_put_noidle(d);
3746
3747         return 0;
3748 }
3749
3750 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3751 {
3752         struct rtl8169_private *tp = netdev_priv(dev);
3753
3754         if (!netif_running(dev))
3755                 return -ENODEV;
3756
3757         return phy_mii_ioctl(tp->phydev, ifr, cmd);
3758 }
3759
3760 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3761 {
3762         switch (tp->mac_version) {
3763         case RTL_GIGA_MAC_VER_25:
3764         case RTL_GIGA_MAC_VER_26:
3765         case RTL_GIGA_MAC_VER_29:
3766         case RTL_GIGA_MAC_VER_30:
3767         case RTL_GIGA_MAC_VER_32:
3768         case RTL_GIGA_MAC_VER_33:
3769         case RTL_GIGA_MAC_VER_34:
3770         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3771                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3772                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3773                 break;
3774         default:
3775                 break;
3776         }
3777 }
3778
3779 static void rtl_pll_power_down(struct rtl8169_private *tp)
3780 {
3781         if (r8168_check_dash(tp))
3782                 return;
3783
3784         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3785             tp->mac_version == RTL_GIGA_MAC_VER_33)
3786                 rtl_ephy_write(tp, 0x19, 0xff64);
3787
3788         if (device_may_wakeup(tp_to_dev(tp))) {
3789                 phy_speed_down(tp->phydev, false);
3790                 rtl_wol_suspend_quirk(tp);
3791                 return;
3792         }
3793
3794         switch (tp->mac_version) {
3795         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3796         case RTL_GIGA_MAC_VER_37:
3797         case RTL_GIGA_MAC_VER_39:
3798         case RTL_GIGA_MAC_VER_43:
3799         case RTL_GIGA_MAC_VER_44:
3800         case RTL_GIGA_MAC_VER_45:
3801         case RTL_GIGA_MAC_VER_46:
3802         case RTL_GIGA_MAC_VER_47:
3803         case RTL_GIGA_MAC_VER_48:
3804         case RTL_GIGA_MAC_VER_50:
3805         case RTL_GIGA_MAC_VER_51:
3806         case RTL_GIGA_MAC_VER_60:
3807         case RTL_GIGA_MAC_VER_61:
3808                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3809                 break;
3810         case RTL_GIGA_MAC_VER_40:
3811         case RTL_GIGA_MAC_VER_41:
3812         case RTL_GIGA_MAC_VER_49:
3813                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3814                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3815                 break;
3816         default:
3817                 break;
3818         }
3819 }
3820
3821 static void rtl_pll_power_up(struct rtl8169_private *tp)
3822 {
3823         switch (tp->mac_version) {
3824         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3825         case RTL_GIGA_MAC_VER_37:
3826         case RTL_GIGA_MAC_VER_39:
3827         case RTL_GIGA_MAC_VER_43:
3828                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3829                 break;
3830         case RTL_GIGA_MAC_VER_44:
3831         case RTL_GIGA_MAC_VER_45:
3832         case RTL_GIGA_MAC_VER_46:
3833         case RTL_GIGA_MAC_VER_47:
3834         case RTL_GIGA_MAC_VER_48:
3835         case RTL_GIGA_MAC_VER_50:
3836         case RTL_GIGA_MAC_VER_51:
3837         case RTL_GIGA_MAC_VER_60:
3838         case RTL_GIGA_MAC_VER_61:
3839                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3840                 break;
3841         case RTL_GIGA_MAC_VER_40:
3842         case RTL_GIGA_MAC_VER_41:
3843         case RTL_GIGA_MAC_VER_49:
3844                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3845                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3846                 break;
3847         default:
3848                 break;
3849         }
3850
3851         phy_resume(tp->phydev);
3852         /* give MAC/PHY some time to resume */
3853         msleep(20);
3854 }
3855
3856 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3857 {
3858         switch (tp->mac_version) {
3859         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3860         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3861                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3862                 break;
3863         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3864         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3865         case RTL_GIGA_MAC_VER_38:
3866                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3867                 break;
3868         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
3869                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3870                 break;
3871         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
3872                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
3873                                       RX_DMA_BURST);
3874                 break;
3875         default:
3876                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3877                 break;
3878         }
3879 }
3880
3881 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3882 {
3883         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3884 }
3885
3886 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3887 {
3888         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3889         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3890         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3891 }
3892
3893 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3894 {
3895         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3896         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3897         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3898 }
3899
3900 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3901 {
3902         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3903 }
3904
3905 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3906 {
3907         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3908 }
3909
3910 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3911 {
3912         RTL_W8(tp, MaxTxPacketSize, 0x3f);
3913         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3914         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3915         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
3916 }
3917
3918 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3919 {
3920         RTL_W8(tp, MaxTxPacketSize, 0x0c);
3921         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3922         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3923         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
3924 }
3925
3926 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3927 {
3928         rtl_tx_performance_tweak(tp,
3929                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3930 }
3931
3932 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3933 {
3934         rtl_tx_performance_tweak(tp,
3935                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
3936 }
3937
3938 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3939 {
3940         r8168b_0_hw_jumbo_enable(tp);
3941
3942         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3943 }
3944
3945 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3946 {
3947         r8168b_0_hw_jumbo_disable(tp);
3948
3949         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3950 }
3951
3952 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3953 {
3954         rtl_unlock_config_regs(tp);
3955         switch (tp->mac_version) {
3956         case RTL_GIGA_MAC_VER_11:
3957                 r8168b_0_hw_jumbo_enable(tp);
3958                 break;
3959         case RTL_GIGA_MAC_VER_12:
3960         case RTL_GIGA_MAC_VER_17:
3961                 r8168b_1_hw_jumbo_enable(tp);
3962                 break;
3963         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3964                 r8168c_hw_jumbo_enable(tp);
3965                 break;
3966         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3967                 r8168dp_hw_jumbo_enable(tp);
3968                 break;
3969         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3970                 r8168e_hw_jumbo_enable(tp);
3971                 break;
3972         default:
3973                 break;
3974         }
3975         rtl_lock_config_regs(tp);
3976 }
3977
3978 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3979 {
3980         rtl_unlock_config_regs(tp);
3981         switch (tp->mac_version) {
3982         case RTL_GIGA_MAC_VER_11:
3983                 r8168b_0_hw_jumbo_disable(tp);
3984                 break;
3985         case RTL_GIGA_MAC_VER_12:
3986         case RTL_GIGA_MAC_VER_17:
3987                 r8168b_1_hw_jumbo_disable(tp);
3988                 break;
3989         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3990                 r8168c_hw_jumbo_disable(tp);
3991                 break;
3992         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3993                 r8168dp_hw_jumbo_disable(tp);
3994                 break;
3995         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3996                 r8168e_hw_jumbo_disable(tp);
3997                 break;
3998         default:
3999                 break;
4000         }
4001         rtl_lock_config_regs(tp);
4002 }
4003
4004 DECLARE_RTL_COND(rtl_chipcmd_cond)
4005 {
4006         return RTL_R8(tp, ChipCmd) & CmdReset;
4007 }
4008
4009 static void rtl_hw_reset(struct rtl8169_private *tp)
4010 {
4011         RTL_W8(tp, ChipCmd, CmdReset);
4012
4013         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4014 }
4015
4016 static void rtl_request_firmware(struct rtl8169_private *tp)
4017 {
4018         struct rtl_fw *rtl_fw;
4019
4020         /* firmware loaded already or no firmware available */
4021         if (tp->rtl_fw || !tp->fw_name)
4022                 return;
4023
4024         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4025         if (!rtl_fw) {
4026                 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4027                 return;
4028         }
4029
4030         rtl_fw->phy_write = rtl_writephy;
4031         rtl_fw->phy_read = rtl_readphy;
4032         rtl_fw->mac_mcu_write = mac_mcu_write;
4033         rtl_fw->mac_mcu_read = mac_mcu_read;
4034         rtl_fw->fw_name = tp->fw_name;
4035         rtl_fw->dev = tp_to_dev(tp);
4036
4037         if (rtl_fw_request_firmware(rtl_fw))
4038                 kfree(rtl_fw);
4039         else
4040                 tp->rtl_fw = rtl_fw;
4041 }
4042
4043 static void rtl_rx_close(struct rtl8169_private *tp)
4044 {
4045         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4046 }
4047
4048 DECLARE_RTL_COND(rtl_npq_cond)
4049 {
4050         return RTL_R8(tp, TxPoll) & NPQ;
4051 }
4052
4053 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4054 {
4055         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4056 }
4057
4058 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4059 {
4060         /* Disable interrupts */
4061         rtl8169_irq_mask_and_ack(tp);
4062
4063         rtl_rx_close(tp);
4064
4065         switch (tp->mac_version) {
4066         case RTL_GIGA_MAC_VER_27:
4067         case RTL_GIGA_MAC_VER_28:
4068         case RTL_GIGA_MAC_VER_31:
4069                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4070                 break;
4071         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4072         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4073                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4074                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4075                 break;
4076         default:
4077                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4078                 udelay(100);
4079                 break;
4080         }
4081
4082         rtl_hw_reset(tp);
4083 }
4084
4085 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4086 {
4087         u32 val = TX_DMA_BURST << TxDMAShift |
4088                   InterFrameGap << TxInterFrameGapShift;
4089
4090         if (rtl_is_8168evl_up(tp))
4091                 val |= TXCFG_AUTO_FIFO;
4092
4093         RTL_W32(tp, TxConfig, val);
4094 }
4095
4096 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4097 {
4098         /* Low hurts. Let's disable the filtering. */
4099         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4100 }
4101
4102 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4103 {
4104         /*
4105          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4106          * register to be written before TxDescAddrLow to work.
4107          * Switching from MMIO to I/O access fixes the issue as well.
4108          */
4109         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4110         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4111         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4112         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4113 }
4114
4115 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4116 {
4117         u32 val;
4118
4119         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4120                 val = 0x000fff00;
4121         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4122                 val = 0x00ffff00;
4123         else
4124                 return;
4125
4126         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4127                 val |= 0xff;
4128
4129         RTL_W32(tp, 0x7c, val);
4130 }
4131
4132 static void rtl_set_rx_mode(struct net_device *dev)
4133 {
4134         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4135         /* Multicast hash filter */
4136         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4137         struct rtl8169_private *tp = netdev_priv(dev);
4138         u32 tmp;
4139
4140         if (dev->flags & IFF_PROMISC) {
4141                 /* Unconditionally log net taps. */
4142                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4143                 rx_mode |= AcceptAllPhys;
4144         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4145                    dev->flags & IFF_ALLMULTI ||
4146                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
4147                 /* accept all multicasts */
4148         } else if (netdev_mc_empty(dev)) {
4149                 rx_mode &= ~AcceptMulticast;
4150         } else {
4151                 struct netdev_hw_addr *ha;
4152
4153                 mc_filter[1] = mc_filter[0] = 0;
4154                 netdev_for_each_mc_addr(ha, dev) {
4155                         u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4156                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4157                 }
4158
4159                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4160                         tmp = mc_filter[0];
4161                         mc_filter[0] = swab32(mc_filter[1]);
4162                         mc_filter[1] = swab32(tmp);
4163                 }
4164         }
4165
4166         if (dev->features & NETIF_F_RXALL)
4167                 rx_mode |= (AcceptErr | AcceptRunt);
4168
4169         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4170         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4171
4172         tmp = RTL_R32(tp, RxConfig);
4173         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4174 }
4175
4176 DECLARE_RTL_COND(rtl_csiar_cond)
4177 {
4178         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4179 }
4180
4181 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4182 {
4183         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4184
4185         RTL_W32(tp, CSIDR, value);
4186         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4187                 CSIAR_BYTE_ENABLE | func << 16);
4188
4189         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4190 }
4191
4192 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4193 {
4194         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4195
4196         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4197                 CSIAR_BYTE_ENABLE);
4198
4199         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4200                 RTL_R32(tp, CSIDR) : ~0;
4201 }
4202
4203 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4204 {
4205         struct pci_dev *pdev = tp->pci_dev;
4206         u32 csi;
4207
4208         /* According to Realtek the value at config space address 0x070f
4209          * controls the L0s/L1 entrance latency. We try standard ECAM access
4210          * first and if it fails fall back to CSI.
4211          */
4212         if (pdev->cfg_size > 0x070f &&
4213             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4214                 return;
4215
4216         netdev_notice_once(tp->dev,
4217                 "No native access to PCI extended config space, falling back to CSI\n");
4218         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4219         rtl_csi_write(tp, 0x070c, csi | val << 24);
4220 }
4221
4222 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4223 {
4224         rtl_csi_access_enable(tp, 0x27);
4225 }
4226
4227 struct ephy_info {
4228         unsigned int offset;
4229         u16 mask;
4230         u16 bits;
4231 };
4232
4233 static void __rtl_ephy_init(struct rtl8169_private *tp,
4234                             const struct ephy_info *e, int len)
4235 {
4236         u16 w;
4237
4238         while (len-- > 0) {
4239                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4240                 rtl_ephy_write(tp, e->offset, w);
4241                 e++;
4242         }
4243 }
4244
4245 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4246
4247 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4248 {
4249         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4250                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4251 }
4252
4253 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4254 {
4255         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4256                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4257 }
4258
4259 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4260 {
4261         /* work around an issue when PCI reset occurs during L2/L3 state */
4262         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4263 }
4264
4265 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4266 {
4267         /* Don't enable ASPM in the chip if OS can't control ASPM */
4268         if (enable && tp->aspm_manageable) {
4269                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4270                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4271         } else {
4272                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4273                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4274         }
4275
4276         udelay(10);
4277 }
4278
4279 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4280                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4281 {
4282         /* Usage of dynamic vs. static FIFO is controlled by bit
4283          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4284          */
4285         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4286         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4287 }
4288
4289 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4290                                           u8 low, u8 high)
4291 {
4292         /* FIFO thresholds for pause flow control */
4293         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4294         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4295 }
4296
4297 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4298 {
4299         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4300
4301         if (tp->dev->mtu <= ETH_DATA_LEN) {
4302                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4303                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4304         }
4305 }
4306
4307 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4308 {
4309         rtl_hw_start_8168bb(tp);
4310
4311         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4312 }
4313
4314 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4315 {
4316         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4317
4318         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4319
4320         if (tp->dev->mtu <= ETH_DATA_LEN)
4321                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4322
4323         rtl_disable_clock_request(tp);
4324 }
4325
4326 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4327 {
4328         static const struct ephy_info e_info_8168cp[] = {
4329                 { 0x01, 0,      0x0001 },
4330                 { 0x02, 0x0800, 0x1000 },
4331                 { 0x03, 0,      0x0042 },
4332                 { 0x06, 0x0080, 0x0000 },
4333                 { 0x07, 0,      0x2000 }
4334         };
4335
4336         rtl_set_def_aspm_entry_latency(tp);
4337
4338         rtl_ephy_init(tp, e_info_8168cp);
4339
4340         __rtl_hw_start_8168cp(tp);
4341 }
4342
4343 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4344 {
4345         rtl_set_def_aspm_entry_latency(tp);
4346
4347         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4348
4349         if (tp->dev->mtu <= ETH_DATA_LEN)
4350                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4351 }
4352
4353 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4354 {
4355         rtl_set_def_aspm_entry_latency(tp);
4356
4357         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4358
4359         /* Magic. */
4360         RTL_W8(tp, DBG_REG, 0x20);
4361
4362         if (tp->dev->mtu <= ETH_DATA_LEN)
4363                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4364 }
4365
4366 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4367 {
4368         static const struct ephy_info e_info_8168c_1[] = {
4369                 { 0x02, 0x0800, 0x1000 },
4370                 { 0x03, 0,      0x0002 },
4371                 { 0x06, 0x0080, 0x0000 }
4372         };
4373
4374         rtl_set_def_aspm_entry_latency(tp);
4375
4376         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4377
4378         rtl_ephy_init(tp, e_info_8168c_1);
4379
4380         __rtl_hw_start_8168cp(tp);
4381 }
4382
4383 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4384 {
4385         static const struct ephy_info e_info_8168c_2[] = {
4386                 { 0x01, 0,      0x0001 },
4387                 { 0x03, 0x0400, 0x0020 }
4388         };
4389
4390         rtl_set_def_aspm_entry_latency(tp);
4391
4392         rtl_ephy_init(tp, e_info_8168c_2);
4393
4394         __rtl_hw_start_8168cp(tp);
4395 }
4396
4397 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4398 {
4399         rtl_hw_start_8168c_2(tp);
4400 }
4401
4402 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4403 {
4404         rtl_set_def_aspm_entry_latency(tp);
4405
4406         __rtl_hw_start_8168cp(tp);
4407 }
4408
4409 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4410 {
4411         rtl_set_def_aspm_entry_latency(tp);
4412
4413         rtl_disable_clock_request(tp);
4414
4415         if (tp->dev->mtu <= ETH_DATA_LEN)
4416                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4417 }
4418
4419 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4420 {
4421         rtl_set_def_aspm_entry_latency(tp);
4422
4423         if (tp->dev->mtu <= ETH_DATA_LEN)
4424                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4425
4426         rtl_disable_clock_request(tp);
4427 }
4428
4429 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4430 {
4431         static const struct ephy_info e_info_8168d_4[] = {
4432                 { 0x0b, 0x0000, 0x0048 },
4433                 { 0x19, 0x0020, 0x0050 },
4434                 { 0x0c, 0x0100, 0x0020 },
4435                 { 0x10, 0x0004, 0x0000 },
4436         };
4437
4438         rtl_set_def_aspm_entry_latency(tp);
4439
4440         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4441
4442         rtl_ephy_init(tp, e_info_8168d_4);
4443
4444         rtl_enable_clock_request(tp);
4445 }
4446
4447 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4448 {
4449         static const struct ephy_info e_info_8168e_1[] = {
4450                 { 0x00, 0x0200, 0x0100 },
4451                 { 0x00, 0x0000, 0x0004 },
4452                 { 0x06, 0x0002, 0x0001 },
4453                 { 0x06, 0x0000, 0x0030 },
4454                 { 0x07, 0x0000, 0x2000 },
4455                 { 0x00, 0x0000, 0x0020 },
4456                 { 0x03, 0x5800, 0x2000 },
4457                 { 0x03, 0x0000, 0x0001 },
4458                 { 0x01, 0x0800, 0x1000 },
4459                 { 0x07, 0x0000, 0x4000 },
4460                 { 0x1e, 0x0000, 0x2000 },
4461                 { 0x19, 0xffff, 0xfe6c },
4462                 { 0x0a, 0x0000, 0x0040 }
4463         };
4464
4465         rtl_set_def_aspm_entry_latency(tp);
4466
4467         rtl_ephy_init(tp, e_info_8168e_1);
4468
4469         if (tp->dev->mtu <= ETH_DATA_LEN)
4470                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4471
4472         rtl_disable_clock_request(tp);
4473
4474         /* Reset tx FIFO pointer */
4475         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4476         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4477
4478         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4479 }
4480
4481 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4482 {
4483         static const struct ephy_info e_info_8168e_2[] = {
4484                 { 0x09, 0x0000, 0x0080 },
4485                 { 0x19, 0x0000, 0x0224 },
4486                 { 0x00, 0x0000, 0x0004 },
4487                 { 0x0c, 0x3df0, 0x0200 },
4488         };
4489
4490         rtl_set_def_aspm_entry_latency(tp);
4491
4492         rtl_ephy_init(tp, e_info_8168e_2);
4493
4494         if (tp->dev->mtu <= ETH_DATA_LEN)
4495                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4496
4497         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4498         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4499         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4500         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4501         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4502         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4503         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4504
4505         rtl_disable_clock_request(tp);
4506
4507         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4508
4509         rtl8168_config_eee_mac(tp);
4510
4511         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4512         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4513         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4514
4515         rtl_hw_aspm_clkreq_enable(tp, true);
4516 }
4517
4518 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4519 {
4520         rtl_set_def_aspm_entry_latency(tp);
4521
4522         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4523
4524         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4525         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4526         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4527         rtl_reset_packet_filter(tp);
4528         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4529         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4530         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4531         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4532
4533         rtl_disable_clock_request(tp);
4534
4535         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4536         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4537         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4538         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4539
4540         rtl8168_config_eee_mac(tp);
4541 }
4542
4543 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4544 {
4545         static const struct ephy_info e_info_8168f_1[] = {
4546                 { 0x06, 0x00c0, 0x0020 },
4547                 { 0x08, 0x0001, 0x0002 },
4548                 { 0x09, 0x0000, 0x0080 },
4549                 { 0x19, 0x0000, 0x0224 },
4550                 { 0x00, 0x0000, 0x0004 },
4551                 { 0x0c, 0x3df0, 0x0200 },
4552         };
4553
4554         rtl_hw_start_8168f(tp);
4555
4556         rtl_ephy_init(tp, e_info_8168f_1);
4557
4558         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4559 }
4560
4561 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4562 {
4563         static const struct ephy_info e_info_8168f_1[] = {
4564                 { 0x06, 0x00c0, 0x0020 },
4565                 { 0x0f, 0xffff, 0x5200 },
4566                 { 0x19, 0x0000, 0x0224 },
4567                 { 0x00, 0x0000, 0x0004 },
4568                 { 0x0c, 0x3df0, 0x0200 },
4569         };
4570
4571         rtl_hw_start_8168f(tp);
4572         rtl_pcie_state_l2l3_disable(tp);
4573
4574         rtl_ephy_init(tp, e_info_8168f_1);
4575
4576         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4577 }
4578
4579 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4580 {
4581         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4582         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4583
4584         rtl_set_def_aspm_entry_latency(tp);
4585
4586         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4587
4588         rtl_reset_packet_filter(tp);
4589         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4590
4591         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4592
4593         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4594         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4595
4596         rtl8168_config_eee_mac(tp);
4597
4598         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4599         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4600
4601         rtl_pcie_state_l2l3_disable(tp);
4602 }
4603
4604 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4605 {
4606         static const struct ephy_info e_info_8168g_1[] = {
4607                 { 0x00, 0x0008, 0x0000 },
4608                 { 0x0c, 0x3ff0, 0x0820 },
4609                 { 0x1e, 0x0000, 0x0001 },
4610                 { 0x19, 0x8000, 0x0000 }
4611         };
4612
4613         rtl_hw_start_8168g(tp);
4614
4615         /* disable aspm and clock request before access ephy */
4616         rtl_hw_aspm_clkreq_enable(tp, false);
4617         rtl_ephy_init(tp, e_info_8168g_1);
4618         rtl_hw_aspm_clkreq_enable(tp, true);
4619 }
4620
4621 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4622 {
4623         static const struct ephy_info e_info_8168g_2[] = {
4624                 { 0x00, 0x0008, 0x0000 },
4625                 { 0x0c, 0x3ff0, 0x0820 },
4626                 { 0x19, 0xffff, 0x7c00 },
4627                 { 0x1e, 0xffff, 0x20eb },
4628                 { 0x0d, 0xffff, 0x1666 },
4629                 { 0x00, 0xffff, 0x10a3 },
4630                 { 0x06, 0xffff, 0xf050 },
4631                 { 0x04, 0x0000, 0x0010 },
4632                 { 0x1d, 0x4000, 0x0000 },
4633         };
4634
4635         rtl_hw_start_8168g(tp);
4636
4637         /* disable aspm and clock request before access ephy */
4638         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4639         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4640         rtl_ephy_init(tp, e_info_8168g_2);
4641 }
4642
4643 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4644 {
4645         static const struct ephy_info e_info_8411_2[] = {
4646                 { 0x00, 0x0008, 0x0000 },
4647                 { 0x0c, 0x37d0, 0x0820 },
4648                 { 0x1e, 0x0000, 0x0001 },
4649                 { 0x19, 0x8021, 0x0000 },
4650                 { 0x1e, 0x0000, 0x2000 },
4651                 { 0x0d, 0x0100, 0x0200 },
4652                 { 0x00, 0x0000, 0x0080 },
4653                 { 0x06, 0x0000, 0x0010 },
4654                 { 0x04, 0x0000, 0x0010 },
4655                 { 0x1d, 0x0000, 0x4000 },
4656         };
4657
4658         rtl_hw_start_8168g(tp);
4659
4660         /* disable aspm and clock request before access ephy */
4661         rtl_hw_aspm_clkreq_enable(tp, false);
4662         rtl_ephy_init(tp, e_info_8411_2);
4663
4664         /* The following Realtek-provided magic fixes an issue with the RX unit
4665          * getting confused after the PHY having been powered-down.
4666          */
4667         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4668         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4669         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4670         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4671         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4672         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4673         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4674         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4675         mdelay(3);
4676         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4677
4678         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4679         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4680         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4681         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4682         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4683         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4684         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4685         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4686         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4687         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4688         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4689         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4690         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4691         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4692         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4693         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4694         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4695         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4696         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4697         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4698         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4699         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4700         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4701         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4702         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4703         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4704         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4705         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4706         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4707         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4708         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4709         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4710         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4711         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4712         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4713         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4714         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4715         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4716         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4717         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4718         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4719         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4720         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4721         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4722         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4723         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4724         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4725         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4726         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4727         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4728         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4729         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4730         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4731         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4732         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4733         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4734         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4735         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4736         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4737         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4738         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4739         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4740         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4741         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4742         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4743         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4744         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4745         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4746         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4747         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4748         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4749         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4750         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4751         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4752         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4753         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4754         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4755         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4756         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4757         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4758         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4759         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4760         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4761         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4762         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4763         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4764         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4765         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4766         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4767         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4768         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4769         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4770         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4771         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4772         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4773         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4774         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4775         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4776         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4777         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4778         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4779         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4780         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4781         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4782         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4783         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4784         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4785         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4786         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4787         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4788         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4789
4790         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4791
4792         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4793         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4794         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4795         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4796         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4797         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4798         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4799
4800         rtl_hw_aspm_clkreq_enable(tp, true);
4801 }
4802
4803 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4804 {
4805         static const struct ephy_info e_info_8168h_1[] = {
4806                 { 0x1e, 0x0800, 0x0001 },
4807                 { 0x1d, 0x0000, 0x0800 },
4808                 { 0x05, 0xffff, 0x2089 },
4809                 { 0x06, 0xffff, 0x5881 },
4810                 { 0x04, 0xffff, 0x854a },
4811                 { 0x01, 0xffff, 0x068b }
4812         };
4813         int rg_saw_cnt;
4814
4815         /* disable aspm and clock request before access ephy */
4816         rtl_hw_aspm_clkreq_enable(tp, false);
4817         rtl_ephy_init(tp, e_info_8168h_1);
4818
4819         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4820         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4821
4822         rtl_set_def_aspm_entry_latency(tp);
4823
4824         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4825
4826         rtl_reset_packet_filter(tp);
4827
4828         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4829
4830         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4831
4832         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4833
4834         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4835
4836         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4837         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4838
4839         rtl8168_config_eee_mac(tp);
4840
4841         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4842         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4843
4844         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4845
4846         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4847
4848         rtl_pcie_state_l2l3_disable(tp);
4849
4850         rtl_writephy(tp, 0x1f, 0x0c42);
4851         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4852         rtl_writephy(tp, 0x1f, 0x0000);
4853         if (rg_saw_cnt > 0) {
4854                 u16 sw_cnt_1ms_ini;
4855
4856                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4857                 sw_cnt_1ms_ini &= 0x0fff;
4858                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4859         }
4860
4861         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4862         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4863         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4864         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4865
4866         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4867         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4868         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4869         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4870
4871         rtl_hw_aspm_clkreq_enable(tp, true);
4872 }
4873
4874 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4875 {
4876         rtl8168ep_stop_cmac(tp);
4877
4878         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4879         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4880
4881         rtl_set_def_aspm_entry_latency(tp);
4882
4883         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4884
4885         rtl_reset_packet_filter(tp);
4886
4887         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4888
4889         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4890
4891         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4892
4893         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4894         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4895
4896         rtl8168_config_eee_mac(tp);
4897
4898         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4899
4900         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4901
4902         rtl_pcie_state_l2l3_disable(tp);
4903 }
4904
4905 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4906 {
4907         static const struct ephy_info e_info_8168ep_1[] = {
4908                 { 0x00, 0xffff, 0x10ab },
4909                 { 0x06, 0xffff, 0xf030 },
4910                 { 0x08, 0xffff, 0x2006 },
4911                 { 0x0d, 0xffff, 0x1666 },
4912                 { 0x0c, 0x3ff0, 0x0000 }
4913         };
4914
4915         /* disable aspm and clock request before access ephy */
4916         rtl_hw_aspm_clkreq_enable(tp, false);
4917         rtl_ephy_init(tp, e_info_8168ep_1);
4918
4919         rtl_hw_start_8168ep(tp);
4920
4921         rtl_hw_aspm_clkreq_enable(tp, true);
4922 }
4923
4924 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4925 {
4926         static const struct ephy_info e_info_8168ep_2[] = {
4927                 { 0x00, 0xffff, 0x10a3 },
4928                 { 0x19, 0xffff, 0xfc00 },
4929                 { 0x1e, 0xffff, 0x20ea }
4930         };
4931
4932         /* disable aspm and clock request before access ephy */
4933         rtl_hw_aspm_clkreq_enable(tp, false);
4934         rtl_ephy_init(tp, e_info_8168ep_2);
4935
4936         rtl_hw_start_8168ep(tp);
4937
4938         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4939         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4940
4941         rtl_hw_aspm_clkreq_enable(tp, true);
4942 }
4943
4944 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4945 {
4946         static const struct ephy_info e_info_8168ep_3[] = {
4947                 { 0x00, 0x0000, 0x0080 },
4948                 { 0x0d, 0x0100, 0x0200 },
4949                 { 0x19, 0x8021, 0x0000 },
4950                 { 0x1e, 0x0000, 0x2000 },
4951         };
4952
4953         /* disable aspm and clock request before access ephy */
4954         rtl_hw_aspm_clkreq_enable(tp, false);
4955         rtl_ephy_init(tp, e_info_8168ep_3);
4956
4957         rtl_hw_start_8168ep(tp);
4958
4959         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4960         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4961
4962         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4963         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4964         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4965
4966         rtl_hw_aspm_clkreq_enable(tp, true);
4967 }
4968
4969 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4970 {
4971         static const struct ephy_info e_info_8102e_1[] = {
4972                 { 0x01, 0, 0x6e65 },
4973                 { 0x02, 0, 0x091f },
4974                 { 0x03, 0, 0xc2f9 },
4975                 { 0x06, 0, 0xafb5 },
4976                 { 0x07, 0, 0x0e00 },
4977                 { 0x19, 0, 0xec80 },
4978                 { 0x01, 0, 0x2e65 },
4979                 { 0x01, 0, 0x6e65 }
4980         };
4981         u8 cfg1;
4982
4983         rtl_set_def_aspm_entry_latency(tp);
4984
4985         RTL_W8(tp, DBG_REG, FIX_NAK_1);
4986
4987         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4988
4989         RTL_W8(tp, Config1,
4990                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4991         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4992
4993         cfg1 = RTL_R8(tp, Config1);
4994         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4995                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4996
4997         rtl_ephy_init(tp, e_info_8102e_1);
4998 }
4999
5000 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5001 {
5002         rtl_set_def_aspm_entry_latency(tp);
5003
5004         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5005
5006         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5007         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5008 }
5009
5010 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5011 {
5012         rtl_hw_start_8102e_2(tp);
5013
5014         rtl_ephy_write(tp, 0x03, 0xc2f9);
5015 }
5016
5017 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5018 {
5019         static const struct ephy_info e_info_8105e_1[] = {
5020                 { 0x07, 0, 0x4000 },
5021                 { 0x19, 0, 0x0200 },
5022                 { 0x19, 0, 0x0020 },
5023                 { 0x1e, 0, 0x2000 },
5024                 { 0x03, 0, 0x0001 },
5025                 { 0x19, 0, 0x0100 },
5026                 { 0x19, 0, 0x0004 },
5027                 { 0x0a, 0, 0x0020 }
5028         };
5029
5030         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5031         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5032
5033         /* Disable Early Tally Counter */
5034         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5035
5036         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5037         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5038
5039         rtl_ephy_init(tp, e_info_8105e_1);
5040
5041         rtl_pcie_state_l2l3_disable(tp);
5042 }
5043
5044 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5045 {
5046         rtl_hw_start_8105e_1(tp);
5047         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5048 }
5049
5050 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5051 {
5052         static const struct ephy_info e_info_8402[] = {
5053                 { 0x19, 0xffff, 0xff64 },
5054                 { 0x1e, 0, 0x4000 }
5055         };
5056
5057         rtl_set_def_aspm_entry_latency(tp);
5058
5059         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5060         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5061
5062         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5063
5064         rtl_ephy_init(tp, e_info_8402);
5065
5066         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5067
5068         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5069         rtl_reset_packet_filter(tp);
5070         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5071         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5072         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5073
5074         rtl_pcie_state_l2l3_disable(tp);
5075 }
5076
5077 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5078 {
5079         rtl_hw_aspm_clkreq_enable(tp, false);
5080
5081         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5082         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5083
5084         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5085         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5086         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5087
5088         rtl_pcie_state_l2l3_disable(tp);
5089         rtl_hw_aspm_clkreq_enable(tp, true);
5090 }
5091
5092 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5093 {
5094         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5095 }
5096
5097 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5098 {
5099         rtl_pcie_state_l2l3_disable(tp);
5100
5101         RTL_W16(tp, 0x382, 0x221b);
5102         RTL_W8(tp, 0x4500, 0);
5103         RTL_W16(tp, 0x4800, 0);
5104
5105         /* disable UPS */
5106         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5107
5108         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5109
5110         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5111         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5112
5113         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5114         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5115         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5116
5117         /* disable new tx descriptor format */
5118         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5119
5120         r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5121         r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5122         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5123         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5124         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5125         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5126         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5127         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5128         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5129         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5130         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5131         r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5132         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5133         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5134         udelay(1);
5135         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5136         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5137
5138         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5139
5140         rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5141
5142         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5143         udelay(10);
5144 }
5145
5146 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5147 {
5148         static const struct ephy_info e_info_8125_1[] = {
5149                 { 0x01, 0xffff, 0xa812 },
5150                 { 0x09, 0xffff, 0x520c },
5151                 { 0x04, 0xffff, 0xd000 },
5152                 { 0x0d, 0xffff, 0xf702 },
5153                 { 0x0a, 0xffff, 0x8653 },
5154                 { 0x06, 0xffff, 0x001e },
5155                 { 0x08, 0xffff, 0x3595 },
5156                 { 0x20, 0xffff, 0x9455 },
5157                 { 0x21, 0xffff, 0x99ff },
5158                 { 0x02, 0xffff, 0x6046 },
5159                 { 0x29, 0xffff, 0xfe00 },
5160                 { 0x23, 0xffff, 0xab62 },
5161
5162                 { 0x41, 0xffff, 0xa80c },
5163                 { 0x49, 0xffff, 0x520c },
5164                 { 0x44, 0xffff, 0xd000 },
5165                 { 0x4d, 0xffff, 0xf702 },
5166                 { 0x4a, 0xffff, 0x8653 },
5167                 { 0x46, 0xffff, 0x001e },
5168                 { 0x48, 0xffff, 0x3595 },
5169                 { 0x60, 0xffff, 0x9455 },
5170                 { 0x61, 0xffff, 0x99ff },
5171                 { 0x42, 0xffff, 0x6046 },
5172                 { 0x69, 0xffff, 0xfe00 },
5173                 { 0x63, 0xffff, 0xab62 },
5174         };
5175
5176         rtl_set_def_aspm_entry_latency(tp);
5177
5178         /* disable aspm and clock request before access ephy */
5179         rtl_hw_aspm_clkreq_enable(tp, false);
5180         rtl_ephy_init(tp, e_info_8125_1);
5181
5182         rtl_hw_start_8125_common(tp);
5183 }
5184
5185 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5186 {
5187         static const struct ephy_info e_info_8125_2[] = {
5188                 { 0x04, 0xffff, 0xd000 },
5189                 { 0x0a, 0xffff, 0x8653 },
5190                 { 0x23, 0xffff, 0xab66 },
5191                 { 0x20, 0xffff, 0x9455 },
5192                 { 0x21, 0xffff, 0x99ff },
5193                 { 0x29, 0xffff, 0xfe04 },
5194
5195                 { 0x44, 0xffff, 0xd000 },
5196                 { 0x4a, 0xffff, 0x8653 },
5197                 { 0x63, 0xffff, 0xab66 },
5198                 { 0x60, 0xffff, 0x9455 },
5199                 { 0x61, 0xffff, 0x99ff },
5200                 { 0x69, 0xffff, 0xfe04 },
5201         };
5202
5203         rtl_set_def_aspm_entry_latency(tp);
5204
5205         /* disable aspm and clock request before access ephy */
5206         rtl_hw_aspm_clkreq_enable(tp, false);
5207         rtl_ephy_init(tp, e_info_8125_2);
5208
5209         rtl_hw_start_8125_common(tp);
5210 }
5211
5212 static void rtl_hw_config(struct rtl8169_private *tp)
5213 {
5214         static const rtl_generic_fct hw_configs[] = {
5215                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5216                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5217                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5218                 [RTL_GIGA_MAC_VER_10] = NULL,
5219                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5220                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5221                 [RTL_GIGA_MAC_VER_13] = NULL,
5222                 [RTL_GIGA_MAC_VER_14] = NULL,
5223                 [RTL_GIGA_MAC_VER_15] = NULL,
5224                 [RTL_GIGA_MAC_VER_16] = NULL,
5225                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5226                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5227                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5228                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5229                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5230                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5231                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5232                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5233                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5234                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5235                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5236                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5237                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5238                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5239                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5240                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5241                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5242                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5243                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5244                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5245                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5246                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5247                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5248                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5249                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5250                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5251                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5252                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5253                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5254                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5255                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5256                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5257                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5258                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5259                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5260                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5261                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
5262         };
5263
5264         if (hw_configs[tp->mac_version])
5265                 hw_configs[tp->mac_version](tp);
5266 }
5267
5268 static void rtl_hw_start_8125(struct rtl8169_private *tp)
5269 {
5270         int i;
5271
5272         /* disable interrupt coalescing */
5273         for (i = 0xa00; i < 0xb00; i += 4)
5274                 RTL_W32(tp, i, 0);
5275
5276         rtl_hw_config(tp);
5277 }
5278
5279 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5280 {
5281         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5282             tp->mac_version == RTL_GIGA_MAC_VER_16)
5283                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5284                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5285
5286         if (rtl_is_8168evl_up(tp))
5287                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5288         else
5289                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5290
5291         rtl_hw_config(tp);
5292
5293         /* disable interrupt coalescing */
5294         RTL_W16(tp, IntrMitigate, 0x0000);
5295 }
5296
5297 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5298 {
5299         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5300                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5301
5302         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5303
5304         tp->cp_cmd |= PCIMulRW;
5305
5306         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5307             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5308                 netif_dbg(tp, drv, tp->dev,
5309                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5310                 tp->cp_cmd |= (1 << 14);
5311         }
5312
5313         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5314
5315         rtl8169_set_magic_reg(tp, tp->mac_version);
5316
5317         RTL_W32(tp, RxMissed, 0);
5318
5319         /* disable interrupt coalescing */
5320         RTL_W16(tp, IntrMitigate, 0x0000);
5321 }
5322
5323 static void rtl_hw_start(struct  rtl8169_private *tp)
5324 {
5325         rtl_unlock_config_regs(tp);
5326
5327         tp->cp_cmd &= CPCMD_MASK;
5328         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5329
5330         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5331                 rtl_hw_start_8169(tp);
5332         else if (rtl_is_8125(tp))
5333                 rtl_hw_start_8125(tp);
5334         else
5335                 rtl_hw_start_8168(tp);
5336
5337         rtl_set_rx_max_size(tp);
5338         rtl_set_rx_tx_desc_registers(tp);
5339         rtl_lock_config_regs(tp);
5340
5341         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5342         RTL_R16(tp, CPlusCmd);
5343         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5344         rtl_init_rxcfg(tp);
5345         rtl_set_tx_config_registers(tp);
5346         rtl_set_rx_mode(tp->dev);
5347         rtl_irq_enable(tp);
5348 }
5349
5350 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5351 {
5352         struct rtl8169_private *tp = netdev_priv(dev);
5353
5354         if (new_mtu > ETH_DATA_LEN)
5355                 rtl_hw_jumbo_enable(tp);
5356         else
5357                 rtl_hw_jumbo_disable(tp);
5358
5359         dev->mtu = new_mtu;
5360         netdev_update_features(dev);
5361
5362         return 0;
5363 }
5364
5365 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5366 {
5367         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5368         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5369 }
5370
5371 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5372 {
5373         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5374
5375         /* Force memory writes to complete before releasing descriptor */
5376         dma_wmb();
5377
5378         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5379 }
5380
5381 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5382                                           struct RxDesc *desc)
5383 {
5384         struct device *d = tp_to_dev(tp);
5385         int node = dev_to_node(d);
5386         dma_addr_t mapping;
5387         struct page *data;
5388
5389         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5390         if (!data)
5391                 return NULL;
5392
5393         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5394         if (unlikely(dma_mapping_error(d, mapping))) {
5395                 if (net_ratelimit())
5396                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5397                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5398                 return NULL;
5399         }
5400
5401         desc->addr = cpu_to_le64(mapping);
5402         rtl8169_mark_to_asic(desc);
5403
5404         return data;
5405 }
5406
5407 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5408 {
5409         unsigned int i;
5410
5411         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5412                 dma_unmap_page(tp_to_dev(tp),
5413                                le64_to_cpu(tp->RxDescArray[i].addr),
5414                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5415                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5416                 tp->Rx_databuff[i] = NULL;
5417                 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5418         }
5419 }
5420
5421 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5422 {
5423         desc->opts1 |= cpu_to_le32(RingEnd);
5424 }
5425
5426 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5427 {
5428         unsigned int i;
5429
5430         for (i = 0; i < NUM_RX_DESC; i++) {
5431                 struct page *data;
5432
5433                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5434                 if (!data) {
5435                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5436                         goto err_out;
5437                 }
5438                 tp->Rx_databuff[i] = data;
5439         }
5440
5441         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5442         return 0;
5443
5444 err_out:
5445         rtl8169_rx_clear(tp);
5446         return -ENOMEM;
5447 }
5448
5449 static int rtl8169_init_ring(struct rtl8169_private *tp)
5450 {
5451         rtl8169_init_ring_indexes(tp);
5452
5453         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5454         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5455
5456         return rtl8169_rx_fill(tp);
5457 }
5458
5459 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5460                                  struct TxDesc *desc)
5461 {
5462         unsigned int len = tx_skb->len;
5463
5464         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5465
5466         desc->opts1 = 0x00;
5467         desc->opts2 = 0x00;
5468         desc->addr = 0x00;
5469         tx_skb->len = 0;
5470 }
5471
5472 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5473                                    unsigned int n)
5474 {
5475         unsigned int i;
5476
5477         for (i = 0; i < n; i++) {
5478                 unsigned int entry = (start + i) % NUM_TX_DESC;
5479                 struct ring_info *tx_skb = tp->tx_skb + entry;
5480                 unsigned int len = tx_skb->len;
5481
5482                 if (len) {
5483                         struct sk_buff *skb = tx_skb->skb;
5484
5485                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5486                                              tp->TxDescArray + entry);
5487                         if (skb) {
5488                                 dev_consume_skb_any(skb);
5489                                 tx_skb->skb = NULL;
5490                         }
5491                 }
5492         }
5493 }
5494
5495 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5496 {
5497         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5498         tp->cur_tx = tp->dirty_tx = 0;
5499         netdev_reset_queue(tp->dev);
5500 }
5501
5502 static void rtl_reset_work(struct rtl8169_private *tp)
5503 {
5504         struct net_device *dev = tp->dev;
5505         int i;
5506
5507         napi_disable(&tp->napi);
5508         netif_stop_queue(dev);
5509         synchronize_rcu();
5510
5511         rtl8169_hw_reset(tp);
5512
5513         for (i = 0; i < NUM_RX_DESC; i++)
5514                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5515
5516         rtl8169_tx_clear(tp);
5517         rtl8169_init_ring_indexes(tp);
5518
5519         napi_enable(&tp->napi);
5520         rtl_hw_start(tp);
5521         netif_wake_queue(dev);
5522 }
5523
5524 static void rtl8169_tx_timeout(struct net_device *dev)
5525 {
5526         struct rtl8169_private *tp = netdev_priv(dev);
5527
5528         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5529 }
5530
5531 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5532 {
5533         u32 status = opts0 | len;
5534
5535         if (entry == NUM_TX_DESC - 1)
5536                 status |= RingEnd;
5537
5538         return cpu_to_le32(status);
5539 }
5540
5541 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5542                               u32 *opts)
5543 {
5544         struct skb_shared_info *info = skb_shinfo(skb);
5545         unsigned int cur_frag, entry;
5546         struct TxDesc *uninitialized_var(txd);
5547         struct device *d = tp_to_dev(tp);
5548
5549         entry = tp->cur_tx;
5550         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5551                 const skb_frag_t *frag = info->frags + cur_frag;
5552                 dma_addr_t mapping;
5553                 u32 len;
5554                 void *addr;
5555
5556                 entry = (entry + 1) % NUM_TX_DESC;
5557
5558                 txd = tp->TxDescArray + entry;
5559                 len = skb_frag_size(frag);
5560                 addr = skb_frag_address(frag);
5561                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5562                 if (unlikely(dma_mapping_error(d, mapping))) {
5563                         if (net_ratelimit())
5564                                 netif_err(tp, drv, tp->dev,
5565                                           "Failed to map TX fragments DMA!\n");
5566                         goto err_out;
5567                 }
5568
5569                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5570                 txd->opts2 = cpu_to_le32(opts[1]);
5571                 txd->addr = cpu_to_le64(mapping);
5572
5573                 tp->tx_skb[entry].len = len;
5574         }
5575
5576         if (cur_frag) {
5577                 tp->tx_skb[entry].skb = skb;
5578                 txd->opts1 |= cpu_to_le32(LastFrag);
5579         }
5580
5581         return cur_frag;
5582
5583 err_out:
5584         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5585         return -EIO;
5586 }
5587
5588 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5589 {
5590         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5591 }
5592
5593 /* msdn_giant_send_check()
5594  * According to the document of microsoft, the TCP Pseudo Header excludes the
5595  * packet length for IPv6 TCP large packets.
5596  */
5597 static int msdn_giant_send_check(struct sk_buff *skb)
5598 {
5599         const struct ipv6hdr *ipv6h;
5600         struct tcphdr *th;
5601         int ret;
5602
5603         ret = skb_cow_head(skb, 0);
5604         if (ret)
5605                 return ret;
5606
5607         ipv6h = ipv6_hdr(skb);
5608         th = tcp_hdr(skb);
5609
5610         th->check = 0;
5611         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5612
5613         return ret;
5614 }
5615
5616 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5617 {
5618         u32 mss = skb_shinfo(skb)->gso_size;
5619
5620         if (mss) {
5621                 opts[0] |= TD_LSO;
5622                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5623         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5624                 const struct iphdr *ip = ip_hdr(skb);
5625
5626                 if (ip->protocol == IPPROTO_TCP)
5627                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5628                 else if (ip->protocol == IPPROTO_UDP)
5629                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5630                 else
5631                         WARN_ON_ONCE(1);
5632         }
5633 }
5634
5635 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5636                                 struct sk_buff *skb, u32 *opts)
5637 {
5638         u32 transport_offset = (u32)skb_transport_offset(skb);
5639         u32 mss = skb_shinfo(skb)->gso_size;
5640
5641         if (mss) {
5642                 switch (vlan_get_protocol(skb)) {
5643                 case htons(ETH_P_IP):
5644                         opts[0] |= TD1_GTSENV4;
5645                         break;
5646
5647                 case htons(ETH_P_IPV6):
5648                         if (msdn_giant_send_check(skb))
5649                                 return false;
5650
5651                         opts[0] |= TD1_GTSENV6;
5652                         break;
5653
5654                 default:
5655                         WARN_ON_ONCE(1);
5656                         break;
5657                 }
5658
5659                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5660                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5661         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5662                 u8 ip_protocol;
5663
5664                 switch (vlan_get_protocol(skb)) {
5665                 case htons(ETH_P_IP):
5666                         opts[1] |= TD1_IPv4_CS;
5667                         ip_protocol = ip_hdr(skb)->protocol;
5668                         break;
5669
5670                 case htons(ETH_P_IPV6):
5671                         opts[1] |= TD1_IPv6_CS;
5672                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5673                         break;
5674
5675                 default:
5676                         ip_protocol = IPPROTO_RAW;
5677                         break;
5678                 }
5679
5680                 if (ip_protocol == IPPROTO_TCP)
5681                         opts[1] |= TD1_TCP_CS;
5682                 else if (ip_protocol == IPPROTO_UDP)
5683                         opts[1] |= TD1_UDP_CS;
5684                 else
5685                         WARN_ON_ONCE(1);
5686
5687                 opts[1] |= transport_offset << TCPHO_SHIFT;
5688         } else {
5689                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5690                         return !eth_skb_pad(skb);
5691         }
5692
5693         return true;
5694 }
5695
5696 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5697                                unsigned int nr_frags)
5698 {
5699         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5700
5701         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5702         return slots_avail > nr_frags;
5703 }
5704
5705 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5706 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5707 {
5708         switch (tp->mac_version) {
5709         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5710         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5711                 return false;
5712         default:
5713                 return true;
5714         }
5715 }
5716
5717 static void rtl8169_doorbell(struct rtl8169_private *tp)
5718 {
5719         if (rtl_is_8125(tp))
5720                 RTL_W16(tp, TxPoll_8125, BIT(0));
5721         else
5722                 RTL_W8(tp, TxPoll, NPQ);
5723 }
5724
5725 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5726                                       struct net_device *dev)
5727 {
5728         struct rtl8169_private *tp = netdev_priv(dev);
5729         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5730         struct TxDesc *txd = tp->TxDescArray + entry;
5731         struct device *d = tp_to_dev(tp);
5732         dma_addr_t mapping;
5733         u32 opts[2], len;
5734         bool stop_queue;
5735         bool door_bell;
5736         int frags;
5737
5738         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5739                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5740                 goto err_stop_0;
5741         }
5742
5743         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5744                 goto err_stop_0;
5745
5746         opts[1] = rtl8169_tx_vlan_tag(skb);
5747         opts[0] = DescOwn;
5748
5749         if (rtl_chip_supports_csum_v2(tp)) {
5750                 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5751                         goto err_dma_0;
5752         } else {
5753                 rtl8169_tso_csum_v1(skb, opts);
5754         }
5755
5756         len = skb_headlen(skb);
5757         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5758         if (unlikely(dma_mapping_error(d, mapping))) {
5759                 if (net_ratelimit())
5760                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5761                 goto err_dma_0;
5762         }
5763
5764         tp->tx_skb[entry].len = len;
5765         txd->addr = cpu_to_le64(mapping);
5766
5767         frags = rtl8169_xmit_frags(tp, skb, opts);
5768         if (frags < 0)
5769                 goto err_dma_1;
5770         else if (frags)
5771                 opts[0] |= FirstFrag;
5772         else {
5773                 opts[0] |= FirstFrag | LastFrag;
5774                 tp->tx_skb[entry].skb = skb;
5775         }
5776
5777         txd->opts2 = cpu_to_le32(opts[1]);
5778
5779         skb_tx_timestamp(skb);
5780
5781         /* Force memory writes to complete before releasing descriptor */
5782         dma_wmb();
5783
5784         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5785
5786         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5787
5788         /* Force all memory writes to complete before notifying device */
5789         wmb();
5790
5791         tp->cur_tx += frags + 1;
5792
5793         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5794         if (unlikely(stop_queue)) {
5795                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5796                  * not miss a ring update when it notices a stopped queue.
5797                  */
5798                 smp_wmb();
5799                 netif_stop_queue(dev);
5800                 door_bell = true;
5801         }
5802
5803         if (door_bell)
5804                 rtl8169_doorbell(tp);
5805
5806         if (unlikely(stop_queue)) {
5807                 /* Sync with rtl_tx:
5808                  * - publish queue status and cur_tx ring index (write barrier)
5809                  * - refresh dirty_tx ring index (read barrier).
5810                  * May the current thread have a pessimistic view of the ring
5811                  * status and forget to wake up queue, a racing rtl_tx thread
5812                  * can't.
5813                  */
5814                 smp_mb();
5815                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5816                         netif_start_queue(dev);
5817         }
5818
5819         return NETDEV_TX_OK;
5820
5821 err_dma_1:
5822         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5823 err_dma_0:
5824         dev_kfree_skb_any(skb);
5825         dev->stats.tx_dropped++;
5826         return NETDEV_TX_OK;
5827
5828 err_stop_0:
5829         netif_stop_queue(dev);
5830         dev->stats.tx_dropped++;
5831         return NETDEV_TX_BUSY;
5832 }
5833
5834 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5835                                                 struct net_device *dev,
5836                                                 netdev_features_t features)
5837 {
5838         int transport_offset = skb_transport_offset(skb);
5839         struct rtl8169_private *tp = netdev_priv(dev);
5840
5841         if (skb_is_gso(skb)) {
5842                 if (transport_offset > GTTCPHO_MAX &&
5843                     rtl_chip_supports_csum_v2(tp))
5844                         features &= ~NETIF_F_ALL_TSO;
5845         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5846                 if (skb->len < ETH_ZLEN) {
5847                         switch (tp->mac_version) {
5848                         case RTL_GIGA_MAC_VER_11:
5849                         case RTL_GIGA_MAC_VER_12:
5850                         case RTL_GIGA_MAC_VER_17:
5851                         case RTL_GIGA_MAC_VER_34:
5852                                 features &= ~NETIF_F_CSUM_MASK;
5853                                 break;
5854                         default:
5855                                 break;
5856                         }
5857                 }
5858
5859                 if (transport_offset > TCPHO_MAX &&
5860                     rtl_chip_supports_csum_v2(tp))
5861                         features &= ~NETIF_F_CSUM_MASK;
5862         }
5863
5864         return vlan_features_check(skb, features);
5865 }
5866
5867 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5868 {
5869         struct rtl8169_private *tp = netdev_priv(dev);
5870         struct pci_dev *pdev = tp->pci_dev;
5871         u16 pci_status, pci_cmd;
5872
5873         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5874         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5875
5876         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5877                   pci_cmd, pci_status);
5878
5879         /*
5880          * The recovery sequence below admits a very elaborated explanation:
5881          * - it seems to work;
5882          * - I did not see what else could be done;
5883          * - it makes iop3xx happy.
5884          *
5885          * Feel free to adjust to your needs.
5886          */
5887         if (pdev->broken_parity_status)
5888                 pci_cmd &= ~PCI_COMMAND_PARITY;
5889         else
5890                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5891
5892         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5893
5894         pci_write_config_word(pdev, PCI_STATUS,
5895                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5896                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5897                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5898
5899         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5900 }
5901
5902 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5903                    int budget)
5904 {
5905         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5906
5907         dirty_tx = tp->dirty_tx;
5908         smp_rmb();
5909         tx_left = tp->cur_tx - dirty_tx;
5910
5911         while (tx_left > 0) {
5912                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5913                 struct ring_info *tx_skb = tp->tx_skb + entry;
5914                 u32 status;
5915
5916                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5917                 if (status & DescOwn)
5918                         break;
5919
5920                 /* This barrier is needed to keep us from reading
5921                  * any other fields out of the Tx descriptor until
5922                  * we know the status of DescOwn
5923                  */
5924                 dma_rmb();
5925
5926                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5927                                      tp->TxDescArray + entry);
5928                 if (tx_skb->skb) {
5929                         pkts_compl++;
5930                         bytes_compl += tx_skb->skb->len;
5931                         napi_consume_skb(tx_skb->skb, budget);
5932                         tx_skb->skb = NULL;
5933                 }
5934                 dirty_tx++;
5935                 tx_left--;
5936         }
5937
5938         if (tp->dirty_tx != dirty_tx) {
5939                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5940
5941                 u64_stats_update_begin(&tp->tx_stats.syncp);
5942                 tp->tx_stats.packets += pkts_compl;
5943                 tp->tx_stats.bytes += bytes_compl;
5944                 u64_stats_update_end(&tp->tx_stats.syncp);
5945
5946                 tp->dirty_tx = dirty_tx;
5947                 /* Sync with rtl8169_start_xmit:
5948                  * - publish dirty_tx ring index (write barrier)
5949                  * - refresh cur_tx ring index and queue status (read barrier)
5950                  * May the current thread miss the stopped queue condition,
5951                  * a racing xmit thread can only have a right view of the
5952                  * ring status.
5953                  */
5954                 smp_mb();
5955                 if (netif_queue_stopped(dev) &&
5956                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5957                         netif_wake_queue(dev);
5958                 }
5959                 /*
5960                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5961                  * too close. Let's kick an extra TxPoll request when a burst
5962                  * of start_xmit activity is detected (if it is not detected,
5963                  * it is slow enough). -- FR
5964                  */
5965                 if (tp->cur_tx != dirty_tx)
5966                         rtl8169_doorbell(tp);
5967         }
5968 }
5969
5970 static inline int rtl8169_fragmented_frame(u32 status)
5971 {
5972         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5973 }
5974
5975 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5976 {
5977         u32 status = opts1 & RxProtoMask;
5978
5979         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5980             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5981                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5982         else
5983                 skb_checksum_none_assert(skb);
5984 }
5985
5986 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5987 {
5988         unsigned int cur_rx, rx_left;
5989         unsigned int count;
5990
5991         cur_rx = tp->cur_rx;
5992
5993         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5994                 unsigned int entry = cur_rx % NUM_RX_DESC;
5995                 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
5996                 struct RxDesc *desc = tp->RxDescArray + entry;
5997                 u32 status;
5998
5999                 status = le32_to_cpu(desc->opts1);
6000                 if (status & DescOwn)
6001                         break;
6002
6003                 /* This barrier is needed to keep us from reading
6004                  * any other fields out of the Rx descriptor until
6005                  * we know the status of DescOwn
6006                  */
6007                 dma_rmb();
6008
6009                 if (unlikely(status & RxRES)) {
6010                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6011                                    status);
6012                         dev->stats.rx_errors++;
6013                         if (status & (RxRWT | RxRUNT))
6014                                 dev->stats.rx_length_errors++;
6015                         if (status & RxCRC)
6016                                 dev->stats.rx_crc_errors++;
6017                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6018                             dev->features & NETIF_F_RXALL) {
6019                                 goto process_pkt;
6020                         }
6021                 } else {
6022                         unsigned int pkt_size;
6023                         struct sk_buff *skb;
6024
6025 process_pkt:
6026                         pkt_size = status & GENMASK(13, 0);
6027                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6028                                 pkt_size -= ETH_FCS_LEN;
6029                         /*
6030                          * The driver does not support incoming fragmented
6031                          * frames. They are seen as a symptom of over-mtu
6032                          * sized frames.
6033                          */
6034                         if (unlikely(rtl8169_fragmented_frame(status))) {
6035                                 dev->stats.rx_dropped++;
6036                                 dev->stats.rx_length_errors++;
6037                                 goto release_descriptor;
6038                         }
6039
6040                         skb = napi_alloc_skb(&tp->napi, pkt_size);
6041                         if (unlikely(!skb)) {
6042                                 dev->stats.rx_dropped++;
6043                                 goto release_descriptor;
6044                         }
6045
6046                         dma_sync_single_for_cpu(tp_to_dev(tp),
6047                                                 le64_to_cpu(desc->addr),
6048                                                 pkt_size, DMA_FROM_DEVICE);
6049                         prefetch(rx_buf);
6050                         skb_copy_to_linear_data(skb, rx_buf, pkt_size);
6051                         skb->tail += pkt_size;
6052                         skb->len = pkt_size;
6053
6054                         dma_sync_single_for_device(tp_to_dev(tp),
6055                                                    le64_to_cpu(desc->addr),
6056                                                    pkt_size, DMA_FROM_DEVICE);
6057
6058                         rtl8169_rx_csum(skb, status);
6059                         skb->protocol = eth_type_trans(skb, dev);
6060
6061                         rtl8169_rx_vlan_tag(desc, skb);
6062
6063                         if (skb->pkt_type == PACKET_MULTICAST)
6064                                 dev->stats.multicast++;
6065
6066                         napi_gro_receive(&tp->napi, skb);
6067
6068                         u64_stats_update_begin(&tp->rx_stats.syncp);
6069                         tp->rx_stats.packets++;
6070                         tp->rx_stats.bytes += pkt_size;
6071                         u64_stats_update_end(&tp->rx_stats.syncp);
6072                 }
6073 release_descriptor:
6074                 desc->opts2 = 0;
6075                 rtl8169_mark_to_asic(desc);
6076         }
6077
6078         count = cur_rx - tp->cur_rx;
6079         tp->cur_rx = cur_rx;
6080
6081         return count;
6082 }
6083
6084 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6085 {
6086         struct rtl8169_private *tp = dev_instance;
6087         u32 status = rtl_get_events(tp);
6088
6089         if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6090             !(status & tp->irq_mask))
6091                 return IRQ_NONE;
6092
6093         if (unlikely(status & SYSErr)) {
6094                 rtl8169_pcierr_interrupt(tp->dev);
6095                 goto out;
6096         }
6097
6098         if (status & LinkChg)
6099                 phy_mac_interrupt(tp->phydev);
6100
6101         if (unlikely(status & RxFIFOOver &&
6102             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6103                 netif_stop_queue(tp->dev);
6104                 /* XXX - Hack alert. See rtl_task(). */
6105                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6106         }
6107
6108         rtl_irq_disable(tp);
6109         napi_schedule_irqoff(&tp->napi);
6110 out:
6111         rtl_ack_events(tp, status);
6112
6113         return IRQ_HANDLED;
6114 }
6115
6116 static void rtl_task(struct work_struct *work)
6117 {
6118         static const struct {
6119                 int bitnr;
6120                 void (*action)(struct rtl8169_private *);
6121         } rtl_work[] = {
6122                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6123         };
6124         struct rtl8169_private *tp =
6125                 container_of(work, struct rtl8169_private, wk.work);
6126         struct net_device *dev = tp->dev;
6127         int i;
6128
6129         rtl_lock_work(tp);
6130
6131         if (!netif_running(dev) ||
6132             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6133                 goto out_unlock;
6134
6135         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6136                 bool pending;
6137
6138                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6139                 if (pending)
6140                         rtl_work[i].action(tp);
6141         }
6142
6143 out_unlock:
6144         rtl_unlock_work(tp);
6145 }
6146
6147 static int rtl8169_poll(struct napi_struct *napi, int budget)
6148 {
6149         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6150         struct net_device *dev = tp->dev;
6151         int work_done;
6152
6153         work_done = rtl_rx(dev, tp, (u32) budget);
6154
6155         rtl_tx(dev, tp, budget);
6156
6157         if (work_done < budget) {
6158                 napi_complete_done(napi, work_done);
6159                 rtl_irq_enable(tp);
6160         }
6161
6162         return work_done;
6163 }
6164
6165 static void rtl8169_rx_missed(struct net_device *dev)
6166 {
6167         struct rtl8169_private *tp = netdev_priv(dev);
6168
6169         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6170                 return;
6171
6172         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6173         RTL_W32(tp, RxMissed, 0);
6174 }
6175
6176 static void r8169_phylink_handler(struct net_device *ndev)
6177 {
6178         struct rtl8169_private *tp = netdev_priv(ndev);
6179
6180         if (netif_carrier_ok(ndev)) {
6181                 rtl_link_chg_patch(tp);
6182                 pm_request_resume(&tp->pci_dev->dev);
6183         } else {
6184                 pm_runtime_idle(&tp->pci_dev->dev);
6185         }
6186
6187         if (net_ratelimit())
6188                 phy_print_status(tp->phydev);
6189 }
6190
6191 static int r8169_phy_connect(struct rtl8169_private *tp)
6192 {
6193         struct phy_device *phydev = tp->phydev;
6194         phy_interface_t phy_mode;
6195         int ret;
6196
6197         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6198                    PHY_INTERFACE_MODE_MII;
6199
6200         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6201                                  phy_mode);
6202         if (ret)
6203                 return ret;
6204
6205         if (!tp->supports_gmii)
6206                 phy_set_max_speed(phydev, SPEED_100);
6207
6208         phy_support_asym_pause(phydev);
6209
6210         phy_attached_info(phydev);
6211
6212         return 0;
6213 }
6214
6215 static void rtl8169_down(struct net_device *dev)
6216 {
6217         struct rtl8169_private *tp = netdev_priv(dev);
6218
6219         phy_stop(tp->phydev);
6220
6221         napi_disable(&tp->napi);
6222         netif_stop_queue(dev);
6223
6224         rtl8169_hw_reset(tp);
6225         /*
6226          * At this point device interrupts can not be enabled in any function,
6227          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6228          * and napi is disabled (rtl8169_poll).
6229          */
6230         rtl8169_rx_missed(dev);
6231
6232         /* Give a racing hard_start_xmit a few cycles to complete. */
6233         synchronize_rcu();
6234
6235         rtl8169_tx_clear(tp);
6236
6237         rtl8169_rx_clear(tp);
6238
6239         rtl_pll_power_down(tp);
6240 }
6241
6242 static int rtl8169_close(struct net_device *dev)
6243 {
6244         struct rtl8169_private *tp = netdev_priv(dev);
6245         struct pci_dev *pdev = tp->pci_dev;
6246
6247         pm_runtime_get_sync(&pdev->dev);
6248
6249         /* Update counters before going down */
6250         rtl8169_update_counters(tp);
6251
6252         rtl_lock_work(tp);
6253         /* Clear all task flags */
6254         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6255
6256         rtl8169_down(dev);
6257         rtl_unlock_work(tp);
6258
6259         cancel_work_sync(&tp->wk.work);
6260
6261         phy_disconnect(tp->phydev);
6262
6263         pci_free_irq(pdev, 0, tp);
6264
6265         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6266                           tp->RxPhyAddr);
6267         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6268                           tp->TxPhyAddr);
6269         tp->TxDescArray = NULL;
6270         tp->RxDescArray = NULL;
6271
6272         pm_runtime_put_sync(&pdev->dev);
6273
6274         return 0;
6275 }
6276
6277 #ifdef CONFIG_NET_POLL_CONTROLLER
6278 static void rtl8169_netpoll(struct net_device *dev)
6279 {
6280         struct rtl8169_private *tp = netdev_priv(dev);
6281
6282         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6283 }
6284 #endif
6285
6286 static int rtl_open(struct net_device *dev)
6287 {
6288         struct rtl8169_private *tp = netdev_priv(dev);
6289         struct pci_dev *pdev = tp->pci_dev;
6290         int retval = -ENOMEM;
6291
6292         pm_runtime_get_sync(&pdev->dev);
6293
6294         /*
6295          * Rx and Tx descriptors needs 256 bytes alignment.
6296          * dma_alloc_coherent provides more.
6297          */
6298         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6299                                              &tp->TxPhyAddr, GFP_KERNEL);
6300         if (!tp->TxDescArray)
6301                 goto err_pm_runtime_put;
6302
6303         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6304                                              &tp->RxPhyAddr, GFP_KERNEL);
6305         if (!tp->RxDescArray)
6306                 goto err_free_tx_0;
6307
6308         retval = rtl8169_init_ring(tp);
6309         if (retval < 0)
6310                 goto err_free_rx_1;
6311
6312         rtl_request_firmware(tp);
6313
6314         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6315                                  dev->name);
6316         if (retval < 0)
6317                 goto err_release_fw_2;
6318
6319         retval = r8169_phy_connect(tp);
6320         if (retval)
6321                 goto err_free_irq;
6322
6323         rtl_lock_work(tp);
6324
6325         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6326
6327         napi_enable(&tp->napi);
6328
6329         rtl8169_init_phy(dev, tp);
6330
6331         rtl_pll_power_up(tp);
6332
6333         rtl_hw_start(tp);
6334
6335         if (!rtl8169_init_counter_offsets(tp))
6336                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6337
6338         phy_start(tp->phydev);
6339         netif_start_queue(dev);
6340
6341         rtl_unlock_work(tp);
6342
6343         pm_runtime_put_sync(&pdev->dev);
6344 out:
6345         return retval;
6346
6347 err_free_irq:
6348         pci_free_irq(pdev, 0, tp);
6349 err_release_fw_2:
6350         rtl_release_firmware(tp);
6351         rtl8169_rx_clear(tp);
6352 err_free_rx_1:
6353         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6354                           tp->RxPhyAddr);
6355         tp->RxDescArray = NULL;
6356 err_free_tx_0:
6357         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6358                           tp->TxPhyAddr);
6359         tp->TxDescArray = NULL;
6360 err_pm_runtime_put:
6361         pm_runtime_put_noidle(&pdev->dev);
6362         goto out;
6363 }
6364
6365 static void
6366 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6367 {
6368         struct rtl8169_private *tp = netdev_priv(dev);
6369         struct pci_dev *pdev = tp->pci_dev;
6370         struct rtl8169_counters *counters = tp->counters;
6371         unsigned int start;
6372
6373         pm_runtime_get_noresume(&pdev->dev);
6374
6375         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6376                 rtl8169_rx_missed(dev);
6377
6378         do {
6379                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6380                 stats->rx_packets = tp->rx_stats.packets;
6381                 stats->rx_bytes = tp->rx_stats.bytes;
6382         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6383
6384         do {
6385                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6386                 stats->tx_packets = tp->tx_stats.packets;
6387                 stats->tx_bytes = tp->tx_stats.bytes;
6388         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6389
6390         stats->rx_dropped       = dev->stats.rx_dropped;
6391         stats->tx_dropped       = dev->stats.tx_dropped;
6392         stats->rx_length_errors = dev->stats.rx_length_errors;
6393         stats->rx_errors        = dev->stats.rx_errors;
6394         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6395         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6396         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6397         stats->multicast        = dev->stats.multicast;
6398
6399         /*
6400          * Fetch additional counter values missing in stats collected by driver
6401          * from tally counters.
6402          */
6403         if (pm_runtime_active(&pdev->dev))
6404                 rtl8169_update_counters(tp);
6405
6406         /*
6407          * Subtract values fetched during initalization.
6408          * See rtl8169_init_counter_offsets for a description why we do that.
6409          */
6410         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6411                 le64_to_cpu(tp->tc_offset.tx_errors);
6412         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6413                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6414         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6415                 le16_to_cpu(tp->tc_offset.tx_aborted);
6416
6417         pm_runtime_put_noidle(&pdev->dev);
6418 }
6419
6420 static void rtl8169_net_suspend(struct net_device *dev)
6421 {
6422         struct rtl8169_private *tp = netdev_priv(dev);
6423
6424         if (!netif_running(dev))
6425                 return;
6426
6427         phy_stop(tp->phydev);
6428         netif_device_detach(dev);
6429
6430         rtl_lock_work(tp);
6431         napi_disable(&tp->napi);
6432         /* Clear all task flags */
6433         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6434
6435         rtl_unlock_work(tp);
6436
6437         rtl_pll_power_down(tp);
6438 }
6439
6440 #ifdef CONFIG_PM
6441
6442 static int rtl8169_suspend(struct device *device)
6443 {
6444         struct net_device *dev = dev_get_drvdata(device);
6445         struct rtl8169_private *tp = netdev_priv(dev);
6446
6447         rtl8169_net_suspend(dev);
6448         clk_disable_unprepare(tp->clk);
6449
6450         return 0;
6451 }
6452
6453 static void __rtl8169_resume(struct net_device *dev)
6454 {
6455         struct rtl8169_private *tp = netdev_priv(dev);
6456
6457         netif_device_attach(dev);
6458
6459         rtl_pll_power_up(tp);
6460         rtl8169_init_phy(dev, tp);
6461
6462         phy_start(tp->phydev);
6463
6464         rtl_lock_work(tp);
6465         napi_enable(&tp->napi);
6466         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6467         rtl_reset_work(tp);
6468         rtl_unlock_work(tp);
6469 }
6470
6471 static int rtl8169_resume(struct device *device)
6472 {
6473         struct net_device *dev = dev_get_drvdata(device);
6474         struct rtl8169_private *tp = netdev_priv(dev);
6475
6476         rtl_rar_set(tp, dev->dev_addr);
6477
6478         clk_prepare_enable(tp->clk);
6479
6480         if (netif_running(dev))
6481                 __rtl8169_resume(dev);
6482
6483         return 0;
6484 }
6485
6486 static int rtl8169_runtime_suspend(struct device *device)
6487 {
6488         struct net_device *dev = dev_get_drvdata(device);
6489         struct rtl8169_private *tp = netdev_priv(dev);
6490
6491         if (!tp->TxDescArray)
6492                 return 0;
6493
6494         rtl_lock_work(tp);
6495         __rtl8169_set_wol(tp, WAKE_ANY);
6496         rtl_unlock_work(tp);
6497
6498         rtl8169_net_suspend(dev);
6499
6500         /* Update counters before going runtime suspend */
6501         rtl8169_rx_missed(dev);
6502         rtl8169_update_counters(tp);
6503
6504         return 0;
6505 }
6506
6507 static int rtl8169_runtime_resume(struct device *device)
6508 {
6509         struct net_device *dev = dev_get_drvdata(device);
6510         struct rtl8169_private *tp = netdev_priv(dev);
6511
6512         rtl_rar_set(tp, dev->dev_addr);
6513
6514         if (!tp->TxDescArray)
6515                 return 0;
6516
6517         rtl_lock_work(tp);
6518         __rtl8169_set_wol(tp, tp->saved_wolopts);
6519         rtl_unlock_work(tp);
6520
6521         __rtl8169_resume(dev);
6522
6523         return 0;
6524 }
6525
6526 static int rtl8169_runtime_idle(struct device *device)
6527 {
6528         struct net_device *dev = dev_get_drvdata(device);
6529
6530         if (!netif_running(dev) || !netif_carrier_ok(dev))
6531                 pm_schedule_suspend(device, 10000);
6532
6533         return -EBUSY;
6534 }
6535
6536 static const struct dev_pm_ops rtl8169_pm_ops = {
6537         .suspend                = rtl8169_suspend,
6538         .resume                 = rtl8169_resume,
6539         .freeze                 = rtl8169_suspend,
6540         .thaw                   = rtl8169_resume,
6541         .poweroff               = rtl8169_suspend,
6542         .restore                = rtl8169_resume,
6543         .runtime_suspend        = rtl8169_runtime_suspend,
6544         .runtime_resume         = rtl8169_runtime_resume,
6545         .runtime_idle           = rtl8169_runtime_idle,
6546 };
6547
6548 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6549
6550 #else /* !CONFIG_PM */
6551
6552 #define RTL8169_PM_OPS  NULL
6553
6554 #endif /* !CONFIG_PM */
6555
6556 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6557 {
6558         /* WoL fails with 8168b when the receiver is disabled. */
6559         switch (tp->mac_version) {
6560         case RTL_GIGA_MAC_VER_11:
6561         case RTL_GIGA_MAC_VER_12:
6562         case RTL_GIGA_MAC_VER_17:
6563                 pci_clear_master(tp->pci_dev);
6564
6565                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6566                 /* PCI commit */
6567                 RTL_R8(tp, ChipCmd);
6568                 break;
6569         default:
6570                 break;
6571         }
6572 }
6573
6574 static void rtl_shutdown(struct pci_dev *pdev)
6575 {
6576         struct net_device *dev = pci_get_drvdata(pdev);
6577         struct rtl8169_private *tp = netdev_priv(dev);
6578
6579         rtl8169_net_suspend(dev);
6580
6581         /* Restore original MAC address */
6582         rtl_rar_set(tp, dev->perm_addr);
6583
6584         rtl8169_hw_reset(tp);
6585
6586         if (system_state == SYSTEM_POWER_OFF) {
6587                 if (tp->saved_wolopts) {
6588                         rtl_wol_suspend_quirk(tp);
6589                         rtl_wol_shutdown_quirk(tp);
6590                 }
6591
6592                 pci_wake_from_d3(pdev, true);
6593                 pci_set_power_state(pdev, PCI_D3hot);
6594         }
6595 }
6596
6597 static void rtl_remove_one(struct pci_dev *pdev)
6598 {
6599         struct net_device *dev = pci_get_drvdata(pdev);
6600         struct rtl8169_private *tp = netdev_priv(dev);
6601
6602         if (r8168_check_dash(tp))
6603                 rtl8168_driver_stop(tp);
6604
6605         netif_napi_del(&tp->napi);
6606
6607         unregister_netdev(dev);
6608         mdiobus_unregister(tp->phydev->mdio.bus);
6609
6610         rtl_release_firmware(tp);
6611
6612         if (pci_dev_run_wake(pdev))
6613                 pm_runtime_get_noresume(&pdev->dev);
6614
6615         /* restore original MAC address */
6616         rtl_rar_set(tp, dev->perm_addr);
6617 }
6618
6619 static const struct net_device_ops rtl_netdev_ops = {
6620         .ndo_open               = rtl_open,
6621         .ndo_stop               = rtl8169_close,
6622         .ndo_get_stats64        = rtl8169_get_stats64,
6623         .ndo_start_xmit         = rtl8169_start_xmit,
6624         .ndo_features_check     = rtl8169_features_check,
6625         .ndo_tx_timeout         = rtl8169_tx_timeout,
6626         .ndo_validate_addr      = eth_validate_addr,
6627         .ndo_change_mtu         = rtl8169_change_mtu,
6628         .ndo_fix_features       = rtl8169_fix_features,
6629         .ndo_set_features       = rtl8169_set_features,
6630         .ndo_set_mac_address    = rtl_set_mac_address,
6631         .ndo_do_ioctl           = rtl8169_ioctl,
6632         .ndo_set_rx_mode        = rtl_set_rx_mode,
6633 #ifdef CONFIG_NET_POLL_CONTROLLER
6634         .ndo_poll_controller    = rtl8169_netpoll,
6635 #endif
6636
6637 };
6638
6639 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6640 {
6641         tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6642
6643         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6644                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6645         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6646                 /* special workaround needed */
6647                 tp->irq_mask |= RxFIFOOver;
6648         else
6649                 tp->irq_mask |= RxOverflow;
6650 }
6651
6652 static int rtl_alloc_irq(struct rtl8169_private *tp)
6653 {
6654         unsigned int flags;
6655
6656         switch (tp->mac_version) {
6657         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6658                 rtl_unlock_config_regs(tp);
6659                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6660                 rtl_lock_config_regs(tp);
6661                 /* fall through */
6662         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6663                 flags = PCI_IRQ_LEGACY;
6664                 break;
6665         default:
6666                 flags = PCI_IRQ_ALL_TYPES;
6667                 break;
6668         }
6669
6670         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6671 }
6672
6673 static void rtl_read_mac_address(struct rtl8169_private *tp,
6674                                  u8 mac_addr[ETH_ALEN])
6675 {
6676         /* Get MAC address */
6677         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6678                 u32 value = rtl_eri_read(tp, 0xe0);
6679
6680                 mac_addr[0] = (value >>  0) & 0xff;
6681                 mac_addr[1] = (value >>  8) & 0xff;
6682                 mac_addr[2] = (value >> 16) & 0xff;
6683                 mac_addr[3] = (value >> 24) & 0xff;
6684
6685                 value = rtl_eri_read(tp, 0xe4);
6686                 mac_addr[4] = (value >>  0) & 0xff;
6687                 mac_addr[5] = (value >>  8) & 0xff;
6688         } else if (rtl_is_8125(tp)) {
6689                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
6690         }
6691 }
6692
6693 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6694 {
6695         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6696 }
6697
6698 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6699 {
6700         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6701 }
6702
6703 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6704 {
6705         struct rtl8169_private *tp = mii_bus->priv;
6706
6707         if (phyaddr > 0)
6708                 return -ENODEV;
6709
6710         return rtl_readphy(tp, phyreg);
6711 }
6712
6713 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6714                                 int phyreg, u16 val)
6715 {
6716         struct rtl8169_private *tp = mii_bus->priv;
6717
6718         if (phyaddr > 0)
6719                 return -ENODEV;
6720
6721         rtl_writephy(tp, phyreg, val);
6722
6723         return 0;
6724 }
6725
6726 static int r8169_mdio_register(struct rtl8169_private *tp)
6727 {
6728         struct pci_dev *pdev = tp->pci_dev;
6729         struct mii_bus *new_bus;
6730         int ret;
6731
6732         new_bus = devm_mdiobus_alloc(&pdev->dev);
6733         if (!new_bus)
6734                 return -ENOMEM;
6735
6736         new_bus->name = "r8169";
6737         new_bus->priv = tp;
6738         new_bus->parent = &pdev->dev;
6739         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6740         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6741
6742         new_bus->read = r8169_mdio_read_reg;
6743         new_bus->write = r8169_mdio_write_reg;
6744
6745         ret = mdiobus_register(new_bus);
6746         if (ret)
6747                 return ret;
6748
6749         tp->phydev = mdiobus_get_phy(new_bus, 0);
6750         if (!tp->phydev) {
6751                 mdiobus_unregister(new_bus);
6752                 return -ENODEV;
6753         }
6754
6755         /* PHY will be woken up in rtl_open() */
6756         phy_suspend(tp->phydev);
6757
6758         return 0;
6759 }
6760
6761 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6762 {
6763         tp->ocp_base = OCP_STD_PHY_BASE;
6764
6765         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6766
6767         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6768                 return;
6769
6770         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6771                 return;
6772
6773         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6774         msleep(1);
6775         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6776
6777         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6778
6779         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6780                 return;
6781
6782         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6783
6784         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6785 }
6786
6787 static void rtl_hw_init_8125(struct rtl8169_private *tp)
6788 {
6789         tp->ocp_base = OCP_STD_PHY_BASE;
6790
6791         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6792
6793         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6794                 return;
6795
6796         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6797         msleep(1);
6798         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6799
6800         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6801
6802         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6803                 return;
6804
6805         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6806         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6807         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6808
6809         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6810 }
6811
6812 static void rtl_hw_initialize(struct rtl8169_private *tp)
6813 {
6814         switch (tp->mac_version) {
6815         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6816                 rtl8168ep_stop_cmac(tp);
6817                 /* fall through */
6818         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6819                 rtl_hw_init_8168g(tp);
6820                 break;
6821         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6822                 rtl_hw_init_8125(tp);
6823                 break;
6824         default:
6825                 break;
6826         }
6827 }
6828
6829 static int rtl_jumbo_max(struct rtl8169_private *tp)
6830 {
6831         /* Non-GBit versions don't support jumbo frames */
6832         if (!tp->supports_gmii)
6833                 return JUMBO_1K;
6834
6835         switch (tp->mac_version) {
6836         /* RTL8169 */
6837         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6838                 return JUMBO_7K;
6839         /* RTL8168b */
6840         case RTL_GIGA_MAC_VER_11:
6841         case RTL_GIGA_MAC_VER_12:
6842         case RTL_GIGA_MAC_VER_17:
6843                 return JUMBO_4K;
6844         /* RTL8168c */
6845         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6846                 return JUMBO_6K;
6847         default:
6848                 return JUMBO_9K;
6849         }
6850 }
6851
6852 static void rtl_disable_clk(void *data)
6853 {
6854         clk_disable_unprepare(data);
6855 }
6856
6857 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6858 {
6859         struct device *d = tp_to_dev(tp);
6860         struct clk *clk;
6861         int rc;
6862
6863         clk = devm_clk_get(d, "ether_clk");
6864         if (IS_ERR(clk)) {
6865                 rc = PTR_ERR(clk);
6866                 if (rc == -ENOENT)
6867                         /* clk-core allows NULL (for suspend / resume) */
6868                         rc = 0;
6869                 else if (rc != -EPROBE_DEFER)
6870                         dev_err(d, "failed to get clk: %d\n", rc);
6871         } else {
6872                 tp->clk = clk;
6873                 rc = clk_prepare_enable(clk);
6874                 if (rc)
6875                         dev_err(d, "failed to enable clk: %d\n", rc);
6876                 else
6877                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6878         }
6879
6880         return rc;
6881 }
6882
6883 static void rtl_init_mac_address(struct rtl8169_private *tp)
6884 {
6885         struct net_device *dev = tp->dev;
6886         u8 *mac_addr = dev->dev_addr;
6887         int rc;
6888
6889         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6890         if (!rc)
6891                 goto done;
6892
6893         rtl_read_mac_address(tp, mac_addr);
6894         if (is_valid_ether_addr(mac_addr))
6895                 goto done;
6896
6897         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
6898         if (is_valid_ether_addr(mac_addr))
6899                 goto done;
6900
6901         eth_hw_addr_random(dev);
6902         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6903 done:
6904         rtl_rar_set(tp, mac_addr);
6905 }
6906
6907 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6908 {
6909         struct rtl8169_private *tp;
6910         struct net_device *dev;
6911         int chipset, region;
6912         int jumbo_max, rc;
6913
6914         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6915         if (!dev)
6916                 return -ENOMEM;
6917
6918         SET_NETDEV_DEV(dev, &pdev->dev);
6919         dev->netdev_ops = &rtl_netdev_ops;
6920         tp = netdev_priv(dev);
6921         tp->dev = dev;
6922         tp->pci_dev = pdev;
6923         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6924         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6925
6926         /* Get the *optional* external "ether_clk" used on some boards */
6927         rc = rtl_get_ether_clk(tp);
6928         if (rc)
6929                 return rc;
6930
6931         /* Disable ASPM completely as that cause random device stop working
6932          * problems as well as full system hangs for some PCIe devices users.
6933          */
6934         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6935                                           PCIE_LINK_STATE_L1);
6936         tp->aspm_manageable = !rc;
6937
6938         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6939         rc = pcim_enable_device(pdev);
6940         if (rc < 0) {
6941                 dev_err(&pdev->dev, "enable failure\n");
6942                 return rc;
6943         }
6944
6945         if (pcim_set_mwi(pdev) < 0)
6946                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6947
6948         /* use first MMIO region */
6949         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6950         if (region < 0) {
6951                 dev_err(&pdev->dev, "no MMIO resource found\n");
6952                 return -ENODEV;
6953         }
6954
6955         /* check for weird/broken PCI region reporting */
6956         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6957                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6958                 return -ENODEV;
6959         }
6960
6961         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6962         if (rc < 0) {
6963                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6964                 return rc;
6965         }
6966
6967         tp->mmio_addr = pcim_iomap_table(pdev)[region];
6968
6969         /* Identify chip attached to board */
6970         rtl8169_get_mac_version(tp);
6971         if (tp->mac_version == RTL_GIGA_MAC_NONE)
6972                 return -ENODEV;
6973
6974         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6975
6976         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6977             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6978                 dev->features |= NETIF_F_HIGHDMA;
6979
6980         rtl_init_rxcfg(tp);
6981
6982         rtl8169_irq_mask_and_ack(tp);
6983
6984         rtl_hw_initialize(tp);
6985
6986         rtl_hw_reset(tp);
6987
6988         pci_set_master(pdev);
6989
6990         chipset = tp->mac_version;
6991
6992         rc = rtl_alloc_irq(tp);
6993         if (rc < 0) {
6994                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6995                 return rc;
6996         }
6997
6998         mutex_init(&tp->wk.mutex);
6999         INIT_WORK(&tp->wk.work, rtl_task);
7000         u64_stats_init(&tp->rx_stats.syncp);
7001         u64_stats_init(&tp->tx_stats.syncp);
7002
7003         rtl_init_mac_address(tp);
7004
7005         dev->ethtool_ops = &rtl8169_ethtool_ops;
7006
7007         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7008
7009         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7010                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7011                 NETIF_F_HW_VLAN_CTAG_RX;
7012         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7013                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7014                 NETIF_F_HW_VLAN_CTAG_RX;
7015         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7016                 NETIF_F_HIGHDMA;
7017         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7018
7019         tp->cp_cmd |= RxChkSum | RxVlan;
7020
7021         /*
7022          * Pretend we are using VLANs; This bypasses a nasty bug where
7023          * Interrupts stop flowing on high load on 8110SCd controllers.
7024          */
7025         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7026                 /* Disallow toggling */
7027                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7028
7029         if (rtl_chip_supports_csum_v2(tp)) {
7030                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7031                 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7032                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7033                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7034         } else {
7035                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7036                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7037         }
7038
7039         /* RTL8168e-vl has a HW issue with TSO */
7040         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
7041                 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7042                 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7043                 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
7044         }
7045
7046         dev->hw_features |= NETIF_F_RXALL;
7047         dev->hw_features |= NETIF_F_RXFCS;
7048
7049         /* MTU range: 60 - hw-specific max */
7050         dev->min_mtu = ETH_ZLEN;
7051         jumbo_max = rtl_jumbo_max(tp);
7052         dev->max_mtu = jumbo_max;
7053
7054         rtl_set_irq_mask(tp);
7055
7056         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7057
7058         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7059                                             &tp->counters_phys_addr,
7060                                             GFP_KERNEL);
7061         if (!tp->counters)
7062                 return -ENOMEM;
7063
7064         pci_set_drvdata(pdev, dev);
7065
7066         rc = r8169_mdio_register(tp);
7067         if (rc)
7068                 return rc;
7069
7070         /* chip gets powered up in rtl_open() */
7071         rtl_pll_power_down(tp);
7072
7073         rc = register_netdev(dev);
7074         if (rc)
7075                 goto err_mdio_unregister;
7076
7077         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7078                    rtl_chip_infos[chipset].name, dev->dev_addr,
7079                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7080                    pci_irq_vector(pdev, 0));
7081
7082         if (jumbo_max > JUMBO_1K)
7083                 netif_info(tp, probe, dev,
7084                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7085                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7086                            "ok" : "ko");
7087
7088         if (r8168_check_dash(tp))
7089                 rtl8168_driver_start(tp);
7090
7091         if (pci_dev_run_wake(pdev))
7092                 pm_runtime_put_sync(&pdev->dev);
7093
7094         return 0;
7095
7096 err_mdio_unregister:
7097         mdiobus_unregister(tp->phydev->mdio.bus);
7098         return rc;
7099 }
7100
7101 static struct pci_driver rtl8169_pci_driver = {
7102         .name           = MODULENAME,
7103         .id_table       = rtl8169_pci_tbl,
7104         .probe          = rtl_init_one,
7105         .remove         = rtl_remove_one,
7106         .shutdown       = rtl_shutdown,
7107         .driver.pm      = RTL8169_PM_OPS,
7108 };
7109
7110 module_pci_driver(rtl8169_pci_driver);