drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <asm/unaligned.h>
  32 #include <net/ip6_checksum.h>
  33 #include <net/netdev_queues.h>
  34
  35 #include "r8169.h"
  36 #include "r8169_firmware.h"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  57 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 #define MC_FILTER_LIMIT 32
  62
  63 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  64 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  65
  66 #define R8169_REGS_SIZE         256
  67 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  68 #define NUM_TX_DESC     256     /* Number of Tx descriptor registers */
  69 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  70 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  71 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  72 #define R8169_TX_STOP_THRS      (MAX_SKB_FRAGS + 1)
  73 #define R8169_TX_START_THRS     (2 * R8169_TX_STOP_THRS)
  74
  75 #define OCP_STD_PHY_BASE        0xa400
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92 static const struct {
  93         const char *name;
  94         const char *fw_name;
  95 } rtl_chip_infos[] = {
  96         /* PCI devices. */
  97         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102         /* PCI-E devices. */
 103         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106         [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"                    },
 107         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 109         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 110         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 111         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 112         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 113         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 114         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 116         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 117         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 118         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 119         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 120         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 121         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 122         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 124         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 125         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 126         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 127         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 128         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 129         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 130         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 131         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 132         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 133         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 134         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 135         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 136         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 137         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 138         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 139         [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",                   },
 140         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 141         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 142         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 143 };
 144
 145 static const struct pci_device_id rtl8169_pci_tbl[] = {
 146         { PCI_VDEVICE(REALTEK,  0x2502) },
 147         { PCI_VDEVICE(REALTEK,  0x2600) },
 148         { PCI_VDEVICE(REALTEK,  0x8129) },
 149         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 150         { PCI_VDEVICE(REALTEK,  0x8161) },
 151         { PCI_VDEVICE(REALTEK,  0x8162) },
 152         { PCI_VDEVICE(REALTEK,  0x8167) },
 153         { PCI_VDEVICE(REALTEK,  0x8168) },
 154         { PCI_VDEVICE(NCUBE,    0x8168) },
 155         { PCI_VDEVICE(REALTEK,  0x8169) },
 156         { PCI_VENDOR_ID_DLINK,  0x4300,
 157                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 158         { PCI_VDEVICE(DLINK,    0x4300) },
 159         { PCI_VDEVICE(DLINK,    0x4302) },
 160         { PCI_VDEVICE(AT,       0xc107) },
 161         { PCI_VDEVICE(USR,      0x0116) },
 162         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 163         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 164         { PCI_VDEVICE(REALTEK,  0x8125) },
 165         { PCI_VDEVICE(REALTEK,  0x3000) },
 166         {}
 167 };
 168
 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 170
 171 enum rtl_registers {
 172         MAC0            = 0,    /* Ethernet hardware address. */
 173         MAC4            = 4,
 174         MAR0            = 8,    /* Multicast filter. */
 175         CounterAddrLow          = 0x10,
 176         CounterAddrHigh         = 0x14,
 177         TxDescStartAddrLow      = 0x20,
 178         TxDescStartAddrHigh     = 0x24,
 179         TxHDescStartAddrLow     = 0x28,
 180         TxHDescStartAddrHigh    = 0x2c,
 181         FLASH           = 0x30,
 182         ERSR            = 0x36,
 183         ChipCmd         = 0x37,
 184         TxPoll          = 0x38,
 185         IntrMask        = 0x3c,
 186         IntrStatus      = 0x3e,
 187
 188         TxConfig        = 0x40,
 189 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 190 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 191
 192         RxConfig        = 0x44,
 193 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 194 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 195 #define RXCFG_FIFO_SHIFT                13
 196                                         /* No threshold before first PCI xfer */
 197 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 198 #define RX_EARLY_OFF                    (1 << 11)
 199 #define RXCFG_DMA_SHIFT                 8
 200                                         /* Unlimited maximum PCI burst. */
 201 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 202
 203         Cfg9346         = 0x50,
 204         Config0         = 0x51,
 205         Config1         = 0x52,
 206         Config2         = 0x53,
 207 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 208
 209         Config3         = 0x54,
 210         Config4         = 0x55,
 211         Config5         = 0x56,
 212         PHYAR           = 0x60,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217
 218 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 219 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 220 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 221 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 222
 223 #define RTL_COALESCE_T_MAX      0x0fU
 224 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 225
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 229
 230 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 231
 232         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 233
 234 #define TxPacketMax     (8064 >> 7)
 235 #define EarlySize       0x27
 236
 237         FuncEvent       = 0xf0,
 238         FuncEventMask   = 0xf4,
 239         FuncPresetState = 0xf8,
 240         IBCR0           = 0xf8,
 241         IBCR2           = 0xf9,
 242         IBIMR0          = 0xfa,
 243         IBISR0          = 0xfb,
 244         FuncForceEvent  = 0xfc,
 245 };
 246
 247 enum rtl8168_8101_registers {
 248         CSIDR                   = 0x64,
 249         CSIAR                   = 0x68,
 250 #define CSIAR_FLAG                      0x80000000
 251 #define CSIAR_WRITE_CMD                 0x80000000
 252 #define CSIAR_BYTE_ENABLE               0x0000f000
 253 #define CSIAR_ADDR_MASK                 0x00000fff
 254         PMCH                    = 0x6f,
 255 #define D3COLD_NO_PLL_DOWN              BIT(7)
 256 #define D3HOT_NO_PLL_DOWN               BIT(6)
 257 #define D3_NO_PLL_DOWN                  (BIT(7) | BIT(6))
 258         EPHYAR                  = 0x80,
 259 #define EPHYAR_FLAG                     0x80000000
 260 #define EPHYAR_WRITE_CMD                0x80000000
 261 #define EPHYAR_REG_MASK                 0x1f
 262 #define EPHYAR_REG_SHIFT                16
 263 #define EPHYAR_DATA_MASK                0xffff
 264         DLLPR                   = 0xd0,
 265 #define PFM_EN                          (1 << 6)
 266 #define TX_10M_PS_EN                    (1 << 7)
 267         DBG_REG                 = 0xd1,
 268 #define FIX_NAK_1                       (1 << 4)
 269 #define FIX_NAK_2                       (1 << 3)
 270         TWSI                    = 0xd2,
 271         MCU                     = 0xd3,
 272 #define NOW_IS_OOB                      (1 << 7)
 273 #define TX_EMPTY                        (1 << 5)
 274 #define RX_EMPTY                        (1 << 4)
 275 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 276 #define EN_NDP                          (1 << 3)
 277 #define EN_OOB_RESET                    (1 << 2)
 278 #define LINK_LIST_RDY                   (1 << 1)
 279         EFUSEAR                 = 0xdc,
 280 #define EFUSEAR_FLAG                    0x80000000
 281 #define EFUSEAR_WRITE_CMD               0x80000000
 282 #define EFUSEAR_READ_CMD                0x00000000
 283 #define EFUSEAR_REG_MASK                0x03ff
 284 #define EFUSEAR_REG_SHIFT               8
 285 #define EFUSEAR_DATA_MASK               0xff
 286         MISC_1                  = 0xf2,
 287 #define PFM_D3COLD_EN                   (1 << 6)
 288 };
 289
 290 enum rtl8168_registers {
 291         LED_FREQ                = 0x1a,
 292         EEE_LED                 = 0x1b,
 293         ERIDR                   = 0x70,
 294         ERIAR                   = 0x74,
 295 #define ERIAR_FLAG                      0x80000000
 296 #define ERIAR_WRITE_CMD                 0x80000000
 297 #define ERIAR_READ_CMD                  0x00000000
 298 #define ERIAR_ADDR_BYTE_ALIGN           4
 299 #define ERIAR_TYPE_SHIFT                16
 300 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 301 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 302 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 303 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 304 #define ERIAR_MASK_SHIFT                12
 305 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 306 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 307 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 308 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 309 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 310         EPHY_RXER_NUM           = 0x7c,
 311         OCPDR                   = 0xb0, /* OCP GPHY access */
 312 #define OCPDR_WRITE_CMD                 0x80000000
 313 #define OCPDR_READ_CMD                  0x00000000
 314 #define OCPDR_REG_MASK                  0x7f
 315 #define OCPDR_GPHY_REG_SHIFT            16
 316 #define OCPDR_DATA_MASK                 0xffff
 317         OCPAR                   = 0xb4,
 318 #define OCPAR_FLAG                      0x80000000
 319 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 320 #define OCPAR_GPHY_READ_CMD             0x0000f060
 321         GPHY_OCP                = 0xb8,
 322         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 323         MISC                    = 0xf0, /* 8168e only. */
 324 #define TXPLA_RST                       (1 << 29)
 325 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 326 #define PWM_EN                          (1 << 22)
 327 #define RXDV_GATED_EN                   (1 << 19)
 328 #define EARLY_TALLY_EN                  (1 << 16)
 329 };
 330
 331 enum rtl8125_registers {
 332         IntrMask_8125           = 0x38,
 333         IntrStatus_8125         = 0x3c,
 334         TxPoll_8125             = 0x90,
 335         MAC0_BKP                = 0x19e0,
 336         EEE_TXIDLE_TIMER_8125   = 0x6048,
 337 };
 338
 339 #define RX_VLAN_INNER_8125      BIT(22)
 340 #define RX_VLAN_OUTER_8125      BIT(23)
 341 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 342
 343 #define RX_FETCH_DFLT_8125      (8 << 27)
 344
 345 enum rtl_register_content {
 346         /* InterruptStatusBits */
 347         SYSErr          = 0x8000,
 348         PCSTimeout      = 0x4000,
 349         SWInt           = 0x0100,
 350         TxDescUnavail   = 0x0080,
 351         RxFIFOOver      = 0x0040,
 352         LinkChg         = 0x0020,
 353         RxOverflow      = 0x0010,
 354         TxErr           = 0x0008,
 355         TxOK            = 0x0004,
 356         RxErr           = 0x0002,
 357         RxOK            = 0x0001,
 358
 359         /* RxStatusDesc */
 360         RxRWT   = (1 << 22),
 361         RxRES   = (1 << 21),
 362         RxRUNT  = (1 << 20),
 363         RxCRC   = (1 << 19),
 364
 365         /* ChipCmdBits */
 366         StopReq         = 0x80,
 367         CmdReset        = 0x10,
 368         CmdRxEnb        = 0x08,
 369         CmdTxEnb        = 0x04,
 370         RxBufEmpty      = 0x01,
 371
 372         /* TXPoll register p.5 */
 373         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 374         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 375         FSWInt          = 0x01,         /* Forced software interrupt */
 376
 377         /* Cfg9346Bits */
 378         Cfg9346_Lock    = 0x00,
 379         Cfg9346_Unlock  = 0xc0,
 380
 381         /* rx_mode_bits */
 382         AcceptErr       = 0x20,
 383         AcceptRunt      = 0x10,
 384 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 385         AcceptBroadcast = 0x08,
 386         AcceptMulticast = 0x04,
 387         AcceptMyPhys    = 0x02,
 388         AcceptAllPhys   = 0x01,
 389 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 390 #define RX_CONFIG_ACCEPT_MASK           0x3f
 391
 392         /* TxConfigBits */
 393         TxInterFrameGapShift = 24,
 394         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 395
 396         /* Config1 register p.24 */
 397         LEDS1           = (1 << 7),
 398         LEDS0           = (1 << 6),
 399         Speed_down      = (1 << 4),
 400         MEMMAP          = (1 << 3),
 401         IOMAP           = (1 << 2),
 402         VPD             = (1 << 1),
 403         PMEnable        = (1 << 0),     /* Power Management Enable */
 404
 405         /* Config2 register p. 25 */
 406         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 407         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 408         PCI_Clock_66MHz = 0x01,
 409         PCI_Clock_33MHz = 0x00,
 410
 411         /* Config3 register p.25 */
 412         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 413         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 414         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 415         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 416         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 417
 418         /* Config4 register */
 419         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 420
 421         /* Config5 register p.27 */
 422         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 423         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 424         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 425         Spi_en          = (1 << 3),
 426         LanWake         = (1 << 1),     /* LanWake enable/disable */
 427         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 428         ASPM_en         = (1 << 0),     /* ASPM enable */
 429
 430         /* CPlusCmd p.31 */
 431         EnableBist      = (1 << 15),    // 8168 8101
 432         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 433         EnAnaPLL        = (1 << 14),    // 8169
 434         Normal_mode     = (1 << 13),    // unused
 435         Force_half_dup  = (1 << 12),    // 8168 8101
 436         Force_rxflow_en = (1 << 11),    // 8168 8101
 437         Force_txflow_en = (1 << 10),    // 8168 8101
 438         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 439         ASF             = (1 << 8),     // 8168 8101
 440         PktCntrDisable  = (1 << 7),     // 8168 8101
 441         Mac_dbgo_sel    = 0x001c,       // 8168
 442         RxVlan          = (1 << 6),
 443         RxChkSum        = (1 << 5),
 444         PCIDAC          = (1 << 4),
 445         PCIMulRW        = (1 << 3),
 446 #define INTT_MASK       GENMASK(1, 0)
 447 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 448
 449         /* rtl8169_PHYstatus */
 450         TBI_Enable      = 0x80,
 451         TxFlowCtrl      = 0x40,
 452         RxFlowCtrl      = 0x20,
 453         _1000bpsF       = 0x10,
 454         _100bps         = 0x08,
 455         _10bps          = 0x04,
 456         LinkStatus      = 0x02,
 457         FullDup         = 0x01,
 458
 459         /* ResetCounterCommand */
 460         CounterReset    = 0x1,
 461
 462         /* DumpCounterCommand */
 463         CounterDump     = 0x8,
 464
 465         /* magic enable v2 */
 466         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 467 };
 468
 469 enum rtl_desc_bit {
 470         /* First doubleword. */
 471         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 472         RingEnd         = (1 << 30), /* End of descriptor ring */
 473         FirstFrag       = (1 << 29), /* First segment of a packet */
 474         LastFrag        = (1 << 28), /* Final segment of a packet */
 475 };
 476
 477 /* Generic case. */
 478 enum rtl_tx_desc_bit {
 479         /* First doubleword. */
 480         TD_LSO          = (1 << 27),            /* Large Send Offload */
 481 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 482
 483         /* Second doubleword. */
 484         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 485 };
 486
 487 /* 8169, 8168b and 810x except 8102e. */
 488 enum rtl_tx_desc_bit_0 {
 489         /* First doubleword. */
 490 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 491         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 492         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 493         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 494 };
 495
 496 /* 8102e, 8168c and beyond. */
 497 enum rtl_tx_desc_bit_1 {
 498         /* First doubleword. */
 499         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 500         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 501 #define GTTCPHO_SHIFT                   18
 502 #define GTTCPHO_MAX                     0x7f
 503
 504         /* Second doubleword. */
 505 #define TCPHO_SHIFT                     18
 506 #define TCPHO_MAX                       0x3ff
 507 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 508         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 509         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 510         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 511         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 512 };
 513
 514 enum rtl_rx_desc_bit {
 515         /* Rx private */
 516         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 517         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 518
 519 #define RxProtoUDP      (PID1)
 520 #define RxProtoTCP      (PID0)
 521 #define RxProtoIP       (PID1 | PID0)
 522 #define RxProtoMask     RxProtoIP
 523
 524         IPFail          = (1 << 16), /* IP checksum failed */
 525         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 526         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 527
 528 #define RxCSFailMask    (IPFail | UDPFail | TCPFail)
 529
 530         RxVlanTag       = (1 << 16), /* VLAN tag available */
 531 };
 532
 533 #define RTL_GSO_MAX_SIZE_V1     32000
 534 #define RTL_GSO_MAX_SEGS_V1     24
 535 #define RTL_GSO_MAX_SIZE_V2     64000
 536 #define RTL_GSO_MAX_SEGS_V2     64
 537
 538 struct TxDesc {
 539         __le32 opts1;
 540         __le32 opts2;
 541         __le64 addr;
 542 };
 543
 544 struct RxDesc {
 545         __le32 opts1;
 546         __le32 opts2;
 547         __le64 addr;
 548 };
 549
 550 struct ring_info {
 551         struct sk_buff  *skb;
 552         u32             len;
 553 };
 554
 555 struct rtl8169_counters {
 556         __le64  tx_packets;
 557         __le64  rx_packets;
 558         __le64  tx_errors;
 559         __le32  rx_errors;
 560         __le16  rx_missed;
 561         __le16  align_errors;
 562         __le32  tx_one_collision;
 563         __le32  tx_multi_collision;
 564         __le64  rx_unicast;
 565         __le64  rx_broadcast;
 566         __le32  rx_multicast;
 567         __le16  tx_aborted;
 568         __le16  tx_underun;
 569 };
 570
 571 struct rtl8169_tc_offsets {
 572         bool    inited;
 573         __le64  tx_errors;
 574         __le32  tx_multi_collision;
 575         __le16  tx_aborted;
 576         __le16  rx_missed;
 577 };
 578
 579 enum rtl_flag {
 580         RTL_FLAG_TASK_ENABLED = 0,
 581         RTL_FLAG_TASK_RESET_PENDING,
 582         RTL_FLAG_TASK_TX_TIMEOUT,
 583         RTL_FLAG_MAX
 584 };
 585
 586 enum rtl_dash_type {
 587         RTL_DASH_NONE,
 588         RTL_DASH_DP,
 589         RTL_DASH_EP,
 590 };
 591
 592 struct rtl8169_private {
 593         void __iomem *mmio_addr;        /* memory map physical address */
 594         struct pci_dev *pci_dev;
 595         struct net_device *dev;
 596         struct phy_device *phydev;
 597         struct napi_struct napi;
 598         enum mac_version mac_version;
 599         enum rtl_dash_type dash_type;
 600         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 601         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 602         u32 dirty_tx;
 603         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 604         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 605         dma_addr_t TxPhyAddr;
 606         dma_addr_t RxPhyAddr;
 607         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 608         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 609         u16 cp_cmd;
 610         u32 irq_mask;
 611         int irq;
 612         struct clk *clk;
 613
 614         struct {
 615                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 616                 struct work_struct work;
 617         } wk;
 618
 619         raw_spinlock_t config25_lock;
 620         raw_spinlock_t mac_ocp_lock;
 621
 622         raw_spinlock_t cfg9346_usage_lock;
 623         int cfg9346_usage_count;
 624
 625         unsigned supports_gmii:1;
 626         unsigned aspm_manageable:1;
 627         dma_addr_t counters_phys_addr;
 628         struct rtl8169_counters *counters;
 629         struct rtl8169_tc_offsets tc_offset;
 630         u32 saved_wolopts;
 631         int eee_adv;
 632
 633         const char *fw_name;
 634         struct rtl_fw *rtl_fw;
 635
 636         u32 ocp_base;
 637 };
 638
 639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 640
 641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 643 MODULE_SOFTDEP("pre: realtek");
 644 MODULE_LICENSE("GPL");
 645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 653 MODULE_FIRMWARE(FIRMWARE_8402_1);
 654 MODULE_FIRMWARE(FIRMWARE_8411_1);
 655 MODULE_FIRMWARE(FIRMWARE_8411_2);
 656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 660 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 661 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 662 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 663 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 664 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 665
 666 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 667 {
 668         return &tp->pci_dev->dev;
 669 }
 670
 671 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 672 {
 673         unsigned long flags;
 674
 675         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 676         if (!--tp->cfg9346_usage_count)
 677                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 678         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 679 }
 680
 681 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 682 {
 683         unsigned long flags;
 684
 685         raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
 686         if (!tp->cfg9346_usage_count++)
 687                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 688         raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
 689 }
 690
 691 static void rtl_pci_commit(struct rtl8169_private *tp)
 692 {
 693         /* Read an arbitrary register to commit a preceding PCI write */
 694         RTL_R8(tp, ChipCmd);
 695 }
 696
 697 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
 698 {
 699         unsigned long flags;
 700         u8 val;
 701
 702         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 703         val = RTL_R8(tp, Config2);
 704         RTL_W8(tp, Config2, (val & ~clear) | set);
 705         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 706 }
 707
 708 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
 709 {
 710         unsigned long flags;
 711         u8 val;
 712
 713         raw_spin_lock_irqsave(&tp->config25_lock, flags);
 714         val = RTL_R8(tp, Config5);
 715         RTL_W8(tp, Config5, (val & ~clear) | set);
 716         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
 717 }
 718
 719 static bool rtl_is_8125(struct rtl8169_private *tp)
 720 {
 721         return tp->mac_version >= RTL_GIGA_MAC_VER_61;
 722 }
 723
 724 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 725 {
 726         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 727                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 728                tp->mac_version <= RTL_GIGA_MAC_VER_53;
 729 }
 730
 731 static bool rtl_supports_eee(struct rtl8169_private *tp)
 732 {
 733         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 734                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 735                tp->mac_version != RTL_GIGA_MAC_VER_39;
 736 }
 737
 738 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 739 {
 740         int i;
 741
 742         for (i = 0; i < ETH_ALEN; i++)
 743                 mac[i] = RTL_R8(tp, reg + i);
 744 }
 745
 746 struct rtl_cond {
 747         bool (*check)(struct rtl8169_private *);
 748         const char *msg;
 749 };
 750
 751 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 752                           unsigned long usecs, int n, bool high)
 753 {
 754         int i;
 755
 756         for (i = 0; i < n; i++) {
 757                 if (c->check(tp) == high)
 758                         return true;
 759                 fsleep(usecs);
 760         }
 761
 762         if (net_ratelimit())
 763                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 764                            c->msg, !high, n, usecs);
 765         return false;
 766 }
 767
 768 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 769                                const struct rtl_cond *c,
 770                                unsigned long d, int n)
 771 {
 772         return rtl_loop_wait(tp, c, d, n, true);
 773 }
 774
 775 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 776                               const struct rtl_cond *c,
 777                               unsigned long d, int n)
 778 {
 779         return rtl_loop_wait(tp, c, d, n, false);
 780 }
 781
 782 #define DECLARE_RTL_COND(name)                          \
 783 static bool name ## _check(struct rtl8169_private *);   \
 784                                                         \
 785 static const struct rtl_cond name = {                   \
 786         .check  = name ## _check,                       \
 787         .msg    = #name                                 \
 788 };                                                      \
 789                                                         \
 790 static bool name ## _check(struct rtl8169_private *tp)
 791
 792 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
 793 {
 794         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
 795         if (type == ERIAR_OOB &&
 796             (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
 797              tp->mac_version == RTL_GIGA_MAC_VER_53))
 798                 *cmd |= 0xf70 << 18;
 799 }
 800
 801 DECLARE_RTL_COND(rtl_eriar_cond)
 802 {
 803         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
 804 }
 805
 806 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 807                            u32 val, int type)
 808 {
 809         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
 810
 811         if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
 812                 return;
 813
 814         RTL_W32(tp, ERIDR, val);
 815         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 816         RTL_W32(tp, ERIAR, cmd);
 817
 818         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
 819 }
 820
 821 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
 822                           u32 val)
 823 {
 824         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
 825 }
 826
 827 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
 828 {
 829         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
 830
 831         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
 832         RTL_W32(tp, ERIAR, cmd);
 833
 834         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
 835                 RTL_R32(tp, ERIDR) : ~0;
 836 }
 837
 838 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
 839 {
 840         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
 841 }
 842
 843 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
 844 {
 845         u32 val = rtl_eri_read(tp, addr);
 846
 847         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
 848 }
 849
 850 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
 851 {
 852         rtl_w0w1_eri(tp, addr, p, 0);
 853 }
 854
 855 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
 856 {
 857         rtl_w0w1_eri(tp, addr, 0, m);
 858 }
 859
 860 static bool rtl_ocp_reg_failure(u32 reg)
 861 {
 862         return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
 863 }
 864
 865 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 866 {
 867         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 868 }
 869
 870 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 871 {
 872         if (rtl_ocp_reg_failure(reg))
 873                 return;
 874
 875         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 876
 877         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 878 }
 879
 880 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 881 {
 882         if (rtl_ocp_reg_failure(reg))
 883                 return 0;
 884
 885         RTL_W32(tp, GPHY_OCP, reg << 15);
 886
 887         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 888                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 889 }
 890
 891 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 892 {
 893         if (rtl_ocp_reg_failure(reg))
 894                 return;
 895
 896         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 897 }
 898
 899 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 900 {
 901         unsigned long flags;
 902
 903         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 904         __r8168_mac_ocp_write(tp, reg, data);
 905         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 906 }
 907
 908 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 909 {
 910         if (rtl_ocp_reg_failure(reg))
 911                 return 0;
 912
 913         RTL_W32(tp, OCPDR, reg << 15);
 914
 915         return RTL_R32(tp, OCPDR);
 916 }
 917
 918 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 919 {
 920         unsigned long flags;
 921         u16 val;
 922
 923         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 924         val = __r8168_mac_ocp_read(tp, reg);
 925         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 926
 927         return val;
 928 }
 929
 930 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 931                                  u16 set)
 932 {
 933         unsigned long flags;
 934         u16 data;
 935
 936         raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
 937         data = __r8168_mac_ocp_read(tp, reg);
 938         __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 939         raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
 940 }
 941
 942 /* Work around a hw issue with RTL8168g PHY, the quirk disables
 943  * PHY MCU interrupts before PHY power-down.
 944  */
 945 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
 946 {
 947         switch (tp->mac_version) {
 948         case RTL_GIGA_MAC_VER_40:
 949                 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
 950                         rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
 951                 else
 952                         rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
 953                 break;
 954         default:
 955                 break;
 956         }
 957 };
 958
 959 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 960 {
 961         if (reg == 0x1f) {
 962                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 963                 return;
 964         }
 965
 966         if (tp->ocp_base != OCP_STD_PHY_BASE)
 967                 reg -= 0x10;
 968
 969         if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
 970                 rtl8168g_phy_suspend_quirk(tp, value);
 971
 972         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 973 }
 974
 975 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 976 {
 977         if (reg == 0x1f)
 978                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 979
 980         if (tp->ocp_base != OCP_STD_PHY_BASE)
 981                 reg -= 0x10;
 982
 983         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 984 }
 985
 986 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 987 {
 988         if (reg == 0x1f) {
 989                 tp->ocp_base = value << 4;
 990                 return;
 991         }
 992
 993         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 994 }
 995
 996 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 997 {
 998         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 999 }
1000
1001 DECLARE_RTL_COND(rtl_phyar_cond)
1002 {
1003         return RTL_R32(tp, PHYAR) & 0x80000000;
1004 }
1005
1006 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1007 {
1008         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1009
1010         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1011         /*
1012          * According to hardware specs a 20us delay is required after write
1013          * complete indication, but before sending next command.
1014          */
1015         udelay(20);
1016 }
1017
1018 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1019 {
1020         int value;
1021
1022         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1023
1024         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1025                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1026
1027         /*
1028          * According to hardware specs a 20us delay is required after read
1029          * complete indication, but before sending next command.
1030          */
1031         udelay(20);
1032
1033         return value;
1034 }
1035
1036 DECLARE_RTL_COND(rtl_ocpar_cond)
1037 {
1038         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1039 }
1040
1041 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1042
1043 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1044 {
1045         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1046 }
1047
1048 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1049 {
1050         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1051 }
1052
1053 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1054 {
1055         r8168dp_2_mdio_start(tp);
1056
1057         r8169_mdio_write(tp, reg, value);
1058
1059         r8168dp_2_mdio_stop(tp);
1060 }
1061
1062 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1063 {
1064         int value;
1065
1066         /* Work around issue with chip reporting wrong PHY ID */
1067         if (reg == MII_PHYSID2)
1068                 return 0xc912;
1069
1070         r8168dp_2_mdio_start(tp);
1071
1072         value = r8169_mdio_read(tp, reg);
1073
1074         r8168dp_2_mdio_stop(tp);
1075
1076         return value;
1077 }
1078
1079 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1080 {
1081         switch (tp->mac_version) {
1082         case RTL_GIGA_MAC_VER_28:
1083         case RTL_GIGA_MAC_VER_31:
1084                 r8168dp_2_mdio_write(tp, location, val);
1085                 break;
1086         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1087                 r8168g_mdio_write(tp, location, val);
1088                 break;
1089         default:
1090                 r8169_mdio_write(tp, location, val);
1091                 break;
1092         }
1093 }
1094
1095 static int rtl_readphy(struct rtl8169_private *tp, int location)
1096 {
1097         switch (tp->mac_version) {
1098         case RTL_GIGA_MAC_VER_28:
1099         case RTL_GIGA_MAC_VER_31:
1100                 return r8168dp_2_mdio_read(tp, location);
1101         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1102                 return r8168g_mdio_read(tp, location);
1103         default:
1104                 return r8169_mdio_read(tp, location);
1105         }
1106 }
1107
1108 DECLARE_RTL_COND(rtl_ephyar_cond)
1109 {
1110         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1111 }
1112
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1114 {
1115         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1116                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1117
1118         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1119
1120         udelay(10);
1121 }
1122
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1124 {
1125         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1126
1127         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1128                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1129 }
1130
1131 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1132 {
1133         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1134         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1135                 RTL_R32(tp, OCPDR) : ~0;
1136 }
1137
1138 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1139 {
1140         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1141 }
1142
1143 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1144                               u32 data)
1145 {
1146         RTL_W32(tp, OCPDR, data);
1147         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1148         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1149 }
1150
1151 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1152                               u32 data)
1153 {
1154         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1155                        data, ERIAR_OOB);
1156 }
1157
1158 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1159 {
1160         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1161
1162         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1163 }
1164
1165 #define OOB_CMD_RESET           0x00
1166 #define OOB_CMD_DRIVER_START    0x05
1167 #define OOB_CMD_DRIVER_STOP     0x06
1168
1169 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1170 {
1171         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1172 }
1173
1174 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1175 {
1176         u16 reg;
1177
1178         reg = rtl8168_get_ocp_reg(tp);
1179
1180         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1181 }
1182
1183 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1184 {
1185         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1186 }
1187
1188 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1189 {
1190         return RTL_R8(tp, IBISR0) & 0x20;
1191 }
1192
1193 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1194 {
1195         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1196         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1197         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1198         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1199 }
1200
1201 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1202 {
1203         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1204         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1205 }
1206
1207 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1208 {
1209         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1210         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1211         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1212 }
1213
1214 static void rtl8168_driver_start(struct rtl8169_private *tp)
1215 {
1216         if (tp->dash_type == RTL_DASH_DP)
1217                 rtl8168dp_driver_start(tp);
1218         else
1219                 rtl8168ep_driver_start(tp);
1220 }
1221
1222 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1223 {
1224         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1225         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1226 }
1227
1228 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1229 {
1230         rtl8168ep_stop_cmac(tp);
1231         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1232         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1233         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1234 }
1235
1236 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1237 {
1238         if (tp->dash_type == RTL_DASH_DP)
1239                 rtl8168dp_driver_stop(tp);
1240         else
1241                 rtl8168ep_driver_stop(tp);
1242 }
1243
1244 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1245 {
1246         u16 reg = rtl8168_get_ocp_reg(tp);
1247
1248         return r8168dp_ocp_read(tp, reg) & BIT(15);
1249 }
1250
1251 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1252 {
1253         return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1254 }
1255
1256 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1257 {
1258         switch (tp->mac_version) {
1259         case RTL_GIGA_MAC_VER_28:
1260         case RTL_GIGA_MAC_VER_31:
1261                 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1262         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1263                 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1264         default:
1265                 return RTL_DASH_NONE;
1266         }
1267 }
1268
1269 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1270 {
1271         switch (tp->mac_version) {
1272         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1273         case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1274         case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1275         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1276                 if (enable)
1277                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1278                 else
1279                         RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1280                 break;
1281         default:
1282                 break;
1283         }
1284 }
1285
1286 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1287 {
1288         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1289         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1290 }
1291
1292 DECLARE_RTL_COND(rtl_efusear_cond)
1293 {
1294         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1295 }
1296
1297 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1298 {
1299         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1300
1301         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1302                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1303 }
1304
1305 static u32 rtl_get_events(struct rtl8169_private *tp)
1306 {
1307         if (rtl_is_8125(tp))
1308                 return RTL_R32(tp, IntrStatus_8125);
1309         else
1310                 return RTL_R16(tp, IntrStatus);
1311 }
1312
1313 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1314 {
1315         if (rtl_is_8125(tp))
1316                 RTL_W32(tp, IntrStatus_8125, bits);
1317         else
1318                 RTL_W16(tp, IntrStatus, bits);
1319 }
1320
1321 static void rtl_irq_disable(struct rtl8169_private *tp)
1322 {
1323         if (rtl_is_8125(tp))
1324                 RTL_W32(tp, IntrMask_8125, 0);
1325         else
1326                 RTL_W16(tp, IntrMask, 0);
1327 }
1328
1329 static void rtl_irq_enable(struct rtl8169_private *tp)
1330 {
1331         if (rtl_is_8125(tp))
1332                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1333         else
1334                 RTL_W16(tp, IntrMask, tp->irq_mask);
1335 }
1336
1337 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1338 {
1339         rtl_irq_disable(tp);
1340         rtl_ack_events(tp, 0xffffffff);
1341         rtl_pci_commit(tp);
1342 }
1343
1344 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1345 {
1346         struct phy_device *phydev = tp->phydev;
1347
1348         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1349             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1350                 if (phydev->speed == SPEED_1000) {
1351                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1352                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1353                 } else if (phydev->speed == SPEED_100) {
1354                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1355                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1356                 } else {
1357                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1358                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1359                 }
1360                 rtl_reset_packet_filter(tp);
1361         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1362                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1363                 if (phydev->speed == SPEED_1000) {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1366                 } else {
1367                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1368                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1369                 }
1370         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1371                 if (phydev->speed == SPEED_10) {
1372                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1373                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1374                 } else {
1375                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1376                 }
1377         }
1378 }
1379
1380 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1381
1382 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1383 {
1384         struct rtl8169_private *tp = netdev_priv(dev);
1385
1386         wol->supported = WAKE_ANY;
1387         wol->wolopts = tp->saved_wolopts;
1388 }
1389
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1391 {
1392         static const struct {
1393                 u32 opt;
1394                 u16 reg;
1395                 u8  mask;
1396         } cfg[] = {
1397                 { WAKE_PHY,   Config3, LinkUp },
1398                 { WAKE_UCAST, Config5, UWF },
1399                 { WAKE_BCAST, Config5, BWF },
1400                 { WAKE_MCAST, Config5, MWF },
1401                 { WAKE_ANY,   Config5, LanWake },
1402                 { WAKE_MAGIC, Config3, MagicPacket }
1403         };
1404         unsigned int i, tmp = ARRAY_SIZE(cfg);
1405         unsigned long flags;
1406         u8 options;
1407
1408         rtl_unlock_config_regs(tp);
1409
1410         if (rtl_is_8168evl_up(tp)) {
1411                 tmp--;
1412                 if (wolopts & WAKE_MAGIC)
1413                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1414                 else
1415                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1416         } else if (rtl_is_8125(tp)) {
1417                 tmp--;
1418                 if (wolopts & WAKE_MAGIC)
1419                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1420                 else
1421                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1422         }
1423
1424         raw_spin_lock_irqsave(&tp->config25_lock, flags);
1425         for (i = 0; i < tmp; i++) {
1426                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1427                 if (wolopts & cfg[i].opt)
1428                         options |= cfg[i].mask;
1429                 RTL_W8(tp, cfg[i].reg, options);
1430         }
1431         raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1432
1433         switch (tp->mac_version) {
1434         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1435                 options = RTL_R8(tp, Config1) & ~PMEnable;
1436                 if (wolopts)
1437                         options |= PMEnable;
1438                 RTL_W8(tp, Config1, options);
1439                 break;
1440         case RTL_GIGA_MAC_VER_34:
1441         case RTL_GIGA_MAC_VER_37:
1442         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1443                 if (wolopts)
1444                         rtl_mod_config2(tp, 0, PME_SIGNAL);
1445                 else
1446                         rtl_mod_config2(tp, PME_SIGNAL, 0);
1447                 break;
1448         default:
1449                 break;
1450         }
1451
1452         rtl_lock_config_regs(tp);
1453
1454         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1455
1456         if (tp->dash_type == RTL_DASH_NONE) {
1457                 rtl_set_d3_pll_down(tp, !wolopts);
1458                 tp->dev->wol_enabled = wolopts ? 1 : 0;
1459         }
1460 }
1461
1462 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1463 {
1464         struct rtl8169_private *tp = netdev_priv(dev);
1465
1466         if (wol->wolopts & ~WAKE_ANY)
1467                 return -EINVAL;
1468
1469         tp->saved_wolopts = wol->wolopts;
1470         __rtl8169_set_wol(tp, tp->saved_wolopts);
1471
1472         return 0;
1473 }
1474
1475 static void rtl8169_get_drvinfo(struct net_device *dev,
1476                                 struct ethtool_drvinfo *info)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         struct rtl_fw *rtl_fw = tp->rtl_fw;
1480
1481         strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1482         strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1483         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1484         if (rtl_fw)
1485                 strscpy(info->fw_version, rtl_fw->version,
1486                         sizeof(info->fw_version));
1487 }
1488
1489 static int rtl8169_get_regs_len(struct net_device *dev)
1490 {
1491         return R8169_REGS_SIZE;
1492 }
1493
1494 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1495         netdev_features_t features)
1496 {
1497         struct rtl8169_private *tp = netdev_priv(dev);
1498
1499         if (dev->mtu > TD_MSS_MAX)
1500                 features &= ~NETIF_F_ALL_TSO;
1501
1502         if (dev->mtu > ETH_DATA_LEN &&
1503             tp->mac_version > RTL_GIGA_MAC_VER_06)
1504                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1505
1506         return features;
1507 }
1508
1509 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1510                                        netdev_features_t features)
1511 {
1512         u32 rx_config = RTL_R32(tp, RxConfig);
1513
1514         if (features & NETIF_F_RXALL)
1515                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1516         else
1517                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1518
1519         if (rtl_is_8125(tp)) {
1520                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1521                         rx_config |= RX_VLAN_8125;
1522                 else
1523                         rx_config &= ~RX_VLAN_8125;
1524         }
1525
1526         RTL_W32(tp, RxConfig, rx_config);
1527 }
1528
1529 static int rtl8169_set_features(struct net_device *dev,
1530                                 netdev_features_t features)
1531 {
1532         struct rtl8169_private *tp = netdev_priv(dev);
1533
1534         rtl_set_rx_config_features(tp, features);
1535
1536         if (features & NETIF_F_RXCSUM)
1537                 tp->cp_cmd |= RxChkSum;
1538         else
1539                 tp->cp_cmd &= ~RxChkSum;
1540
1541         if (!rtl_is_8125(tp)) {
1542                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1543                         tp->cp_cmd |= RxVlan;
1544                 else
1545                         tp->cp_cmd &= ~RxVlan;
1546         }
1547
1548         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1549         rtl_pci_commit(tp);
1550
1551         return 0;
1552 }
1553
1554 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1555 {
1556         return (skb_vlan_tag_present(skb)) ?
1557                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1558 }
1559
1560 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1561 {
1562         u32 opts2 = le32_to_cpu(desc->opts2);
1563
1564         if (opts2 & RxVlanTag)
1565                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1566 }
1567
1568 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1569                              void *p)
1570 {
1571         struct rtl8169_private *tp = netdev_priv(dev);
1572         u32 __iomem *data = tp->mmio_addr;
1573         u32 *dw = p;
1574         int i;
1575
1576         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1577                 memcpy_fromio(dw++, data++, 4);
1578 }
1579
1580 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1581         "tx_packets",
1582         "rx_packets",
1583         "tx_errors",
1584         "rx_errors",
1585         "rx_missed",
1586         "align_errors",
1587         "tx_single_collisions",
1588         "tx_multi_collisions",
1589         "unicast",
1590         "broadcast",
1591         "multicast",
1592         "tx_aborted",
1593         "tx_underrun",
1594 };
1595
1596 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1597 {
1598         switch (sset) {
1599         case ETH_SS_STATS:
1600                 return ARRAY_SIZE(rtl8169_gstrings);
1601         default:
1602                 return -EOPNOTSUPP;
1603         }
1604 }
1605
1606 DECLARE_RTL_COND(rtl_counters_cond)
1607 {
1608         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1609 }
1610
1611 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1612 {
1613         u32 cmd = lower_32_bits(tp->counters_phys_addr);
1614
1615         RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1616         rtl_pci_commit(tp);
1617         RTL_W32(tp, CounterAddrLow, cmd);
1618         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1619
1620         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1621 }
1622
1623 static void rtl8169_update_counters(struct rtl8169_private *tp)
1624 {
1625         u8 val = RTL_R8(tp, ChipCmd);
1626
1627         /*
1628          * Some chips are unable to dump tally counters when the receiver
1629          * is disabled. If 0xff chip may be in a PCI power-save state.
1630          */
1631         if (val & CmdRxEnb && val != 0xff)
1632                 rtl8169_do_counters(tp, CounterDump);
1633 }
1634
1635 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1636 {
1637         struct rtl8169_counters *counters = tp->counters;
1638
1639         /*
1640          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1641          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1642          * reset by a power cycle, while the counter values collected by the
1643          * driver are reset at every driver unload/load cycle.
1644          *
1645          * To make sure the HW values returned by @get_stats64 match the SW
1646          * values, we collect the initial values at first open(*) and use them
1647          * as offsets to normalize the values returned by @get_stats64.
1648          *
1649          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1650          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1651          * set at open time by rtl_hw_start.
1652          */
1653
1654         if (tp->tc_offset.inited)
1655                 return;
1656
1657         if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1658                 rtl8169_do_counters(tp, CounterReset);
1659         } else {
1660                 rtl8169_update_counters(tp);
1661                 tp->tc_offset.tx_errors = counters->tx_errors;
1662                 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1663                 tp->tc_offset.tx_aborted = counters->tx_aborted;
1664                 tp->tc_offset.rx_missed = counters->rx_missed;
1665         }
1666
1667         tp->tc_offset.inited = true;
1668 }
1669
1670 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1671                                       struct ethtool_stats *stats, u64 *data)
1672 {
1673         struct rtl8169_private *tp = netdev_priv(dev);
1674         struct rtl8169_counters *counters;
1675
1676         counters = tp->counters;
1677         rtl8169_update_counters(tp);
1678
1679         data[0] = le64_to_cpu(counters->tx_packets);
1680         data[1] = le64_to_cpu(counters->rx_packets);
1681         data[2] = le64_to_cpu(counters->tx_errors);
1682         data[3] = le32_to_cpu(counters->rx_errors);
1683         data[4] = le16_to_cpu(counters->rx_missed);
1684         data[5] = le16_to_cpu(counters->align_errors);
1685         data[6] = le32_to_cpu(counters->tx_one_collision);
1686         data[7] = le32_to_cpu(counters->tx_multi_collision);
1687         data[8] = le64_to_cpu(counters->rx_unicast);
1688         data[9] = le64_to_cpu(counters->rx_broadcast);
1689         data[10] = le32_to_cpu(counters->rx_multicast);
1690         data[11] = le16_to_cpu(counters->tx_aborted);
1691         data[12] = le16_to_cpu(counters->tx_underun);
1692 }
1693
1694 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1695 {
1696         switch(stringset) {
1697         case ETH_SS_STATS:
1698                 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1699                 break;
1700         }
1701 }
1702
1703 /*
1704  * Interrupt coalescing
1705  *
1706  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1707  * >     8169, 8168 and 810x line of chipsets
1708  *
1709  * 8169, 8168, and 8136(810x) serial chipsets support it.
1710  *
1711  * > 2 - the Tx timer unit at gigabit speed
1712  *
1713  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1714  * (0xe0) bit 1 and bit 0.
1715  *
1716  * For 8169
1717  * bit[1:0] \ speed        1000M           100M            10M
1718  * 0 0                     320ns           2.56us          40.96us
1719  * 0 1                     2.56us          20.48us         327.7us
1720  * 1 0                     5.12us          40.96us         655.4us
1721  * 1 1                     10.24us         81.92us         1.31ms
1722  *
1723  * For the other
1724  * bit[1:0] \ speed        1000M           100M            10M
1725  * 0 0                     5us             2.56us          40.96us
1726  * 0 1                     40us            20.48us         327.7us
1727  * 1 0                     80us            40.96us         655.4us
1728  * 1 1                     160us           81.92us         1.31ms
1729  */
1730
1731 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1732 struct rtl_coalesce_info {
1733         u32 speed;
1734         u32 scale_nsecs[4];
1735 };
1736
1737 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1738 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1739
1740 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1741         { SPEED_1000,   COALESCE_DELAY(320) },
1742         { SPEED_100,    COALESCE_DELAY(2560) },
1743         { SPEED_10,     COALESCE_DELAY(40960) },
1744         { 0 },
1745 };
1746
1747 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1748         { SPEED_1000,   COALESCE_DELAY(5000) },
1749         { SPEED_100,    COALESCE_DELAY(2560) },
1750         { SPEED_10,     COALESCE_DELAY(40960) },
1751         { 0 },
1752 };
1753 #undef COALESCE_DELAY
1754
1755 /* get rx/tx scale vector corresponding to current speed */
1756 static const struct rtl_coalesce_info *
1757 rtl_coalesce_info(struct rtl8169_private *tp)
1758 {
1759         const struct rtl_coalesce_info *ci;
1760
1761         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1762                 ci = rtl_coalesce_info_8169;
1763         else
1764                 ci = rtl_coalesce_info_8168_8136;
1765
1766         /* if speed is unknown assume highest one */
1767         if (tp->phydev->speed == SPEED_UNKNOWN)
1768                 return ci;
1769
1770         for (; ci->speed; ci++) {
1771                 if (tp->phydev->speed == ci->speed)
1772                         return ci;
1773         }
1774
1775         return ERR_PTR(-ELNRNG);
1776 }
1777
1778 static int rtl_get_coalesce(struct net_device *dev,
1779                             struct ethtool_coalesce *ec,
1780                             struct kernel_ethtool_coalesce *kernel_coal,
1781                             struct netlink_ext_ack *extack)
1782 {
1783         struct rtl8169_private *tp = netdev_priv(dev);
1784         const struct rtl_coalesce_info *ci;
1785         u32 scale, c_us, c_fr;
1786         u16 intrmit;
1787
1788         if (rtl_is_8125(tp))
1789                 return -EOPNOTSUPP;
1790
1791         memset(ec, 0, sizeof(*ec));
1792
1793         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1794         ci = rtl_coalesce_info(tp);
1795         if (IS_ERR(ci))
1796                 return PTR_ERR(ci);
1797
1798         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1799
1800         intrmit = RTL_R16(tp, IntrMitigate);
1801
1802         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1803         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1804
1805         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1806         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1807         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1808
1809         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1810         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1811
1812         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1813         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1814
1815         return 0;
1816 }
1817
1818 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1819 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1820                                      u16 *cp01)
1821 {
1822         const struct rtl_coalesce_info *ci;
1823         u16 i;
1824
1825         ci = rtl_coalesce_info(tp);
1826         if (IS_ERR(ci))
1827                 return PTR_ERR(ci);
1828
1829         for (i = 0; i < 4; i++) {
1830                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1831                         *cp01 = i;
1832                         return ci->scale_nsecs[i];
1833                 }
1834         }
1835
1836         return -ERANGE;
1837 }
1838
1839 static int rtl_set_coalesce(struct net_device *dev,
1840                             struct ethtool_coalesce *ec,
1841                             struct kernel_ethtool_coalesce *kernel_coal,
1842                             struct netlink_ext_ack *extack)
1843 {
1844         struct rtl8169_private *tp = netdev_priv(dev);
1845         u32 tx_fr = ec->tx_max_coalesced_frames;
1846         u32 rx_fr = ec->rx_max_coalesced_frames;
1847         u32 coal_usec_max, units;
1848         u16 w = 0, cp01 = 0;
1849         int scale;
1850
1851         if (rtl_is_8125(tp))
1852                 return -EOPNOTSUPP;
1853
1854         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1855                 return -ERANGE;
1856
1857         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1858         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1859         if (scale < 0)
1860                 return scale;
1861
1862         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1863          * not only when usecs=0 because of e.g. the following scenario:
1864          *
1865          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1866          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1867          * - then user does `ethtool -C eth0 rx-usecs 100`
1868          *
1869          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1870          * if we want to ignore rx_frames then it has to be set to 0.
1871          */
1872         if (rx_fr == 1)
1873                 rx_fr = 0;
1874         if (tx_fr == 1)
1875                 tx_fr = 0;
1876
1877         /* HW requires time limit to be set if frame limit is set */
1878         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1879             (rx_fr && !ec->rx_coalesce_usecs))
1880                 return -EINVAL;
1881
1882         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1883         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1884
1885         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1886         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1887         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1888         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1889
1890         RTL_W16(tp, IntrMitigate, w);
1891
1892         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1893         if (rtl_is_8168evl_up(tp)) {
1894                 if (!rx_fr && !tx_fr)
1895                         /* disable packet counter */
1896                         tp->cp_cmd |= PktCntrDisable;
1897                 else
1898                         tp->cp_cmd &= ~PktCntrDisable;
1899         }
1900
1901         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1902         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1903         rtl_pci_commit(tp);
1904
1905         return 0;
1906 }
1907
1908 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1909 {
1910         struct rtl8169_private *tp = netdev_priv(dev);
1911
1912         if (!rtl_supports_eee(tp))
1913                 return -EOPNOTSUPP;
1914
1915         return phy_ethtool_get_eee(tp->phydev, data);
1916 }
1917
1918 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1919 {
1920         struct rtl8169_private *tp = netdev_priv(dev);
1921         int ret;
1922
1923         if (!rtl_supports_eee(tp))
1924                 return -EOPNOTSUPP;
1925
1926         ret = phy_ethtool_set_eee(tp->phydev, data);
1927
1928         if (!ret)
1929                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1930                                            MDIO_AN_EEE_ADV);
1931         return ret;
1932 }
1933
1934 static void rtl8169_get_ringparam(struct net_device *dev,
1935                                   struct ethtool_ringparam *data,
1936                                   struct kernel_ethtool_ringparam *kernel_data,
1937                                   struct netlink_ext_ack *extack)
1938 {
1939         data->rx_max_pending = NUM_RX_DESC;
1940         data->rx_pending = NUM_RX_DESC;
1941         data->tx_max_pending = NUM_TX_DESC;
1942         data->tx_pending = NUM_TX_DESC;
1943 }
1944
1945 static void rtl8169_get_pauseparam(struct net_device *dev,
1946                                    struct ethtool_pauseparam *data)
1947 {
1948         struct rtl8169_private *tp = netdev_priv(dev);
1949         bool tx_pause, rx_pause;
1950
1951         phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1952
1953         data->autoneg = tp->phydev->autoneg;
1954         data->tx_pause = tx_pause ? 1 : 0;
1955         data->rx_pause = rx_pause ? 1 : 0;
1956 }
1957
1958 static int rtl8169_set_pauseparam(struct net_device *dev,
1959                                   struct ethtool_pauseparam *data)
1960 {
1961         struct rtl8169_private *tp = netdev_priv(dev);
1962
1963         if (dev->mtu > ETH_DATA_LEN)
1964                 return -EOPNOTSUPP;
1965
1966         phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1967
1968         return 0;
1969 }
1970
1971 static const struct ethtool_ops rtl8169_ethtool_ops = {
1972         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1973                                      ETHTOOL_COALESCE_MAX_FRAMES,
1974         .get_drvinfo            = rtl8169_get_drvinfo,
1975         .get_regs_len           = rtl8169_get_regs_len,
1976         .get_link               = ethtool_op_get_link,
1977         .get_coalesce           = rtl_get_coalesce,
1978         .set_coalesce           = rtl_set_coalesce,
1979         .get_regs               = rtl8169_get_regs,
1980         .get_wol                = rtl8169_get_wol,
1981         .set_wol                = rtl8169_set_wol,
1982         .get_strings            = rtl8169_get_strings,
1983         .get_sset_count         = rtl8169_get_sset_count,
1984         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1985         .get_ts_info            = ethtool_op_get_ts_info,
1986         .nway_reset             = phy_ethtool_nway_reset,
1987         .get_eee                = rtl8169_get_eee,
1988         .set_eee                = rtl8169_set_eee,
1989         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1990         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1991         .get_ringparam          = rtl8169_get_ringparam,
1992         .get_pauseparam         = rtl8169_get_pauseparam,
1993         .set_pauseparam         = rtl8169_set_pauseparam,
1994 };
1995
1996 static void rtl_enable_eee(struct rtl8169_private *tp)
1997 {
1998         struct phy_device *phydev = tp->phydev;
1999         int adv;
2000
2001         /* respect EEE advertisement the user may have set */
2002         if (tp->eee_adv >= 0)
2003                 adv = tp->eee_adv;
2004         else
2005                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2006
2007         if (adv >= 0)
2008                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2009 }
2010
2011 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2012 {
2013         /*
2014          * The driver currently handles the 8168Bf and the 8168Be identically
2015          * but they can be identified more specifically through the test below
2016          * if needed:
2017          *
2018          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2019          *
2020          * Same thing for the 8101Eb and the 8101Ec:
2021          *
2022          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2023          */
2024         static const struct rtl_mac_info {
2025                 u16 mask;
2026                 u16 val;
2027                 enum mac_version ver;
2028         } mac_info[] = {
2029                 /* 8125B family. */
2030                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2031
2032                 /* 8125A family. */
2033                 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2034                 /* It seems only XID 609 made it to the mass market.
2035                  * { 0x7cf, 0x608,      RTL_GIGA_MAC_VER_60 },
2036                  * { 0x7c8, 0x608,      RTL_GIGA_MAC_VER_61 },
2037                  */
2038
2039                 /* RTL8117 */
2040                 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2041                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2042
2043                 /* 8168EP family. */
2044                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2045                 /* It seems this chip version never made it to
2046                  * the wild. Let's disable detection.
2047                  * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
2048                  * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
2049                  */
2050
2051                 /* 8168H family. */
2052                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2053                 /* It seems this chip version never made it to
2054                  * the wild. Let's disable detection.
2055                  * { 0x7cf, 0x540,      RTL_GIGA_MAC_VER_45 },
2056                  */
2057
2058                 /* 8168G family. */
2059                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2060                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2061                 /* It seems this chip version never made it to
2062                  * the wild. Let's disable detection.
2063                  * { 0x7cf, 0x4c1,      RTL_GIGA_MAC_VER_41 },
2064                  */
2065                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2066
2067                 /* 8168F family. */
2068                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2069                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2070                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2071
2072                 /* 8168E family. */
2073                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2074                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2075                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2076
2077                 /* 8168D family. */
2078                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2079                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2080
2081                 /* 8168DP family. */
2082                 /* It seems this early RTL8168dp version never made it to
2083                  * the wild. Support has been removed.
2084                  * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2085                  */
2086                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2087                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2088
2089                 /* 8168C family. */
2090                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2091                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2092                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2093                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2094                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2095                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2096                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2097
2098                 /* 8168B family. */
2099                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2100                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2101
2102                 /* 8101 family. */
2103                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2104                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2105                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2106                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2107                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2108                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2109                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2110                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2111                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2112                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2113                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2114                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2115
2116                 /* 8110 family. */
2117                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2118                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2119                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2120                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2121                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2122
2123                 /* Catch-all */
2124                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2125         };
2126         const struct rtl_mac_info *p = mac_info;
2127         enum mac_version ver;
2128
2129         while ((xid & p->mask) != p->val)
2130                 p++;
2131         ver = p->ver;
2132
2133         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2134                 if (ver == RTL_GIGA_MAC_VER_42)
2135                         ver = RTL_GIGA_MAC_VER_43;
2136                 else if (ver == RTL_GIGA_MAC_VER_46)
2137                         ver = RTL_GIGA_MAC_VER_48;
2138         }
2139
2140         return ver;
2141 }
2142
2143 static void rtl_release_firmware(struct rtl8169_private *tp)
2144 {
2145         if (tp->rtl_fw) {
2146                 rtl_fw_release_firmware(tp->rtl_fw);
2147                 kfree(tp->rtl_fw);
2148                 tp->rtl_fw = NULL;
2149         }
2150 }
2151
2152 void r8169_apply_firmware(struct rtl8169_private *tp)
2153 {
2154         int val;
2155
2156         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2157         if (tp->rtl_fw) {
2158                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2159                 /* At least one firmware doesn't reset tp->ocp_base. */
2160                 tp->ocp_base = OCP_STD_PHY_BASE;
2161
2162                 /* PHY soft reset may still be in progress */
2163                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2164                                       !(val & BMCR_RESET),
2165                                       50000, 600000, true);
2166         }
2167 }
2168
2169 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2170 {
2171         /* Adjust EEE LED frequency */
2172         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2173                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2174
2175         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2176 }
2177
2178 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2179 {
2180         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2181         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2182 }
2183
2184 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2185 {
2186         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2187 }
2188
2189 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2190 {
2191         rtl8125_set_eee_txidle_timer(tp);
2192         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2193 }
2194
2195 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2196 {
2197         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2198         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2199         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2200         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2201 }
2202
2203 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2204 {
2205         u16 data1, data2, ioffset;
2206
2207         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2208         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2209         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2210
2211         ioffset = (data2 >> 1) & 0x7ff8;
2212         ioffset |= data2 & 0x0007;
2213         if (data1 & BIT(7))
2214                 ioffset |= BIT(15);
2215
2216         return ioffset;
2217 }
2218
2219 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2220 {
2221         set_bit(flag, tp->wk.flags);
2222         schedule_work(&tp->wk.work);
2223 }
2224
2225 static void rtl8169_init_phy(struct rtl8169_private *tp)
2226 {
2227         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2228
2229         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2230                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2231                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2232                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2233                 RTL_W8(tp, 0x82, 0x01);
2234         }
2235
2236         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2237             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2238             tp->pci_dev->subsystem_device == 0xe000)
2239                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2240
2241         /* We may have called phy_speed_down before */
2242         phy_speed_up(tp->phydev);
2243
2244         if (rtl_supports_eee(tp))
2245                 rtl_enable_eee(tp);
2246
2247         genphy_soft_reset(tp->phydev);
2248 }
2249
2250 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2251 {
2252         rtl_unlock_config_regs(tp);
2253
2254         RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2255         rtl_pci_commit(tp);
2256
2257         RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2258         rtl_pci_commit(tp);
2259
2260         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2261                 rtl_rar_exgmac_set(tp, addr);
2262
2263         rtl_lock_config_regs(tp);
2264 }
2265
2266 static int rtl_set_mac_address(struct net_device *dev, void *p)
2267 {
2268         struct rtl8169_private *tp = netdev_priv(dev);
2269         int ret;
2270
2271         ret = eth_mac_addr(dev, p);
2272         if (ret)
2273                 return ret;
2274
2275         rtl_rar_set(tp, dev->dev_addr);
2276
2277         return 0;
2278 }
2279
2280 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2281 {
2282         switch (tp->mac_version) {
2283         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2284         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2285                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2286                 break;
2287         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2288         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2289         case RTL_GIGA_MAC_VER_38:
2290                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2291                 break;
2292         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2293                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2294                 break;
2295         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2296                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2297                 break;
2298         default:
2299                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2300                 break;
2301         }
2302 }
2303
2304 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2305 {
2306         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2307 }
2308
2309 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2310 {
2311         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2312         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2313 }
2314
2315 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2316 {
2317         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2318         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2319 }
2320
2321 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2322 {
2323         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2324 }
2325
2326 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2327 {
2328         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2329 }
2330
2331 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2332 {
2333         RTL_W8(tp, MaxTxPacketSize, 0x24);
2334         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2335         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2336 }
2337
2338 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2339 {
2340         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2341         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2342         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2343 }
2344
2345 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2346 {
2347         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2348 }
2349
2350 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2351 {
2352         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2353 }
2354
2355 static void rtl_jumbo_config(struct rtl8169_private *tp)
2356 {
2357         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2358         int readrq = 4096;
2359
2360         rtl_unlock_config_regs(tp);
2361         switch (tp->mac_version) {
2362         case RTL_GIGA_MAC_VER_17:
2363                 if (jumbo) {
2364                         readrq = 512;
2365                         r8168b_1_hw_jumbo_enable(tp);
2366                 } else {
2367                         r8168b_1_hw_jumbo_disable(tp);
2368                 }
2369                 break;
2370         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2371                 if (jumbo) {
2372                         readrq = 512;
2373                         r8168c_hw_jumbo_enable(tp);
2374                 } else {
2375                         r8168c_hw_jumbo_disable(tp);
2376                 }
2377                 break;
2378         case RTL_GIGA_MAC_VER_28:
2379                 if (jumbo)
2380                         r8168dp_hw_jumbo_enable(tp);
2381                 else
2382                         r8168dp_hw_jumbo_disable(tp);
2383                 break;
2384         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2385                 if (jumbo)
2386                         r8168e_hw_jumbo_enable(tp);
2387                 else
2388                         r8168e_hw_jumbo_disable(tp);
2389                 break;
2390         default:
2391                 break;
2392         }
2393         rtl_lock_config_regs(tp);
2394
2395         if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2396                 pcie_set_readrq(tp->pci_dev, readrq);
2397
2398         /* Chip doesn't support pause in jumbo mode */
2399         if (jumbo) {
2400                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2401                                    tp->phydev->advertising);
2402                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2403                                    tp->phydev->advertising);
2404                 phy_start_aneg(tp->phydev);
2405         }
2406 }
2407
2408 DECLARE_RTL_COND(rtl_chipcmd_cond)
2409 {
2410         return RTL_R8(tp, ChipCmd) & CmdReset;
2411 }
2412
2413 static void rtl_hw_reset(struct rtl8169_private *tp)
2414 {
2415         RTL_W8(tp, ChipCmd, CmdReset);
2416
2417         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2418 }
2419
2420 static void rtl_request_firmware(struct rtl8169_private *tp)
2421 {
2422         struct rtl_fw *rtl_fw;
2423
2424         /* firmware loaded already or no firmware available */
2425         if (tp->rtl_fw || !tp->fw_name)
2426                 return;
2427
2428         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2429         if (!rtl_fw)
2430                 return;
2431
2432         rtl_fw->phy_write = rtl_writephy;
2433         rtl_fw->phy_read = rtl_readphy;
2434         rtl_fw->mac_mcu_write = mac_mcu_write;
2435         rtl_fw->mac_mcu_read = mac_mcu_read;
2436         rtl_fw->fw_name = tp->fw_name;
2437         rtl_fw->dev = tp_to_dev(tp);
2438
2439         if (rtl_fw_request_firmware(rtl_fw))
2440                 kfree(rtl_fw);
2441         else
2442                 tp->rtl_fw = rtl_fw;
2443 }
2444
2445 static void rtl_rx_close(struct rtl8169_private *tp)
2446 {
2447         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2448 }
2449
2450 DECLARE_RTL_COND(rtl_npq_cond)
2451 {
2452         return RTL_R8(tp, TxPoll) & NPQ;
2453 }
2454
2455 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2456 {
2457         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2458 }
2459
2460 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2461 {
2462         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2463 }
2464
2465 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2466 {
2467         /* IntrMitigate has new functionality on RTL8125 */
2468         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2469 }
2470
2471 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2472 {
2473         switch (tp->mac_version) {
2474         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2475                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2476                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2477                 break;
2478         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2479                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2480                 break;
2481         case RTL_GIGA_MAC_VER_63:
2482                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2483                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2484                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2485                 break;
2486         default:
2487                 break;
2488         }
2489 }
2490
2491 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2492 {
2493         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2494 }
2495
2496 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2497 {
2498         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2499         fsleep(2000);
2500         rtl_wait_txrx_fifo_empty(tp);
2501 }
2502
2503 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2504 {
2505         if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2506                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2507                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2508
2509         if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2510                 rtl_disable_rxdvgate(tp);
2511 }
2512
2513 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2514 {
2515         if (tp->dash_type != RTL_DASH_NONE)
2516                 return;
2517
2518         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2519             tp->mac_version == RTL_GIGA_MAC_VER_33)
2520                 rtl_ephy_write(tp, 0x19, 0xff64);
2521
2522         if (device_may_wakeup(tp_to_dev(tp))) {
2523                 phy_speed_down(tp->phydev, false);
2524                 rtl_wol_enable_rx(tp);
2525         }
2526 }
2527
2528 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2529 {
2530         u32 val = TX_DMA_BURST << TxDMAShift |
2531                   InterFrameGap << TxInterFrameGapShift;
2532
2533         if (rtl_is_8168evl_up(tp))
2534                 val |= TXCFG_AUTO_FIFO;
2535
2536         RTL_W32(tp, TxConfig, val);
2537 }
2538
2539 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2540 {
2541         /* Low hurts. Let's disable the filtering. */
2542         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2543 }
2544
2545 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2546 {
2547         /*
2548          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2549          * register to be written before TxDescAddrLow to work.
2550          * Switching from MMIO to I/O access fixes the issue as well.
2551          */
2552         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2553         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2554         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2555         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2556 }
2557
2558 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2559 {
2560         u32 val;
2561
2562         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2563                 val = 0x000fff00;
2564         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2565                 val = 0x00ffff00;
2566         else
2567                 return;
2568
2569         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2570                 val |= 0xff;
2571
2572         RTL_W32(tp, 0x7c, val);
2573 }
2574
2575 static void rtl_set_rx_mode(struct net_device *dev)
2576 {
2577         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2578         /* Multicast hash filter */
2579         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2580         struct rtl8169_private *tp = netdev_priv(dev);
2581         u32 tmp;
2582
2583         if (dev->flags & IFF_PROMISC) {
2584                 rx_mode |= AcceptAllPhys;
2585         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2586                    dev->flags & IFF_ALLMULTI ||
2587                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2588                 /* accept all multicasts */
2589         } else if (netdev_mc_empty(dev)) {
2590                 rx_mode &= ~AcceptMulticast;
2591         } else {
2592                 struct netdev_hw_addr *ha;
2593
2594                 mc_filter[1] = mc_filter[0] = 0;
2595                 netdev_for_each_mc_addr(ha, dev) {
2596                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2597                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2598                 }
2599
2600                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2601                         tmp = mc_filter[0];
2602                         mc_filter[0] = swab32(mc_filter[1]);
2603                         mc_filter[1] = swab32(tmp);
2604                 }
2605         }
2606
2607         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2608         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2609
2610         tmp = RTL_R32(tp, RxConfig);
2611         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2612 }
2613
2614 DECLARE_RTL_COND(rtl_csiar_cond)
2615 {
2616         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2617 }
2618
2619 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2620 {
2621         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2622
2623         RTL_W32(tp, CSIDR, value);
2624         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2625                 CSIAR_BYTE_ENABLE | func << 16);
2626
2627         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2628 }
2629
2630 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2631 {
2632         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2633
2634         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2635                 CSIAR_BYTE_ENABLE);
2636
2637         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2638                 RTL_R32(tp, CSIDR) : ~0;
2639 }
2640
2641 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2642 {
2643         struct pci_dev *pdev = tp->pci_dev;
2644         u32 csi;
2645
2646         /* According to Realtek the value at config space address 0x070f
2647          * controls the L0s/L1 entrance latency. We try standard ECAM access
2648          * first and if it fails fall back to CSI.
2649          * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2650          * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2651          */
2652         if (pdev->cfg_size > 0x070f &&
2653             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2654                 return;
2655
2656         netdev_notice_once(tp->dev,
2657                 "No native access to PCI extended config space, falling back to CSI\n");
2658         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2659         rtl_csi_write(tp, 0x070c, csi | val << 24);
2660 }
2661
2662 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2663 {
2664         /* L0 7us, L1 16us */
2665         rtl_set_aspm_entry_latency(tp, 0x27);
2666 }
2667
2668 struct ephy_info {
2669         unsigned int offset;
2670         u16 mask;
2671         u16 bits;
2672 };
2673
2674 static void __rtl_ephy_init(struct rtl8169_private *tp,
2675                             const struct ephy_info *e, int len)
2676 {
2677         u16 w;
2678
2679         while (len-- > 0) {
2680                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2681                 rtl_ephy_write(tp, e->offset, w);
2682                 e++;
2683         }
2684 }
2685
2686 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2687
2688 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2689 {
2690         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2691                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2692 }
2693
2694 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2695 {
2696         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2697                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2698 }
2699
2700 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2701 {
2702         /* work around an issue when PCI reset occurs during L2/L3 state */
2703         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2704 }
2705
2706 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2707 {
2708         /* Bits control which events trigger ASPM L1 exit:
2709          * Bit 12: rxdv
2710          * Bit 11: ltr_msg
2711          * Bit 10: txdma_poll
2712          * Bit  9: xadm
2713          * Bit  8: pktavi
2714          * Bit  7: txpla
2715          */
2716         switch (tp->mac_version) {
2717         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2718                 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2719                 break;
2720         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2721                 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2722                 break;
2723         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2724                 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2725                 break;
2726         default:
2727                 break;
2728         }
2729 }
2730
2731 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2732 {
2733         switch (tp->mac_version) {
2734         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2735                 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2736                 break;
2737         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2738                 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2739                 break;
2740         default:
2741                 break;
2742         }
2743 }
2744
2745 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2746 {
2747         if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2748                 return;
2749
2750         /* Don't enable ASPM in the chip if OS can't control ASPM */
2751         if (enable && tp->aspm_manageable) {
2752                 /* On these chip versions ASPM can even harm
2753                  * bus communication of other PCI devices.
2754                  */
2755                 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2756                     tp->mac_version == RTL_GIGA_MAC_VER_43)
2757                         return;
2758
2759                 rtl_mod_config5(tp, 0, ASPM_en);
2760                 rtl_mod_config2(tp, 0, ClkReqEn);
2761
2762                 switch (tp->mac_version) {
2763                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2764                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2765                         /* reset ephy tx/rx disable timer */
2766                         r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2767                         /* chip can trigger L1.2 */
2768                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2769                         break;
2770                 default:
2771                         break;
2772                 }
2773         } else {
2774                 switch (tp->mac_version) {
2775                 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2776                 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2777                         r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2778                         break;
2779                 default:
2780                         break;
2781                 }
2782
2783                 rtl_mod_config2(tp, ClkReqEn, 0);
2784                 rtl_mod_config5(tp, ASPM_en, 0);
2785         }
2786 }
2787
2788 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2789                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2790 {
2791         /* Usage of dynamic vs. static FIFO is controlled by bit
2792          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2793          */
2794         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2795         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2796 }
2797
2798 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2799                                           u8 low, u8 high)
2800 {
2801         /* FIFO thresholds for pause flow control */
2802         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2803         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2804 }
2805
2806 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2807 {
2808         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2809 }
2810
2811 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2812 {
2813         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2814
2815         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2816
2817         rtl_disable_clock_request(tp);
2818 }
2819
2820 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2821 {
2822         static const struct ephy_info e_info_8168cp[] = {
2823                 { 0x01, 0,      0x0001 },
2824                 { 0x02, 0x0800, 0x1000 },
2825                 { 0x03, 0,      0x0042 },
2826                 { 0x06, 0x0080, 0x0000 },
2827                 { 0x07, 0,      0x2000 }
2828         };
2829
2830         rtl_set_def_aspm_entry_latency(tp);
2831
2832         rtl_ephy_init(tp, e_info_8168cp);
2833
2834         __rtl_hw_start_8168cp(tp);
2835 }
2836
2837 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2838 {
2839         rtl_set_def_aspm_entry_latency(tp);
2840
2841         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2842 }
2843
2844 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2845 {
2846         rtl_set_def_aspm_entry_latency(tp);
2847
2848         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2849
2850         /* Magic. */
2851         RTL_W8(tp, DBG_REG, 0x20);
2852 }
2853
2854 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2855 {
2856         static const struct ephy_info e_info_8168c_1[] = {
2857                 { 0x02, 0x0800, 0x1000 },
2858                 { 0x03, 0,      0x0002 },
2859                 { 0x06, 0x0080, 0x0000 }
2860         };
2861
2862         rtl_set_def_aspm_entry_latency(tp);
2863
2864         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2865
2866         rtl_ephy_init(tp, e_info_8168c_1);
2867
2868         __rtl_hw_start_8168cp(tp);
2869 }
2870
2871 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2872 {
2873         static const struct ephy_info e_info_8168c_2[] = {
2874                 { 0x01, 0,      0x0001 },
2875                 { 0x03, 0x0400, 0x0020 }
2876         };
2877
2878         rtl_set_def_aspm_entry_latency(tp);
2879
2880         rtl_ephy_init(tp, e_info_8168c_2);
2881
2882         __rtl_hw_start_8168cp(tp);
2883 }
2884
2885 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2886 {
2887         rtl_set_def_aspm_entry_latency(tp);
2888
2889         __rtl_hw_start_8168cp(tp);
2890 }
2891
2892 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2893 {
2894         rtl_set_def_aspm_entry_latency(tp);
2895
2896         rtl_disable_clock_request(tp);
2897 }
2898
2899 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2900 {
2901         static const struct ephy_info e_info_8168d_4[] = {
2902                 { 0x0b, 0x0000, 0x0048 },
2903                 { 0x19, 0x0020, 0x0050 },
2904                 { 0x0c, 0x0100, 0x0020 },
2905                 { 0x10, 0x0004, 0x0000 },
2906         };
2907
2908         rtl_set_def_aspm_entry_latency(tp);
2909
2910         rtl_ephy_init(tp, e_info_8168d_4);
2911
2912         rtl_enable_clock_request(tp);
2913 }
2914
2915 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2916 {
2917         static const struct ephy_info e_info_8168e_1[] = {
2918                 { 0x00, 0x0200, 0x0100 },
2919                 { 0x00, 0x0000, 0x0004 },
2920                 { 0x06, 0x0002, 0x0001 },
2921                 { 0x06, 0x0000, 0x0030 },
2922                 { 0x07, 0x0000, 0x2000 },
2923                 { 0x00, 0x0000, 0x0020 },
2924                 { 0x03, 0x5800, 0x2000 },
2925                 { 0x03, 0x0000, 0x0001 },
2926                 { 0x01, 0x0800, 0x1000 },
2927                 { 0x07, 0x0000, 0x4000 },
2928                 { 0x1e, 0x0000, 0x2000 },
2929                 { 0x19, 0xffff, 0xfe6c },
2930                 { 0x0a, 0x0000, 0x0040 }
2931         };
2932
2933         rtl_set_def_aspm_entry_latency(tp);
2934
2935         rtl_ephy_init(tp, e_info_8168e_1);
2936
2937         rtl_disable_clock_request(tp);
2938
2939         /* Reset tx FIFO pointer */
2940         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2941         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2942
2943         rtl_mod_config5(tp, Spi_en, 0);
2944 }
2945
2946 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2947 {
2948         static const struct ephy_info e_info_8168e_2[] = {
2949                 { 0x09, 0x0000, 0x0080 },
2950                 { 0x19, 0x0000, 0x0224 },
2951                 { 0x00, 0x0000, 0x0004 },
2952                 { 0x0c, 0x3df0, 0x0200 },
2953         };
2954
2955         rtl_set_def_aspm_entry_latency(tp);
2956
2957         rtl_ephy_init(tp, e_info_8168e_2);
2958
2959         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2960         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2961         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2962         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2963         rtl_reset_packet_filter(tp);
2964         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2965         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2966         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2967
2968         rtl_disable_clock_request(tp);
2969
2970         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2971
2972         rtl8168_config_eee_mac(tp);
2973
2974         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2975         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2976         rtl_mod_config5(tp, Spi_en, 0);
2977 }
2978
2979 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2980 {
2981         rtl_set_def_aspm_entry_latency(tp);
2982
2983         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2984         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2985         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2986         rtl_reset_packet_filter(tp);
2987         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2988         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2989         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2990         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2991
2992         rtl_disable_clock_request(tp);
2993
2994         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2995         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2996         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2997         rtl_mod_config5(tp, Spi_en, 0);
2998
2999         rtl8168_config_eee_mac(tp);
3000 }
3001
3002 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3003 {
3004         static const struct ephy_info e_info_8168f_1[] = {
3005                 { 0x06, 0x00c0, 0x0020 },
3006                 { 0x08, 0x0001, 0x0002 },
3007                 { 0x09, 0x0000, 0x0080 },
3008                 { 0x19, 0x0000, 0x0224 },
3009                 { 0x00, 0x0000, 0x0008 },
3010                 { 0x0c, 0x3df0, 0x0200 },
3011         };
3012
3013         rtl_hw_start_8168f(tp);
3014
3015         rtl_ephy_init(tp, e_info_8168f_1);
3016 }
3017
3018 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3019 {
3020         static const struct ephy_info e_info_8168f_1[] = {
3021                 { 0x06, 0x00c0, 0x0020 },
3022                 { 0x0f, 0xffff, 0x5200 },
3023                 { 0x19, 0x0000, 0x0224 },
3024                 { 0x00, 0x0000, 0x0008 },
3025                 { 0x0c, 0x3df0, 0x0200 },
3026         };
3027
3028         rtl_hw_start_8168f(tp);
3029         rtl_pcie_state_l2l3_disable(tp);
3030
3031         rtl_ephy_init(tp, e_info_8168f_1);
3032 }
3033
3034 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3035 {
3036         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3037         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3038
3039         rtl_set_def_aspm_entry_latency(tp);
3040
3041         rtl_reset_packet_filter(tp);
3042         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3043
3044         rtl_disable_rxdvgate(tp);
3045
3046         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3047         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3048
3049         rtl8168_config_eee_mac(tp);
3050
3051         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3052         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3053
3054         rtl_pcie_state_l2l3_disable(tp);
3055 }
3056
3057 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3058 {
3059         static const struct ephy_info e_info_8168g_1[] = {
3060                 { 0x00, 0x0008, 0x0000 },
3061                 { 0x0c, 0x3ff0, 0x0820 },
3062                 { 0x1e, 0x0000, 0x0001 },
3063                 { 0x19, 0x8000, 0x0000 }
3064         };
3065
3066         rtl_hw_start_8168g(tp);
3067         rtl_ephy_init(tp, e_info_8168g_1);
3068 }
3069
3070 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3071 {
3072         static const struct ephy_info e_info_8168g_2[] = {
3073                 { 0x00, 0x0008, 0x0000 },
3074                 { 0x0c, 0x3ff0, 0x0820 },
3075                 { 0x19, 0xffff, 0x7c00 },
3076                 { 0x1e, 0xffff, 0x20eb },
3077                 { 0x0d, 0xffff, 0x1666 },
3078                 { 0x00, 0xffff, 0x10a3 },
3079                 { 0x06, 0xffff, 0xf050 },
3080                 { 0x04, 0x0000, 0x0010 },
3081                 { 0x1d, 0x4000, 0x0000 },
3082         };
3083
3084         rtl_hw_start_8168g(tp);
3085         rtl_ephy_init(tp, e_info_8168g_2);
3086 }
3087
3088 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3089 {
3090         static const struct ephy_info e_info_8411_2[] = {
3091                 { 0x00, 0x0008, 0x0000 },
3092                 { 0x0c, 0x37d0, 0x0820 },
3093                 { 0x1e, 0x0000, 0x0001 },
3094                 { 0x19, 0x8021, 0x0000 },
3095                 { 0x1e, 0x0000, 0x2000 },
3096                 { 0x0d, 0x0100, 0x0200 },
3097                 { 0x00, 0x0000, 0x0080 },
3098                 { 0x06, 0x0000, 0x0010 },
3099                 { 0x04, 0x0000, 0x0010 },
3100                 { 0x1d, 0x0000, 0x4000 },
3101         };
3102
3103         rtl_hw_start_8168g(tp);
3104
3105         rtl_ephy_init(tp, e_info_8411_2);
3106
3107         /* The following Realtek-provided magic fixes an issue with the RX unit
3108          * getting confused after the PHY having been powered-down.
3109          */
3110         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3111         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3112         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3113         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3114         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3115         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3116         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3117         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3118         mdelay(3);
3119         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3120
3121         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3122         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3123         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3124         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3125         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3126         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3127         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3128         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3129         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3130         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3131         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3132         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3133         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3134         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3135         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3136         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3137         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3138         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3139         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3140         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3141         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3142         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3143         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3144         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3145         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3146         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3147         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3148         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3149         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3150         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3151         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3152         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3153         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3154         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3155         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3156         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3157         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3158         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3159         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3160         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3161         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3162         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3163         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3164         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3165         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3166         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3167         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3168         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3169         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3170         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3171         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3172         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3173         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3174         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3175         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3176         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3177         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3178         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3179         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3180         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3181         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3182         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3183         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3184         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3185         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3186         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3187         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3188         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3189         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3190         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3191         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3192         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3193         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3194         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3195         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3196         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3197         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3198         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3199         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3200         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3201         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3202         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3203         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3204         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3205         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3206         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3207         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3208         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3209         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3210         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3211         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3212         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3213         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3214         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3215         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3216         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3217         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3218         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3219         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3220         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3221         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3222         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3223         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3224         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3225         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3226         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3227         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3228         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3229         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3230         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3231         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3232
3233         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3234
3235         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3236         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3237         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3238         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3239         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3240         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3241         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3242 }
3243
3244 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3245 {
3246         static const struct ephy_info e_info_8168h_1[] = {
3247                 { 0x1e, 0x0800, 0x0001 },
3248                 { 0x1d, 0x0000, 0x0800 },
3249                 { 0x05, 0xffff, 0x2089 },
3250                 { 0x06, 0xffff, 0x5881 },
3251                 { 0x04, 0xffff, 0x854a },
3252                 { 0x01, 0xffff, 0x068b }
3253         };
3254         int rg_saw_cnt;
3255
3256         rtl_ephy_init(tp, e_info_8168h_1);
3257
3258         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3259         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3260
3261         rtl_set_def_aspm_entry_latency(tp);
3262
3263         rtl_reset_packet_filter(tp);
3264
3265         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3266
3267         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3268
3269         rtl_disable_rxdvgate(tp);
3270
3271         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3272         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3273
3274         rtl8168_config_eee_mac(tp);
3275
3276         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3277         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3278
3279         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3280
3281         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3282
3283         rtl_pcie_state_l2l3_disable(tp);
3284
3285         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3286         if (rg_saw_cnt > 0) {
3287                 u16 sw_cnt_1ms_ini;
3288
3289                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3290                 sw_cnt_1ms_ini &= 0x0fff;
3291                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3292         }
3293
3294         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3295         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3296         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3297         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3298
3299         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3300         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3301         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3302         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3303 }
3304
3305 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3306 {
3307         rtl8168ep_stop_cmac(tp);
3308
3309         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3310         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3311
3312         rtl_set_def_aspm_entry_latency(tp);
3313
3314         rtl_reset_packet_filter(tp);
3315
3316         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3317
3318         rtl_disable_rxdvgate(tp);
3319
3320         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3321         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3322
3323         rtl8168_config_eee_mac(tp);
3324
3325         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3326
3327         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3328
3329         rtl_pcie_state_l2l3_disable(tp);
3330 }
3331
3332 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3333 {
3334         static const struct ephy_info e_info_8168ep_3[] = {
3335                 { 0x00, 0x0000, 0x0080 },
3336                 { 0x0d, 0x0100, 0x0200 },
3337                 { 0x19, 0x8021, 0x0000 },
3338                 { 0x1e, 0x0000, 0x2000 },
3339         };
3340
3341         rtl_ephy_init(tp, e_info_8168ep_3);
3342
3343         rtl_hw_start_8168ep(tp);
3344
3345         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3346         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3347
3348         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3349         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3350         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3351 }
3352
3353 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3354 {
3355         static const struct ephy_info e_info_8117[] = {
3356                 { 0x19, 0x0040, 0x1100 },
3357                 { 0x59, 0x0040, 0x1100 },
3358         };
3359         int rg_saw_cnt;
3360
3361         rtl8168ep_stop_cmac(tp);
3362         rtl_ephy_init(tp, e_info_8117);
3363
3364         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3365         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3366
3367         rtl_set_def_aspm_entry_latency(tp);
3368
3369         rtl_reset_packet_filter(tp);
3370
3371         rtl_eri_set_bits(tp, 0xd4, 0x0010);
3372
3373         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3374
3375         rtl_disable_rxdvgate(tp);
3376
3377         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3378         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3379
3380         rtl8168_config_eee_mac(tp);
3381
3382         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3383         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3384
3385         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3386
3387         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3388
3389         rtl_pcie_state_l2l3_disable(tp);
3390
3391         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3392         if (rg_saw_cnt > 0) {
3393                 u16 sw_cnt_1ms_ini;
3394
3395                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3396                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3397         }
3398
3399         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3400         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3401         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3402         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3403
3404         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3405         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3406         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3407         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3408
3409         /* firmware is for MAC only */
3410         r8169_apply_firmware(tp);
3411 }
3412
3413 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3414 {
3415         static const struct ephy_info e_info_8102e_1[] = {
3416                 { 0x01, 0, 0x6e65 },
3417                 { 0x02, 0, 0x091f },
3418                 { 0x03, 0, 0xc2f9 },
3419                 { 0x06, 0, 0xafb5 },
3420                 { 0x07, 0, 0x0e00 },
3421                 { 0x19, 0, 0xec80 },
3422                 { 0x01, 0, 0x2e65 },
3423                 { 0x01, 0, 0x6e65 }
3424         };
3425         u8 cfg1;
3426
3427         rtl_set_def_aspm_entry_latency(tp);
3428
3429         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3430
3431         RTL_W8(tp, Config1,
3432                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3433         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3434
3435         cfg1 = RTL_R8(tp, Config1);
3436         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3437                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3438
3439         rtl_ephy_init(tp, e_info_8102e_1);
3440 }
3441
3442 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3443 {
3444         rtl_set_def_aspm_entry_latency(tp);
3445
3446         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3447         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3448 }
3449
3450 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3451 {
3452         rtl_hw_start_8102e_2(tp);
3453
3454         rtl_ephy_write(tp, 0x03, 0xc2f9);
3455 }
3456
3457 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3458 {
3459         static const struct ephy_info e_info_8401[] = {
3460                 { 0x01, 0xffff, 0x6fe5 },
3461                 { 0x03, 0xffff, 0x0599 },
3462                 { 0x06, 0xffff, 0xaf25 },
3463                 { 0x07, 0xffff, 0x8e68 },
3464         };
3465
3466         rtl_ephy_init(tp, e_info_8401);
3467         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3468 }
3469
3470 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3471 {
3472         static const struct ephy_info e_info_8105e_1[] = {
3473                 { 0x07, 0, 0x4000 },
3474                 { 0x19, 0, 0x0200 },
3475                 { 0x19, 0, 0x0020 },
3476                 { 0x1e, 0, 0x2000 },
3477                 { 0x03, 0, 0x0001 },
3478                 { 0x19, 0, 0x0100 },
3479                 { 0x19, 0, 0x0004 },
3480                 { 0x0a, 0, 0x0020 }
3481         };
3482
3483         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3484         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3485
3486         /* Disable Early Tally Counter */
3487         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3488
3489         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3490         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3491
3492         rtl_ephy_init(tp, e_info_8105e_1);
3493
3494         rtl_pcie_state_l2l3_disable(tp);
3495 }
3496
3497 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3498 {
3499         rtl_hw_start_8105e_1(tp);
3500         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3501 }
3502
3503 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3504 {
3505         static const struct ephy_info e_info_8402[] = {
3506                 { 0x19, 0xffff, 0xff64 },
3507                 { 0x1e, 0, 0x4000 }
3508         };
3509
3510         rtl_set_def_aspm_entry_latency(tp);
3511
3512         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3513         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3514
3515         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3516
3517         rtl_ephy_init(tp, e_info_8402);
3518
3519         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3520         rtl_reset_packet_filter(tp);
3521         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3522         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3523         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3524
3525         /* disable EEE */
3526         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3527
3528         rtl_pcie_state_l2l3_disable(tp);
3529 }
3530
3531 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3532 {
3533         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3534         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3535
3536         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3537         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3538         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3539
3540         /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3541         rtl_set_aspm_entry_latency(tp, 0x2f);
3542
3543         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3544
3545         /* disable EEE */
3546         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3547
3548         rtl_pcie_state_l2l3_disable(tp);
3549 }
3550
3551 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3552 {
3553         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3554 }
3555
3556 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3557 {
3558         rtl_pcie_state_l2l3_disable(tp);
3559
3560         RTL_W16(tp, 0x382, 0x221b);
3561         RTL_W8(tp, 0x4500, 0);
3562         RTL_W16(tp, 0x4800, 0);
3563
3564         /* disable UPS */
3565         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3566
3567         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3568
3569         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3570         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3571
3572         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3573         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3574         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3575
3576         /* disable new tx descriptor format */
3577         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3578
3579         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3580                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3581         else
3582                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3583
3584         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3585                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3586         else
3587                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3588
3589         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3590         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3591         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3592         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3593         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3594         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3595         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3596         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3597         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3598
3599         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3600         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3601         udelay(1);
3602         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3603         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3604
3605         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3606
3607         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3608
3609         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3610                 rtl8125b_config_eee_mac(tp);
3611         else
3612                 rtl8125a_config_eee_mac(tp);
3613
3614         rtl_disable_rxdvgate(tp);
3615 }
3616
3617 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3618 {
3619         static const struct ephy_info e_info_8125a_2[] = {
3620                 { 0x04, 0xffff, 0xd000 },
3621                 { 0x0a, 0xffff, 0x8653 },
3622                 { 0x23, 0xffff, 0xab66 },
3623                 { 0x20, 0xffff, 0x9455 },
3624                 { 0x21, 0xffff, 0x99ff },
3625                 { 0x29, 0xffff, 0xfe04 },
3626
3627                 { 0x44, 0xffff, 0xd000 },
3628                 { 0x4a, 0xffff, 0x8653 },
3629                 { 0x63, 0xffff, 0xab66 },
3630                 { 0x60, 0xffff, 0x9455 },
3631                 { 0x61, 0xffff, 0x99ff },
3632                 { 0x69, 0xffff, 0xfe04 },
3633         };
3634
3635         rtl_set_def_aspm_entry_latency(tp);
3636         rtl_ephy_init(tp, e_info_8125a_2);
3637         rtl_hw_start_8125_common(tp);
3638 }
3639
3640 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3641 {
3642         static const struct ephy_info e_info_8125b[] = {
3643                 { 0x0b, 0xffff, 0xa908 },
3644                 { 0x1e, 0xffff, 0x20eb },
3645                 { 0x4b, 0xffff, 0xa908 },
3646                 { 0x5e, 0xffff, 0x20eb },
3647                 { 0x22, 0x0030, 0x0020 },
3648                 { 0x62, 0x0030, 0x0020 },
3649         };
3650
3651         rtl_set_def_aspm_entry_latency(tp);
3652         rtl_ephy_init(tp, e_info_8125b);
3653         rtl_hw_start_8125_common(tp);
3654 }
3655
3656 static void rtl_hw_config(struct rtl8169_private *tp)
3657 {
3658         static const rtl_generic_fct hw_configs[] = {
3659                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3660                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3661                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3662                 [RTL_GIGA_MAC_VER_10] = NULL,
3663                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3664                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3665                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3666                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3667                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3668                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3669                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3670                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3671                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3672                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3673                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3674                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3675                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3676                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3677                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3678                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3679                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3680                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3681                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3682                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3683                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3684                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3685                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3686                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3687                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3688                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3689                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3690                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3691                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3692                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3693                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3694                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3695                 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3696                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3697                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3698         };
3699
3700         if (hw_configs[tp->mac_version])
3701                 hw_configs[tp->mac_version](tp);
3702 }
3703
3704 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3705 {
3706         int i;
3707
3708         /* disable interrupt coalescing */
3709         for (i = 0xa00; i < 0xb00; i += 4)
3710                 RTL_W32(tp, i, 0);
3711
3712         rtl_hw_config(tp);
3713 }
3714
3715 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3716 {
3717         if (rtl_is_8168evl_up(tp))
3718                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3719         else
3720                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3721
3722         rtl_hw_config(tp);
3723
3724         /* disable interrupt coalescing */
3725         RTL_W16(tp, IntrMitigate, 0x0000);
3726 }
3727
3728 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3729 {
3730         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3731
3732         tp->cp_cmd |= PCIMulRW;
3733
3734         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3735             tp->mac_version == RTL_GIGA_MAC_VER_03)
3736                 tp->cp_cmd |= EnAnaPLL;
3737
3738         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3739
3740         rtl8169_set_magic_reg(tp);
3741
3742         /* disable interrupt coalescing */
3743         RTL_W16(tp, IntrMitigate, 0x0000);
3744 }
3745
3746 static void rtl_hw_start(struct  rtl8169_private *tp)
3747 {
3748         rtl_unlock_config_regs(tp);
3749         /* disable aspm and clock request before ephy access */
3750         rtl_hw_aspm_clkreq_enable(tp, false);
3751         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3752
3753         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3754                 rtl_hw_start_8169(tp);
3755         else if (rtl_is_8125(tp))
3756                 rtl_hw_start_8125(tp);
3757         else
3758                 rtl_hw_start_8168(tp);
3759
3760         rtl_enable_exit_l1(tp);
3761         rtl_hw_aspm_clkreq_enable(tp, true);
3762         rtl_set_rx_max_size(tp);
3763         rtl_set_rx_tx_desc_registers(tp);
3764         rtl_lock_config_regs(tp);
3765
3766         rtl_jumbo_config(tp);
3767
3768         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3769         rtl_pci_commit(tp);
3770
3771         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3772         rtl_init_rxcfg(tp);
3773         rtl_set_tx_config_registers(tp);
3774         rtl_set_rx_config_features(tp, tp->dev->features);
3775         rtl_set_rx_mode(tp->dev);
3776         rtl_irq_enable(tp);
3777 }
3778
3779 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3780 {
3781         struct rtl8169_private *tp = netdev_priv(dev);
3782
3783         dev->mtu = new_mtu;
3784         netdev_update_features(dev);
3785         rtl_jumbo_config(tp);
3786
3787         switch (tp->mac_version) {
3788         case RTL_GIGA_MAC_VER_61:
3789         case RTL_GIGA_MAC_VER_63:
3790                 rtl8125_set_eee_txidle_timer(tp);
3791                 break;
3792         default:
3793                 break;
3794         }
3795
3796         return 0;
3797 }
3798
3799 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3800 {
3801         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3802
3803         desc->opts2 = 0;
3804         /* Force memory writes to complete before releasing descriptor */
3805         dma_wmb();
3806         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3807 }
3808
3809 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3810                                           struct RxDesc *desc)
3811 {
3812         struct device *d = tp_to_dev(tp);
3813         int node = dev_to_node(d);
3814         dma_addr_t mapping;
3815         struct page *data;
3816
3817         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3818         if (!data)
3819                 return NULL;
3820
3821         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3822         if (unlikely(dma_mapping_error(d, mapping))) {
3823                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3824                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3825                 return NULL;
3826         }
3827
3828         desc->addr = cpu_to_le64(mapping);
3829         rtl8169_mark_to_asic(desc);
3830
3831         return data;
3832 }
3833
3834 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3835 {
3836         int i;
3837
3838         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3839                 dma_unmap_page(tp_to_dev(tp),
3840                                le64_to_cpu(tp->RxDescArray[i].addr),
3841                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3842                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3843                 tp->Rx_databuff[i] = NULL;
3844                 tp->RxDescArray[i].addr = 0;
3845                 tp->RxDescArray[i].opts1 = 0;
3846         }
3847 }
3848
3849 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3850 {
3851         int i;
3852
3853         for (i = 0; i < NUM_RX_DESC; i++) {
3854                 struct page *data;
3855
3856                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3857                 if (!data) {
3858                         rtl8169_rx_clear(tp);
3859                         return -ENOMEM;
3860                 }
3861                 tp->Rx_databuff[i] = data;
3862         }
3863
3864         /* mark as last descriptor in the ring */
3865         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3866
3867         return 0;
3868 }
3869
3870 static int rtl8169_init_ring(struct rtl8169_private *tp)
3871 {
3872         rtl8169_init_ring_indexes(tp);
3873
3874         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3875         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3876
3877         return rtl8169_rx_fill(tp);
3878 }
3879
3880 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3881 {
3882         struct ring_info *tx_skb = tp->tx_skb + entry;
3883         struct TxDesc *desc = tp->TxDescArray + entry;
3884
3885         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3886                          DMA_TO_DEVICE);
3887         memset(desc, 0, sizeof(*desc));
3888         memset(tx_skb, 0, sizeof(*tx_skb));
3889 }
3890
3891 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3892                                    unsigned int n)
3893 {
3894         unsigned int i;
3895
3896         for (i = 0; i < n; i++) {
3897                 unsigned int entry = (start + i) % NUM_TX_DESC;
3898                 struct ring_info *tx_skb = tp->tx_skb + entry;
3899                 unsigned int len = tx_skb->len;
3900
3901                 if (len) {
3902                         struct sk_buff *skb = tx_skb->skb;
3903
3904                         rtl8169_unmap_tx_skb(tp, entry);
3905                         if (skb)
3906                                 dev_consume_skb_any(skb);
3907                 }
3908         }
3909 }
3910
3911 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3912 {
3913         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3914         netdev_reset_queue(tp->dev);
3915 }
3916
3917 static void rtl8169_cleanup(struct rtl8169_private *tp)
3918 {
3919         napi_disable(&tp->napi);
3920
3921         /* Give a racing hard_start_xmit a few cycles to complete. */
3922         synchronize_net();
3923
3924         /* Disable interrupts */
3925         rtl8169_irq_mask_and_ack(tp);
3926
3927         rtl_rx_close(tp);
3928
3929         switch (tp->mac_version) {
3930         case RTL_GIGA_MAC_VER_28:
3931         case RTL_GIGA_MAC_VER_31:
3932                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3933                 break;
3934         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3935                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3936                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3937                 break;
3938         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3939                 rtl_enable_rxdvgate(tp);
3940                 fsleep(2000);
3941                 break;
3942         default:
3943                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3944                 fsleep(100);
3945                 break;
3946         }
3947
3948         rtl_hw_reset(tp);
3949
3950         rtl8169_tx_clear(tp);
3951         rtl8169_init_ring_indexes(tp);
3952 }
3953
3954 static void rtl_reset_work(struct rtl8169_private *tp)
3955 {
3956         int i;
3957
3958         netif_stop_queue(tp->dev);
3959
3960         rtl8169_cleanup(tp);
3961
3962         for (i = 0; i < NUM_RX_DESC; i++)
3963                 rtl8169_mark_to_asic(tp->RxDescArray + i);
3964
3965         napi_enable(&tp->napi);
3966         rtl_hw_start(tp);
3967 }
3968
3969 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3970 {
3971         struct rtl8169_private *tp = netdev_priv(dev);
3972
3973         rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
3974 }
3975
3976 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
3977                           void *addr, unsigned int entry, bool desc_own)
3978 {
3979         struct TxDesc *txd = tp->TxDescArray + entry;
3980         struct device *d = tp_to_dev(tp);
3981         dma_addr_t mapping;
3982         u32 opts1;
3983         int ret;
3984
3985         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3986         ret = dma_mapping_error(d, mapping);
3987         if (unlikely(ret)) {
3988                 if (net_ratelimit())
3989                         netdev_err(tp->dev, "Failed to map TX data!\n");
3990                 return ret;
3991         }
3992
3993         txd->addr = cpu_to_le64(mapping);
3994         txd->opts2 = cpu_to_le32(opts[1]);
3995
3996         opts1 = opts[0] | len;
3997         if (entry == NUM_TX_DESC - 1)
3998                 opts1 |= RingEnd;
3999         if (desc_own)
4000                 opts1 |= DescOwn;
4001         txd->opts1 = cpu_to_le32(opts1);
4002
4003         tp->tx_skb[entry].len = len;
4004
4005         return 0;
4006 }
4007
4008 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4009                               const u32 *opts, unsigned int entry)
4010 {
4011         struct skb_shared_info *info = skb_shinfo(skb);
4012         unsigned int cur_frag;
4013
4014         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4015                 const skb_frag_t *frag = info->frags + cur_frag;
4016                 void *addr = skb_frag_address(frag);
4017                 u32 len = skb_frag_size(frag);
4018
4019                 entry = (entry + 1) % NUM_TX_DESC;
4020
4021                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4022                         goto err_out;
4023         }
4024
4025         return 0;
4026
4027 err_out:
4028         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4029         return -EIO;
4030 }
4031
4032 static bool rtl_skb_is_udp(struct sk_buff *skb)
4033 {
4034         int no = skb_network_offset(skb);
4035         struct ipv6hdr *i6h, _i6h;
4036         struct iphdr *ih, _ih;
4037
4038         switch (vlan_get_protocol(skb)) {
4039         case htons(ETH_P_IP):
4040                 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4041                 return ih && ih->protocol == IPPROTO_UDP;
4042         case htons(ETH_P_IPV6):
4043                 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4044                 return i6h && i6h->nexthdr == IPPROTO_UDP;
4045         default:
4046                 return false;
4047         }
4048 }
4049
4050 #define RTL_MIN_PATCH_LEN       47
4051
4052 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4053 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4054                                             struct sk_buff *skb)
4055 {
4056         unsigned int padto = 0, len = skb->len;
4057
4058         if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4059             rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4060                 unsigned int trans_data_len = skb_tail_pointer(skb) -
4061                                               skb_transport_header(skb);
4062
4063                 if (trans_data_len >= offsetof(struct udphdr, len) &&
4064                     trans_data_len < RTL_MIN_PATCH_LEN) {
4065                         u16 dest = ntohs(udp_hdr(skb)->dest);
4066
4067                         /* dest is a standard PTP port */
4068                         if (dest == 319 || dest == 320)
4069                                 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4070                 }
4071
4072                 if (trans_data_len < sizeof(struct udphdr))
4073                         padto = max_t(unsigned int, padto,
4074                                       len + sizeof(struct udphdr) - trans_data_len);
4075         }
4076
4077         return padto;
4078 }
4079
4080 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4081                                            struct sk_buff *skb)
4082 {
4083         unsigned int padto;
4084
4085         padto = rtl8125_quirk_udp_padto(tp, skb);
4086
4087         switch (tp->mac_version) {
4088         case RTL_GIGA_MAC_VER_34:
4089         case RTL_GIGA_MAC_VER_61:
4090         case RTL_GIGA_MAC_VER_63:
4091                 padto = max_t(unsigned int, padto, ETH_ZLEN);
4092                 break;
4093         default:
4094                 break;
4095         }
4096
4097         return padto;
4098 }
4099
4100 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4101 {
4102         u32 mss = skb_shinfo(skb)->gso_size;
4103
4104         if (mss) {
4105                 opts[0] |= TD_LSO;
4106                 opts[0] |= mss << TD0_MSS_SHIFT;
4107         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4108                 const struct iphdr *ip = ip_hdr(skb);
4109
4110                 if (ip->protocol == IPPROTO_TCP)
4111                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4112                 else if (ip->protocol == IPPROTO_UDP)
4113                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4114                 else
4115                         WARN_ON_ONCE(1);
4116         }
4117 }
4118
4119 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4120                                 struct sk_buff *skb, u32 *opts)
4121 {
4122         struct skb_shared_info *shinfo = skb_shinfo(skb);
4123         u32 mss = shinfo->gso_size;
4124
4125         if (mss) {
4126                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4127                         opts[0] |= TD1_GTSENV4;
4128                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4129                         if (skb_cow_head(skb, 0))
4130                                 return false;
4131
4132                         tcp_v6_gso_csum_prep(skb);
4133                         opts[0] |= TD1_GTSENV6;
4134                 } else {
4135                         WARN_ON_ONCE(1);
4136                 }
4137
4138                 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4139                 opts[1] |= mss << TD1_MSS_SHIFT;
4140         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4141                 u8 ip_protocol;
4142
4143                 switch (vlan_get_protocol(skb)) {
4144                 case htons(ETH_P_IP):
4145                         opts[1] |= TD1_IPv4_CS;
4146                         ip_protocol = ip_hdr(skb)->protocol;
4147                         break;
4148
4149                 case htons(ETH_P_IPV6):
4150                         opts[1] |= TD1_IPv6_CS;
4151                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4152                         break;
4153
4154                 default:
4155                         ip_protocol = IPPROTO_RAW;
4156                         break;
4157                 }
4158
4159                 if (ip_protocol == IPPROTO_TCP)
4160                         opts[1] |= TD1_TCP_CS;
4161                 else if (ip_protocol == IPPROTO_UDP)
4162                         opts[1] |= TD1_UDP_CS;
4163                 else
4164                         WARN_ON_ONCE(1);
4165
4166                 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4167         } else {
4168                 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4169
4170                 /* skb_padto would free the skb on error */
4171                 return !__skb_put_padto(skb, padto, false);
4172         }
4173
4174         return true;
4175 }
4176
4177 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4178 {
4179         return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4180 }
4181
4182 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4183 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4184 {
4185         switch (tp->mac_version) {
4186         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4187         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4188                 return false;
4189         default:
4190                 return true;
4191         }
4192 }
4193
4194 static void rtl8169_doorbell(struct rtl8169_private *tp)
4195 {
4196         if (rtl_is_8125(tp))
4197                 RTL_W16(tp, TxPoll_8125, BIT(0));
4198         else
4199                 RTL_W8(tp, TxPoll, NPQ);
4200 }
4201
4202 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4203                                       struct net_device *dev)
4204 {
4205         unsigned int frags = skb_shinfo(skb)->nr_frags;
4206         struct rtl8169_private *tp = netdev_priv(dev);
4207         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4208         struct TxDesc *txd_first, *txd_last;
4209         bool stop_queue, door_bell;
4210         u32 opts[2];
4211
4212         if (unlikely(!rtl_tx_slots_avail(tp))) {
4213                 if (net_ratelimit())
4214                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4215                 goto err_stop_0;
4216         }
4217
4218         opts[1] = rtl8169_tx_vlan_tag(skb);
4219         opts[0] = 0;
4220
4221         if (!rtl_chip_supports_csum_v2(tp))
4222                 rtl8169_tso_csum_v1(skb, opts);
4223         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4224                 goto err_dma_0;
4225
4226         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4227                                     entry, false)))
4228                 goto err_dma_0;
4229
4230         txd_first = tp->TxDescArray + entry;
4231
4232         if (frags) {
4233                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4234                         goto err_dma_1;
4235                 entry = (entry + frags) % NUM_TX_DESC;
4236         }
4237
4238         txd_last = tp->TxDescArray + entry;
4239         txd_last->opts1 |= cpu_to_le32(LastFrag);
4240         tp->tx_skb[entry].skb = skb;
4241
4242         skb_tx_timestamp(skb);
4243
4244         /* Force memory writes to complete before releasing descriptor */
4245         dma_wmb();
4246
4247         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4248
4249         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4250
4251         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4252         smp_wmb();
4253
4254         WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4255
4256         stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4257                                                 R8169_TX_STOP_THRS,
4258                                                 R8169_TX_START_THRS);
4259         if (door_bell || stop_queue)
4260                 rtl8169_doorbell(tp);
4261
4262         return NETDEV_TX_OK;
4263
4264 err_dma_1:
4265         rtl8169_unmap_tx_skb(tp, entry);
4266 err_dma_0:
4267         dev_kfree_skb_any(skb);
4268         dev->stats.tx_dropped++;
4269         return NETDEV_TX_OK;
4270
4271 err_stop_0:
4272         netif_stop_queue(dev);
4273         dev->stats.tx_dropped++;
4274         return NETDEV_TX_BUSY;
4275 }
4276
4277 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4278 {
4279         struct skb_shared_info *info = skb_shinfo(skb);
4280         unsigned int nr_frags = info->nr_frags;
4281
4282         if (!nr_frags)
4283                 return UINT_MAX;
4284
4285         return skb_frag_size(info->frags + nr_frags - 1);
4286 }
4287
4288 /* Workaround for hw issues with TSO on RTL8168evl */
4289 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4290                                             netdev_features_t features)
4291 {
4292         /* IPv4 header has options field */
4293         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4294             ip_hdrlen(skb) > sizeof(struct iphdr))
4295                 features &= ~NETIF_F_ALL_TSO;
4296
4297         /* IPv4 TCP header has options field */
4298         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4299                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4300                 features &= ~NETIF_F_ALL_TSO;
4301
4302         else if (rtl_last_frag_len(skb) <= 6)
4303                 features &= ~NETIF_F_ALL_TSO;
4304
4305         return features;
4306 }
4307
4308 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4309                                                 struct net_device *dev,
4310                                                 netdev_features_t features)
4311 {
4312         struct rtl8169_private *tp = netdev_priv(dev);
4313
4314         if (skb_is_gso(skb)) {
4315                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4316                         features = rtl8168evl_fix_tso(skb, features);
4317
4318                 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4319                     rtl_chip_supports_csum_v2(tp))
4320                         features &= ~NETIF_F_ALL_TSO;
4321         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4322                 /* work around hw bug on some chip versions */
4323                 if (skb->len < ETH_ZLEN)
4324                         features &= ~NETIF_F_CSUM_MASK;
4325
4326                 if (rtl_quirk_packet_padto(tp, skb))
4327                         features &= ~NETIF_F_CSUM_MASK;
4328
4329                 if (skb_transport_offset(skb) > TCPHO_MAX &&
4330                     rtl_chip_supports_csum_v2(tp))
4331                         features &= ~NETIF_F_CSUM_MASK;
4332         }
4333
4334         return vlan_features_check(skb, features);
4335 }
4336
4337 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4338 {
4339         struct rtl8169_private *tp = netdev_priv(dev);
4340         struct pci_dev *pdev = tp->pci_dev;
4341         int pci_status_errs;
4342         u16 pci_cmd;
4343
4344         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4345
4346         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4347
4348         if (net_ratelimit())
4349                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4350                            pci_cmd, pci_status_errs);
4351
4352         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4353 }
4354
4355 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4356                    int budget)
4357 {
4358         unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4359         struct sk_buff *skb;
4360
4361         dirty_tx = tp->dirty_tx;
4362
4363         while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4364                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4365                 u32 status;
4366
4367                 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4368                 if (status & DescOwn)
4369                         break;
4370
4371                 skb = tp->tx_skb[entry].skb;
4372                 rtl8169_unmap_tx_skb(tp, entry);
4373
4374                 if (skb) {
4375                         pkts_compl++;
4376                         bytes_compl += skb->len;
4377                         napi_consume_skb(skb, budget);
4378                 }
4379                 dirty_tx++;
4380         }
4381
4382         if (tp->dirty_tx != dirty_tx) {
4383                 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4384                 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4385
4386                 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4387                                               rtl_tx_slots_avail(tp),
4388                                               R8169_TX_START_THRS);
4389                 /*
4390                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4391                  * too close. Let's kick an extra TxPoll request when a burst
4392                  * of start_xmit activity is detected (if it is not detected,
4393                  * it is slow enough). -- FR
4394                  * If skb is NULL then we come here again once a tx irq is
4395                  * triggered after the last fragment is marked transmitted.
4396                  */
4397                 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4398                         rtl8169_doorbell(tp);
4399         }
4400 }
4401
4402 static inline int rtl8169_fragmented_frame(u32 status)
4403 {
4404         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4405 }
4406
4407 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4408 {
4409         u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4410
4411         if (status == RxProtoTCP || status == RxProtoUDP)
4412                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4413         else
4414                 skb_checksum_none_assert(skb);
4415 }
4416
4417 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4418 {
4419         struct device *d = tp_to_dev(tp);
4420         int count;
4421
4422         for (count = 0; count < budget; count++, tp->cur_rx++) {
4423                 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4424                 struct RxDesc *desc = tp->RxDescArray + entry;
4425                 struct sk_buff *skb;
4426                 const void *rx_buf;
4427                 dma_addr_t addr;
4428                 u32 status;
4429
4430                 status = le32_to_cpu(READ_ONCE(desc->opts1));
4431                 if (status & DescOwn)
4432                         break;
4433
4434                 /* This barrier is needed to keep us from reading
4435                  * any other fields out of the Rx descriptor until
4436                  * we know the status of DescOwn
4437                  */
4438                 dma_rmb();
4439
4440                 if (unlikely(status & RxRES)) {
4441                         if (net_ratelimit())
4442                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4443                                             status);
4444                         dev->stats.rx_errors++;
4445                         if (status & (RxRWT | RxRUNT))
4446                                 dev->stats.rx_length_errors++;
4447                         if (status & RxCRC)
4448                                 dev->stats.rx_crc_errors++;
4449
4450                         if (!(dev->features & NETIF_F_RXALL))
4451                                 goto release_descriptor;
4452                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4453                                 goto release_descriptor;
4454                 }
4455
4456                 pkt_size = status & GENMASK(13, 0);
4457                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4458                         pkt_size -= ETH_FCS_LEN;
4459
4460                 /* The driver does not support incoming fragmented frames.
4461                  * They are seen as a symptom of over-mtu sized frames.
4462                  */
4463                 if (unlikely(rtl8169_fragmented_frame(status))) {
4464                         dev->stats.rx_dropped++;
4465                         dev->stats.rx_length_errors++;
4466                         goto release_descriptor;
4467                 }
4468
4469                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4470                 if (unlikely(!skb)) {
4471                         dev->stats.rx_dropped++;
4472                         goto release_descriptor;
4473                 }
4474
4475                 addr = le64_to_cpu(desc->addr);
4476                 rx_buf = page_address(tp->Rx_databuff[entry]);
4477
4478                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4479                 prefetch(rx_buf);
4480                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4481                 skb->tail += pkt_size;
4482                 skb->len = pkt_size;
4483                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4484
4485                 rtl8169_rx_csum(skb, status);
4486                 skb->protocol = eth_type_trans(skb, dev);
4487
4488                 rtl8169_rx_vlan_tag(desc, skb);
4489
4490                 if (skb->pkt_type == PACKET_MULTICAST)
4491                         dev->stats.multicast++;
4492
4493                 napi_gro_receive(&tp->napi, skb);
4494
4495                 dev_sw_netstats_rx_add(dev, pkt_size);
4496 release_descriptor:
4497                 rtl8169_mark_to_asic(desc);
4498         }
4499
4500         return count;
4501 }
4502
4503 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4504 {
4505         struct rtl8169_private *tp = dev_instance;
4506         u32 status = rtl_get_events(tp);
4507
4508         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4509                 return IRQ_NONE;
4510
4511         if (unlikely(status & SYSErr)) {
4512                 rtl8169_pcierr_interrupt(tp->dev);
4513                 goto out;
4514         }
4515
4516         if (status & LinkChg)
4517                 phy_mac_interrupt(tp->phydev);
4518
4519         if (unlikely(status & RxFIFOOver &&
4520             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4521                 netif_stop_queue(tp->dev);
4522                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4523         }
4524
4525         if (napi_schedule_prep(&tp->napi)) {
4526                 rtl_irq_disable(tp);
4527                 __napi_schedule(&tp->napi);
4528         }
4529 out:
4530         rtl_ack_events(tp, status);
4531
4532         return IRQ_HANDLED;
4533 }
4534
4535 static void rtl_task(struct work_struct *work)
4536 {
4537         struct rtl8169_private *tp =
4538                 container_of(work, struct rtl8169_private, wk.work);
4539         int ret;
4540
4541         rtnl_lock();
4542
4543         if (!netif_running(tp->dev) ||
4544             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4545                 goto out_unlock;
4546
4547         if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4548                 /* if chip isn't accessible, reset bus to revive it */
4549                 if (RTL_R32(tp, TxConfig) == ~0) {
4550                         ret = pci_reset_bus(tp->pci_dev);
4551                         if (ret < 0) {
4552                                 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4553                                 netif_device_detach(tp->dev);
4554                                 goto out_unlock;
4555                         }
4556                 }
4557
4558                 /* ASPM compatibility issues are a typical reason for tx timeouts */
4559                 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4560                                                           PCIE_LINK_STATE_L0S);
4561                 if (!ret)
4562                         netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4563                 goto reset;
4564         }
4565
4566         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4567 reset:
4568                 rtl_reset_work(tp);
4569                 netif_wake_queue(tp->dev);
4570         }
4571 out_unlock:
4572         rtnl_unlock();
4573 }
4574
4575 static int rtl8169_poll(struct napi_struct *napi, int budget)
4576 {
4577         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4578         struct net_device *dev = tp->dev;
4579         int work_done;
4580
4581         rtl_tx(dev, tp, budget);
4582
4583         work_done = rtl_rx(dev, tp, budget);
4584
4585         if (work_done < budget && napi_complete_done(napi, work_done))
4586                 rtl_irq_enable(tp);
4587
4588         return work_done;
4589 }
4590
4591 static void r8169_phylink_handler(struct net_device *ndev)
4592 {
4593         struct rtl8169_private *tp = netdev_priv(ndev);
4594         struct device *d = tp_to_dev(tp);
4595
4596         if (netif_carrier_ok(ndev)) {
4597                 rtl_link_chg_patch(tp);
4598                 pm_request_resume(d);
4599         } else {
4600                 pm_runtime_idle(d);
4601         }
4602
4603         phy_print_status(tp->phydev);
4604 }
4605
4606 static int r8169_phy_connect(struct rtl8169_private *tp)
4607 {
4608         struct phy_device *phydev = tp->phydev;
4609         phy_interface_t phy_mode;
4610         int ret;
4611
4612         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4613                    PHY_INTERFACE_MODE_MII;
4614
4615         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4616                                  phy_mode);
4617         if (ret)
4618                 return ret;
4619
4620         if (!tp->supports_gmii)
4621                 phy_set_max_speed(phydev, SPEED_100);
4622
4623         phy_attached_info(phydev);
4624
4625         return 0;
4626 }
4627
4628 static void rtl8169_down(struct rtl8169_private *tp)
4629 {
4630         /* Clear all task flags */
4631         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4632
4633         phy_stop(tp->phydev);
4634
4635         rtl8169_update_counters(tp);
4636
4637         pci_clear_master(tp->pci_dev);
4638         rtl_pci_commit(tp);
4639
4640         rtl8169_cleanup(tp);
4641         rtl_disable_exit_l1(tp);
4642         rtl_prepare_power_down(tp);
4643 }
4644
4645 static void rtl8169_up(struct rtl8169_private *tp)
4646 {
4647         pci_set_master(tp->pci_dev);
4648         phy_init_hw(tp->phydev);
4649         phy_resume(tp->phydev);
4650         rtl8169_init_phy(tp);
4651         napi_enable(&tp->napi);
4652         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4653         rtl_reset_work(tp);
4654
4655         phy_start(tp->phydev);
4656 }
4657
4658 static int rtl8169_close(struct net_device *dev)
4659 {
4660         struct rtl8169_private *tp = netdev_priv(dev);
4661         struct pci_dev *pdev = tp->pci_dev;
4662
4663         pm_runtime_get_sync(&pdev->dev);
4664
4665         netif_stop_queue(dev);
4666         rtl8169_down(tp);
4667         rtl8169_rx_clear(tp);
4668
4669         cancel_work_sync(&tp->wk.work);
4670
4671         free_irq(tp->irq, tp);
4672
4673         phy_disconnect(tp->phydev);
4674
4675         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4676                           tp->RxPhyAddr);
4677         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4678                           tp->TxPhyAddr);
4679         tp->TxDescArray = NULL;
4680         tp->RxDescArray = NULL;
4681
4682         pm_runtime_put_sync(&pdev->dev);
4683
4684         return 0;
4685 }
4686
4687 #ifdef CONFIG_NET_POLL_CONTROLLER
4688 static void rtl8169_netpoll(struct net_device *dev)
4689 {
4690         struct rtl8169_private *tp = netdev_priv(dev);
4691
4692         rtl8169_interrupt(tp->irq, tp);
4693 }
4694 #endif
4695
4696 static int rtl_open(struct net_device *dev)
4697 {
4698         struct rtl8169_private *tp = netdev_priv(dev);
4699         struct pci_dev *pdev = tp->pci_dev;
4700         unsigned long irqflags;
4701         int retval = -ENOMEM;
4702
4703         pm_runtime_get_sync(&pdev->dev);
4704
4705         /*
4706          * Rx and Tx descriptors needs 256 bytes alignment.
4707          * dma_alloc_coherent provides more.
4708          */
4709         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4710                                              &tp->TxPhyAddr, GFP_KERNEL);
4711         if (!tp->TxDescArray)
4712                 goto out;
4713
4714         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4715                                              &tp->RxPhyAddr, GFP_KERNEL);
4716         if (!tp->RxDescArray)
4717                 goto err_free_tx_0;
4718
4719         retval = rtl8169_init_ring(tp);
4720         if (retval < 0)
4721                 goto err_free_rx_1;
4722
4723         rtl_request_firmware(tp);
4724
4725         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4726         retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4727         if (retval < 0)
4728                 goto err_release_fw_2;
4729
4730         retval = r8169_phy_connect(tp);
4731         if (retval)
4732                 goto err_free_irq;
4733
4734         rtl8169_up(tp);
4735         rtl8169_init_counter_offsets(tp);
4736         netif_start_queue(dev);
4737 out:
4738         pm_runtime_put_sync(&pdev->dev);
4739
4740         return retval;
4741
4742 err_free_irq:
4743         free_irq(tp->irq, tp);
4744 err_release_fw_2:
4745         rtl_release_firmware(tp);
4746         rtl8169_rx_clear(tp);
4747 err_free_rx_1:
4748         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4749                           tp->RxPhyAddr);
4750         tp->RxDescArray = NULL;
4751 err_free_tx_0:
4752         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4753                           tp->TxPhyAddr);
4754         tp->TxDescArray = NULL;
4755         goto out;
4756 }
4757
4758 static void
4759 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4760 {
4761         struct rtl8169_private *tp = netdev_priv(dev);
4762         struct pci_dev *pdev = tp->pci_dev;
4763         struct rtl8169_counters *counters = tp->counters;
4764
4765         pm_runtime_get_noresume(&pdev->dev);
4766
4767         netdev_stats_to_stats64(stats, &dev->stats);
4768         dev_fetch_sw_netstats(stats, dev->tstats);
4769
4770         /*
4771          * Fetch additional counter values missing in stats collected by driver
4772          * from tally counters.
4773          */
4774         if (pm_runtime_active(&pdev->dev))
4775                 rtl8169_update_counters(tp);
4776
4777         /*
4778          * Subtract values fetched during initalization.
4779          * See rtl8169_init_counter_offsets for a description why we do that.
4780          */
4781         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4782                 le64_to_cpu(tp->tc_offset.tx_errors);
4783         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4784                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4785         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4786                 le16_to_cpu(tp->tc_offset.tx_aborted);
4787         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4788                 le16_to_cpu(tp->tc_offset.rx_missed);
4789
4790         pm_runtime_put_noidle(&pdev->dev);
4791 }
4792
4793 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4794 {
4795         netif_device_detach(tp->dev);
4796
4797         if (netif_running(tp->dev))
4798                 rtl8169_down(tp);
4799 }
4800
4801 static int rtl8169_runtime_resume(struct device *dev)
4802 {
4803         struct rtl8169_private *tp = dev_get_drvdata(dev);
4804
4805         rtl_rar_set(tp, tp->dev->dev_addr);
4806         __rtl8169_set_wol(tp, tp->saved_wolopts);
4807
4808         if (tp->TxDescArray)
4809                 rtl8169_up(tp);
4810
4811         netif_device_attach(tp->dev);
4812
4813         return 0;
4814 }
4815
4816 static int rtl8169_suspend(struct device *device)
4817 {
4818         struct rtl8169_private *tp = dev_get_drvdata(device);
4819
4820         rtnl_lock();
4821         rtl8169_net_suspend(tp);
4822         if (!device_may_wakeup(tp_to_dev(tp)))
4823                 clk_disable_unprepare(tp->clk);
4824         rtnl_unlock();
4825
4826         return 0;
4827 }
4828
4829 static int rtl8169_resume(struct device *device)
4830 {
4831         struct rtl8169_private *tp = dev_get_drvdata(device);
4832
4833         if (!device_may_wakeup(tp_to_dev(tp)))
4834                 clk_prepare_enable(tp->clk);
4835
4836         /* Reportedly at least Asus X453MA truncates packets otherwise */
4837         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4838                 rtl_init_rxcfg(tp);
4839
4840         return rtl8169_runtime_resume(device);
4841 }
4842
4843 static int rtl8169_runtime_suspend(struct device *device)
4844 {
4845         struct rtl8169_private *tp = dev_get_drvdata(device);
4846
4847         if (!tp->TxDescArray) {
4848                 netif_device_detach(tp->dev);
4849                 return 0;
4850         }
4851
4852         rtnl_lock();
4853         __rtl8169_set_wol(tp, WAKE_PHY);
4854         rtl8169_net_suspend(tp);
4855         rtnl_unlock();
4856
4857         return 0;
4858 }
4859
4860 static int rtl8169_runtime_idle(struct device *device)
4861 {
4862         struct rtl8169_private *tp = dev_get_drvdata(device);
4863
4864         if (tp->dash_type != RTL_DASH_NONE)
4865                 return -EBUSY;
4866
4867         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4868                 pm_schedule_suspend(device, 10000);
4869
4870         return -EBUSY;
4871 }
4872
4873 static const struct dev_pm_ops rtl8169_pm_ops = {
4874         SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4875         RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4876                        rtl8169_runtime_idle)
4877 };
4878
4879 static void rtl_shutdown(struct pci_dev *pdev)
4880 {
4881         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4882
4883         rtnl_lock();
4884         rtl8169_net_suspend(tp);
4885         rtnl_unlock();
4886
4887         /* Restore original MAC address */
4888         rtl_rar_set(tp, tp->dev->perm_addr);
4889
4890         if (system_state == SYSTEM_POWER_OFF &&
4891             tp->dash_type == RTL_DASH_NONE) {
4892                 pci_wake_from_d3(pdev, tp->saved_wolopts);
4893                 pci_set_power_state(pdev, PCI_D3hot);
4894         }
4895 }
4896
4897 static void rtl_remove_one(struct pci_dev *pdev)
4898 {
4899         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4900
4901         if (pci_dev_run_wake(pdev))
4902                 pm_runtime_get_noresume(&pdev->dev);
4903
4904         unregister_netdev(tp->dev);
4905
4906         if (tp->dash_type != RTL_DASH_NONE)
4907                 rtl8168_driver_stop(tp);
4908
4909         rtl_release_firmware(tp);
4910
4911         /* restore original MAC address */
4912         rtl_rar_set(tp, tp->dev->perm_addr);
4913 }
4914
4915 static const struct net_device_ops rtl_netdev_ops = {
4916         .ndo_open               = rtl_open,
4917         .ndo_stop               = rtl8169_close,
4918         .ndo_get_stats64        = rtl8169_get_stats64,
4919         .ndo_start_xmit         = rtl8169_start_xmit,
4920         .ndo_features_check     = rtl8169_features_check,
4921         .ndo_tx_timeout         = rtl8169_tx_timeout,
4922         .ndo_validate_addr      = eth_validate_addr,
4923         .ndo_change_mtu         = rtl8169_change_mtu,
4924         .ndo_fix_features       = rtl8169_fix_features,
4925         .ndo_set_features       = rtl8169_set_features,
4926         .ndo_set_mac_address    = rtl_set_mac_address,
4927         .ndo_eth_ioctl          = phy_do_ioctl_running,
4928         .ndo_set_rx_mode        = rtl_set_rx_mode,
4929 #ifdef CONFIG_NET_POLL_CONTROLLER
4930         .ndo_poll_controller    = rtl8169_netpoll,
4931 #endif
4932
4933 };
4934
4935 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4936 {
4937         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4938
4939         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4940                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4941         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4942                 /* special workaround needed */
4943                 tp->irq_mask |= RxFIFOOver;
4944         else
4945                 tp->irq_mask |= RxOverflow;
4946 }
4947
4948 static int rtl_alloc_irq(struct rtl8169_private *tp)
4949 {
4950         unsigned int flags;
4951
4952         switch (tp->mac_version) {
4953         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4954                 rtl_unlock_config_regs(tp);
4955                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
4956                 rtl_lock_config_regs(tp);
4957                 fallthrough;
4958         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
4959                 flags = PCI_IRQ_LEGACY;
4960                 break;
4961         default:
4962                 flags = PCI_IRQ_ALL_TYPES;
4963                 break;
4964         }
4965
4966         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
4967 }
4968
4969 static void rtl_read_mac_address(struct rtl8169_private *tp,
4970                                  u8 mac_addr[ETH_ALEN])
4971 {
4972         /* Get MAC address */
4973         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
4974                 u32 value;
4975
4976                 value = rtl_eri_read(tp, 0xe0);
4977                 put_unaligned_le32(value, mac_addr);
4978                 value = rtl_eri_read(tp, 0xe4);
4979                 put_unaligned_le16(value, mac_addr + 4);
4980         } else if (rtl_is_8125(tp)) {
4981                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
4982         }
4983 }
4984
4985 DECLARE_RTL_COND(rtl_link_list_ready_cond)
4986 {
4987         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
4988 }
4989
4990 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
4991 {
4992         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
4993 }
4994
4995 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
4996 {
4997         struct rtl8169_private *tp = mii_bus->priv;
4998
4999         if (phyaddr > 0)
5000                 return -ENODEV;
5001
5002         return rtl_readphy(tp, phyreg);
5003 }
5004
5005 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5006                                 int phyreg, u16 val)
5007 {
5008         struct rtl8169_private *tp = mii_bus->priv;
5009
5010         if (phyaddr > 0)
5011                 return -ENODEV;
5012
5013         rtl_writephy(tp, phyreg, val);
5014
5015         return 0;
5016 }
5017
5018 static int r8169_mdio_register(struct rtl8169_private *tp)
5019 {
5020         struct pci_dev *pdev = tp->pci_dev;
5021         struct mii_bus *new_bus;
5022         int ret;
5023
5024         new_bus = devm_mdiobus_alloc(&pdev->dev);
5025         if (!new_bus)
5026                 return -ENOMEM;
5027
5028         new_bus->name = "r8169";
5029         new_bus->priv = tp;
5030         new_bus->parent = &pdev->dev;
5031         new_bus->irq[0] = PHY_MAC_INTERRUPT;
5032         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5033                  pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5034
5035         new_bus->read = r8169_mdio_read_reg;
5036         new_bus->write = r8169_mdio_write_reg;
5037
5038         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5039         if (ret)
5040                 return ret;
5041
5042         tp->phydev = mdiobus_get_phy(new_bus, 0);
5043         if (!tp->phydev) {
5044                 return -ENODEV;
5045         } else if (!tp->phydev->drv) {
5046                 /* Most chip versions fail with the genphy driver.
5047                  * Therefore ensure that the dedicated PHY driver is loaded.
5048                  */
5049                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5050                         tp->phydev->phy_id);
5051                 return -EUNATCH;
5052         }
5053
5054         tp->phydev->mac_managed_pm = true;
5055
5056         phy_support_asym_pause(tp->phydev);
5057
5058         /* PHY will be woken up in rtl_open() */
5059         phy_suspend(tp->phydev);
5060
5061         return 0;
5062 }
5063
5064 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5065 {
5066         rtl_enable_rxdvgate(tp);
5067
5068         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5069         msleep(1);
5070         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5071
5072         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5073         r8168g_wait_ll_share_fifo_ready(tp);
5074
5075         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5076         r8168g_wait_ll_share_fifo_ready(tp);
5077 }
5078
5079 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5080 {
5081         rtl_enable_rxdvgate(tp);
5082
5083         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5084         msleep(1);
5085         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5086
5087         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5088         r8168g_wait_ll_share_fifo_ready(tp);
5089
5090         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5091         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5092         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5093         r8168g_wait_ll_share_fifo_ready(tp);
5094 }
5095
5096 static void rtl_hw_initialize(struct rtl8169_private *tp)
5097 {
5098         switch (tp->mac_version) {
5099         case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5100                 rtl8168ep_stop_cmac(tp);
5101                 fallthrough;
5102         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5103                 rtl_hw_init_8168g(tp);
5104                 break;
5105         case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5106                 rtl_hw_init_8125(tp);
5107                 break;
5108         default:
5109                 break;
5110         }
5111 }
5112
5113 static int rtl_jumbo_max(struct rtl8169_private *tp)
5114 {
5115         /* Non-GBit versions don't support jumbo frames */
5116         if (!tp->supports_gmii)
5117                 return 0;
5118
5119         switch (tp->mac_version) {
5120         /* RTL8169 */
5121         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5122                 return JUMBO_7K;
5123         /* RTL8168b */
5124         case RTL_GIGA_MAC_VER_11:
5125         case RTL_GIGA_MAC_VER_17:
5126                 return JUMBO_4K;
5127         /* RTL8168c */
5128         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5129                 return JUMBO_6K;
5130         default:
5131                 return JUMBO_9K;
5132         }
5133 }
5134
5135 static void rtl_init_mac_address(struct rtl8169_private *tp)
5136 {
5137         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5138         struct net_device *dev = tp->dev;
5139         int rc;
5140
5141         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5142         if (!rc)
5143                 goto done;
5144
5145         rtl_read_mac_address(tp, mac_addr);
5146         if (is_valid_ether_addr(mac_addr))
5147                 goto done;
5148
5149         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5150         if (is_valid_ether_addr(mac_addr))
5151                 goto done;
5152
5153         eth_random_addr(mac_addr);
5154         dev->addr_assign_type = NET_ADDR_RANDOM;
5155         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5156 done:
5157         eth_hw_addr_set(dev, mac_addr);
5158         rtl_rar_set(tp, mac_addr);
5159 }
5160
5161 /* register is set if system vendor successfully tested ASPM 1.2 */
5162 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5163 {
5164         if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5165             r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5166                 return true;
5167
5168         return false;
5169 }
5170
5171 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5172 {
5173         struct rtl8169_private *tp;
5174         int jumbo_max, region, rc;
5175         enum mac_version chipset;
5176         struct net_device *dev;
5177         u32 txconfig;
5178         u16 xid;
5179
5180         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5181         if (!dev)
5182                 return -ENOMEM;
5183
5184         SET_NETDEV_DEV(dev, &pdev->dev);
5185         dev->netdev_ops = &rtl_netdev_ops;
5186         tp = netdev_priv(dev);
5187         tp->dev = dev;
5188         tp->pci_dev = pdev;
5189         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5190         tp->eee_adv = -1;
5191         tp->ocp_base = OCP_STD_PHY_BASE;
5192
5193         raw_spin_lock_init(&tp->cfg9346_usage_lock);
5194         raw_spin_lock_init(&tp->config25_lock);
5195         raw_spin_lock_init(&tp->mac_ocp_lock);
5196
5197         dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5198                                                    struct pcpu_sw_netstats);
5199         if (!dev->tstats)
5200                 return -ENOMEM;
5201
5202         /* Get the *optional* external "ether_clk" used on some boards */
5203         tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5204         if (IS_ERR(tp->clk))
5205                 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5206
5207         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5208         rc = pcim_enable_device(pdev);
5209         if (rc < 0)
5210                 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5211
5212         if (pcim_set_mwi(pdev) < 0)
5213                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5214
5215         /* use first MMIO region */
5216         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5217         if (region < 0)
5218                 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5219
5220         rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5221         if (rc < 0)
5222                 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5223
5224         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5225
5226         txconfig = RTL_R32(tp, TxConfig);
5227         if (txconfig == ~0U)
5228                 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5229
5230         xid = (txconfig >> 20) & 0xfcf;
5231
5232         /* Identify chip attached to board */
5233         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5234         if (chipset == RTL_GIGA_MAC_NONE)
5235                 return dev_err_probe(&pdev->dev, -ENODEV,
5236                                      "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5237                                      xid);
5238         tp->mac_version = chipset;
5239
5240         /* Disable ASPM L1 as that cause random device stop working
5241          * problems as well as full system hangs for some PCIe devices users.
5242          */
5243         if (rtl_aspm_is_safe(tp))
5244                 rc = 0;
5245         else
5246                 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5247         tp->aspm_manageable = !rc;
5248
5249         tp->dash_type = rtl_check_dash(tp);
5250
5251         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5252
5253         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5254             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5255                 dev->features |= NETIF_F_HIGHDMA;
5256
5257         rtl_init_rxcfg(tp);
5258
5259         rtl8169_irq_mask_and_ack(tp);
5260
5261         rtl_hw_initialize(tp);
5262
5263         rtl_hw_reset(tp);
5264
5265         rc = rtl_alloc_irq(tp);
5266         if (rc < 0)
5267                 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5268
5269         tp->irq = pci_irq_vector(pdev, 0);
5270
5271         INIT_WORK(&tp->wk.work, rtl_task);
5272
5273         rtl_init_mac_address(tp);
5274
5275         dev->ethtool_ops = &rtl8169_ethtool_ops;
5276
5277         netif_napi_add(dev, &tp->napi, rtl8169_poll);
5278
5279         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5280                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5281         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5282         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5283
5284         /*
5285          * Pretend we are using VLANs; This bypasses a nasty bug where
5286          * Interrupts stop flowing on high load on 8110SCd controllers.
5287          */
5288         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5289                 /* Disallow toggling */
5290                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5291
5292         if (rtl_chip_supports_csum_v2(tp))
5293                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5294
5295         dev->features |= dev->hw_features;
5296
5297         /* There has been a number of reports that using SG/TSO results in
5298          * tx timeouts. However for a lot of people SG/TSO works fine.
5299          * Therefore disable both features by default, but allow users to
5300          * enable them. Use at own risk!
5301          */
5302         if (rtl_chip_supports_csum_v2(tp)) {
5303                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5304                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5305                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5306         } else {
5307                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5308                 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5309                 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5310         }
5311
5312         dev->hw_features |= NETIF_F_RXALL;
5313         dev->hw_features |= NETIF_F_RXFCS;
5314
5315         netdev_sw_irq_coalesce_default_on(dev);
5316
5317         /* configure chip for default features */
5318         rtl8169_set_features(dev, dev->features);
5319
5320         if (tp->dash_type == RTL_DASH_NONE) {
5321                 rtl_set_d3_pll_down(tp, true);
5322         } else {
5323                 rtl_set_d3_pll_down(tp, false);
5324                 dev->wol_enabled = 1;
5325         }
5326
5327         jumbo_max = rtl_jumbo_max(tp);
5328         if (jumbo_max)
5329                 dev->max_mtu = jumbo_max;
5330
5331         rtl_set_irq_mask(tp);
5332
5333         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5334
5335         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5336                                             &tp->counters_phys_addr,
5337                                             GFP_KERNEL);
5338         if (!tp->counters)
5339                 return -ENOMEM;
5340
5341         pci_set_drvdata(pdev, tp);
5342
5343         rc = r8169_mdio_register(tp);
5344         if (rc)
5345                 return rc;
5346
5347         rc = register_netdev(dev);
5348         if (rc)
5349                 return rc;
5350
5351         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5352                     rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5353
5354         if (jumbo_max)
5355                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5356                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5357                             "ok" : "ko");
5358
5359         if (tp->dash_type != RTL_DASH_NONE) {
5360                 netdev_info(dev, "DASH enabled\n");
5361                 rtl8168_driver_start(tp);
5362         }
5363
5364         if (pci_dev_run_wake(pdev))
5365                 pm_runtime_put_sync(&pdev->dev);
5366
5367         return 0;
5368 }
5369
5370 static struct pci_driver rtl8169_pci_driver = {
5371         .name           = KBUILD_MODNAME,
5372         .id_table       = rtl8169_pci_tbl,
5373         .probe          = rtl_init_one,
5374         .remove         = rtl_remove_one,
5375         .shutdown       = rtl_shutdown,
5376         .driver.pm      = pm_ptr(&rtl8169_pm_ops),
5377 };
5378
5379 module_pci_driver(rtl8169_pci_driver);