1 // SPDX-License-Identifier: GPL-2.0-only
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
9 * See MAINTAINERS file for support contact information.
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
35 #include "r8169_firmware.h"
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
60 #define MC_FILTER_LIMIT 32
62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
65 #define R8169_REGS_SIZE 256
66 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
72 #define OCP_STD_PHY_BASE 0xa400
74 #define RTL_CFG_NO_GBIT 1
76 /* write/read MMIO register */
77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92 } rtl_chip_infos[] = {
94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
142 static const struct pci_device_id rtl8169_pci_tbl[] = {
143 { PCI_VDEVICE(REALTEK, 0x2502) },
144 { PCI_VDEVICE(REALTEK, 0x2600) },
145 { PCI_VDEVICE(REALTEK, 0x8129) },
146 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
147 { PCI_VDEVICE(REALTEK, 0x8161) },
148 { PCI_VDEVICE(REALTEK, 0x8162) },
149 { PCI_VDEVICE(REALTEK, 0x8167) },
150 { PCI_VDEVICE(REALTEK, 0x8168) },
151 { PCI_VDEVICE(NCUBE, 0x8168) },
152 { PCI_VDEVICE(REALTEK, 0x8169) },
153 { PCI_VENDOR_ID_DLINK, 0x4300,
154 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
155 { PCI_VDEVICE(DLINK, 0x4300) },
156 { PCI_VDEVICE(DLINK, 0x4302) },
157 { PCI_VDEVICE(AT, 0xc107) },
158 { PCI_VDEVICE(USR, 0x0116) },
159 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
160 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
161 { PCI_VDEVICE(REALTEK, 0x8125) },
162 { PCI_VDEVICE(REALTEK, 0x3000) },
166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
169 MAC0 = 0, /* Ethernet hardware address. */
171 MAR0 = 8, /* Multicast filter. */
172 CounterAddrLow = 0x10,
173 CounterAddrHigh = 0x14,
174 TxDescStartAddrLow = 0x20,
175 TxDescStartAddrHigh = 0x24,
176 TxHDescStartAddrLow = 0x28,
177 TxHDescStartAddrHigh = 0x2c,
186 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
187 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
190 #define RX128_INT_EN (1 << 15) /* 8111c and later */
191 #define RX_MULTI_EN (1 << 14) /* 8111c only */
192 #define RXCFG_FIFO_SHIFT 13
193 /* No threshold before first PCI xfer */
194 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
195 #define RX_EARLY_OFF (1 << 11)
196 #define RXCFG_DMA_SHIFT 8
197 /* Unlimited maximum PCI burst. */
198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
204 #define PME_SIGNAL (1 << 5) /* 8168c and later */
215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
220 #define RTL_COALESCE_T_MAX 0x0fU
221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
231 #define TxPacketMax (8064 >> 7)
232 #define EarlySize 0x27
235 FuncEventMask = 0xf4,
236 FuncPresetState = 0xf8,
241 FuncForceEvent = 0xfc,
244 enum rtl8168_8101_registers {
247 #define CSIAR_FLAG 0x80000000
248 #define CSIAR_WRITE_CMD 0x80000000
249 #define CSIAR_BYTE_ENABLE 0x0000f000
250 #define CSIAR_ADDR_MASK 0x00000fff
252 #define D3COLD_NO_PLL_DOWN BIT(7)
253 #define D3HOT_NO_PLL_DOWN BIT(6)
254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
256 #define EPHYAR_FLAG 0x80000000
257 #define EPHYAR_WRITE_CMD 0x80000000
258 #define EPHYAR_REG_MASK 0x1f
259 #define EPHYAR_REG_SHIFT 16
260 #define EPHYAR_DATA_MASK 0xffff
262 #define PFM_EN (1 << 6)
263 #define TX_10M_PS_EN (1 << 7)
265 #define FIX_NAK_1 (1 << 4)
266 #define FIX_NAK_2 (1 << 3)
269 #define NOW_IS_OOB (1 << 7)
270 #define TX_EMPTY (1 << 5)
271 #define RX_EMPTY (1 << 4)
272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
273 #define EN_NDP (1 << 3)
274 #define EN_OOB_RESET (1 << 2)
275 #define LINK_LIST_RDY (1 << 1)
277 #define EFUSEAR_FLAG 0x80000000
278 #define EFUSEAR_WRITE_CMD 0x80000000
279 #define EFUSEAR_READ_CMD 0x00000000
280 #define EFUSEAR_REG_MASK 0x03ff
281 #define EFUSEAR_REG_SHIFT 8
282 #define EFUSEAR_DATA_MASK 0xff
284 #define PFM_D3COLD_EN (1 << 6)
287 enum rtl8168_registers {
292 #define ERIAR_FLAG 0x80000000
293 #define ERIAR_WRITE_CMD 0x80000000
294 #define ERIAR_READ_CMD 0x00000000
295 #define ERIAR_ADDR_BYTE_ALIGN 4
296 #define ERIAR_TYPE_SHIFT 16
297 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
298 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
299 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
300 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
301 #define ERIAR_MASK_SHIFT 12
302 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
303 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
304 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
305 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
306 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
307 EPHY_RXER_NUM = 0x7c,
308 OCPDR = 0xb0, /* OCP GPHY access */
309 #define OCPDR_WRITE_CMD 0x80000000
310 #define OCPDR_READ_CMD 0x00000000
311 #define OCPDR_REG_MASK 0x7f
312 #define OCPDR_GPHY_REG_SHIFT 16
313 #define OCPDR_DATA_MASK 0xffff
315 #define OCPAR_FLAG 0x80000000
316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
317 #define OCPAR_GPHY_READ_CMD 0x0000f060
319 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
320 MISC = 0xf0, /* 8168e only. */
321 #define TXPLA_RST (1 << 29)
322 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
323 #define PWM_EN (1 << 22)
324 #define RXDV_GATED_EN (1 << 19)
325 #define EARLY_TALLY_EN (1 << 16)
328 enum rtl8125_registers {
329 IntrMask_8125 = 0x38,
330 IntrStatus_8125 = 0x3c,
333 EEE_TXIDLE_TIMER_8125 = 0x6048,
336 #define RX_VLAN_INNER_8125 BIT(22)
337 #define RX_VLAN_OUTER_8125 BIT(23)
338 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
340 #define RX_FETCH_DFLT_8125 (8 << 27)
342 enum rtl_register_content {
343 /* InterruptStatusBits */
347 TxDescUnavail = 0x0080,
369 /* TXPoll register p.5 */
370 HPQ = 0x80, /* Poll cmd on the high prio queue */
371 NPQ = 0x40, /* Poll cmd on the low prio queue */
372 FSWInt = 0x01, /* Forced software interrupt */
376 Cfg9346_Unlock = 0xc0,
381 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
382 AcceptBroadcast = 0x08,
383 AcceptMulticast = 0x04,
385 AcceptAllPhys = 0x01,
386 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
387 #define RX_CONFIG_ACCEPT_MASK 0x3f
390 TxInterFrameGapShift = 24,
391 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
393 /* Config1 register p.24 */
396 Speed_down = (1 << 4),
400 PMEnable = (1 << 0), /* Power Management Enable */
402 /* Config2 register p. 25 */
403 ClkReqEn = (1 << 7), /* Clock Request Enable */
404 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
405 PCI_Clock_66MHz = 0x01,
406 PCI_Clock_33MHz = 0x00,
408 /* Config3 register p.25 */
409 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
410 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
411 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
412 Rdy_to_L23 = (1 << 1), /* L23 Enable */
413 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
415 /* Config4 register */
416 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
418 /* Config5 register p.27 */
419 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
420 MWF = (1 << 5), /* Accept Multicast wakeup frame */
421 UWF = (1 << 4), /* Accept Unicast wakeup frame */
423 LanWake = (1 << 1), /* LanWake enable/disable */
424 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
425 ASPM_en = (1 << 0), /* ASPM enable */
428 EnableBist = (1 << 15), // 8168 8101
429 Mac_dbgo_oe = (1 << 14), // 8168 8101
430 EnAnaPLL = (1 << 14), // 8169
431 Normal_mode = (1 << 13), // unused
432 Force_half_dup = (1 << 12), // 8168 8101
433 Force_rxflow_en = (1 << 11), // 8168 8101
434 Force_txflow_en = (1 << 10), // 8168 8101
435 Cxpl_dbg_sel = (1 << 9), // 8168 8101
436 ASF = (1 << 8), // 8168 8101
437 PktCntrDisable = (1 << 7), // 8168 8101
438 Mac_dbgo_sel = 0x001c, // 8168
443 #define INTT_MASK GENMASK(1, 0)
444 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
446 /* rtl8169_PHYstatus */
456 /* ResetCounterCommand */
459 /* DumpCounterCommand */
462 /* magic enable v2 */
463 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
467 /* First doubleword. */
468 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
469 RingEnd = (1 << 30), /* End of descriptor ring */
470 FirstFrag = (1 << 29), /* First segment of a packet */
471 LastFrag = (1 << 28), /* Final segment of a packet */
475 enum rtl_tx_desc_bit {
476 /* First doubleword. */
477 TD_LSO = (1 << 27), /* Large Send Offload */
478 #define TD_MSS_MAX 0x07ffu /* MSS value */
480 /* Second doubleword. */
481 TxVlanTag = (1 << 17), /* Add VLAN tag */
484 /* 8169, 8168b and 810x except 8102e. */
485 enum rtl_tx_desc_bit_0 {
486 /* First doubleword. */
487 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
488 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
489 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
490 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
493 /* 8102e, 8168c and beyond. */
494 enum rtl_tx_desc_bit_1 {
495 /* First doubleword. */
496 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
497 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
498 #define GTTCPHO_SHIFT 18
499 #define GTTCPHO_MAX 0x7f
501 /* Second doubleword. */
502 #define TCPHO_SHIFT 18
503 #define TCPHO_MAX 0x3ff
504 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
505 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
506 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
511 enum rtl_rx_desc_bit {
513 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
514 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
516 #define RxProtoUDP (PID1)
517 #define RxProtoTCP (PID0)
518 #define RxProtoIP (PID1 | PID0)
519 #define RxProtoMask RxProtoIP
521 IPFail = (1 << 16), /* IP checksum failed */
522 UDPFail = (1 << 15), /* UDP/IP checksum failed */
523 TCPFail = (1 << 14), /* TCP/IP checksum failed */
525 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
527 RxVlanTag = (1 << 16), /* VLAN tag available */
530 #define RTL_GSO_MAX_SIZE_V1 32000
531 #define RTL_GSO_MAX_SEGS_V1 24
532 #define RTL_GSO_MAX_SIZE_V2 64000
533 #define RTL_GSO_MAX_SEGS_V2 64
552 struct rtl8169_counters {
559 __le32 tx_one_collision;
560 __le32 tx_multi_collision;
568 struct rtl8169_tc_offsets {
571 __le32 tx_multi_collision;
577 RTL_FLAG_TASK_ENABLED = 0,
578 RTL_FLAG_TASK_RESET_PENDING,
579 RTL_FLAG_TASK_TX_TIMEOUT,
589 struct rtl8169_private {
590 void __iomem *mmio_addr; /* memory map physical address */
591 struct pci_dev *pci_dev;
592 struct net_device *dev;
593 struct phy_device *phydev;
594 struct napi_struct napi;
595 enum mac_version mac_version;
596 enum rtl_dash_type dash_type;
597 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
598 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
600 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
601 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
602 dma_addr_t TxPhyAddr;
603 dma_addr_t RxPhyAddr;
604 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
605 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
612 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
613 struct work_struct work;
616 spinlock_t config25_lock;
617 spinlock_t mac_ocp_lock;
619 spinlock_t cfg9346_usage_lock;
620 int cfg9346_usage_count;
622 unsigned supports_gmii:1;
623 unsigned aspm_manageable:1;
624 dma_addr_t counters_phys_addr;
625 struct rtl8169_counters *counters;
626 struct rtl8169_tc_offsets tc_offset;
631 struct rtl_fw *rtl_fw;
636 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
638 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
639 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
640 MODULE_SOFTDEP("pre: realtek");
641 MODULE_LICENSE("GPL");
642 MODULE_FIRMWARE(FIRMWARE_8168D_1);
643 MODULE_FIRMWARE(FIRMWARE_8168D_2);
644 MODULE_FIRMWARE(FIRMWARE_8168E_1);
645 MODULE_FIRMWARE(FIRMWARE_8168E_2);
646 MODULE_FIRMWARE(FIRMWARE_8168E_3);
647 MODULE_FIRMWARE(FIRMWARE_8105E_1);
648 MODULE_FIRMWARE(FIRMWARE_8168F_1);
649 MODULE_FIRMWARE(FIRMWARE_8168F_2);
650 MODULE_FIRMWARE(FIRMWARE_8402_1);
651 MODULE_FIRMWARE(FIRMWARE_8411_1);
652 MODULE_FIRMWARE(FIRMWARE_8411_2);
653 MODULE_FIRMWARE(FIRMWARE_8106E_1);
654 MODULE_FIRMWARE(FIRMWARE_8106E_2);
655 MODULE_FIRMWARE(FIRMWARE_8168G_2);
656 MODULE_FIRMWARE(FIRMWARE_8168G_3);
657 MODULE_FIRMWARE(FIRMWARE_8168H_2);
658 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
659 MODULE_FIRMWARE(FIRMWARE_8107E_2);
660 MODULE_FIRMWARE(FIRMWARE_8125A_3);
661 MODULE_FIRMWARE(FIRMWARE_8125B_2);
663 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
665 return &tp->pci_dev->dev;
668 static void rtl_lock_config_regs(struct rtl8169_private *tp)
672 spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
673 if (!--tp->cfg9346_usage_count)
674 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
675 spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
678 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
682 spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
683 if (!tp->cfg9346_usage_count++)
684 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
685 spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
688 static void rtl_pci_commit(struct rtl8169_private *tp)
690 /* Read an arbitrary register to commit a preceding PCI write */
694 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
699 spin_lock_irqsave(&tp->config25_lock, flags);
700 val = RTL_R8(tp, Config2);
701 RTL_W8(tp, Config2, (val & ~clear) | set);
702 spin_unlock_irqrestore(&tp->config25_lock, flags);
705 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
710 spin_lock_irqsave(&tp->config25_lock, flags);
711 val = RTL_R8(tp, Config5);
712 RTL_W8(tp, Config5, (val & ~clear) | set);
713 spin_unlock_irqrestore(&tp->config25_lock, flags);
716 static bool rtl_is_8125(struct rtl8169_private *tp)
718 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
721 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
723 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
724 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
725 tp->mac_version <= RTL_GIGA_MAC_VER_53;
728 static bool rtl_supports_eee(struct rtl8169_private *tp)
730 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
731 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
732 tp->mac_version != RTL_GIGA_MAC_VER_39;
735 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
739 for (i = 0; i < ETH_ALEN; i++)
740 mac[i] = RTL_R8(tp, reg + i);
744 bool (*check)(struct rtl8169_private *);
748 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
749 unsigned long usecs, int n, bool high)
753 for (i = 0; i < n; i++) {
754 if (c->check(tp) == high)
760 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
761 c->msg, !high, n, usecs);
765 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
766 const struct rtl_cond *c,
767 unsigned long d, int n)
769 return rtl_loop_wait(tp, c, d, n, true);
772 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
773 const struct rtl_cond *c,
774 unsigned long d, int n)
776 return rtl_loop_wait(tp, c, d, n, false);
779 #define DECLARE_RTL_COND(name) \
780 static bool name ## _check(struct rtl8169_private *); \
782 static const struct rtl_cond name = { \
783 .check = name ## _check, \
787 static bool name ## _check(struct rtl8169_private *tp)
789 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
791 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
792 if (type == ERIAR_OOB &&
793 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
794 tp->mac_version == RTL_GIGA_MAC_VER_53))
798 DECLARE_RTL_COND(rtl_eriar_cond)
800 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
803 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
806 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
808 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
811 RTL_W32(tp, ERIDR, val);
812 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
813 RTL_W32(tp, ERIAR, cmd);
815 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
818 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
821 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
824 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
826 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
828 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
829 RTL_W32(tp, ERIAR, cmd);
831 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
832 RTL_R32(tp, ERIDR) : ~0;
835 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
837 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
840 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
842 u32 val = rtl_eri_read(tp, addr);
844 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
847 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
849 rtl_w0w1_eri(tp, addr, p, 0);
852 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
854 rtl_w0w1_eri(tp, addr, 0, m);
857 static bool rtl_ocp_reg_failure(u32 reg)
859 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
862 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
864 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
867 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
869 if (rtl_ocp_reg_failure(reg))
872 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
874 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
877 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
879 if (rtl_ocp_reg_failure(reg))
882 RTL_W32(tp, GPHY_OCP, reg << 15);
884 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
885 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
888 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
890 if (rtl_ocp_reg_failure(reg))
893 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
896 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
900 spin_lock_irqsave(&tp->mac_ocp_lock, flags);
901 __r8168_mac_ocp_write(tp, reg, data);
902 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
905 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
907 if (rtl_ocp_reg_failure(reg))
910 RTL_W32(tp, OCPDR, reg << 15);
912 return RTL_R32(tp, OCPDR);
915 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
920 spin_lock_irqsave(&tp->mac_ocp_lock, flags);
921 val = __r8168_mac_ocp_read(tp, reg);
922 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
927 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
933 spin_lock_irqsave(&tp->mac_ocp_lock, flags);
934 data = __r8168_mac_ocp_read(tp, reg);
935 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
936 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
939 /* Work around a hw issue with RTL8168g PHY, the quirk disables
940 * PHY MCU interrupts before PHY power-down.
942 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
944 switch (tp->mac_version) {
945 case RTL_GIGA_MAC_VER_40:
946 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
947 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
949 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
956 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
959 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
963 if (tp->ocp_base != OCP_STD_PHY_BASE)
966 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
967 rtl8168g_phy_suspend_quirk(tp, value);
969 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
972 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
975 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
977 if (tp->ocp_base != OCP_STD_PHY_BASE)
980 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
983 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
986 tp->ocp_base = value << 4;
990 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
993 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
995 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
998 DECLARE_RTL_COND(rtl_phyar_cond)
1000 return RTL_R32(tp, PHYAR) & 0x80000000;
1003 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1005 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1007 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1009 * According to hardware specs a 20us delay is required after write
1010 * complete indication, but before sending next command.
1015 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1019 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1021 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1022 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1025 * According to hardware specs a 20us delay is required after read
1026 * complete indication, but before sending next command.
1033 DECLARE_RTL_COND(rtl_ocpar_cond)
1035 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1038 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1040 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1042 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1045 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1047 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1050 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1052 r8168dp_2_mdio_start(tp);
1054 r8169_mdio_write(tp, reg, value);
1056 r8168dp_2_mdio_stop(tp);
1059 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1063 /* Work around issue with chip reporting wrong PHY ID */
1064 if (reg == MII_PHYSID2)
1067 r8168dp_2_mdio_start(tp);
1069 value = r8169_mdio_read(tp, reg);
1071 r8168dp_2_mdio_stop(tp);
1076 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1078 switch (tp->mac_version) {
1079 case RTL_GIGA_MAC_VER_28:
1080 case RTL_GIGA_MAC_VER_31:
1081 r8168dp_2_mdio_write(tp, location, val);
1083 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1084 r8168g_mdio_write(tp, location, val);
1087 r8169_mdio_write(tp, location, val);
1092 static int rtl_readphy(struct rtl8169_private *tp, int location)
1094 switch (tp->mac_version) {
1095 case RTL_GIGA_MAC_VER_28:
1096 case RTL_GIGA_MAC_VER_31:
1097 return r8168dp_2_mdio_read(tp, location);
1098 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1099 return r8168g_mdio_read(tp, location);
1101 return r8169_mdio_read(tp, location);
1105 DECLARE_RTL_COND(rtl_ephyar_cond)
1107 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1110 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1112 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1113 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1115 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1120 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1122 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1124 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1125 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1128 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1130 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1131 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1132 RTL_R32(tp, OCPDR) : ~0;
1135 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1137 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1140 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1143 RTL_W32(tp, OCPDR, data);
1144 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1145 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1148 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1151 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1155 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1157 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1159 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1162 #define OOB_CMD_RESET 0x00
1163 #define OOB_CMD_DRIVER_START 0x05
1164 #define OOB_CMD_DRIVER_STOP 0x06
1166 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1168 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1171 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1175 reg = rtl8168_get_ocp_reg(tp);
1177 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1180 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1182 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1185 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1187 return RTL_R8(tp, IBISR0) & 0x20;
1190 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1192 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1193 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1194 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1195 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1198 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1200 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1201 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1204 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1206 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1207 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1208 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1211 static void rtl8168_driver_start(struct rtl8169_private *tp)
1213 if (tp->dash_type == RTL_DASH_DP)
1214 rtl8168dp_driver_start(tp);
1216 rtl8168ep_driver_start(tp);
1219 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1221 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1222 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1225 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1227 rtl8168ep_stop_cmac(tp);
1228 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1229 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1230 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1233 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1235 if (tp->dash_type == RTL_DASH_DP)
1236 rtl8168dp_driver_stop(tp);
1238 rtl8168ep_driver_stop(tp);
1241 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1243 u16 reg = rtl8168_get_ocp_reg(tp);
1245 return r8168dp_ocp_read(tp, reg) & BIT(15);
1248 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1250 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1253 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1255 switch (tp->mac_version) {
1256 case RTL_GIGA_MAC_VER_28:
1257 case RTL_GIGA_MAC_VER_31:
1258 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1259 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1260 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1262 return RTL_DASH_NONE;
1266 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1268 switch (tp->mac_version) {
1269 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1270 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1271 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1272 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1274 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1276 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1283 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1285 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1286 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1289 DECLARE_RTL_COND(rtl_efusear_cond)
1291 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1294 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1296 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1298 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1299 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1302 static u32 rtl_get_events(struct rtl8169_private *tp)
1304 if (rtl_is_8125(tp))
1305 return RTL_R32(tp, IntrStatus_8125);
1307 return RTL_R16(tp, IntrStatus);
1310 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1312 if (rtl_is_8125(tp))
1313 RTL_W32(tp, IntrStatus_8125, bits);
1315 RTL_W16(tp, IntrStatus, bits);
1318 static void rtl_irq_disable(struct rtl8169_private *tp)
1320 if (rtl_is_8125(tp))
1321 RTL_W32(tp, IntrMask_8125, 0);
1323 RTL_W16(tp, IntrMask, 0);
1326 static void rtl_irq_enable(struct rtl8169_private *tp)
1328 if (rtl_is_8125(tp))
1329 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1331 RTL_W16(tp, IntrMask, tp->irq_mask);
1334 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1336 rtl_irq_disable(tp);
1337 rtl_ack_events(tp, 0xffffffff);
1341 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1343 struct phy_device *phydev = tp->phydev;
1345 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1346 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1347 if (phydev->speed == SPEED_1000) {
1348 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1350 } else if (phydev->speed == SPEED_100) {
1351 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1352 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1354 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1357 rtl_reset_packet_filter(tp);
1358 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1359 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1360 if (phydev->speed == SPEED_1000) {
1361 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1362 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1364 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1367 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1368 if (phydev->speed == SPEED_10) {
1369 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1370 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1372 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1377 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1379 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1381 struct rtl8169_private *tp = netdev_priv(dev);
1383 wol->supported = WAKE_ANY;
1384 wol->wolopts = tp->saved_wolopts;
1387 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1389 static const struct {
1394 { WAKE_PHY, Config3, LinkUp },
1395 { WAKE_UCAST, Config5, UWF },
1396 { WAKE_BCAST, Config5, BWF },
1397 { WAKE_MCAST, Config5, MWF },
1398 { WAKE_ANY, Config5, LanWake },
1399 { WAKE_MAGIC, Config3, MagicPacket }
1401 unsigned int i, tmp = ARRAY_SIZE(cfg);
1402 unsigned long flags;
1405 rtl_unlock_config_regs(tp);
1407 if (rtl_is_8168evl_up(tp)) {
1409 if (wolopts & WAKE_MAGIC)
1410 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1412 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1413 } else if (rtl_is_8125(tp)) {
1415 if (wolopts & WAKE_MAGIC)
1416 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1418 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1421 spin_lock_irqsave(&tp->config25_lock, flags);
1422 for (i = 0; i < tmp; i++) {
1423 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1424 if (wolopts & cfg[i].opt)
1425 options |= cfg[i].mask;
1426 RTL_W8(tp, cfg[i].reg, options);
1428 spin_unlock_irqrestore(&tp->config25_lock, flags);
1430 switch (tp->mac_version) {
1431 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1432 options = RTL_R8(tp, Config1) & ~PMEnable;
1434 options |= PMEnable;
1435 RTL_W8(tp, Config1, options);
1437 case RTL_GIGA_MAC_VER_34:
1438 case RTL_GIGA_MAC_VER_37:
1439 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1441 rtl_mod_config2(tp, 0, PME_SIGNAL);
1443 rtl_mod_config2(tp, PME_SIGNAL, 0);
1449 rtl_lock_config_regs(tp);
1451 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1453 if (tp->dash_type == RTL_DASH_NONE) {
1454 rtl_set_d3_pll_down(tp, !wolopts);
1455 tp->dev->wol_enabled = wolopts ? 1 : 0;
1459 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1461 struct rtl8169_private *tp = netdev_priv(dev);
1463 if (wol->wolopts & ~WAKE_ANY)
1466 tp->saved_wolopts = wol->wolopts;
1467 __rtl8169_set_wol(tp, tp->saved_wolopts);
1472 static void rtl8169_get_drvinfo(struct net_device *dev,
1473 struct ethtool_drvinfo *info)
1475 struct rtl8169_private *tp = netdev_priv(dev);
1476 struct rtl_fw *rtl_fw = tp->rtl_fw;
1478 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1479 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1480 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1482 strscpy(info->fw_version, rtl_fw->version,
1483 sizeof(info->fw_version));
1486 static int rtl8169_get_regs_len(struct net_device *dev)
1488 return R8169_REGS_SIZE;
1491 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1492 netdev_features_t features)
1494 struct rtl8169_private *tp = netdev_priv(dev);
1496 if (dev->mtu > TD_MSS_MAX)
1497 features &= ~NETIF_F_ALL_TSO;
1499 if (dev->mtu > ETH_DATA_LEN &&
1500 tp->mac_version > RTL_GIGA_MAC_VER_06)
1501 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1506 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1507 netdev_features_t features)
1509 u32 rx_config = RTL_R32(tp, RxConfig);
1511 if (features & NETIF_F_RXALL)
1512 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1514 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1516 if (rtl_is_8125(tp)) {
1517 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1518 rx_config |= RX_VLAN_8125;
1520 rx_config &= ~RX_VLAN_8125;
1523 RTL_W32(tp, RxConfig, rx_config);
1526 static int rtl8169_set_features(struct net_device *dev,
1527 netdev_features_t features)
1529 struct rtl8169_private *tp = netdev_priv(dev);
1531 rtl_set_rx_config_features(tp, features);
1533 if (features & NETIF_F_RXCSUM)
1534 tp->cp_cmd |= RxChkSum;
1536 tp->cp_cmd &= ~RxChkSum;
1538 if (!rtl_is_8125(tp)) {
1539 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1540 tp->cp_cmd |= RxVlan;
1542 tp->cp_cmd &= ~RxVlan;
1545 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1551 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1553 return (skb_vlan_tag_present(skb)) ?
1554 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1557 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1559 u32 opts2 = le32_to_cpu(desc->opts2);
1561 if (opts2 & RxVlanTag)
1562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1565 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1568 struct rtl8169_private *tp = netdev_priv(dev);
1569 u32 __iomem *data = tp->mmio_addr;
1573 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1574 memcpy_fromio(dw++, data++, 4);
1577 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1584 "tx_single_collisions",
1585 "tx_multi_collisions",
1593 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1597 return ARRAY_SIZE(rtl8169_gstrings);
1603 DECLARE_RTL_COND(rtl_counters_cond)
1605 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1608 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1610 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1612 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1614 RTL_W32(tp, CounterAddrLow, cmd);
1615 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1617 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1620 static void rtl8169_update_counters(struct rtl8169_private *tp)
1622 u8 val = RTL_R8(tp, ChipCmd);
1625 * Some chips are unable to dump tally counters when the receiver
1626 * is disabled. If 0xff chip may be in a PCI power-save state.
1628 if (val & CmdRxEnb && val != 0xff)
1629 rtl8169_do_counters(tp, CounterDump);
1632 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1634 struct rtl8169_counters *counters = tp->counters;
1637 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1638 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1639 * reset by a power cycle, while the counter values collected by the
1640 * driver are reset at every driver unload/load cycle.
1642 * To make sure the HW values returned by @get_stats64 match the SW
1643 * values, we collect the initial values at first open(*) and use them
1644 * as offsets to normalize the values returned by @get_stats64.
1646 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1647 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1648 * set at open time by rtl_hw_start.
1651 if (tp->tc_offset.inited)
1654 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1655 rtl8169_do_counters(tp, CounterReset);
1657 rtl8169_update_counters(tp);
1658 tp->tc_offset.tx_errors = counters->tx_errors;
1659 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1660 tp->tc_offset.tx_aborted = counters->tx_aborted;
1661 tp->tc_offset.rx_missed = counters->rx_missed;
1664 tp->tc_offset.inited = true;
1667 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1668 struct ethtool_stats *stats, u64 *data)
1670 struct rtl8169_private *tp = netdev_priv(dev);
1671 struct rtl8169_counters *counters;
1673 counters = tp->counters;
1674 rtl8169_update_counters(tp);
1676 data[0] = le64_to_cpu(counters->tx_packets);
1677 data[1] = le64_to_cpu(counters->rx_packets);
1678 data[2] = le64_to_cpu(counters->tx_errors);
1679 data[3] = le32_to_cpu(counters->rx_errors);
1680 data[4] = le16_to_cpu(counters->rx_missed);
1681 data[5] = le16_to_cpu(counters->align_errors);
1682 data[6] = le32_to_cpu(counters->tx_one_collision);
1683 data[7] = le32_to_cpu(counters->tx_multi_collision);
1684 data[8] = le64_to_cpu(counters->rx_unicast);
1685 data[9] = le64_to_cpu(counters->rx_broadcast);
1686 data[10] = le32_to_cpu(counters->rx_multicast);
1687 data[11] = le16_to_cpu(counters->tx_aborted);
1688 data[12] = le16_to_cpu(counters->tx_underun);
1691 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1695 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1701 * Interrupt coalescing
1703 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1704 * > 8169, 8168 and 810x line of chipsets
1706 * 8169, 8168, and 8136(810x) serial chipsets support it.
1708 * > 2 - the Tx timer unit at gigabit speed
1710 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1711 * (0xe0) bit 1 and bit 0.
1714 * bit[1:0] \ speed 1000M 100M 10M
1715 * 0 0 320ns 2.56us 40.96us
1716 * 0 1 2.56us 20.48us 327.7us
1717 * 1 0 5.12us 40.96us 655.4us
1718 * 1 1 10.24us 81.92us 1.31ms
1721 * bit[1:0] \ speed 1000M 100M 10M
1722 * 0 0 5us 2.56us 40.96us
1723 * 0 1 40us 20.48us 327.7us
1724 * 1 0 80us 40.96us 655.4us
1725 * 1 1 160us 81.92us 1.31ms
1728 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1729 struct rtl_coalesce_info {
1734 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1735 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1737 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1738 { SPEED_1000, COALESCE_DELAY(320) },
1739 { SPEED_100, COALESCE_DELAY(2560) },
1740 { SPEED_10, COALESCE_DELAY(40960) },
1744 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1745 { SPEED_1000, COALESCE_DELAY(5000) },
1746 { SPEED_100, COALESCE_DELAY(2560) },
1747 { SPEED_10, COALESCE_DELAY(40960) },
1750 #undef COALESCE_DELAY
1752 /* get rx/tx scale vector corresponding to current speed */
1753 static const struct rtl_coalesce_info *
1754 rtl_coalesce_info(struct rtl8169_private *tp)
1756 const struct rtl_coalesce_info *ci;
1758 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1759 ci = rtl_coalesce_info_8169;
1761 ci = rtl_coalesce_info_8168_8136;
1763 /* if speed is unknown assume highest one */
1764 if (tp->phydev->speed == SPEED_UNKNOWN)
1767 for (; ci->speed; ci++) {
1768 if (tp->phydev->speed == ci->speed)
1772 return ERR_PTR(-ELNRNG);
1775 static int rtl_get_coalesce(struct net_device *dev,
1776 struct ethtool_coalesce *ec,
1777 struct kernel_ethtool_coalesce *kernel_coal,
1778 struct netlink_ext_ack *extack)
1780 struct rtl8169_private *tp = netdev_priv(dev);
1781 const struct rtl_coalesce_info *ci;
1782 u32 scale, c_us, c_fr;
1785 if (rtl_is_8125(tp))
1788 memset(ec, 0, sizeof(*ec));
1790 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1791 ci = rtl_coalesce_info(tp);
1795 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1797 intrmit = RTL_R16(tp, IntrMitigate);
1799 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1800 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1802 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1803 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1804 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1806 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1807 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1809 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1810 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1815 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1816 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1819 const struct rtl_coalesce_info *ci;
1822 ci = rtl_coalesce_info(tp);
1826 for (i = 0; i < 4; i++) {
1827 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1829 return ci->scale_nsecs[i];
1836 static int rtl_set_coalesce(struct net_device *dev,
1837 struct ethtool_coalesce *ec,
1838 struct kernel_ethtool_coalesce *kernel_coal,
1839 struct netlink_ext_ack *extack)
1841 struct rtl8169_private *tp = netdev_priv(dev);
1842 u32 tx_fr = ec->tx_max_coalesced_frames;
1843 u32 rx_fr = ec->rx_max_coalesced_frames;
1844 u32 coal_usec_max, units;
1845 u16 w = 0, cp01 = 0;
1848 if (rtl_is_8125(tp))
1851 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1854 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1855 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1859 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1860 * not only when usecs=0 because of e.g. the following scenario:
1862 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1863 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1864 * - then user does `ethtool -C eth0 rx-usecs 100`
1866 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1867 * if we want to ignore rx_frames then it has to be set to 0.
1874 /* HW requires time limit to be set if frame limit is set */
1875 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1876 (rx_fr && !ec->rx_coalesce_usecs))
1879 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1880 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1882 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1883 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1884 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1885 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1887 RTL_W16(tp, IntrMitigate, w);
1889 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1890 if (rtl_is_8168evl_up(tp)) {
1891 if (!rx_fr && !tx_fr)
1892 /* disable packet counter */
1893 tp->cp_cmd |= PktCntrDisable;
1895 tp->cp_cmd &= ~PktCntrDisable;
1898 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1899 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1905 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1907 struct rtl8169_private *tp = netdev_priv(dev);
1909 if (!rtl_supports_eee(tp))
1912 return phy_ethtool_get_eee(tp->phydev, data);
1915 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1917 struct rtl8169_private *tp = netdev_priv(dev);
1920 if (!rtl_supports_eee(tp))
1923 ret = phy_ethtool_set_eee(tp->phydev, data);
1926 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1931 static void rtl8169_get_ringparam(struct net_device *dev,
1932 struct ethtool_ringparam *data,
1933 struct kernel_ethtool_ringparam *kernel_data,
1934 struct netlink_ext_ack *extack)
1936 data->rx_max_pending = NUM_RX_DESC;
1937 data->rx_pending = NUM_RX_DESC;
1938 data->tx_max_pending = NUM_TX_DESC;
1939 data->tx_pending = NUM_TX_DESC;
1942 static void rtl8169_get_pauseparam(struct net_device *dev,
1943 struct ethtool_pauseparam *data)
1945 struct rtl8169_private *tp = netdev_priv(dev);
1946 bool tx_pause, rx_pause;
1948 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1950 data->autoneg = tp->phydev->autoneg;
1951 data->tx_pause = tx_pause ? 1 : 0;
1952 data->rx_pause = rx_pause ? 1 : 0;
1955 static int rtl8169_set_pauseparam(struct net_device *dev,
1956 struct ethtool_pauseparam *data)
1958 struct rtl8169_private *tp = netdev_priv(dev);
1960 if (dev->mtu > ETH_DATA_LEN)
1963 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1968 static const struct ethtool_ops rtl8169_ethtool_ops = {
1969 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1970 ETHTOOL_COALESCE_MAX_FRAMES,
1971 .get_drvinfo = rtl8169_get_drvinfo,
1972 .get_regs_len = rtl8169_get_regs_len,
1973 .get_link = ethtool_op_get_link,
1974 .get_coalesce = rtl_get_coalesce,
1975 .set_coalesce = rtl_set_coalesce,
1976 .get_regs = rtl8169_get_regs,
1977 .get_wol = rtl8169_get_wol,
1978 .set_wol = rtl8169_set_wol,
1979 .get_strings = rtl8169_get_strings,
1980 .get_sset_count = rtl8169_get_sset_count,
1981 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1982 .get_ts_info = ethtool_op_get_ts_info,
1983 .nway_reset = phy_ethtool_nway_reset,
1984 .get_eee = rtl8169_get_eee,
1985 .set_eee = rtl8169_set_eee,
1986 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1987 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1988 .get_ringparam = rtl8169_get_ringparam,
1989 .get_pauseparam = rtl8169_get_pauseparam,
1990 .set_pauseparam = rtl8169_set_pauseparam,
1993 static void rtl_enable_eee(struct rtl8169_private *tp)
1995 struct phy_device *phydev = tp->phydev;
1998 /* respect EEE advertisement the user may have set */
1999 if (tp->eee_adv >= 0)
2002 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2005 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2008 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2011 * The driver currently handles the 8168Bf and the 8168Be identically
2012 * but they can be identified more specifically through the test below
2015 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2017 * Same thing for the 8101Eb and the 8101Ec:
2019 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2021 static const struct rtl_mac_info {
2024 enum mac_version ver;
2027 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2030 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2031 /* It seems only XID 609 made it to the mass market.
2032 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2033 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2037 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2038 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2040 /* 8168EP family. */
2041 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2042 /* It seems this chip version never made it to
2043 * the wild. Let's disable detection.
2044 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2045 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2049 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2050 /* It seems this chip version never made it to
2051 * the wild. Let's disable detection.
2052 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2056 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2057 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2058 /* It seems this chip version never made it to
2059 * the wild. Let's disable detection.
2060 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2062 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2065 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2066 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2067 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2070 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2071 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2072 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2075 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2076 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2078 /* 8168DP family. */
2079 /* It seems this early RTL8168dp version never made it to
2080 * the wild. Support has been removed.
2081 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2083 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2084 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2087 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2088 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2089 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2090 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2091 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2092 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2093 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2096 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2097 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2100 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2101 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2102 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2103 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2104 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2105 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2106 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2107 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2108 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2109 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2110 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2111 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2114 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2115 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2116 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2117 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2118 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2121 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2123 const struct rtl_mac_info *p = mac_info;
2124 enum mac_version ver;
2126 while ((xid & p->mask) != p->val)
2130 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2131 if (ver == RTL_GIGA_MAC_VER_42)
2132 ver = RTL_GIGA_MAC_VER_43;
2133 else if (ver == RTL_GIGA_MAC_VER_46)
2134 ver = RTL_GIGA_MAC_VER_48;
2140 static void rtl_release_firmware(struct rtl8169_private *tp)
2143 rtl_fw_release_firmware(tp->rtl_fw);
2149 void r8169_apply_firmware(struct rtl8169_private *tp)
2153 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2155 rtl_fw_write_firmware(tp, tp->rtl_fw);
2156 /* At least one firmware doesn't reset tp->ocp_base. */
2157 tp->ocp_base = OCP_STD_PHY_BASE;
2159 /* PHY soft reset may still be in progress */
2160 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2161 !(val & BMCR_RESET),
2162 50000, 600000, true);
2166 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2168 /* Adjust EEE LED frequency */
2169 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2170 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2172 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2175 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2177 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2178 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2181 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2183 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2186 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2188 rtl8125_set_eee_txidle_timer(tp);
2189 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2192 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2194 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2195 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2196 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2197 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2200 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2202 u16 data1, data2, ioffset;
2204 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2205 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2206 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2208 ioffset = (data2 >> 1) & 0x7ff8;
2209 ioffset |= data2 & 0x0007;
2216 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2218 set_bit(flag, tp->wk.flags);
2219 schedule_work(&tp->wk.work);
2222 static void rtl8169_init_phy(struct rtl8169_private *tp)
2224 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2226 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2227 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2228 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2229 /* set undocumented MAC Reg C+CR Offset 0x82h */
2230 RTL_W8(tp, 0x82, 0x01);
2233 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2234 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2235 tp->pci_dev->subsystem_device == 0xe000)
2236 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2238 /* We may have called phy_speed_down before */
2239 phy_speed_up(tp->phydev);
2241 if (rtl_supports_eee(tp))
2244 genphy_soft_reset(tp->phydev);
2247 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2249 rtl_unlock_config_regs(tp);
2251 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2254 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2257 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2258 rtl_rar_exgmac_set(tp, addr);
2260 rtl_lock_config_regs(tp);
2263 static int rtl_set_mac_address(struct net_device *dev, void *p)
2265 struct rtl8169_private *tp = netdev_priv(dev);
2268 ret = eth_mac_addr(dev, p);
2272 rtl_rar_set(tp, dev->dev_addr);
2277 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2279 switch (tp->mac_version) {
2280 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2281 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2282 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2284 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2285 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2286 case RTL_GIGA_MAC_VER_38:
2287 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2289 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2290 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2292 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2293 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2296 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2301 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2303 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2306 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2308 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2309 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2312 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2314 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2315 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2318 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2320 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2323 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2325 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2328 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2330 RTL_W8(tp, MaxTxPacketSize, 0x24);
2331 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2332 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2335 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2337 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2338 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2339 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2342 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2344 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2347 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2349 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2352 static void rtl_jumbo_config(struct rtl8169_private *tp)
2354 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2357 rtl_unlock_config_regs(tp);
2358 switch (tp->mac_version) {
2359 case RTL_GIGA_MAC_VER_17:
2362 r8168b_1_hw_jumbo_enable(tp);
2364 r8168b_1_hw_jumbo_disable(tp);
2367 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2370 r8168c_hw_jumbo_enable(tp);
2372 r8168c_hw_jumbo_disable(tp);
2375 case RTL_GIGA_MAC_VER_28:
2377 r8168dp_hw_jumbo_enable(tp);
2379 r8168dp_hw_jumbo_disable(tp);
2381 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2383 r8168e_hw_jumbo_enable(tp);
2385 r8168e_hw_jumbo_disable(tp);
2390 rtl_lock_config_regs(tp);
2392 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2393 pcie_set_readrq(tp->pci_dev, readrq);
2395 /* Chip doesn't support pause in jumbo mode */
2397 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2398 tp->phydev->advertising);
2399 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2400 tp->phydev->advertising);
2401 phy_start_aneg(tp->phydev);
2405 DECLARE_RTL_COND(rtl_chipcmd_cond)
2407 return RTL_R8(tp, ChipCmd) & CmdReset;
2410 static void rtl_hw_reset(struct rtl8169_private *tp)
2412 RTL_W8(tp, ChipCmd, CmdReset);
2414 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2417 static void rtl_request_firmware(struct rtl8169_private *tp)
2419 struct rtl_fw *rtl_fw;
2421 /* firmware loaded already or no firmware available */
2422 if (tp->rtl_fw || !tp->fw_name)
2425 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2429 rtl_fw->phy_write = rtl_writephy;
2430 rtl_fw->phy_read = rtl_readphy;
2431 rtl_fw->mac_mcu_write = mac_mcu_write;
2432 rtl_fw->mac_mcu_read = mac_mcu_read;
2433 rtl_fw->fw_name = tp->fw_name;
2434 rtl_fw->dev = tp_to_dev(tp);
2436 if (rtl_fw_request_firmware(rtl_fw))
2439 tp->rtl_fw = rtl_fw;
2442 static void rtl_rx_close(struct rtl8169_private *tp)
2444 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2447 DECLARE_RTL_COND(rtl_npq_cond)
2449 return RTL_R8(tp, TxPoll) & NPQ;
2452 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2454 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2457 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2459 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2462 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2464 /* IntrMitigate has new functionality on RTL8125 */
2465 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2468 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2470 switch (tp->mac_version) {
2471 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2472 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2473 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2475 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2476 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2478 case RTL_GIGA_MAC_VER_63:
2479 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2480 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2481 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2488 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2490 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2493 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2495 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2497 rtl_wait_txrx_fifo_empty(tp);
2500 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2502 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2503 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2504 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2506 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2507 rtl_disable_rxdvgate(tp);
2510 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2512 if (tp->dash_type != RTL_DASH_NONE)
2515 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2516 tp->mac_version == RTL_GIGA_MAC_VER_33)
2517 rtl_ephy_write(tp, 0x19, 0xff64);
2519 if (device_may_wakeup(tp_to_dev(tp))) {
2520 phy_speed_down(tp->phydev, false);
2521 rtl_wol_enable_rx(tp);
2525 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2527 u32 val = TX_DMA_BURST << TxDMAShift |
2528 InterFrameGap << TxInterFrameGapShift;
2530 if (rtl_is_8168evl_up(tp))
2531 val |= TXCFG_AUTO_FIFO;
2533 RTL_W32(tp, TxConfig, val);
2536 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2538 /* Low hurts. Let's disable the filtering. */
2539 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2542 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2545 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2546 * register to be written before TxDescAddrLow to work.
2547 * Switching from MMIO to I/O access fixes the issue as well.
2549 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2550 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2551 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2552 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2555 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2559 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2561 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2566 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2569 RTL_W32(tp, 0x7c, val);
2572 static void rtl_set_rx_mode(struct net_device *dev)
2574 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2575 /* Multicast hash filter */
2576 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2577 struct rtl8169_private *tp = netdev_priv(dev);
2580 if (dev->flags & IFF_PROMISC) {
2581 rx_mode |= AcceptAllPhys;
2582 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2583 dev->flags & IFF_ALLMULTI ||
2584 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2585 /* accept all multicasts */
2586 } else if (netdev_mc_empty(dev)) {
2587 rx_mode &= ~AcceptMulticast;
2589 struct netdev_hw_addr *ha;
2591 mc_filter[1] = mc_filter[0] = 0;
2592 netdev_for_each_mc_addr(ha, dev) {
2593 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2594 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2597 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2599 mc_filter[0] = swab32(mc_filter[1]);
2600 mc_filter[1] = swab32(tmp);
2604 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2605 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2607 tmp = RTL_R32(tp, RxConfig);
2608 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2611 DECLARE_RTL_COND(rtl_csiar_cond)
2613 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2616 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2618 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2620 RTL_W32(tp, CSIDR, value);
2621 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2622 CSIAR_BYTE_ENABLE | func << 16);
2624 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2627 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2629 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2631 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2634 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2635 RTL_R32(tp, CSIDR) : ~0;
2638 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2640 struct pci_dev *pdev = tp->pci_dev;
2643 /* According to Realtek the value at config space address 0x070f
2644 * controls the L0s/L1 entrance latency. We try standard ECAM access
2645 * first and if it fails fall back to CSI.
2646 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2647 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2649 if (pdev->cfg_size > 0x070f &&
2650 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2653 netdev_notice_once(tp->dev,
2654 "No native access to PCI extended config space, falling back to CSI\n");
2655 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2656 rtl_csi_write(tp, 0x070c, csi | val << 24);
2659 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2661 /* L0 7us, L1 16us */
2662 rtl_set_aspm_entry_latency(tp, 0x27);
2666 unsigned int offset;
2671 static void __rtl_ephy_init(struct rtl8169_private *tp,
2672 const struct ephy_info *e, int len)
2677 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2678 rtl_ephy_write(tp, e->offset, w);
2683 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2685 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2687 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2688 PCI_EXP_LNKCTL_CLKREQ_EN);
2691 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2693 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2694 PCI_EXP_LNKCTL_CLKREQ_EN);
2697 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2699 /* work around an issue when PCI reset occurs during L2/L3 state */
2700 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2703 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2705 /* Bits control which events trigger ASPM L1 exit:
2708 * Bit 10: txdma_poll
2713 switch (tp->mac_version) {
2714 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2715 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2717 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2718 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2720 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2721 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2728 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2730 switch (tp->mac_version) {
2731 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2732 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2734 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
2735 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2742 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2744 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2747 /* Don't enable ASPM in the chip if OS can't control ASPM */
2748 if (enable && tp->aspm_manageable) {
2749 rtl_mod_config5(tp, 0, ASPM_en);
2750 rtl_mod_config2(tp, 0, ClkReqEn);
2752 switch (tp->mac_version) {
2753 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2754 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2755 /* reset ephy tx/rx disable timer */
2756 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2757 /* chip can trigger L1.2 */
2758 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2764 switch (tp->mac_version) {
2765 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2766 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
2767 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
2773 rtl_mod_config2(tp, ClkReqEn, 0);
2774 rtl_mod_config5(tp, ASPM_en, 0);
2778 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2779 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2781 /* Usage of dynamic vs. static FIFO is controlled by bit
2782 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2784 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2785 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2788 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2791 /* FIFO thresholds for pause flow control */
2792 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2793 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2796 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2798 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2801 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2803 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2805 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2807 rtl_disable_clock_request(tp);
2810 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2812 static const struct ephy_info e_info_8168cp[] = {
2813 { 0x01, 0, 0x0001 },
2814 { 0x02, 0x0800, 0x1000 },
2815 { 0x03, 0, 0x0042 },
2816 { 0x06, 0x0080, 0x0000 },
2820 rtl_set_def_aspm_entry_latency(tp);
2822 rtl_ephy_init(tp, e_info_8168cp);
2824 __rtl_hw_start_8168cp(tp);
2827 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2829 rtl_set_def_aspm_entry_latency(tp);
2831 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2834 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2836 rtl_set_def_aspm_entry_latency(tp);
2838 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2841 RTL_W8(tp, DBG_REG, 0x20);
2844 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2846 static const struct ephy_info e_info_8168c_1[] = {
2847 { 0x02, 0x0800, 0x1000 },
2848 { 0x03, 0, 0x0002 },
2849 { 0x06, 0x0080, 0x0000 }
2852 rtl_set_def_aspm_entry_latency(tp);
2854 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2856 rtl_ephy_init(tp, e_info_8168c_1);
2858 __rtl_hw_start_8168cp(tp);
2861 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2863 static const struct ephy_info e_info_8168c_2[] = {
2864 { 0x01, 0, 0x0001 },
2865 { 0x03, 0x0400, 0x0020 }
2868 rtl_set_def_aspm_entry_latency(tp);
2870 rtl_ephy_init(tp, e_info_8168c_2);
2872 __rtl_hw_start_8168cp(tp);
2875 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2877 rtl_set_def_aspm_entry_latency(tp);
2879 __rtl_hw_start_8168cp(tp);
2882 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2884 rtl_set_def_aspm_entry_latency(tp);
2886 rtl_disable_clock_request(tp);
2889 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2891 static const struct ephy_info e_info_8168d_4[] = {
2892 { 0x0b, 0x0000, 0x0048 },
2893 { 0x19, 0x0020, 0x0050 },
2894 { 0x0c, 0x0100, 0x0020 },
2895 { 0x10, 0x0004, 0x0000 },
2898 rtl_set_def_aspm_entry_latency(tp);
2900 rtl_ephy_init(tp, e_info_8168d_4);
2902 rtl_enable_clock_request(tp);
2905 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2907 static const struct ephy_info e_info_8168e_1[] = {
2908 { 0x00, 0x0200, 0x0100 },
2909 { 0x00, 0x0000, 0x0004 },
2910 { 0x06, 0x0002, 0x0001 },
2911 { 0x06, 0x0000, 0x0030 },
2912 { 0x07, 0x0000, 0x2000 },
2913 { 0x00, 0x0000, 0x0020 },
2914 { 0x03, 0x5800, 0x2000 },
2915 { 0x03, 0x0000, 0x0001 },
2916 { 0x01, 0x0800, 0x1000 },
2917 { 0x07, 0x0000, 0x4000 },
2918 { 0x1e, 0x0000, 0x2000 },
2919 { 0x19, 0xffff, 0xfe6c },
2920 { 0x0a, 0x0000, 0x0040 }
2923 rtl_set_def_aspm_entry_latency(tp);
2925 rtl_ephy_init(tp, e_info_8168e_1);
2927 rtl_disable_clock_request(tp);
2929 /* Reset tx FIFO pointer */
2930 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2931 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2933 rtl_mod_config5(tp, Spi_en, 0);
2936 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2938 static const struct ephy_info e_info_8168e_2[] = {
2939 { 0x09, 0x0000, 0x0080 },
2940 { 0x19, 0x0000, 0x0224 },
2941 { 0x00, 0x0000, 0x0004 },
2942 { 0x0c, 0x3df0, 0x0200 },
2945 rtl_set_def_aspm_entry_latency(tp);
2947 rtl_ephy_init(tp, e_info_8168e_2);
2949 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2950 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2951 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2952 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2953 rtl_reset_packet_filter(tp);
2954 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2955 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2956 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2958 rtl_disable_clock_request(tp);
2960 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2962 rtl8168_config_eee_mac(tp);
2964 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2965 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2966 rtl_mod_config5(tp, Spi_en, 0);
2968 rtl_hw_aspm_clkreq_enable(tp, true);
2971 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2973 rtl_set_def_aspm_entry_latency(tp);
2975 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2976 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2977 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2978 rtl_reset_packet_filter(tp);
2979 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2980 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2981 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2982 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2984 rtl_disable_clock_request(tp);
2986 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2987 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2988 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2989 rtl_mod_config5(tp, Spi_en, 0);
2991 rtl8168_config_eee_mac(tp);
2994 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2996 static const struct ephy_info e_info_8168f_1[] = {
2997 { 0x06, 0x00c0, 0x0020 },
2998 { 0x08, 0x0001, 0x0002 },
2999 { 0x09, 0x0000, 0x0080 },
3000 { 0x19, 0x0000, 0x0224 },
3001 { 0x00, 0x0000, 0x0008 },
3002 { 0x0c, 0x3df0, 0x0200 },
3005 rtl_hw_start_8168f(tp);
3007 rtl_ephy_init(tp, e_info_8168f_1);
3010 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3012 static const struct ephy_info e_info_8168f_1[] = {
3013 { 0x06, 0x00c0, 0x0020 },
3014 { 0x0f, 0xffff, 0x5200 },
3015 { 0x19, 0x0000, 0x0224 },
3016 { 0x00, 0x0000, 0x0008 },
3017 { 0x0c, 0x3df0, 0x0200 },
3020 rtl_hw_start_8168f(tp);
3021 rtl_pcie_state_l2l3_disable(tp);
3023 rtl_ephy_init(tp, e_info_8168f_1);
3026 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3028 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3029 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3031 rtl_set_def_aspm_entry_latency(tp);
3033 rtl_reset_packet_filter(tp);
3034 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3036 rtl_disable_rxdvgate(tp);
3038 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3039 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3041 rtl8168_config_eee_mac(tp);
3043 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3044 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3046 rtl_pcie_state_l2l3_disable(tp);
3049 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3051 static const struct ephy_info e_info_8168g_1[] = {
3052 { 0x00, 0x0008, 0x0000 },
3053 { 0x0c, 0x3ff0, 0x0820 },
3054 { 0x1e, 0x0000, 0x0001 },
3055 { 0x19, 0x8000, 0x0000 }
3058 rtl_hw_start_8168g(tp);
3060 /* disable aspm and clock request before access ephy */
3061 rtl_hw_aspm_clkreq_enable(tp, false);
3062 rtl_ephy_init(tp, e_info_8168g_1);
3063 rtl_hw_aspm_clkreq_enable(tp, true);
3066 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3068 static const struct ephy_info e_info_8168g_2[] = {
3069 { 0x00, 0x0008, 0x0000 },
3070 { 0x0c, 0x3ff0, 0x0820 },
3071 { 0x19, 0xffff, 0x7c00 },
3072 { 0x1e, 0xffff, 0x20eb },
3073 { 0x0d, 0xffff, 0x1666 },
3074 { 0x00, 0xffff, 0x10a3 },
3075 { 0x06, 0xffff, 0xf050 },
3076 { 0x04, 0x0000, 0x0010 },
3077 { 0x1d, 0x4000, 0x0000 },
3080 rtl_hw_start_8168g(tp);
3082 /* disable aspm and clock request before access ephy */
3083 rtl_hw_aspm_clkreq_enable(tp, false);
3084 rtl_ephy_init(tp, e_info_8168g_2);
3087 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3089 static const struct ephy_info e_info_8411_2[] = {
3090 { 0x00, 0x0008, 0x0000 },
3091 { 0x0c, 0x37d0, 0x0820 },
3092 { 0x1e, 0x0000, 0x0001 },
3093 { 0x19, 0x8021, 0x0000 },
3094 { 0x1e, 0x0000, 0x2000 },
3095 { 0x0d, 0x0100, 0x0200 },
3096 { 0x00, 0x0000, 0x0080 },
3097 { 0x06, 0x0000, 0x0010 },
3098 { 0x04, 0x0000, 0x0010 },
3099 { 0x1d, 0x0000, 0x4000 },
3102 rtl_hw_start_8168g(tp);
3104 /* disable aspm and clock request before access ephy */
3105 rtl_hw_aspm_clkreq_enable(tp, false);
3106 rtl_ephy_init(tp, e_info_8411_2);
3108 /* The following Realtek-provided magic fixes an issue with the RX unit
3109 * getting confused after the PHY having been powered-down.
3111 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3112 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3113 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3114 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3115 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3116 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3117 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3118 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3120 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3122 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3123 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3124 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3125 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3126 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3127 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3128 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3129 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3130 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3131 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3132 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3133 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3134 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3135 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3136 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3137 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3138 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3139 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3140 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3141 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3142 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3143 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3144 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3145 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3146 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3147 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3148 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3149 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3150 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3151 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3152 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3153 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3154 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3155 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3156 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3157 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3158 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3159 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3160 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3161 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3162 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3163 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3164 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3165 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3166 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3167 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3168 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3169 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3170 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3171 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3172 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3173 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3174 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3175 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3176 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3177 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3178 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3179 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3180 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3181 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3182 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3183 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3184 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3185 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3186 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3187 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3188 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3189 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3190 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3191 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3192 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3193 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3194 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3195 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3196 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3197 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3198 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3199 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3200 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3201 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3202 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3203 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3204 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3205 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3206 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3207 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3208 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3209 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3210 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3211 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3212 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3213 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3214 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3215 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3216 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3217 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3218 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3219 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3220 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3221 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3222 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3223 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3224 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3225 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3226 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3227 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3228 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3229 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3230 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3231 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3232 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3234 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3236 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3237 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3238 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3239 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3240 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3241 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3242 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3244 rtl_hw_aspm_clkreq_enable(tp, true);
3247 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3249 static const struct ephy_info e_info_8168h_1[] = {
3250 { 0x1e, 0x0800, 0x0001 },
3251 { 0x1d, 0x0000, 0x0800 },
3252 { 0x05, 0xffff, 0x2089 },
3253 { 0x06, 0xffff, 0x5881 },
3254 { 0x04, 0xffff, 0x854a },
3255 { 0x01, 0xffff, 0x068b }
3259 /* disable aspm and clock request before access ephy */
3260 rtl_hw_aspm_clkreq_enable(tp, false);
3261 rtl_ephy_init(tp, e_info_8168h_1);
3263 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3264 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3266 rtl_set_def_aspm_entry_latency(tp);
3268 rtl_reset_packet_filter(tp);
3270 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3272 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3274 rtl_disable_rxdvgate(tp);
3276 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3277 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3279 rtl8168_config_eee_mac(tp);
3281 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3282 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3284 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3286 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3288 rtl_pcie_state_l2l3_disable(tp);
3290 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3291 if (rg_saw_cnt > 0) {
3294 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3295 sw_cnt_1ms_ini &= 0x0fff;
3296 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3299 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3300 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3301 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3302 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3304 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3305 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3306 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3307 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3309 rtl_hw_aspm_clkreq_enable(tp, true);
3312 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3314 rtl8168ep_stop_cmac(tp);
3316 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3317 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3319 rtl_set_def_aspm_entry_latency(tp);
3321 rtl_reset_packet_filter(tp);
3323 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3325 rtl_disable_rxdvgate(tp);
3327 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3328 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3330 rtl8168_config_eee_mac(tp);
3332 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3334 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3336 rtl_pcie_state_l2l3_disable(tp);
3339 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3341 static const struct ephy_info e_info_8168ep_3[] = {
3342 { 0x00, 0x0000, 0x0080 },
3343 { 0x0d, 0x0100, 0x0200 },
3344 { 0x19, 0x8021, 0x0000 },
3345 { 0x1e, 0x0000, 0x2000 },
3348 /* disable aspm and clock request before access ephy */
3349 rtl_hw_aspm_clkreq_enable(tp, false);
3350 rtl_ephy_init(tp, e_info_8168ep_3);
3352 rtl_hw_start_8168ep(tp);
3354 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3355 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3357 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3358 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3359 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3361 rtl_hw_aspm_clkreq_enable(tp, true);
3364 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3366 static const struct ephy_info e_info_8117[] = {
3367 { 0x19, 0x0040, 0x1100 },
3368 { 0x59, 0x0040, 0x1100 },
3372 rtl8168ep_stop_cmac(tp);
3374 /* disable aspm and clock request before access ephy */
3375 rtl_hw_aspm_clkreq_enable(tp, false);
3376 rtl_ephy_init(tp, e_info_8117);
3378 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3379 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3381 rtl_set_def_aspm_entry_latency(tp);
3383 rtl_reset_packet_filter(tp);
3385 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3389 rtl_disable_rxdvgate(tp);
3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3394 rtl8168_config_eee_mac(tp);
3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3397 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3399 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3401 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3403 rtl_pcie_state_l2l3_disable(tp);
3405 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3406 if (rg_saw_cnt > 0) {
3409 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3410 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3413 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3414 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3415 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3416 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3418 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3420 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3421 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3423 /* firmware is for MAC only */
3424 r8169_apply_firmware(tp);
3426 rtl_hw_aspm_clkreq_enable(tp, true);
3429 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3431 static const struct ephy_info e_info_8102e_1[] = {
3432 { 0x01, 0, 0x6e65 },
3433 { 0x02, 0, 0x091f },
3434 { 0x03, 0, 0xc2f9 },
3435 { 0x06, 0, 0xafb5 },
3436 { 0x07, 0, 0x0e00 },
3437 { 0x19, 0, 0xec80 },
3438 { 0x01, 0, 0x2e65 },
3443 rtl_set_def_aspm_entry_latency(tp);
3445 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3448 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3449 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3451 cfg1 = RTL_R8(tp, Config1);
3452 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3453 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3455 rtl_ephy_init(tp, e_info_8102e_1);
3458 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3460 rtl_set_def_aspm_entry_latency(tp);
3462 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3463 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3466 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3468 rtl_hw_start_8102e_2(tp);
3470 rtl_ephy_write(tp, 0x03, 0xc2f9);
3473 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3475 static const struct ephy_info e_info_8401[] = {
3476 { 0x01, 0xffff, 0x6fe5 },
3477 { 0x03, 0xffff, 0x0599 },
3478 { 0x06, 0xffff, 0xaf25 },
3479 { 0x07, 0xffff, 0x8e68 },
3482 rtl_ephy_init(tp, e_info_8401);
3483 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3486 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3488 static const struct ephy_info e_info_8105e_1[] = {
3489 { 0x07, 0, 0x4000 },
3490 { 0x19, 0, 0x0200 },
3491 { 0x19, 0, 0x0020 },
3492 { 0x1e, 0, 0x2000 },
3493 { 0x03, 0, 0x0001 },
3494 { 0x19, 0, 0x0100 },
3495 { 0x19, 0, 0x0004 },
3499 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3500 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3502 /* Disable Early Tally Counter */
3503 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3505 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3506 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3508 rtl_ephy_init(tp, e_info_8105e_1);
3510 rtl_pcie_state_l2l3_disable(tp);
3513 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3515 rtl_hw_start_8105e_1(tp);
3516 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3519 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3521 static const struct ephy_info e_info_8402[] = {
3522 { 0x19, 0xffff, 0xff64 },
3526 rtl_set_def_aspm_entry_latency(tp);
3528 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3529 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3533 rtl_ephy_init(tp, e_info_8402);
3535 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3536 rtl_reset_packet_filter(tp);
3537 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3538 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3539 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3542 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3544 rtl_pcie_state_l2l3_disable(tp);
3547 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3549 rtl_hw_aspm_clkreq_enable(tp, false);
3551 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3552 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3554 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3555 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3556 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3558 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3559 rtl_set_aspm_entry_latency(tp, 0x2f);
3561 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3564 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3566 rtl_pcie_state_l2l3_disable(tp);
3567 rtl_hw_aspm_clkreq_enable(tp, true);
3570 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3572 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3575 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3577 rtl_pcie_state_l2l3_disable(tp);
3579 RTL_W16(tp, 0x382, 0x221b);
3580 RTL_W8(tp, 0x4500, 0);
3581 RTL_W16(tp, 0x4800, 0);
3584 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3586 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3588 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3589 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3591 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3592 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3593 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3595 /* disable new tx descriptor format */
3596 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3598 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3599 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3601 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3603 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3604 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3606 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3608 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3609 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3610 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3611 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3612 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3613 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3614 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3615 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3616 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3618 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3619 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3621 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3622 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3624 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3626 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3628 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3629 rtl8125b_config_eee_mac(tp);
3631 rtl8125a_config_eee_mac(tp);
3633 rtl_disable_rxdvgate(tp);
3636 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3638 static const struct ephy_info e_info_8125a_2[] = {
3639 { 0x04, 0xffff, 0xd000 },
3640 { 0x0a, 0xffff, 0x8653 },
3641 { 0x23, 0xffff, 0xab66 },
3642 { 0x20, 0xffff, 0x9455 },
3643 { 0x21, 0xffff, 0x99ff },
3644 { 0x29, 0xffff, 0xfe04 },
3646 { 0x44, 0xffff, 0xd000 },
3647 { 0x4a, 0xffff, 0x8653 },
3648 { 0x63, 0xffff, 0xab66 },
3649 { 0x60, 0xffff, 0x9455 },
3650 { 0x61, 0xffff, 0x99ff },
3651 { 0x69, 0xffff, 0xfe04 },
3654 rtl_set_def_aspm_entry_latency(tp);
3656 /* disable aspm and clock request before access ephy */
3657 rtl_hw_aspm_clkreq_enable(tp, false);
3658 rtl_ephy_init(tp, e_info_8125a_2);
3660 rtl_hw_start_8125_common(tp);
3661 rtl_hw_aspm_clkreq_enable(tp, true);
3664 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3666 static const struct ephy_info e_info_8125b[] = {
3667 { 0x0b, 0xffff, 0xa908 },
3668 { 0x1e, 0xffff, 0x20eb },
3669 { 0x4b, 0xffff, 0xa908 },
3670 { 0x5e, 0xffff, 0x20eb },
3671 { 0x22, 0x0030, 0x0020 },
3672 { 0x62, 0x0030, 0x0020 },
3675 rtl_set_def_aspm_entry_latency(tp);
3676 rtl_hw_aspm_clkreq_enable(tp, false);
3678 rtl_ephy_init(tp, e_info_8125b);
3679 rtl_hw_start_8125_common(tp);
3681 rtl_hw_aspm_clkreq_enable(tp, true);
3684 static void rtl_hw_config(struct rtl8169_private *tp)
3686 static const rtl_generic_fct hw_configs[] = {
3687 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3688 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3689 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3690 [RTL_GIGA_MAC_VER_10] = NULL,
3691 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3692 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3693 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3694 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3695 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3696 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3697 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3698 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3699 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3700 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3701 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3702 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3703 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3704 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3705 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3706 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3707 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3708 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3709 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3710 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3711 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3712 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3713 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3714 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3715 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3716 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3717 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3718 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3719 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3720 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3721 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3722 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3723 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3724 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3725 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3728 if (hw_configs[tp->mac_version])
3729 hw_configs[tp->mac_version](tp);
3732 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3736 /* disable interrupt coalescing */
3737 for (i = 0xa00; i < 0xb00; i += 4)
3743 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3745 if (rtl_is_8168evl_up(tp))
3746 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3748 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3752 /* disable interrupt coalescing */
3753 RTL_W16(tp, IntrMitigate, 0x0000);
3756 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3758 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3760 tp->cp_cmd |= PCIMulRW;
3762 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3763 tp->mac_version == RTL_GIGA_MAC_VER_03)
3764 tp->cp_cmd |= EnAnaPLL;
3766 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3768 rtl8169_set_magic_reg(tp);
3770 /* disable interrupt coalescing */
3771 RTL_W16(tp, IntrMitigate, 0x0000);
3774 static void rtl_hw_start(struct rtl8169_private *tp)
3776 rtl_unlock_config_regs(tp);
3778 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3780 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3781 rtl_hw_start_8169(tp);
3782 else if (rtl_is_8125(tp))
3783 rtl_hw_start_8125(tp);
3785 rtl_hw_start_8168(tp);
3787 rtl_enable_exit_l1(tp);
3788 rtl_set_rx_max_size(tp);
3789 rtl_set_rx_tx_desc_registers(tp);
3790 rtl_lock_config_regs(tp);
3792 rtl_jumbo_config(tp);
3794 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3797 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3799 rtl_set_tx_config_registers(tp);
3800 rtl_set_rx_config_features(tp, tp->dev->features);
3801 rtl_set_rx_mode(tp->dev);
3805 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3807 struct rtl8169_private *tp = netdev_priv(dev);
3810 netdev_update_features(dev);
3811 rtl_jumbo_config(tp);
3813 switch (tp->mac_version) {
3814 case RTL_GIGA_MAC_VER_61:
3815 case RTL_GIGA_MAC_VER_63:
3816 rtl8125_set_eee_txidle_timer(tp);
3825 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3827 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3830 /* Force memory writes to complete before releasing descriptor */
3832 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3835 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3836 struct RxDesc *desc)
3838 struct device *d = tp_to_dev(tp);
3839 int node = dev_to_node(d);
3843 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3847 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3848 if (unlikely(dma_mapping_error(d, mapping))) {
3849 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3850 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3854 desc->addr = cpu_to_le64(mapping);
3855 rtl8169_mark_to_asic(desc);
3860 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3864 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3865 dma_unmap_page(tp_to_dev(tp),
3866 le64_to_cpu(tp->RxDescArray[i].addr),
3867 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3868 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3869 tp->Rx_databuff[i] = NULL;
3870 tp->RxDescArray[i].addr = 0;
3871 tp->RxDescArray[i].opts1 = 0;
3875 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3879 for (i = 0; i < NUM_RX_DESC; i++) {
3882 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3884 rtl8169_rx_clear(tp);
3887 tp->Rx_databuff[i] = data;
3890 /* mark as last descriptor in the ring */
3891 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3896 static int rtl8169_init_ring(struct rtl8169_private *tp)
3898 rtl8169_init_ring_indexes(tp);
3900 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3901 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3903 return rtl8169_rx_fill(tp);
3906 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3908 struct ring_info *tx_skb = tp->tx_skb + entry;
3909 struct TxDesc *desc = tp->TxDescArray + entry;
3911 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3913 memset(desc, 0, sizeof(*desc));
3914 memset(tx_skb, 0, sizeof(*tx_skb));
3917 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3922 for (i = 0; i < n; i++) {
3923 unsigned int entry = (start + i) % NUM_TX_DESC;
3924 struct ring_info *tx_skb = tp->tx_skb + entry;
3925 unsigned int len = tx_skb->len;
3928 struct sk_buff *skb = tx_skb->skb;
3930 rtl8169_unmap_tx_skb(tp, entry);
3932 dev_consume_skb_any(skb);
3937 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3939 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3940 netdev_reset_queue(tp->dev);
3943 static void rtl8169_cleanup(struct rtl8169_private *tp)
3945 napi_disable(&tp->napi);
3947 /* Give a racing hard_start_xmit a few cycles to complete. */
3950 /* Disable interrupts */
3951 rtl8169_irq_mask_and_ack(tp);
3955 switch (tp->mac_version) {
3956 case RTL_GIGA_MAC_VER_28:
3957 case RTL_GIGA_MAC_VER_31:
3958 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3960 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3961 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3962 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3964 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3965 rtl_enable_rxdvgate(tp);
3969 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3976 rtl8169_tx_clear(tp);
3977 rtl8169_init_ring_indexes(tp);
3980 static void rtl_reset_work(struct rtl8169_private *tp)
3984 netif_stop_queue(tp->dev);
3986 rtl8169_cleanup(tp);
3988 for (i = 0; i < NUM_RX_DESC; i++)
3989 rtl8169_mark_to_asic(tp->RxDescArray + i);
3991 napi_enable(&tp->napi);
3995 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
3997 struct rtl8169_private *tp = netdev_priv(dev);
3999 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4002 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4003 void *addr, unsigned int entry, bool desc_own)
4005 struct TxDesc *txd = tp->TxDescArray + entry;
4006 struct device *d = tp_to_dev(tp);
4011 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4012 ret = dma_mapping_error(d, mapping);
4013 if (unlikely(ret)) {
4014 if (net_ratelimit())
4015 netdev_err(tp->dev, "Failed to map TX data!\n");
4019 txd->addr = cpu_to_le64(mapping);
4020 txd->opts2 = cpu_to_le32(opts[1]);
4022 opts1 = opts[0] | len;
4023 if (entry == NUM_TX_DESC - 1)
4027 txd->opts1 = cpu_to_le32(opts1);
4029 tp->tx_skb[entry].len = len;
4034 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4035 const u32 *opts, unsigned int entry)
4037 struct skb_shared_info *info = skb_shinfo(skb);
4038 unsigned int cur_frag;
4040 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4041 const skb_frag_t *frag = info->frags + cur_frag;
4042 void *addr = skb_frag_address(frag);
4043 u32 len = skb_frag_size(frag);
4045 entry = (entry + 1) % NUM_TX_DESC;
4047 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4054 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4058 static bool rtl_skb_is_udp(struct sk_buff *skb)
4060 int no = skb_network_offset(skb);
4061 struct ipv6hdr *i6h, _i6h;
4062 struct iphdr *ih, _ih;
4064 switch (vlan_get_protocol(skb)) {
4065 case htons(ETH_P_IP):
4066 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4067 return ih && ih->protocol == IPPROTO_UDP;
4068 case htons(ETH_P_IPV6):
4069 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4070 return i6h && i6h->nexthdr == IPPROTO_UDP;
4076 #define RTL_MIN_PATCH_LEN 47
4078 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
4079 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4080 struct sk_buff *skb)
4082 unsigned int padto = 0, len = skb->len;
4084 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4085 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4086 unsigned int trans_data_len = skb_tail_pointer(skb) -
4087 skb_transport_header(skb);
4089 if (trans_data_len >= offsetof(struct udphdr, len) &&
4090 trans_data_len < RTL_MIN_PATCH_LEN) {
4091 u16 dest = ntohs(udp_hdr(skb)->dest);
4093 /* dest is a standard PTP port */
4094 if (dest == 319 || dest == 320)
4095 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4098 if (trans_data_len < sizeof(struct udphdr))
4099 padto = max_t(unsigned int, padto,
4100 len + sizeof(struct udphdr) - trans_data_len);
4106 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4107 struct sk_buff *skb)
4111 padto = rtl8125_quirk_udp_padto(tp, skb);
4113 switch (tp->mac_version) {
4114 case RTL_GIGA_MAC_VER_34:
4115 case RTL_GIGA_MAC_VER_61:
4116 case RTL_GIGA_MAC_VER_63:
4117 padto = max_t(unsigned int, padto, ETH_ZLEN);
4126 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4128 u32 mss = skb_shinfo(skb)->gso_size;
4132 opts[0] |= mss << TD0_MSS_SHIFT;
4133 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4134 const struct iphdr *ip = ip_hdr(skb);
4136 if (ip->protocol == IPPROTO_TCP)
4137 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4138 else if (ip->protocol == IPPROTO_UDP)
4139 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4145 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4146 struct sk_buff *skb, u32 *opts)
4148 struct skb_shared_info *shinfo = skb_shinfo(skb);
4149 u32 mss = shinfo->gso_size;
4152 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4153 opts[0] |= TD1_GTSENV4;
4154 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4155 if (skb_cow_head(skb, 0))
4158 tcp_v6_gso_csum_prep(skb);
4159 opts[0] |= TD1_GTSENV6;
4164 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4165 opts[1] |= mss << TD1_MSS_SHIFT;
4166 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4169 switch (vlan_get_protocol(skb)) {
4170 case htons(ETH_P_IP):
4171 opts[1] |= TD1_IPv4_CS;
4172 ip_protocol = ip_hdr(skb)->protocol;
4175 case htons(ETH_P_IPV6):
4176 opts[1] |= TD1_IPv6_CS;
4177 ip_protocol = ipv6_hdr(skb)->nexthdr;
4181 ip_protocol = IPPROTO_RAW;
4185 if (ip_protocol == IPPROTO_TCP)
4186 opts[1] |= TD1_TCP_CS;
4187 else if (ip_protocol == IPPROTO_UDP)
4188 opts[1] |= TD1_UDP_CS;
4192 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4194 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4196 /* skb_padto would free the skb on error */
4197 return !__skb_put_padto(skb, padto, false);
4203 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4205 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4206 - READ_ONCE(tp->cur_tx);
4208 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4209 return slots_avail > MAX_SKB_FRAGS;
4212 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4213 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4215 switch (tp->mac_version) {
4216 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4217 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4224 static void rtl8169_doorbell(struct rtl8169_private *tp)
4226 if (rtl_is_8125(tp))
4227 RTL_W16(tp, TxPoll_8125, BIT(0));
4229 RTL_W8(tp, TxPoll, NPQ);
4232 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4233 struct net_device *dev)
4235 unsigned int frags = skb_shinfo(skb)->nr_frags;
4236 struct rtl8169_private *tp = netdev_priv(dev);
4237 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4238 struct TxDesc *txd_first, *txd_last;
4239 bool stop_queue, door_bell;
4242 if (unlikely(!rtl_tx_slots_avail(tp))) {
4243 if (net_ratelimit())
4244 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4248 opts[1] = rtl8169_tx_vlan_tag(skb);
4251 if (!rtl_chip_supports_csum_v2(tp))
4252 rtl8169_tso_csum_v1(skb, opts);
4253 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4256 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4260 txd_first = tp->TxDescArray + entry;
4263 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4265 entry = (entry + frags) % NUM_TX_DESC;
4268 txd_last = tp->TxDescArray + entry;
4269 txd_last->opts1 |= cpu_to_le32(LastFrag);
4270 tp->tx_skb[entry].skb = skb;
4272 skb_tx_timestamp(skb);
4274 /* Force memory writes to complete before releasing descriptor */
4277 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4279 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4281 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4284 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4286 stop_queue = !rtl_tx_slots_avail(tp);
4287 if (unlikely(stop_queue)) {
4288 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4289 * not miss a ring update when it notices a stopped queue.
4292 netif_stop_queue(dev);
4293 /* Sync with rtl_tx:
4294 * - publish queue status and cur_tx ring index (write barrier)
4295 * - refresh dirty_tx ring index (read barrier).
4296 * May the current thread have a pessimistic view of the ring
4297 * status and forget to wake up queue, a racing rtl_tx thread
4300 smp_mb__after_atomic();
4301 if (rtl_tx_slots_avail(tp))
4302 netif_start_queue(dev);
4307 rtl8169_doorbell(tp);
4309 return NETDEV_TX_OK;
4312 rtl8169_unmap_tx_skb(tp, entry);
4314 dev_kfree_skb_any(skb);
4315 dev->stats.tx_dropped++;
4316 return NETDEV_TX_OK;
4319 netif_stop_queue(dev);
4320 dev->stats.tx_dropped++;
4321 return NETDEV_TX_BUSY;
4324 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4326 struct skb_shared_info *info = skb_shinfo(skb);
4327 unsigned int nr_frags = info->nr_frags;
4332 return skb_frag_size(info->frags + nr_frags - 1);
4335 /* Workaround for hw issues with TSO on RTL8168evl */
4336 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4337 netdev_features_t features)
4339 /* IPv4 header has options field */
4340 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4341 ip_hdrlen(skb) > sizeof(struct iphdr))
4342 features &= ~NETIF_F_ALL_TSO;
4344 /* IPv4 TCP header has options field */
4345 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4346 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4347 features &= ~NETIF_F_ALL_TSO;
4349 else if (rtl_last_frag_len(skb) <= 6)
4350 features &= ~NETIF_F_ALL_TSO;
4355 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4356 struct net_device *dev,
4357 netdev_features_t features)
4359 struct rtl8169_private *tp = netdev_priv(dev);
4361 if (skb_is_gso(skb)) {
4362 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4363 features = rtl8168evl_fix_tso(skb, features);
4365 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4366 rtl_chip_supports_csum_v2(tp))
4367 features &= ~NETIF_F_ALL_TSO;
4368 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4369 /* work around hw bug on some chip versions */
4370 if (skb->len < ETH_ZLEN)
4371 features &= ~NETIF_F_CSUM_MASK;
4373 if (rtl_quirk_packet_padto(tp, skb))
4374 features &= ~NETIF_F_CSUM_MASK;
4376 if (skb_transport_offset(skb) > TCPHO_MAX &&
4377 rtl_chip_supports_csum_v2(tp))
4378 features &= ~NETIF_F_CSUM_MASK;
4381 return vlan_features_check(skb, features);
4384 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4386 struct rtl8169_private *tp = netdev_priv(dev);
4387 struct pci_dev *pdev = tp->pci_dev;
4388 int pci_status_errs;
4391 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4393 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4395 if (net_ratelimit())
4396 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4397 pci_cmd, pci_status_errs);
4399 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4402 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4405 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4406 struct sk_buff *skb;
4408 dirty_tx = tp->dirty_tx;
4410 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4411 unsigned int entry = dirty_tx % NUM_TX_DESC;
4414 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4415 if (status & DescOwn)
4418 skb = tp->tx_skb[entry].skb;
4419 rtl8169_unmap_tx_skb(tp, entry);
4423 bytes_compl += skb->len;
4424 napi_consume_skb(skb, budget);
4429 if (tp->dirty_tx != dirty_tx) {
4430 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4431 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4433 /* Sync with rtl8169_start_xmit:
4434 * - publish dirty_tx ring index (write barrier)
4435 * - refresh cur_tx ring index and queue status (read barrier)
4436 * May the current thread miss the stopped queue condition,
4437 * a racing xmit thread can only have a right view of the
4440 smp_store_mb(tp->dirty_tx, dirty_tx);
4441 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4442 netif_wake_queue(dev);
4444 * 8168 hack: TxPoll requests are lost when the Tx packets are
4445 * too close. Let's kick an extra TxPoll request when a burst
4446 * of start_xmit activity is detected (if it is not detected,
4447 * it is slow enough). -- FR
4448 * If skb is NULL then we come here again once a tx irq is
4449 * triggered after the last fragment is marked transmitted.
4451 if (tp->cur_tx != dirty_tx && skb)
4452 rtl8169_doorbell(tp);
4456 static inline int rtl8169_fragmented_frame(u32 status)
4458 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4461 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4463 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4465 if (status == RxProtoTCP || status == RxProtoUDP)
4466 skb->ip_summed = CHECKSUM_UNNECESSARY;
4468 skb_checksum_none_assert(skb);
4471 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4473 struct device *d = tp_to_dev(tp);
4476 for (count = 0; count < budget; count++, tp->cur_rx++) {
4477 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4478 struct RxDesc *desc = tp->RxDescArray + entry;
4479 struct sk_buff *skb;
4484 status = le32_to_cpu(desc->opts1);
4485 if (status & DescOwn)
4488 /* This barrier is needed to keep us from reading
4489 * any other fields out of the Rx descriptor until
4490 * we know the status of DescOwn
4494 if (unlikely(status & RxRES)) {
4495 if (net_ratelimit())
4496 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4498 dev->stats.rx_errors++;
4499 if (status & (RxRWT | RxRUNT))
4500 dev->stats.rx_length_errors++;
4502 dev->stats.rx_crc_errors++;
4504 if (!(dev->features & NETIF_F_RXALL))
4505 goto release_descriptor;
4506 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4507 goto release_descriptor;
4510 pkt_size = status & GENMASK(13, 0);
4511 if (likely(!(dev->features & NETIF_F_RXFCS)))
4512 pkt_size -= ETH_FCS_LEN;
4514 /* The driver does not support incoming fragmented frames.
4515 * They are seen as a symptom of over-mtu sized frames.
4517 if (unlikely(rtl8169_fragmented_frame(status))) {
4518 dev->stats.rx_dropped++;
4519 dev->stats.rx_length_errors++;
4520 goto release_descriptor;
4523 skb = napi_alloc_skb(&tp->napi, pkt_size);
4524 if (unlikely(!skb)) {
4525 dev->stats.rx_dropped++;
4526 goto release_descriptor;
4529 addr = le64_to_cpu(desc->addr);
4530 rx_buf = page_address(tp->Rx_databuff[entry]);
4532 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4534 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4535 skb->tail += pkt_size;
4536 skb->len = pkt_size;
4537 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4539 rtl8169_rx_csum(skb, status);
4540 skb->protocol = eth_type_trans(skb, dev);
4542 rtl8169_rx_vlan_tag(desc, skb);
4544 if (skb->pkt_type == PACKET_MULTICAST)
4545 dev->stats.multicast++;
4547 napi_gro_receive(&tp->napi, skb);
4549 dev_sw_netstats_rx_add(dev, pkt_size);
4551 rtl8169_mark_to_asic(desc);
4557 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4559 struct rtl8169_private *tp = dev_instance;
4560 u32 status = rtl_get_events(tp);
4562 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4565 if (unlikely(status & SYSErr)) {
4566 rtl8169_pcierr_interrupt(tp->dev);
4570 if (status & LinkChg)
4571 phy_mac_interrupt(tp->phydev);
4573 if (unlikely(status & RxFIFOOver &&
4574 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4575 netif_stop_queue(tp->dev);
4576 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4579 if (napi_schedule_prep(&tp->napi)) {
4580 rtl_unlock_config_regs(tp);
4581 rtl_hw_aspm_clkreq_enable(tp, false);
4582 rtl_lock_config_regs(tp);
4584 rtl_irq_disable(tp);
4585 __napi_schedule(&tp->napi);
4588 rtl_ack_events(tp, status);
4593 static void rtl_task(struct work_struct *work)
4595 struct rtl8169_private *tp =
4596 container_of(work, struct rtl8169_private, wk.work);
4601 if (!netif_running(tp->dev) ||
4602 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4605 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4606 /* if chip isn't accessible, reset bus to revive it */
4607 if (RTL_R32(tp, TxConfig) == ~0) {
4608 ret = pci_reset_bus(tp->pci_dev);
4610 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4611 netif_device_detach(tp->dev);
4616 /* ASPM compatibility issues are a typical reason for tx timeouts */
4617 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4618 PCIE_LINK_STATE_L0S);
4620 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4624 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4627 netif_wake_queue(tp->dev);
4633 static int rtl8169_poll(struct napi_struct *napi, int budget)
4635 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4636 struct net_device *dev = tp->dev;
4639 rtl_tx(dev, tp, budget);
4641 work_done = rtl_rx(dev, tp, budget);
4643 if (work_done < budget && napi_complete_done(napi, work_done)) {
4646 rtl_unlock_config_regs(tp);
4647 rtl_hw_aspm_clkreq_enable(tp, true);
4648 rtl_lock_config_regs(tp);
4654 static void r8169_phylink_handler(struct net_device *ndev)
4656 struct rtl8169_private *tp = netdev_priv(ndev);
4657 struct device *d = tp_to_dev(tp);
4659 if (netif_carrier_ok(ndev)) {
4660 rtl_link_chg_patch(tp);
4661 pm_request_resume(d);
4666 phy_print_status(tp->phydev);
4669 static int r8169_phy_connect(struct rtl8169_private *tp)
4671 struct phy_device *phydev = tp->phydev;
4672 phy_interface_t phy_mode;
4675 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4676 PHY_INTERFACE_MODE_MII;
4678 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4683 if (!tp->supports_gmii)
4684 phy_set_max_speed(phydev, SPEED_100);
4686 phy_attached_info(phydev);
4691 static void rtl8169_down(struct rtl8169_private *tp)
4693 /* Clear all task flags */
4694 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4696 phy_stop(tp->phydev);
4698 rtl8169_update_counters(tp);
4700 pci_clear_master(tp->pci_dev);
4703 rtl8169_cleanup(tp);
4704 rtl_disable_exit_l1(tp);
4705 rtl_prepare_power_down(tp);
4708 static void rtl8169_up(struct rtl8169_private *tp)
4710 pci_set_master(tp->pci_dev);
4711 phy_init_hw(tp->phydev);
4712 phy_resume(tp->phydev);
4713 rtl8169_init_phy(tp);
4714 napi_enable(&tp->napi);
4715 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4718 phy_start(tp->phydev);
4721 static int rtl8169_close(struct net_device *dev)
4723 struct rtl8169_private *tp = netdev_priv(dev);
4724 struct pci_dev *pdev = tp->pci_dev;
4726 pm_runtime_get_sync(&pdev->dev);
4728 netif_stop_queue(dev);
4730 rtl8169_rx_clear(tp);
4732 cancel_work_sync(&tp->wk.work);
4734 free_irq(tp->irq, tp);
4736 phy_disconnect(tp->phydev);
4738 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4740 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4742 tp->TxDescArray = NULL;
4743 tp->RxDescArray = NULL;
4745 pm_runtime_put_sync(&pdev->dev);
4750 #ifdef CONFIG_NET_POLL_CONTROLLER
4751 static void rtl8169_netpoll(struct net_device *dev)
4753 struct rtl8169_private *tp = netdev_priv(dev);
4755 rtl8169_interrupt(tp->irq, tp);
4759 static int rtl_open(struct net_device *dev)
4761 struct rtl8169_private *tp = netdev_priv(dev);
4762 struct pci_dev *pdev = tp->pci_dev;
4763 unsigned long irqflags;
4764 int retval = -ENOMEM;
4766 pm_runtime_get_sync(&pdev->dev);
4769 * Rx and Tx descriptors needs 256 bytes alignment.
4770 * dma_alloc_coherent provides more.
4772 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4773 &tp->TxPhyAddr, GFP_KERNEL);
4774 if (!tp->TxDescArray)
4777 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4778 &tp->RxPhyAddr, GFP_KERNEL);
4779 if (!tp->RxDescArray)
4782 retval = rtl8169_init_ring(tp);
4786 rtl_request_firmware(tp);
4788 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4789 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4791 goto err_release_fw_2;
4793 retval = r8169_phy_connect(tp);
4798 rtl8169_init_counter_offsets(tp);
4799 netif_start_queue(dev);
4801 pm_runtime_put_sync(&pdev->dev);
4806 free_irq(tp->irq, tp);
4808 rtl_release_firmware(tp);
4809 rtl8169_rx_clear(tp);
4811 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4813 tp->RxDescArray = NULL;
4815 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4817 tp->TxDescArray = NULL;
4822 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4824 struct rtl8169_private *tp = netdev_priv(dev);
4825 struct pci_dev *pdev = tp->pci_dev;
4826 struct rtl8169_counters *counters = tp->counters;
4828 pm_runtime_get_noresume(&pdev->dev);
4830 netdev_stats_to_stats64(stats, &dev->stats);
4831 dev_fetch_sw_netstats(stats, dev->tstats);
4834 * Fetch additional counter values missing in stats collected by driver
4835 * from tally counters.
4837 if (pm_runtime_active(&pdev->dev))
4838 rtl8169_update_counters(tp);
4841 * Subtract values fetched during initalization.
4842 * See rtl8169_init_counter_offsets for a description why we do that.
4844 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4845 le64_to_cpu(tp->tc_offset.tx_errors);
4846 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4847 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4848 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4849 le16_to_cpu(tp->tc_offset.tx_aborted);
4850 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4851 le16_to_cpu(tp->tc_offset.rx_missed);
4853 pm_runtime_put_noidle(&pdev->dev);
4856 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4858 netif_device_detach(tp->dev);
4860 if (netif_running(tp->dev))
4864 static int rtl8169_runtime_resume(struct device *dev)
4866 struct rtl8169_private *tp = dev_get_drvdata(dev);
4868 rtl_rar_set(tp, tp->dev->dev_addr);
4869 __rtl8169_set_wol(tp, tp->saved_wolopts);
4871 if (tp->TxDescArray)
4874 netif_device_attach(tp->dev);
4879 static int rtl8169_suspend(struct device *device)
4881 struct rtl8169_private *tp = dev_get_drvdata(device);
4884 rtl8169_net_suspend(tp);
4885 if (!device_may_wakeup(tp_to_dev(tp)))
4886 clk_disable_unprepare(tp->clk);
4892 static int rtl8169_resume(struct device *device)
4894 struct rtl8169_private *tp = dev_get_drvdata(device);
4896 if (!device_may_wakeup(tp_to_dev(tp)))
4897 clk_prepare_enable(tp->clk);
4899 /* Reportedly at least Asus X453MA truncates packets otherwise */
4900 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4903 return rtl8169_runtime_resume(device);
4906 static int rtl8169_runtime_suspend(struct device *device)
4908 struct rtl8169_private *tp = dev_get_drvdata(device);
4910 if (!tp->TxDescArray) {
4911 netif_device_detach(tp->dev);
4916 __rtl8169_set_wol(tp, WAKE_PHY);
4917 rtl8169_net_suspend(tp);
4923 static int rtl8169_runtime_idle(struct device *device)
4925 struct rtl8169_private *tp = dev_get_drvdata(device);
4927 if (tp->dash_type != RTL_DASH_NONE)
4930 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4931 pm_schedule_suspend(device, 10000);
4936 static const struct dev_pm_ops rtl8169_pm_ops = {
4937 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4938 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4939 rtl8169_runtime_idle)
4942 static void rtl_shutdown(struct pci_dev *pdev)
4944 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4947 rtl8169_net_suspend(tp);
4950 /* Restore original MAC address */
4951 rtl_rar_set(tp, tp->dev->perm_addr);
4953 if (system_state == SYSTEM_POWER_OFF &&
4954 tp->dash_type == RTL_DASH_NONE) {
4955 pci_wake_from_d3(pdev, tp->saved_wolopts);
4956 pci_set_power_state(pdev, PCI_D3hot);
4960 static void rtl_remove_one(struct pci_dev *pdev)
4962 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4964 if (pci_dev_run_wake(pdev))
4965 pm_runtime_get_noresume(&pdev->dev);
4967 unregister_netdev(tp->dev);
4969 if (tp->dash_type != RTL_DASH_NONE)
4970 rtl8168_driver_stop(tp);
4972 rtl_release_firmware(tp);
4974 /* restore original MAC address */
4975 rtl_rar_set(tp, tp->dev->perm_addr);
4978 static const struct net_device_ops rtl_netdev_ops = {
4979 .ndo_open = rtl_open,
4980 .ndo_stop = rtl8169_close,
4981 .ndo_get_stats64 = rtl8169_get_stats64,
4982 .ndo_start_xmit = rtl8169_start_xmit,
4983 .ndo_features_check = rtl8169_features_check,
4984 .ndo_tx_timeout = rtl8169_tx_timeout,
4985 .ndo_validate_addr = eth_validate_addr,
4986 .ndo_change_mtu = rtl8169_change_mtu,
4987 .ndo_fix_features = rtl8169_fix_features,
4988 .ndo_set_features = rtl8169_set_features,
4989 .ndo_set_mac_address = rtl_set_mac_address,
4990 .ndo_eth_ioctl = phy_do_ioctl_running,
4991 .ndo_set_rx_mode = rtl_set_rx_mode,
4992 #ifdef CONFIG_NET_POLL_CONTROLLER
4993 .ndo_poll_controller = rtl8169_netpoll,
4998 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5000 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5002 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5003 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5004 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5005 /* special workaround needed */
5006 tp->irq_mask |= RxFIFOOver;
5008 tp->irq_mask |= RxOverflow;
5011 static int rtl_alloc_irq(struct rtl8169_private *tp)
5015 switch (tp->mac_version) {
5016 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5017 rtl_unlock_config_regs(tp);
5018 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5019 rtl_lock_config_regs(tp);
5021 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5022 flags = PCI_IRQ_LEGACY;
5025 flags = PCI_IRQ_ALL_TYPES;
5029 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5032 static void rtl_read_mac_address(struct rtl8169_private *tp,
5033 u8 mac_addr[ETH_ALEN])
5035 /* Get MAC address */
5036 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5039 value = rtl_eri_read(tp, 0xe0);
5040 put_unaligned_le32(value, mac_addr);
5041 value = rtl_eri_read(tp, 0xe4);
5042 put_unaligned_le16(value, mac_addr + 4);
5043 } else if (rtl_is_8125(tp)) {
5044 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5048 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5050 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5053 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5055 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5058 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5060 struct rtl8169_private *tp = mii_bus->priv;
5065 return rtl_readphy(tp, phyreg);
5068 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5069 int phyreg, u16 val)
5071 struct rtl8169_private *tp = mii_bus->priv;
5076 rtl_writephy(tp, phyreg, val);
5081 static int r8169_mdio_register(struct rtl8169_private *tp)
5083 struct pci_dev *pdev = tp->pci_dev;
5084 struct mii_bus *new_bus;
5087 new_bus = devm_mdiobus_alloc(&pdev->dev);
5091 new_bus->name = "r8169";
5093 new_bus->parent = &pdev->dev;
5094 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5095 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5096 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5098 new_bus->read = r8169_mdio_read_reg;
5099 new_bus->write = r8169_mdio_write_reg;
5101 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5105 tp->phydev = mdiobus_get_phy(new_bus, 0);
5108 } else if (!tp->phydev->drv) {
5109 /* Most chip versions fail with the genphy driver.
5110 * Therefore ensure that the dedicated PHY driver is loaded.
5112 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5113 tp->phydev->phy_id);
5117 tp->phydev->mac_managed_pm = true;
5119 phy_support_asym_pause(tp->phydev);
5121 /* PHY will be woken up in rtl_open() */
5122 phy_suspend(tp->phydev);
5127 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5129 rtl_enable_rxdvgate(tp);
5131 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5133 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5135 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5136 r8168g_wait_ll_share_fifo_ready(tp);
5138 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5139 r8168g_wait_ll_share_fifo_ready(tp);
5142 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5144 rtl_enable_rxdvgate(tp);
5146 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5148 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5150 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5151 r8168g_wait_ll_share_fifo_ready(tp);
5153 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5154 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5155 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5156 r8168g_wait_ll_share_fifo_ready(tp);
5159 static void rtl_hw_initialize(struct rtl8169_private *tp)
5161 switch (tp->mac_version) {
5162 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5163 rtl8168ep_stop_cmac(tp);
5165 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5166 rtl_hw_init_8168g(tp);
5168 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
5169 rtl_hw_init_8125(tp);
5176 static int rtl_jumbo_max(struct rtl8169_private *tp)
5178 /* Non-GBit versions don't support jumbo frames */
5179 if (!tp->supports_gmii)
5182 switch (tp->mac_version) {
5184 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5187 case RTL_GIGA_MAC_VER_11:
5188 case RTL_GIGA_MAC_VER_17:
5191 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5198 static void rtl_init_mac_address(struct rtl8169_private *tp)
5200 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5201 struct net_device *dev = tp->dev;
5204 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5208 rtl_read_mac_address(tp, mac_addr);
5209 if (is_valid_ether_addr(mac_addr))
5212 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5213 if (is_valid_ether_addr(mac_addr))
5216 eth_random_addr(mac_addr);
5217 dev->addr_assign_type = NET_ADDR_RANDOM;
5218 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5220 eth_hw_addr_set(dev, mac_addr);
5221 rtl_rar_set(tp, mac_addr);
5224 /* register is set if system vendor successfully tested ASPM 1.2 */
5225 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5227 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5228 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5234 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5236 struct rtl8169_private *tp;
5237 int jumbo_max, region, rc;
5238 enum mac_version chipset;
5239 struct net_device *dev;
5242 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5246 SET_NETDEV_DEV(dev, &pdev->dev);
5247 dev->netdev_ops = &rtl_netdev_ops;
5248 tp = netdev_priv(dev);
5251 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5253 tp->ocp_base = OCP_STD_PHY_BASE;
5255 spin_lock_init(&tp->cfg9346_usage_lock);
5256 spin_lock_init(&tp->config25_lock);
5257 spin_lock_init(&tp->mac_ocp_lock);
5259 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5260 struct pcpu_sw_netstats);
5264 /* Get the *optional* external "ether_clk" used on some boards */
5265 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5266 if (IS_ERR(tp->clk))
5267 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5269 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5270 rc = pcim_enable_device(pdev);
5272 dev_err(&pdev->dev, "enable failure\n");
5276 if (pcim_set_mwi(pdev) < 0)
5277 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5279 /* use first MMIO region */
5280 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5282 dev_err(&pdev->dev, "no MMIO resource found\n");
5286 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5288 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5292 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5294 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5296 /* Identify chip attached to board */
5297 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5298 if (chipset == RTL_GIGA_MAC_NONE) {
5299 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5303 tp->mac_version = chipset;
5305 /* Disable ASPM L1 as that cause random device stop working
5306 * problems as well as full system hangs for some PCIe devices users.
5307 * Chips from RTL8168h partially have issues with L1.2, but seem
5308 * to work fine with L1 and L1.1.
5310 if (rtl_aspm_is_safe(tp))
5312 else if (tp->mac_version >= RTL_GIGA_MAC_VER_46)
5313 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
5315 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5316 tp->aspm_manageable = !rc;
5318 tp->dash_type = rtl_check_dash(tp);
5320 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5322 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5323 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5324 dev->features |= NETIF_F_HIGHDMA;
5328 rtl8169_irq_mask_and_ack(tp);
5330 rtl_hw_initialize(tp);
5334 rc = rtl_alloc_irq(tp);
5336 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5339 tp->irq = pci_irq_vector(pdev, 0);
5341 INIT_WORK(&tp->wk.work, rtl_task);
5343 rtl_init_mac_address(tp);
5345 dev->ethtool_ops = &rtl8169_ethtool_ops;
5347 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5349 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5350 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5351 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5352 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5355 * Pretend we are using VLANs; This bypasses a nasty bug where
5356 * Interrupts stop flowing on high load on 8110SCd controllers.
5358 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5359 /* Disallow toggling */
5360 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5362 if (rtl_chip_supports_csum_v2(tp))
5363 dev->hw_features |= NETIF_F_IPV6_CSUM;
5365 dev->features |= dev->hw_features;
5367 /* There has been a number of reports that using SG/TSO results in
5368 * tx timeouts. However for a lot of people SG/TSO works fine.
5369 * Therefore disable both features by default, but allow users to
5370 * enable them. Use at own risk!
5372 if (rtl_chip_supports_csum_v2(tp)) {
5373 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5374 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5375 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5377 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5378 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5379 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5382 dev->hw_features |= NETIF_F_RXALL;
5383 dev->hw_features |= NETIF_F_RXFCS;
5385 netdev_sw_irq_coalesce_default_on(dev);
5387 /* configure chip for default features */
5388 rtl8169_set_features(dev, dev->features);
5390 if (tp->dash_type == RTL_DASH_NONE) {
5391 rtl_set_d3_pll_down(tp, true);
5393 rtl_set_d3_pll_down(tp, false);
5394 dev->wol_enabled = 1;
5397 jumbo_max = rtl_jumbo_max(tp);
5399 dev->max_mtu = jumbo_max;
5401 rtl_set_irq_mask(tp);
5403 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5405 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5406 &tp->counters_phys_addr,
5411 pci_set_drvdata(pdev, tp);
5413 rc = r8169_mdio_register(tp);
5417 rc = register_netdev(dev);
5421 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5422 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5425 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5426 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5429 if (tp->dash_type != RTL_DASH_NONE) {
5430 netdev_info(dev, "DASH enabled\n");
5431 rtl8168_driver_start(tp);
5434 if (pci_dev_run_wake(pdev))
5435 pm_runtime_put_sync(&pdev->dev);
5440 static struct pci_driver rtl8169_pci_driver = {
5441 .name = KBUILD_MODNAME,
5442 .id_table = rtl8169_pci_tbl,
5443 .probe = rtl_init_one,
5444 .remove = rtl_remove_one,
5445 .shutdown = rtl_shutdown,
5446 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5449 module_pci_driver(rtl8169_pci_driver);