drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/in.h>
  22 #include <linux/io.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/bitfield.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include "r8169.h"
  34 #include "r8169_firmware.h"
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  59 #define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 #define MC_FILTER_LIMIT 32
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 #define OCP_STD_PHY_BASE        0xa400
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 #define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88 #define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89 #define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90 #define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92 static const struct {
  93         const char *name;
  94         const char *fw_name;
  95 } rtl_chip_infos[] = {
  96         /* PCI devices. */
  97         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102         /* PCI-E devices. */
 103         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 107         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 109         [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 110         [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 111         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 112         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 113         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 114         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 115         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 116         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 117         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 118         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 119         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 120         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 121         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 122         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 123         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 124         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 125         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 126         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 127         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 128         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 129         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 130         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 131         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 132         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 133         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 134         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 135         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 136         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 137         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 138         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 139         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 140         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 141         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 142         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 143         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 144         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 145         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 146         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 147         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 148         [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 149         [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 150         /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 151         [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 152 };
 153
 154 static const struct pci_device_id rtl8169_pci_tbl[] = {
 155         { PCI_VDEVICE(REALTEK,  0x2502) },
 156         { PCI_VDEVICE(REALTEK,  0x2600) },
 157         { PCI_VDEVICE(REALTEK,  0x8129) },
 158         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 159         { PCI_VDEVICE(REALTEK,  0x8161) },
 160         { PCI_VDEVICE(REALTEK,  0x8167) },
 161         { PCI_VDEVICE(REALTEK,  0x8168) },
 162         { PCI_VDEVICE(NCUBE,    0x8168) },
 163         { PCI_VDEVICE(REALTEK,  0x8169) },
 164         { PCI_VENDOR_ID_DLINK,  0x4300,
 165                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 166         { PCI_VDEVICE(DLINK,    0x4300) },
 167         { PCI_VDEVICE(DLINK,    0x4302) },
 168         { PCI_VDEVICE(AT,       0xc107) },
 169         { PCI_VDEVICE(USR,      0x0116) },
 170         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 171         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 172         { PCI_VDEVICE(REALTEK,  0x8125) },
 173         { PCI_VDEVICE(REALTEK,  0x3000) },
 174         {}
 175 };
 176
 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 178
 179 enum rtl_registers {
 180         MAC0            = 0,    /* Ethernet hardware address. */
 181         MAC4            = 4,
 182         MAR0            = 8,    /* Multicast filter. */
 183         CounterAddrLow          = 0x10,
 184         CounterAddrHigh         = 0x14,
 185         TxDescStartAddrLow      = 0x20,
 186         TxDescStartAddrHigh     = 0x24,
 187         TxHDescStartAddrLow     = 0x28,
 188         TxHDescStartAddrHigh    = 0x2c,
 189         FLASH           = 0x30,
 190         ERSR            = 0x36,
 191         ChipCmd         = 0x37,
 192         TxPoll          = 0x38,
 193         IntrMask        = 0x3c,
 194         IntrStatus      = 0x3e,
 195
 196         TxConfig        = 0x40,
 197 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 198 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 199
 200         RxConfig        = 0x44,
 201 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 202 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 203 #define RXCFG_FIFO_SHIFT                13
 204                                         /* No threshold before first PCI xfer */
 205 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 206 #define RX_EARLY_OFF                    (1 << 11)
 207 #define RXCFG_DMA_SHIFT                 8
 208                                         /* Unlimited maximum PCI burst. */
 209 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 210
 211         Cfg9346         = 0x50,
 212         Config0         = 0x51,
 213         Config1         = 0x52,
 214         Config2         = 0x53,
 215 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 216
 217         Config3         = 0x54,
 218         Config4         = 0x55,
 219         Config5         = 0x56,
 220         PHYAR           = 0x60,
 221         PHYstatus       = 0x6c,
 222         RxMaxSize       = 0xda,
 223         CPlusCmd        = 0xe0,
 224         IntrMitigate    = 0xe2,
 225
 226 #define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 227 #define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 228 #define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 229 #define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 230
 231 #define RTL_COALESCE_T_MAX      0x0fU
 232 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 233
 234         RxDescAddrLow   = 0xe4,
 235         RxDescAddrHigh  = 0xe8,
 236         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 237
 238 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 239
 240         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 241
 242 #define TxPacketMax     (8064 >> 7)
 243 #define EarlySize       0x27
 244
 245         FuncEvent       = 0xf0,
 246         FuncEventMask   = 0xf4,
 247         FuncPresetState = 0xf8,
 248         IBCR0           = 0xf8,
 249         IBCR2           = 0xf9,
 250         IBIMR0          = 0xfa,
 251         IBISR0          = 0xfb,
 252         FuncForceEvent  = 0xfc,
 253 };
 254
 255 enum rtl8168_8101_registers {
 256         CSIDR                   = 0x64,
 257         CSIAR                   = 0x68,
 258 #define CSIAR_FLAG                      0x80000000
 259 #define CSIAR_WRITE_CMD                 0x80000000
 260 #define CSIAR_BYTE_ENABLE               0x0000f000
 261 #define CSIAR_ADDR_MASK                 0x00000fff
 262         PMCH                    = 0x6f,
 263         EPHYAR                  = 0x80,
 264 #define EPHYAR_FLAG                     0x80000000
 265 #define EPHYAR_WRITE_CMD                0x80000000
 266 #define EPHYAR_REG_MASK                 0x1f
 267 #define EPHYAR_REG_SHIFT                16
 268 #define EPHYAR_DATA_MASK                0xffff
 269         DLLPR                   = 0xd0,
 270 #define PFM_EN                          (1 << 6)
 271 #define TX_10M_PS_EN                    (1 << 7)
 272         DBG_REG                 = 0xd1,
 273 #define FIX_NAK_1                       (1 << 4)
 274 #define FIX_NAK_2                       (1 << 3)
 275         TWSI                    = 0xd2,
 276         MCU                     = 0xd3,
 277 #define NOW_IS_OOB                      (1 << 7)
 278 #define TX_EMPTY                        (1 << 5)
 279 #define RX_EMPTY                        (1 << 4)
 280 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 281 #define EN_NDP                          (1 << 3)
 282 #define EN_OOB_RESET                    (1 << 2)
 283 #define LINK_LIST_RDY                   (1 << 1)
 284         EFUSEAR                 = 0xdc,
 285 #define EFUSEAR_FLAG                    0x80000000
 286 #define EFUSEAR_WRITE_CMD               0x80000000
 287 #define EFUSEAR_READ_CMD                0x00000000
 288 #define EFUSEAR_REG_MASK                0x03ff
 289 #define EFUSEAR_REG_SHIFT               8
 290 #define EFUSEAR_DATA_MASK               0xff
 291         MISC_1                  = 0xf2,
 292 #define PFM_D3COLD_EN                   (1 << 6)
 293 };
 294
 295 enum rtl8168_registers {
 296         LED_FREQ                = 0x1a,
 297         EEE_LED                 = 0x1b,
 298         ERIDR                   = 0x70,
 299         ERIAR                   = 0x74,
 300 #define ERIAR_FLAG                      0x80000000
 301 #define ERIAR_WRITE_CMD                 0x80000000
 302 #define ERIAR_READ_CMD                  0x00000000
 303 #define ERIAR_ADDR_BYTE_ALIGN           4
 304 #define ERIAR_TYPE_SHIFT                16
 305 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 306 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 307 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 308 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 309 #define ERIAR_MASK_SHIFT                12
 310 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 311 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 312 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 313 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 314 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 315         EPHY_RXER_NUM           = 0x7c,
 316         OCPDR                   = 0xb0, /* OCP GPHY access */
 317 #define OCPDR_WRITE_CMD                 0x80000000
 318 #define OCPDR_READ_CMD                  0x00000000
 319 #define OCPDR_REG_MASK                  0x7f
 320 #define OCPDR_GPHY_REG_SHIFT            16
 321 #define OCPDR_DATA_MASK                 0xffff
 322         OCPAR                   = 0xb4,
 323 #define OCPAR_FLAG                      0x80000000
 324 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 325 #define OCPAR_GPHY_READ_CMD             0x0000f060
 326         GPHY_OCP                = 0xb8,
 327         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 328         MISC                    = 0xf0, /* 8168e only. */
 329 #define TXPLA_RST                       (1 << 29)
 330 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 331 #define PWM_EN                          (1 << 22)
 332 #define RXDV_GATED_EN                   (1 << 19)
 333 #define EARLY_TALLY_EN                  (1 << 16)
 334 };
 335
 336 enum rtl8125_registers {
 337         IntrMask_8125           = 0x38,
 338         IntrStatus_8125         = 0x3c,
 339         TxPoll_8125             = 0x90,
 340         MAC0_BKP                = 0x19e0,
 341         EEE_TXIDLE_TIMER_8125   = 0x6048,
 342 };
 343
 344 #define RX_VLAN_INNER_8125      BIT(22)
 345 #define RX_VLAN_OUTER_8125      BIT(23)
 346 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 347
 348 #define RX_FETCH_DFLT_8125      (8 << 27)
 349
 350 enum rtl_register_content {
 351         /* InterruptStatusBits */
 352         SYSErr          = 0x8000,
 353         PCSTimeout      = 0x4000,
 354         SWInt           = 0x0100,
 355         TxDescUnavail   = 0x0080,
 356         RxFIFOOver      = 0x0040,
 357         LinkChg         = 0x0020,
 358         RxOverflow      = 0x0010,
 359         TxErr           = 0x0008,
 360         TxOK            = 0x0004,
 361         RxErr           = 0x0002,
 362         RxOK            = 0x0001,
 363
 364         /* RxStatusDesc */
 365         RxRWT   = (1 << 22),
 366         RxRES   = (1 << 21),
 367         RxRUNT  = (1 << 20),
 368         RxCRC   = (1 << 19),
 369
 370         /* ChipCmdBits */
 371         StopReq         = 0x80,
 372         CmdReset        = 0x10,
 373         CmdRxEnb        = 0x08,
 374         CmdTxEnb        = 0x04,
 375         RxBufEmpty      = 0x01,
 376
 377         /* TXPoll register p.5 */
 378         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 379         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 380         FSWInt          = 0x01,         /* Forced software interrupt */
 381
 382         /* Cfg9346Bits */
 383         Cfg9346_Lock    = 0x00,
 384         Cfg9346_Unlock  = 0xc0,
 385
 386         /* rx_mode_bits */
 387         AcceptErr       = 0x20,
 388         AcceptRunt      = 0x10,
 389 #define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 390         AcceptBroadcast = 0x08,
 391         AcceptMulticast = 0x04,
 392         AcceptMyPhys    = 0x02,
 393         AcceptAllPhys   = 0x01,
 394 #define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 395 #define RX_CONFIG_ACCEPT_MASK           0x3f
 396
 397         /* TxConfigBits */
 398         TxInterFrameGapShift = 24,
 399         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 400
 401         /* Config1 register p.24 */
 402         LEDS1           = (1 << 7),
 403         LEDS0           = (1 << 6),
 404         Speed_down      = (1 << 4),
 405         MEMMAP          = (1 << 3),
 406         IOMAP           = (1 << 2),
 407         VPD             = (1 << 1),
 408         PMEnable        = (1 << 0),     /* Power Management Enable */
 409
 410         /* Config2 register p. 25 */
 411         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 412         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 413         PCI_Clock_66MHz = 0x01,
 414         PCI_Clock_33MHz = 0x00,
 415
 416         /* Config3 register p.25 */
 417         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 418         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 419         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 420         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 421         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 422
 423         /* Config4 register */
 424         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 425
 426         /* Config5 register p.27 */
 427         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 428         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 429         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 430         Spi_en          = (1 << 3),
 431         LanWake         = (1 << 1),     /* LanWake enable/disable */
 432         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 433         ASPM_en         = (1 << 0),     /* ASPM enable */
 434
 435         /* CPlusCmd p.31 */
 436         EnableBist      = (1 << 15),    // 8168 8101
 437         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 438         EnAnaPLL        = (1 << 14),    // 8169
 439         Normal_mode     = (1 << 13),    // unused
 440         Force_half_dup  = (1 << 12),    // 8168 8101
 441         Force_rxflow_en = (1 << 11),    // 8168 8101
 442         Force_txflow_en = (1 << 10),    // 8168 8101
 443         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 444         ASF             = (1 << 8),     // 8168 8101
 445         PktCntrDisable  = (1 << 7),     // 8168 8101
 446         Mac_dbgo_sel    = 0x001c,       // 8168
 447         RxVlan          = (1 << 6),
 448         RxChkSum        = (1 << 5),
 449         PCIDAC          = (1 << 4),
 450         PCIMulRW        = (1 << 3),
 451 #define INTT_MASK       GENMASK(1, 0)
 452 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 453
 454         /* rtl8169_PHYstatus */
 455         TBI_Enable      = 0x80,
 456         TxFlowCtrl      = 0x40,
 457         RxFlowCtrl      = 0x20,
 458         _1000bpsF       = 0x10,
 459         _100bps         = 0x08,
 460         _10bps          = 0x04,
 461         LinkStatus      = 0x02,
 462         FullDup         = 0x01,
 463
 464         /* ResetCounterCommand */
 465         CounterReset    = 0x1,
 466
 467         /* DumpCounterCommand */
 468         CounterDump     = 0x8,
 469
 470         /* magic enable v2 */
 471         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 472 };
 473
 474 enum rtl_desc_bit {
 475         /* First doubleword. */
 476         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 477         RingEnd         = (1 << 30), /* End of descriptor ring */
 478         FirstFrag       = (1 << 29), /* First segment of a packet */
 479         LastFrag        = (1 << 28), /* Final segment of a packet */
 480 };
 481
 482 /* Generic case. */
 483 enum rtl_tx_desc_bit {
 484         /* First doubleword. */
 485         TD_LSO          = (1 << 27),            /* Large Send Offload */
 486 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 487
 488         /* Second doubleword. */
 489         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 490 };
 491
 492 /* 8169, 8168b and 810x except 8102e. */
 493 enum rtl_tx_desc_bit_0 {
 494         /* First doubleword. */
 495 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 496         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 497         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 498         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 499 };
 500
 501 /* 8102e, 8168c and beyond. */
 502 enum rtl_tx_desc_bit_1 {
 503         /* First doubleword. */
 504         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 505         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 506 #define GTTCPHO_SHIFT                   18
 507 #define GTTCPHO_MAX                     0x7f
 508
 509         /* Second doubleword. */
 510 #define TCPHO_SHIFT                     18
 511 #define TCPHO_MAX                       0x3ff
 512 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 513         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 514         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 515         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 516         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 517 };
 518
 519 enum rtl_rx_desc_bit {
 520         /* Rx private */
 521         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 522         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 523
 524 #define RxProtoUDP      (PID1)
 525 #define RxProtoTCP      (PID0)
 526 #define RxProtoIP       (PID1 | PID0)
 527 #define RxProtoMask     RxProtoIP
 528
 529         IPFail          = (1 << 16), /* IP checksum failed */
 530         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 531         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 532         RxVlanTag       = (1 << 16), /* VLAN tag available */
 533 };
 534
 535 #define RTL_GSO_MAX_SIZE_V1     32000
 536 #define RTL_GSO_MAX_SEGS_V1     24
 537 #define RTL_GSO_MAX_SIZE_V2     64000
 538 #define RTL_GSO_MAX_SEGS_V2     64
 539
 540 struct TxDesc {
 541         __le32 opts1;
 542         __le32 opts2;
 543         __le64 addr;
 544 };
 545
 546 struct RxDesc {
 547         __le32 opts1;
 548         __le32 opts2;
 549         __le64 addr;
 550 };
 551
 552 struct ring_info {
 553         struct sk_buff  *skb;
 554         u32             len;
 555 };
 556
 557 struct rtl8169_counters {
 558         __le64  tx_packets;
 559         __le64  rx_packets;
 560         __le64  tx_errors;
 561         __le32  rx_errors;
 562         __le16  rx_missed;
 563         __le16  align_errors;
 564         __le32  tx_one_collision;
 565         __le32  tx_multi_collision;
 566         __le64  rx_unicast;
 567         __le64  rx_broadcast;
 568         __le32  rx_multicast;
 569         __le16  tx_aborted;
 570         __le16  tx_underun;
 571 };
 572
 573 struct rtl8169_tc_offsets {
 574         bool    inited;
 575         __le64  tx_errors;
 576         __le32  tx_multi_collision;
 577         __le16  tx_aborted;
 578         __le16  rx_missed;
 579 };
 580
 581 enum rtl_flag {
 582         RTL_FLAG_TASK_ENABLED = 0,
 583         RTL_FLAG_TASK_RESET_PENDING,
 584         RTL_FLAG_MAX
 585 };
 586
 587 struct rtl8169_stats {
 588         u64                     packets;
 589         u64                     bytes;
 590         struct u64_stats_sync   syncp;
 591 };
 592
 593 struct rtl8169_private {
 594         void __iomem *mmio_addr;        /* memory map physical address */
 595         struct pci_dev *pci_dev;
 596         struct net_device *dev;
 597         struct phy_device *phydev;
 598         struct napi_struct napi;
 599         enum mac_version mac_version;
 600         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 601         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 602         u32 dirty_tx;
 603         struct rtl8169_stats rx_stats;
 604         struct rtl8169_stats tx_stats;
 605         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 606         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 607         dma_addr_t TxPhyAddr;
 608         dma_addr_t RxPhyAddr;
 609         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 610         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 611         u16 cp_cmd;
 612         u32 irq_mask;
 613         struct clk *clk;
 614
 615         struct {
 616                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 617                 struct work_struct work;
 618         } wk;
 619
 620         unsigned supports_gmii:1;
 621         unsigned aspm_manageable:1;
 622         dma_addr_t counters_phys_addr;
 623         struct rtl8169_counters *counters;
 624         struct rtl8169_tc_offsets tc_offset;
 625         u32 saved_wolopts;
 626         int eee_adv;
 627
 628         const char *fw_name;
 629         struct rtl_fw *rtl_fw;
 630
 631         u32 ocp_base;
 632 };
 633
 634 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 635
 636 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 637 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 638 MODULE_SOFTDEP("pre: realtek");
 639 MODULE_LICENSE("GPL");
 640 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 641 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 642 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 643 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 644 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 645 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 646 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 647 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 648 MODULE_FIRMWARE(FIRMWARE_8402_1);
 649 MODULE_FIRMWARE(FIRMWARE_8411_1);
 650 MODULE_FIRMWARE(FIRMWARE_8411_2);
 651 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 652 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 653 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 654 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 655 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 656 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 657 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 658 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 659 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 660 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 661 MODULE_FIRMWARE(FIRMWARE_8125B_2);
 662
 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 664 {
 665         return &tp->pci_dev->dev;
 666 }
 667
 668 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 669 {
 670         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 671 }
 672
 673 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 674 {
 675         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 676 }
 677
 678 static void rtl_pci_commit(struct rtl8169_private *tp)
 679 {
 680         /* Read an arbitrary register to commit a preceding PCI write */
 681         RTL_R8(tp, ChipCmd);
 682 }
 683
 684 static bool rtl_is_8125(struct rtl8169_private *tp)
 685 {
 686         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 687 }
 688
 689 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 690 {
 691         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 692                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 693                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 694 }
 695
 696 static bool rtl_supports_eee(struct rtl8169_private *tp)
 697 {
 698         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 699                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 700                tp->mac_version != RTL_GIGA_MAC_VER_39;
 701 }
 702
 703 static void rtl_get_priv_stats(struct rtl8169_stats *stats,
 704                                u64 *pkts, u64 *bytes)
 705 {
 706         unsigned int start;
 707
 708         do {
 709                 start = u64_stats_fetch_begin_irq(&stats->syncp);
 710                 *pkts = stats->packets;
 711                 *bytes = stats->bytes;
 712         } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
 713 }
 714
 715 static void rtl_inc_priv_stats(struct rtl8169_stats *stats,
 716                                u64 pkts, u64 bytes)
 717 {
 718         u64_stats_update_begin(&stats->syncp);
 719         stats->packets += pkts;
 720         stats->bytes += bytes;
 721         u64_stats_update_end(&stats->syncp);
 722 }
 723
 724 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 725 {
 726         int i;
 727
 728         for (i = 0; i < ETH_ALEN; i++)
 729                 mac[i] = RTL_R8(tp, reg + i);
 730 }
 731
 732 struct rtl_cond {
 733         bool (*check)(struct rtl8169_private *);
 734         const char *msg;
 735 };
 736
 737 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 738                           unsigned long usecs, int n, bool high)
 739 {
 740         int i;
 741
 742         for (i = 0; i < n; i++) {
 743                 if (c->check(tp) == high)
 744                         return true;
 745                 fsleep(usecs);
 746         }
 747
 748         if (net_ratelimit())
 749                 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 750                            c->msg, !high, n, usecs);
 751         return false;
 752 }
 753
 754 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 755                                const struct rtl_cond *c,
 756                                unsigned long d, int n)
 757 {
 758         return rtl_loop_wait(tp, c, d, n, true);
 759 }
 760
 761 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 762                               const struct rtl_cond *c,
 763                               unsigned long d, int n)
 764 {
 765         return rtl_loop_wait(tp, c, d, n, false);
 766 }
 767
 768 #define DECLARE_RTL_COND(name)                          \
 769 static bool name ## _check(struct rtl8169_private *);   \
 770                                                         \
 771 static const struct rtl_cond name = {                   \
 772         .check  = name ## _check,                       \
 773         .msg    = #name                                 \
 774 };                                                      \
 775                                                         \
 776 static bool name ## _check(struct rtl8169_private *tp)
 777
 778 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 779 {
 780         if (reg & 0xffff0001) {
 781                 if (net_ratelimit())
 782                         netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
 783                 return true;
 784         }
 785         return false;
 786 }
 787
 788 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 789 {
 790         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 791 }
 792
 793 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 794 {
 795         if (rtl_ocp_reg_failure(tp, reg))
 796                 return;
 797
 798         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 799
 800         rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 801 }
 802
 803 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 804 {
 805         if (rtl_ocp_reg_failure(tp, reg))
 806                 return 0;
 807
 808         RTL_W32(tp, GPHY_OCP, reg << 15);
 809
 810         return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 811                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 812 }
 813
 814 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 815 {
 816         if (rtl_ocp_reg_failure(tp, reg))
 817                 return;
 818
 819         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 820 }
 821
 822 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 823 {
 824         if (rtl_ocp_reg_failure(tp, reg))
 825                 return 0;
 826
 827         RTL_W32(tp, OCPDR, reg << 15);
 828
 829         return RTL_R32(tp, OCPDR);
 830 }
 831
 832 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 833                                  u16 set)
 834 {
 835         u16 data = r8168_mac_ocp_read(tp, reg);
 836
 837         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 838 }
 839
 840 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 841 {
 842         if (reg == 0x1f) {
 843                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 844                 return;
 845         }
 846
 847         if (tp->ocp_base != OCP_STD_PHY_BASE)
 848                 reg -= 0x10;
 849
 850         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 851 }
 852
 853 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 854 {
 855         if (reg == 0x1f)
 856                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 857
 858         if (tp->ocp_base != OCP_STD_PHY_BASE)
 859                 reg -= 0x10;
 860
 861         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 862 }
 863
 864 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 865 {
 866         if (reg == 0x1f) {
 867                 tp->ocp_base = value << 4;
 868                 return;
 869         }
 870
 871         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 872 }
 873
 874 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 875 {
 876         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 877 }
 878
 879 DECLARE_RTL_COND(rtl_phyar_cond)
 880 {
 881         return RTL_R32(tp, PHYAR) & 0x80000000;
 882 }
 883
 884 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 885 {
 886         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 887
 888         rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 889         /*
 890          * According to hardware specs a 20us delay is required after write
 891          * complete indication, but before sending next command.
 892          */
 893         udelay(20);
 894 }
 895
 896 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 897 {
 898         int value;
 899
 900         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 901
 902         value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 903                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 904
 905         /*
 906          * According to hardware specs a 20us delay is required after read
 907          * complete indication, but before sending next command.
 908          */
 909         udelay(20);
 910
 911         return value;
 912 }
 913
 914 DECLARE_RTL_COND(rtl_ocpar_cond)
 915 {
 916         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 917 }
 918
 919 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 920 {
 921         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 922         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 923         RTL_W32(tp, EPHY_RXER_NUM, 0);
 924
 925         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 926 }
 927
 928 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 929 {
 930         r8168dp_1_mdio_access(tp, reg,
 931                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 932 }
 933
 934 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 935 {
 936         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 937
 938         mdelay(1);
 939         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 940         RTL_W32(tp, EPHY_RXER_NUM, 0);
 941
 942         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 943                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 944 }
 945
 946 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 947
 948 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 949 {
 950         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 951 }
 952
 953 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 954 {
 955         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 956 }
 957
 958 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 959 {
 960         r8168dp_2_mdio_start(tp);
 961
 962         r8169_mdio_write(tp, reg, value);
 963
 964         r8168dp_2_mdio_stop(tp);
 965 }
 966
 967 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 968 {
 969         int value;
 970
 971         /* Work around issue with chip reporting wrong PHY ID */
 972         if (reg == MII_PHYSID2)
 973                 return 0xc912;
 974
 975         r8168dp_2_mdio_start(tp);
 976
 977         value = r8169_mdio_read(tp, reg);
 978
 979         r8168dp_2_mdio_stop(tp);
 980
 981         return value;
 982 }
 983
 984 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 985 {
 986         switch (tp->mac_version) {
 987         case RTL_GIGA_MAC_VER_27:
 988                 r8168dp_1_mdio_write(tp, location, val);
 989                 break;
 990         case RTL_GIGA_MAC_VER_28:
 991         case RTL_GIGA_MAC_VER_31:
 992                 r8168dp_2_mdio_write(tp, location, val);
 993                 break;
 994         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 995                 r8168g_mdio_write(tp, location, val);
 996                 break;
 997         default:
 998                 r8169_mdio_write(tp, location, val);
 999                 break;
1000         }
1001 }
1002
1003 static int rtl_readphy(struct rtl8169_private *tp, int location)
1004 {
1005         switch (tp->mac_version) {
1006         case RTL_GIGA_MAC_VER_27:
1007                 return r8168dp_1_mdio_read(tp, location);
1008         case RTL_GIGA_MAC_VER_28:
1009         case RTL_GIGA_MAC_VER_31:
1010                 return r8168dp_2_mdio_read(tp, location);
1011         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1012                 return r8168g_mdio_read(tp, location);
1013         default:
1014                 return r8169_mdio_read(tp, location);
1015         }
1016 }
1017
1018 DECLARE_RTL_COND(rtl_ephyar_cond)
1019 {
1020         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1021 }
1022
1023 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1024 {
1025         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1026                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1027
1028         rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1029
1030         udelay(10);
1031 }
1032
1033 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1034 {
1035         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1036
1037         return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1038                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1039 }
1040
1041 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1042 {
1043         /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1044         if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1045                 *cmd |= 0x7f0 << 18;
1046 }
1047
1048 DECLARE_RTL_COND(rtl_eriar_cond)
1049 {
1050         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1051 }
1052
1053 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1054                            u32 val, int type)
1055 {
1056         u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1057
1058         BUG_ON((addr & 3) || (mask == 0));
1059         RTL_W32(tp, ERIDR, val);
1060         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1061         RTL_W32(tp, ERIAR, cmd);
1062
1063         rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1064 }
1065
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1067                           u32 val)
1068 {
1069         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1070 }
1071
1072 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1073 {
1074         u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1075
1076         r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1077         RTL_W32(tp, ERIAR, cmd);
1078
1079         return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1080                 RTL_R32(tp, ERIDR) : ~0;
1081 }
1082
1083 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1084 {
1085         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1086 }
1087
1088 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1089 {
1090         u32 val = rtl_eri_read(tp, addr);
1091
1092         rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1093 }
1094
1095 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1096 {
1097         rtl_w0w1_eri(tp, addr, p, 0);
1098 }
1099
1100 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1101 {
1102         rtl_w0w1_eri(tp, addr, 0, m);
1103 }
1104
1105 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1106 {
1107         RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1108         return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1109                 RTL_R32(tp, OCPDR) : ~0;
1110 }
1111
1112 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1113 {
1114         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1115 }
1116
1117 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1118                               u32 data)
1119 {
1120         RTL_W32(tp, OCPDR, data);
1121         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1122         rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1123 }
1124
1125 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126                               u32 data)
1127 {
1128         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1129                        data, ERIAR_OOB);
1130 }
1131
1132 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1133 {
1134         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1135
1136         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1137 }
1138
1139 #define OOB_CMD_RESET           0x00
1140 #define OOB_CMD_DRIVER_START    0x05
1141 #define OOB_CMD_DRIVER_STOP     0x06
1142
1143 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1144 {
1145         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1146 }
1147
1148 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1149 {
1150         u16 reg;
1151
1152         reg = rtl8168_get_ocp_reg(tp);
1153
1154         return r8168dp_ocp_read(tp, reg) & 0x00000800;
1155 }
1156
1157 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1158 {
1159         return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1160 }
1161
1162 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1163 {
1164         return RTL_R8(tp, IBISR0) & 0x20;
1165 }
1166
1167 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1168 {
1169         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1170         rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1171         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1172         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1173 }
1174
1175 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1176 {
1177         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1178         rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1179 }
1180
1181 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1182 {
1183         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1184         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1185         rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1186 }
1187
1188 static void rtl8168_driver_start(struct rtl8169_private *tp)
1189 {
1190         switch (tp->mac_version) {
1191         case RTL_GIGA_MAC_VER_27:
1192         case RTL_GIGA_MAC_VER_28:
1193         case RTL_GIGA_MAC_VER_31:
1194                 rtl8168dp_driver_start(tp);
1195                 break;
1196         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1197                 rtl8168ep_driver_start(tp);
1198                 break;
1199         default:
1200                 BUG();
1201                 break;
1202         }
1203 }
1204
1205 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1206 {
1207         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1208         rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1209 }
1210
1211 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1212 {
1213         rtl8168ep_stop_cmac(tp);
1214         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1215         r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1216         rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1217 }
1218
1219 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1220 {
1221         switch (tp->mac_version) {
1222         case RTL_GIGA_MAC_VER_27:
1223         case RTL_GIGA_MAC_VER_28:
1224         case RTL_GIGA_MAC_VER_31:
1225                 rtl8168dp_driver_stop(tp);
1226                 break;
1227         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1228                 rtl8168ep_driver_stop(tp);
1229                 break;
1230         default:
1231                 BUG();
1232                 break;
1233         }
1234 }
1235
1236 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1237 {
1238         u16 reg = rtl8168_get_ocp_reg(tp);
1239
1240         return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1241 }
1242
1243 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1244 {
1245         return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1246 }
1247
1248 static bool r8168_check_dash(struct rtl8169_private *tp)
1249 {
1250         switch (tp->mac_version) {
1251         case RTL_GIGA_MAC_VER_27:
1252         case RTL_GIGA_MAC_VER_28:
1253         case RTL_GIGA_MAC_VER_31:
1254                 return r8168dp_check_dash(tp);
1255         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1256                 return r8168ep_check_dash(tp);
1257         default:
1258                 return false;
1259         }
1260 }
1261
1262 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1263 {
1264         rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1265         rtl_eri_set_bits(tp, 0xdc, BIT(0));
1266 }
1267
1268 DECLARE_RTL_COND(rtl_efusear_cond)
1269 {
1270         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1271 }
1272
1273 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1274 {
1275         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1276
1277         return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1278                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1279 }
1280
1281 static u32 rtl_get_events(struct rtl8169_private *tp)
1282 {
1283         if (rtl_is_8125(tp))
1284                 return RTL_R32(tp, IntrStatus_8125);
1285         else
1286                 return RTL_R16(tp, IntrStatus);
1287 }
1288
1289 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1290 {
1291         if (rtl_is_8125(tp))
1292                 RTL_W32(tp, IntrStatus_8125, bits);
1293         else
1294                 RTL_W16(tp, IntrStatus, bits);
1295 }
1296
1297 static void rtl_irq_disable(struct rtl8169_private *tp)
1298 {
1299         if (rtl_is_8125(tp))
1300                 RTL_W32(tp, IntrMask_8125, 0);
1301         else
1302                 RTL_W16(tp, IntrMask, 0);
1303 }
1304
1305 static void rtl_irq_enable(struct rtl8169_private *tp)
1306 {
1307         if (rtl_is_8125(tp))
1308                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1309         else
1310                 RTL_W16(tp, IntrMask, tp->irq_mask);
1311 }
1312
1313 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1314 {
1315         rtl_irq_disable(tp);
1316         rtl_ack_events(tp, 0xffffffff);
1317         rtl_pci_commit(tp);
1318 }
1319
1320 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1321 {
1322         struct phy_device *phydev = tp->phydev;
1323
1324         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1325             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1326                 if (phydev->speed == SPEED_1000) {
1327                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1328                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1329                 } else if (phydev->speed == SPEED_100) {
1330                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1331                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1332                 } else {
1333                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1334                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1335                 }
1336                 rtl_reset_packet_filter(tp);
1337         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1338                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1339                 if (phydev->speed == SPEED_1000) {
1340                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1341                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342                 } else {
1343                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1344                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1345                 }
1346         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1347                 if (phydev->speed == SPEED_10) {
1348                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1349                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1350                 } else {
1351                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1352                 }
1353         }
1354 }
1355
1356 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1357
1358 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1359 {
1360         struct rtl8169_private *tp = netdev_priv(dev);
1361
1362         wol->supported = WAKE_ANY;
1363         wol->wolopts = tp->saved_wolopts;
1364 }
1365
1366 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1367 {
1368         static const struct {
1369                 u32 opt;
1370                 u16 reg;
1371                 u8  mask;
1372         } cfg[] = {
1373                 { WAKE_PHY,   Config3, LinkUp },
1374                 { WAKE_UCAST, Config5, UWF },
1375                 { WAKE_BCAST, Config5, BWF },
1376                 { WAKE_MCAST, Config5, MWF },
1377                 { WAKE_ANY,   Config5, LanWake },
1378                 { WAKE_MAGIC, Config3, MagicPacket }
1379         };
1380         unsigned int i, tmp = ARRAY_SIZE(cfg);
1381         u8 options;
1382
1383         rtl_unlock_config_regs(tp);
1384
1385         if (rtl_is_8168evl_up(tp)) {
1386                 tmp--;
1387                 if (wolopts & WAKE_MAGIC)
1388                         rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1389                 else
1390                         rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1391         } else if (rtl_is_8125(tp)) {
1392                 tmp--;
1393                 if (wolopts & WAKE_MAGIC)
1394                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1395                 else
1396                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1397         }
1398
1399         for (i = 0; i < tmp; i++) {
1400                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1401                 if (wolopts & cfg[i].opt)
1402                         options |= cfg[i].mask;
1403                 RTL_W8(tp, cfg[i].reg, options);
1404         }
1405
1406         switch (tp->mac_version) {
1407         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1408                 options = RTL_R8(tp, Config1) & ~PMEnable;
1409                 if (wolopts)
1410                         options |= PMEnable;
1411                 RTL_W8(tp, Config1, options);
1412                 break;
1413         case RTL_GIGA_MAC_VER_34:
1414         case RTL_GIGA_MAC_VER_37:
1415         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1416                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1417                 if (wolopts)
1418                         options |= PME_SIGNAL;
1419                 RTL_W8(tp, Config2, options);
1420                 break;
1421         default:
1422                 break;
1423         }
1424
1425         rtl_lock_config_regs(tp);
1426
1427         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1428         tp->dev->wol_enabled = wolopts ? 1 : 0;
1429 }
1430
1431 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1432 {
1433         struct rtl8169_private *tp = netdev_priv(dev);
1434
1435         if (wol->wolopts & ~WAKE_ANY)
1436                 return -EINVAL;
1437
1438         tp->saved_wolopts = wol->wolopts;
1439         __rtl8169_set_wol(tp, tp->saved_wolopts);
1440
1441         return 0;
1442 }
1443
1444 static void rtl8169_get_drvinfo(struct net_device *dev,
1445                                 struct ethtool_drvinfo *info)
1446 {
1447         struct rtl8169_private *tp = netdev_priv(dev);
1448         struct rtl_fw *rtl_fw = tp->rtl_fw;
1449
1450         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1451         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1452         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1453         if (rtl_fw)
1454                 strlcpy(info->fw_version, rtl_fw->version,
1455                         sizeof(info->fw_version));
1456 }
1457
1458 static int rtl8169_get_regs_len(struct net_device *dev)
1459 {
1460         return R8169_REGS_SIZE;
1461 }
1462
1463 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1464         netdev_features_t features)
1465 {
1466         struct rtl8169_private *tp = netdev_priv(dev);
1467
1468         if (dev->mtu > TD_MSS_MAX)
1469                 features &= ~NETIF_F_ALL_TSO;
1470
1471         if (dev->mtu > ETH_DATA_LEN &&
1472             tp->mac_version > RTL_GIGA_MAC_VER_06)
1473                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1474
1475         return features;
1476 }
1477
1478 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1479                                        netdev_features_t features)
1480 {
1481         u32 rx_config = RTL_R32(tp, RxConfig);
1482
1483         if (features & NETIF_F_RXALL)
1484                 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1485         else
1486                 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1487
1488         if (rtl_is_8125(tp)) {
1489                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1490                         rx_config |= RX_VLAN_8125;
1491                 else
1492                         rx_config &= ~RX_VLAN_8125;
1493         }
1494
1495         RTL_W32(tp, RxConfig, rx_config);
1496 }
1497
1498 static int rtl8169_set_features(struct net_device *dev,
1499                                 netdev_features_t features)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502
1503         rtl_set_rx_config_features(tp, features);
1504
1505         if (features & NETIF_F_RXCSUM)
1506                 tp->cp_cmd |= RxChkSum;
1507         else
1508                 tp->cp_cmd &= ~RxChkSum;
1509
1510         if (!rtl_is_8125(tp)) {
1511                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1512                         tp->cp_cmd |= RxVlan;
1513                 else
1514                         tp->cp_cmd &= ~RxVlan;
1515         }
1516
1517         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1518         rtl_pci_commit(tp);
1519
1520         return 0;
1521 }
1522
1523 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1524 {
1525         return (skb_vlan_tag_present(skb)) ?
1526                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1527 }
1528
1529 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1530 {
1531         u32 opts2 = le32_to_cpu(desc->opts2);
1532
1533         if (opts2 & RxVlanTag)
1534                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1535 }
1536
1537 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1538                              void *p)
1539 {
1540         struct rtl8169_private *tp = netdev_priv(dev);
1541         u32 __iomem *data = tp->mmio_addr;
1542         u32 *dw = p;
1543         int i;
1544
1545         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1546                 memcpy_fromio(dw++, data++, 4);
1547 }
1548
1549 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1550         "tx_packets",
1551         "rx_packets",
1552         "tx_errors",
1553         "rx_errors",
1554         "rx_missed",
1555         "align_errors",
1556         "tx_single_collisions",
1557         "tx_multi_collisions",
1558         "unicast",
1559         "broadcast",
1560         "multicast",
1561         "tx_aborted",
1562         "tx_underrun",
1563 };
1564
1565 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1566 {
1567         switch (sset) {
1568         case ETH_SS_STATS:
1569                 return ARRAY_SIZE(rtl8169_gstrings);
1570         default:
1571                 return -EOPNOTSUPP;
1572         }
1573 }
1574
1575 DECLARE_RTL_COND(rtl_counters_cond)
1576 {
1577         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1578 }
1579
1580 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1581 {
1582         dma_addr_t paddr = tp->counters_phys_addr;
1583         u32 cmd;
1584
1585         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1586         rtl_pci_commit(tp);
1587         cmd = (u64)paddr & DMA_BIT_MASK(32);
1588         RTL_W32(tp, CounterAddrLow, cmd);
1589         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1590
1591         rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1592 }
1593
1594 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1595 {
1596         /*
1597          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1598          * tally counters.
1599          */
1600         if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1601                 rtl8169_do_counters(tp, CounterReset);
1602 }
1603
1604 static void rtl8169_update_counters(struct rtl8169_private *tp)
1605 {
1606         u8 val = RTL_R8(tp, ChipCmd);
1607
1608         /*
1609          * Some chips are unable to dump tally counters when the receiver
1610          * is disabled. If 0xff chip may be in a PCI power-save state.
1611          */
1612         if (val & CmdRxEnb && val != 0xff)
1613                 rtl8169_do_counters(tp, CounterDump);
1614 }
1615
1616 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1617 {
1618         struct rtl8169_counters *counters = tp->counters;
1619
1620         /*
1621          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1622          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1623          * reset by a power cycle, while the counter values collected by the
1624          * driver are reset at every driver unload/load cycle.
1625          *
1626          * To make sure the HW values returned by @get_stats64 match the SW
1627          * values, we collect the initial values at first open(*) and use them
1628          * as offsets to normalize the values returned by @get_stats64.
1629          *
1630          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1631          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1632          * set at open time by rtl_hw_start.
1633          */
1634
1635         if (tp->tc_offset.inited)
1636                 return;
1637
1638         rtl8169_reset_counters(tp);
1639         rtl8169_update_counters(tp);
1640
1641         tp->tc_offset.tx_errors = counters->tx_errors;
1642         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1643         tp->tc_offset.tx_aborted = counters->tx_aborted;
1644         tp->tc_offset.rx_missed = counters->rx_missed;
1645         tp->tc_offset.inited = true;
1646 }
1647
1648 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1649                                       struct ethtool_stats *stats, u64 *data)
1650 {
1651         struct rtl8169_private *tp = netdev_priv(dev);
1652         struct rtl8169_counters *counters;
1653
1654         counters = tp->counters;
1655         rtl8169_update_counters(tp);
1656
1657         data[0] = le64_to_cpu(counters->tx_packets);
1658         data[1] = le64_to_cpu(counters->rx_packets);
1659         data[2] = le64_to_cpu(counters->tx_errors);
1660         data[3] = le32_to_cpu(counters->rx_errors);
1661         data[4] = le16_to_cpu(counters->rx_missed);
1662         data[5] = le16_to_cpu(counters->align_errors);
1663         data[6] = le32_to_cpu(counters->tx_one_collision);
1664         data[7] = le32_to_cpu(counters->tx_multi_collision);
1665         data[8] = le64_to_cpu(counters->rx_unicast);
1666         data[9] = le64_to_cpu(counters->rx_broadcast);
1667         data[10] = le32_to_cpu(counters->rx_multicast);
1668         data[11] = le16_to_cpu(counters->tx_aborted);
1669         data[12] = le16_to_cpu(counters->tx_underun);
1670 }
1671
1672 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1673 {
1674         switch(stringset) {
1675         case ETH_SS_STATS:
1676                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1677                 break;
1678         }
1679 }
1680
1681 /*
1682  * Interrupt coalescing
1683  *
1684  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1685  * >     8169, 8168 and 810x line of chipsets
1686  *
1687  * 8169, 8168, and 8136(810x) serial chipsets support it.
1688  *
1689  * > 2 - the Tx timer unit at gigabit speed
1690  *
1691  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1692  * (0xe0) bit 1 and bit 0.
1693  *
1694  * For 8169
1695  * bit[1:0] \ speed        1000M           100M            10M
1696  * 0 0                     320ns           2.56us          40.96us
1697  * 0 1                     2.56us          20.48us         327.7us
1698  * 1 0                     5.12us          40.96us         655.4us
1699  * 1 1                     10.24us         81.92us         1.31ms
1700  *
1701  * For the other
1702  * bit[1:0] \ speed        1000M           100M            10M
1703  * 0 0                     5us             2.56us          40.96us
1704  * 0 1                     40us            20.48us         327.7us
1705  * 1 0                     80us            40.96us         655.4us
1706  * 1 1                     160us           81.92us         1.31ms
1707  */
1708
1709 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1710 struct rtl_coalesce_info {
1711         u32 speed;
1712         u32 scale_nsecs[4];
1713 };
1714
1715 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1716 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1717
1718 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1719         { SPEED_1000,   COALESCE_DELAY(320) },
1720         { SPEED_100,    COALESCE_DELAY(2560) },
1721         { SPEED_10,     COALESCE_DELAY(40960) },
1722         { 0 },
1723 };
1724
1725 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1726         { SPEED_1000,   COALESCE_DELAY(5000) },
1727         { SPEED_100,    COALESCE_DELAY(2560) },
1728         { SPEED_10,     COALESCE_DELAY(40960) },
1729         { 0 },
1730 };
1731 #undef COALESCE_DELAY
1732
1733 /* get rx/tx scale vector corresponding to current speed */
1734 static const struct rtl_coalesce_info *
1735 rtl_coalesce_info(struct rtl8169_private *tp)
1736 {
1737         const struct rtl_coalesce_info *ci;
1738
1739         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1740                 ci = rtl_coalesce_info_8169;
1741         else
1742                 ci = rtl_coalesce_info_8168_8136;
1743
1744         /* if speed is unknown assume highest one */
1745         if (tp->phydev->speed == SPEED_UNKNOWN)
1746                 return ci;
1747
1748         for (; ci->speed; ci++) {
1749                 if (tp->phydev->speed == ci->speed)
1750                         return ci;
1751         }
1752
1753         return ERR_PTR(-ELNRNG);
1754 }
1755
1756 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1757 {
1758         struct rtl8169_private *tp = netdev_priv(dev);
1759         const struct rtl_coalesce_info *ci;
1760         u32 scale, c_us, c_fr;
1761         u16 intrmit;
1762
1763         if (rtl_is_8125(tp))
1764                 return -EOPNOTSUPP;
1765
1766         memset(ec, 0, sizeof(*ec));
1767
1768         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1769         ci = rtl_coalesce_info(tp);
1770         if (IS_ERR(ci))
1771                 return PTR_ERR(ci);
1772
1773         scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1774
1775         intrmit = RTL_R16(tp, IntrMitigate);
1776
1777         c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1778         ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1779
1780         c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1781         /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1782         ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1783
1784         c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1785         ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1786
1787         c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1788         ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1789
1790         return 0;
1791 }
1792
1793 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1794 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1795                                      u16 *cp01)
1796 {
1797         const struct rtl_coalesce_info *ci;
1798         u16 i;
1799
1800         ci = rtl_coalesce_info(tp);
1801         if (IS_ERR(ci))
1802                 return PTR_ERR(ci);
1803
1804         for (i = 0; i < 4; i++) {
1805                 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1806                         *cp01 = i;
1807                         return ci->scale_nsecs[i];
1808                 }
1809         }
1810
1811         return -ERANGE;
1812 }
1813
1814 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1815 {
1816         struct rtl8169_private *tp = netdev_priv(dev);
1817         u32 tx_fr = ec->tx_max_coalesced_frames;
1818         u32 rx_fr = ec->rx_max_coalesced_frames;
1819         u32 coal_usec_max, units;
1820         u16 w = 0, cp01 = 0;
1821         int scale;
1822
1823         if (rtl_is_8125(tp))
1824                 return -EOPNOTSUPP;
1825
1826         if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1827                 return -ERANGE;
1828
1829         coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1830         scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1831         if (scale < 0)
1832                 return scale;
1833
1834         /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1835          * not only when usecs=0 because of e.g. the following scenario:
1836          *
1837          * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1838          * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1839          * - then user does `ethtool -C eth0 rx-usecs 100`
1840          *
1841          * Since ethtool sends to kernel whole ethtool_coalesce settings,
1842          * if we want to ignore rx_frames then it has to be set to 0.
1843          */
1844         if (rx_fr == 1)
1845                 rx_fr = 0;
1846         if (tx_fr == 1)
1847                 tx_fr = 0;
1848
1849         /* HW requires time limit to be set if frame limit is set */
1850         if ((tx_fr && !ec->tx_coalesce_usecs) ||
1851             (rx_fr && !ec->rx_coalesce_usecs))
1852                 return -EINVAL;
1853
1854         w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1855         w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1856
1857         units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1858         w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1859         units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1860         w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1861
1862         RTL_W16(tp, IntrMitigate, w);
1863
1864         /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1865         if (rtl_is_8168evl_up(tp)) {
1866                 if (!rx_fr && !tx_fr)
1867                         /* disable packet counter */
1868                         tp->cp_cmd |= PktCntrDisable;
1869                 else
1870                         tp->cp_cmd &= ~PktCntrDisable;
1871         }
1872
1873         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1874         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1875         rtl_pci_commit(tp);
1876
1877         return 0;
1878 }
1879
1880 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1881 {
1882         struct rtl8169_private *tp = netdev_priv(dev);
1883
1884         if (!rtl_supports_eee(tp))
1885                 return -EOPNOTSUPP;
1886
1887         return phy_ethtool_get_eee(tp->phydev, data);
1888 }
1889
1890 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1891 {
1892         struct rtl8169_private *tp = netdev_priv(dev);
1893         int ret;
1894
1895         if (!rtl_supports_eee(tp))
1896                 return -EOPNOTSUPP;
1897
1898         ret = phy_ethtool_set_eee(tp->phydev, data);
1899
1900         if (!ret)
1901                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1902                                            MDIO_AN_EEE_ADV);
1903         return ret;
1904 }
1905
1906 static const struct ethtool_ops rtl8169_ethtool_ops = {
1907         .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1908                                      ETHTOOL_COALESCE_MAX_FRAMES,
1909         .get_drvinfo            = rtl8169_get_drvinfo,
1910         .get_regs_len           = rtl8169_get_regs_len,
1911         .get_link               = ethtool_op_get_link,
1912         .get_coalesce           = rtl_get_coalesce,
1913         .set_coalesce           = rtl_set_coalesce,
1914         .get_regs               = rtl8169_get_regs,
1915         .get_wol                = rtl8169_get_wol,
1916         .set_wol                = rtl8169_set_wol,
1917         .get_strings            = rtl8169_get_strings,
1918         .get_sset_count         = rtl8169_get_sset_count,
1919         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1920         .get_ts_info            = ethtool_op_get_ts_info,
1921         .nway_reset             = phy_ethtool_nway_reset,
1922         .get_eee                = rtl8169_get_eee,
1923         .set_eee                = rtl8169_set_eee,
1924         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1925         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1926 };
1927
1928 static void rtl_enable_eee(struct rtl8169_private *tp)
1929 {
1930         struct phy_device *phydev = tp->phydev;
1931         int adv;
1932
1933         /* respect EEE advertisement the user may have set */
1934         if (tp->eee_adv >= 0)
1935                 adv = tp->eee_adv;
1936         else
1937                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1938
1939         if (adv >= 0)
1940                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1941 }
1942
1943 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1944 {
1945         /*
1946          * The driver currently handles the 8168Bf and the 8168Be identically
1947          * but they can be identified more specifically through the test below
1948          * if needed:
1949          *
1950          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1951          *
1952          * Same thing for the 8101Eb and the 8101Ec:
1953          *
1954          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1955          */
1956         static const struct rtl_mac_info {
1957                 u16 mask;
1958                 u16 val;
1959                 enum mac_version ver;
1960         } mac_info[] = {
1961                 /* 8125B family. */
1962                 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1963
1964                 /* 8125A family. */
1965                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1966                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1967
1968                 /* RTL8117 */
1969                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1970
1971                 /* 8168EP family. */
1972                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1973                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1974                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1975
1976                 /* 8168H family. */
1977                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1978                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1979
1980                 /* 8168G family. */
1981                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1982                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1983                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1984                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1985
1986                 /* 8168F family. */
1987                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1988                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1989                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1990
1991                 /* 8168E family. */
1992                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1993                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1994                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1995
1996                 /* 8168D family. */
1997                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1998                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1999
2000                 /* 8168DP family. */
2001                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2002                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2003                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2004
2005                 /* 8168C family. */
2006                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2007                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2008                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2009                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2010                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2011                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2012                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2013
2014                 /* 8168B family. */
2015                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2016                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2017                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2018
2019                 /* 8101 family. */
2020                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2021                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2022                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2023                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2024                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2025                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2026                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2027                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2028                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2029                 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2030                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2031                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2032                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2033                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2034                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2035                 /* FIXME: where did these entries come from ? -- FR */
2036                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2037                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2038
2039                 /* 8110 family. */
2040                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2041                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2042                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2043                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2044                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2045
2046                 /* Catch-all */
2047                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2048         };
2049         const struct rtl_mac_info *p = mac_info;
2050         enum mac_version ver;
2051
2052         while ((xid & p->mask) != p->val)
2053                 p++;
2054         ver = p->ver;
2055
2056         if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2057                 if (ver == RTL_GIGA_MAC_VER_42)
2058                         ver = RTL_GIGA_MAC_VER_43;
2059                 else if (ver == RTL_GIGA_MAC_VER_45)
2060                         ver = RTL_GIGA_MAC_VER_47;
2061                 else if (ver == RTL_GIGA_MAC_VER_46)
2062                         ver = RTL_GIGA_MAC_VER_48;
2063         }
2064
2065         return ver;
2066 }
2067
2068 static void rtl_release_firmware(struct rtl8169_private *tp)
2069 {
2070         if (tp->rtl_fw) {
2071                 rtl_fw_release_firmware(tp->rtl_fw);
2072                 kfree(tp->rtl_fw);
2073                 tp->rtl_fw = NULL;
2074         }
2075 }
2076
2077 void r8169_apply_firmware(struct rtl8169_private *tp)
2078 {
2079         int val;
2080
2081         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2082         if (tp->rtl_fw) {
2083                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2084                 /* At least one firmware doesn't reset tp->ocp_base. */
2085                 tp->ocp_base = OCP_STD_PHY_BASE;
2086
2087                 /* PHY soft reset may still be in progress */
2088                 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2089                                       !(val & BMCR_RESET),
2090                                       50000, 600000, true);
2091         }
2092 }
2093
2094 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2095 {
2096         /* Adjust EEE LED frequency */
2097         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2098                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2099
2100         rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2101 }
2102
2103 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2104 {
2105         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2106         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2107 }
2108
2109 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2110 {
2111         RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2112 }
2113
2114 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2115 {
2116         rtl8125_set_eee_txidle_timer(tp);
2117         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2118 }
2119
2120 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2121 {
2122         const u16 w[] = {
2123                 addr[0] | (addr[1] << 8),
2124                 addr[2] | (addr[3] << 8),
2125                 addr[4] | (addr[5] << 8)
2126         };
2127
2128         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2129         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2130         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2131         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2132 }
2133
2134 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2135 {
2136         u16 data1, data2, ioffset;
2137
2138         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2139         data1 = r8168_mac_ocp_read(tp, 0xdd02);
2140         data2 = r8168_mac_ocp_read(tp, 0xdd00);
2141
2142         ioffset = (data2 >> 1) & 0x7ff8;
2143         ioffset |= data2 & 0x0007;
2144         if (data1 & BIT(7))
2145                 ioffset |= BIT(15);
2146
2147         return ioffset;
2148 }
2149
2150 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2151 {
2152         set_bit(flag, tp->wk.flags);
2153         schedule_work(&tp->wk.work);
2154 }
2155
2156 static void rtl8169_init_phy(struct rtl8169_private *tp)
2157 {
2158         r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2159
2160         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2161                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2162                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2163                 /* set undocumented MAC Reg C+CR Offset 0x82h */
2164                 RTL_W8(tp, 0x82, 0x01);
2165         }
2166
2167         if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2168             tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2169             tp->pci_dev->subsystem_device == 0xe000)
2170                 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2171
2172         /* We may have called phy_speed_down before */
2173         phy_speed_up(tp->phydev);
2174
2175         if (rtl_supports_eee(tp))
2176                 rtl_enable_eee(tp);
2177
2178         genphy_soft_reset(tp->phydev);
2179 }
2180
2181 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2182 {
2183         rtl_unlock_config_regs(tp);
2184
2185         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2186         rtl_pci_commit(tp);
2187
2188         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2189         rtl_pci_commit(tp);
2190
2191         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2192                 rtl_rar_exgmac_set(tp, addr);
2193
2194         rtl_lock_config_regs(tp);
2195 }
2196
2197 static int rtl_set_mac_address(struct net_device *dev, void *p)
2198 {
2199         struct rtl8169_private *tp = netdev_priv(dev);
2200         int ret;
2201
2202         ret = eth_mac_addr(dev, p);
2203         if (ret)
2204                 return ret;
2205
2206         rtl_rar_set(tp, dev->dev_addr);
2207
2208         return 0;
2209 }
2210
2211 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2212 {
2213         switch (tp->mac_version) {
2214         case RTL_GIGA_MAC_VER_25:
2215         case RTL_GIGA_MAC_VER_26:
2216         case RTL_GIGA_MAC_VER_29:
2217         case RTL_GIGA_MAC_VER_30:
2218         case RTL_GIGA_MAC_VER_32:
2219         case RTL_GIGA_MAC_VER_33:
2220         case RTL_GIGA_MAC_VER_34:
2221         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2222                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2223                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2224                 break;
2225         default:
2226                 break;
2227         }
2228 }
2229
2230 static void rtl_pll_power_down(struct rtl8169_private *tp)
2231 {
2232         if (r8168_check_dash(tp))
2233                 return;
2234
2235         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2236             tp->mac_version == RTL_GIGA_MAC_VER_33)
2237                 rtl_ephy_write(tp, 0x19, 0xff64);
2238
2239         if (device_may_wakeup(tp_to_dev(tp))) {
2240                 phy_speed_down(tp->phydev, false);
2241                 rtl_wol_suspend_quirk(tp);
2242                 return;
2243         }
2244
2245         switch (tp->mac_version) {
2246         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2247         case RTL_GIGA_MAC_VER_37:
2248         case RTL_GIGA_MAC_VER_39:
2249         case RTL_GIGA_MAC_VER_43:
2250         case RTL_GIGA_MAC_VER_44:
2251         case RTL_GIGA_MAC_VER_45:
2252         case RTL_GIGA_MAC_VER_46:
2253         case RTL_GIGA_MAC_VER_47:
2254         case RTL_GIGA_MAC_VER_48:
2255         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2256                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2257                 break;
2258         case RTL_GIGA_MAC_VER_40:
2259         case RTL_GIGA_MAC_VER_41:
2260         case RTL_GIGA_MAC_VER_49:
2261                 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2262                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2263                 break;
2264         default:
2265                 break;
2266         }
2267 }
2268
2269 static void rtl_pll_power_up(struct rtl8169_private *tp)
2270 {
2271         switch (tp->mac_version) {
2272         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2273         case RTL_GIGA_MAC_VER_37:
2274         case RTL_GIGA_MAC_VER_39:
2275         case RTL_GIGA_MAC_VER_43:
2276                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2277                 break;
2278         case RTL_GIGA_MAC_VER_44:
2279         case RTL_GIGA_MAC_VER_45:
2280         case RTL_GIGA_MAC_VER_46:
2281         case RTL_GIGA_MAC_VER_47:
2282         case RTL_GIGA_MAC_VER_48:
2283         case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2284                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2285                 break;
2286         case RTL_GIGA_MAC_VER_40:
2287         case RTL_GIGA_MAC_VER_41:
2288         case RTL_GIGA_MAC_VER_49:
2289                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2290                 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2291                 break;
2292         default:
2293                 break;
2294         }
2295
2296         phy_resume(tp->phydev);
2297 }
2298
2299 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2300 {
2301         switch (tp->mac_version) {
2302         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2303         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2304                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2305                 break;
2306         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2307         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2308         case RTL_GIGA_MAC_VER_38:
2309                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2310                 break;
2311         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2312                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2313                 break;
2314         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2315                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2316                 break;
2317         default:
2318                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2319                 break;
2320         }
2321 }
2322
2323 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2324 {
2325         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2326 }
2327
2328 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2329 {
2330         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2331         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2332 }
2333
2334 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2335 {
2336         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2337         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2338 }
2339
2340 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2341 {
2342         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2343 }
2344
2345 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2346 {
2347         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2348 }
2349
2350 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2351 {
2352         RTL_W8(tp, MaxTxPacketSize, 0x3f);
2353         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2354         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2355 }
2356
2357 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2358 {
2359         RTL_W8(tp, MaxTxPacketSize, 0x0c);
2360         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2361         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2362 }
2363
2364 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2365 {
2366         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2367 }
2368
2369 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2370 {
2371         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2372 }
2373
2374 static void rtl_jumbo_config(struct rtl8169_private *tp)
2375 {
2376         bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2377
2378         rtl_unlock_config_regs(tp);
2379         switch (tp->mac_version) {
2380         case RTL_GIGA_MAC_VER_12:
2381         case RTL_GIGA_MAC_VER_17:
2382                 if (jumbo) {
2383                         pcie_set_readrq(tp->pci_dev, 512);
2384                         r8168b_1_hw_jumbo_enable(tp);
2385                 } else {
2386                         r8168b_1_hw_jumbo_disable(tp);
2387                 }
2388                 break;
2389         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2390                 if (jumbo) {
2391                         pcie_set_readrq(tp->pci_dev, 512);
2392                         r8168c_hw_jumbo_enable(tp);
2393                 } else {
2394                         r8168c_hw_jumbo_disable(tp);
2395                 }
2396                 break;
2397         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2398                 if (jumbo)
2399                         r8168dp_hw_jumbo_enable(tp);
2400                 else
2401                         r8168dp_hw_jumbo_disable(tp);
2402                 break;
2403         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2404                 if (jumbo) {
2405                         pcie_set_readrq(tp->pci_dev, 512);
2406                         r8168e_hw_jumbo_enable(tp);
2407                 } else {
2408                         r8168e_hw_jumbo_disable(tp);
2409                 }
2410                 break;
2411         default:
2412                 break;
2413         }
2414         rtl_lock_config_regs(tp);
2415
2416         if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2417                 pcie_set_readrq(tp->pci_dev, 4096);
2418 }
2419
2420 DECLARE_RTL_COND(rtl_chipcmd_cond)
2421 {
2422         return RTL_R8(tp, ChipCmd) & CmdReset;
2423 }
2424
2425 static void rtl_hw_reset(struct rtl8169_private *tp)
2426 {
2427         RTL_W8(tp, ChipCmd, CmdReset);
2428
2429         rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2430 }
2431
2432 static void rtl_request_firmware(struct rtl8169_private *tp)
2433 {
2434         struct rtl_fw *rtl_fw;
2435
2436         /* firmware loaded already or no firmware available */
2437         if (tp->rtl_fw || !tp->fw_name)
2438                 return;
2439
2440         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2441         if (!rtl_fw)
2442                 return;
2443
2444         rtl_fw->phy_write = rtl_writephy;
2445         rtl_fw->phy_read = rtl_readphy;
2446         rtl_fw->mac_mcu_write = mac_mcu_write;
2447         rtl_fw->mac_mcu_read = mac_mcu_read;
2448         rtl_fw->fw_name = tp->fw_name;
2449         rtl_fw->dev = tp_to_dev(tp);
2450
2451         if (rtl_fw_request_firmware(rtl_fw))
2452                 kfree(rtl_fw);
2453         else
2454                 tp->rtl_fw = rtl_fw;
2455 }
2456
2457 static void rtl_rx_close(struct rtl8169_private *tp)
2458 {
2459         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2460 }
2461
2462 DECLARE_RTL_COND(rtl_npq_cond)
2463 {
2464         return RTL_R8(tp, TxPoll) & NPQ;
2465 }
2466
2467 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2468 {
2469         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2470 }
2471
2472 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2473 {
2474         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2475 }
2476
2477 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2478 {
2479         /* IntrMitigate has new functionality on RTL8125 */
2480         return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2481 }
2482
2483 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2484 {
2485         switch (tp->mac_version) {
2486         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2487                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2488                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2489                 break;
2490         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2491                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2492                 break;
2493         case RTL_GIGA_MAC_VER_63:
2494                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2495                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2496                 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2497                 break;
2498         default:
2499                 break;
2500         }
2501 }
2502
2503 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2504 {
2505         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2506         fsleep(2000);
2507         rtl_wait_txrx_fifo_empty(tp);
2508 }
2509
2510 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2511 {
2512         u32 val = TX_DMA_BURST << TxDMAShift |
2513                   InterFrameGap << TxInterFrameGapShift;
2514
2515         if (rtl_is_8168evl_up(tp))
2516                 val |= TXCFG_AUTO_FIFO;
2517
2518         RTL_W32(tp, TxConfig, val);
2519 }
2520
2521 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2522 {
2523         /* Low hurts. Let's disable the filtering. */
2524         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2525 }
2526
2527 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2528 {
2529         /*
2530          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2531          * register to be written before TxDescAddrLow to work.
2532          * Switching from MMIO to I/O access fixes the issue as well.
2533          */
2534         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2535         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2536         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2537         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2538 }
2539
2540 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2541 {
2542         u32 val;
2543
2544         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2545                 val = 0x000fff00;
2546         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2547                 val = 0x00ffff00;
2548         else
2549                 return;
2550
2551         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2552                 val |= 0xff;
2553
2554         RTL_W32(tp, 0x7c, val);
2555 }
2556
2557 static void rtl_set_rx_mode(struct net_device *dev)
2558 {
2559         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2560         /* Multicast hash filter */
2561         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2562         struct rtl8169_private *tp = netdev_priv(dev);
2563         u32 tmp;
2564
2565         if (dev->flags & IFF_PROMISC) {
2566                 rx_mode |= AcceptAllPhys;
2567         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2568                    dev->flags & IFF_ALLMULTI ||
2569                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
2570                 /* accept all multicasts */
2571         } else if (netdev_mc_empty(dev)) {
2572                 rx_mode &= ~AcceptMulticast;
2573         } else {
2574                 struct netdev_hw_addr *ha;
2575
2576                 mc_filter[1] = mc_filter[0] = 0;
2577                 netdev_for_each_mc_addr(ha, dev) {
2578                         u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2579                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2580                 }
2581
2582                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2583                         tmp = mc_filter[0];
2584                         mc_filter[0] = swab32(mc_filter[1]);
2585                         mc_filter[1] = swab32(tmp);
2586                 }
2587         }
2588
2589         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2590         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2591
2592         tmp = RTL_R32(tp, RxConfig);
2593         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2594 }
2595
2596 DECLARE_RTL_COND(rtl_csiar_cond)
2597 {
2598         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2599 }
2600
2601 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2602 {
2603         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2604
2605         RTL_W32(tp, CSIDR, value);
2606         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2607                 CSIAR_BYTE_ENABLE | func << 16);
2608
2609         rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2610 }
2611
2612 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2613 {
2614         u32 func = PCI_FUNC(tp->pci_dev->devfn);
2615
2616         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2617                 CSIAR_BYTE_ENABLE);
2618
2619         return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2620                 RTL_R32(tp, CSIDR) : ~0;
2621 }
2622
2623 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2624 {
2625         struct pci_dev *pdev = tp->pci_dev;
2626         u32 csi;
2627
2628         /* According to Realtek the value at config space address 0x070f
2629          * controls the L0s/L1 entrance latency. We try standard ECAM access
2630          * first and if it fails fall back to CSI.
2631          */
2632         if (pdev->cfg_size > 0x070f &&
2633             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2634                 return;
2635
2636         netdev_notice_once(tp->dev,
2637                 "No native access to PCI extended config space, falling back to CSI\n");
2638         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2639         rtl_csi_write(tp, 0x070c, csi | val << 24);
2640 }
2641
2642 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2643 {
2644         rtl_csi_access_enable(tp, 0x27);
2645 }
2646
2647 struct ephy_info {
2648         unsigned int offset;
2649         u16 mask;
2650         u16 bits;
2651 };
2652
2653 static void __rtl_ephy_init(struct rtl8169_private *tp,
2654                             const struct ephy_info *e, int len)
2655 {
2656         u16 w;
2657
2658         while (len-- > 0) {
2659                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2660                 rtl_ephy_write(tp, e->offset, w);
2661                 e++;
2662         }
2663 }
2664
2665 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2666
2667 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2668 {
2669         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2670                                    PCI_EXP_LNKCTL_CLKREQ_EN);
2671 }
2672
2673 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2674 {
2675         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2676                                  PCI_EXP_LNKCTL_CLKREQ_EN);
2677 }
2678
2679 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2680 {
2681         /* work around an issue when PCI reset occurs during L2/L3 state */
2682         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2683 }
2684
2685 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2686 {
2687         /* Don't enable ASPM in the chip if OS can't control ASPM */
2688         if (enable && tp->aspm_manageable) {
2689                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2690                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2691         } else {
2692                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2693                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2694         }
2695
2696         udelay(10);
2697 }
2698
2699 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2700                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2701 {
2702         /* Usage of dynamic vs. static FIFO is controlled by bit
2703          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2704          */
2705         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2706         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2707 }
2708
2709 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2710                                           u8 low, u8 high)
2711 {
2712         /* FIFO thresholds for pause flow control */
2713         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2714         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2715 }
2716
2717 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2718 {
2719         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2720 }
2721
2722 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2723 {
2724         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2725
2726         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2727
2728         rtl_disable_clock_request(tp);
2729 }
2730
2731 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2732 {
2733         static const struct ephy_info e_info_8168cp[] = {
2734                 { 0x01, 0,      0x0001 },
2735                 { 0x02, 0x0800, 0x1000 },
2736                 { 0x03, 0,      0x0042 },
2737                 { 0x06, 0x0080, 0x0000 },
2738                 { 0x07, 0,      0x2000 }
2739         };
2740
2741         rtl_set_def_aspm_entry_latency(tp);
2742
2743         rtl_ephy_init(tp, e_info_8168cp);
2744
2745         __rtl_hw_start_8168cp(tp);
2746 }
2747
2748 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2749 {
2750         rtl_set_def_aspm_entry_latency(tp);
2751
2752         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2753 }
2754
2755 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2756 {
2757         rtl_set_def_aspm_entry_latency(tp);
2758
2759         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2760
2761         /* Magic. */
2762         RTL_W8(tp, DBG_REG, 0x20);
2763 }
2764
2765 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2766 {
2767         static const struct ephy_info e_info_8168c_1[] = {
2768                 { 0x02, 0x0800, 0x1000 },
2769                 { 0x03, 0,      0x0002 },
2770                 { 0x06, 0x0080, 0x0000 }
2771         };
2772
2773         rtl_set_def_aspm_entry_latency(tp);
2774
2775         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2776
2777         rtl_ephy_init(tp, e_info_8168c_1);
2778
2779         __rtl_hw_start_8168cp(tp);
2780 }
2781
2782 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2783 {
2784         static const struct ephy_info e_info_8168c_2[] = {
2785                 { 0x01, 0,      0x0001 },
2786                 { 0x03, 0x0400, 0x0020 }
2787         };
2788
2789         rtl_set_def_aspm_entry_latency(tp);
2790
2791         rtl_ephy_init(tp, e_info_8168c_2);
2792
2793         __rtl_hw_start_8168cp(tp);
2794 }
2795
2796 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2797 {
2798         rtl_hw_start_8168c_2(tp);
2799 }
2800
2801 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2802 {
2803         rtl_set_def_aspm_entry_latency(tp);
2804
2805         __rtl_hw_start_8168cp(tp);
2806 }
2807
2808 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2809 {
2810         rtl_set_def_aspm_entry_latency(tp);
2811
2812         rtl_disable_clock_request(tp);
2813 }
2814
2815 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2816 {
2817         static const struct ephy_info e_info_8168d_4[] = {
2818                 { 0x0b, 0x0000, 0x0048 },
2819                 { 0x19, 0x0020, 0x0050 },
2820                 { 0x0c, 0x0100, 0x0020 },
2821                 { 0x10, 0x0004, 0x0000 },
2822         };
2823
2824         rtl_set_def_aspm_entry_latency(tp);
2825
2826         rtl_ephy_init(tp, e_info_8168d_4);
2827
2828         rtl_enable_clock_request(tp);
2829 }
2830
2831 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2832 {
2833         static const struct ephy_info e_info_8168e_1[] = {
2834                 { 0x00, 0x0200, 0x0100 },
2835                 { 0x00, 0x0000, 0x0004 },
2836                 { 0x06, 0x0002, 0x0001 },
2837                 { 0x06, 0x0000, 0x0030 },
2838                 { 0x07, 0x0000, 0x2000 },
2839                 { 0x00, 0x0000, 0x0020 },
2840                 { 0x03, 0x5800, 0x2000 },
2841                 { 0x03, 0x0000, 0x0001 },
2842                 { 0x01, 0x0800, 0x1000 },
2843                 { 0x07, 0x0000, 0x4000 },
2844                 { 0x1e, 0x0000, 0x2000 },
2845                 { 0x19, 0xffff, 0xfe6c },
2846                 { 0x0a, 0x0000, 0x0040 }
2847         };
2848
2849         rtl_set_def_aspm_entry_latency(tp);
2850
2851         rtl_ephy_init(tp, e_info_8168e_1);
2852
2853         rtl_disable_clock_request(tp);
2854
2855         /* Reset tx FIFO pointer */
2856         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2857         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2858
2859         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2860 }
2861
2862 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2863 {
2864         static const struct ephy_info e_info_8168e_2[] = {
2865                 { 0x09, 0x0000, 0x0080 },
2866                 { 0x19, 0x0000, 0x0224 },
2867                 { 0x00, 0x0000, 0x0004 },
2868                 { 0x0c, 0x3df0, 0x0200 },
2869         };
2870
2871         rtl_set_def_aspm_entry_latency(tp);
2872
2873         rtl_ephy_init(tp, e_info_8168e_2);
2874
2875         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2876         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2877         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2878         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2879         rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2880         rtl_reset_packet_filter(tp);
2881         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2882         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2883         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2884
2885         rtl_disable_clock_request(tp);
2886
2887         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2888
2889         rtl8168_config_eee_mac(tp);
2890
2891         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2892         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2893         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2894
2895         rtl_hw_aspm_clkreq_enable(tp, true);
2896 }
2897
2898 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2899 {
2900         rtl_set_def_aspm_entry_latency(tp);
2901
2902         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2903         rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2904         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2905         rtl_reset_packet_filter(tp);
2906         rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2907         rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2908         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2909         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2910
2911         rtl_disable_clock_request(tp);
2912
2913         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2914         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2915         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2916         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2917
2918         rtl8168_config_eee_mac(tp);
2919 }
2920
2921 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2922 {
2923         static const struct ephy_info e_info_8168f_1[] = {
2924                 { 0x06, 0x00c0, 0x0020 },
2925                 { 0x08, 0x0001, 0x0002 },
2926                 { 0x09, 0x0000, 0x0080 },
2927                 { 0x19, 0x0000, 0x0224 },
2928                 { 0x00, 0x0000, 0x0008 },
2929                 { 0x0c, 0x3df0, 0x0200 },
2930         };
2931
2932         rtl_hw_start_8168f(tp);
2933
2934         rtl_ephy_init(tp, e_info_8168f_1);
2935
2936         rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2937 }
2938
2939 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2940 {
2941         static const struct ephy_info e_info_8168f_1[] = {
2942                 { 0x06, 0x00c0, 0x0020 },
2943                 { 0x0f, 0xffff, 0x5200 },
2944                 { 0x19, 0x0000, 0x0224 },
2945                 { 0x00, 0x0000, 0x0008 },
2946                 { 0x0c, 0x3df0, 0x0200 },
2947         };
2948
2949         rtl_hw_start_8168f(tp);
2950         rtl_pcie_state_l2l3_disable(tp);
2951
2952         rtl_ephy_init(tp, e_info_8168f_1);
2953
2954         rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2955 }
2956
2957 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2958 {
2959         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2960         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2961
2962         rtl_set_def_aspm_entry_latency(tp);
2963
2964         rtl_reset_packet_filter(tp);
2965         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2966
2967         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2968
2969         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2970         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2971         rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2972
2973         rtl8168_config_eee_mac(tp);
2974
2975         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2976         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2977
2978         rtl_pcie_state_l2l3_disable(tp);
2979 }
2980
2981 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2982 {
2983         static const struct ephy_info e_info_8168g_1[] = {
2984                 { 0x00, 0x0008, 0x0000 },
2985                 { 0x0c, 0x3ff0, 0x0820 },
2986                 { 0x1e, 0x0000, 0x0001 },
2987                 { 0x19, 0x8000, 0x0000 }
2988         };
2989
2990         rtl_hw_start_8168g(tp);
2991
2992         /* disable aspm and clock request before access ephy */
2993         rtl_hw_aspm_clkreq_enable(tp, false);
2994         rtl_ephy_init(tp, e_info_8168g_1);
2995         rtl_hw_aspm_clkreq_enable(tp, true);
2996 }
2997
2998 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2999 {
3000         static const struct ephy_info e_info_8168g_2[] = {
3001                 { 0x00, 0x0008, 0x0000 },
3002                 { 0x0c, 0x3ff0, 0x0820 },
3003                 { 0x19, 0xffff, 0x7c00 },
3004                 { 0x1e, 0xffff, 0x20eb },
3005                 { 0x0d, 0xffff, 0x1666 },
3006                 { 0x00, 0xffff, 0x10a3 },
3007                 { 0x06, 0xffff, 0xf050 },
3008                 { 0x04, 0x0000, 0x0010 },
3009                 { 0x1d, 0x4000, 0x0000 },
3010         };
3011
3012         rtl_hw_start_8168g(tp);
3013
3014         /* disable aspm and clock request before access ephy */
3015         rtl_hw_aspm_clkreq_enable(tp, false);
3016         rtl_ephy_init(tp, e_info_8168g_2);
3017 }
3018
3019 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3020 {
3021         static const struct ephy_info e_info_8411_2[] = {
3022                 { 0x00, 0x0008, 0x0000 },
3023                 { 0x0c, 0x37d0, 0x0820 },
3024                 { 0x1e, 0x0000, 0x0001 },
3025                 { 0x19, 0x8021, 0x0000 },
3026                 { 0x1e, 0x0000, 0x2000 },
3027                 { 0x0d, 0x0100, 0x0200 },
3028                 { 0x00, 0x0000, 0x0080 },
3029                 { 0x06, 0x0000, 0x0010 },
3030                 { 0x04, 0x0000, 0x0010 },
3031                 { 0x1d, 0x0000, 0x4000 },
3032         };
3033
3034         rtl_hw_start_8168g(tp);
3035
3036         /* disable aspm and clock request before access ephy */
3037         rtl_hw_aspm_clkreq_enable(tp, false);
3038         rtl_ephy_init(tp, e_info_8411_2);
3039
3040         /* The following Realtek-provided magic fixes an issue with the RX unit
3041          * getting confused after the PHY having been powered-down.
3042          */
3043         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3044         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3045         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3046         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3047         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3048         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3049         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3050         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3051         mdelay(3);
3052         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3053
3054         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3055         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3056         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3057         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3058         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3059         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3060         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3061         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3062         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3063         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3064         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3065         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3066         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3067         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3068         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3069         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3070         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3071         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3072         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3073         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3074         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3075         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3076         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3077         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3078         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3079         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3080         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3081         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3082         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3083         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3084         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3085         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3086         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3087         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3088         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3089         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3090         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3091         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3092         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3093         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3094         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3095         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3096         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3097         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3098         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3099         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3100         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3101         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3102         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3103         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3104         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3105         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3106         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3107         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3108         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3109         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3110         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3111         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3112         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3113         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3114         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3115         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3116         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3117         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3118         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3119         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3120         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3121         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3122         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3123         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3124         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3125         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3126         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3127         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3128         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3129         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3130         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3131         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3132         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3133         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3134         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3135         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3136         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3137         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3138         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3139         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3140         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3141         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3142         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3143         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3144         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3145         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3146         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3147         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3148         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3149         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3150         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3151         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3152         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3153         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3154         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3155         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3156         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3157         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3158         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3159         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3160         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3161         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3162         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3163         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3164         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3165
3166         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3167
3168         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3169         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3170         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3171         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3172         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3173         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3174         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3175
3176         rtl_hw_aspm_clkreq_enable(tp, true);
3177 }
3178
3179 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3180 {
3181         static const struct ephy_info e_info_8168h_1[] = {
3182                 { 0x1e, 0x0800, 0x0001 },
3183                 { 0x1d, 0x0000, 0x0800 },
3184                 { 0x05, 0xffff, 0x2089 },
3185                 { 0x06, 0xffff, 0x5881 },
3186                 { 0x04, 0xffff, 0x854a },
3187                 { 0x01, 0xffff, 0x068b }
3188         };
3189         int rg_saw_cnt;
3190
3191         /* disable aspm and clock request before access ephy */
3192         rtl_hw_aspm_clkreq_enable(tp, false);
3193         rtl_ephy_init(tp, e_info_8168h_1);
3194
3195         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3196         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3197
3198         rtl_set_def_aspm_entry_latency(tp);
3199
3200         rtl_reset_packet_filter(tp);
3201
3202         rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3203         rtl_eri_set_bits(tp, 0xdc, 0x001c);
3204
3205         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3206
3207         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3208
3209         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3210         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3211
3212         rtl8168_config_eee_mac(tp);
3213
3214         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3215         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3216
3217         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3218
3219         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3220
3221         rtl_pcie_state_l2l3_disable(tp);
3222
3223         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3224         if (rg_saw_cnt > 0) {
3225                 u16 sw_cnt_1ms_ini;
3226
3227                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3228                 sw_cnt_1ms_ini &= 0x0fff;
3229                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3230         }
3231
3232         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3233         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3234         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3235         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3236
3237         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3238         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3239         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3240         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3241
3242         rtl_hw_aspm_clkreq_enable(tp, true);
3243 }
3244
3245 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3246 {
3247         rtl8168ep_stop_cmac(tp);
3248
3249         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3250         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3251
3252         rtl_set_def_aspm_entry_latency(tp);
3253
3254         rtl_reset_packet_filter(tp);
3255
3256         rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3257
3258         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3259
3260         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3261
3262         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3263         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3264
3265         rtl8168_config_eee_mac(tp);
3266
3267         rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3268
3269         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3270
3271         rtl_pcie_state_l2l3_disable(tp);
3272 }
3273
3274 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3275 {
3276         static const struct ephy_info e_info_8168ep_1[] = {
3277                 { 0x00, 0xffff, 0x10ab },
3278                 { 0x06, 0xffff, 0xf030 },
3279                 { 0x08, 0xffff, 0x2006 },
3280                 { 0x0d, 0xffff, 0x1666 },
3281                 { 0x0c, 0x3ff0, 0x0000 }
3282         };
3283
3284         /* disable aspm and clock request before access ephy */
3285         rtl_hw_aspm_clkreq_enable(tp, false);
3286         rtl_ephy_init(tp, e_info_8168ep_1);
3287
3288         rtl_hw_start_8168ep(tp);
3289
3290         rtl_hw_aspm_clkreq_enable(tp, true);
3291 }
3292
3293 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3294 {
3295         static const struct ephy_info e_info_8168ep_2[] = {
3296                 { 0x00, 0xffff, 0x10a3 },
3297                 { 0x19, 0xffff, 0xfc00 },
3298                 { 0x1e, 0xffff, 0x20ea }
3299         };
3300
3301         /* disable aspm and clock request before access ephy */
3302         rtl_hw_aspm_clkreq_enable(tp, false);
3303         rtl_ephy_init(tp, e_info_8168ep_2);
3304
3305         rtl_hw_start_8168ep(tp);
3306
3307         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3308         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3309
3310         rtl_hw_aspm_clkreq_enable(tp, true);
3311 }
3312
3313 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3314 {
3315         static const struct ephy_info e_info_8168ep_3[] = {
3316                 { 0x00, 0x0000, 0x0080 },
3317                 { 0x0d, 0x0100, 0x0200 },
3318                 { 0x19, 0x8021, 0x0000 },
3319                 { 0x1e, 0x0000, 0x2000 },
3320         };
3321
3322         /* disable aspm and clock request before access ephy */
3323         rtl_hw_aspm_clkreq_enable(tp, false);
3324         rtl_ephy_init(tp, e_info_8168ep_3);
3325
3326         rtl_hw_start_8168ep(tp);
3327
3328         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3329         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3330
3331         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3332         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3333         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3334
3335         rtl_hw_aspm_clkreq_enable(tp, true);
3336 }
3337
3338 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3339 {
3340         static const struct ephy_info e_info_8117[] = {
3341                 { 0x19, 0x0040, 0x1100 },
3342                 { 0x59, 0x0040, 0x1100 },
3343         };
3344         int rg_saw_cnt;
3345
3346         rtl8168ep_stop_cmac(tp);
3347
3348         /* disable aspm and clock request before access ephy */
3349         rtl_hw_aspm_clkreq_enable(tp, false);
3350         rtl_ephy_init(tp, e_info_8117);
3351
3352         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3353         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3354
3355         rtl_set_def_aspm_entry_latency(tp);
3356
3357         rtl_reset_packet_filter(tp);
3358
3359         rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3360
3361         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3362
3363         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3364
3365         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3366         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3367
3368         rtl8168_config_eee_mac(tp);
3369
3370         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3371         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3372
3373         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3374
3375         rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3376
3377         rtl_pcie_state_l2l3_disable(tp);
3378
3379         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3380         if (rg_saw_cnt > 0) {
3381                 u16 sw_cnt_1ms_ini;
3382
3383                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3384                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3385         }
3386
3387         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3388         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3389         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3390         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3391
3392         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3393         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3394         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3395         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3396
3397         /* firmware is for MAC only */
3398         r8169_apply_firmware(tp);
3399
3400         rtl_hw_aspm_clkreq_enable(tp, true);
3401 }
3402
3403 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3404 {
3405         static const struct ephy_info e_info_8102e_1[] = {
3406                 { 0x01, 0, 0x6e65 },
3407                 { 0x02, 0, 0x091f },
3408                 { 0x03, 0, 0xc2f9 },
3409                 { 0x06, 0, 0xafb5 },
3410                 { 0x07, 0, 0x0e00 },
3411                 { 0x19, 0, 0xec80 },
3412                 { 0x01, 0, 0x2e65 },
3413                 { 0x01, 0, 0x6e65 }
3414         };
3415         u8 cfg1;
3416
3417         rtl_set_def_aspm_entry_latency(tp);
3418
3419         RTL_W8(tp, DBG_REG, FIX_NAK_1);
3420
3421         RTL_W8(tp, Config1,
3422                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3423         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3424
3425         cfg1 = RTL_R8(tp, Config1);
3426         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3427                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3428
3429         rtl_ephy_init(tp, e_info_8102e_1);
3430 }
3431
3432 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3433 {
3434         rtl_set_def_aspm_entry_latency(tp);
3435
3436         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3437         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3438 }
3439
3440 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3441 {
3442         rtl_hw_start_8102e_2(tp);
3443
3444         rtl_ephy_write(tp, 0x03, 0xc2f9);
3445 }
3446
3447 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3448 {
3449         static const struct ephy_info e_info_8401[] = {
3450                 { 0x01, 0xffff, 0x6fe5 },
3451                 { 0x03, 0xffff, 0x0599 },
3452                 { 0x06, 0xffff, 0xaf25 },
3453                 { 0x07, 0xffff, 0x8e68 },
3454         };
3455
3456         rtl_ephy_init(tp, e_info_8401);
3457         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3458 }
3459
3460 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3461 {
3462         static const struct ephy_info e_info_8105e_1[] = {
3463                 { 0x07, 0, 0x4000 },
3464                 { 0x19, 0, 0x0200 },
3465                 { 0x19, 0, 0x0020 },
3466                 { 0x1e, 0, 0x2000 },
3467                 { 0x03, 0, 0x0001 },
3468                 { 0x19, 0, 0x0100 },
3469                 { 0x19, 0, 0x0004 },
3470                 { 0x0a, 0, 0x0020 }
3471         };
3472
3473         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3474         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3475
3476         /* Disable Early Tally Counter */
3477         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3478
3479         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3480         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3481
3482         rtl_ephy_init(tp, e_info_8105e_1);
3483
3484         rtl_pcie_state_l2l3_disable(tp);
3485 }
3486
3487 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3488 {
3489         rtl_hw_start_8105e_1(tp);
3490         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3491 }
3492
3493 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3494 {
3495         static const struct ephy_info e_info_8402[] = {
3496                 { 0x19, 0xffff, 0xff64 },
3497                 { 0x1e, 0, 0x4000 }
3498         };
3499
3500         rtl_set_def_aspm_entry_latency(tp);
3501
3502         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3503         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3504
3505         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3506
3507         rtl_ephy_init(tp, e_info_8402);
3508
3509         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3510         rtl_reset_packet_filter(tp);
3511         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3512         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3513         rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3514
3515         /* disable EEE */
3516         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3517
3518         rtl_pcie_state_l2l3_disable(tp);
3519 }
3520
3521 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3522 {
3523         rtl_hw_aspm_clkreq_enable(tp, false);
3524
3525         /* Force LAN exit from ASPM if Rx/Tx are not idle */
3526         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3527
3528         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3529         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3530         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3531
3532         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3533
3534         /* disable EEE */
3535         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3536
3537         rtl_pcie_state_l2l3_disable(tp);
3538         rtl_hw_aspm_clkreq_enable(tp, true);
3539 }
3540
3541 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3542 {
3543         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3544 }
3545
3546 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3547 {
3548         rtl_pcie_state_l2l3_disable(tp);
3549
3550         RTL_W16(tp, 0x382, 0x221b);
3551         RTL_W8(tp, 0x4500, 0);
3552         RTL_W16(tp, 0x4800, 0);
3553
3554         /* disable UPS */
3555         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3556
3557         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3558
3559         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3560         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3561
3562         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3563         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3564         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3565
3566         /* disable new tx descriptor format */
3567         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3568
3569         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3570                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3571         else
3572                 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3573
3574         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3575                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3576         else
3577                 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3578
3579         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3580         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3581         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3582         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3583         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3584         r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3585         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3586         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3587         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3588         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3589
3590         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3591         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3592         udelay(1);
3593         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3594         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3595
3596         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3597
3598         rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3599
3600         if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3601                 rtl8125b_config_eee_mac(tp);
3602         else
3603                 rtl8125a_config_eee_mac(tp);
3604
3605         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3606         udelay(10);
3607 }
3608
3609 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3610 {
3611         static const struct ephy_info e_info_8125a_1[] = {
3612                 { 0x01, 0xffff, 0xa812 },
3613                 { 0x09, 0xffff, 0x520c },
3614                 { 0x04, 0xffff, 0xd000 },
3615                 { 0x0d, 0xffff, 0xf702 },
3616                 { 0x0a, 0xffff, 0x8653 },
3617                 { 0x06, 0xffff, 0x001e },
3618                 { 0x08, 0xffff, 0x3595 },
3619                 { 0x20, 0xffff, 0x9455 },
3620                 { 0x21, 0xffff, 0x99ff },
3621                 { 0x02, 0xffff, 0x6046 },
3622                 { 0x29, 0xffff, 0xfe00 },
3623                 { 0x23, 0xffff, 0xab62 },
3624
3625                 { 0x41, 0xffff, 0xa80c },
3626                 { 0x49, 0xffff, 0x520c },
3627                 { 0x44, 0xffff, 0xd000 },
3628                 { 0x4d, 0xffff, 0xf702 },
3629                 { 0x4a, 0xffff, 0x8653 },
3630                 { 0x46, 0xffff, 0x001e },
3631                 { 0x48, 0xffff, 0x3595 },
3632                 { 0x60, 0xffff, 0x9455 },
3633                 { 0x61, 0xffff, 0x99ff },
3634                 { 0x42, 0xffff, 0x6046 },
3635                 { 0x69, 0xffff, 0xfe00 },
3636                 { 0x63, 0xffff, 0xab62 },
3637         };
3638
3639         rtl_set_def_aspm_entry_latency(tp);
3640
3641         /* disable aspm and clock request before access ephy */
3642         rtl_hw_aspm_clkreq_enable(tp, false);
3643         rtl_ephy_init(tp, e_info_8125a_1);
3644
3645         rtl_hw_start_8125_common(tp);
3646         rtl_hw_aspm_clkreq_enable(tp, true);
3647 }
3648
3649 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3650 {
3651         static const struct ephy_info e_info_8125a_2[] = {
3652                 { 0x04, 0xffff, 0xd000 },
3653                 { 0x0a, 0xffff, 0x8653 },
3654                 { 0x23, 0xffff, 0xab66 },
3655                 { 0x20, 0xffff, 0x9455 },
3656                 { 0x21, 0xffff, 0x99ff },
3657                 { 0x29, 0xffff, 0xfe04 },
3658
3659                 { 0x44, 0xffff, 0xd000 },
3660                 { 0x4a, 0xffff, 0x8653 },
3661                 { 0x63, 0xffff, 0xab66 },
3662                 { 0x60, 0xffff, 0x9455 },
3663                 { 0x61, 0xffff, 0x99ff },
3664                 { 0x69, 0xffff, 0xfe04 },
3665         };
3666
3667         rtl_set_def_aspm_entry_latency(tp);
3668
3669         /* disable aspm and clock request before access ephy */
3670         rtl_hw_aspm_clkreq_enable(tp, false);
3671         rtl_ephy_init(tp, e_info_8125a_2);
3672
3673         rtl_hw_start_8125_common(tp);
3674         rtl_hw_aspm_clkreq_enable(tp, true);
3675 }
3676
3677 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3678 {
3679         static const struct ephy_info e_info_8125b[] = {
3680                 { 0x0b, 0xffff, 0xa908 },
3681                 { 0x1e, 0xffff, 0x20eb },
3682                 { 0x4b, 0xffff, 0xa908 },
3683                 { 0x5e, 0xffff, 0x20eb },
3684                 { 0x22, 0x0030, 0x0020 },
3685                 { 0x62, 0x0030, 0x0020 },
3686         };
3687
3688         rtl_set_def_aspm_entry_latency(tp);
3689         rtl_hw_aspm_clkreq_enable(tp, false);
3690
3691         rtl_ephy_init(tp, e_info_8125b);
3692         rtl_hw_start_8125_common(tp);
3693
3694         rtl_hw_aspm_clkreq_enable(tp, true);
3695 }
3696
3697 static void rtl_hw_config(struct rtl8169_private *tp)
3698 {
3699         static const rtl_generic_fct hw_configs[] = {
3700                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3701                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3702                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3703                 [RTL_GIGA_MAC_VER_10] = NULL,
3704                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3705                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3706                 [RTL_GIGA_MAC_VER_13] = NULL,
3707                 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3708                 [RTL_GIGA_MAC_VER_16] = NULL,
3709                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3710                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3711                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3712                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3713                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3714                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3715                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3716                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3717                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3718                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3719                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3720                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3721                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3722                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3723                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3724                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3725                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3726                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3727                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3728                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3729                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3730                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3731                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3732                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3733                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3734                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3735                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3736                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3737                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3738                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3739                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3740                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3741                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3742                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3743                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3744                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3745                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3746                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3747                 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3748         };
3749
3750         if (hw_configs[tp->mac_version])
3751                 hw_configs[tp->mac_version](tp);
3752 }
3753
3754 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3755 {
3756         int i;
3757
3758         /* disable interrupt coalescing */
3759         for (i = 0xa00; i < 0xb00; i += 4)
3760                 RTL_W32(tp, i, 0);
3761
3762         rtl_hw_config(tp);
3763 }
3764
3765 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3766 {
3767         if (rtl_is_8168evl_up(tp))
3768                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3769         else
3770                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3771
3772         rtl_hw_config(tp);
3773
3774         /* disable interrupt coalescing */
3775         RTL_W16(tp, IntrMitigate, 0x0000);
3776 }
3777
3778 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3779 {
3780         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3781
3782         tp->cp_cmd |= PCIMulRW;
3783
3784         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3785             tp->mac_version == RTL_GIGA_MAC_VER_03)
3786                 tp->cp_cmd |= EnAnaPLL;
3787
3788         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3789
3790         rtl8169_set_magic_reg(tp);
3791
3792         /* disable interrupt coalescing */
3793         RTL_W16(tp, IntrMitigate, 0x0000);
3794 }
3795
3796 static void rtl_hw_start(struct  rtl8169_private *tp)
3797 {
3798         rtl_unlock_config_regs(tp);
3799
3800         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3801
3802         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3803                 rtl_hw_start_8169(tp);
3804         else if (rtl_is_8125(tp))
3805                 rtl_hw_start_8125(tp);
3806         else
3807                 rtl_hw_start_8168(tp);
3808
3809         rtl_set_rx_max_size(tp);
3810         rtl_set_rx_tx_desc_registers(tp);
3811         rtl_lock_config_regs(tp);
3812
3813         rtl_jumbo_config(tp);
3814
3815         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3816         rtl_pci_commit(tp);
3817
3818         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3819         rtl_init_rxcfg(tp);
3820         rtl_set_tx_config_registers(tp);
3821         rtl_set_rx_config_features(tp, tp->dev->features);
3822         rtl_set_rx_mode(tp->dev);
3823         rtl_irq_enable(tp);
3824 }
3825
3826 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3827 {
3828         struct rtl8169_private *tp = netdev_priv(dev);
3829
3830         dev->mtu = new_mtu;
3831         netdev_update_features(dev);
3832         rtl_jumbo_config(tp);
3833
3834         switch (tp->mac_version) {
3835         case RTL_GIGA_MAC_VER_61:
3836         case RTL_GIGA_MAC_VER_63:
3837                 rtl8125_set_eee_txidle_timer(tp);
3838                 break;
3839         default:
3840                 break;
3841         }
3842
3843         return 0;
3844 }
3845
3846 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3847 {
3848         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3849
3850         desc->opts2 = 0;
3851         /* Force memory writes to complete before releasing descriptor */
3852         dma_wmb();
3853         WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3854 }
3855
3856 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3857                                           struct RxDesc *desc)
3858 {
3859         struct device *d = tp_to_dev(tp);
3860         int node = dev_to_node(d);
3861         dma_addr_t mapping;
3862         struct page *data;
3863
3864         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3865         if (!data)
3866                 return NULL;
3867
3868         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3869         if (unlikely(dma_mapping_error(d, mapping))) {
3870                 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3871                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3872                 return NULL;
3873         }
3874
3875         desc->addr = cpu_to_le64(mapping);
3876         rtl8169_mark_to_asic(desc);
3877
3878         return data;
3879 }
3880
3881 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3882 {
3883         unsigned int i;
3884
3885         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3886                 dma_unmap_page(tp_to_dev(tp),
3887                                le64_to_cpu(tp->RxDescArray[i].addr),
3888                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3889                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3890                 tp->Rx_databuff[i] = NULL;
3891                 tp->RxDescArray[i].addr = 0;
3892                 tp->RxDescArray[i].opts1 = 0;
3893         }
3894 }
3895
3896 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3897 {
3898         unsigned int i;
3899
3900         for (i = 0; i < NUM_RX_DESC; i++) {
3901                 struct page *data;
3902
3903                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3904                 if (!data) {
3905                         rtl8169_rx_clear(tp);
3906                         return -ENOMEM;
3907                 }
3908                 tp->Rx_databuff[i] = data;
3909         }
3910
3911         /* mark as last descriptor in the ring */
3912         tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3913
3914         return 0;
3915 }
3916
3917 static int rtl8169_init_ring(struct rtl8169_private *tp)
3918 {
3919         rtl8169_init_ring_indexes(tp);
3920
3921         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3922         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3923
3924         return rtl8169_rx_fill(tp);
3925 }
3926
3927 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3928 {
3929         struct ring_info *tx_skb = tp->tx_skb + entry;
3930         struct TxDesc *desc = tp->TxDescArray + entry;
3931
3932         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3933                          DMA_TO_DEVICE);
3934         memset(desc, 0, sizeof(*desc));
3935         memset(tx_skb, 0, sizeof(*tx_skb));
3936 }
3937
3938 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3939                                    unsigned int n)
3940 {
3941         unsigned int i;
3942
3943         for (i = 0; i < n; i++) {
3944                 unsigned int entry = (start + i) % NUM_TX_DESC;
3945                 struct ring_info *tx_skb = tp->tx_skb + entry;
3946                 unsigned int len = tx_skb->len;
3947
3948                 if (len) {
3949                         struct sk_buff *skb = tx_skb->skb;
3950
3951                         rtl8169_unmap_tx_skb(tp, entry);
3952                         if (skb)
3953                                 dev_consume_skb_any(skb);
3954                 }
3955         }
3956 }
3957
3958 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3959 {
3960         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3961         netdev_reset_queue(tp->dev);
3962 }
3963
3964 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3965 {
3966         napi_disable(&tp->napi);
3967
3968         /* Give a racing hard_start_xmit a few cycles to complete. */
3969         synchronize_net();
3970
3971         /* Disable interrupts */
3972         rtl8169_irq_mask_and_ack(tp);
3973
3974         rtl_rx_close(tp);
3975
3976         if (going_down && tp->dev->wol_enabled)
3977                 goto no_reset;
3978
3979         switch (tp->mac_version) {
3980         case RTL_GIGA_MAC_VER_27:
3981         case RTL_GIGA_MAC_VER_28:
3982         case RTL_GIGA_MAC_VER_31:
3983                 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3984                 break;
3985         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3986                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3987                 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3988                 break;
3989         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3990                 rtl_enable_rxdvgate(tp);
3991                 fsleep(2000);
3992                 break;
3993         default:
3994                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3995                 fsleep(100);
3996                 break;
3997         }
3998
3999         rtl_hw_reset(tp);
4000 no_reset:
4001         rtl8169_tx_clear(tp);
4002         rtl8169_init_ring_indexes(tp);
4003 }
4004
4005 static void rtl_reset_work(struct rtl8169_private *tp)
4006 {
4007         int i;
4008
4009         netif_stop_queue(tp->dev);
4010
4011         rtl8169_cleanup(tp, false);
4012
4013         for (i = 0; i < NUM_RX_DESC; i++)
4014                 rtl8169_mark_to_asic(tp->RxDescArray + i);
4015
4016         napi_enable(&tp->napi);
4017         rtl_hw_start(tp);
4018 }
4019
4020 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4021 {
4022         struct rtl8169_private *tp = netdev_priv(dev);
4023
4024         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4025 }
4026
4027 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4028                           void *addr, unsigned int entry, bool desc_own)
4029 {
4030         struct TxDesc *txd = tp->TxDescArray + entry;
4031         struct device *d = tp_to_dev(tp);
4032         dma_addr_t mapping;
4033         u32 opts1;
4034         int ret;
4035
4036         mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4037         ret = dma_mapping_error(d, mapping);
4038         if (unlikely(ret)) {
4039                 if (net_ratelimit())
4040                         netdev_err(tp->dev, "Failed to map TX data!\n");
4041                 return ret;
4042         }
4043
4044         txd->addr = cpu_to_le64(mapping);
4045         txd->opts2 = cpu_to_le32(opts[1]);
4046
4047         opts1 = opts[0] | len;
4048         if (entry == NUM_TX_DESC - 1)
4049                 opts1 |= RingEnd;
4050         if (desc_own)
4051                 opts1 |= DescOwn;
4052         txd->opts1 = cpu_to_le32(opts1);
4053
4054         tp->tx_skb[entry].len = len;
4055
4056         return 0;
4057 }
4058
4059 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4060                               const u32 *opts, unsigned int entry)
4061 {
4062         struct skb_shared_info *info = skb_shinfo(skb);
4063         unsigned int cur_frag;
4064
4065         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4066                 const skb_frag_t *frag = info->frags + cur_frag;
4067                 void *addr = skb_frag_address(frag);
4068                 u32 len = skb_frag_size(frag);
4069
4070                 entry = (entry + 1) % NUM_TX_DESC;
4071
4072                 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4073                         goto err_out;
4074         }
4075
4076         return 0;
4077
4078 err_out:
4079         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4080         return -EIO;
4081 }
4082
4083 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4084 {
4085         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4086 }
4087
4088 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4089 {
4090         u32 mss = skb_shinfo(skb)->gso_size;
4091
4092         if (mss) {
4093                 opts[0] |= TD_LSO;
4094                 opts[0] |= mss << TD0_MSS_SHIFT;
4095         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4096                 const struct iphdr *ip = ip_hdr(skb);
4097
4098                 if (ip->protocol == IPPROTO_TCP)
4099                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4100                 else if (ip->protocol == IPPROTO_UDP)
4101                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4102                 else
4103                         WARN_ON_ONCE(1);
4104         }
4105 }
4106
4107 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4108                                 struct sk_buff *skb, u32 *opts)
4109 {
4110         u32 transport_offset = (u32)skb_transport_offset(skb);
4111         struct skb_shared_info *shinfo = skb_shinfo(skb);
4112         u32 mss = shinfo->gso_size;
4113
4114         if (mss) {
4115                 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4116                         opts[0] |= TD1_GTSENV4;
4117                 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4118                         if (skb_cow_head(skb, 0))
4119                                 return false;
4120
4121                         tcp_v6_gso_csum_prep(skb);
4122                         opts[0] |= TD1_GTSENV6;
4123                 } else {
4124                         WARN_ON_ONCE(1);
4125                 }
4126
4127                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4128                 opts[1] |= mss << TD1_MSS_SHIFT;
4129         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4130                 u8 ip_protocol;
4131
4132                 switch (vlan_get_protocol(skb)) {
4133                 case htons(ETH_P_IP):
4134                         opts[1] |= TD1_IPv4_CS;
4135                         ip_protocol = ip_hdr(skb)->protocol;
4136                         break;
4137
4138                 case htons(ETH_P_IPV6):
4139                         opts[1] |= TD1_IPv6_CS;
4140                         ip_protocol = ipv6_hdr(skb)->nexthdr;
4141                         break;
4142
4143                 default:
4144                         ip_protocol = IPPROTO_RAW;
4145                         break;
4146                 }
4147
4148                 if (ip_protocol == IPPROTO_TCP)
4149                         opts[1] |= TD1_TCP_CS;
4150                 else if (ip_protocol == IPPROTO_UDP)
4151                         opts[1] |= TD1_UDP_CS;
4152                 else
4153                         WARN_ON_ONCE(1);
4154
4155                 opts[1] |= transport_offset << TCPHO_SHIFT;
4156         } else {
4157                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4158                         return !eth_skb_pad(skb);
4159         }
4160
4161         return true;
4162 }
4163
4164 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4165                                unsigned int nr_frags)
4166 {
4167         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4168
4169         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4170         return slots_avail > nr_frags;
4171 }
4172
4173 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4174 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4175 {
4176         switch (tp->mac_version) {
4177         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4178         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4179                 return false;
4180         default:
4181                 return true;
4182         }
4183 }
4184
4185 static void rtl8169_doorbell(struct rtl8169_private *tp)
4186 {
4187         if (rtl_is_8125(tp))
4188                 RTL_W16(tp, TxPoll_8125, BIT(0));
4189         else
4190                 RTL_W8(tp, TxPoll, NPQ);
4191 }
4192
4193 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4194                                       struct net_device *dev)
4195 {
4196         unsigned int frags = skb_shinfo(skb)->nr_frags;
4197         struct rtl8169_private *tp = netdev_priv(dev);
4198         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4199         struct TxDesc *txd_first, *txd_last;
4200         bool stop_queue, door_bell;
4201         u32 opts[2];
4202
4203         txd_first = tp->TxDescArray + entry;
4204
4205         if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4206                 if (net_ratelimit())
4207                         netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4208                 goto err_stop_0;
4209         }
4210
4211         if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4212                 goto err_stop_0;
4213
4214         opts[1] = rtl8169_tx_vlan_tag(skb);
4215         opts[0] = 0;
4216
4217         if (!rtl_chip_supports_csum_v2(tp))
4218                 rtl8169_tso_csum_v1(skb, opts);
4219         else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4220                 goto err_dma_0;
4221
4222         if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4223                                     entry, false)))
4224                 goto err_dma_0;
4225
4226         if (frags) {
4227                 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4228                         goto err_dma_1;
4229                 entry = (entry + frags) % NUM_TX_DESC;
4230         }
4231
4232         txd_last = tp->TxDescArray + entry;
4233         txd_last->opts1 |= cpu_to_le32(LastFrag);
4234         tp->tx_skb[entry].skb = skb;
4235
4236         skb_tx_timestamp(skb);
4237
4238         /* Force memory writes to complete before releasing descriptor */
4239         dma_wmb();
4240
4241         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4242
4243         txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4244
4245         /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4246         smp_wmb();
4247
4248         tp->cur_tx += frags + 1;
4249
4250         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4251         if (unlikely(stop_queue)) {
4252                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4253                  * not miss a ring update when it notices a stopped queue.
4254                  */
4255                 smp_wmb();
4256                 netif_stop_queue(dev);
4257                 door_bell = true;
4258         }
4259
4260         if (door_bell)
4261                 rtl8169_doorbell(tp);
4262
4263         if (unlikely(stop_queue)) {
4264                 /* Sync with rtl_tx:
4265                  * - publish queue status and cur_tx ring index (write barrier)
4266                  * - refresh dirty_tx ring index (read barrier).
4267                  * May the current thread have a pessimistic view of the ring
4268                  * status and forget to wake up queue, a racing rtl_tx thread
4269                  * can't.
4270                  */
4271                 smp_mb();
4272                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4273                         netif_start_queue(dev);
4274         }
4275
4276         return NETDEV_TX_OK;
4277
4278 err_dma_1:
4279         rtl8169_unmap_tx_skb(tp, entry);
4280 err_dma_0:
4281         dev_kfree_skb_any(skb);
4282         dev->stats.tx_dropped++;
4283         return NETDEV_TX_OK;
4284
4285 err_stop_0:
4286         netif_stop_queue(dev);
4287         dev->stats.tx_dropped++;
4288         return NETDEV_TX_BUSY;
4289 }
4290
4291 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4292 {
4293         struct skb_shared_info *info = skb_shinfo(skb);
4294         unsigned int nr_frags = info->nr_frags;
4295
4296         if (!nr_frags)
4297                 return UINT_MAX;
4298
4299         return skb_frag_size(info->frags + nr_frags - 1);
4300 }
4301
4302 /* Workaround for hw issues with TSO on RTL8168evl */
4303 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4304                                             netdev_features_t features)
4305 {
4306         /* IPv4 header has options field */
4307         if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4308             ip_hdrlen(skb) > sizeof(struct iphdr))
4309                 features &= ~NETIF_F_ALL_TSO;
4310
4311         /* IPv4 TCP header has options field */
4312         else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4313                  tcp_hdrlen(skb) > sizeof(struct tcphdr))
4314                 features &= ~NETIF_F_ALL_TSO;
4315
4316         else if (rtl_last_frag_len(skb) <= 6)
4317                 features &= ~NETIF_F_ALL_TSO;
4318
4319         return features;
4320 }
4321
4322 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4323                                                 struct net_device *dev,
4324                                                 netdev_features_t features)
4325 {
4326         int transport_offset = skb_transport_offset(skb);
4327         struct rtl8169_private *tp = netdev_priv(dev);
4328
4329         if (skb_is_gso(skb)) {
4330                 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4331                         features = rtl8168evl_fix_tso(skb, features);
4332
4333                 if (transport_offset > GTTCPHO_MAX &&
4334                     rtl_chip_supports_csum_v2(tp))
4335                         features &= ~NETIF_F_ALL_TSO;
4336         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4337                 if (skb->len < ETH_ZLEN) {
4338                         switch (tp->mac_version) {
4339                         case RTL_GIGA_MAC_VER_11:
4340                         case RTL_GIGA_MAC_VER_12:
4341                         case RTL_GIGA_MAC_VER_17:
4342                         case RTL_GIGA_MAC_VER_34:
4343                                 features &= ~NETIF_F_CSUM_MASK;
4344                                 break;
4345                         default:
4346                                 break;
4347                         }
4348                 }
4349
4350                 if (transport_offset > TCPHO_MAX &&
4351                     rtl_chip_supports_csum_v2(tp))
4352                         features &= ~NETIF_F_CSUM_MASK;
4353         }
4354
4355         return vlan_features_check(skb, features);
4356 }
4357
4358 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4359 {
4360         struct rtl8169_private *tp = netdev_priv(dev);
4361         struct pci_dev *pdev = tp->pci_dev;
4362         int pci_status_errs;
4363         u16 pci_cmd;
4364
4365         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4366
4367         pci_status_errs = pci_status_get_and_clear_errors(pdev);
4368
4369         if (net_ratelimit())
4370                 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4371                            pci_cmd, pci_status_errs);
4372         /*
4373          * The recovery sequence below admits a very elaborated explanation:
4374          * - it seems to work;
4375          * - I did not see what else could be done;
4376          * - it makes iop3xx happy.
4377          *
4378          * Feel free to adjust to your needs.
4379          */
4380         if (pdev->broken_parity_status)
4381                 pci_cmd &= ~PCI_COMMAND_PARITY;
4382         else
4383                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4384
4385         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4386
4387         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4388 }
4389
4390 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4391                    int budget)
4392 {
4393         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4394
4395         dirty_tx = tp->dirty_tx;
4396         smp_rmb();
4397
4398         for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4399                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4400                 struct sk_buff *skb = tp->tx_skb[entry].skb;
4401                 u32 status;
4402
4403                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4404                 if (status & DescOwn)
4405                         break;
4406
4407                 rtl8169_unmap_tx_skb(tp, entry);
4408
4409                 if (skb) {
4410                         pkts_compl++;
4411                         bytes_compl += skb->len;
4412                         napi_consume_skb(skb, budget);
4413                 }
4414                 dirty_tx++;
4415         }
4416
4417         if (tp->dirty_tx != dirty_tx) {
4418                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4419
4420                 rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);
4421
4422                 tp->dirty_tx = dirty_tx;
4423                 /* Sync with rtl8169_start_xmit:
4424                  * - publish dirty_tx ring index (write barrier)
4425                  * - refresh cur_tx ring index and queue status (read barrier)
4426                  * May the current thread miss the stopped queue condition,
4427                  * a racing xmit thread can only have a right view of the
4428                  * ring status.
4429                  */
4430                 smp_mb();
4431                 if (netif_queue_stopped(dev) &&
4432                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4433                         netif_wake_queue(dev);
4434                 }
4435                 /*
4436                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4437                  * too close. Let's kick an extra TxPoll request when a burst
4438                  * of start_xmit activity is detected (if it is not detected,
4439                  * it is slow enough). -- FR
4440                  */
4441                 if (tp->cur_tx != dirty_tx)
4442                         rtl8169_doorbell(tp);
4443         }
4444 }
4445
4446 static inline int rtl8169_fragmented_frame(u32 status)
4447 {
4448         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4449 }
4450
4451 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4452 {
4453         u32 status = opts1 & RxProtoMask;
4454
4455         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4456             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4457                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4458         else
4459                 skb_checksum_none_assert(skb);
4460 }
4461
4462 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4463 {
4464         unsigned int cur_rx, rx_left, count;
4465         struct device *d = tp_to_dev(tp);
4466
4467         cur_rx = tp->cur_rx;
4468
4469         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4470                 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4471                 struct RxDesc *desc = tp->RxDescArray + entry;
4472                 struct sk_buff *skb;
4473                 const void *rx_buf;
4474                 dma_addr_t addr;
4475                 u32 status;
4476
4477                 status = le32_to_cpu(desc->opts1);
4478                 if (status & DescOwn)
4479                         break;
4480
4481                 /* This barrier is needed to keep us from reading
4482                  * any other fields out of the Rx descriptor until
4483                  * we know the status of DescOwn
4484                  */
4485                 dma_rmb();
4486
4487                 if (unlikely(status & RxRES)) {
4488                         if (net_ratelimit())
4489                                 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4490                                             status);
4491                         dev->stats.rx_errors++;
4492                         if (status & (RxRWT | RxRUNT))
4493                                 dev->stats.rx_length_errors++;
4494                         if (status & RxCRC)
4495                                 dev->stats.rx_crc_errors++;
4496
4497                         if (!(dev->features & NETIF_F_RXALL))
4498                                 goto release_descriptor;
4499                         else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4500                                 goto release_descriptor;
4501                 }
4502
4503                 pkt_size = status & GENMASK(13, 0);
4504                 if (likely(!(dev->features & NETIF_F_RXFCS)))
4505                         pkt_size -= ETH_FCS_LEN;
4506
4507                 /* The driver does not support incoming fragmented frames.
4508                  * They are seen as a symptom of over-mtu sized frames.
4509                  */
4510                 if (unlikely(rtl8169_fragmented_frame(status))) {
4511                         dev->stats.rx_dropped++;
4512                         dev->stats.rx_length_errors++;
4513                         goto release_descriptor;
4514                 }
4515
4516                 skb = napi_alloc_skb(&tp->napi, pkt_size);
4517                 if (unlikely(!skb)) {
4518                         dev->stats.rx_dropped++;
4519                         goto release_descriptor;
4520                 }
4521
4522                 addr = le64_to_cpu(desc->addr);
4523                 rx_buf = page_address(tp->Rx_databuff[entry]);
4524
4525                 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4526                 prefetch(rx_buf);
4527                 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4528                 skb->tail += pkt_size;
4529                 skb->len = pkt_size;
4530                 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4531
4532                 rtl8169_rx_csum(skb, status);
4533                 skb->protocol = eth_type_trans(skb, dev);
4534
4535                 rtl8169_rx_vlan_tag(desc, skb);
4536
4537                 if (skb->pkt_type == PACKET_MULTICAST)
4538                         dev->stats.multicast++;
4539
4540                 napi_gro_receive(&tp->napi, skb);
4541
4542                 rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);
4543 release_descriptor:
4544                 rtl8169_mark_to_asic(desc);
4545         }
4546
4547         count = cur_rx - tp->cur_rx;
4548         tp->cur_rx = cur_rx;
4549
4550         return count;
4551 }
4552
4553 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4554 {
4555         struct rtl8169_private *tp = dev_instance;
4556         u32 status = rtl_get_events(tp);
4557
4558         if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4559                 return IRQ_NONE;
4560
4561         if (unlikely(status & SYSErr)) {
4562                 rtl8169_pcierr_interrupt(tp->dev);
4563                 goto out;
4564         }
4565
4566         if (status & LinkChg)
4567                 phy_mac_interrupt(tp->phydev);
4568
4569         if (unlikely(status & RxFIFOOver &&
4570             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4571                 netif_stop_queue(tp->dev);
4572                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4573         }
4574
4575         rtl_irq_disable(tp);
4576         napi_schedule(&tp->napi);
4577 out:
4578         rtl_ack_events(tp, status);
4579
4580         return IRQ_HANDLED;
4581 }
4582
4583 static void rtl_task(struct work_struct *work)
4584 {
4585         struct rtl8169_private *tp =
4586                 container_of(work, struct rtl8169_private, wk.work);
4587
4588         rtnl_lock();
4589
4590         if (!netif_running(tp->dev) ||
4591             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4592                 goto out_unlock;
4593
4594         if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4595                 rtl_reset_work(tp);
4596                 netif_wake_queue(tp->dev);
4597         }
4598 out_unlock:
4599         rtnl_unlock();
4600 }
4601
4602 static int rtl8169_poll(struct napi_struct *napi, int budget)
4603 {
4604         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4605         struct net_device *dev = tp->dev;
4606         int work_done;
4607
4608         work_done = rtl_rx(dev, tp, (u32) budget);
4609
4610         rtl_tx(dev, tp, budget);
4611
4612         if (work_done < budget && napi_complete_done(napi, work_done))
4613                 rtl_irq_enable(tp);
4614
4615         return work_done;
4616 }
4617
4618 static void r8169_phylink_handler(struct net_device *ndev)
4619 {
4620         struct rtl8169_private *tp = netdev_priv(ndev);
4621
4622         if (netif_carrier_ok(ndev)) {
4623                 rtl_link_chg_patch(tp);
4624                 pm_request_resume(&tp->pci_dev->dev);
4625         } else {
4626                 pm_runtime_idle(&tp->pci_dev->dev);
4627         }
4628
4629         if (net_ratelimit())
4630                 phy_print_status(tp->phydev);
4631 }
4632
4633 static int r8169_phy_connect(struct rtl8169_private *tp)
4634 {
4635         struct phy_device *phydev = tp->phydev;
4636         phy_interface_t phy_mode;
4637         int ret;
4638
4639         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4640                    PHY_INTERFACE_MODE_MII;
4641
4642         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4643                                  phy_mode);
4644         if (ret)
4645                 return ret;
4646
4647         if (!tp->supports_gmii)
4648                 phy_set_max_speed(phydev, SPEED_100);
4649
4650         phy_support_asym_pause(phydev);
4651
4652         phy_attached_info(phydev);
4653
4654         return 0;
4655 }
4656
4657 static void rtl8169_down(struct rtl8169_private *tp)
4658 {
4659         /* Clear all task flags */
4660         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4661
4662         phy_stop(tp->phydev);
4663
4664         rtl8169_update_counters(tp);
4665
4666         rtl8169_cleanup(tp, true);
4667
4668         rtl_pll_power_down(tp);
4669 }
4670
4671 static void rtl8169_up(struct rtl8169_private *tp)
4672 {
4673         rtl_pll_power_up(tp);
4674         rtl8169_init_phy(tp);
4675         napi_enable(&tp->napi);
4676         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4677         rtl_reset_work(tp);
4678
4679         phy_start(tp->phydev);
4680 }
4681
4682 static int rtl8169_close(struct net_device *dev)
4683 {
4684         struct rtl8169_private *tp = netdev_priv(dev);
4685         struct pci_dev *pdev = tp->pci_dev;
4686
4687         pm_runtime_get_sync(&pdev->dev);
4688
4689         netif_stop_queue(dev);
4690         rtl8169_down(tp);
4691         rtl8169_rx_clear(tp);
4692
4693         cancel_work_sync(&tp->wk.work);
4694
4695         phy_disconnect(tp->phydev);
4696
4697         free_irq(pci_irq_vector(pdev, 0), tp);
4698
4699         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4700                           tp->RxPhyAddr);
4701         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4702                           tp->TxPhyAddr);
4703         tp->TxDescArray = NULL;
4704         tp->RxDescArray = NULL;
4705
4706         pm_runtime_put_sync(&pdev->dev);
4707
4708         return 0;
4709 }
4710
4711 #ifdef CONFIG_NET_POLL_CONTROLLER
4712 static void rtl8169_netpoll(struct net_device *dev)
4713 {
4714         struct rtl8169_private *tp = netdev_priv(dev);
4715
4716         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4717 }
4718 #endif
4719
4720 static int rtl_open(struct net_device *dev)
4721 {
4722         struct rtl8169_private *tp = netdev_priv(dev);
4723         struct pci_dev *pdev = tp->pci_dev;
4724         int retval = -ENOMEM;
4725
4726         pm_runtime_get_sync(&pdev->dev);
4727
4728         /*
4729          * Rx and Tx descriptors needs 256 bytes alignment.
4730          * dma_alloc_coherent provides more.
4731          */
4732         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4733                                              &tp->TxPhyAddr, GFP_KERNEL);
4734         if (!tp->TxDescArray)
4735                 goto err_pm_runtime_put;
4736
4737         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4738                                              &tp->RxPhyAddr, GFP_KERNEL);
4739         if (!tp->RxDescArray)
4740                 goto err_free_tx_0;
4741
4742         retval = rtl8169_init_ring(tp);
4743         if (retval < 0)
4744                 goto err_free_rx_1;
4745
4746         rtl_request_firmware(tp);
4747
4748         retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4749                              IRQF_SHARED, dev->name, tp);
4750         if (retval < 0)
4751                 goto err_release_fw_2;
4752
4753         retval = r8169_phy_connect(tp);
4754         if (retval)
4755                 goto err_free_irq;
4756
4757         rtl8169_up(tp);
4758         rtl8169_init_counter_offsets(tp);
4759         netif_start_queue(dev);
4760
4761         pm_runtime_put_sync(&pdev->dev);
4762 out:
4763         return retval;
4764
4765 err_free_irq:
4766         free_irq(pci_irq_vector(pdev, 0), tp);
4767 err_release_fw_2:
4768         rtl_release_firmware(tp);
4769         rtl8169_rx_clear(tp);
4770 err_free_rx_1:
4771         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4772                           tp->RxPhyAddr);
4773         tp->RxDescArray = NULL;
4774 err_free_tx_0:
4775         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4776                           tp->TxPhyAddr);
4777         tp->TxDescArray = NULL;
4778 err_pm_runtime_put:
4779         pm_runtime_put_noidle(&pdev->dev);
4780         goto out;
4781 }
4782
4783 static void
4784 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4785 {
4786         struct rtl8169_private *tp = netdev_priv(dev);
4787         struct pci_dev *pdev = tp->pci_dev;
4788         struct rtl8169_counters *counters = tp->counters;
4789
4790         pm_runtime_get_noresume(&pdev->dev);
4791
4792         netdev_stats_to_stats64(stats, &dev->stats);
4793
4794         rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);
4795         rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);
4796
4797         /*
4798          * Fetch additional counter values missing in stats collected by driver
4799          * from tally counters.
4800          */
4801         if (pm_runtime_active(&pdev->dev))
4802                 rtl8169_update_counters(tp);
4803
4804         /*
4805          * Subtract values fetched during initalization.
4806          * See rtl8169_init_counter_offsets for a description why we do that.
4807          */
4808         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4809                 le64_to_cpu(tp->tc_offset.tx_errors);
4810         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4811                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4812         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4813                 le16_to_cpu(tp->tc_offset.tx_aborted);
4814         stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4815                 le16_to_cpu(tp->tc_offset.rx_missed);
4816
4817         pm_runtime_put_noidle(&pdev->dev);
4818 }
4819
4820 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4821 {
4822         netif_device_detach(tp->dev);
4823
4824         if (netif_running(tp->dev))
4825                 rtl8169_down(tp);
4826 }
4827
4828 #ifdef CONFIG_PM
4829
4830 static int rtl8169_net_resume(struct rtl8169_private *tp)
4831 {
4832         rtl_rar_set(tp, tp->dev->dev_addr);
4833
4834         if (tp->TxDescArray)
4835                 rtl8169_up(tp);
4836
4837         netif_device_attach(tp->dev);
4838
4839         return 0;
4840 }
4841
4842 static int __maybe_unused rtl8169_suspend(struct device *device)
4843 {
4844         struct rtl8169_private *tp = dev_get_drvdata(device);
4845
4846         rtnl_lock();
4847         rtl8169_net_suspend(tp);
4848         if (!device_may_wakeup(tp_to_dev(tp)))
4849                 clk_disable_unprepare(tp->clk);
4850         rtnl_unlock();
4851
4852         return 0;
4853 }
4854
4855 static int __maybe_unused rtl8169_resume(struct device *device)
4856 {
4857         struct rtl8169_private *tp = dev_get_drvdata(device);
4858
4859         if (!device_may_wakeup(tp_to_dev(tp)))
4860                 clk_prepare_enable(tp->clk);
4861
4862         /* Reportedly at least Asus X453MA truncates packets otherwise */
4863         if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4864                 rtl_init_rxcfg(tp);
4865
4866         return rtl8169_net_resume(tp);
4867 }
4868
4869 static int rtl8169_runtime_suspend(struct device *device)
4870 {
4871         struct rtl8169_private *tp = dev_get_drvdata(device);
4872
4873         if (!tp->TxDescArray) {
4874                 netif_device_detach(tp->dev);
4875                 return 0;
4876         }
4877
4878         rtnl_lock();
4879         __rtl8169_set_wol(tp, WAKE_PHY);
4880         rtl8169_net_suspend(tp);
4881         rtnl_unlock();
4882
4883         return 0;
4884 }
4885
4886 static int rtl8169_runtime_resume(struct device *device)
4887 {
4888         struct rtl8169_private *tp = dev_get_drvdata(device);
4889
4890         __rtl8169_set_wol(tp, tp->saved_wolopts);
4891
4892         return rtl8169_net_resume(tp);
4893 }
4894
4895 static int rtl8169_runtime_idle(struct device *device)
4896 {
4897         struct rtl8169_private *tp = dev_get_drvdata(device);
4898
4899         if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4900                 pm_schedule_suspend(device, 10000);
4901
4902         return -EBUSY;
4903 }
4904
4905 static const struct dev_pm_ops rtl8169_pm_ops = {
4906         SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4907         SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4908                            rtl8169_runtime_idle)
4909 };
4910
4911 #endif /* CONFIG_PM */
4912
4913 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4914 {
4915         /* WoL fails with 8168b when the receiver is disabled. */
4916         switch (tp->mac_version) {
4917         case RTL_GIGA_MAC_VER_11:
4918         case RTL_GIGA_MAC_VER_12:
4919         case RTL_GIGA_MAC_VER_17:
4920                 pci_clear_master(tp->pci_dev);
4921
4922                 RTL_W8(tp, ChipCmd, CmdRxEnb);
4923                 rtl_pci_commit(tp);
4924                 break;
4925         default:
4926                 break;
4927         }
4928 }
4929
4930 static void rtl_shutdown(struct pci_dev *pdev)
4931 {
4932         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4933
4934         rtnl_lock();
4935         rtl8169_net_suspend(tp);
4936         rtnl_unlock();
4937
4938         /* Restore original MAC address */
4939         rtl_rar_set(tp, tp->dev->perm_addr);
4940
4941         if (system_state == SYSTEM_POWER_OFF) {
4942                 if (tp->saved_wolopts) {
4943                         rtl_wol_suspend_quirk(tp);
4944                         rtl_wol_shutdown_quirk(tp);
4945                 }
4946
4947                 pci_wake_from_d3(pdev, true);
4948                 pci_set_power_state(pdev, PCI_D3hot);
4949         }
4950 }
4951
4952 static void rtl_remove_one(struct pci_dev *pdev)
4953 {
4954         struct rtl8169_private *tp = pci_get_drvdata(pdev);
4955
4956         if (pci_dev_run_wake(pdev))
4957                 pm_runtime_get_noresume(&pdev->dev);
4958
4959         unregister_netdev(tp->dev);
4960
4961         if (r8168_check_dash(tp))
4962                 rtl8168_driver_stop(tp);
4963
4964         rtl_release_firmware(tp);
4965
4966         /* restore original MAC address */
4967         rtl_rar_set(tp, tp->dev->perm_addr);
4968 }
4969
4970 static const struct net_device_ops rtl_netdev_ops = {
4971         .ndo_open               = rtl_open,
4972         .ndo_stop               = rtl8169_close,
4973         .ndo_get_stats64        = rtl8169_get_stats64,
4974         .ndo_start_xmit         = rtl8169_start_xmit,
4975         .ndo_features_check     = rtl8169_features_check,
4976         .ndo_tx_timeout         = rtl8169_tx_timeout,
4977         .ndo_validate_addr      = eth_validate_addr,
4978         .ndo_change_mtu         = rtl8169_change_mtu,
4979         .ndo_fix_features       = rtl8169_fix_features,
4980         .ndo_set_features       = rtl8169_set_features,
4981         .ndo_set_mac_address    = rtl_set_mac_address,
4982         .ndo_do_ioctl           = phy_do_ioctl_running,
4983         .ndo_set_rx_mode        = rtl_set_rx_mode,
4984 #ifdef CONFIG_NET_POLL_CONTROLLER
4985         .ndo_poll_controller    = rtl8169_netpoll,
4986 #endif
4987
4988 };
4989
4990 static void rtl_set_irq_mask(struct rtl8169_private *tp)
4991 {
4992         tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4993
4994         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4995                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4996         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4997                 /* special workaround needed */
4998                 tp->irq_mask |= RxFIFOOver;
4999         else
5000                 tp->irq_mask |= RxOverflow;
5001 }
5002
5003 static int rtl_alloc_irq(struct rtl8169_private *tp)
5004 {
5005         unsigned int flags;
5006
5007         switch (tp->mac_version) {
5008         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5009                 rtl_unlock_config_regs(tp);
5010                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5011                 rtl_lock_config_regs(tp);
5012                 fallthrough;
5013         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5014                 flags = PCI_IRQ_LEGACY;
5015                 break;
5016         default:
5017                 flags = PCI_IRQ_ALL_TYPES;
5018                 break;
5019         }
5020
5021         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5022 }
5023
5024 static void rtl_read_mac_address(struct rtl8169_private *tp,
5025                                  u8 mac_addr[ETH_ALEN])
5026 {
5027         /* Get MAC address */
5028         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5029                 u32 value = rtl_eri_read(tp, 0xe0);
5030
5031                 mac_addr[0] = (value >>  0) & 0xff;
5032                 mac_addr[1] = (value >>  8) & 0xff;
5033                 mac_addr[2] = (value >> 16) & 0xff;
5034                 mac_addr[3] = (value >> 24) & 0xff;
5035
5036                 value = rtl_eri_read(tp, 0xe4);
5037                 mac_addr[4] = (value >>  0) & 0xff;
5038                 mac_addr[5] = (value >>  8) & 0xff;
5039         } else if (rtl_is_8125(tp)) {
5040                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5041         }
5042 }
5043
5044 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5045 {
5046         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5047 }
5048
5049 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5050 {
5051         rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5052 }
5053
5054 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5055 {
5056         struct rtl8169_private *tp = mii_bus->priv;
5057
5058         if (phyaddr > 0)
5059                 return -ENODEV;
5060
5061         return rtl_readphy(tp, phyreg);
5062 }
5063
5064 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5065                                 int phyreg, u16 val)
5066 {
5067         struct rtl8169_private *tp = mii_bus->priv;
5068
5069         if (phyaddr > 0)
5070                 return -ENODEV;
5071
5072         rtl_writephy(tp, phyreg, val);
5073
5074         return 0;
5075 }
5076
5077 static int r8169_mdio_register(struct rtl8169_private *tp)
5078 {
5079         struct pci_dev *pdev = tp->pci_dev;
5080         struct mii_bus *new_bus;
5081         int ret;
5082
5083         new_bus = devm_mdiobus_alloc(&pdev->dev);
5084         if (!new_bus)
5085                 return -ENOMEM;
5086
5087         new_bus->name = "r8169";
5088         new_bus->priv = tp;
5089         new_bus->parent = &pdev->dev;
5090         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5091         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5092
5093         new_bus->read = r8169_mdio_read_reg;
5094         new_bus->write = r8169_mdio_write_reg;
5095
5096         ret = devm_mdiobus_register(&pdev->dev, new_bus);
5097         if (ret)
5098                 return ret;
5099
5100         tp->phydev = mdiobus_get_phy(new_bus, 0);
5101         if (!tp->phydev) {
5102                 return -ENODEV;
5103         } else if (!tp->phydev->drv) {
5104                 /* Most chip versions fail with the genphy driver.
5105                  * Therefore ensure that the dedicated PHY driver is loaded.
5106                  */
5107                 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5108                         tp->phydev->phy_id);
5109                 return -EUNATCH;
5110         }
5111
5112         /* PHY will be woken up in rtl_open() */
5113         phy_suspend(tp->phydev);
5114
5115         return 0;
5116 }
5117
5118 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5119 {
5120         rtl_enable_rxdvgate(tp);
5121
5122         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5123         msleep(1);
5124         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5125
5126         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5127         r8168g_wait_ll_share_fifo_ready(tp);
5128
5129         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5130         r8168g_wait_ll_share_fifo_ready(tp);
5131 }
5132
5133 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5134 {
5135         rtl_enable_rxdvgate(tp);
5136
5137         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5138         msleep(1);
5139         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5140
5141         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5142         r8168g_wait_ll_share_fifo_ready(tp);
5143
5144         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5145         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5146         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5147         r8168g_wait_ll_share_fifo_ready(tp);
5148 }
5149
5150 static void rtl_hw_initialize(struct rtl8169_private *tp)
5151 {
5152         switch (tp->mac_version) {
5153         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5154                 rtl8168ep_stop_cmac(tp);
5155                 fallthrough;
5156         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5157                 rtl_hw_init_8168g(tp);
5158                 break;
5159         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5160                 rtl_hw_init_8125(tp);
5161                 break;
5162         default:
5163                 break;
5164         }
5165 }
5166
5167 static int rtl_jumbo_max(struct rtl8169_private *tp)
5168 {
5169         /* Non-GBit versions don't support jumbo frames */
5170         if (!tp->supports_gmii)
5171                 return 0;
5172
5173         switch (tp->mac_version) {
5174         /* RTL8169 */
5175         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5176                 return JUMBO_7K;
5177         /* RTL8168b */
5178         case RTL_GIGA_MAC_VER_11:
5179         case RTL_GIGA_MAC_VER_12:
5180         case RTL_GIGA_MAC_VER_17:
5181                 return JUMBO_4K;
5182         /* RTL8168c */
5183         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5184                 return JUMBO_6K;
5185         default:
5186                 return JUMBO_9K;
5187         }
5188 }
5189
5190 static void rtl_disable_clk(void *data)
5191 {
5192         clk_disable_unprepare(data);
5193 }
5194
5195 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5196 {
5197         struct device *d = tp_to_dev(tp);
5198         struct clk *clk;
5199         int rc;
5200
5201         clk = devm_clk_get(d, "ether_clk");
5202         if (IS_ERR(clk)) {
5203                 rc = PTR_ERR(clk);
5204                 if (rc == -ENOENT)
5205                         /* clk-core allows NULL (for suspend / resume) */
5206                         rc = 0;
5207                 else if (rc != -EPROBE_DEFER)
5208                         dev_err(d, "failed to get clk: %d\n", rc);
5209         } else {
5210                 tp->clk = clk;
5211                 rc = clk_prepare_enable(clk);
5212                 if (rc)
5213                         dev_err(d, "failed to enable clk: %d\n", rc);
5214                 else
5215                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5216         }
5217
5218         return rc;
5219 }
5220
5221 static void rtl_init_mac_address(struct rtl8169_private *tp)
5222 {
5223         struct net_device *dev = tp->dev;
5224         u8 *mac_addr = dev->dev_addr;
5225         int rc;
5226
5227         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5228         if (!rc)
5229                 goto done;
5230
5231         rtl_read_mac_address(tp, mac_addr);
5232         if (is_valid_ether_addr(mac_addr))
5233                 goto done;
5234
5235         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5236         if (is_valid_ether_addr(mac_addr))
5237                 goto done;
5238
5239         eth_hw_addr_random(dev);
5240         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5241 done:
5242         rtl_rar_set(tp, mac_addr);
5243 }
5244
5245 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5246 {
5247         struct rtl8169_private *tp;
5248         int jumbo_max, region, rc;
5249         enum mac_version chipset;
5250         struct net_device *dev;
5251         u16 xid;
5252
5253         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5254         if (!dev)
5255                 return -ENOMEM;
5256
5257         SET_NETDEV_DEV(dev, &pdev->dev);
5258         dev->netdev_ops = &rtl_netdev_ops;
5259         tp = netdev_priv(dev);
5260         tp->dev = dev;
5261         tp->pci_dev = pdev;
5262         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5263         tp->eee_adv = -1;
5264         tp->ocp_base = OCP_STD_PHY_BASE;
5265
5266         /* Get the *optional* external "ether_clk" used on some boards */
5267         rc = rtl_get_ether_clk(tp);
5268         if (rc)
5269                 return rc;
5270
5271         /* Disable ASPM completely as that cause random device stop working
5272          * problems as well as full system hangs for some PCIe devices users.
5273          */
5274         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5275                                           PCIE_LINK_STATE_L1);
5276         tp->aspm_manageable = !rc;
5277
5278         /* enable device (incl. PCI PM wakeup and hotplug setup) */
5279         rc = pcim_enable_device(pdev);
5280         if (rc < 0) {
5281                 dev_err(&pdev->dev, "enable failure\n");
5282                 return rc;
5283         }
5284
5285         if (pcim_set_mwi(pdev) < 0)
5286                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5287
5288         /* use first MMIO region */
5289         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5290         if (region < 0) {
5291                 dev_err(&pdev->dev, "no MMIO resource found\n");
5292                 return -ENODEV;
5293         }
5294
5295         /* check for weird/broken PCI region reporting */
5296         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5297                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5298                 return -ENODEV;
5299         }
5300
5301         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5302         if (rc < 0) {
5303                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5304                 return rc;
5305         }
5306
5307         tp->mmio_addr = pcim_iomap_table(pdev)[region];
5308
5309         xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5310
5311         /* Identify chip attached to board */
5312         chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5313         if (chipset == RTL_GIGA_MAC_NONE) {
5314                 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5315                 return -ENODEV;
5316         }
5317
5318         tp->mac_version = chipset;
5319
5320         tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5321
5322         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5323             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5324                 dev->features |= NETIF_F_HIGHDMA;
5325
5326         rtl_init_rxcfg(tp);
5327
5328         rtl8169_irq_mask_and_ack(tp);
5329
5330         rtl_hw_initialize(tp);
5331
5332         rtl_hw_reset(tp);
5333
5334         pci_set_master(pdev);
5335
5336         rc = rtl_alloc_irq(tp);
5337         if (rc < 0) {
5338                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5339                 return rc;
5340         }
5341
5342         INIT_WORK(&tp->wk.work, rtl_task);
5343         u64_stats_init(&tp->rx_stats.syncp);
5344         u64_stats_init(&tp->tx_stats.syncp);
5345
5346         rtl_init_mac_address(tp);
5347
5348         dev->ethtool_ops = &rtl8169_ethtool_ops;
5349
5350         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5351
5352         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5353                            NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5354         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5355         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5356
5357         /*
5358          * Pretend we are using VLANs; This bypasses a nasty bug where
5359          * Interrupts stop flowing on high load on 8110SCd controllers.
5360          */
5361         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5362                 /* Disallow toggling */
5363                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5364
5365         if (rtl_chip_supports_csum_v2(tp))
5366                 dev->hw_features |= NETIF_F_IPV6_CSUM;
5367
5368         dev->features |= dev->hw_features;
5369
5370         /* There has been a number of reports that using SG/TSO results in
5371          * tx timeouts. However for a lot of people SG/TSO works fine.
5372          * Therefore disable both features by default, but allow users to
5373          * enable them. Use at own risk!
5374          */
5375         if (rtl_chip_supports_csum_v2(tp)) {
5376                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5377                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5378                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5379         } else {
5380                 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5381                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5382                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5383         }
5384
5385         dev->hw_features |= NETIF_F_RXALL;
5386         dev->hw_features |= NETIF_F_RXFCS;
5387
5388         /* configure chip for default features */
5389         rtl8169_set_features(dev, dev->features);
5390
5391         jumbo_max = rtl_jumbo_max(tp);
5392         if (jumbo_max)
5393                 dev->max_mtu = jumbo_max;
5394
5395         rtl_set_irq_mask(tp);
5396
5397         tp->fw_name = rtl_chip_infos[chipset].fw_name;
5398
5399         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5400                                             &tp->counters_phys_addr,
5401                                             GFP_KERNEL);
5402         if (!tp->counters)
5403                 return -ENOMEM;
5404
5405         pci_set_drvdata(pdev, tp);
5406
5407         rc = r8169_mdio_register(tp);
5408         if (rc)
5409                 return rc;
5410
5411         /* chip gets powered up in rtl_open() */
5412         rtl_pll_power_down(tp);
5413
5414         rc = register_netdev(dev);
5415         if (rc)
5416                 return rc;
5417
5418         netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5419                     rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5420                     pci_irq_vector(pdev, 0));
5421
5422         if (jumbo_max)
5423                 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5424                             jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5425                             "ok" : "ko");
5426
5427         if (r8168_check_dash(tp)) {
5428                 netdev_info(dev, "DASH enabled\n");
5429                 rtl8168_driver_start(tp);
5430         }
5431
5432         if (pci_dev_run_wake(pdev))
5433                 pm_runtime_put_sync(&pdev->dev);
5434
5435         return 0;
5436 }
5437
5438 static struct pci_driver rtl8169_pci_driver = {
5439         .name           = MODULENAME,
5440         .id_table       = rtl8169_pci_tbl,
5441         .probe          = rtl_init_one,
5442         .remove         = rtl_remove_one,
5443         .shutdown       = rtl_shutdown,
5444 #ifdef CONFIG_PM
5445         .driver.pm      = &rtl8169_pm_ops,
5446 #endif
5447 };
5448
5449 module_pci_driver(rtl8169_pci_driver);