2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
50 #define assert(expr) \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
53 #expr,__FILE__,__func__,__LINE__); \
55 #define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
58 #define assert(expr) do {} while (0)
59 #define dprintk(fmt, args...) do {} while (0)
60 #endif /* RTL8169_DEBUG */
62 #define R8169_MSG_DEFAULT \
63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
65 #define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77 #define R8169_REGS_SIZE 256
78 #define R8169_NAPI_WEIGHT 64
79 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
82 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85 #define RTL8169_TX_TIMEOUT (6*HZ)
86 #define RTL8169_PHY_TIMEOUT (10*HZ)
88 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
90 #define RTL_EEPROM_SIG_ADDR 0x0000
92 /* write/read MMIO register */
93 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96 #define RTL_R8(reg) readb (ioaddr + (reg))
97 #define RTL_R16(reg) readw (ioaddr + (reg))
98 #define RTL_R32(reg) readl (ioaddr + (reg))
101 RTL_GIGA_MAC_VER_01 = 0,
137 RTL_GIGA_MAC_NONE = 0xff,
140 enum rtl_tx_desc_version {
145 #define JUMBO_1K ETH_DATA_LEN
146 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151 #define _R(NAME,TD,FW,SZ,B) { \
159 static const struct {
161 enum rtl_tx_desc_version txd_version;
165 } rtl_chip_infos[] = {
167 [RTL_GIGA_MAC_VER_01] =
168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
169 [RTL_GIGA_MAC_VER_02] =
170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
171 [RTL_GIGA_MAC_VER_03] =
172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
173 [RTL_GIGA_MAC_VER_04] =
174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
175 [RTL_GIGA_MAC_VER_05] =
176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
177 [RTL_GIGA_MAC_VER_06] =
178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_07] =
181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
182 [RTL_GIGA_MAC_VER_08] =
183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
184 [RTL_GIGA_MAC_VER_09] =
185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
186 [RTL_GIGA_MAC_VER_10] =
187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
188 [RTL_GIGA_MAC_VER_11] =
189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
190 [RTL_GIGA_MAC_VER_12] =
191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
192 [RTL_GIGA_MAC_VER_13] =
193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_14] =
195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_15] =
197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_16] =
199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
200 [RTL_GIGA_MAC_VER_17] =
201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
202 [RTL_GIGA_MAC_VER_18] =
203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
204 [RTL_GIGA_MAC_VER_19] =
205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
206 [RTL_GIGA_MAC_VER_20] =
207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
208 [RTL_GIGA_MAC_VER_21] =
209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
210 [RTL_GIGA_MAC_VER_22] =
211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
212 [RTL_GIGA_MAC_VER_23] =
213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_24] =
215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_25] =
217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
219 [RTL_GIGA_MAC_VER_26] =
220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
222 [RTL_GIGA_MAC_VER_27] =
223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
224 [RTL_GIGA_MAC_VER_28] =
225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
226 [RTL_GIGA_MAC_VER_29] =
227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
229 [RTL_GIGA_MAC_VER_30] =
230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
232 [RTL_GIGA_MAC_VER_31] =
233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
234 [RTL_GIGA_MAC_VER_32] =
235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
237 [RTL_GIGA_MAC_VER_33] =
238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
240 [RTL_GIGA_MAC_VER_34] =
241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
243 [RTL_GIGA_MAC_VER_35] =
244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
246 [RTL_GIGA_MAC_VER_36] =
247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
258 static void rtl_hw_start_8169(struct net_device *);
259 static void rtl_hw_start_8168(struct net_device *);
260 static void rtl_hw_start_8101(struct net_device *);
262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
281 static int rx_buf_sz = 16383;
288 MAC0 = 0, /* Ethernet hardware address. */
290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
305 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
309 #define RX128_INT_EN (1 << 15) /* 8111c and later */
310 #define RX_MULTI_EN (1 << 14) /* 8111c only */
311 #define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314 #define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
336 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
340 #define TxPacketMax (8064 >> 7)
341 #define EarlySize 0x27
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
349 enum rtl8110_registers {
355 enum rtl8168_8101_registers {
358 #define CSIAR_FLAG 0x80000000
359 #define CSIAR_WRITE_CMD 0x80000000
360 #define CSIAR_BYTE_ENABLE 0x0f
361 #define CSIAR_BYTE_ENABLE_SHIFT 12
362 #define CSIAR_ADDR_MASK 0x0fff
365 #define EPHYAR_FLAG 0x80000000
366 #define EPHYAR_WRITE_CMD 0x80000000
367 #define EPHYAR_REG_MASK 0x1f
368 #define EPHYAR_REG_SHIFT 16
369 #define EPHYAR_DATA_MASK 0xffff
371 #define PFM_EN (1 << 6)
373 #define FIX_NAK_1 (1 << 4)
374 #define FIX_NAK_2 (1 << 3)
377 #define NOW_IS_OOB (1 << 7)
378 #define EN_NDP (1 << 3)
379 #define EN_OOB_RESET (1 << 2)
381 #define EFUSEAR_FLAG 0x80000000
382 #define EFUSEAR_WRITE_CMD 0x80000000
383 #define EFUSEAR_READ_CMD 0x00000000
384 #define EFUSEAR_REG_MASK 0x03ff
385 #define EFUSEAR_REG_SHIFT 8
386 #define EFUSEAR_DATA_MASK 0xff
389 enum rtl8168_registers {
394 #define ERIAR_FLAG 0x80000000
395 #define ERIAR_WRITE_CMD 0x80000000
396 #define ERIAR_READ_CMD 0x00000000
397 #define ERIAR_ADDR_BYTE_ALIGN 4
398 #define ERIAR_TYPE_SHIFT 16
399 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402 #define ERIAR_MASK_SHIFT 12
403 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408 #define OCPDR_WRITE_CMD 0x80000000
409 #define OCPDR_READ_CMD 0x00000000
410 #define OCPDR_REG_MASK 0x7f
411 #define OCPDR_GPHY_REG_SHIFT 16
412 #define OCPDR_DATA_MASK 0xffff
414 #define OCPAR_FLAG 0x80000000
415 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
416 #define OCPAR_GPHY_READ_CMD 0x0000f060
417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
419 #define TXPLA_RST (1 << 29)
420 #define PWM_EN (1 << 22)
423 enum rtl_register_content {
424 /* InterruptStatusBits */
428 TxDescUnavail = 0x0080,
452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
459 Cfg9346_Unlock = 0xc0,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
467 AcceptAllPhys = 0x01,
468 #define RX_CONFIG_ACCEPT_MASK 0x3f
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
474 /* Config1 register p.24 */
477 Speed_down = (1 << 4),
481 PMEnable = (1 << 0), /* Power Management Enable */
483 /* Config2 register p. 25 */
484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
497 /* Config5 register p.27 */
498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
502 LanWake = (1 << 1), /* LanWake enable/disable */
503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
533 /* rtl8169_PHYstatus */
544 TBILinkOK = 0x02000000,
546 /* DumpCounterCommand */
551 /* First doubleword. */
552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
559 enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562 #define TD_MSS_MAX 0x07ffu /* MSS value */
564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
568 /* 8169, 8168b and 810x except 8102e. */
569 enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
577 /* 8102e, 8168c and beyond. */
578 enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
586 static const struct rtl_tx_desc_info {
593 } tx_desc_info [] = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
599 .mss_shift = TD0_MSS_SHIFT,
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
607 .mss_shift = TD1_MSS_SHIFT,
612 enum rtl_rx_desc_bit {
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
617 #define RxProtoUDP (PID1)
618 #define RxProtoTCP (PID0)
619 #define RxProtoIP (PID1 | PID0)
620 #define RxProtoMask RxProtoIP
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
628 #define RsvdMask 0x3fffc000
645 u8 __pad[sizeof(void *) - sizeof(u32)];
649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
654 struct rtl8169_counters {
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
671 RTL_FLAG_TASK_ENABLED,
672 RTL_FLAG_TASK_SLOW_PENDING,
673 RTL_FLAG_TASK_RESET_PENDING,
674 RTL_FLAG_TASK_PHY_PENDING,
678 struct rtl8169_private {
679 void __iomem *mmio_addr; /* memory map physical address */
680 struct pci_dev *pci_dev;
681 struct net_device *dev;
682 struct napi_struct napi;
686 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
687 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
690 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
691 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
692 dma_addr_t TxPhyAddr;
693 dma_addr_t RxPhyAddr;
694 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
695 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
696 struct timer_list timer;
702 void (*write)(void __iomem *, int, int);
703 int (*read)(void __iomem *, int);
706 struct pll_power_ops {
707 void (*down)(struct rtl8169_private *);
708 void (*up)(struct rtl8169_private *);
712 void (*enable)(struct rtl8169_private *);
713 void (*disable)(struct rtl8169_private *);
716 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
717 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
718 void (*phy_reset_enable)(struct rtl8169_private *tp);
719 void (*hw_start)(struct net_device *);
720 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
721 unsigned int (*link_ok)(void __iomem *);
722 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
725 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
727 struct work_struct work;
732 struct mii_if_info mii;
733 struct rtl8169_counters counters;
738 const struct firmware *fw;
740 #define RTL_VER_SIZE 32
742 char version[RTL_VER_SIZE];
744 struct rtl_fw_phy_action {
749 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
752 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
753 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
754 module_param(use_dac, int, 0);
755 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
756 module_param_named(debug, debug.msg_enable, int, 0);
757 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
758 MODULE_LICENSE("GPL");
759 MODULE_VERSION(RTL8169_VERSION);
760 MODULE_FIRMWARE(FIRMWARE_8168D_1);
761 MODULE_FIRMWARE(FIRMWARE_8168D_2);
762 MODULE_FIRMWARE(FIRMWARE_8168E_1);
763 MODULE_FIRMWARE(FIRMWARE_8168E_2);
764 MODULE_FIRMWARE(FIRMWARE_8168E_3);
765 MODULE_FIRMWARE(FIRMWARE_8105E_1);
766 MODULE_FIRMWARE(FIRMWARE_8168F_1);
767 MODULE_FIRMWARE(FIRMWARE_8168F_2);
769 static int rtl8169_open(struct net_device *dev);
770 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
771 struct net_device *dev);
772 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
773 static int rtl8169_init_ring(struct net_device *dev);
774 static void rtl_hw_start(struct net_device *dev);
775 static int rtl8169_close(struct net_device *dev);
776 static void rtl_set_rx_mode(struct net_device *dev);
777 static void rtl8169_tx_timeout(struct net_device *dev);
778 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
779 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
780 static void rtl8169_rx_clear(struct rtl8169_private *tp);
781 static int rtl8169_poll(struct napi_struct *napi, int budget);
783 static void rtl_lock_work(struct rtl8169_private *tp)
785 mutex_lock(&tp->wk.mutex);
788 static void rtl_unlock_work(struct rtl8169_private *tp)
790 mutex_unlock(&tp->wk.mutex);
793 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
795 int cap = pci_pcie_cap(pdev);
800 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
801 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
802 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
806 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
808 void __iomem *ioaddr = tp->mmio_addr;
811 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
812 for (i = 0; i < 20; i++) {
814 if (RTL_R32(OCPAR) & OCPAR_FLAG)
817 return RTL_R32(OCPDR);
820 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
822 void __iomem *ioaddr = tp->mmio_addr;
825 RTL_W32(OCPDR, data);
826 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
827 for (i = 0; i < 20; i++) {
829 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
834 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
836 void __iomem *ioaddr = tp->mmio_addr;
840 RTL_W32(ERIAR, 0x800010e8);
842 for (i = 0; i < 5; i++) {
844 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
848 ocp_write(tp, 0x1, 0x30, 0x00000001);
851 #define OOB_CMD_RESET 0x00
852 #define OOB_CMD_DRIVER_START 0x05
853 #define OOB_CMD_DRIVER_STOP 0x06
855 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
857 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
860 static void rtl8168_driver_start(struct rtl8169_private *tp)
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
867 reg = rtl8168_get_ocp_reg(tp);
869 for (i = 0; i < 10; i++) {
871 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
876 static void rtl8168_driver_stop(struct rtl8169_private *tp)
881 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
883 reg = rtl8168_get_ocp_reg(tp);
885 for (i = 0; i < 10; i++) {
887 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
892 static int r8168dp_check_dash(struct rtl8169_private *tp)
894 u16 reg = rtl8168_get_ocp_reg(tp);
896 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
899 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
903 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
905 for (i = 20; i > 0; i--) {
907 * Check if the RTL8169 has completed writing to the specified
910 if (!(RTL_R32(PHYAR) & 0x80000000))
915 * According to hardware specs a 20us delay is required after write
916 * complete indication, but before sending next command.
921 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
925 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
927 for (i = 20; i > 0; i--) {
929 * Check if the RTL8169 has completed retrieving data from
930 * the specified MII register.
932 if (RTL_R32(PHYAR) & 0x80000000) {
933 value = RTL_R32(PHYAR) & 0xffff;
939 * According to hardware specs a 20us delay is required after read
940 * complete indication, but before sending next command.
947 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
951 RTL_W32(OCPDR, data |
952 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
953 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
954 RTL_W32(EPHY_RXER_NUM, 0);
956 for (i = 0; i < 100; i++) {
958 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
963 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
965 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
966 (value & OCPDR_DATA_MASK));
969 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
973 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
976 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
977 RTL_W32(EPHY_RXER_NUM, 0);
979 for (i = 0; i < 100; i++) {
981 if (RTL_R32(OCPAR) & OCPAR_FLAG)
985 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
988 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
990 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
992 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
995 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
997 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1000 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1002 r8168dp_2_mdio_start(ioaddr);
1004 r8169_mdio_write(ioaddr, reg_addr, value);
1006 r8168dp_2_mdio_stop(ioaddr);
1009 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1013 r8168dp_2_mdio_start(ioaddr);
1015 value = r8169_mdio_read(ioaddr, reg_addr);
1017 r8168dp_2_mdio_stop(ioaddr);
1022 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1024 tp->mdio_ops.write(tp->mmio_addr, location, val);
1027 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 return tp->mdio_ops.read(tp->mmio_addr, location);
1032 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1034 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1037 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1041 val = rtl_readphy(tp, reg_addr);
1042 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1045 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1048 struct rtl8169_private *tp = netdev_priv(dev);
1050 rtl_writephy(tp, location, val);
1053 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1055 struct rtl8169_private *tp = netdev_priv(dev);
1057 return rtl_readphy(tp, location);
1060 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1064 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1067 for (i = 0; i < 100; i++) {
1068 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1074 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1079 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1081 for (i = 0; i < 100; i++) {
1082 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1092 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1096 RTL_W32(CSIDR, value);
1097 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1100 for (i = 0; i < 100; i++) {
1101 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1107 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1112 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1115 for (i = 0; i < 100; i++) {
1116 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117 value = RTL_R32(CSIDR);
1127 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1131 BUG_ON((addr & 3) || (mask == 0));
1132 RTL_W32(ERIDR, val);
1133 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1135 for (i = 0; i < 100; i++) {
1136 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1142 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1147 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1149 for (i = 0; i < 100; i++) {
1150 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151 value = RTL_R32(ERIDR);
1161 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1165 val = rtl_eri_read(ioaddr, addr, type);
1166 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1175 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176 const struct exgmac_reg *r, int len)
1179 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1184 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1189 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1191 for (i = 0; i < 300; i++) {
1192 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1202 static u16 rtl_get_events(struct rtl8169_private *tp)
1204 void __iomem *ioaddr = tp->mmio_addr;
1206 return RTL_R16(IntrStatus);
1209 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1211 void __iomem *ioaddr = tp->mmio_addr;
1213 RTL_W16(IntrStatus, bits);
1217 static void rtl_irq_disable(struct rtl8169_private *tp)
1219 void __iomem *ioaddr = tp->mmio_addr;
1221 RTL_W16(IntrMask, 0);
1225 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1227 void __iomem *ioaddr = tp->mmio_addr;
1229 RTL_W16(IntrMask, bits);
1232 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1236 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1238 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1243 void __iomem *ioaddr = tp->mmio_addr;
1245 rtl_irq_disable(tp);
1246 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1252 void __iomem *ioaddr = tp->mmio_addr;
1254 return RTL_R32(TBICSR) & TBIReset;
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1259 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1264 return RTL_R32(TBICSR) & TBILinkOk;
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1269 return RTL_R8(PHYstatus) & LinkStatus;
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1274 void __iomem *ioaddr = tp->mmio_addr;
1276 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1283 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1287 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1289 void __iomem *ioaddr = tp->mmio_addr;
1290 struct net_device *dev = tp->dev;
1292 if (!netif_running(dev))
1295 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298 0x00000011, ERIAR_EXGMAC);
1299 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300 0x00000005, ERIAR_EXGMAC);
1301 } else if (RTL_R8(PHYstatus) & _100bps) {
1302 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303 0x0000001f, ERIAR_EXGMAC);
1304 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305 0x00000005, ERIAR_EXGMAC);
1307 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308 0x0000001f, ERIAR_EXGMAC);
1309 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310 0x0000003f, ERIAR_EXGMAC);
1312 /* Reset packet filter */
1313 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1315 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1317 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321 0x00000011, ERIAR_EXGMAC);
1322 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323 0x00000005, ERIAR_EXGMAC);
1325 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326 0x0000001f, ERIAR_EXGMAC);
1327 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328 0x0000003f, ERIAR_EXGMAC);
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334 struct rtl8169_private *tp,
1335 void __iomem *ioaddr, bool pm)
1337 if (tp->link_ok(ioaddr)) {
1338 rtl_link_chg_patch(tp);
1339 /* This is to cancel a scheduled suspend if there's one. */
1341 pm_request_resume(&tp->pci_dev->dev);
1342 netif_carrier_on(dev);
1343 if (net_ratelimit())
1344 netif_info(tp, ifup, dev, "link up\n");
1346 netif_carrier_off(dev);
1347 netif_info(tp, ifdown, dev, "link down\n");
1349 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354 struct rtl8169_private *tp,
1355 void __iomem *ioaddr)
1357 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1364 void __iomem *ioaddr = tp->mmio_addr;
1368 options = RTL_R8(Config1);
1369 if (!(options & PMEnable))
1372 options = RTL_R8(Config3);
1373 if (options & LinkUp)
1374 wolopts |= WAKE_PHY;
1375 if (options & MagicPacket)
1376 wolopts |= WAKE_MAGIC;
1378 options = RTL_R8(Config5);
1380 wolopts |= WAKE_UCAST;
1382 wolopts |= WAKE_BCAST;
1384 wolopts |= WAKE_MCAST;
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1391 struct rtl8169_private *tp = netdev_priv(dev);
1395 wol->supported = WAKE_ANY;
1396 wol->wolopts = __rtl8169_get_wol(tp);
1398 rtl_unlock_work(tp);
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1403 void __iomem *ioaddr = tp->mmio_addr;
1405 static const struct {
1410 { WAKE_ANY, Config1, PMEnable },
1411 { WAKE_PHY, Config3, LinkUp },
1412 { WAKE_MAGIC, Config3, MagicPacket },
1413 { WAKE_UCAST, Config5, UWF },
1414 { WAKE_BCAST, Config5, BWF },
1415 { WAKE_MCAST, Config5, MWF },
1416 { WAKE_ANY, Config5, LanWake }
1419 RTL_W8(Cfg9346, Cfg9346_Unlock);
1421 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423 if (wolopts & cfg[i].opt)
1424 options |= cfg[i].mask;
1425 RTL_W8(cfg[i].reg, options);
1428 RTL_W8(Cfg9346, Cfg9346_Lock);
1431 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1433 struct rtl8169_private *tp = netdev_priv(dev);
1438 tp->features |= RTL_FEATURE_WOL;
1440 tp->features &= ~RTL_FEATURE_WOL;
1441 __rtl8169_set_wol(tp, wol->wolopts);
1443 rtl_unlock_work(tp);
1445 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1450 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1452 return rtl_chip_infos[tp->mac_version].fw_name;
1455 static void rtl8169_get_drvinfo(struct net_device *dev,
1456 struct ethtool_drvinfo *info)
1458 struct rtl8169_private *tp = netdev_priv(dev);
1459 struct rtl_fw *rtl_fw = tp->rtl_fw;
1461 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1462 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1463 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1464 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1465 if (!IS_ERR_OR_NULL(rtl_fw))
1466 strlcpy(info->fw_version, rtl_fw->version,
1467 sizeof(info->fw_version));
1470 static int rtl8169_get_regs_len(struct net_device *dev)
1472 return R8169_REGS_SIZE;
1475 static int rtl8169_set_speed_tbi(struct net_device *dev,
1476 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1478 struct rtl8169_private *tp = netdev_priv(dev);
1479 void __iomem *ioaddr = tp->mmio_addr;
1483 reg = RTL_R32(TBICSR);
1484 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1485 (duplex == DUPLEX_FULL)) {
1486 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1487 } else if (autoneg == AUTONEG_ENABLE)
1488 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1490 netif_warn(tp, link, dev,
1491 "incorrect speed setting refused in TBI mode\n");
1498 static int rtl8169_set_speed_xmii(struct net_device *dev,
1499 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1501 struct rtl8169_private *tp = netdev_priv(dev);
1502 int giga_ctrl, bmcr;
1505 rtl_writephy(tp, 0x1f, 0x0000);
1507 if (autoneg == AUTONEG_ENABLE) {
1510 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1511 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1512 ADVERTISE_100HALF | ADVERTISE_100FULL);
1514 if (adv & ADVERTISED_10baseT_Half)
1515 auto_nego |= ADVERTISE_10HALF;
1516 if (adv & ADVERTISED_10baseT_Full)
1517 auto_nego |= ADVERTISE_10FULL;
1518 if (adv & ADVERTISED_100baseT_Half)
1519 auto_nego |= ADVERTISE_100HALF;
1520 if (adv & ADVERTISED_100baseT_Full)
1521 auto_nego |= ADVERTISE_100FULL;
1523 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1525 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1526 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1528 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1529 if (tp->mii.supports_gmii) {
1530 if (adv & ADVERTISED_1000baseT_Half)
1531 giga_ctrl |= ADVERTISE_1000HALF;
1532 if (adv & ADVERTISED_1000baseT_Full)
1533 giga_ctrl |= ADVERTISE_1000FULL;
1534 } else if (adv & (ADVERTISED_1000baseT_Half |
1535 ADVERTISED_1000baseT_Full)) {
1536 netif_info(tp, link, dev,
1537 "PHY does not support 1000Mbps\n");
1541 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1543 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1544 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1548 if (speed == SPEED_10)
1550 else if (speed == SPEED_100)
1551 bmcr = BMCR_SPEED100;
1555 if (duplex == DUPLEX_FULL)
1556 bmcr |= BMCR_FULLDPLX;
1559 rtl_writephy(tp, MII_BMCR, bmcr);
1561 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1562 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1563 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1564 rtl_writephy(tp, 0x17, 0x2138);
1565 rtl_writephy(tp, 0x0e, 0x0260);
1567 rtl_writephy(tp, 0x17, 0x2108);
1568 rtl_writephy(tp, 0x0e, 0x0000);
1577 static int rtl8169_set_speed(struct net_device *dev,
1578 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1580 struct rtl8169_private *tp = netdev_priv(dev);
1583 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1587 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1588 (advertising & ADVERTISED_1000baseT_Full)) {
1589 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1595 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1597 struct rtl8169_private *tp = netdev_priv(dev);
1600 del_timer_sync(&tp->timer);
1603 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1604 cmd->duplex, cmd->advertising);
1605 rtl_unlock_work(tp);
1610 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1611 netdev_features_t features)
1613 struct rtl8169_private *tp = netdev_priv(dev);
1615 if (dev->mtu > TD_MSS_MAX)
1616 features &= ~NETIF_F_ALL_TSO;
1618 if (dev->mtu > JUMBO_1K &&
1619 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1620 features &= ~NETIF_F_IP_CSUM;
1625 static void __rtl8169_set_features(struct net_device *dev,
1626 netdev_features_t features)
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 netdev_features_t changed = features ^ dev->features;
1630 void __iomem *ioaddr = tp->mmio_addr;
1632 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1635 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1636 if (features & NETIF_F_RXCSUM)
1637 tp->cp_cmd |= RxChkSum;
1639 tp->cp_cmd &= ~RxChkSum;
1641 if (dev->features & NETIF_F_HW_VLAN_RX)
1642 tp->cp_cmd |= RxVlan;
1644 tp->cp_cmd &= ~RxVlan;
1646 RTL_W16(CPlusCmd, tp->cp_cmd);
1649 if (changed & NETIF_F_RXALL) {
1650 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1651 if (features & NETIF_F_RXALL)
1652 tmp |= (AcceptErr | AcceptRunt);
1653 RTL_W32(RxConfig, tmp);
1657 static int rtl8169_set_features(struct net_device *dev,
1658 netdev_features_t features)
1660 struct rtl8169_private *tp = netdev_priv(dev);
1663 __rtl8169_set_features(dev, features);
1664 rtl_unlock_work(tp);
1670 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1671 struct sk_buff *skb)
1673 return (vlan_tx_tag_present(skb)) ?
1674 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1677 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1679 u32 opts2 = le32_to_cpu(desc->opts2);
1681 if (opts2 & RxVlanTag)
1682 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1687 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1689 struct rtl8169_private *tp = netdev_priv(dev);
1690 void __iomem *ioaddr = tp->mmio_addr;
1694 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1695 cmd->port = PORT_FIBRE;
1696 cmd->transceiver = XCVR_INTERNAL;
1698 status = RTL_R32(TBICSR);
1699 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1700 cmd->autoneg = !!(status & TBINwEnable);
1702 ethtool_cmd_speed_set(cmd, SPEED_1000);
1703 cmd->duplex = DUPLEX_FULL; /* Always set */
1708 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1710 struct rtl8169_private *tp = netdev_priv(dev);
1712 return mii_ethtool_gset(&tp->mii, cmd);
1715 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1717 struct rtl8169_private *tp = netdev_priv(dev);
1721 rc = tp->get_settings(dev, cmd);
1722 rtl_unlock_work(tp);
1727 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1730 struct rtl8169_private *tp = netdev_priv(dev);
1732 if (regs->len > R8169_REGS_SIZE)
1733 regs->len = R8169_REGS_SIZE;
1736 memcpy_fromio(p, tp->mmio_addr, regs->len);
1737 rtl_unlock_work(tp);
1740 static u32 rtl8169_get_msglevel(struct net_device *dev)
1742 struct rtl8169_private *tp = netdev_priv(dev);
1744 return tp->msg_enable;
1747 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1749 struct rtl8169_private *tp = netdev_priv(dev);
1751 tp->msg_enable = value;
1754 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1761 "tx_single_collisions",
1762 "tx_multi_collisions",
1770 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1774 return ARRAY_SIZE(rtl8169_gstrings);
1780 static void rtl8169_update_counters(struct net_device *dev)
1782 struct rtl8169_private *tp = netdev_priv(dev);
1783 void __iomem *ioaddr = tp->mmio_addr;
1784 struct device *d = &tp->pci_dev->dev;
1785 struct rtl8169_counters *counters;
1791 * Some chips are unable to dump tally counters when the receiver
1794 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1797 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1801 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1802 cmd = (u64)paddr & DMA_BIT_MASK(32);
1803 RTL_W32(CounterAddrLow, cmd);
1804 RTL_W32(CounterAddrLow, cmd | CounterDump);
1807 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1808 memcpy(&tp->counters, counters, sizeof(*counters));
1814 RTL_W32(CounterAddrLow, 0);
1815 RTL_W32(CounterAddrHigh, 0);
1817 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1820 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1821 struct ethtool_stats *stats, u64 *data)
1823 struct rtl8169_private *tp = netdev_priv(dev);
1827 rtl8169_update_counters(dev);
1829 data[0] = le64_to_cpu(tp->counters.tx_packets);
1830 data[1] = le64_to_cpu(tp->counters.rx_packets);
1831 data[2] = le64_to_cpu(tp->counters.tx_errors);
1832 data[3] = le32_to_cpu(tp->counters.rx_errors);
1833 data[4] = le16_to_cpu(tp->counters.rx_missed);
1834 data[5] = le16_to_cpu(tp->counters.align_errors);
1835 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1836 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1837 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1838 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1839 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1840 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1841 data[12] = le16_to_cpu(tp->counters.tx_underun);
1844 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1848 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1853 static const struct ethtool_ops rtl8169_ethtool_ops = {
1854 .get_drvinfo = rtl8169_get_drvinfo,
1855 .get_regs_len = rtl8169_get_regs_len,
1856 .get_link = ethtool_op_get_link,
1857 .get_settings = rtl8169_get_settings,
1858 .set_settings = rtl8169_set_settings,
1859 .get_msglevel = rtl8169_get_msglevel,
1860 .set_msglevel = rtl8169_set_msglevel,
1861 .get_regs = rtl8169_get_regs,
1862 .get_wol = rtl8169_get_wol,
1863 .set_wol = rtl8169_set_wol,
1864 .get_strings = rtl8169_get_strings,
1865 .get_sset_count = rtl8169_get_sset_count,
1866 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1869 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1870 struct net_device *dev, u8 default_version)
1872 void __iomem *ioaddr = tp->mmio_addr;
1874 * The driver currently handles the 8168Bf and the 8168Be identically
1875 * but they can be identified more specifically through the test below
1878 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1880 * Same thing for the 8101Eb and the 8101Ec:
1882 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1884 static const struct rtl_mac_info {
1890 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1891 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1894 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1895 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1896 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1897 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1900 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1901 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1902 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1904 /* 8168DP family. */
1905 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1906 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1907 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1910 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1911 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1912 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1913 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1914 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1915 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1916 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1917 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1918 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1921 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1922 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1923 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1924 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1927 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1928 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1929 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1930 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1931 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1932 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1933 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1934 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1935 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1936 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1937 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1938 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1939 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1940 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1941 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1942 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1943 /* FIXME: where did these entries come from ? -- FR */
1944 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1945 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1948 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1949 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1950 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1951 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1952 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1953 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1956 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1958 const struct rtl_mac_info *p = mac_info;
1961 reg = RTL_R32(TxConfig);
1962 while ((reg & p->mask) != p->val)
1964 tp->mac_version = p->mac_version;
1966 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1967 netif_notice(tp, probe, dev,
1968 "unknown MAC, using family default\n");
1969 tp->mac_version = default_version;
1973 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1975 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1983 static void rtl_writephy_batch(struct rtl8169_private *tp,
1984 const struct phy_reg *regs, int len)
1987 rtl_writephy(tp, regs->reg, regs->val);
1992 #define PHY_READ 0x00000000
1993 #define PHY_DATA_OR 0x10000000
1994 #define PHY_DATA_AND 0x20000000
1995 #define PHY_BJMPN 0x30000000
1996 #define PHY_READ_EFUSE 0x40000000
1997 #define PHY_READ_MAC_BYTE 0x50000000
1998 #define PHY_WRITE_MAC_BYTE 0x60000000
1999 #define PHY_CLEAR_READCOUNT 0x70000000
2000 #define PHY_WRITE 0x80000000
2001 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2002 #define PHY_COMP_EQ_SKIPN 0xa0000000
2003 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2004 #define PHY_WRITE_PREVIOUS 0xc0000000
2005 #define PHY_SKIPN 0xd0000000
2006 #define PHY_DELAY_MS 0xe0000000
2007 #define PHY_WRITE_ERI_WORD 0xf0000000
2011 char version[RTL_VER_SIZE];
2017 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2019 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2021 const struct firmware *fw = rtl_fw->fw;
2022 struct fw_info *fw_info = (struct fw_info *)fw->data;
2023 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2024 char *version = rtl_fw->version;
2027 if (fw->size < FW_OPCODE_SIZE)
2030 if (!fw_info->magic) {
2031 size_t i, size, start;
2034 if (fw->size < sizeof(*fw_info))
2037 for (i = 0; i < fw->size; i++)
2038 checksum += fw->data[i];
2042 start = le32_to_cpu(fw_info->fw_start);
2043 if (start > fw->size)
2046 size = le32_to_cpu(fw_info->fw_len);
2047 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2050 memcpy(version, fw_info->version, RTL_VER_SIZE);
2052 pa->code = (__le32 *)(fw->data + start);
2055 if (fw->size % FW_OPCODE_SIZE)
2058 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2060 pa->code = (__le32 *)fw->data;
2061 pa->size = fw->size / FW_OPCODE_SIZE;
2063 version[RTL_VER_SIZE - 1] = 0;
2070 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2071 struct rtl_fw_phy_action *pa)
2076 for (index = 0; index < pa->size; index++) {
2077 u32 action = le32_to_cpu(pa->code[index]);
2078 u32 regno = (action & 0x0fff0000) >> 16;
2080 switch(action & 0xf0000000) {
2084 case PHY_READ_EFUSE:
2085 case PHY_CLEAR_READCOUNT:
2087 case PHY_WRITE_PREVIOUS:
2092 if (regno > index) {
2093 netif_err(tp, ifup, tp->dev,
2094 "Out of range of firmware\n");
2098 case PHY_READCOUNT_EQ_SKIP:
2099 if (index + 2 >= pa->size) {
2100 netif_err(tp, ifup, tp->dev,
2101 "Out of range of firmware\n");
2105 case PHY_COMP_EQ_SKIPN:
2106 case PHY_COMP_NEQ_SKIPN:
2108 if (index + 1 + regno >= pa->size) {
2109 netif_err(tp, ifup, tp->dev,
2110 "Out of range of firmware\n");
2115 case PHY_READ_MAC_BYTE:
2116 case PHY_WRITE_MAC_BYTE:
2117 case PHY_WRITE_ERI_WORD:
2119 netif_err(tp, ifup, tp->dev,
2120 "Invalid action 0x%08x\n", action);
2129 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2131 struct net_device *dev = tp->dev;
2134 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2135 netif_err(tp, ifup, dev, "invalid firwmare\n");
2139 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2145 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2147 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2151 predata = count = 0;
2153 for (index = 0; index < pa->size; ) {
2154 u32 action = le32_to_cpu(pa->code[index]);
2155 u32 data = action & 0x0000ffff;
2156 u32 regno = (action & 0x0fff0000) >> 16;
2161 switch(action & 0xf0000000) {
2163 predata = rtl_readphy(tp, regno);
2178 case PHY_READ_EFUSE:
2179 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2182 case PHY_CLEAR_READCOUNT:
2187 rtl_writephy(tp, regno, data);
2190 case PHY_READCOUNT_EQ_SKIP:
2191 index += (count == data) ? 2 : 1;
2193 case PHY_COMP_EQ_SKIPN:
2194 if (predata == data)
2198 case PHY_COMP_NEQ_SKIPN:
2199 if (predata != data)
2203 case PHY_WRITE_PREVIOUS:
2204 rtl_writephy(tp, regno, predata);
2215 case PHY_READ_MAC_BYTE:
2216 case PHY_WRITE_MAC_BYTE:
2217 case PHY_WRITE_ERI_WORD:
2224 static void rtl_release_firmware(struct rtl8169_private *tp)
2226 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2227 release_firmware(tp->rtl_fw->fw);
2230 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2233 static void rtl_apply_firmware(struct rtl8169_private *tp)
2235 struct rtl_fw *rtl_fw = tp->rtl_fw;
2237 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2238 if (!IS_ERR_OR_NULL(rtl_fw))
2239 rtl_phy_write_fw(tp, rtl_fw);
2242 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2244 if (rtl_readphy(tp, reg) != val)
2245 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2247 rtl_apply_firmware(tp);
2250 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2252 static const struct phy_reg phy_reg_init[] = {
2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2317 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2319 static const struct phy_reg phy_reg_init[] = {
2325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2328 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2330 struct pci_dev *pdev = tp->pci_dev;
2332 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2333 (pdev->subsystem_device != 0xe000))
2336 rtl_writephy(tp, 0x1f, 0x0001);
2337 rtl_writephy(tp, 0x10, 0xf01b);
2338 rtl_writephy(tp, 0x1f, 0x0000);
2341 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2343 static const struct phy_reg phy_reg_init[] = {
2383 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2385 rtl8169scd_hw_phy_config_quirk(tp);
2388 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2390 static const struct phy_reg phy_reg_init[] = {
2438 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2441 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2443 static const struct phy_reg phy_reg_init[] = {
2448 rtl_writephy(tp, 0x1f, 0x0001);
2449 rtl_patchphy(tp, 0x16, 1 << 0);
2451 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2454 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2456 static const struct phy_reg phy_reg_init[] = {
2462 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2465 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2467 static const struct phy_reg phy_reg_init[] = {
2475 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2478 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2480 static const struct phy_reg phy_reg_init[] = {
2486 rtl_writephy(tp, 0x1f, 0x0000);
2487 rtl_patchphy(tp, 0x14, 1 << 5);
2488 rtl_patchphy(tp, 0x0d, 1 << 5);
2490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2493 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2495 static const struct phy_reg phy_reg_init[] = {
2515 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2517 rtl_patchphy(tp, 0x14, 1 << 5);
2518 rtl_patchphy(tp, 0x0d, 1 << 5);
2519 rtl_writephy(tp, 0x1f, 0x0000);
2522 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2524 static const struct phy_reg phy_reg_init[] = {
2542 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2544 rtl_patchphy(tp, 0x16, 1 << 0);
2545 rtl_patchphy(tp, 0x14, 1 << 5);
2546 rtl_patchphy(tp, 0x0d, 1 << 5);
2547 rtl_writephy(tp, 0x1f, 0x0000);
2550 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2552 static const struct phy_reg phy_reg_init[] = {
2564 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2566 rtl_patchphy(tp, 0x16, 1 << 0);
2567 rtl_patchphy(tp, 0x14, 1 << 5);
2568 rtl_patchphy(tp, 0x0d, 1 << 5);
2569 rtl_writephy(tp, 0x1f, 0x0000);
2572 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2574 rtl8168c_3_hw_phy_config(tp);
2577 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2579 static const struct phy_reg phy_reg_init_0[] = {
2580 /* Channel Estimation */
2601 * Enhance line driver power
2610 * Can not link to 1Gbps with bad cable
2611 * Decrease SNR threshold form 21.07dB to 19.04dB
2619 void __iomem *ioaddr = tp->mmio_addr;
2621 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2625 * Fine Tune Switching regulator parameter
2627 rtl_writephy(tp, 0x1f, 0x0002);
2628 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2629 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2631 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2632 static const struct phy_reg phy_reg_init[] = {
2642 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 val = rtl_readphy(tp, 0x0d);
2646 if ((val & 0x00ff) != 0x006c) {
2647 static const u32 set[] = {
2648 0x0065, 0x0066, 0x0067, 0x0068,
2649 0x0069, 0x006a, 0x006b, 0x006c
2653 rtl_writephy(tp, 0x1f, 0x0002);
2656 for (i = 0; i < ARRAY_SIZE(set); i++)
2657 rtl_writephy(tp, 0x0d, val | set[i]);
2660 static const struct phy_reg phy_reg_init[] = {
2668 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2671 /* RSET couple improve */
2672 rtl_writephy(tp, 0x1f, 0x0002);
2673 rtl_patchphy(tp, 0x0d, 0x0300);
2674 rtl_patchphy(tp, 0x0f, 0x0010);
2676 /* Fine tune PLL performance */
2677 rtl_writephy(tp, 0x1f, 0x0002);
2678 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2679 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2681 rtl_writephy(tp, 0x1f, 0x0005);
2682 rtl_writephy(tp, 0x05, 0x001b);
2684 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2686 rtl_writephy(tp, 0x1f, 0x0000);
2689 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2691 static const struct phy_reg phy_reg_init_0[] = {
2692 /* Channel Estimation */
2713 * Enhance line driver power
2722 * Can not link to 1Gbps with bad cable
2723 * Decrease SNR threshold form 21.07dB to 19.04dB
2731 void __iomem *ioaddr = tp->mmio_addr;
2733 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2735 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2736 static const struct phy_reg phy_reg_init[] = {
2747 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2749 val = rtl_readphy(tp, 0x0d);
2750 if ((val & 0x00ff) != 0x006c) {
2751 static const u32 set[] = {
2752 0x0065, 0x0066, 0x0067, 0x0068,
2753 0x0069, 0x006a, 0x006b, 0x006c
2757 rtl_writephy(tp, 0x1f, 0x0002);
2760 for (i = 0; i < ARRAY_SIZE(set); i++)
2761 rtl_writephy(tp, 0x0d, val | set[i]);
2764 static const struct phy_reg phy_reg_init[] = {
2772 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2775 /* Fine tune PLL performance */
2776 rtl_writephy(tp, 0x1f, 0x0002);
2777 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2778 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2780 /* Switching regulator Slew rate */
2781 rtl_writephy(tp, 0x1f, 0x0002);
2782 rtl_patchphy(tp, 0x0f, 0x0017);
2784 rtl_writephy(tp, 0x1f, 0x0005);
2785 rtl_writephy(tp, 0x05, 0x001b);
2787 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2789 rtl_writephy(tp, 0x1f, 0x0000);
2792 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2794 static const struct phy_reg phy_reg_init[] = {
2850 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2855 static const struct phy_reg phy_reg_init[] = {
2865 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866 rtl_patchphy(tp, 0x0d, 1 << 5);
2869 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2871 static const struct phy_reg phy_reg_init[] = {
2872 /* Enable Delay cap */
2878 /* Channel estimation fine tune */
2887 /* Update PFM & 10M TX idle timer */
2899 rtl_apply_firmware(tp);
2901 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2903 /* DCO enable for 10M IDLE Power */
2904 rtl_writephy(tp, 0x1f, 0x0007);
2905 rtl_writephy(tp, 0x1e, 0x0023);
2906 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2907 rtl_writephy(tp, 0x1f, 0x0000);
2909 /* For impedance matching */
2910 rtl_writephy(tp, 0x1f, 0x0002);
2911 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2912 rtl_writephy(tp, 0x1f, 0x0000);
2914 /* PHY auto speed down */
2915 rtl_writephy(tp, 0x1f, 0x0007);
2916 rtl_writephy(tp, 0x1e, 0x002d);
2917 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2918 rtl_writephy(tp, 0x1f, 0x0000);
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2921 rtl_writephy(tp, 0x1f, 0x0005);
2922 rtl_writephy(tp, 0x05, 0x8b86);
2923 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2924 rtl_writephy(tp, 0x1f, 0x0000);
2926 rtl_writephy(tp, 0x1f, 0x0005);
2927 rtl_writephy(tp, 0x05, 0x8b85);
2928 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2929 rtl_writephy(tp, 0x1f, 0x0007);
2930 rtl_writephy(tp, 0x1e, 0x0020);
2931 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2932 rtl_writephy(tp, 0x1f, 0x0006);
2933 rtl_writephy(tp, 0x00, 0x5a00);
2934 rtl_writephy(tp, 0x1f, 0x0000);
2935 rtl_writephy(tp, 0x0d, 0x0007);
2936 rtl_writephy(tp, 0x0e, 0x003c);
2937 rtl_writephy(tp, 0x0d, 0x4007);
2938 rtl_writephy(tp, 0x0e, 0x0000);
2939 rtl_writephy(tp, 0x0d, 0x0000);
2942 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2944 static const struct phy_reg phy_reg_init[] = {
2945 /* Enable Delay cap */
2954 /* Channel estimation fine tune */
2971 rtl_apply_firmware(tp);
2973 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2975 /* For 4-corner performance improve */
2976 rtl_writephy(tp, 0x1f, 0x0005);
2977 rtl_writephy(tp, 0x05, 0x8b80);
2978 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2979 rtl_writephy(tp, 0x1f, 0x0000);
2981 /* PHY auto speed down */
2982 rtl_writephy(tp, 0x1f, 0x0004);
2983 rtl_writephy(tp, 0x1f, 0x0007);
2984 rtl_writephy(tp, 0x1e, 0x002d);
2985 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2986 rtl_writephy(tp, 0x1f, 0x0002);
2987 rtl_writephy(tp, 0x1f, 0x0000);
2988 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2990 /* improve 10M EEE waveform */
2991 rtl_writephy(tp, 0x1f, 0x0005);
2992 rtl_writephy(tp, 0x05, 0x8b86);
2993 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2994 rtl_writephy(tp, 0x1f, 0x0000);
2996 /* Improve 2-pair detection performance */
2997 rtl_writephy(tp, 0x1f, 0x0005);
2998 rtl_writephy(tp, 0x05, 0x8b85);
2999 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3000 rtl_writephy(tp, 0x1f, 0x0000);
3003 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3005 rtl_writephy(tp, 0x1f, 0x0005);
3006 rtl_writephy(tp, 0x05, 0x8b85);
3007 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3008 rtl_writephy(tp, 0x1f, 0x0004);
3009 rtl_writephy(tp, 0x1f, 0x0007);
3010 rtl_writephy(tp, 0x1e, 0x0020);
3011 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3012 rtl_writephy(tp, 0x1f, 0x0002);
3013 rtl_writephy(tp, 0x1f, 0x0000);
3014 rtl_writephy(tp, 0x0d, 0x0007);
3015 rtl_writephy(tp, 0x0e, 0x003c);
3016 rtl_writephy(tp, 0x0d, 0x4007);
3017 rtl_writephy(tp, 0x0e, 0x0000);
3018 rtl_writephy(tp, 0x0d, 0x0000);
3021 rtl_writephy(tp, 0x1f, 0x0003);
3022 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3023 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3024 rtl_writephy(tp, 0x1f, 0x0000);
3027 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3029 static const struct phy_reg phy_reg_init[] = {
3030 /* Channel estimation fine tune */
3035 /* Modify green table for giga & fnet */
3052 /* Modify green table for 10M */
3058 /* Disable hiimpedance detection (RTCT) */
3064 rtl_apply_firmware(tp);
3066 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3068 /* For 4-corner performance improve */
3069 rtl_writephy(tp, 0x1f, 0x0005);
3070 rtl_writephy(tp, 0x05, 0x8b80);
3071 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3072 rtl_writephy(tp, 0x1f, 0x0000);
3074 /* PHY auto speed down */
3075 rtl_writephy(tp, 0x1f, 0x0007);
3076 rtl_writephy(tp, 0x1e, 0x002d);
3077 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3079 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3081 /* Improve 10M EEE waveform */
3082 rtl_writephy(tp, 0x1f, 0x0005);
3083 rtl_writephy(tp, 0x05, 0x8b86);
3084 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3085 rtl_writephy(tp, 0x1f, 0x0000);
3087 /* Improve 2-pair detection performance */
3088 rtl_writephy(tp, 0x1f, 0x0005);
3089 rtl_writephy(tp, 0x05, 0x8b85);
3090 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3091 rtl_writephy(tp, 0x1f, 0x0000);
3094 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3096 rtl_apply_firmware(tp);
3098 /* For 4-corner performance improve */
3099 rtl_writephy(tp, 0x1f, 0x0005);
3100 rtl_writephy(tp, 0x05, 0x8b80);
3101 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3102 rtl_writephy(tp, 0x1f, 0x0000);
3104 /* PHY auto speed down */
3105 rtl_writephy(tp, 0x1f, 0x0007);
3106 rtl_writephy(tp, 0x1e, 0x002d);
3107 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3109 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3111 /* Improve 10M EEE waveform */
3112 rtl_writephy(tp, 0x1f, 0x0005);
3113 rtl_writephy(tp, 0x05, 0x8b86);
3114 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3115 rtl_writephy(tp, 0x1f, 0x0000);
3118 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3120 static const struct phy_reg phy_reg_init[] = {
3127 rtl_writephy(tp, 0x1f, 0x0000);
3128 rtl_patchphy(tp, 0x11, 1 << 12);
3129 rtl_patchphy(tp, 0x19, 1 << 13);
3130 rtl_patchphy(tp, 0x10, 1 << 15);
3132 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3135 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3137 static const struct phy_reg phy_reg_init[] = {
3151 /* Disable ALDPS before ram code */
3152 rtl_writephy(tp, 0x1f, 0x0000);
3153 rtl_writephy(tp, 0x18, 0x0310);
3156 rtl_apply_firmware(tp);
3158 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3161 static void rtl_hw_phy_config(struct net_device *dev)
3163 struct rtl8169_private *tp = netdev_priv(dev);
3165 rtl8169_print_mac_version(tp);
3167 switch (tp->mac_version) {
3168 case RTL_GIGA_MAC_VER_01:
3170 case RTL_GIGA_MAC_VER_02:
3171 case RTL_GIGA_MAC_VER_03:
3172 rtl8169s_hw_phy_config(tp);
3174 case RTL_GIGA_MAC_VER_04:
3175 rtl8169sb_hw_phy_config(tp);
3177 case RTL_GIGA_MAC_VER_05:
3178 rtl8169scd_hw_phy_config(tp);
3180 case RTL_GIGA_MAC_VER_06:
3181 rtl8169sce_hw_phy_config(tp);
3183 case RTL_GIGA_MAC_VER_07:
3184 case RTL_GIGA_MAC_VER_08:
3185 case RTL_GIGA_MAC_VER_09:
3186 rtl8102e_hw_phy_config(tp);
3188 case RTL_GIGA_MAC_VER_11:
3189 rtl8168bb_hw_phy_config(tp);
3191 case RTL_GIGA_MAC_VER_12:
3192 rtl8168bef_hw_phy_config(tp);
3194 case RTL_GIGA_MAC_VER_17:
3195 rtl8168bef_hw_phy_config(tp);
3197 case RTL_GIGA_MAC_VER_18:
3198 rtl8168cp_1_hw_phy_config(tp);
3200 case RTL_GIGA_MAC_VER_19:
3201 rtl8168c_1_hw_phy_config(tp);
3203 case RTL_GIGA_MAC_VER_20:
3204 rtl8168c_2_hw_phy_config(tp);
3206 case RTL_GIGA_MAC_VER_21:
3207 rtl8168c_3_hw_phy_config(tp);
3209 case RTL_GIGA_MAC_VER_22:
3210 rtl8168c_4_hw_phy_config(tp);
3212 case RTL_GIGA_MAC_VER_23:
3213 case RTL_GIGA_MAC_VER_24:
3214 rtl8168cp_2_hw_phy_config(tp);
3216 case RTL_GIGA_MAC_VER_25:
3217 rtl8168d_1_hw_phy_config(tp);
3219 case RTL_GIGA_MAC_VER_26:
3220 rtl8168d_2_hw_phy_config(tp);
3222 case RTL_GIGA_MAC_VER_27:
3223 rtl8168d_3_hw_phy_config(tp);
3225 case RTL_GIGA_MAC_VER_28:
3226 rtl8168d_4_hw_phy_config(tp);
3228 case RTL_GIGA_MAC_VER_29:
3229 case RTL_GIGA_MAC_VER_30:
3230 rtl8105e_hw_phy_config(tp);
3232 case RTL_GIGA_MAC_VER_31:
3235 case RTL_GIGA_MAC_VER_32:
3236 case RTL_GIGA_MAC_VER_33:
3237 rtl8168e_1_hw_phy_config(tp);
3239 case RTL_GIGA_MAC_VER_34:
3240 rtl8168e_2_hw_phy_config(tp);
3242 case RTL_GIGA_MAC_VER_35:
3243 rtl8168f_1_hw_phy_config(tp);
3245 case RTL_GIGA_MAC_VER_36:
3246 rtl8168f_2_hw_phy_config(tp);
3254 static void rtl_phy_work(struct rtl8169_private *tp)
3256 struct timer_list *timer = &tp->timer;
3257 void __iomem *ioaddr = tp->mmio_addr;
3258 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3260 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3262 if (tp->phy_reset_pending(tp)) {
3264 * A busy loop could burn quite a few cycles on nowadays CPU.
3265 * Let's delay the execution of the timer for a few ticks.
3271 if (tp->link_ok(ioaddr))
3274 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3276 tp->phy_reset_enable(tp);
3279 mod_timer(timer, jiffies + timeout);
3282 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3284 if (!test_and_set_bit(flag, tp->wk.flags))
3285 schedule_work(&tp->wk.work);
3288 static void rtl8169_phy_timer(unsigned long __opaque)
3290 struct net_device *dev = (struct net_device *)__opaque;
3291 struct rtl8169_private *tp = netdev_priv(dev);
3293 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3296 #ifdef CONFIG_NET_POLL_CONTROLLER
3297 static void rtl8169_netpoll(struct net_device *dev)
3299 struct rtl8169_private *tp = netdev_priv(dev);
3301 rtl8169_interrupt(tp->pci_dev->irq, dev);
3305 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3306 void __iomem *ioaddr)
3309 pci_release_regions(pdev);
3310 pci_clear_mwi(pdev);
3311 pci_disable_device(pdev);
3315 static void rtl8169_phy_reset(struct net_device *dev,
3316 struct rtl8169_private *tp)
3320 tp->phy_reset_enable(tp);
3321 for (i = 0; i < 100; i++) {
3322 if (!tp->phy_reset_pending(tp))
3326 netif_err(tp, link, dev, "PHY reset failed\n");
3329 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3331 void __iomem *ioaddr = tp->mmio_addr;
3333 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3334 (RTL_R8(PHYstatus) & TBI_Enable);
3337 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3339 void __iomem *ioaddr = tp->mmio_addr;
3341 rtl_hw_phy_config(dev);
3343 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3344 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3348 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3350 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3351 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3353 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3354 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3356 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3357 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3360 rtl8169_phy_reset(dev, tp);
3362 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3363 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3364 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3365 (tp->mii.supports_gmii ?
3366 ADVERTISED_1000baseT_Half |
3367 ADVERTISED_1000baseT_Full : 0));
3369 if (rtl_tbi_enabled(tp))
3370 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3373 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3375 void __iomem *ioaddr = tp->mmio_addr;
3379 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3380 high = addr[4] | (addr[5] << 8);
3384 RTL_W8(Cfg9346, Cfg9346_Unlock);
3386 RTL_W32(MAC4, high);
3392 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3393 const struct exgmac_reg e[] = {
3394 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3395 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3396 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3397 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3401 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3404 RTL_W8(Cfg9346, Cfg9346_Lock);
3406 rtl_unlock_work(tp);
3409 static int rtl_set_mac_address(struct net_device *dev, void *p)
3411 struct rtl8169_private *tp = netdev_priv(dev);
3412 struct sockaddr *addr = p;
3414 if (!is_valid_ether_addr(addr->sa_data))
3415 return -EADDRNOTAVAIL;
3417 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3419 rtl_rar_set(tp, dev->dev_addr);
3424 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3426 struct rtl8169_private *tp = netdev_priv(dev);
3427 struct mii_ioctl_data *data = if_mii(ifr);
3429 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3432 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3433 struct mii_ioctl_data *data, int cmd)
3437 data->phy_id = 32; /* Internal PHY */
3441 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3445 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3451 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3456 static const struct rtl_cfg_info {
3457 void (*hw_start)(struct net_device *);
3458 unsigned int region;
3463 } rtl_cfg_infos [] = {
3465 .hw_start = rtl_hw_start_8169,
3468 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3469 .features = RTL_FEATURE_GMII,
3470 .default_ver = RTL_GIGA_MAC_VER_01,
3473 .hw_start = rtl_hw_start_8168,
3476 .event_slow = SYSErr | LinkChg | RxOverflow,
3477 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3478 .default_ver = RTL_GIGA_MAC_VER_11,
3481 .hw_start = rtl_hw_start_8101,
3484 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3486 .features = RTL_FEATURE_MSI,
3487 .default_ver = RTL_GIGA_MAC_VER_13,
3491 /* Cfg9346_Unlock assumed. */
3492 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3493 const struct rtl_cfg_info *cfg)
3495 void __iomem *ioaddr = tp->mmio_addr;
3499 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3500 if (cfg->features & RTL_FEATURE_MSI) {
3501 if (pci_enable_msi(tp->pci_dev)) {
3502 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3505 msi = RTL_FEATURE_MSI;
3508 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3509 RTL_W8(Config2, cfg2);
3513 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3515 if (tp->features & RTL_FEATURE_MSI) {
3516 pci_disable_msi(pdev);
3517 tp->features &= ~RTL_FEATURE_MSI;
3521 static const struct net_device_ops rtl8169_netdev_ops = {
3522 .ndo_open = rtl8169_open,
3523 .ndo_stop = rtl8169_close,
3524 .ndo_get_stats = rtl8169_get_stats,
3525 .ndo_start_xmit = rtl8169_start_xmit,
3526 .ndo_tx_timeout = rtl8169_tx_timeout,
3527 .ndo_validate_addr = eth_validate_addr,
3528 .ndo_change_mtu = rtl8169_change_mtu,
3529 .ndo_fix_features = rtl8169_fix_features,
3530 .ndo_set_features = rtl8169_set_features,
3531 .ndo_set_mac_address = rtl_set_mac_address,
3532 .ndo_do_ioctl = rtl8169_ioctl,
3533 .ndo_set_rx_mode = rtl_set_rx_mode,
3534 #ifdef CONFIG_NET_POLL_CONTROLLER
3535 .ndo_poll_controller = rtl8169_netpoll,
3540 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3542 struct mdio_ops *ops = &tp->mdio_ops;
3544 switch (tp->mac_version) {
3545 case RTL_GIGA_MAC_VER_27:
3546 ops->write = r8168dp_1_mdio_write;
3547 ops->read = r8168dp_1_mdio_read;
3549 case RTL_GIGA_MAC_VER_28:
3550 case RTL_GIGA_MAC_VER_31:
3551 ops->write = r8168dp_2_mdio_write;
3552 ops->read = r8168dp_2_mdio_read;
3555 ops->write = r8169_mdio_write;
3556 ops->read = r8169_mdio_read;
3561 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3563 void __iomem *ioaddr = tp->mmio_addr;
3565 switch (tp->mac_version) {
3566 case RTL_GIGA_MAC_VER_29:
3567 case RTL_GIGA_MAC_VER_30:
3568 case RTL_GIGA_MAC_VER_32:
3569 case RTL_GIGA_MAC_VER_33:
3570 case RTL_GIGA_MAC_VER_34:
3571 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3572 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3579 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3581 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3584 rtl_writephy(tp, 0x1f, 0x0000);
3585 rtl_writephy(tp, MII_BMCR, 0x0000);
3587 rtl_wol_suspend_quirk(tp);
3592 static void r810x_phy_power_down(struct rtl8169_private *tp)
3594 rtl_writephy(tp, 0x1f, 0x0000);
3595 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3598 static void r810x_phy_power_up(struct rtl8169_private *tp)
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3604 static void r810x_pll_power_down(struct rtl8169_private *tp)
3606 if (rtl_wol_pll_power_down(tp))
3609 r810x_phy_power_down(tp);
3612 static void r810x_pll_power_up(struct rtl8169_private *tp)
3614 r810x_phy_power_up(tp);
3617 static void r8168_phy_power_up(struct rtl8169_private *tp)
3619 rtl_writephy(tp, 0x1f, 0x0000);
3620 switch (tp->mac_version) {
3621 case RTL_GIGA_MAC_VER_11:
3622 case RTL_GIGA_MAC_VER_12:
3623 case RTL_GIGA_MAC_VER_17:
3624 case RTL_GIGA_MAC_VER_18:
3625 case RTL_GIGA_MAC_VER_19:
3626 case RTL_GIGA_MAC_VER_20:
3627 case RTL_GIGA_MAC_VER_21:
3628 case RTL_GIGA_MAC_VER_22:
3629 case RTL_GIGA_MAC_VER_23:
3630 case RTL_GIGA_MAC_VER_24:
3631 case RTL_GIGA_MAC_VER_25:
3632 case RTL_GIGA_MAC_VER_26:
3633 case RTL_GIGA_MAC_VER_27:
3634 case RTL_GIGA_MAC_VER_28:
3635 case RTL_GIGA_MAC_VER_31:
3636 rtl_writephy(tp, 0x0e, 0x0000);
3641 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3644 static void r8168_phy_power_down(struct rtl8169_private *tp)
3646 rtl_writephy(tp, 0x1f, 0x0000);
3647 switch (tp->mac_version) {
3648 case RTL_GIGA_MAC_VER_32:
3649 case RTL_GIGA_MAC_VER_33:
3650 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3653 case RTL_GIGA_MAC_VER_11:
3654 case RTL_GIGA_MAC_VER_12:
3655 case RTL_GIGA_MAC_VER_17:
3656 case RTL_GIGA_MAC_VER_18:
3657 case RTL_GIGA_MAC_VER_19:
3658 case RTL_GIGA_MAC_VER_20:
3659 case RTL_GIGA_MAC_VER_21:
3660 case RTL_GIGA_MAC_VER_22:
3661 case RTL_GIGA_MAC_VER_23:
3662 case RTL_GIGA_MAC_VER_24:
3663 case RTL_GIGA_MAC_VER_25:
3664 case RTL_GIGA_MAC_VER_26:
3665 case RTL_GIGA_MAC_VER_27:
3666 case RTL_GIGA_MAC_VER_28:
3667 case RTL_GIGA_MAC_VER_31:
3668 rtl_writephy(tp, 0x0e, 0x0200);
3670 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3675 static void r8168_pll_power_down(struct rtl8169_private *tp)
3677 void __iomem *ioaddr = tp->mmio_addr;
3679 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3680 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3681 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3682 r8168dp_check_dash(tp)) {
3686 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3687 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3688 (RTL_R16(CPlusCmd) & ASF)) {
3692 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3693 tp->mac_version == RTL_GIGA_MAC_VER_33)
3694 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3696 if (rtl_wol_pll_power_down(tp))
3699 r8168_phy_power_down(tp);
3701 switch (tp->mac_version) {
3702 case RTL_GIGA_MAC_VER_25:
3703 case RTL_GIGA_MAC_VER_26:
3704 case RTL_GIGA_MAC_VER_27:
3705 case RTL_GIGA_MAC_VER_28:
3706 case RTL_GIGA_MAC_VER_31:
3707 case RTL_GIGA_MAC_VER_32:
3708 case RTL_GIGA_MAC_VER_33:
3709 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3714 static void r8168_pll_power_up(struct rtl8169_private *tp)
3716 void __iomem *ioaddr = tp->mmio_addr;
3718 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3719 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3720 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3721 r8168dp_check_dash(tp)) {
3725 switch (tp->mac_version) {
3726 case RTL_GIGA_MAC_VER_25:
3727 case RTL_GIGA_MAC_VER_26:
3728 case RTL_GIGA_MAC_VER_27:
3729 case RTL_GIGA_MAC_VER_28:
3730 case RTL_GIGA_MAC_VER_31:
3731 case RTL_GIGA_MAC_VER_32:
3732 case RTL_GIGA_MAC_VER_33:
3733 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3737 r8168_phy_power_up(tp);
3740 static void rtl_generic_op(struct rtl8169_private *tp,
3741 void (*op)(struct rtl8169_private *))
3747 static void rtl_pll_power_down(struct rtl8169_private *tp)
3749 rtl_generic_op(tp, tp->pll_power_ops.down);
3752 static void rtl_pll_power_up(struct rtl8169_private *tp)
3754 rtl_generic_op(tp, tp->pll_power_ops.up);
3757 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3759 struct pll_power_ops *ops = &tp->pll_power_ops;
3761 switch (tp->mac_version) {
3762 case RTL_GIGA_MAC_VER_07:
3763 case RTL_GIGA_MAC_VER_08:
3764 case RTL_GIGA_MAC_VER_09:
3765 case RTL_GIGA_MAC_VER_10:
3766 case RTL_GIGA_MAC_VER_16:
3767 case RTL_GIGA_MAC_VER_29:
3768 case RTL_GIGA_MAC_VER_30:
3769 ops->down = r810x_pll_power_down;
3770 ops->up = r810x_pll_power_up;
3773 case RTL_GIGA_MAC_VER_11:
3774 case RTL_GIGA_MAC_VER_12:
3775 case RTL_GIGA_MAC_VER_17:
3776 case RTL_GIGA_MAC_VER_18:
3777 case RTL_GIGA_MAC_VER_19:
3778 case RTL_GIGA_MAC_VER_20:
3779 case RTL_GIGA_MAC_VER_21:
3780 case RTL_GIGA_MAC_VER_22:
3781 case RTL_GIGA_MAC_VER_23:
3782 case RTL_GIGA_MAC_VER_24:
3783 case RTL_GIGA_MAC_VER_25:
3784 case RTL_GIGA_MAC_VER_26:
3785 case RTL_GIGA_MAC_VER_27:
3786 case RTL_GIGA_MAC_VER_28:
3787 case RTL_GIGA_MAC_VER_31:
3788 case RTL_GIGA_MAC_VER_32:
3789 case RTL_GIGA_MAC_VER_33:
3790 case RTL_GIGA_MAC_VER_34:
3791 case RTL_GIGA_MAC_VER_35:
3792 case RTL_GIGA_MAC_VER_36:
3793 ops->down = r8168_pll_power_down;
3794 ops->up = r8168_pll_power_up;
3804 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3806 void __iomem *ioaddr = tp->mmio_addr;
3808 switch (tp->mac_version) {
3809 case RTL_GIGA_MAC_VER_01:
3810 case RTL_GIGA_MAC_VER_02:
3811 case RTL_GIGA_MAC_VER_03:
3812 case RTL_GIGA_MAC_VER_04:
3813 case RTL_GIGA_MAC_VER_05:
3814 case RTL_GIGA_MAC_VER_06:
3815 case RTL_GIGA_MAC_VER_10:
3816 case RTL_GIGA_MAC_VER_11:
3817 case RTL_GIGA_MAC_VER_12:
3818 case RTL_GIGA_MAC_VER_13:
3819 case RTL_GIGA_MAC_VER_14:
3820 case RTL_GIGA_MAC_VER_15:
3821 case RTL_GIGA_MAC_VER_16:
3822 case RTL_GIGA_MAC_VER_17:
3823 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3825 case RTL_GIGA_MAC_VER_18:
3826 case RTL_GIGA_MAC_VER_19:
3827 case RTL_GIGA_MAC_VER_20:
3828 case RTL_GIGA_MAC_VER_21:
3829 case RTL_GIGA_MAC_VER_22:
3830 case RTL_GIGA_MAC_VER_23:
3831 case RTL_GIGA_MAC_VER_24:
3832 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3835 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3840 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3842 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3845 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3847 rtl_generic_op(tp, tp->jumbo_ops.enable);
3850 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3852 rtl_generic_op(tp, tp->jumbo_ops.disable);
3855 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3857 void __iomem *ioaddr = tp->mmio_addr;
3859 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3860 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3861 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3864 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3866 void __iomem *ioaddr = tp->mmio_addr;
3868 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3869 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3870 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3873 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3875 void __iomem *ioaddr = tp->mmio_addr;
3877 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3880 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3882 void __iomem *ioaddr = tp->mmio_addr;
3884 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3887 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3889 void __iomem *ioaddr = tp->mmio_addr;
3891 RTL_W8(MaxTxPacketSize, 0x3f);
3892 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3893 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3894 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3897 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3899 void __iomem *ioaddr = tp->mmio_addr;
3901 RTL_W8(MaxTxPacketSize, 0x0c);
3902 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3903 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3904 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3907 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3909 rtl_tx_performance_tweak(tp->pci_dev,
3910 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3913 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3915 rtl_tx_performance_tweak(tp->pci_dev,
3916 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3919 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3921 void __iomem *ioaddr = tp->mmio_addr;
3923 r8168b_0_hw_jumbo_enable(tp);
3925 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3928 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3930 void __iomem *ioaddr = tp->mmio_addr;
3932 r8168b_0_hw_jumbo_disable(tp);
3934 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3937 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3939 struct jumbo_ops *ops = &tp->jumbo_ops;
3941 switch (tp->mac_version) {
3942 case RTL_GIGA_MAC_VER_11:
3943 ops->disable = r8168b_0_hw_jumbo_disable;
3944 ops->enable = r8168b_0_hw_jumbo_enable;
3946 case RTL_GIGA_MAC_VER_12:
3947 case RTL_GIGA_MAC_VER_17:
3948 ops->disable = r8168b_1_hw_jumbo_disable;
3949 ops->enable = r8168b_1_hw_jumbo_enable;
3951 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3952 case RTL_GIGA_MAC_VER_19:
3953 case RTL_GIGA_MAC_VER_20:
3954 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3955 case RTL_GIGA_MAC_VER_22:
3956 case RTL_GIGA_MAC_VER_23:
3957 case RTL_GIGA_MAC_VER_24:
3958 case RTL_GIGA_MAC_VER_25:
3959 case RTL_GIGA_MAC_VER_26:
3960 ops->disable = r8168c_hw_jumbo_disable;
3961 ops->enable = r8168c_hw_jumbo_enable;
3963 case RTL_GIGA_MAC_VER_27:
3964 case RTL_GIGA_MAC_VER_28:
3965 ops->disable = r8168dp_hw_jumbo_disable;
3966 ops->enable = r8168dp_hw_jumbo_enable;
3968 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3969 case RTL_GIGA_MAC_VER_32:
3970 case RTL_GIGA_MAC_VER_33:
3971 case RTL_GIGA_MAC_VER_34:
3972 ops->disable = r8168e_hw_jumbo_disable;
3973 ops->enable = r8168e_hw_jumbo_enable;
3977 * No action needed for jumbo frames with 8169.
3978 * No jumbo for 810x at all.
3981 ops->disable = NULL;
3987 static void rtl_hw_reset(struct rtl8169_private *tp)
3989 void __iomem *ioaddr = tp->mmio_addr;
3992 /* Soft reset the chip. */
3993 RTL_W8(ChipCmd, CmdReset);
3995 /* Check that the chip has finished the reset. */
3996 for (i = 0; i < 100; i++) {
3997 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4003 static int __devinit
4004 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4006 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4007 const unsigned int region = cfg->region;
4008 struct rtl8169_private *tp;
4009 struct mii_if_info *mii;
4010 struct net_device *dev;
4011 void __iomem *ioaddr;
4015 if (netif_msg_drv(&debug)) {
4016 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4017 MODULENAME, RTL8169_VERSION);
4020 dev = alloc_etherdev(sizeof (*tp));
4026 SET_NETDEV_DEV(dev, &pdev->dev);
4027 dev->netdev_ops = &rtl8169_netdev_ops;
4028 tp = netdev_priv(dev);
4031 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
4035 mii->mdio_read = rtl_mdio_read;
4036 mii->mdio_write = rtl_mdio_write;
4037 mii->phy_id_mask = 0x1f;
4038 mii->reg_num_mask = 0x1f;
4039 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4041 /* disable ASPM completely as that cause random device stop working
4042 * problems as well as full system hangs for some PCIe devices users */
4043 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4044 PCIE_LINK_STATE_CLKPM);
4046 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4047 rc = pci_enable_device(pdev);
4049 netif_err(tp, probe, dev, "enable failure\n");
4050 goto err_out_free_dev_1;
4053 if (pci_set_mwi(pdev) < 0)
4054 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4056 /* make sure PCI base addr 1 is MMIO */
4057 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4058 netif_err(tp, probe, dev,
4059 "region #%d not an MMIO resource, aborting\n",
4065 /* check for weird/broken PCI region reporting */
4066 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4067 netif_err(tp, probe, dev,
4068 "Invalid PCI region size(s), aborting\n");
4073 rc = pci_request_regions(pdev, MODULENAME);
4075 netif_err(tp, probe, dev, "could not request regions\n");
4079 tp->cp_cmd = RxChkSum;
4081 if ((sizeof(dma_addr_t) > 4) &&
4082 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4083 tp->cp_cmd |= PCIDAC;
4084 dev->features |= NETIF_F_HIGHDMA;
4086 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4088 netif_err(tp, probe, dev, "DMA configuration failed\n");
4089 goto err_out_free_res_3;
4093 /* ioremap MMIO region */
4094 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4096 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4098 goto err_out_free_res_3;
4100 tp->mmio_addr = ioaddr;
4102 if (!pci_is_pcie(pdev))
4103 netif_info(tp, probe, dev, "not PCI Express\n");
4105 /* Identify chip attached to board */
4106 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4110 rtl_irq_disable(tp);
4114 rtl_ack_events(tp, 0xffff);
4116 pci_set_master(pdev);
4119 * Pretend we are using VLANs; This bypasses a nasty bug where
4120 * Interrupts stop flowing on high load on 8110SCd controllers.
4122 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4123 tp->cp_cmd |= RxVlan;
4125 rtl_init_mdio_ops(tp);
4126 rtl_init_pll_power_ops(tp);
4127 rtl_init_jumbo_ops(tp);
4129 rtl8169_print_mac_version(tp);
4131 chipset = tp->mac_version;
4132 tp->txd_version = rtl_chip_infos[chipset].txd_version;
4134 RTL_W8(Cfg9346, Cfg9346_Unlock);
4135 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4136 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4137 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4138 tp->features |= RTL_FEATURE_WOL;
4139 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4140 tp->features |= RTL_FEATURE_WOL;
4141 tp->features |= rtl_try_msi(tp, cfg);
4142 RTL_W8(Cfg9346, Cfg9346_Lock);
4144 if (rtl_tbi_enabled(tp)) {
4145 tp->set_speed = rtl8169_set_speed_tbi;
4146 tp->get_settings = rtl8169_gset_tbi;
4147 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4148 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4149 tp->link_ok = rtl8169_tbi_link_ok;
4150 tp->do_ioctl = rtl_tbi_ioctl;
4152 tp->set_speed = rtl8169_set_speed_xmii;
4153 tp->get_settings = rtl8169_gset_xmii;
4154 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4155 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4156 tp->link_ok = rtl8169_xmii_link_ok;
4157 tp->do_ioctl = rtl_xmii_ioctl;
4160 mutex_init(&tp->wk.mutex);
4162 /* Get MAC address */
4163 for (i = 0; i < ETH_ALEN; i++)
4164 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4165 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4167 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4168 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4169 dev->irq = pdev->irq;
4170 dev->base_addr = (unsigned long) ioaddr;
4172 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4174 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4175 * properly for all devices */
4176 dev->features |= NETIF_F_RXCSUM |
4177 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4179 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4180 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4181 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4184 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4185 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4186 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4188 dev->hw_features |= NETIF_F_RXALL;
4189 dev->hw_features |= NETIF_F_RXFCS;
4191 tp->hw_start = cfg->hw_start;
4192 tp->event_slow = cfg->event_slow;
4194 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4195 ~(RxBOVF | RxFOVF) : ~0;
4197 init_timer(&tp->timer);
4198 tp->timer.data = (unsigned long) dev;
4199 tp->timer.function = rtl8169_phy_timer;
4201 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4203 rc = register_netdev(dev);
4207 pci_set_drvdata(pdev, dev);
4209 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4210 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4211 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4212 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4213 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4214 "tx checksumming: %s]\n",
4215 rtl_chip_infos[chipset].jumbo_max,
4216 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4219 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4220 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4221 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4222 rtl8168_driver_start(tp);
4225 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4227 if (pci_dev_run_wake(pdev))
4228 pm_runtime_put_noidle(&pdev->dev);
4230 netif_carrier_off(dev);
4236 rtl_disable_msi(pdev, tp);
4239 pci_release_regions(pdev);
4241 pci_clear_mwi(pdev);
4242 pci_disable_device(pdev);
4248 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4250 struct net_device *dev = pci_get_drvdata(pdev);
4251 struct rtl8169_private *tp = netdev_priv(dev);
4253 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4254 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4255 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4256 rtl8168_driver_stop(tp);
4259 cancel_work_sync(&tp->wk.work);
4261 unregister_netdev(dev);
4263 rtl_release_firmware(tp);
4265 if (pci_dev_run_wake(pdev))
4266 pm_runtime_get_noresume(&pdev->dev);
4268 /* restore original MAC address */
4269 rtl_rar_set(tp, dev->perm_addr);
4271 rtl_disable_msi(pdev, tp);
4272 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4273 pci_set_drvdata(pdev, NULL);
4276 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4278 struct rtl_fw *rtl_fw;
4282 name = rtl_lookup_firmware_name(tp);
4284 goto out_no_firmware;
4286 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4290 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4294 rc = rtl_check_firmware(tp, rtl_fw);
4296 goto err_release_firmware;
4298 tp->rtl_fw = rtl_fw;
4302 err_release_firmware:
4303 release_firmware(rtl_fw->fw);
4307 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4314 static void rtl_request_firmware(struct rtl8169_private *tp)
4316 if (IS_ERR(tp->rtl_fw))
4317 rtl_request_uncached_firmware(tp);
4320 static void rtl_task(struct work_struct *);
4322 static int rtl8169_open(struct net_device *dev)
4324 struct rtl8169_private *tp = netdev_priv(dev);
4325 void __iomem *ioaddr = tp->mmio_addr;
4326 struct pci_dev *pdev = tp->pci_dev;
4327 int retval = -ENOMEM;
4329 pm_runtime_get_sync(&pdev->dev);
4332 * Rx and Tx desscriptors needs 256 bytes alignment.
4333 * dma_alloc_coherent provides more.
4335 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4336 &tp->TxPhyAddr, GFP_KERNEL);
4337 if (!tp->TxDescArray)
4338 goto err_pm_runtime_put;
4340 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4341 &tp->RxPhyAddr, GFP_KERNEL);
4342 if (!tp->RxDescArray)
4345 retval = rtl8169_init_ring(dev);
4349 INIT_WORK(&tp->wk.work, rtl_task);
4353 rtl_request_firmware(tp);
4355 retval = request_irq(dev->irq, rtl8169_interrupt,
4356 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4359 goto err_release_fw_2;
4363 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4365 napi_enable(&tp->napi);
4367 rtl8169_init_phy(dev, tp);
4369 __rtl8169_set_features(dev, dev->features);
4371 rtl_pll_power_up(tp);
4375 netif_start_queue(dev);
4377 rtl_unlock_work(tp);
4379 tp->saved_wolopts = 0;
4380 pm_runtime_put_noidle(&pdev->dev);
4382 rtl8169_check_link_status(dev, tp, ioaddr);
4387 rtl_release_firmware(tp);
4388 rtl8169_rx_clear(tp);
4390 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4392 tp->RxDescArray = NULL;
4394 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4396 tp->TxDescArray = NULL;
4398 pm_runtime_put_noidle(&pdev->dev);
4402 static void rtl_rx_close(struct rtl8169_private *tp)
4404 void __iomem *ioaddr = tp->mmio_addr;
4406 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4409 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4411 void __iomem *ioaddr = tp->mmio_addr;
4413 /* Disable interrupts */
4414 rtl8169_irq_mask_and_ack(tp);
4418 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4419 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4420 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4421 while (RTL_R8(TxPoll) & NPQ)
4423 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4424 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4425 tp->mac_version == RTL_GIGA_MAC_VER_36) {
4426 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4427 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4430 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4437 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4439 void __iomem *ioaddr = tp->mmio_addr;
4441 /* Set DMA burst size and Interframe Gap Time */
4442 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4443 (InterFrameGap << TxInterFrameGapShift));
4446 static void rtl_hw_start(struct net_device *dev)
4448 struct rtl8169_private *tp = netdev_priv(dev);
4452 rtl_irq_enable_all(tp);
4455 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4456 void __iomem *ioaddr)
4459 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4460 * register to be written before TxDescAddrLow to work.
4461 * Switching from MMIO to I/O access fixes the issue as well.
4463 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4464 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4465 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4466 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4469 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4473 cmd = RTL_R16(CPlusCmd);
4474 RTL_W16(CPlusCmd, cmd);
4478 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4480 /* Low hurts. Let's disable the filtering. */
4481 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4484 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4486 static const struct rtl_cfg2_info {
4491 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4492 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4493 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4494 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4496 const struct rtl_cfg2_info *p = cfg2_info;
4500 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4501 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4502 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4503 RTL_W32(0x7c, p->val);
4509 static void rtl_hw_start_8169(struct net_device *dev)
4511 struct rtl8169_private *tp = netdev_priv(dev);
4512 void __iomem *ioaddr = tp->mmio_addr;
4513 struct pci_dev *pdev = tp->pci_dev;
4515 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4516 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4517 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4520 RTL_W8(Cfg9346, Cfg9346_Unlock);
4521 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4522 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4523 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4524 tp->mac_version == RTL_GIGA_MAC_VER_04)
4525 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4529 RTL_W8(EarlyTxThres, NoEarlyTx);
4531 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4533 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4534 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4535 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4536 tp->mac_version == RTL_GIGA_MAC_VER_04)
4537 rtl_set_rx_tx_config_registers(tp);
4539 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4541 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4542 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4543 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4544 "Bit-3 and bit-14 MUST be 1\n");
4545 tp->cp_cmd |= (1 << 14);
4548 RTL_W16(CPlusCmd, tp->cp_cmd);
4550 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4553 * Undocumented corner. Supposedly:
4554 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4556 RTL_W16(IntrMitigate, 0x0000);
4558 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4560 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4561 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4562 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4563 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4564 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4565 rtl_set_rx_tx_config_registers(tp);
4568 RTL_W8(Cfg9346, Cfg9346_Lock);
4570 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4573 RTL_W32(RxMissed, 0);
4575 rtl_set_rx_mode(dev);
4577 /* no early-rx interrupts */
4578 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4581 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4585 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4586 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4589 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4591 rtl_csi_access_enable(ioaddr, 0x17000000);
4594 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4596 rtl_csi_access_enable(ioaddr, 0x27000000);
4600 unsigned int offset;
4605 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4610 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4611 rtl_ephy_write(ioaddr, e->offset, w);
4616 static void rtl_disable_clock_request(struct pci_dev *pdev)
4618 int cap = pci_pcie_cap(pdev);
4623 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4624 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4625 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4629 static void rtl_enable_clock_request(struct pci_dev *pdev)
4631 int cap = pci_pcie_cap(pdev);
4636 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4637 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4638 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4642 #define R8168_CPCMD_QUIRK_MASK (\
4653 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4655 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4657 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4659 rtl_tx_performance_tweak(pdev,
4660 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4663 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4665 rtl_hw_start_8168bb(ioaddr, pdev);
4667 RTL_W8(MaxTxPacketSize, TxPacketMax);
4669 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4672 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4674 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4676 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4678 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4680 rtl_disable_clock_request(pdev);
4682 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4685 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4687 static const struct ephy_info e_info_8168cp[] = {
4688 { 0x01, 0, 0x0001 },
4689 { 0x02, 0x0800, 0x1000 },
4690 { 0x03, 0, 0x0042 },
4691 { 0x06, 0x0080, 0x0000 },
4695 rtl_csi_access_enable_2(ioaddr);
4697 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4699 __rtl_hw_start_8168cp(ioaddr, pdev);
4702 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4704 rtl_csi_access_enable_2(ioaddr);
4706 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4708 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4710 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4713 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4715 rtl_csi_access_enable_2(ioaddr);
4717 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4720 RTL_W8(DBG_REG, 0x20);
4722 RTL_W8(MaxTxPacketSize, TxPacketMax);
4724 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4726 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4729 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4731 static const struct ephy_info e_info_8168c_1[] = {
4732 { 0x02, 0x0800, 0x1000 },
4733 { 0x03, 0, 0x0002 },
4734 { 0x06, 0x0080, 0x0000 }
4737 rtl_csi_access_enable_2(ioaddr);
4739 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4741 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4743 __rtl_hw_start_8168cp(ioaddr, pdev);
4746 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4748 static const struct ephy_info e_info_8168c_2[] = {
4749 { 0x01, 0, 0x0001 },
4750 { 0x03, 0x0400, 0x0220 }
4753 rtl_csi_access_enable_2(ioaddr);
4755 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4757 __rtl_hw_start_8168cp(ioaddr, pdev);
4760 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4762 rtl_hw_start_8168c_2(ioaddr, pdev);
4765 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4767 rtl_csi_access_enable_2(ioaddr);
4769 __rtl_hw_start_8168cp(ioaddr, pdev);
4772 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4774 rtl_csi_access_enable_2(ioaddr);
4776 rtl_disable_clock_request(pdev);
4778 RTL_W8(MaxTxPacketSize, TxPacketMax);
4780 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4782 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4785 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4787 rtl_csi_access_enable_1(ioaddr);
4789 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4791 RTL_W8(MaxTxPacketSize, TxPacketMax);
4793 rtl_disable_clock_request(pdev);
4796 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4798 static const struct ephy_info e_info_8168d_4[] = {
4800 { 0x19, 0x20, 0x50 },
4805 rtl_csi_access_enable_1(ioaddr);
4807 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4809 RTL_W8(MaxTxPacketSize, TxPacketMax);
4811 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4812 const struct ephy_info *e = e_info_8168d_4 + i;
4815 w = rtl_ephy_read(ioaddr, e->offset);
4816 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4819 rtl_enable_clock_request(pdev);
4822 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4824 static const struct ephy_info e_info_8168e_1[] = {
4825 { 0x00, 0x0200, 0x0100 },
4826 { 0x00, 0x0000, 0x0004 },
4827 { 0x06, 0x0002, 0x0001 },
4828 { 0x06, 0x0000, 0x0030 },
4829 { 0x07, 0x0000, 0x2000 },
4830 { 0x00, 0x0000, 0x0020 },
4831 { 0x03, 0x5800, 0x2000 },
4832 { 0x03, 0x0000, 0x0001 },
4833 { 0x01, 0x0800, 0x1000 },
4834 { 0x07, 0x0000, 0x4000 },
4835 { 0x1e, 0x0000, 0x2000 },
4836 { 0x19, 0xffff, 0xfe6c },
4837 { 0x0a, 0x0000, 0x0040 }
4840 rtl_csi_access_enable_2(ioaddr);
4842 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4844 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4846 RTL_W8(MaxTxPacketSize, TxPacketMax);
4848 rtl_disable_clock_request(pdev);
4850 /* Reset tx FIFO pointer */
4851 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4852 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4854 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4857 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4859 static const struct ephy_info e_info_8168e_2[] = {
4860 { 0x09, 0x0000, 0x0080 },
4861 { 0x19, 0x0000, 0x0224 }
4864 rtl_csi_access_enable_1(ioaddr);
4866 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4868 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4870 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4871 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4872 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4873 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4874 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4875 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4876 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4877 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4880 RTL_W8(MaxTxPacketSize, EarlySize);
4882 rtl_disable_clock_request(pdev);
4884 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4885 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4887 /* Adjust EEE LED frequency */
4888 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4890 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4891 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4892 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4895 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4897 static const struct ephy_info e_info_8168f_1[] = {
4898 { 0x06, 0x00c0, 0x0020 },
4899 { 0x08, 0x0001, 0x0002 },
4900 { 0x09, 0x0000, 0x0080 },
4901 { 0x19, 0x0000, 0x0224 }
4904 rtl_csi_access_enable_1(ioaddr);
4906 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4908 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4910 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4911 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4912 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4913 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4914 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4915 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4916 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4917 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4918 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4919 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4920 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4923 RTL_W8(MaxTxPacketSize, EarlySize);
4925 rtl_disable_clock_request(pdev);
4927 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4928 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4930 /* Adjust EEE LED frequency */
4931 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4933 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4934 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4935 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4938 static void rtl_hw_start_8168(struct net_device *dev)
4940 struct rtl8169_private *tp = netdev_priv(dev);
4941 void __iomem *ioaddr = tp->mmio_addr;
4942 struct pci_dev *pdev = tp->pci_dev;
4944 RTL_W8(Cfg9346, Cfg9346_Unlock);
4946 RTL_W8(MaxTxPacketSize, TxPacketMax);
4948 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4950 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4952 RTL_W16(CPlusCmd, tp->cp_cmd);
4954 RTL_W16(IntrMitigate, 0x5151);
4956 /* Work around for RxFIFO overflow. */
4957 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4958 tp->event_slow |= RxFIFOOver | PCSTimeout;
4959 tp->event_slow &= ~RxOverflow;
4962 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4964 rtl_set_rx_mode(dev);
4966 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4967 (InterFrameGap << TxInterFrameGapShift));
4971 switch (tp->mac_version) {
4972 case RTL_GIGA_MAC_VER_11:
4973 rtl_hw_start_8168bb(ioaddr, pdev);
4976 case RTL_GIGA_MAC_VER_12:
4977 case RTL_GIGA_MAC_VER_17:
4978 rtl_hw_start_8168bef(ioaddr, pdev);
4981 case RTL_GIGA_MAC_VER_18:
4982 rtl_hw_start_8168cp_1(ioaddr, pdev);
4985 case RTL_GIGA_MAC_VER_19:
4986 rtl_hw_start_8168c_1(ioaddr, pdev);
4989 case RTL_GIGA_MAC_VER_20:
4990 rtl_hw_start_8168c_2(ioaddr, pdev);
4993 case RTL_GIGA_MAC_VER_21:
4994 rtl_hw_start_8168c_3(ioaddr, pdev);
4997 case RTL_GIGA_MAC_VER_22:
4998 rtl_hw_start_8168c_4(ioaddr, pdev);
5001 case RTL_GIGA_MAC_VER_23:
5002 rtl_hw_start_8168cp_2(ioaddr, pdev);
5005 case RTL_GIGA_MAC_VER_24:
5006 rtl_hw_start_8168cp_3(ioaddr, pdev);
5009 case RTL_GIGA_MAC_VER_25:
5010 case RTL_GIGA_MAC_VER_26:
5011 case RTL_GIGA_MAC_VER_27:
5012 rtl_hw_start_8168d(ioaddr, pdev);
5015 case RTL_GIGA_MAC_VER_28:
5016 rtl_hw_start_8168d_4(ioaddr, pdev);
5019 case RTL_GIGA_MAC_VER_31:
5020 rtl_hw_start_8168dp(ioaddr, pdev);
5023 case RTL_GIGA_MAC_VER_32:
5024 case RTL_GIGA_MAC_VER_33:
5025 rtl_hw_start_8168e_1(ioaddr, pdev);
5027 case RTL_GIGA_MAC_VER_34:
5028 rtl_hw_start_8168e_2(ioaddr, pdev);
5031 case RTL_GIGA_MAC_VER_35:
5032 case RTL_GIGA_MAC_VER_36:
5033 rtl_hw_start_8168f_1(ioaddr, pdev);
5037 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5038 dev->name, tp->mac_version);
5042 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5044 RTL_W8(Cfg9346, Cfg9346_Lock);
5046 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5049 #define R810X_CPCMD_QUIRK_MASK (\
5060 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5062 static const struct ephy_info e_info_8102e_1[] = {
5063 { 0x01, 0, 0x6e65 },
5064 { 0x02, 0, 0x091f },
5065 { 0x03, 0, 0xc2f9 },
5066 { 0x06, 0, 0xafb5 },
5067 { 0x07, 0, 0x0e00 },
5068 { 0x19, 0, 0xec80 },
5069 { 0x01, 0, 0x2e65 },
5074 rtl_csi_access_enable_2(ioaddr);
5076 RTL_W8(DBG_REG, FIX_NAK_1);
5078 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5081 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5082 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5084 cfg1 = RTL_R8(Config1);
5085 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5086 RTL_W8(Config1, cfg1 & ~LEDS0);
5088 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5091 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5093 rtl_csi_access_enable_2(ioaddr);
5095 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5097 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5098 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5101 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5103 rtl_hw_start_8102e_2(ioaddr, pdev);
5105 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5108 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5110 static const struct ephy_info e_info_8105e_1[] = {
5111 { 0x07, 0, 0x4000 },
5112 { 0x19, 0, 0x0200 },
5113 { 0x19, 0, 0x0020 },
5114 { 0x1e, 0, 0x2000 },
5115 { 0x03, 0, 0x0001 },
5116 { 0x19, 0, 0x0100 },
5117 { 0x19, 0, 0x0004 },
5121 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5122 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5124 /* Disable Early Tally Counter */
5125 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5127 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5128 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5130 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5133 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5135 rtl_hw_start_8105e_1(ioaddr, pdev);
5136 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5139 static void rtl_hw_start_8101(struct net_device *dev)
5141 struct rtl8169_private *tp = netdev_priv(dev);
5142 void __iomem *ioaddr = tp->mmio_addr;
5143 struct pci_dev *pdev = tp->pci_dev;
5145 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5146 tp->event_slow &= ~RxFIFOOver;
5148 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5149 tp->mac_version == RTL_GIGA_MAC_VER_16) {
5150 int cap = pci_pcie_cap(pdev);
5153 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5154 PCI_EXP_DEVCTL_NOSNOOP_EN);
5158 RTL_W8(Cfg9346, Cfg9346_Unlock);
5160 switch (tp->mac_version) {
5161 case RTL_GIGA_MAC_VER_07:
5162 rtl_hw_start_8102e_1(ioaddr, pdev);
5165 case RTL_GIGA_MAC_VER_08:
5166 rtl_hw_start_8102e_3(ioaddr, pdev);
5169 case RTL_GIGA_MAC_VER_09:
5170 rtl_hw_start_8102e_2(ioaddr, pdev);
5173 case RTL_GIGA_MAC_VER_29:
5174 rtl_hw_start_8105e_1(ioaddr, pdev);
5176 case RTL_GIGA_MAC_VER_30:
5177 rtl_hw_start_8105e_2(ioaddr, pdev);
5181 RTL_W8(Cfg9346, Cfg9346_Lock);
5183 RTL_W8(MaxTxPacketSize, TxPacketMax);
5185 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5187 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5188 RTL_W16(CPlusCmd, tp->cp_cmd);
5190 RTL_W16(IntrMitigate, 0x0000);
5192 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5194 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5195 rtl_set_rx_tx_config_registers(tp);
5199 rtl_set_rx_mode(dev);
5201 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5204 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5206 struct rtl8169_private *tp = netdev_priv(dev);
5208 if (new_mtu < ETH_ZLEN ||
5209 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5212 if (new_mtu > ETH_DATA_LEN)
5213 rtl_hw_jumbo_enable(tp);
5215 rtl_hw_jumbo_disable(tp);
5218 netdev_update_features(dev);
5223 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5225 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5226 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5229 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5230 void **data_buff, struct RxDesc *desc)
5232 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5237 rtl8169_make_unusable_by_asic(desc);
5240 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5242 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5244 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5247 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5250 desc->addr = cpu_to_le64(mapping);
5252 rtl8169_mark_to_asic(desc, rx_buf_sz);
5255 static inline void *rtl8169_align(void *data)
5257 return (void *)ALIGN((long)data, 16);
5260 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5261 struct RxDesc *desc)
5265 struct device *d = &tp->pci_dev->dev;
5266 struct net_device *dev = tp->dev;
5267 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5269 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5273 if (rtl8169_align(data) != data) {
5275 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5280 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5282 if (unlikely(dma_mapping_error(d, mapping))) {
5283 if (net_ratelimit())
5284 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5288 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5296 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5300 for (i = 0; i < NUM_RX_DESC; i++) {
5301 if (tp->Rx_databuff[i]) {
5302 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5303 tp->RxDescArray + i);
5308 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5310 desc->opts1 |= cpu_to_le32(RingEnd);
5313 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5317 for (i = 0; i < NUM_RX_DESC; i++) {
5320 if (tp->Rx_databuff[i])
5323 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5325 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5328 tp->Rx_databuff[i] = data;
5331 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5335 rtl8169_rx_clear(tp);
5339 static int rtl8169_init_ring(struct net_device *dev)
5341 struct rtl8169_private *tp = netdev_priv(dev);
5343 rtl8169_init_ring_indexes(tp);
5345 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5346 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5348 return rtl8169_rx_fill(tp);
5351 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5352 struct TxDesc *desc)
5354 unsigned int len = tx_skb->len;
5356 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5364 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5369 for (i = 0; i < n; i++) {
5370 unsigned int entry = (start + i) % NUM_TX_DESC;
5371 struct ring_info *tx_skb = tp->tx_skb + entry;
5372 unsigned int len = tx_skb->len;
5375 struct sk_buff *skb = tx_skb->skb;
5377 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5378 tp->TxDescArray + entry);
5380 tp->dev->stats.tx_dropped++;
5388 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5390 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5391 tp->cur_tx = tp->dirty_tx = 0;
5394 static void rtl_reset_work(struct rtl8169_private *tp)
5396 struct net_device *dev = tp->dev;
5399 napi_disable(&tp->napi);
5400 netif_stop_queue(dev);
5401 synchronize_sched();
5403 rtl8169_hw_reset(tp);
5405 for (i = 0; i < NUM_RX_DESC; i++)
5406 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5408 rtl8169_tx_clear(tp);
5409 rtl8169_init_ring_indexes(tp);
5411 napi_enable(&tp->napi);
5413 netif_wake_queue(dev);
5414 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5417 static void rtl8169_tx_timeout(struct net_device *dev)
5419 struct rtl8169_private *tp = netdev_priv(dev);
5421 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5424 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5427 struct skb_shared_info *info = skb_shinfo(skb);
5428 unsigned int cur_frag, entry;
5429 struct TxDesc * uninitialized_var(txd);
5430 struct device *d = &tp->pci_dev->dev;
5433 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5434 const skb_frag_t *frag = info->frags + cur_frag;
5439 entry = (entry + 1) % NUM_TX_DESC;
5441 txd = tp->TxDescArray + entry;
5442 len = skb_frag_size(frag);
5443 addr = skb_frag_address(frag);
5444 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5445 if (unlikely(dma_mapping_error(d, mapping))) {
5446 if (net_ratelimit())
5447 netif_err(tp, drv, tp->dev,
5448 "Failed to map TX fragments DMA!\n");
5452 /* Anti gcc 2.95.3 bugware (sic) */
5453 status = opts[0] | len |
5454 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5456 txd->opts1 = cpu_to_le32(status);
5457 txd->opts2 = cpu_to_le32(opts[1]);
5458 txd->addr = cpu_to_le64(mapping);
5460 tp->tx_skb[entry].len = len;
5464 tp->tx_skb[entry].skb = skb;
5465 txd->opts1 |= cpu_to_le32(LastFrag);
5471 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5475 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5476 struct sk_buff *skb, u32 *opts)
5478 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5479 u32 mss = skb_shinfo(skb)->gso_size;
5480 int offset = info->opts_offset;
5484 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5485 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5486 const struct iphdr *ip = ip_hdr(skb);
5488 if (ip->protocol == IPPROTO_TCP)
5489 opts[offset] |= info->checksum.tcp;
5490 else if (ip->protocol == IPPROTO_UDP)
5491 opts[offset] |= info->checksum.udp;
5497 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5498 struct net_device *dev)
5500 struct rtl8169_private *tp = netdev_priv(dev);
5501 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5502 struct TxDesc *txd = tp->TxDescArray + entry;
5503 void __iomem *ioaddr = tp->mmio_addr;
5504 struct device *d = &tp->pci_dev->dev;
5510 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5511 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5515 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5518 len = skb_headlen(skb);
5519 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5520 if (unlikely(dma_mapping_error(d, mapping))) {
5521 if (net_ratelimit())
5522 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5526 tp->tx_skb[entry].len = len;
5527 txd->addr = cpu_to_le64(mapping);
5529 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5532 rtl8169_tso_csum(tp, skb, opts);
5534 frags = rtl8169_xmit_frags(tp, skb, opts);
5538 opts[0] |= FirstFrag;
5540 opts[0] |= FirstFrag | LastFrag;
5541 tp->tx_skb[entry].skb = skb;
5544 txd->opts2 = cpu_to_le32(opts[1]);
5548 /* Anti gcc 2.95.3 bugware (sic) */
5549 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5550 txd->opts1 = cpu_to_le32(status);
5552 tp->cur_tx += frags + 1;
5556 RTL_W8(TxPoll, NPQ);
5560 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5561 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5562 * not miss a ring update when it notices a stopped queue.
5565 netif_stop_queue(dev);
5566 /* Sync with rtl_tx:
5567 * - publish queue status and cur_tx ring index (write barrier)
5568 * - refresh dirty_tx ring index (read barrier).
5569 * May the current thread have a pessimistic view of the ring
5570 * status and forget to wake up queue, a racing rtl_tx thread
5574 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5575 netif_wake_queue(dev);
5578 return NETDEV_TX_OK;
5581 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5584 dev->stats.tx_dropped++;
5585 return NETDEV_TX_OK;
5588 netif_stop_queue(dev);
5589 dev->stats.tx_dropped++;
5590 return NETDEV_TX_BUSY;
5593 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5595 struct rtl8169_private *tp = netdev_priv(dev);
5596 struct pci_dev *pdev = tp->pci_dev;
5597 u16 pci_status, pci_cmd;
5599 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5600 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5602 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5603 pci_cmd, pci_status);
5606 * The recovery sequence below admits a very elaborated explanation:
5607 * - it seems to work;
5608 * - I did not see what else could be done;
5609 * - it makes iop3xx happy.
5611 * Feel free to adjust to your needs.
5613 if (pdev->broken_parity_status)
5614 pci_cmd &= ~PCI_COMMAND_PARITY;
5616 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5618 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5620 pci_write_config_word(pdev, PCI_STATUS,
5621 pci_status & (PCI_STATUS_DETECTED_PARITY |
5622 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5623 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5625 /* The infamous DAC f*ckup only happens at boot time */
5626 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5627 void __iomem *ioaddr = tp->mmio_addr;
5629 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5630 tp->cp_cmd &= ~PCIDAC;
5631 RTL_W16(CPlusCmd, tp->cp_cmd);
5632 dev->features &= ~NETIF_F_HIGHDMA;
5635 rtl8169_hw_reset(tp);
5637 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5640 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5642 unsigned int dirty_tx, tx_left;
5644 dirty_tx = tp->dirty_tx;
5646 tx_left = tp->cur_tx - dirty_tx;
5648 while (tx_left > 0) {
5649 unsigned int entry = dirty_tx % NUM_TX_DESC;
5650 struct ring_info *tx_skb = tp->tx_skb + entry;
5654 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5655 if (status & DescOwn)
5658 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5659 tp->TxDescArray + entry);
5660 if (status & LastFrag) {
5661 dev->stats.tx_packets++;
5662 dev->stats.tx_bytes += tx_skb->skb->len;
5663 dev_kfree_skb(tx_skb->skb);
5670 if (tp->dirty_tx != dirty_tx) {
5671 tp->dirty_tx = dirty_tx;
5672 /* Sync with rtl8169_start_xmit:
5673 * - publish dirty_tx ring index (write barrier)
5674 * - refresh cur_tx ring index and queue status (read barrier)
5675 * May the current thread miss the stopped queue condition,
5676 * a racing xmit thread can only have a right view of the
5680 if (netif_queue_stopped(dev) &&
5681 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5682 netif_wake_queue(dev);
5685 * 8168 hack: TxPoll requests are lost when the Tx packets are
5686 * too close. Let's kick an extra TxPoll request when a burst
5687 * of start_xmit activity is detected (if it is not detected,
5688 * it is slow enough). -- FR
5690 if (tp->cur_tx != dirty_tx) {
5691 void __iomem *ioaddr = tp->mmio_addr;
5693 RTL_W8(TxPoll, NPQ);
5698 static inline int rtl8169_fragmented_frame(u32 status)
5700 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5703 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5705 u32 status = opts1 & RxProtoMask;
5707 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5708 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5709 skb->ip_summed = CHECKSUM_UNNECESSARY;
5711 skb_checksum_none_assert(skb);
5714 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5715 struct rtl8169_private *tp,
5719 struct sk_buff *skb;
5720 struct device *d = &tp->pci_dev->dev;
5722 data = rtl8169_align(data);
5723 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5725 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5727 memcpy(skb->data, data, pkt_size);
5728 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5733 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5735 unsigned int cur_rx, rx_left;
5738 cur_rx = tp->cur_rx;
5739 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5740 rx_left = min(rx_left, budget);
5742 for (; rx_left > 0; rx_left--, cur_rx++) {
5743 unsigned int entry = cur_rx % NUM_RX_DESC;
5744 struct RxDesc *desc = tp->RxDescArray + entry;
5748 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5750 if (status & DescOwn)
5752 if (unlikely(status & RxRES)) {
5753 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5755 dev->stats.rx_errors++;
5756 if (status & (RxRWT | RxRUNT))
5757 dev->stats.rx_length_errors++;
5759 dev->stats.rx_crc_errors++;
5760 if (status & RxFOVF) {
5761 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5762 dev->stats.rx_fifo_errors++;
5764 if ((status & (RxRUNT | RxCRC)) &&
5765 !(status & (RxRWT | RxFOVF)) &&
5766 (dev->features & NETIF_F_RXALL))
5769 rtl8169_mark_to_asic(desc, rx_buf_sz);
5771 struct sk_buff *skb;
5776 addr = le64_to_cpu(desc->addr);
5777 if (likely(!(dev->features & NETIF_F_RXFCS)))
5778 pkt_size = (status & 0x00003fff) - 4;
5780 pkt_size = status & 0x00003fff;
5783 * The driver does not support incoming fragmented
5784 * frames. They are seen as a symptom of over-mtu
5787 if (unlikely(rtl8169_fragmented_frame(status))) {
5788 dev->stats.rx_dropped++;
5789 dev->stats.rx_length_errors++;
5790 rtl8169_mark_to_asic(desc, rx_buf_sz);
5794 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5795 tp, pkt_size, addr);
5796 rtl8169_mark_to_asic(desc, rx_buf_sz);
5798 dev->stats.rx_dropped++;
5802 rtl8169_rx_csum(skb, status);
5803 skb_put(skb, pkt_size);
5804 skb->protocol = eth_type_trans(skb, dev);
5806 rtl8169_rx_vlan_tag(desc, skb);
5808 napi_gro_receive(&tp->napi, skb);
5810 dev->stats.rx_bytes += pkt_size;
5811 dev->stats.rx_packets++;
5814 /* Work around for AMD plateform. */
5815 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5816 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5822 count = cur_rx - tp->cur_rx;
5823 tp->cur_rx = cur_rx;
5825 tp->dirty_rx += count;
5830 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5832 struct net_device *dev = dev_instance;
5833 struct rtl8169_private *tp = netdev_priv(dev);
5837 status = rtl_get_events(tp);
5838 if (status && status != 0xffff) {
5839 status &= RTL_EVENT_NAPI | tp->event_slow;
5843 rtl_irq_disable(tp);
5844 napi_schedule(&tp->napi);
5847 return IRQ_RETVAL(handled);
5851 * Workqueue context.
5853 static void rtl_slow_event_work(struct rtl8169_private *tp)
5855 struct net_device *dev = tp->dev;
5858 status = rtl_get_events(tp) & tp->event_slow;
5859 rtl_ack_events(tp, status);
5861 if (unlikely(status & RxFIFOOver)) {
5862 switch (tp->mac_version) {
5863 /* Work around for rx fifo overflow */
5864 case RTL_GIGA_MAC_VER_11:
5865 netif_stop_queue(dev);
5866 /* XXX - Hack alert. See rtl_task(). */
5867 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5873 if (unlikely(status & SYSErr))
5874 rtl8169_pcierr_interrupt(dev);
5876 if (status & LinkChg)
5877 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5879 napi_disable(&tp->napi);
5880 rtl_irq_disable(tp);
5882 napi_enable(&tp->napi);
5883 napi_schedule(&tp->napi);
5886 static void rtl_task(struct work_struct *work)
5888 static const struct {
5890 void (*action)(struct rtl8169_private *);
5892 /* XXX - keep rtl_slow_event_work() as first element. */
5893 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
5894 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
5895 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
5897 struct rtl8169_private *tp =
5898 container_of(work, struct rtl8169_private, wk.work);
5899 struct net_device *dev = tp->dev;
5904 if (!netif_running(dev) ||
5905 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5908 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5911 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5913 rtl_work[i].action(tp);
5917 rtl_unlock_work(tp);
5920 static int rtl8169_poll(struct napi_struct *napi, int budget)
5922 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5923 struct net_device *dev = tp->dev;
5924 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5928 status = rtl_get_events(tp);
5929 rtl_ack_events(tp, status & ~tp->event_slow);
5931 if (status & RTL_EVENT_NAPI_RX)
5932 work_done = rtl_rx(dev, tp, (u32) budget);
5934 if (status & RTL_EVENT_NAPI_TX)
5937 if (status & tp->event_slow) {
5938 enable_mask &= ~tp->event_slow;
5940 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5943 if (work_done < budget) {
5944 napi_complete(napi);
5946 rtl_irq_enable(tp, enable_mask);
5953 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5955 struct rtl8169_private *tp = netdev_priv(dev);
5957 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5960 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5961 RTL_W32(RxMissed, 0);
5964 static void rtl8169_down(struct net_device *dev)
5966 struct rtl8169_private *tp = netdev_priv(dev);
5967 void __iomem *ioaddr = tp->mmio_addr;
5969 del_timer_sync(&tp->timer);
5971 napi_disable(&tp->napi);
5972 netif_stop_queue(dev);
5974 rtl8169_hw_reset(tp);
5976 * At this point device interrupts can not be enabled in any function,
5977 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5978 * and napi is disabled (rtl8169_poll).
5980 rtl8169_rx_missed(dev, ioaddr);
5982 /* Give a racing hard_start_xmit a few cycles to complete. */
5983 synchronize_sched();
5985 rtl8169_tx_clear(tp);
5987 rtl8169_rx_clear(tp);
5989 rtl_pll_power_down(tp);
5992 static int rtl8169_close(struct net_device *dev)
5994 struct rtl8169_private *tp = netdev_priv(dev);
5995 struct pci_dev *pdev = tp->pci_dev;
5997 pm_runtime_get_sync(&pdev->dev);
5999 /* Update counters before going down */
6000 rtl8169_update_counters(dev);
6003 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6006 rtl_unlock_work(tp);
6008 free_irq(dev->irq, dev);
6010 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6012 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6014 tp->TxDescArray = NULL;
6015 tp->RxDescArray = NULL;
6017 pm_runtime_put_sync(&pdev->dev);
6022 static void rtl_set_rx_mode(struct net_device *dev)
6024 struct rtl8169_private *tp = netdev_priv(dev);
6025 void __iomem *ioaddr = tp->mmio_addr;
6026 u32 mc_filter[2]; /* Multicast hash filter */
6030 if (dev->flags & IFF_PROMISC) {
6031 /* Unconditionally log net taps. */
6032 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6034 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6036 mc_filter[1] = mc_filter[0] = 0xffffffff;
6037 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6038 (dev->flags & IFF_ALLMULTI)) {
6039 /* Too many to filter perfectly -- accept all multicasts. */
6040 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6041 mc_filter[1] = mc_filter[0] = 0xffffffff;
6043 struct netdev_hw_addr *ha;
6045 rx_mode = AcceptBroadcast | AcceptMyPhys;
6046 mc_filter[1] = mc_filter[0] = 0;
6047 netdev_for_each_mc_addr(ha, dev) {
6048 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6049 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6050 rx_mode |= AcceptMulticast;
6054 if (dev->features & NETIF_F_RXALL)
6055 rx_mode |= (AcceptErr | AcceptRunt);
6057 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6059 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6060 u32 data = mc_filter[0];
6062 mc_filter[0] = swab32(mc_filter[1]);
6063 mc_filter[1] = swab32(data);
6066 RTL_W32(MAR0 + 4, mc_filter[1]);
6067 RTL_W32(MAR0 + 0, mc_filter[0]);
6069 RTL_W32(RxConfig, tmp);
6073 * rtl8169_get_stats - Get rtl8169 read/write statistics
6074 * @dev: The Ethernet Device to get statistics for
6076 * Get TX/RX statistics for rtl8169
6078 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6080 struct rtl8169_private *tp = netdev_priv(dev);
6081 void __iomem *ioaddr = tp->mmio_addr;
6083 if (netif_running(dev))
6084 rtl8169_rx_missed(dev, ioaddr);
6089 static void rtl8169_net_suspend(struct net_device *dev)
6091 struct rtl8169_private *tp = netdev_priv(dev);
6093 if (!netif_running(dev))
6096 netif_device_detach(dev);
6097 netif_stop_queue(dev);
6100 napi_disable(&tp->napi);
6101 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6102 rtl_unlock_work(tp);
6104 rtl_pll_power_down(tp);
6109 static int rtl8169_suspend(struct device *device)
6111 struct pci_dev *pdev = to_pci_dev(device);
6112 struct net_device *dev = pci_get_drvdata(pdev);
6114 rtl8169_net_suspend(dev);
6119 static void __rtl8169_resume(struct net_device *dev)
6121 struct rtl8169_private *tp = netdev_priv(dev);
6123 netif_device_attach(dev);
6125 rtl_pll_power_up(tp);
6127 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6129 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6132 static int rtl8169_resume(struct device *device)
6134 struct pci_dev *pdev = to_pci_dev(device);
6135 struct net_device *dev = pci_get_drvdata(pdev);
6136 struct rtl8169_private *tp = netdev_priv(dev);
6138 rtl8169_init_phy(dev, tp);
6140 if (netif_running(dev))
6141 __rtl8169_resume(dev);
6146 static int rtl8169_runtime_suspend(struct device *device)
6148 struct pci_dev *pdev = to_pci_dev(device);
6149 struct net_device *dev = pci_get_drvdata(pdev);
6150 struct rtl8169_private *tp = netdev_priv(dev);
6152 if (!tp->TxDescArray)
6156 tp->saved_wolopts = __rtl8169_get_wol(tp);
6157 __rtl8169_set_wol(tp, WAKE_ANY);
6158 rtl_unlock_work(tp);
6160 rtl8169_net_suspend(dev);
6165 static int rtl8169_runtime_resume(struct device *device)
6167 struct pci_dev *pdev = to_pci_dev(device);
6168 struct net_device *dev = pci_get_drvdata(pdev);
6169 struct rtl8169_private *tp = netdev_priv(dev);
6171 if (!tp->TxDescArray)
6175 __rtl8169_set_wol(tp, tp->saved_wolopts);
6176 tp->saved_wolopts = 0;
6177 rtl_unlock_work(tp);
6179 rtl8169_init_phy(dev, tp);
6181 __rtl8169_resume(dev);
6186 static int rtl8169_runtime_idle(struct device *device)
6188 struct pci_dev *pdev = to_pci_dev(device);
6189 struct net_device *dev = pci_get_drvdata(pdev);
6190 struct rtl8169_private *tp = netdev_priv(dev);
6192 return tp->TxDescArray ? -EBUSY : 0;
6195 static const struct dev_pm_ops rtl8169_pm_ops = {
6196 .suspend = rtl8169_suspend,
6197 .resume = rtl8169_resume,
6198 .freeze = rtl8169_suspend,
6199 .thaw = rtl8169_resume,
6200 .poweroff = rtl8169_suspend,
6201 .restore = rtl8169_resume,
6202 .runtime_suspend = rtl8169_runtime_suspend,
6203 .runtime_resume = rtl8169_runtime_resume,
6204 .runtime_idle = rtl8169_runtime_idle,
6207 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6209 #else /* !CONFIG_PM */
6211 #define RTL8169_PM_OPS NULL
6213 #endif /* !CONFIG_PM */
6215 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6217 void __iomem *ioaddr = tp->mmio_addr;
6219 /* WoL fails with 8168b when the receiver is disabled. */
6220 switch (tp->mac_version) {
6221 case RTL_GIGA_MAC_VER_11:
6222 case RTL_GIGA_MAC_VER_12:
6223 case RTL_GIGA_MAC_VER_17:
6224 pci_clear_master(tp->pci_dev);
6226 RTL_W8(ChipCmd, CmdRxEnb);
6235 static void rtl_shutdown(struct pci_dev *pdev)
6237 struct net_device *dev = pci_get_drvdata(pdev);
6238 struct rtl8169_private *tp = netdev_priv(dev);
6240 rtl8169_net_suspend(dev);
6242 /* Restore original MAC address */
6243 rtl_rar_set(tp, dev->perm_addr);
6245 rtl8169_hw_reset(tp);
6247 if (system_state == SYSTEM_POWER_OFF) {
6248 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6249 rtl_wol_suspend_quirk(tp);
6250 rtl_wol_shutdown_quirk(tp);
6253 pci_wake_from_d3(pdev, true);
6254 pci_set_power_state(pdev, PCI_D3hot);
6258 static struct pci_driver rtl8169_pci_driver = {
6260 .id_table = rtl8169_pci_tbl,
6261 .probe = rtl8169_init_one,
6262 .remove = __devexit_p(rtl8169_remove_one),
6263 .shutdown = rtl_shutdown,
6264 .driver.pm = RTL8169_PM_OPS,
6267 static int __init rtl8169_init_module(void)
6269 return pci_register_driver(&rtl8169_pci_driver);
6272 static void __exit rtl8169_cleanup_module(void)
6274 pci_unregister_driver(&rtl8169_pci_driver);
6277 module_init(rtl8169_init_module);
6278 module_exit(rtl8169_cleanup_module);