drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         struct mdio_ops {
 659                 void (*write)(struct rtl8169_private *, int, int);
 660                 int (*read)(struct rtl8169_private *, int);
 661         } mdio_ops;
 662
 663         struct jumbo_ops {
 664                 void (*enable)(struct rtl8169_private *);
 665                 void (*disable)(struct rtl8169_private *);
 666         } jumbo_ops;
 667
 668         void (*hw_start)(struct rtl8169_private *tp);
 669         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 670
 671         struct {
 672                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 673                 struct mutex mutex;
 674                 struct work_struct work;
 675         } wk;
 676
 677         unsigned irq_enabled:1;
 678         unsigned supports_gmii:1;
 679         dma_addr_t counters_phys_addr;
 680         struct rtl8169_counters *counters;
 681         struct rtl8169_tc_offsets tc_offset;
 682         u32 saved_wolopts;
 683
 684         const char *fw_name;
 685         struct rtl_fw {
 686                 rtl_fw_write_t phy_write;
 687                 rtl_fw_read_t phy_read;
 688                 rtl_fw_write_t mac_mcu_write;
 689                 rtl_fw_read_t mac_mcu_read;
 690                 const struct firmware *fw;
 691
 692 #define RTL_VER_SIZE            32
 693
 694                 char version[RTL_VER_SIZE];
 695
 696                 struct rtl_fw_phy_action {
 697                         __le32 *code;
 698                         size_t size;
 699                 } phy_action;
 700         } *rtl_fw;
 701
 702         u32 ocp_base;
 703 };
 704
 705 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 706
 707 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 708 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 709 module_param_named(debug, debug.msg_enable, int, 0);
 710 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 711 MODULE_SOFTDEP("pre: realtek");
 712 MODULE_LICENSE("GPL");
 713 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 714 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 717 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 718 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 719 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 720 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 721 MODULE_FIRMWARE(FIRMWARE_8402_1);
 722 MODULE_FIRMWARE(FIRMWARE_8411_1);
 723 MODULE_FIRMWARE(FIRMWARE_8411_2);
 724 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 725 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 726 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 727 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 728 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 729 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 730 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 731 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 732
 733 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 734 {
 735         return &tp->pci_dev->dev;
 736 }
 737
 738 static void rtl_lock_work(struct rtl8169_private *tp)
 739 {
 740         mutex_lock(&tp->wk.mutex);
 741 }
 742
 743 static void rtl_unlock_work(struct rtl8169_private *tp)
 744 {
 745         mutex_unlock(&tp->wk.mutex);
 746 }
 747
 748 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 749 {
 750         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 751 }
 752
 753 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 754 {
 755         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 756 }
 757
 758 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 759 {
 760         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 761                                            PCI_EXP_DEVCTL_READRQ, force);
 762 }
 763
 764 struct rtl_cond {
 765         bool (*check)(struct rtl8169_private *);
 766         const char *msg;
 767 };
 768
 769 static void rtl_udelay(unsigned int d)
 770 {
 771         udelay(d);
 772 }
 773
 774 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 775                           void (*delay)(unsigned int), unsigned int d, int n,
 776                           bool high)
 777 {
 778         int i;
 779
 780         for (i = 0; i < n; i++) {
 781                 if (c->check(tp) == high)
 782                         return true;
 783                 delay(d);
 784         }
 785         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 786                   c->msg, !high, n, d);
 787         return false;
 788 }
 789
 790 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 791                                       const struct rtl_cond *c,
 792                                       unsigned int d, int n)
 793 {
 794         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 795 }
 796
 797 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 798                                      const struct rtl_cond *c,
 799                                      unsigned int d, int n)
 800 {
 801         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 802 }
 803
 804 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 805                                       const struct rtl_cond *c,
 806                                       unsigned int d, int n)
 807 {
 808         return rtl_loop_wait(tp, c, msleep, d, n, true);
 809 }
 810
 811 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 812                                      const struct rtl_cond *c,
 813                                      unsigned int d, int n)
 814 {
 815         return rtl_loop_wait(tp, c, msleep, d, n, false);
 816 }
 817
 818 #define DECLARE_RTL_COND(name)                          \
 819 static bool name ## _check(struct rtl8169_private *);   \
 820                                                         \
 821 static const struct rtl_cond name = {                   \
 822         .check  = name ## _check,                       \
 823         .msg    = #name                                 \
 824 };                                                      \
 825                                                         \
 826 static bool name ## _check(struct rtl8169_private *tp)
 827
 828 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 829 {
 830         if (reg & 0xffff0001) {
 831                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 832                 return true;
 833         }
 834         return false;
 835 }
 836
 837 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 838 {
 839         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 840 }
 841
 842 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 843 {
 844         if (rtl_ocp_reg_failure(tp, reg))
 845                 return;
 846
 847         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 848
 849         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 850 }
 851
 852 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 853 {
 854         if (rtl_ocp_reg_failure(tp, reg))
 855                 return 0;
 856
 857         RTL_W32(tp, GPHY_OCP, reg << 15);
 858
 859         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 860                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 861 }
 862
 863 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 864 {
 865         if (rtl_ocp_reg_failure(tp, reg))
 866                 return;
 867
 868         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 869 }
 870
 871 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 872 {
 873         if (rtl_ocp_reg_failure(tp, reg))
 874                 return 0;
 875
 876         RTL_W32(tp, OCPDR, reg << 15);
 877
 878         return RTL_R32(tp, OCPDR);
 879 }
 880
 881 #define OCP_STD_PHY_BASE        0xa400
 882
 883 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 884 {
 885         if (reg == 0x1f) {
 886                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 887                 return;
 888         }
 889
 890         if (tp->ocp_base != OCP_STD_PHY_BASE)
 891                 reg -= 0x10;
 892
 893         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 894 }
 895
 896 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 897 {
 898         if (tp->ocp_base != OCP_STD_PHY_BASE)
 899                 reg -= 0x10;
 900
 901         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 902 }
 903
 904 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 905 {
 906         if (reg == 0x1f) {
 907                 tp->ocp_base = value << 4;
 908                 return;
 909         }
 910
 911         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 912 }
 913
 914 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 915 {
 916         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 917 }
 918
 919 DECLARE_RTL_COND(rtl_phyar_cond)
 920 {
 921         return RTL_R32(tp, PHYAR) & 0x80000000;
 922 }
 923
 924 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 925 {
 926         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 927
 928         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 929         /*
 930          * According to hardware specs a 20us delay is required after write
 931          * complete indication, but before sending next command.
 932          */
 933         udelay(20);
 934 }
 935
 936 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 937 {
 938         int value;
 939
 940         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 941
 942         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 943                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 944
 945         /*
 946          * According to hardware specs a 20us delay is required after read
 947          * complete indication, but before sending next command.
 948          */
 949         udelay(20);
 950
 951         return value;
 952 }
 953
 954 DECLARE_RTL_COND(rtl_ocpar_cond)
 955 {
 956         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 957 }
 958
 959 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 960 {
 961         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 962         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 963         RTL_W32(tp, EPHY_RXER_NUM, 0);
 964
 965         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 966 }
 967
 968 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 969 {
 970         r8168dp_1_mdio_access(tp, reg,
 971                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 972 }
 973
 974 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 975 {
 976         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 977
 978         mdelay(1);
 979         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 980         RTL_W32(tp, EPHY_RXER_NUM, 0);
 981
 982         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 983                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 984 }
 985
 986 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 987
 988 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 989 {
 990         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 994 {
 995         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 996 }
 997
 998 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 999 {
1000         r8168dp_2_mdio_start(tp);
1001
1002         r8169_mdio_write(tp, reg, value);
1003
1004         r8168dp_2_mdio_stop(tp);
1005 }
1006
1007 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1008 {
1009         int value;
1010
1011         r8168dp_2_mdio_start(tp);
1012
1013         value = r8169_mdio_read(tp, reg);
1014
1015         r8168dp_2_mdio_stop(tp);
1016
1017         return value;
1018 }
1019
1020 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1021 {
1022         tp->mdio_ops.write(tp, location, val);
1023 }
1024
1025 static int rtl_readphy(struct rtl8169_private *tp, int location)
1026 {
1027         return tp->mdio_ops.read(tp, location);
1028 }
1029
1030 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1031 {
1032         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1033 }
1034
1035 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1036 {
1037         int val;
1038
1039         val = rtl_readphy(tp, reg_addr);
1040         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1041 }
1042
1043 DECLARE_RTL_COND(rtl_ephyar_cond)
1044 {
1045         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1046 }
1047
1048 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1049 {
1050         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1051                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1052
1053         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1054
1055         udelay(10);
1056 }
1057
1058 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1059 {
1060         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1061
1062         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1063                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1064 }
1065
1066 DECLARE_RTL_COND(rtl_eriar_cond)
1067 {
1068         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1069 }
1070
1071 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1072                            u32 val, int type)
1073 {
1074         BUG_ON((addr & 3) || (mask == 0));
1075         RTL_W32(tp, ERIDR, val);
1076         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1077
1078         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1079 }
1080
1081 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1082                           u32 val)
1083 {
1084         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1085 }
1086
1087 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1088 {
1089         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1090
1091         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1092                 RTL_R32(tp, ERIDR) : ~0;
1093 }
1094
1095 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1096 {
1097         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1098 }
1099
1100 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1101                          u32 m)
1102 {
1103         u32 val;
1104
1105         val = rtl_eri_read(tp, addr);
1106         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1107 }
1108
1109 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1110                              u32 p)
1111 {
1112         rtl_w0w1_eri(tp, addr, mask, p, 0);
1113 }
1114
1115 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1116                                u32 m)
1117 {
1118         rtl_w0w1_eri(tp, addr, mask, 0, m);
1119 }
1120
1121 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1122 {
1123         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1124         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1125                 RTL_R32(tp, OCPDR) : ~0;
1126 }
1127
1128 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1129 {
1130         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1131 }
1132
1133 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134                               u32 data)
1135 {
1136         RTL_W32(tp, OCPDR, data);
1137         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1138         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1139 }
1140
1141 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1142                               u32 data)
1143 {
1144         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1145                        data, ERIAR_OOB);
1146 }
1147
1148 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1149 {
1150         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1151
1152         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1153 }
1154
1155 #define OOB_CMD_RESET           0x00
1156 #define OOB_CMD_DRIVER_START    0x05
1157 #define OOB_CMD_DRIVER_STOP     0x06
1158
1159 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1160 {
1161         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1162 }
1163
1164 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1165 {
1166         u16 reg;
1167
1168         reg = rtl8168_get_ocp_reg(tp);
1169
1170         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1171 }
1172
1173 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1174 {
1175         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1176 }
1177
1178 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1179 {
1180         return RTL_R8(tp, IBISR0) & 0x20;
1181 }
1182
1183 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1184 {
1185         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1186         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1187         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1188         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1189 }
1190
1191 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1192 {
1193         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1194         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1195 }
1196
1197 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1198 {
1199         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1200         r8168ep_ocp_write(tp, 0x01, 0x30,
1201                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1202         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168_driver_start(struct rtl8169_private *tp)
1206 {
1207         switch (tp->mac_version) {
1208         case RTL_GIGA_MAC_VER_27:
1209         case RTL_GIGA_MAC_VER_28:
1210         case RTL_GIGA_MAC_VER_31:
1211                 rtl8168dp_driver_start(tp);
1212                 break;
1213         case RTL_GIGA_MAC_VER_49:
1214         case RTL_GIGA_MAC_VER_50:
1215         case RTL_GIGA_MAC_VER_51:
1216                 rtl8168ep_driver_start(tp);
1217                 break;
1218         default:
1219                 BUG();
1220                 break;
1221         }
1222 }
1223
1224 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1225 {
1226         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1227         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1228 }
1229
1230 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1231 {
1232         rtl8168ep_stop_cmac(tp);
1233         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1234         r8168ep_ocp_write(tp, 0x01, 0x30,
1235                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1236         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1237 }
1238
1239 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1240 {
1241         switch (tp->mac_version) {
1242         case RTL_GIGA_MAC_VER_27:
1243         case RTL_GIGA_MAC_VER_28:
1244         case RTL_GIGA_MAC_VER_31:
1245                 rtl8168dp_driver_stop(tp);
1246                 break;
1247         case RTL_GIGA_MAC_VER_49:
1248         case RTL_GIGA_MAC_VER_50:
1249         case RTL_GIGA_MAC_VER_51:
1250                 rtl8168ep_driver_stop(tp);
1251                 break;
1252         default:
1253                 BUG();
1254                 break;
1255         }
1256 }
1257
1258 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1259 {
1260         u16 reg = rtl8168_get_ocp_reg(tp);
1261
1262         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1263 }
1264
1265 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1266 {
1267         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1268 }
1269
1270 static bool r8168_check_dash(struct rtl8169_private *tp)
1271 {
1272         switch (tp->mac_version) {
1273         case RTL_GIGA_MAC_VER_27:
1274         case RTL_GIGA_MAC_VER_28:
1275         case RTL_GIGA_MAC_VER_31:
1276                 return r8168dp_check_dash(tp);
1277         case RTL_GIGA_MAC_VER_49:
1278         case RTL_GIGA_MAC_VER_50:
1279         case RTL_GIGA_MAC_VER_51:
1280                 return r8168ep_check_dash(tp);
1281         default:
1282                 return false;
1283         }
1284 }
1285
1286 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1287 {
1288         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1289         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1290 }
1291
1292 DECLARE_RTL_COND(rtl_efusear_cond)
1293 {
1294         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1295 }
1296
1297 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1298 {
1299         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1300
1301         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1302                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1303 }
1304
1305 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1306 {
1307         RTL_W16(tp, IntrStatus, bits);
1308 }
1309
1310 static void rtl_irq_disable(struct rtl8169_private *tp)
1311 {
1312         RTL_W16(tp, IntrMask, 0);
1313         tp->irq_enabled = 0;
1314 }
1315
1316 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1317 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1318 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1319
1320 static void rtl_irq_enable(struct rtl8169_private *tp)
1321 {
1322         tp->irq_enabled = 1;
1323         RTL_W16(tp, IntrMask, tp->irq_mask);
1324 }
1325
1326 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1327 {
1328         rtl_irq_disable(tp);
1329         rtl_ack_events(tp, 0xffff);
1330         /* PCI commit */
1331         RTL_R8(tp, ChipCmd);
1332 }
1333
1334 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1335 {
1336         struct net_device *dev = tp->dev;
1337         struct phy_device *phydev = tp->phydev;
1338
1339         if (!netif_running(dev))
1340                 return;
1341
1342         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1343             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1344                 if (phydev->speed == SPEED_1000) {
1345                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1346                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1347                 } else if (phydev->speed == SPEED_100) {
1348                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1349                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1350                 } else {
1351                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1352                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1353                 }
1354                 rtl_reset_packet_filter(tp);
1355         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1356                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1357                 if (phydev->speed == SPEED_1000) {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1360                 } else {
1361                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1362                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1363                 }
1364         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1365                 if (phydev->speed == SPEED_10) {
1366                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1367                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1368                 } else {
1369                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1370                 }
1371         }
1372 }
1373
1374 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1375
1376 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1377 {
1378         struct rtl8169_private *tp = netdev_priv(dev);
1379
1380         rtl_lock_work(tp);
1381         wol->supported = WAKE_ANY;
1382         wol->wolopts = tp->saved_wolopts;
1383         rtl_unlock_work(tp);
1384 }
1385
1386 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1387 {
1388         unsigned int i, tmp;
1389         static const struct {
1390                 u32 opt;
1391                 u16 reg;
1392                 u8  mask;
1393         } cfg[] = {
1394                 { WAKE_PHY,   Config3, LinkUp },
1395                 { WAKE_UCAST, Config5, UWF },
1396                 { WAKE_BCAST, Config5, BWF },
1397                 { WAKE_MCAST, Config5, MWF },
1398                 { WAKE_ANY,   Config5, LanWake },
1399                 { WAKE_MAGIC, Config3, MagicPacket }
1400         };
1401         u8 options;
1402
1403         rtl_unlock_config_regs(tp);
1404
1405         switch (tp->mac_version) {
1406         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1407         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1408                 tmp = ARRAY_SIZE(cfg) - 1;
1409                 if (wolopts & WAKE_MAGIC)
1410                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1411                                          MagicPacket_v2);
1412                 else
1413                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1414                                            MagicPacket_v2);
1415                 break;
1416         default:
1417                 tmp = ARRAY_SIZE(cfg);
1418                 break;
1419         }
1420
1421         for (i = 0; i < tmp; i++) {
1422                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(tp, cfg[i].reg, options);
1426         }
1427
1428         switch (tp->mac_version) {
1429         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1430                 options = RTL_R8(tp, Config1) & ~PMEnable;
1431                 if (wolopts)
1432                         options |= PMEnable;
1433                 RTL_W8(tp, Config1, options);
1434                 break;
1435         default:
1436                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1437                 if (wolopts)
1438                         options |= PME_SIGNAL;
1439                 RTL_W8(tp, Config2, options);
1440                 break;
1441         }
1442
1443         rtl_lock_config_regs(tp);
1444
1445         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1446 }
1447
1448 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1449 {
1450         struct rtl8169_private *tp = netdev_priv(dev);
1451         struct device *d = tp_to_dev(tp);
1452
1453         if (wol->wolopts & ~WAKE_ANY)
1454                 return -EINVAL;
1455
1456         pm_runtime_get_noresume(d);
1457
1458         rtl_lock_work(tp);
1459
1460         tp->saved_wolopts = wol->wolopts;
1461
1462         if (pm_runtime_active(d))
1463                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1464
1465         rtl_unlock_work(tp);
1466
1467         pm_runtime_put_noidle(d);
1468
1469         return 0;
1470 }
1471
1472 static void rtl8169_get_drvinfo(struct net_device *dev,
1473                                 struct ethtool_drvinfo *info)
1474 {
1475         struct rtl8169_private *tp = netdev_priv(dev);
1476         struct rtl_fw *rtl_fw = tp->rtl_fw;
1477
1478         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1479         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1480         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1481         if (rtl_fw)
1482                 strlcpy(info->fw_version, rtl_fw->version,
1483                         sizeof(info->fw_version));
1484 }
1485
1486 static int rtl8169_get_regs_len(struct net_device *dev)
1487 {
1488         return R8169_REGS_SIZE;
1489 }
1490
1491 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1492         netdev_features_t features)
1493 {
1494         struct rtl8169_private *tp = netdev_priv(dev);
1495
1496         if (dev->mtu > TD_MSS_MAX)
1497                 features &= ~NETIF_F_ALL_TSO;
1498
1499         if (dev->mtu > JUMBO_1K &&
1500             tp->mac_version > RTL_GIGA_MAC_VER_06)
1501                 features &= ~NETIF_F_IP_CSUM;
1502
1503         return features;
1504 }
1505
1506 static int rtl8169_set_features(struct net_device *dev,
1507                                 netdev_features_t features)
1508 {
1509         struct rtl8169_private *tp = netdev_priv(dev);
1510         u32 rx_config;
1511
1512         rtl_lock_work(tp);
1513
1514         rx_config = RTL_R32(tp, RxConfig);
1515         if (features & NETIF_F_RXALL)
1516                 rx_config |= (AcceptErr | AcceptRunt);
1517         else
1518                 rx_config &= ~(AcceptErr | AcceptRunt);
1519
1520         RTL_W32(tp, RxConfig, rx_config);
1521
1522         if (features & NETIF_F_RXCSUM)
1523                 tp->cp_cmd |= RxChkSum;
1524         else
1525                 tp->cp_cmd &= ~RxChkSum;
1526
1527         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1528                 tp->cp_cmd |= RxVlan;
1529         else
1530                 tp->cp_cmd &= ~RxVlan;
1531
1532         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1533         RTL_R16(tp, CPlusCmd);
1534
1535         rtl_unlock_work(tp);
1536
1537         return 0;
1538 }
1539
1540 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1541 {
1542         return (skb_vlan_tag_present(skb)) ?
1543                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1544 }
1545
1546 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1547 {
1548         u32 opts2 = le32_to_cpu(desc->opts2);
1549
1550         if (opts2 & RxVlanTag)
1551                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1552 }
1553
1554 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1555                              void *p)
1556 {
1557         struct rtl8169_private *tp = netdev_priv(dev);
1558         u32 __iomem *data = tp->mmio_addr;
1559         u32 *dw = p;
1560         int i;
1561
1562         rtl_lock_work(tp);
1563         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1564                 memcpy_fromio(dw++, data++, 4);
1565         rtl_unlock_work(tp);
1566 }
1567
1568 static u32 rtl8169_get_msglevel(struct net_device *dev)
1569 {
1570         struct rtl8169_private *tp = netdev_priv(dev);
1571
1572         return tp->msg_enable;
1573 }
1574
1575 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578
1579         tp->msg_enable = value;
1580 }
1581
1582 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1583         "tx_packets",
1584         "rx_packets",
1585         "tx_errors",
1586         "rx_errors",
1587         "rx_missed",
1588         "align_errors",
1589         "tx_single_collisions",
1590         "tx_multi_collisions",
1591         "unicast",
1592         "broadcast",
1593         "multicast",
1594         "tx_aborted",
1595         "tx_underrun",
1596 };
1597
1598 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1599 {
1600         switch (sset) {
1601         case ETH_SS_STATS:
1602                 return ARRAY_SIZE(rtl8169_gstrings);
1603         default:
1604                 return -EOPNOTSUPP;
1605         }
1606 }
1607
1608 DECLARE_RTL_COND(rtl_counters_cond)
1609 {
1610         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1611 }
1612
1613 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1614 {
1615         dma_addr_t paddr = tp->counters_phys_addr;
1616         u32 cmd;
1617
1618         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1619         RTL_R32(tp, CounterAddrHigh);
1620         cmd = (u64)paddr & DMA_BIT_MASK(32);
1621         RTL_W32(tp, CounterAddrLow, cmd);
1622         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1623
1624         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1625 }
1626
1627 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1628 {
1629         /*
1630          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1631          * tally counters.
1632          */
1633         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1634                 return true;
1635
1636         return rtl8169_do_counters(tp, CounterReset);
1637 }
1638
1639 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1640 {
1641         u8 val = RTL_R8(tp, ChipCmd);
1642
1643         /*
1644          * Some chips are unable to dump tally counters when the receiver
1645          * is disabled. If 0xff chip may be in a PCI power-save state.
1646          */
1647         if (!(val & CmdRxEnb) || val == 0xff)
1648                 return true;
1649
1650         return rtl8169_do_counters(tp, CounterDump);
1651 }
1652
1653 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1654 {
1655         struct rtl8169_counters *counters = tp->counters;
1656         bool ret = false;
1657
1658         /*
1659          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1660          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1661          * reset by a power cycle, while the counter values collected by the
1662          * driver are reset at every driver unload/load cycle.
1663          *
1664          * To make sure the HW values returned by @get_stats64 match the SW
1665          * values, we collect the initial values at first open(*) and use them
1666          * as offsets to normalize the values returned by @get_stats64.
1667          *
1668          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1669          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1670          * set at open time by rtl_hw_start.
1671          */
1672
1673         if (tp->tc_offset.inited)
1674                 return true;
1675
1676         /* If both, reset and update fail, propagate to caller. */
1677         if (rtl8169_reset_counters(tp))
1678                 ret = true;
1679
1680         if (rtl8169_update_counters(tp))
1681                 ret = true;
1682
1683         tp->tc_offset.tx_errors = counters->tx_errors;
1684         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1685         tp->tc_offset.tx_aborted = counters->tx_aborted;
1686         tp->tc_offset.inited = true;
1687
1688         return ret;
1689 }
1690
1691 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1692                                       struct ethtool_stats *stats, u64 *data)
1693 {
1694         struct rtl8169_private *tp = netdev_priv(dev);
1695         struct device *d = tp_to_dev(tp);
1696         struct rtl8169_counters *counters = tp->counters;
1697
1698         ASSERT_RTNL();
1699
1700         pm_runtime_get_noresume(d);
1701
1702         if (pm_runtime_active(d))
1703                 rtl8169_update_counters(tp);
1704
1705         pm_runtime_put_noidle(d);
1706
1707         data[0] = le64_to_cpu(counters->tx_packets);
1708         data[1] = le64_to_cpu(counters->rx_packets);
1709         data[2] = le64_to_cpu(counters->tx_errors);
1710         data[3] = le32_to_cpu(counters->rx_errors);
1711         data[4] = le16_to_cpu(counters->rx_missed);
1712         data[5] = le16_to_cpu(counters->align_errors);
1713         data[6] = le32_to_cpu(counters->tx_one_collision);
1714         data[7] = le32_to_cpu(counters->tx_multi_collision);
1715         data[8] = le64_to_cpu(counters->rx_unicast);
1716         data[9] = le64_to_cpu(counters->rx_broadcast);
1717         data[10] = le32_to_cpu(counters->rx_multicast);
1718         data[11] = le16_to_cpu(counters->tx_aborted);
1719         data[12] = le16_to_cpu(counters->tx_underun);
1720 }
1721
1722 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1723 {
1724         switch(stringset) {
1725         case ETH_SS_STATS:
1726                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1727                 break;
1728         }
1729 }
1730
1731 /*
1732  * Interrupt coalescing
1733  *
1734  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1735  * >     8169, 8168 and 810x line of chipsets
1736  *
1737  * 8169, 8168, and 8136(810x) serial chipsets support it.
1738  *
1739  * > 2 - the Tx timer unit at gigabit speed
1740  *
1741  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1742  * (0xe0) bit 1 and bit 0.
1743  *
1744  * For 8169
1745  * bit[1:0] \ speed        1000M           100M            10M
1746  * 0 0                     320ns           2.56us          40.96us
1747  * 0 1                     2.56us          20.48us         327.7us
1748  * 1 0                     5.12us          40.96us         655.4us
1749  * 1 1                     10.24us         81.92us         1.31ms
1750  *
1751  * For the other
1752  * bit[1:0] \ speed        1000M           100M            10M
1753  * 0 0                     5us             2.56us          40.96us
1754  * 0 1                     40us            20.48us         327.7us
1755  * 1 0                     80us            40.96us         655.4us
1756  * 1 1                     160us           81.92us         1.31ms
1757  */
1758
1759 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1760 struct rtl_coalesce_scale {
1761         /* Rx / Tx */
1762         u32 nsecs[2];
1763 };
1764
1765 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1766 struct rtl_coalesce_info {
1767         u32 speed;
1768         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1769 };
1770
1771 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1772 #define rxtx_x1822(r, t) {              \
1773         {{(r),          (t)}},          \
1774         {{(r)*8,        (t)*8}},        \
1775         {{(r)*8*2,      (t)*8*2}},      \
1776         {{(r)*8*2*2,    (t)*8*2*2}},    \
1777 }
1778 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1779         /* speed        delays:     rx00   tx00 */
1780         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1781         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1782         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1783         { 0 },
1784 };
1785
1786 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1787         /* speed        delays:     rx00   tx00 */
1788         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1789         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1790         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1791         { 0 },
1792 };
1793 #undef rxtx_x1822
1794
1795 /* get rx/tx scale vector corresponding to current speed */
1796 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1797 {
1798         struct rtl8169_private *tp = netdev_priv(dev);
1799         struct ethtool_link_ksettings ecmd;
1800         const struct rtl_coalesce_info *ci;
1801         int rc;
1802
1803         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1804         if (rc < 0)
1805                 return ERR_PTR(rc);
1806
1807         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1808                 if (ecmd.base.speed == ci->speed) {
1809                         return ci;
1810                 }
1811         }
1812
1813         return ERR_PTR(-ELNRNG);
1814 }
1815
1816 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1817 {
1818         struct rtl8169_private *tp = netdev_priv(dev);
1819         const struct rtl_coalesce_info *ci;
1820         const struct rtl_coalesce_scale *scale;
1821         struct {
1822                 u32 *max_frames;
1823                 u32 *usecs;
1824         } coal_settings [] = {
1825                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1826                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1827         }, *p = coal_settings;
1828         int i;
1829         u16 w;
1830
1831         memset(ec, 0, sizeof(*ec));
1832
1833         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1834         ci = rtl_coalesce_info(dev);
1835         if (IS_ERR(ci))
1836                 return PTR_ERR(ci);
1837
1838         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1839
1840         /* read IntrMitigate and adjust according to scale */
1841         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1842                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1843                 w >>= RTL_COALESCE_SHIFT;
1844                 *p->usecs = w & RTL_COALESCE_MASK;
1845         }
1846
1847         for (i = 0; i < 2; i++) {
1848                 p = coal_settings + i;
1849                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1850
1851                 /*
1852                  * ethtool_coalesce says it is illegal to set both usecs and
1853                  * max_frames to 0.
1854                  */
1855                 if (!*p->usecs && !*p->max_frames)
1856                         *p->max_frames = 1;
1857         }
1858
1859         return 0;
1860 }
1861
1862 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1863 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1864                         struct net_device *dev, u32 nsec, u16 *cp01)
1865 {
1866         const struct rtl_coalesce_info *ci;
1867         u16 i;
1868
1869         ci = rtl_coalesce_info(dev);
1870         if (IS_ERR(ci))
1871                 return ERR_CAST(ci);
1872
1873         for (i = 0; i < 4; i++) {
1874                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1875                                         ci->scalev[i].nsecs[1]);
1876                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1877                         *cp01 = i;
1878                         return &ci->scalev[i];
1879                 }
1880         }
1881
1882         return ERR_PTR(-EINVAL);
1883 }
1884
1885 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1886 {
1887         struct rtl8169_private *tp = netdev_priv(dev);
1888         const struct rtl_coalesce_scale *scale;
1889         struct {
1890                 u32 frames;
1891                 u32 usecs;
1892         } coal_settings [] = {
1893                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1894                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1895         }, *p = coal_settings;
1896         u16 w = 0, cp01;
1897         int i;
1898
1899         scale = rtl_coalesce_choose_scale(dev,
1900                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1901         if (IS_ERR(scale))
1902                 return PTR_ERR(scale);
1903
1904         for (i = 0; i < 2; i++, p++) {
1905                 u32 units;
1906
1907                 /*
1908                  * accept max_frames=1 we returned in rtl_get_coalesce.
1909                  * accept it not only when usecs=0 because of e.g. the following scenario:
1910                  *
1911                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1912                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1913                  * - then user does `ethtool -C eth0 rx-usecs 100`
1914                  *
1915                  * since ethtool sends to kernel whole ethtool_coalesce
1916                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1917                  * we'll reject it below in `frames % 4 != 0`.
1918                  */
1919                 if (p->frames == 1) {
1920                         p->frames = 0;
1921                 }
1922
1923                 units = p->usecs * 1000 / scale->nsecs[i];
1924                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1925                         return -EINVAL;
1926
1927                 w <<= RTL_COALESCE_SHIFT;
1928                 w |= units;
1929                 w <<= RTL_COALESCE_SHIFT;
1930                 w |= p->frames >> 2;
1931         }
1932
1933         rtl_lock_work(tp);
1934
1935         RTL_W16(tp, IntrMitigate, swab16(w));
1936
1937         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1938         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1939         RTL_R16(tp, CPlusCmd);
1940
1941         rtl_unlock_work(tp);
1942
1943         return 0;
1944 }
1945
1946 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1947 {
1948         struct phy_device *phydev = tp->phydev;
1949         int ret;
1950
1951         switch (tp->mac_version) {
1952         case RTL_GIGA_MAC_VER_34:
1953         case RTL_GIGA_MAC_VER_35:
1954         case RTL_GIGA_MAC_VER_36:
1955         case RTL_GIGA_MAC_VER_38:
1956                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1957                 break;
1958         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1959                 phy_write(phydev, 0x1f, 0x0a5c);
1960                 ret = phy_read(phydev, 0x12);
1961                 phy_write(phydev, 0x1f, 0x0000);
1962                 break;
1963         default:
1964                 ret = -EPROTONOSUPPORT;
1965                 break;
1966         }
1967
1968         return ret;
1969 }
1970
1971 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1972 {
1973         struct phy_device *phydev = tp->phydev;
1974         int ret;
1975
1976         switch (tp->mac_version) {
1977         case RTL_GIGA_MAC_VER_34:
1978         case RTL_GIGA_MAC_VER_35:
1979         case RTL_GIGA_MAC_VER_36:
1980         case RTL_GIGA_MAC_VER_38:
1981                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1982                 break;
1983         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1984                 phy_write(phydev, 0x1f, 0x0a5d);
1985                 ret = phy_read(phydev, 0x11);
1986                 phy_write(phydev, 0x1f, 0x0000);
1987                 break;
1988         default:
1989                 ret = -EPROTONOSUPPORT;
1990                 break;
1991         }
1992
1993         return ret;
1994 }
1995
1996 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1997 {
1998         struct phy_device *phydev = tp->phydev;
1999         int ret;
2000
2001         switch (tp->mac_version) {
2002         case RTL_GIGA_MAC_VER_34:
2003         case RTL_GIGA_MAC_VER_35:
2004         case RTL_GIGA_MAC_VER_36:
2005         case RTL_GIGA_MAC_VER_38:
2006                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2007                 break;
2008         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2009                 phy_write(phydev, 0x1f, 0x0a5d);
2010                 ret = phy_read(phydev, 0x10);
2011                 phy_write(phydev, 0x1f, 0x0000);
2012                 break;
2013         default:
2014                 ret = -EPROTONOSUPPORT;
2015                 break;
2016         }
2017
2018         return ret;
2019 }
2020
2021 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2022 {
2023         struct phy_device *phydev = tp->phydev;
2024         int ret = 0;
2025
2026         switch (tp->mac_version) {
2027         case RTL_GIGA_MAC_VER_34:
2028         case RTL_GIGA_MAC_VER_35:
2029         case RTL_GIGA_MAC_VER_36:
2030         case RTL_GIGA_MAC_VER_38:
2031                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2032                 break;
2033         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2034                 phy_write(phydev, 0x1f, 0x0a5d);
2035                 phy_write(phydev, 0x10, val);
2036                 phy_write(phydev, 0x1f, 0x0000);
2037                 break;
2038         default:
2039                 ret = -EPROTONOSUPPORT;
2040                 break;
2041         }
2042
2043         return ret;
2044 }
2045
2046 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2047 {
2048         struct rtl8169_private *tp = netdev_priv(dev);
2049         struct device *d = tp_to_dev(tp);
2050         int ret;
2051
2052         pm_runtime_get_noresume(d);
2053
2054         if (!pm_runtime_active(d)) {
2055                 ret = -EOPNOTSUPP;
2056                 goto out;
2057         }
2058
2059         /* Get Supported EEE */
2060         ret = rtl_get_eee_supp(tp);
2061         if (ret < 0)
2062                 goto out;
2063         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2064
2065         /* Get advertisement EEE */
2066         ret = rtl_get_eee_adv(tp);
2067         if (ret < 0)
2068                 goto out;
2069         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2070         data->eee_enabled = !!data->advertised;
2071
2072         /* Get LP advertisement EEE */
2073         ret = rtl_get_eee_lpadv(tp);
2074         if (ret < 0)
2075                 goto out;
2076         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2077         data->eee_active = !!(data->advertised & data->lp_advertised);
2078 out:
2079         pm_runtime_put_noidle(d);
2080         return ret < 0 ? ret : 0;
2081 }
2082
2083 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2084 {
2085         struct rtl8169_private *tp = netdev_priv(dev);
2086         struct device *d = tp_to_dev(tp);
2087         int old_adv, adv = 0, cap, ret;
2088
2089         pm_runtime_get_noresume(d);
2090
2091         if (!dev->phydev || !pm_runtime_active(d)) {
2092                 ret = -EOPNOTSUPP;
2093                 goto out;
2094         }
2095
2096         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2097             dev->phydev->duplex != DUPLEX_FULL) {
2098                 ret = -EPROTONOSUPPORT;
2099                 goto out;
2100         }
2101
2102         /* Get Supported EEE */
2103         ret = rtl_get_eee_supp(tp);
2104         if (ret < 0)
2105                 goto out;
2106         cap = ret;
2107
2108         ret = rtl_get_eee_adv(tp);
2109         if (ret < 0)
2110                 goto out;
2111         old_adv = ret;
2112
2113         if (data->eee_enabled) {
2114                 adv = !data->advertised ? cap :
2115                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2116                 /* Mask prohibited EEE modes */
2117                 adv &= ~dev->phydev->eee_broken_modes;
2118         }
2119
2120         if (old_adv != adv) {
2121                 ret = rtl_set_eee_adv(tp, adv);
2122                 if (ret < 0)
2123                         goto out;
2124
2125                 /* Restart autonegotiation so the new modes get sent to the
2126                  * link partner.
2127                  */
2128                 ret = phy_restart_aneg(dev->phydev);
2129         }
2130
2131 out:
2132         pm_runtime_put_noidle(d);
2133         return ret < 0 ? ret : 0;
2134 }
2135
2136 static const struct ethtool_ops rtl8169_ethtool_ops = {
2137         .get_drvinfo            = rtl8169_get_drvinfo,
2138         .get_regs_len           = rtl8169_get_regs_len,
2139         .get_link               = ethtool_op_get_link,
2140         .get_coalesce           = rtl_get_coalesce,
2141         .set_coalesce           = rtl_set_coalesce,
2142         .get_msglevel           = rtl8169_get_msglevel,
2143         .set_msglevel           = rtl8169_set_msglevel,
2144         .get_regs               = rtl8169_get_regs,
2145         .get_wol                = rtl8169_get_wol,
2146         .set_wol                = rtl8169_set_wol,
2147         .get_strings            = rtl8169_get_strings,
2148         .get_sset_count         = rtl8169_get_sset_count,
2149         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2150         .get_ts_info            = ethtool_op_get_ts_info,
2151         .nway_reset             = phy_ethtool_nway_reset,
2152         .get_eee                = rtl8169_get_eee,
2153         .set_eee                = rtl8169_set_eee,
2154         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2155         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2156 };
2157
2158 static void rtl_enable_eee(struct rtl8169_private *tp)
2159 {
2160         int supported = rtl_get_eee_supp(tp);
2161
2162         if (supported > 0)
2163                 rtl_set_eee_adv(tp, supported);
2164 }
2165
2166 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2167 {
2168         /*
2169          * The driver currently handles the 8168Bf and the 8168Be identically
2170          * but they can be identified more specifically through the test below
2171          * if needed:
2172          *
2173          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2174          *
2175          * Same thing for the 8101Eb and the 8101Ec:
2176          *
2177          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2178          */
2179         static const struct rtl_mac_info {
2180                 u16 mask;
2181                 u16 val;
2182                 u16 mac_version;
2183         } mac_info[] = {
2184                 /* 8168EP family. */
2185                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2186                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2187                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2188
2189                 /* 8168H family. */
2190                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2191                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2192
2193                 /* 8168G family. */
2194                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2195                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2196                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2197                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2198
2199                 /* 8168F family. */
2200                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2201                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2202                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2203
2204                 /* 8168E family. */
2205                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2206                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2207                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2208
2209                 /* 8168D family. */
2210                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2211                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2212
2213                 /* 8168DP family. */
2214                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2215                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2216                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2217
2218                 /* 8168C family. */
2219                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2220                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2221                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2222                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2223                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2224                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2225                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2226
2227                 /* 8168B family. */
2228                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2229                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2230                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2231
2232                 /* 8101 family. */
2233                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2234                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2235                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2236                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2237                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2238                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2239                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2240                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2241                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2242                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2243                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2244                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2245                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2246                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2247                 /* FIXME: where did these entries come from ? -- FR */
2248                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2249                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2250
2251                 /* 8110 family. */
2252                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2253                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2254                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2255                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2256                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2257
2258                 /* Catch-all */
2259                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2260         };
2261         const struct rtl_mac_info *p = mac_info;
2262         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2263
2264         while ((reg & p->mask) != p->val)
2265                 p++;
2266         tp->mac_version = p->mac_version;
2267
2268         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2269                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2270         } else if (!tp->supports_gmii) {
2271                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2272                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2273                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2274                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2275                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2276                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2277         }
2278 }
2279
2280 struct phy_reg {
2281         u16 reg;
2282         u16 val;
2283 };
2284
2285 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2286                                  const struct phy_reg *regs, int len)
2287 {
2288         while (len-- > 0) {
2289                 rtl_writephy(tp, regs->reg, regs->val);
2290                 regs++;
2291         }
2292 }
2293
2294 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2295
2296 #define PHY_READ                0x00000000
2297 #define PHY_DATA_OR             0x10000000
2298 #define PHY_DATA_AND            0x20000000
2299 #define PHY_BJMPN               0x30000000
2300 #define PHY_MDIO_CHG            0x40000000
2301 #define PHY_CLEAR_READCOUNT     0x70000000
2302 #define PHY_WRITE               0x80000000
2303 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2304 #define PHY_COMP_EQ_SKIPN       0xa0000000
2305 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2306 #define PHY_WRITE_PREVIOUS      0xc0000000
2307 #define PHY_SKIPN               0xd0000000
2308 #define PHY_DELAY_MS            0xe0000000
2309
2310 struct fw_info {
2311         u32     magic;
2312         char    version[RTL_VER_SIZE];
2313         __le32  fw_start;
2314         __le32  fw_len;
2315         u8      chksum;
2316 } __packed;
2317
2318 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2319
2320 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2321 {
2322         const struct firmware *fw = rtl_fw->fw;
2323         struct fw_info *fw_info = (struct fw_info *)fw->data;
2324         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2325
2326         if (fw->size < FW_OPCODE_SIZE)
2327                 return false;
2328
2329         if (!fw_info->magic) {
2330                 size_t i, size, start;
2331                 u8 checksum = 0;
2332
2333                 if (fw->size < sizeof(*fw_info))
2334                         return false;
2335
2336                 for (i = 0; i < fw->size; i++)
2337                         checksum += fw->data[i];
2338                 if (checksum != 0)
2339                         return false;
2340
2341                 start = le32_to_cpu(fw_info->fw_start);
2342                 if (start > fw->size)
2343                         return false;
2344
2345                 size = le32_to_cpu(fw_info->fw_len);
2346                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2347                         return false;
2348
2349                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2350
2351                 pa->code = (__le32 *)(fw->data + start);
2352                 pa->size = size;
2353         } else {
2354                 if (fw->size % FW_OPCODE_SIZE)
2355                         return false;
2356
2357                 strscpy(rtl_fw->version, tp->fw_name, RTL_VER_SIZE);
2358
2359                 pa->code = (__le32 *)fw->data;
2360                 pa->size = fw->size / FW_OPCODE_SIZE;
2361         }
2362
2363         return true;
2364 }
2365
2366 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2367                            struct rtl_fw_phy_action *pa)
2368 {
2369         bool rc = false;
2370         size_t index;
2371
2372         for (index = 0; index < pa->size; index++) {
2373                 u32 action = le32_to_cpu(pa->code[index]);
2374                 u32 regno = (action & 0x0fff0000) >> 16;
2375
2376                 switch(action & 0xf0000000) {
2377                 case PHY_READ:
2378                 case PHY_DATA_OR:
2379                 case PHY_DATA_AND:
2380                 case PHY_MDIO_CHG:
2381                 case PHY_CLEAR_READCOUNT:
2382                 case PHY_WRITE:
2383                 case PHY_WRITE_PREVIOUS:
2384                 case PHY_DELAY_MS:
2385                         break;
2386
2387                 case PHY_BJMPN:
2388                         if (regno > index) {
2389                                 netif_err(tp, ifup, tp->dev,
2390                                           "Out of range of firmware\n");
2391                                 goto out;
2392                         }
2393                         break;
2394                 case PHY_READCOUNT_EQ_SKIP:
2395                         if (index + 2 >= pa->size) {
2396                                 netif_err(tp, ifup, tp->dev,
2397                                           "Out of range of firmware\n");
2398                                 goto out;
2399                         }
2400                         break;
2401                 case PHY_COMP_EQ_SKIPN:
2402                 case PHY_COMP_NEQ_SKIPN:
2403                 case PHY_SKIPN:
2404                         if (index + 1 + regno >= pa->size) {
2405                                 netif_err(tp, ifup, tp->dev,
2406                                           "Out of range of firmware\n");
2407                                 goto out;
2408                         }
2409                         break;
2410
2411                 default:
2412                         netif_err(tp, ifup, tp->dev,
2413                                   "Invalid action 0x%08x\n", action);
2414                         goto out;
2415                 }
2416         }
2417         rc = true;
2418 out:
2419         return rc;
2420 }
2421
2422 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2423 {
2424         struct net_device *dev = tp->dev;
2425         int rc = -EINVAL;
2426
2427         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2428                 netif_err(tp, ifup, dev, "invalid firmware\n");
2429                 goto out;
2430         }
2431
2432         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2433                 rc = 0;
2434 out:
2435         return rc;
2436 }
2437
2438 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2439                                   struct rtl_fw *rtl_fw)
2440 {
2441         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2442         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2443         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2444         int predata = 0, count = 0;
2445         size_t index;
2446
2447         for (index = 0; index < pa->size; ) {
2448                 u32 action = le32_to_cpu(pa->code[index]);
2449                 u32 data = action & 0x0000ffff;
2450                 u32 regno = (action & 0x0fff0000) >> 16;
2451
2452                 if (!action)
2453                         break;
2454
2455                 switch(action & 0xf0000000) {
2456                 case PHY_READ:
2457                         predata = fw_read(tp, regno);
2458                         count++;
2459                         index++;
2460                         break;
2461                 case PHY_DATA_OR:
2462                         predata |= data;
2463                         index++;
2464                         break;
2465                 case PHY_DATA_AND:
2466                         predata &= data;
2467                         index++;
2468                         break;
2469                 case PHY_BJMPN:
2470                         index -= regno;
2471                         break;
2472                 case PHY_MDIO_CHG:
2473                         if (data == 0) {
2474                                 fw_write = rtl_fw->phy_write;
2475                                 fw_read = rtl_fw->phy_read;
2476                         } else if (data == 1) {
2477                                 fw_write = rtl_fw->mac_mcu_write;
2478                                 fw_read = rtl_fw->mac_mcu_read;
2479                         }
2480
2481                         index++;
2482                         break;
2483                 case PHY_CLEAR_READCOUNT:
2484                         count = 0;
2485                         index++;
2486                         break;
2487                 case PHY_WRITE:
2488                         fw_write(tp, regno, data);
2489                         index++;
2490                         break;
2491                 case PHY_READCOUNT_EQ_SKIP:
2492                         index += (count == data) ? 2 : 1;
2493                         break;
2494                 case PHY_COMP_EQ_SKIPN:
2495                         if (predata == data)
2496                                 index += regno;
2497                         index++;
2498                         break;
2499                 case PHY_COMP_NEQ_SKIPN:
2500                         if (predata != data)
2501                                 index += regno;
2502                         index++;
2503                         break;
2504                 case PHY_WRITE_PREVIOUS:
2505                         fw_write(tp, regno, predata);
2506                         index++;
2507                         break;
2508                 case PHY_SKIPN:
2509                         index += regno + 1;
2510                         break;
2511                 case PHY_DELAY_MS:
2512                         mdelay(data);
2513                         index++;
2514                         break;
2515
2516                 default:
2517                         BUG();
2518                 }
2519         }
2520 }
2521
2522 static void rtl_release_firmware(struct rtl8169_private *tp)
2523 {
2524         if (tp->rtl_fw) {
2525                 release_firmware(tp->rtl_fw->fw);
2526                 kfree(tp->rtl_fw);
2527                 tp->rtl_fw = NULL;
2528         }
2529 }
2530
2531 static void rtl_apply_firmware(struct rtl8169_private *tp)
2532 {
2533         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2534         if (tp->rtl_fw)
2535                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2536 }
2537
2538 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2539 {
2540         if (rtl_readphy(tp, reg) != val)
2541                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2542         else
2543                 rtl_apply_firmware(tp);
2544 }
2545
2546 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2547 {
2548         /* Adjust EEE LED frequency */
2549         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2550                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2551
2552         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2553 }
2554
2555 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2556 {
2557         struct phy_device *phydev = tp->phydev;
2558
2559         phy_write(phydev, 0x1f, 0x0007);
2560         phy_write(phydev, 0x1e, 0x0020);
2561         phy_set_bits(phydev, 0x15, BIT(8));
2562
2563         phy_write(phydev, 0x1f, 0x0005);
2564         phy_write(phydev, 0x05, 0x8b85);
2565         phy_set_bits(phydev, 0x06, BIT(13));
2566
2567         phy_write(phydev, 0x1f, 0x0000);
2568 }
2569
2570 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2571 {
2572         phy_write(tp->phydev, 0x1f, 0x0a43);
2573         phy_set_bits(tp->phydev, 0x11, BIT(4));
2574         phy_write(tp->phydev, 0x1f, 0x0000);
2575 }
2576
2577 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579         static const struct phy_reg phy_reg_init[] = {
2580                 { 0x1f, 0x0001 },
2581                 { 0x06, 0x006e },
2582                 { 0x08, 0x0708 },
2583                 { 0x15, 0x4000 },
2584                 { 0x18, 0x65c7 },
2585
2586                 { 0x1f, 0x0001 },
2587                 { 0x03, 0x00a1 },
2588                 { 0x02, 0x0008 },
2589                 { 0x01, 0x0120 },
2590                 { 0x00, 0x1000 },
2591                 { 0x04, 0x0800 },
2592                 { 0x04, 0x0000 },
2593
2594                 { 0x03, 0xff41 },
2595                 { 0x02, 0xdf60 },
2596                 { 0x01, 0x0140 },
2597                 { 0x00, 0x0077 },
2598                 { 0x04, 0x7800 },
2599                 { 0x04, 0x7000 },
2600
2601                 { 0x03, 0x802f },
2602                 { 0x02, 0x4f02 },
2603                 { 0x01, 0x0409 },
2604                 { 0x00, 0xf0f9 },
2605                 { 0x04, 0x9800 },
2606                 { 0x04, 0x9000 },
2607
2608                 { 0x03, 0xdf01 },
2609                 { 0x02, 0xdf20 },
2610                 { 0x01, 0xff95 },
2611                 { 0x00, 0xba00 },
2612                 { 0x04, 0xa800 },
2613                 { 0x04, 0xa000 },
2614
2615                 { 0x03, 0xff41 },
2616                 { 0x02, 0xdf20 },
2617                 { 0x01, 0x0140 },
2618                 { 0x00, 0x00bb },
2619                 { 0x04, 0xb800 },
2620                 { 0x04, 0xb000 },
2621
2622                 { 0x03, 0xdf41 },
2623                 { 0x02, 0xdc60 },
2624                 { 0x01, 0x6340 },
2625                 { 0x00, 0x007d },
2626                 { 0x04, 0xd800 },
2627                 { 0x04, 0xd000 },
2628
2629                 { 0x03, 0xdf01 },
2630                 { 0x02, 0xdf20 },
2631                 { 0x01, 0x100a },
2632                 { 0x00, 0xa0ff },
2633                 { 0x04, 0xf800 },
2634                 { 0x04, 0xf000 },
2635
2636                 { 0x1f, 0x0000 },
2637                 { 0x0b, 0x0000 },
2638                 { 0x00, 0x9200 }
2639         };
2640
2641         rtl_writephy_batch(tp, phy_reg_init);
2642 }
2643
2644 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2645 {
2646         static const struct phy_reg phy_reg_init[] = {
2647                 { 0x1f, 0x0002 },
2648                 { 0x01, 0x90d0 },
2649                 { 0x1f, 0x0000 }
2650         };
2651
2652         rtl_writephy_batch(tp, phy_reg_init);
2653 }
2654
2655 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2656 {
2657         struct pci_dev *pdev = tp->pci_dev;
2658
2659         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2660             (pdev->subsystem_device != 0xe000))
2661                 return;
2662
2663         rtl_writephy(tp, 0x1f, 0x0001);
2664         rtl_writephy(tp, 0x10, 0xf01b);
2665         rtl_writephy(tp, 0x1f, 0x0000);
2666 }
2667
2668 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670         static const struct phy_reg phy_reg_init[] = {
2671                 { 0x1f, 0x0001 },
2672                 { 0x04, 0x0000 },
2673                 { 0x03, 0x00a1 },
2674                 { 0x02, 0x0008 },
2675                 { 0x01, 0x0120 },
2676                 { 0x00, 0x1000 },
2677                 { 0x04, 0x0800 },
2678                 { 0x04, 0x9000 },
2679                 { 0x03, 0x802f },
2680                 { 0x02, 0x4f02 },
2681                 { 0x01, 0x0409 },
2682                 { 0x00, 0xf099 },
2683                 { 0x04, 0x9800 },
2684                 { 0x04, 0xa000 },
2685                 { 0x03, 0xdf01 },
2686                 { 0x02, 0xdf20 },
2687                 { 0x01, 0xff95 },
2688                 { 0x00, 0xba00 },
2689                 { 0x04, 0xa800 },
2690                 { 0x04, 0xf000 },
2691                 { 0x03, 0xdf01 },
2692                 { 0x02, 0xdf20 },
2693                 { 0x01, 0x101a },
2694                 { 0x00, 0xa0ff },
2695                 { 0x04, 0xf800 },
2696                 { 0x04, 0x0000 },
2697                 { 0x1f, 0x0000 },
2698
2699                 { 0x1f, 0x0001 },
2700                 { 0x10, 0xf41b },
2701                 { 0x14, 0xfb54 },
2702                 { 0x18, 0xf5c7 },
2703                 { 0x1f, 0x0000 },
2704
2705                 { 0x1f, 0x0001 },
2706                 { 0x17, 0x0cc0 },
2707                 { 0x1f, 0x0000 }
2708         };
2709
2710         rtl_writephy_batch(tp, phy_reg_init);
2711
2712         rtl8169scd_hw_phy_config_quirk(tp);
2713 }
2714
2715 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2716 {
2717         static const struct phy_reg phy_reg_init[] = {
2718                 { 0x1f, 0x0001 },
2719                 { 0x04, 0x0000 },
2720                 { 0x03, 0x00a1 },
2721                 { 0x02, 0x0008 },
2722                 { 0x01, 0x0120 },
2723                 { 0x00, 0x1000 },
2724                 { 0x04, 0x0800 },
2725                 { 0x04, 0x9000 },
2726                 { 0x03, 0x802f },
2727                 { 0x02, 0x4f02 },
2728                 { 0x01, 0x0409 },
2729                 { 0x00, 0xf099 },
2730                 { 0x04, 0x9800 },
2731                 { 0x04, 0xa000 },
2732                 { 0x03, 0xdf01 },
2733                 { 0x02, 0xdf20 },
2734                 { 0x01, 0xff95 },
2735                 { 0x00, 0xba00 },
2736                 { 0x04, 0xa800 },
2737                 { 0x04, 0xf000 },
2738                 { 0x03, 0xdf01 },
2739                 { 0x02, 0xdf20 },
2740                 { 0x01, 0x101a },
2741                 { 0x00, 0xa0ff },
2742                 { 0x04, 0xf800 },
2743                 { 0x04, 0x0000 },
2744                 { 0x1f, 0x0000 },
2745
2746                 { 0x1f, 0x0001 },
2747                 { 0x0b, 0x8480 },
2748                 { 0x1f, 0x0000 },
2749
2750                 { 0x1f, 0x0001 },
2751                 { 0x18, 0x67c7 },
2752                 { 0x04, 0x2000 },
2753                 { 0x03, 0x002f },
2754                 { 0x02, 0x4360 },
2755                 { 0x01, 0x0109 },
2756                 { 0x00, 0x3022 },
2757                 { 0x04, 0x2800 },
2758                 { 0x1f, 0x0000 },
2759
2760                 { 0x1f, 0x0001 },
2761                 { 0x17, 0x0cc0 },
2762                 { 0x1f, 0x0000 }
2763         };
2764
2765         rtl_writephy_batch(tp, phy_reg_init);
2766 }
2767
2768 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2769 {
2770         static const struct phy_reg phy_reg_init[] = {
2771                 { 0x10, 0xf41b },
2772                 { 0x1f, 0x0000 }
2773         };
2774
2775         rtl_writephy(tp, 0x1f, 0x0001);
2776         rtl_patchphy(tp, 0x16, 1 << 0);
2777
2778         rtl_writephy_batch(tp, phy_reg_init);
2779 }
2780
2781 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783         static const struct phy_reg phy_reg_init[] = {
2784                 { 0x1f, 0x0001 },
2785                 { 0x10, 0xf41b },
2786                 { 0x1f, 0x0000 }
2787         };
2788
2789         rtl_writephy_batch(tp, phy_reg_init);
2790 }
2791
2792 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2793 {
2794         static const struct phy_reg phy_reg_init[] = {
2795                 { 0x1f, 0x0000 },
2796                 { 0x1d, 0x0f00 },
2797                 { 0x1f, 0x0002 },
2798                 { 0x0c, 0x1ec8 },
2799                 { 0x1f, 0x0000 }
2800         };
2801
2802         rtl_writephy_batch(tp, phy_reg_init);
2803 }
2804
2805 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2806 {
2807         static const struct phy_reg phy_reg_init[] = {
2808                 { 0x1f, 0x0001 },
2809                 { 0x1d, 0x3d98 },
2810                 { 0x1f, 0x0000 }
2811         };
2812
2813         rtl_writephy(tp, 0x1f, 0x0000);
2814         rtl_patchphy(tp, 0x14, 1 << 5);
2815         rtl_patchphy(tp, 0x0d, 1 << 5);
2816
2817         rtl_writephy_batch(tp, phy_reg_init);
2818 }
2819
2820 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2821 {
2822         static const struct phy_reg phy_reg_init[] = {
2823                 { 0x1f, 0x0001 },
2824                 { 0x12, 0x2300 },
2825                 { 0x1f, 0x0002 },
2826                 { 0x00, 0x88d4 },
2827                 { 0x01, 0x82b1 },
2828                 { 0x03, 0x7002 },
2829                 { 0x08, 0x9e30 },
2830                 { 0x09, 0x01f0 },
2831                 { 0x0a, 0x5500 },
2832                 { 0x0c, 0x00c8 },
2833                 { 0x1f, 0x0003 },
2834                 { 0x12, 0xc096 },
2835                 { 0x16, 0x000a },
2836                 { 0x1f, 0x0000 },
2837                 { 0x1f, 0x0000 },
2838                 { 0x09, 0x2000 },
2839                 { 0x09, 0x0000 }
2840         };
2841
2842         rtl_writephy_batch(tp, phy_reg_init);
2843
2844         rtl_patchphy(tp, 0x14, 1 << 5);
2845         rtl_patchphy(tp, 0x0d, 1 << 5);
2846         rtl_writephy(tp, 0x1f, 0x0000);
2847 }
2848
2849 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2850 {
2851         static const struct phy_reg phy_reg_init[] = {
2852                 { 0x1f, 0x0001 },
2853                 { 0x12, 0x2300 },
2854                 { 0x03, 0x802f },
2855                 { 0x02, 0x4f02 },
2856                 { 0x01, 0x0409 },
2857                 { 0x00, 0xf099 },
2858                 { 0x04, 0x9800 },
2859                 { 0x04, 0x9000 },
2860                 { 0x1d, 0x3d98 },
2861                 { 0x1f, 0x0002 },
2862                 { 0x0c, 0x7eb8 },
2863                 { 0x06, 0x0761 },
2864                 { 0x1f, 0x0003 },
2865                 { 0x16, 0x0f0a },
2866                 { 0x1f, 0x0000 }
2867         };
2868
2869         rtl_writephy_batch(tp, phy_reg_init);
2870
2871         rtl_patchphy(tp, 0x16, 1 << 0);
2872         rtl_patchphy(tp, 0x14, 1 << 5);
2873         rtl_patchphy(tp, 0x0d, 1 << 5);
2874         rtl_writephy(tp, 0x1f, 0x0000);
2875 }
2876
2877 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879         static const struct phy_reg phy_reg_init[] = {
2880                 { 0x1f, 0x0001 },
2881                 { 0x12, 0x2300 },
2882                 { 0x1d, 0x3d98 },
2883                 { 0x1f, 0x0002 },
2884                 { 0x0c, 0x7eb8 },
2885                 { 0x06, 0x5461 },
2886                 { 0x1f, 0x0003 },
2887                 { 0x16, 0x0f0a },
2888                 { 0x1f, 0x0000 }
2889         };
2890
2891         rtl_writephy_batch(tp, phy_reg_init);
2892
2893         rtl_patchphy(tp, 0x16, 1 << 0);
2894         rtl_patchphy(tp, 0x14, 1 << 5);
2895         rtl_patchphy(tp, 0x0d, 1 << 5);
2896         rtl_writephy(tp, 0x1f, 0x0000);
2897 }
2898
2899 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         rtl8168c_3_hw_phy_config(tp);
2902 }
2903
2904 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2905         /* Channel Estimation */
2906         { 0x1f, 0x0001 },
2907         { 0x06, 0x4064 },
2908         { 0x07, 0x2863 },
2909         { 0x08, 0x059c },
2910         { 0x09, 0x26b4 },
2911         { 0x0a, 0x6a19 },
2912         { 0x0b, 0xdcc8 },
2913         { 0x10, 0xf06d },
2914         { 0x14, 0x7f68 },
2915         { 0x18, 0x7fd9 },
2916         { 0x1c, 0xf0ff },
2917         { 0x1d, 0x3d9c },
2918         { 0x1f, 0x0003 },
2919         { 0x12, 0xf49f },
2920         { 0x13, 0x070b },
2921         { 0x1a, 0x05ad },
2922         { 0x14, 0x94c0 },
2923
2924         /*
2925          * Tx Error Issue
2926          * Enhance line driver power
2927          */
2928         { 0x1f, 0x0002 },
2929         { 0x06, 0x5561 },
2930         { 0x1f, 0x0005 },
2931         { 0x05, 0x8332 },
2932         { 0x06, 0x5561 },
2933
2934         /*
2935          * Can not link to 1Gbps with bad cable
2936          * Decrease SNR threshold form 21.07dB to 19.04dB
2937          */
2938         { 0x1f, 0x0001 },
2939         { 0x17, 0x0cc0 },
2940
2941         { 0x1f, 0x0000 },
2942         { 0x0d, 0xf880 }
2943 };
2944
2945 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2946         { 0x1f, 0x0002 },
2947         { 0x05, 0x669a },
2948         { 0x1f, 0x0005 },
2949         { 0x05, 0x8330 },
2950         { 0x06, 0x669a },
2951         { 0x1f, 0x0002 }
2952 };
2953
2954 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2955 {
2956         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2957
2958         /*
2959          * Rx Error Issue
2960          * Fine Tune Switching regulator parameter
2961          */
2962         rtl_writephy(tp, 0x1f, 0x0002);
2963         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2964         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2965
2966         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2967                 int val;
2968
2969                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2970
2971                 val = rtl_readphy(tp, 0x0d);
2972
2973                 if ((val & 0x00ff) != 0x006c) {
2974                         static const u32 set[] = {
2975                                 0x0065, 0x0066, 0x0067, 0x0068,
2976                                 0x0069, 0x006a, 0x006b, 0x006c
2977                         };
2978                         int i;
2979
2980                         rtl_writephy(tp, 0x1f, 0x0002);
2981
2982                         val &= 0xff00;
2983                         for (i = 0; i < ARRAY_SIZE(set); i++)
2984                                 rtl_writephy(tp, 0x0d, val | set[i]);
2985                 }
2986         } else {
2987                 static const struct phy_reg phy_reg_init[] = {
2988                         { 0x1f, 0x0002 },
2989                         { 0x05, 0x6662 },
2990                         { 0x1f, 0x0005 },
2991                         { 0x05, 0x8330 },
2992                         { 0x06, 0x6662 }
2993                 };
2994
2995                 rtl_writephy_batch(tp, phy_reg_init);
2996         }
2997
2998         /* RSET couple improve */
2999         rtl_writephy(tp, 0x1f, 0x0002);
3000         rtl_patchphy(tp, 0x0d, 0x0300);
3001         rtl_patchphy(tp, 0x0f, 0x0010);
3002
3003         /* Fine tune PLL performance */
3004         rtl_writephy(tp, 0x1f, 0x0002);
3005         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3006         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3007
3008         rtl_writephy(tp, 0x1f, 0x0005);
3009         rtl_writephy(tp, 0x05, 0x001b);
3010
3011         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3012
3013         rtl_writephy(tp, 0x1f, 0x0000);
3014 }
3015
3016 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3017 {
3018         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3019
3020         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3021                 int val;
3022
3023                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3024
3025                 val = rtl_readphy(tp, 0x0d);
3026                 if ((val & 0x00ff) != 0x006c) {
3027                         static const u32 set[] = {
3028                                 0x0065, 0x0066, 0x0067, 0x0068,
3029                                 0x0069, 0x006a, 0x006b, 0x006c
3030                         };
3031                         int i;
3032
3033                         rtl_writephy(tp, 0x1f, 0x0002);
3034
3035                         val &= 0xff00;
3036                         for (i = 0; i < ARRAY_SIZE(set); i++)
3037                                 rtl_writephy(tp, 0x0d, val | set[i]);
3038                 }
3039         } else {
3040                 static const struct phy_reg phy_reg_init[] = {
3041                         { 0x1f, 0x0002 },
3042                         { 0x05, 0x2642 },
3043                         { 0x1f, 0x0005 },
3044                         { 0x05, 0x8330 },
3045                         { 0x06, 0x2642 }
3046                 };
3047
3048                 rtl_writephy_batch(tp, phy_reg_init);
3049         }
3050
3051         /* Fine tune PLL performance */
3052         rtl_writephy(tp, 0x1f, 0x0002);
3053         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3054         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3055
3056         /* Switching regulator Slew rate */
3057         rtl_writephy(tp, 0x1f, 0x0002);
3058         rtl_patchphy(tp, 0x0f, 0x0017);
3059
3060         rtl_writephy(tp, 0x1f, 0x0005);
3061         rtl_writephy(tp, 0x05, 0x001b);
3062
3063         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3064
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066 }
3067
3068 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3069 {
3070         static const struct phy_reg phy_reg_init[] = {
3071                 { 0x1f, 0x0002 },
3072                 { 0x10, 0x0008 },
3073                 { 0x0d, 0x006c },
3074
3075                 { 0x1f, 0x0000 },
3076                 { 0x0d, 0xf880 },
3077
3078                 { 0x1f, 0x0001 },
3079                 { 0x17, 0x0cc0 },
3080
3081                 { 0x1f, 0x0001 },
3082                 { 0x0b, 0xa4d8 },
3083                 { 0x09, 0x281c },
3084                 { 0x07, 0x2883 },
3085                 { 0x0a, 0x6b35 },
3086                 { 0x1d, 0x3da4 },
3087                 { 0x1c, 0xeffd },
3088                 { 0x14, 0x7f52 },
3089                 { 0x18, 0x7fc6 },
3090                 { 0x08, 0x0601 },
3091                 { 0x06, 0x4063 },
3092                 { 0x10, 0xf074 },
3093                 { 0x1f, 0x0003 },
3094                 { 0x13, 0x0789 },
3095                 { 0x12, 0xf4bd },
3096                 { 0x1a, 0x04fd },
3097                 { 0x14, 0x84b0 },
3098                 { 0x1f, 0x0000 },
3099                 { 0x00, 0x9200 },
3100
3101                 { 0x1f, 0x0005 },
3102                 { 0x01, 0x0340 },
3103                 { 0x1f, 0x0001 },
3104                 { 0x04, 0x4000 },
3105                 { 0x03, 0x1d21 },
3106                 { 0x02, 0x0c32 },
3107                 { 0x01, 0x0200 },
3108                 { 0x00, 0x5554 },
3109                 { 0x04, 0x4800 },
3110                 { 0x04, 0x4000 },
3111                 { 0x04, 0xf000 },
3112                 { 0x03, 0xdf01 },
3113                 { 0x02, 0xdf20 },
3114                 { 0x01, 0x101a },
3115                 { 0x00, 0xa0ff },
3116                 { 0x04, 0xf800 },
3117                 { 0x04, 0xf000 },
3118                 { 0x1f, 0x0000 },
3119
3120                 { 0x1f, 0x0007 },
3121                 { 0x1e, 0x0023 },
3122                 { 0x16, 0x0000 },
3123                 { 0x1f, 0x0000 }
3124         };
3125
3126         rtl_writephy_batch(tp, phy_reg_init);
3127 }
3128
3129 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3130 {
3131         static const struct phy_reg phy_reg_init[] = {
3132                 { 0x1f, 0x0001 },
3133                 { 0x17, 0x0cc0 },
3134
3135                 { 0x1f, 0x0007 },
3136                 { 0x1e, 0x002d },
3137                 { 0x18, 0x0040 },
3138                 { 0x1f, 0x0000 }
3139         };
3140
3141         rtl_writephy_batch(tp, phy_reg_init);
3142         rtl_patchphy(tp, 0x0d, 1 << 5);
3143 }
3144
3145 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3146 {
3147         static const struct phy_reg phy_reg_init[] = {
3148                 /* Enable Delay cap */
3149                 { 0x1f, 0x0005 },
3150                 { 0x05, 0x8b80 },
3151                 { 0x06, 0xc896 },
3152                 { 0x1f, 0x0000 },
3153
3154                 /* Channel estimation fine tune */
3155                 { 0x1f, 0x0001 },
3156                 { 0x0b, 0x6c20 },
3157                 { 0x07, 0x2872 },
3158                 { 0x1c, 0xefff },
3159                 { 0x1f, 0x0003 },
3160                 { 0x14, 0x6420 },
3161                 { 0x1f, 0x0000 },
3162
3163                 /* Update PFM & 10M TX idle timer */
3164                 { 0x1f, 0x0007 },
3165                 { 0x1e, 0x002f },
3166                 { 0x15, 0x1919 },
3167                 { 0x1f, 0x0000 },
3168
3169                 { 0x1f, 0x0007 },
3170                 { 0x1e, 0x00ac },
3171                 { 0x18, 0x0006 },
3172                 { 0x1f, 0x0000 }
3173         };
3174
3175         rtl_apply_firmware(tp);
3176
3177         rtl_writephy_batch(tp, phy_reg_init);
3178
3179         /* DCO enable for 10M IDLE Power */
3180         rtl_writephy(tp, 0x1f, 0x0007);
3181         rtl_writephy(tp, 0x1e, 0x0023);
3182         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184
3185         /* For impedance matching */
3186         rtl_writephy(tp, 0x1f, 0x0002);
3187         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3188         rtl_writephy(tp, 0x1f, 0x0000);
3189
3190         /* PHY auto speed down */
3191         rtl_writephy(tp, 0x1f, 0x0007);
3192         rtl_writephy(tp, 0x1e, 0x002d);
3193         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3194         rtl_writephy(tp, 0x1f, 0x0000);
3195         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3196
3197         rtl_writephy(tp, 0x1f, 0x0005);
3198         rtl_writephy(tp, 0x05, 0x8b86);
3199         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3200         rtl_writephy(tp, 0x1f, 0x0000);
3201
3202         rtl_writephy(tp, 0x1f, 0x0005);
3203         rtl_writephy(tp, 0x05, 0x8b85);
3204         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3205         rtl_writephy(tp, 0x1f, 0x0007);
3206         rtl_writephy(tp, 0x1e, 0x0020);
3207         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3208         rtl_writephy(tp, 0x1f, 0x0006);
3209         rtl_writephy(tp, 0x00, 0x5a00);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211         rtl_writephy(tp, 0x0d, 0x0007);
3212         rtl_writephy(tp, 0x0e, 0x003c);
3213         rtl_writephy(tp, 0x0d, 0x4007);
3214         rtl_writephy(tp, 0x0e, 0x0000);
3215         rtl_writephy(tp, 0x0d, 0x0000);
3216 }
3217
3218 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3219 {
3220         const u16 w[] = {
3221                 addr[0] | (addr[1] << 8),
3222                 addr[2] | (addr[3] << 8),
3223                 addr[4] | (addr[5] << 8)
3224         };
3225
3226         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3227         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3228         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3229         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3230 }
3231
3232 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3233 {
3234         static const struct phy_reg phy_reg_init[] = {
3235                 /* Enable Delay cap */
3236                 { 0x1f, 0x0004 },
3237                 { 0x1f, 0x0007 },
3238                 { 0x1e, 0x00ac },
3239                 { 0x18, 0x0006 },
3240                 { 0x1f, 0x0002 },
3241                 { 0x1f, 0x0000 },
3242                 { 0x1f, 0x0000 },
3243
3244                 /* Channel estimation fine tune */
3245                 { 0x1f, 0x0003 },
3246                 { 0x09, 0xa20f },
3247                 { 0x1f, 0x0000 },
3248                 { 0x1f, 0x0000 },
3249
3250                 /* Green Setting */
3251                 { 0x1f, 0x0005 },
3252                 { 0x05, 0x8b5b },
3253                 { 0x06, 0x9222 },
3254                 { 0x05, 0x8b6d },
3255                 { 0x06, 0x8000 },
3256                 { 0x05, 0x8b76 },
3257                 { 0x06, 0x8000 },
3258                 { 0x1f, 0x0000 }
3259         };
3260
3261         rtl_apply_firmware(tp);
3262
3263         rtl_writephy_batch(tp, phy_reg_init);
3264
3265         /* For 4-corner performance improve */
3266         rtl_writephy(tp, 0x1f, 0x0005);
3267         rtl_writephy(tp, 0x05, 0x8b80);
3268         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3269         rtl_writephy(tp, 0x1f, 0x0000);
3270
3271         /* PHY auto speed down */
3272         rtl_writephy(tp, 0x1f, 0x0004);
3273         rtl_writephy(tp, 0x1f, 0x0007);
3274         rtl_writephy(tp, 0x1e, 0x002d);
3275         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3276         rtl_writephy(tp, 0x1f, 0x0002);
3277         rtl_writephy(tp, 0x1f, 0x0000);
3278         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3279
3280         /* improve 10M EEE waveform */
3281         rtl_writephy(tp, 0x1f, 0x0005);
3282         rtl_writephy(tp, 0x05, 0x8b86);
3283         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3284         rtl_writephy(tp, 0x1f, 0x0000);
3285
3286         /* Improve 2-pair detection performance */
3287         rtl_writephy(tp, 0x1f, 0x0005);
3288         rtl_writephy(tp, 0x05, 0x8b85);
3289         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3290         rtl_writephy(tp, 0x1f, 0x0000);
3291
3292         rtl8168f_config_eee_phy(tp);
3293         rtl_enable_eee(tp);
3294
3295         /* Green feature */
3296         rtl_writephy(tp, 0x1f, 0x0003);
3297         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3298         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3299         rtl_writephy(tp, 0x1f, 0x0000);
3300         rtl_writephy(tp, 0x1f, 0x0005);
3301         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3302         rtl_writephy(tp, 0x1f, 0x0000);
3303
3304         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3305         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3306 }
3307
3308 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3309 {
3310         /* For 4-corner performance improve */
3311         rtl_writephy(tp, 0x1f, 0x0005);
3312         rtl_writephy(tp, 0x05, 0x8b80);
3313         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3314         rtl_writephy(tp, 0x1f, 0x0000);
3315
3316         /* PHY auto speed down */
3317         rtl_writephy(tp, 0x1f, 0x0007);
3318         rtl_writephy(tp, 0x1e, 0x002d);
3319         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3320         rtl_writephy(tp, 0x1f, 0x0000);
3321         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3322
3323         /* Improve 10M EEE waveform */
3324         rtl_writephy(tp, 0x1f, 0x0005);
3325         rtl_writephy(tp, 0x05, 0x8b86);
3326         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3327         rtl_writephy(tp, 0x1f, 0x0000);
3328
3329         rtl8168f_config_eee_phy(tp);
3330         rtl_enable_eee(tp);
3331 }
3332
3333 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3334 {
3335         static const struct phy_reg phy_reg_init[] = {
3336                 /* Channel estimation fine tune */
3337                 { 0x1f, 0x0003 },
3338                 { 0x09, 0xa20f },
3339                 { 0x1f, 0x0000 },
3340
3341                 /* Modify green table for giga & fnet */
3342                 { 0x1f, 0x0005 },
3343                 { 0x05, 0x8b55 },
3344                 { 0x06, 0x0000 },
3345                 { 0x05, 0x8b5e },
3346                 { 0x06, 0x0000 },
3347                 { 0x05, 0x8b67 },
3348                 { 0x06, 0x0000 },
3349                 { 0x05, 0x8b70 },
3350                 { 0x06, 0x0000 },
3351                 { 0x1f, 0x0000 },
3352                 { 0x1f, 0x0007 },
3353                 { 0x1e, 0x0078 },
3354                 { 0x17, 0x0000 },
3355                 { 0x19, 0x00fb },
3356                 { 0x1f, 0x0000 },
3357
3358                 /* Modify green table for 10M */
3359                 { 0x1f, 0x0005 },
3360                 { 0x05, 0x8b79 },
3361                 { 0x06, 0xaa00 },
3362                 { 0x1f, 0x0000 },
3363
3364                 /* Disable hiimpedance detection (RTCT) */
3365                 { 0x1f, 0x0003 },
3366                 { 0x01, 0x328a },
3367                 { 0x1f, 0x0000 }
3368         };
3369
3370         rtl_apply_firmware(tp);
3371
3372         rtl_writephy_batch(tp, phy_reg_init);
3373
3374         rtl8168f_hw_phy_config(tp);
3375
3376         /* Improve 2-pair detection performance */
3377         rtl_writephy(tp, 0x1f, 0x0005);
3378         rtl_writephy(tp, 0x05, 0x8b85);
3379         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3380         rtl_writephy(tp, 0x1f, 0x0000);
3381 }
3382
3383 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3384 {
3385         rtl_apply_firmware(tp);
3386
3387         rtl8168f_hw_phy_config(tp);
3388 }
3389
3390 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3391 {
3392         static const struct phy_reg phy_reg_init[] = {
3393                 /* Channel estimation fine tune */
3394                 { 0x1f, 0x0003 },
3395                 { 0x09, 0xa20f },
3396                 { 0x1f, 0x0000 },
3397
3398                 /* Modify green table for giga & fnet */
3399                 { 0x1f, 0x0005 },
3400                 { 0x05, 0x8b55 },
3401                 { 0x06, 0x0000 },
3402                 { 0x05, 0x8b5e },
3403                 { 0x06, 0x0000 },
3404                 { 0x05, 0x8b67 },
3405                 { 0x06, 0x0000 },
3406                 { 0x05, 0x8b70 },
3407                 { 0x06, 0x0000 },
3408                 { 0x1f, 0x0000 },
3409                 { 0x1f, 0x0007 },
3410                 { 0x1e, 0x0078 },
3411                 { 0x17, 0x0000 },
3412                 { 0x19, 0x00aa },
3413                 { 0x1f, 0x0000 },
3414
3415                 /* Modify green table for 10M */
3416                 { 0x1f, 0x0005 },
3417                 { 0x05, 0x8b79 },
3418                 { 0x06, 0xaa00 },
3419                 { 0x1f, 0x0000 },
3420
3421                 /* Disable hiimpedance detection (RTCT) */
3422                 { 0x1f, 0x0003 },
3423                 { 0x01, 0x328a },
3424                 { 0x1f, 0x0000 }
3425         };
3426
3427
3428         rtl_apply_firmware(tp);
3429
3430         rtl8168f_hw_phy_config(tp);
3431
3432         /* Improve 2-pair detection performance */
3433         rtl_writephy(tp, 0x1f, 0x0005);
3434         rtl_writephy(tp, 0x05, 0x8b85);
3435         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3436         rtl_writephy(tp, 0x1f, 0x0000);
3437
3438         rtl_writephy_batch(tp, phy_reg_init);
3439
3440         /* Modify green table for giga */
3441         rtl_writephy(tp, 0x1f, 0x0005);
3442         rtl_writephy(tp, 0x05, 0x8b54);
3443         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3444         rtl_writephy(tp, 0x05, 0x8b5d);
3445         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3446         rtl_writephy(tp, 0x05, 0x8a7c);
3447         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3448         rtl_writephy(tp, 0x05, 0x8a7f);
3449         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3450         rtl_writephy(tp, 0x05, 0x8a82);
3451         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3452         rtl_writephy(tp, 0x05, 0x8a85);
3453         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3454         rtl_writephy(tp, 0x05, 0x8a88);
3455         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3456         rtl_writephy(tp, 0x1f, 0x0000);
3457
3458         /* uc same-seed solution */
3459         rtl_writephy(tp, 0x1f, 0x0005);
3460         rtl_writephy(tp, 0x05, 0x8b85);
3461         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3462         rtl_writephy(tp, 0x1f, 0x0000);
3463
3464         /* Green feature */
3465         rtl_writephy(tp, 0x1f, 0x0003);
3466         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3467         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3468         rtl_writephy(tp, 0x1f, 0x0000);
3469 }
3470
3471 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3472 {
3473         phy_write(tp->phydev, 0x1f, 0x0a43);
3474         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3475 }
3476
3477 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3478 {
3479         struct phy_device *phydev = tp->phydev;
3480
3481         phy_write(phydev, 0x1f, 0x0bcc);
3482         phy_clear_bits(phydev, 0x14, BIT(8));
3483
3484         phy_write(phydev, 0x1f, 0x0a44);
3485         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3486
3487         phy_write(phydev, 0x1f, 0x0a43);
3488         phy_write(phydev, 0x13, 0x8084);
3489         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3490         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3491
3492         phy_write(phydev, 0x1f, 0x0000);
3493 }
3494
3495 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3496 {
3497         rtl_apply_firmware(tp);
3498
3499         rtl_writephy(tp, 0x1f, 0x0a46);
3500         if (rtl_readphy(tp, 0x10) & 0x0100) {
3501                 rtl_writephy(tp, 0x1f, 0x0bcc);
3502                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3503         } else {
3504                 rtl_writephy(tp, 0x1f, 0x0bcc);
3505                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3506         }
3507
3508         rtl_writephy(tp, 0x1f, 0x0a46);
3509         if (rtl_readphy(tp, 0x13) & 0x0100) {
3510                 rtl_writephy(tp, 0x1f, 0x0c41);
3511                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3512         } else {
3513                 rtl_writephy(tp, 0x1f, 0x0c41);
3514                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3515         }
3516
3517         /* Enable PHY auto speed down */
3518         rtl_writephy(tp, 0x1f, 0x0a44);
3519         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3520
3521         rtl8168g_phy_adjust_10m_aldps(tp);
3522
3523         /* EEE auto-fallback function */
3524         rtl_writephy(tp, 0x1f, 0x0a4b);
3525         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3526
3527         /* Enable UC LPF tune function */
3528         rtl_writephy(tp, 0x1f, 0x0a43);
3529         rtl_writephy(tp, 0x13, 0x8012);
3530         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3531
3532         rtl_writephy(tp, 0x1f, 0x0c42);
3533         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3534
3535         /* Improve SWR Efficiency */
3536         rtl_writephy(tp, 0x1f, 0x0bcd);
3537         rtl_writephy(tp, 0x14, 0x5065);
3538         rtl_writephy(tp, 0x14, 0xd065);
3539         rtl_writephy(tp, 0x1f, 0x0bc8);
3540         rtl_writephy(tp, 0x11, 0x5655);
3541         rtl_writephy(tp, 0x1f, 0x0bcd);
3542         rtl_writephy(tp, 0x14, 0x1065);
3543         rtl_writephy(tp, 0x14, 0x9065);
3544         rtl_writephy(tp, 0x14, 0x1065);
3545
3546         rtl8168g_disable_aldps(tp);
3547         rtl8168g_config_eee_phy(tp);
3548         rtl_enable_eee(tp);
3549 }
3550
3551 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3552 {
3553         rtl_apply_firmware(tp);
3554         rtl8168g_config_eee_phy(tp);
3555         rtl_enable_eee(tp);
3556 }
3557
3558 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3559 {
3560         u16 dout_tapbin;
3561         u32 data;
3562
3563         rtl_apply_firmware(tp);
3564
3565         /* CHN EST parameters adjust - giga master */
3566         rtl_writephy(tp, 0x1f, 0x0a43);
3567         rtl_writephy(tp, 0x13, 0x809b);
3568         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3569         rtl_writephy(tp, 0x13, 0x80a2);
3570         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3571         rtl_writephy(tp, 0x13, 0x80a4);
3572         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3573         rtl_writephy(tp, 0x13, 0x809c);
3574         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576
3577         /* CHN EST parameters adjust - giga slave */
3578         rtl_writephy(tp, 0x1f, 0x0a43);
3579         rtl_writephy(tp, 0x13, 0x80ad);
3580         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3581         rtl_writephy(tp, 0x13, 0x80b4);
3582         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3583         rtl_writephy(tp, 0x13, 0x80ac);
3584         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3585         rtl_writephy(tp, 0x1f, 0x0000);
3586
3587         /* CHN EST parameters adjust - fnet */
3588         rtl_writephy(tp, 0x1f, 0x0a43);
3589         rtl_writephy(tp, 0x13, 0x808e);
3590         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3591         rtl_writephy(tp, 0x13, 0x8090);
3592         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3593         rtl_writephy(tp, 0x13, 0x8092);
3594         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3595         rtl_writephy(tp, 0x1f, 0x0000);
3596
3597         /* enable R-tune & PGA-retune function */
3598         dout_tapbin = 0;
3599         rtl_writephy(tp, 0x1f, 0x0a46);
3600         data = rtl_readphy(tp, 0x13);
3601         data &= 3;
3602         data <<= 2;
3603         dout_tapbin |= data;
3604         data = rtl_readphy(tp, 0x12);
3605         data &= 0xc000;
3606         data >>= 14;
3607         dout_tapbin |= data;
3608         dout_tapbin = ~(dout_tapbin^0x08);
3609         dout_tapbin <<= 12;
3610         dout_tapbin &= 0xf000;
3611         rtl_writephy(tp, 0x1f, 0x0a43);
3612         rtl_writephy(tp, 0x13, 0x827a);
3613         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3614         rtl_writephy(tp, 0x13, 0x827b);
3615         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3616         rtl_writephy(tp, 0x13, 0x827c);
3617         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3618         rtl_writephy(tp, 0x13, 0x827d);
3619         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3620
3621         rtl_writephy(tp, 0x1f, 0x0a43);
3622         rtl_writephy(tp, 0x13, 0x0811);
3623         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3624         rtl_writephy(tp, 0x1f, 0x0a42);
3625         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3626         rtl_writephy(tp, 0x1f, 0x0000);
3627
3628         /* enable GPHY 10M */
3629         rtl_writephy(tp, 0x1f, 0x0a44);
3630         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3631         rtl_writephy(tp, 0x1f, 0x0000);
3632
3633         /* SAR ADC performance */
3634         rtl_writephy(tp, 0x1f, 0x0bca);
3635         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3636         rtl_writephy(tp, 0x1f, 0x0000);
3637
3638         rtl_writephy(tp, 0x1f, 0x0a43);
3639         rtl_writephy(tp, 0x13, 0x803f);
3640         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3641         rtl_writephy(tp, 0x13, 0x8047);
3642         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3643         rtl_writephy(tp, 0x13, 0x804f);
3644         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3645         rtl_writephy(tp, 0x13, 0x8057);
3646         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3647         rtl_writephy(tp, 0x13, 0x805f);
3648         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3649         rtl_writephy(tp, 0x13, 0x8067);
3650         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3651         rtl_writephy(tp, 0x13, 0x806f);
3652         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3653         rtl_writephy(tp, 0x1f, 0x0000);
3654
3655         /* disable phy pfm mode */
3656         rtl_writephy(tp, 0x1f, 0x0a44);
3657         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3658         rtl_writephy(tp, 0x1f, 0x0000);
3659
3660         rtl8168g_disable_aldps(tp);
3661         rtl8168g_config_eee_phy(tp);
3662         rtl_enable_eee(tp);
3663 }
3664
3665 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3666 {
3667         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3668         u16 rlen;
3669         u32 data;
3670
3671         rtl_apply_firmware(tp);
3672
3673         /* CHIN EST parameter update */
3674         rtl_writephy(tp, 0x1f, 0x0a43);
3675         rtl_writephy(tp, 0x13, 0x808a);
3676         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3677         rtl_writephy(tp, 0x1f, 0x0000);
3678
3679         /* enable R-tune & PGA-retune function */
3680         rtl_writephy(tp, 0x1f, 0x0a43);
3681         rtl_writephy(tp, 0x13, 0x0811);
3682         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3683         rtl_writephy(tp, 0x1f, 0x0a42);
3684         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3685         rtl_writephy(tp, 0x1f, 0x0000);
3686
3687         /* enable GPHY 10M */
3688         rtl_writephy(tp, 0x1f, 0x0a44);
3689         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3690         rtl_writephy(tp, 0x1f, 0x0000);
3691
3692         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3693         data = r8168_mac_ocp_read(tp, 0xdd02);
3694         ioffset_p3 = ((data & 0x80)>>7);
3695         ioffset_p3 <<= 3;
3696
3697         data = r8168_mac_ocp_read(tp, 0xdd00);
3698         ioffset_p3 |= ((data & (0xe000))>>13);
3699         ioffset_p2 = ((data & (0x1e00))>>9);
3700         ioffset_p1 = ((data & (0x01e0))>>5);
3701         ioffset_p0 = ((data & 0x0010)>>4);
3702         ioffset_p0 <<= 3;
3703         ioffset_p0 |= (data & (0x07));
3704         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3705
3706         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3707             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3708                 rtl_writephy(tp, 0x1f, 0x0bcf);
3709                 rtl_writephy(tp, 0x16, data);
3710                 rtl_writephy(tp, 0x1f, 0x0000);
3711         }
3712
3713         /* Modify rlen (TX LPF corner frequency) level */
3714         rtl_writephy(tp, 0x1f, 0x0bcd);
3715         data = rtl_readphy(tp, 0x16);
3716         data &= 0x000f;
3717         rlen = 0;
3718         if (data > 3)
3719                 rlen = data - 3;
3720         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3721         rtl_writephy(tp, 0x17, data);
3722         rtl_writephy(tp, 0x1f, 0x0bcd);
3723         rtl_writephy(tp, 0x1f, 0x0000);
3724
3725         /* disable phy pfm mode */
3726         rtl_writephy(tp, 0x1f, 0x0a44);
3727         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3728         rtl_writephy(tp, 0x1f, 0x0000);
3729
3730         rtl8168g_disable_aldps(tp);
3731         rtl8168g_config_eee_phy(tp);
3732         rtl_enable_eee(tp);
3733 }
3734
3735 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3736 {
3737         /* Enable PHY auto speed down */
3738         rtl_writephy(tp, 0x1f, 0x0a44);
3739         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         rtl8168g_phy_adjust_10m_aldps(tp);
3743
3744         /* Enable EEE auto-fallback function */
3745         rtl_writephy(tp, 0x1f, 0x0a4b);
3746         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3747         rtl_writephy(tp, 0x1f, 0x0000);
3748
3749         /* Enable UC LPF tune function */
3750         rtl_writephy(tp, 0x1f, 0x0a43);
3751         rtl_writephy(tp, 0x13, 0x8012);
3752         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754
3755         /* set rg_sel_sdm_rate */
3756         rtl_writephy(tp, 0x1f, 0x0c42);
3757         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3758         rtl_writephy(tp, 0x1f, 0x0000);
3759
3760         rtl8168g_disable_aldps(tp);
3761         rtl8168g_config_eee_phy(tp);
3762         rtl_enable_eee(tp);
3763 }
3764
3765 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3766 {
3767         rtl8168g_phy_adjust_10m_aldps(tp);
3768
3769         /* Enable UC LPF tune function */
3770         rtl_writephy(tp, 0x1f, 0x0a43);
3771         rtl_writephy(tp, 0x13, 0x8012);
3772         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3773         rtl_writephy(tp, 0x1f, 0x0000);
3774
3775         /* Set rg_sel_sdm_rate */
3776         rtl_writephy(tp, 0x1f, 0x0c42);
3777         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3778         rtl_writephy(tp, 0x1f, 0x0000);
3779
3780         /* Channel estimation parameters */
3781         rtl_writephy(tp, 0x1f, 0x0a43);
3782         rtl_writephy(tp, 0x13, 0x80f3);
3783         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3784         rtl_writephy(tp, 0x13, 0x80f0);
3785         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3786         rtl_writephy(tp, 0x13, 0x80ef);
3787         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3788         rtl_writephy(tp, 0x13, 0x80f6);
3789         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3790         rtl_writephy(tp, 0x13, 0x80ec);
3791         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3792         rtl_writephy(tp, 0x13, 0x80ed);
3793         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3794         rtl_writephy(tp, 0x13, 0x80f2);
3795         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3796         rtl_writephy(tp, 0x13, 0x80f4);
3797         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3798         rtl_writephy(tp, 0x1f, 0x0a43);
3799         rtl_writephy(tp, 0x13, 0x8110);
3800         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3801         rtl_writephy(tp, 0x13, 0x810f);
3802         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3803         rtl_writephy(tp, 0x13, 0x8111);
3804         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3805         rtl_writephy(tp, 0x13, 0x8113);
3806         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3807         rtl_writephy(tp, 0x13, 0x8115);
3808         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3809         rtl_writephy(tp, 0x13, 0x810e);
3810         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3811         rtl_writephy(tp, 0x13, 0x810c);
3812         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3813         rtl_writephy(tp, 0x13, 0x810b);
3814         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3815         rtl_writephy(tp, 0x1f, 0x0a43);
3816         rtl_writephy(tp, 0x13, 0x80d1);
3817         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3818         rtl_writephy(tp, 0x13, 0x80cd);
3819         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3820         rtl_writephy(tp, 0x13, 0x80d3);
3821         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3822         rtl_writephy(tp, 0x13, 0x80d5);
3823         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3824         rtl_writephy(tp, 0x13, 0x80d7);
3825         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3826
3827         /* Force PWM-mode */
3828         rtl_writephy(tp, 0x1f, 0x0bcd);
3829         rtl_writephy(tp, 0x14, 0x5065);
3830         rtl_writephy(tp, 0x14, 0xd065);
3831         rtl_writephy(tp, 0x1f, 0x0bc8);
3832         rtl_writephy(tp, 0x12, 0x00ed);
3833         rtl_writephy(tp, 0x1f, 0x0bcd);
3834         rtl_writephy(tp, 0x14, 0x1065);
3835         rtl_writephy(tp, 0x14, 0x9065);
3836         rtl_writephy(tp, 0x14, 0x1065);
3837         rtl_writephy(tp, 0x1f, 0x0000);
3838
3839         rtl8168g_disable_aldps(tp);
3840         rtl8168g_config_eee_phy(tp);
3841         rtl_enable_eee(tp);
3842 }
3843
3844 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3845 {
3846         static const struct phy_reg phy_reg_init[] = {
3847                 { 0x1f, 0x0003 },
3848                 { 0x08, 0x441d },
3849                 { 0x01, 0x9100 },
3850                 { 0x1f, 0x0000 }
3851         };
3852
3853         rtl_writephy(tp, 0x1f, 0x0000);
3854         rtl_patchphy(tp, 0x11, 1 << 12);
3855         rtl_patchphy(tp, 0x19, 1 << 13);
3856         rtl_patchphy(tp, 0x10, 1 << 15);
3857
3858         rtl_writephy_batch(tp, phy_reg_init);
3859 }
3860
3861 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3862 {
3863         static const struct phy_reg phy_reg_init[] = {
3864                 { 0x1f, 0x0005 },
3865                 { 0x1a, 0x0000 },
3866                 { 0x1f, 0x0000 },
3867
3868                 { 0x1f, 0x0004 },
3869                 { 0x1c, 0x0000 },
3870                 { 0x1f, 0x0000 },
3871
3872                 { 0x1f, 0x0001 },
3873                 { 0x15, 0x7701 },
3874                 { 0x1f, 0x0000 }
3875         };
3876
3877         /* Disable ALDPS before ram code */
3878         rtl_writephy(tp, 0x1f, 0x0000);
3879         rtl_writephy(tp, 0x18, 0x0310);
3880         msleep(100);
3881
3882         rtl_apply_firmware(tp);
3883
3884         rtl_writephy_batch(tp, phy_reg_init);
3885 }
3886
3887 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3888 {
3889         /* Disable ALDPS before setting firmware */
3890         rtl_writephy(tp, 0x1f, 0x0000);
3891         rtl_writephy(tp, 0x18, 0x0310);
3892         msleep(20);
3893
3894         rtl_apply_firmware(tp);
3895
3896         /* EEE setting */
3897         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3898         rtl_writephy(tp, 0x1f, 0x0004);
3899         rtl_writephy(tp, 0x10, 0x401f);
3900         rtl_writephy(tp, 0x19, 0x7030);
3901         rtl_writephy(tp, 0x1f, 0x0000);
3902 }
3903
3904 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3905 {
3906         static const struct phy_reg phy_reg_init[] = {
3907                 { 0x1f, 0x0004 },
3908                 { 0x10, 0xc07f },
3909                 { 0x19, 0x7030 },
3910                 { 0x1f, 0x0000 }
3911         };
3912
3913         /* Disable ALDPS before ram code */
3914         rtl_writephy(tp, 0x1f, 0x0000);
3915         rtl_writephy(tp, 0x18, 0x0310);
3916         msleep(100);
3917
3918         rtl_apply_firmware(tp);
3919
3920         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3921         rtl_writephy_batch(tp, phy_reg_init);
3922
3923         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3924 }
3925
3926 static void rtl_hw_phy_config(struct net_device *dev)
3927 {
3928         static const rtl_generic_fct phy_configs[] = {
3929                 /* PCI devices. */
3930                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3931                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3932                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3933                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3934                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3935                 /* PCI-E devices. */
3936                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3937                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3938                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3939                 [RTL_GIGA_MAC_VER_10] = NULL,
3940                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3941                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3942                 [RTL_GIGA_MAC_VER_13] = NULL,
3943                 [RTL_GIGA_MAC_VER_14] = NULL,
3944                 [RTL_GIGA_MAC_VER_15] = NULL,
3945                 [RTL_GIGA_MAC_VER_16] = NULL,
3946                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3947                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3948                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3949                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3950                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3951                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3952                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3953                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3954                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3955                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3956                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3957                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3958                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3959                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3960                 [RTL_GIGA_MAC_VER_31] = NULL,
3961                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3962                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3963                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3964                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3965                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3966                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3967                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3968                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3969                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3970                 [RTL_GIGA_MAC_VER_41] = NULL,
3971                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3972                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3973                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3974                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3975                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3976                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3977                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3978                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3979                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3980                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3981         };
3982         struct rtl8169_private *tp = netdev_priv(dev);
3983
3984         if (phy_configs[tp->mac_version])
3985                 phy_configs[tp->mac_version](tp);
3986 }
3987
3988 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3989 {
3990         if (!test_and_set_bit(flag, tp->wk.flags))
3991                 schedule_work(&tp->wk.work);
3992 }
3993
3994 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3995 {
3996         rtl_hw_phy_config(dev);
3997
3998         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3999                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4000                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4001                 netif_dbg(tp, drv, dev,
4002                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4003                 RTL_W8(tp, 0x82, 0x01);
4004         }
4005
4006         /* We may have called phy_speed_down before */
4007         phy_speed_up(tp->phydev);
4008
4009         genphy_soft_reset(tp->phydev);
4010 }
4011
4012 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4013 {
4014         rtl_lock_work(tp);
4015
4016         rtl_unlock_config_regs(tp);
4017
4018         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4019         RTL_R32(tp, MAC4);
4020
4021         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4022         RTL_R32(tp, MAC0);
4023
4024         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4025                 rtl_rar_exgmac_set(tp, addr);
4026
4027         rtl_lock_config_regs(tp);
4028
4029         rtl_unlock_work(tp);
4030 }
4031
4032 static int rtl_set_mac_address(struct net_device *dev, void *p)
4033 {
4034         struct rtl8169_private *tp = netdev_priv(dev);
4035         struct device *d = tp_to_dev(tp);
4036         int ret;
4037
4038         ret = eth_mac_addr(dev, p);
4039         if (ret)
4040                 return ret;
4041
4042         pm_runtime_get_noresume(d);
4043
4044         if (pm_runtime_active(d))
4045                 rtl_rar_set(tp, dev->dev_addr);
4046
4047         pm_runtime_put_noidle(d);
4048
4049         return 0;
4050 }
4051
4052 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4053 {
4054         struct rtl8169_private *tp = netdev_priv(dev);
4055
4056         if (!netif_running(dev))
4057                 return -ENODEV;
4058
4059         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4060 }
4061
4062 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4063 {
4064         struct mdio_ops *ops = &tp->mdio_ops;
4065
4066         switch (tp->mac_version) {
4067         case RTL_GIGA_MAC_VER_27:
4068                 ops->write      = r8168dp_1_mdio_write;
4069                 ops->read       = r8168dp_1_mdio_read;
4070                 break;
4071         case RTL_GIGA_MAC_VER_28:
4072         case RTL_GIGA_MAC_VER_31:
4073                 ops->write      = r8168dp_2_mdio_write;
4074                 ops->read       = r8168dp_2_mdio_read;
4075                 break;
4076         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4077                 ops->write      = r8168g_mdio_write;
4078                 ops->read       = r8168g_mdio_read;
4079                 break;
4080         default:
4081                 ops->write      = r8169_mdio_write;
4082                 ops->read       = r8169_mdio_read;
4083                 break;
4084         }
4085 }
4086
4087 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4088 {
4089         switch (tp->mac_version) {
4090         case RTL_GIGA_MAC_VER_25:
4091         case RTL_GIGA_MAC_VER_26:
4092         case RTL_GIGA_MAC_VER_29:
4093         case RTL_GIGA_MAC_VER_30:
4094         case RTL_GIGA_MAC_VER_32:
4095         case RTL_GIGA_MAC_VER_33:
4096         case RTL_GIGA_MAC_VER_34:
4097         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4098                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4099                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4100                 break;
4101         default:
4102                 break;
4103         }
4104 }
4105
4106 static void rtl_pll_power_down(struct rtl8169_private *tp)
4107 {
4108         if (r8168_check_dash(tp))
4109                 return;
4110
4111         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4112             tp->mac_version == RTL_GIGA_MAC_VER_33)
4113                 rtl_ephy_write(tp, 0x19, 0xff64);
4114
4115         if (device_may_wakeup(tp_to_dev(tp))) {
4116                 phy_speed_down(tp->phydev, false);
4117                 rtl_wol_suspend_quirk(tp);
4118                 return;
4119         }
4120
4121         switch (tp->mac_version) {
4122         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4123         case RTL_GIGA_MAC_VER_37:
4124         case RTL_GIGA_MAC_VER_39:
4125         case RTL_GIGA_MAC_VER_43:
4126         case RTL_GIGA_MAC_VER_44:
4127         case RTL_GIGA_MAC_VER_45:
4128         case RTL_GIGA_MAC_VER_46:
4129         case RTL_GIGA_MAC_VER_47:
4130         case RTL_GIGA_MAC_VER_48:
4131         case RTL_GIGA_MAC_VER_50:
4132         case RTL_GIGA_MAC_VER_51:
4133                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4134                 break;
4135         case RTL_GIGA_MAC_VER_40:
4136         case RTL_GIGA_MAC_VER_41:
4137         case RTL_GIGA_MAC_VER_49:
4138                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4139                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4140                 break;
4141         default:
4142                 break;
4143         }
4144 }
4145
4146 static void rtl_pll_power_up(struct rtl8169_private *tp)
4147 {
4148         switch (tp->mac_version) {
4149         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4150         case RTL_GIGA_MAC_VER_37:
4151         case RTL_GIGA_MAC_VER_39:
4152         case RTL_GIGA_MAC_VER_43:
4153                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4154                 break;
4155         case RTL_GIGA_MAC_VER_44:
4156         case RTL_GIGA_MAC_VER_45:
4157         case RTL_GIGA_MAC_VER_46:
4158         case RTL_GIGA_MAC_VER_47:
4159         case RTL_GIGA_MAC_VER_48:
4160         case RTL_GIGA_MAC_VER_50:
4161         case RTL_GIGA_MAC_VER_51:
4162                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4163                 break;
4164         case RTL_GIGA_MAC_VER_40:
4165         case RTL_GIGA_MAC_VER_41:
4166         case RTL_GIGA_MAC_VER_49:
4167                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4168                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4169                 break;
4170         default:
4171                 break;
4172         }
4173
4174         phy_resume(tp->phydev);
4175         /* give MAC/PHY some time to resume */
4176         msleep(20);
4177 }
4178
4179 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4180 {
4181         switch (tp->mac_version) {
4182         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4183         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4184                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4185                 break;
4186         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4187         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4188         case RTL_GIGA_MAC_VER_38:
4189                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4190                 break;
4191         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4192                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4193                 break;
4194         default:
4195                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4196                 break;
4197         }
4198 }
4199
4200 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4201 {
4202         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4203 }
4204
4205 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4206 {
4207         if (tp->jumbo_ops.enable) {
4208                 rtl_unlock_config_regs(tp);
4209                 tp->jumbo_ops.enable(tp);
4210                 rtl_lock_config_regs(tp);
4211         }
4212 }
4213
4214 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4215 {
4216         if (tp->jumbo_ops.disable) {
4217                 rtl_unlock_config_regs(tp);
4218                 tp->jumbo_ops.disable(tp);
4219                 rtl_lock_config_regs(tp);
4220         }
4221 }
4222
4223 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4224 {
4225         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4226         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4227         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4228 }
4229
4230 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4231 {
4232         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4233         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4234         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4235 }
4236
4237 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4238 {
4239         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4240 }
4241
4242 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4243 {
4244         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4245 }
4246
4247 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4248 {
4249         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4250         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4251         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4252         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4253 }
4254
4255 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4256 {
4257         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4258         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4259         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4260         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4261 }
4262
4263 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4264 {
4265         rtl_tx_performance_tweak(tp,
4266                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4267 }
4268
4269 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4270 {
4271         rtl_tx_performance_tweak(tp,
4272                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4273 }
4274
4275 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4276 {
4277         r8168b_0_hw_jumbo_enable(tp);
4278
4279         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4280 }
4281
4282 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4283 {
4284         r8168b_0_hw_jumbo_disable(tp);
4285
4286         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4287 }
4288
4289 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4290 {
4291         struct jumbo_ops *ops = &tp->jumbo_ops;
4292
4293         switch (tp->mac_version) {
4294         case RTL_GIGA_MAC_VER_11:
4295                 ops->disable    = r8168b_0_hw_jumbo_disable;
4296                 ops->enable     = r8168b_0_hw_jumbo_enable;
4297                 break;
4298         case RTL_GIGA_MAC_VER_12:
4299         case RTL_GIGA_MAC_VER_17:
4300                 ops->disable    = r8168b_1_hw_jumbo_disable;
4301                 ops->enable     = r8168b_1_hw_jumbo_enable;
4302                 break;
4303         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4304         case RTL_GIGA_MAC_VER_19:
4305         case RTL_GIGA_MAC_VER_20:
4306         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4307         case RTL_GIGA_MAC_VER_22:
4308         case RTL_GIGA_MAC_VER_23:
4309         case RTL_GIGA_MAC_VER_24:
4310         case RTL_GIGA_MAC_VER_25:
4311         case RTL_GIGA_MAC_VER_26:
4312                 ops->disable    = r8168c_hw_jumbo_disable;
4313                 ops->enable     = r8168c_hw_jumbo_enable;
4314                 break;
4315         case RTL_GIGA_MAC_VER_27:
4316         case RTL_GIGA_MAC_VER_28:
4317                 ops->disable    = r8168dp_hw_jumbo_disable;
4318                 ops->enable     = r8168dp_hw_jumbo_enable;
4319                 break;
4320         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4321         case RTL_GIGA_MAC_VER_32:
4322         case RTL_GIGA_MAC_VER_33:
4323         case RTL_GIGA_MAC_VER_34:
4324                 ops->disable    = r8168e_hw_jumbo_disable;
4325                 ops->enable     = r8168e_hw_jumbo_enable;
4326                 break;
4327
4328         /*
4329          * No action needed for jumbo frames with 8169.
4330          * No jumbo for 810x at all.
4331          */
4332         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4333         default:
4334                 ops->disable    = NULL;
4335                 ops->enable     = NULL;
4336                 break;
4337         }
4338 }
4339
4340 DECLARE_RTL_COND(rtl_chipcmd_cond)
4341 {
4342         return RTL_R8(tp, ChipCmd) & CmdReset;
4343 }
4344
4345 static void rtl_hw_reset(struct rtl8169_private *tp)
4346 {
4347         RTL_W8(tp, ChipCmd, CmdReset);
4348
4349         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4350 }
4351
4352 static void rtl_request_firmware(struct rtl8169_private *tp)
4353 {
4354         struct rtl_fw *rtl_fw;
4355         int rc = -ENOMEM;
4356
4357         /* firmware loaded already or no firmware available */
4358         if (tp->rtl_fw || !tp->fw_name)
4359                 return;
4360
4361         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4362         if (!rtl_fw)
4363                 goto err_warn;
4364
4365         rtl_fw->phy_write = rtl_writephy;
4366         rtl_fw->phy_read = rtl_readphy;
4367         rtl_fw->mac_mcu_write = mac_mcu_write;
4368         rtl_fw->mac_mcu_read = mac_mcu_read;
4369
4370         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4371         if (rc < 0)
4372                 goto err_free;
4373
4374         rc = rtl_check_firmware(tp, rtl_fw);
4375         if (rc < 0)
4376                 goto err_release_firmware;
4377
4378         tp->rtl_fw = rtl_fw;
4379
4380         return;
4381
4382 err_release_firmware:
4383         release_firmware(rtl_fw->fw);
4384 err_free:
4385         kfree(rtl_fw);
4386 err_warn:
4387         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4388                    tp->fw_name, rc);
4389 }
4390
4391 static void rtl_rx_close(struct rtl8169_private *tp)
4392 {
4393         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4394 }
4395
4396 DECLARE_RTL_COND(rtl_npq_cond)
4397 {
4398         return RTL_R8(tp, TxPoll) & NPQ;
4399 }
4400
4401 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4402 {
4403         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4404 }
4405
4406 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4407 {
4408         /* Disable interrupts */
4409         rtl8169_irq_mask_and_ack(tp);
4410
4411         rtl_rx_close(tp);
4412
4413         switch (tp->mac_version) {
4414         case RTL_GIGA_MAC_VER_27:
4415         case RTL_GIGA_MAC_VER_28:
4416         case RTL_GIGA_MAC_VER_31:
4417                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4418                 break;
4419         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4420         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4421                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4422                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4423                 break;
4424         default:
4425                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4426                 udelay(100);
4427                 break;
4428         }
4429
4430         rtl_hw_reset(tp);
4431 }
4432
4433 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4434 {
4435         u32 val = TX_DMA_BURST << TxDMAShift |
4436                   InterFrameGap << TxInterFrameGapShift;
4437
4438         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4439             tp->mac_version != RTL_GIGA_MAC_VER_39)
4440                 val |= TXCFG_AUTO_FIFO;
4441
4442         RTL_W32(tp, TxConfig, val);
4443 }
4444
4445 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4446 {
4447         /* Low hurts. Let's disable the filtering. */
4448         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4449 }
4450
4451 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4452 {
4453         /*
4454          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4455          * register to be written before TxDescAddrLow to work.
4456          * Switching from MMIO to I/O access fixes the issue as well.
4457          */
4458         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4459         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4460         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4461         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4462 }
4463
4464 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4465 {
4466         u32 val;
4467
4468         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4469                 val = 0x000fff00;
4470         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4471                 val = 0x00ffff00;
4472         else
4473                 return;
4474
4475         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4476                 val |= 0xff;
4477
4478         RTL_W32(tp, 0x7c, val);
4479 }
4480
4481 static void rtl_set_rx_mode(struct net_device *dev)
4482 {
4483         struct rtl8169_private *tp = netdev_priv(dev);
4484         u32 mc_filter[2];       /* Multicast hash filter */
4485         int rx_mode;
4486         u32 tmp = 0;
4487
4488         if (dev->flags & IFF_PROMISC) {
4489                 /* Unconditionally log net taps. */
4490                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4491                 rx_mode =
4492                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4493                     AcceptAllPhys;
4494                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4495         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4496                    (dev->flags & IFF_ALLMULTI)) {
4497                 /* Too many to filter perfectly -- accept all multicasts. */
4498                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4499                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4500         } else {
4501                 struct netdev_hw_addr *ha;
4502
4503                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4504                 mc_filter[1] = mc_filter[0] = 0;
4505                 netdev_for_each_mc_addr(ha, dev) {
4506                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4507                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4508                         rx_mode |= AcceptMulticast;
4509                 }
4510         }
4511
4512         if (dev->features & NETIF_F_RXALL)
4513                 rx_mode |= (AcceptErr | AcceptRunt);
4514
4515         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4516
4517         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4518                 u32 data = mc_filter[0];
4519
4520                 mc_filter[0] = swab32(mc_filter[1]);
4521                 mc_filter[1] = swab32(data);
4522         }
4523
4524         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4525                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4526
4527         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4528         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4529
4530         RTL_W32(tp, RxConfig, tmp);
4531 }
4532
4533 static void rtl_hw_start(struct  rtl8169_private *tp)
4534 {
4535         rtl_unlock_config_regs(tp);
4536
4537         tp->hw_start(tp);
4538
4539         rtl_set_rx_max_size(tp);
4540         rtl_set_rx_tx_desc_registers(tp);
4541         rtl_lock_config_regs(tp);
4542
4543         /* disable interrupt coalescing */
4544         RTL_W16(tp, IntrMitigate, 0x0000);
4545         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4546         RTL_R8(tp, IntrMask);
4547         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4548         rtl_init_rxcfg(tp);
4549         rtl_set_tx_config_registers(tp);
4550
4551         rtl_set_rx_mode(tp->dev);
4552         /* no early-rx interrupts */
4553         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4554         rtl_irq_enable(tp);
4555 }
4556
4557 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4558 {
4559         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4560                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4561
4562         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4563
4564         tp->cp_cmd |= PCIMulRW;
4565
4566         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4567             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4568                 netif_dbg(tp, drv, tp->dev,
4569                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4570                 tp->cp_cmd |= (1 << 14);
4571         }
4572
4573         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4574
4575         rtl8169_set_magic_reg(tp, tp->mac_version);
4576
4577         RTL_W32(tp, RxMissed, 0);
4578 }
4579
4580 DECLARE_RTL_COND(rtl_csiar_cond)
4581 {
4582         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4583 }
4584
4585 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4586 {
4587         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4588
4589         RTL_W32(tp, CSIDR, value);
4590         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4591                 CSIAR_BYTE_ENABLE | func << 16);
4592
4593         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4594 }
4595
4596 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4597 {
4598         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4599
4600         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4601                 CSIAR_BYTE_ENABLE);
4602
4603         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4604                 RTL_R32(tp, CSIDR) : ~0;
4605 }
4606
4607 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4608 {
4609         struct pci_dev *pdev = tp->pci_dev;
4610         u32 csi;
4611
4612         /* According to Realtek the value at config space address 0x070f
4613          * controls the L0s/L1 entrance latency. We try standard ECAM access
4614          * first and if it fails fall back to CSI.
4615          */
4616         if (pdev->cfg_size > 0x070f &&
4617             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4618                 return;
4619
4620         netdev_notice_once(tp->dev,
4621                 "No native access to PCI extended config space, falling back to CSI\n");
4622         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4623         rtl_csi_write(tp, 0x070c, csi | val << 24);
4624 }
4625
4626 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4627 {
4628         rtl_csi_access_enable(tp, 0x27);
4629 }
4630
4631 struct ephy_info {
4632         unsigned int offset;
4633         u16 mask;
4634         u16 bits;
4635 };
4636
4637 static void __rtl_ephy_init(struct rtl8169_private *tp,
4638                             const struct ephy_info *e, int len)
4639 {
4640         u16 w;
4641
4642         while (len-- > 0) {
4643                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4644                 rtl_ephy_write(tp, e->offset, w);
4645                 e++;
4646         }
4647 }
4648
4649 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4650
4651 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4652 {
4653         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4654                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4655 }
4656
4657 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4658 {
4659         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4660                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4661 }
4662
4663 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4664 {
4665         /* work around an issue when PCI reset occurs during L2/L3 state */
4666         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4667 }
4668
4669 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4670 {
4671         if (enable) {
4672                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4673                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4674         } else {
4675                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4676                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4677         }
4678
4679         udelay(10);
4680 }
4681
4682 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4683                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4684 {
4685         /* Usage of dynamic vs. static FIFO is controlled by bit
4686          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4687          */
4688         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4689         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4690 }
4691
4692 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4693                                           u8 low, u8 high)
4694 {
4695         /* FIFO thresholds for pause flow control */
4696         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4697         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4698 }
4699
4700 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4701 {
4702         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4703
4704         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4705         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4706
4707         if (tp->dev->mtu <= ETH_DATA_LEN) {
4708                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4709                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4710         }
4711 }
4712
4713 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4714 {
4715         rtl_hw_start_8168bb(tp);
4716
4717         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4718
4719         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4720 }
4721
4722 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4723 {
4724         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4725
4726         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4727
4728         if (tp->dev->mtu <= ETH_DATA_LEN)
4729                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4730
4731         rtl_disable_clock_request(tp);
4732
4733         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4734         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4735 }
4736
4737 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4738 {
4739         static const struct ephy_info e_info_8168cp[] = {
4740                 { 0x01, 0,      0x0001 },
4741                 { 0x02, 0x0800, 0x1000 },
4742                 { 0x03, 0,      0x0042 },
4743                 { 0x06, 0x0080, 0x0000 },
4744                 { 0x07, 0,      0x2000 }
4745         };
4746
4747         rtl_set_def_aspm_entry_latency(tp);
4748
4749         rtl_ephy_init(tp, e_info_8168cp);
4750
4751         __rtl_hw_start_8168cp(tp);
4752 }
4753
4754 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4755 {
4756         rtl_set_def_aspm_entry_latency(tp);
4757
4758         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4759
4760         if (tp->dev->mtu <= ETH_DATA_LEN)
4761                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4762
4763         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4764         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4765 }
4766
4767 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4768 {
4769         rtl_set_def_aspm_entry_latency(tp);
4770
4771         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4772
4773         /* Magic. */
4774         RTL_W8(tp, DBG_REG, 0x20);
4775
4776         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4777
4778         if (tp->dev->mtu <= ETH_DATA_LEN)
4779                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4780
4781         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4782         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4783 }
4784
4785 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4786 {
4787         static const struct ephy_info e_info_8168c_1[] = {
4788                 { 0x02, 0x0800, 0x1000 },
4789                 { 0x03, 0,      0x0002 },
4790                 { 0x06, 0x0080, 0x0000 }
4791         };
4792
4793         rtl_set_def_aspm_entry_latency(tp);
4794
4795         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4796
4797         rtl_ephy_init(tp, e_info_8168c_1);
4798
4799         __rtl_hw_start_8168cp(tp);
4800 }
4801
4802 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4803 {
4804         static const struct ephy_info e_info_8168c_2[] = {
4805                 { 0x01, 0,      0x0001 },
4806                 { 0x03, 0x0400, 0x0220 }
4807         };
4808
4809         rtl_set_def_aspm_entry_latency(tp);
4810
4811         rtl_ephy_init(tp, e_info_8168c_2);
4812
4813         __rtl_hw_start_8168cp(tp);
4814 }
4815
4816 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4817 {
4818         rtl_hw_start_8168c_2(tp);
4819 }
4820
4821 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4822 {
4823         rtl_set_def_aspm_entry_latency(tp);
4824
4825         __rtl_hw_start_8168cp(tp);
4826 }
4827
4828 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4829 {
4830         rtl_set_def_aspm_entry_latency(tp);
4831
4832         rtl_disable_clock_request(tp);
4833
4834         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4835
4836         if (tp->dev->mtu <= ETH_DATA_LEN)
4837                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4838
4839         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4840         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4841 }
4842
4843 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4844 {
4845         rtl_set_def_aspm_entry_latency(tp);
4846
4847         if (tp->dev->mtu <= ETH_DATA_LEN)
4848                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4849
4850         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4851
4852         rtl_disable_clock_request(tp);
4853 }
4854
4855 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4856 {
4857         static const struct ephy_info e_info_8168d_4[] = {
4858                 { 0x0b, 0x0000, 0x0048 },
4859                 { 0x19, 0x0020, 0x0050 },
4860                 { 0x0c, 0x0100, 0x0020 }
4861         };
4862
4863         rtl_set_def_aspm_entry_latency(tp);
4864
4865         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4866
4867         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4868
4869         rtl_ephy_init(tp, e_info_8168d_4);
4870
4871         rtl_enable_clock_request(tp);
4872 }
4873
4874 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4875 {
4876         static const struct ephy_info e_info_8168e_1[] = {
4877                 { 0x00, 0x0200, 0x0100 },
4878                 { 0x00, 0x0000, 0x0004 },
4879                 { 0x06, 0x0002, 0x0001 },
4880                 { 0x06, 0x0000, 0x0030 },
4881                 { 0x07, 0x0000, 0x2000 },
4882                 { 0x00, 0x0000, 0x0020 },
4883                 { 0x03, 0x5800, 0x2000 },
4884                 { 0x03, 0x0000, 0x0001 },
4885                 { 0x01, 0x0800, 0x1000 },
4886                 { 0x07, 0x0000, 0x4000 },
4887                 { 0x1e, 0x0000, 0x2000 },
4888                 { 0x19, 0xffff, 0xfe6c },
4889                 { 0x0a, 0x0000, 0x0040 }
4890         };
4891
4892         rtl_set_def_aspm_entry_latency(tp);
4893
4894         rtl_ephy_init(tp, e_info_8168e_1);
4895
4896         if (tp->dev->mtu <= ETH_DATA_LEN)
4897                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4898
4899         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4900
4901         rtl_disable_clock_request(tp);
4902
4903         /* Reset tx FIFO pointer */
4904         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4905         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4906
4907         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4908 }
4909
4910 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4911 {
4912         static const struct ephy_info e_info_8168e_2[] = {
4913                 { 0x09, 0x0000, 0x0080 },
4914                 { 0x19, 0x0000, 0x0224 }
4915         };
4916
4917         rtl_set_def_aspm_entry_latency(tp);
4918
4919         rtl_ephy_init(tp, e_info_8168e_2);
4920
4921         if (tp->dev->mtu <= ETH_DATA_LEN)
4922                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4923
4924         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4925         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4926         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4927         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4928         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4929         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4930         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4931
4932         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4933
4934         rtl_disable_clock_request(tp);
4935
4936         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4937
4938         rtl8168_config_eee_mac(tp);
4939
4940         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4941         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4942         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4943
4944         rtl_hw_aspm_clkreq_enable(tp, true);
4945 }
4946
4947 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4948 {
4949         rtl_set_def_aspm_entry_latency(tp);
4950
4951         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4952
4953         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4954         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4955         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4956         rtl_reset_packet_filter(tp);
4957         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4958         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4959         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4960         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4961
4962         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4963
4964         rtl_disable_clock_request(tp);
4965
4966         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4967         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4968         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4969         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4970
4971         rtl8168_config_eee_mac(tp);
4972 }
4973
4974 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4975 {
4976         static const struct ephy_info e_info_8168f_1[] = {
4977                 { 0x06, 0x00c0, 0x0020 },
4978                 { 0x08, 0x0001, 0x0002 },
4979                 { 0x09, 0x0000, 0x0080 },
4980                 { 0x19, 0x0000, 0x0224 }
4981         };
4982
4983         rtl_hw_start_8168f(tp);
4984
4985         rtl_ephy_init(tp, e_info_8168f_1);
4986
4987         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4988 }
4989
4990 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4991 {
4992         static const struct ephy_info e_info_8168f_1[] = {
4993                 { 0x06, 0x00c0, 0x0020 },
4994                 { 0x0f, 0xffff, 0x5200 },
4995                 { 0x1e, 0x0000, 0x4000 },
4996                 { 0x19, 0x0000, 0x0224 }
4997         };
4998
4999         rtl_hw_start_8168f(tp);
5000         rtl_pcie_state_l2l3_disable(tp);
5001
5002         rtl_ephy_init(tp, e_info_8168f_1);
5003
5004         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5005 }
5006
5007 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5008 {
5009         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5010         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5011
5012         rtl_set_def_aspm_entry_latency(tp);
5013
5014         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5015
5016         rtl_reset_packet_filter(tp);
5017         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5018
5019         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5020         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5021
5022         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5023         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5024
5025         rtl8168_config_eee_mac(tp);
5026
5027         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5028         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5029
5030         rtl_pcie_state_l2l3_disable(tp);
5031 }
5032
5033 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5034 {
5035         static const struct ephy_info e_info_8168g_1[] = {
5036                 { 0x00, 0x0000, 0x0008 },
5037                 { 0x0c, 0x37d0, 0x0820 },
5038                 { 0x1e, 0x0000, 0x0001 },
5039                 { 0x19, 0x8000, 0x0000 }
5040         };
5041
5042         rtl_hw_start_8168g(tp);
5043
5044         /* disable aspm and clock request before access ephy */
5045         rtl_hw_aspm_clkreq_enable(tp, false);
5046         rtl_ephy_init(tp, e_info_8168g_1);
5047         rtl_hw_aspm_clkreq_enable(tp, true);
5048 }
5049
5050 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5051 {
5052         static const struct ephy_info e_info_8168g_2[] = {
5053                 { 0x00, 0x0000, 0x0008 },
5054                 { 0x0c, 0x3df0, 0x0200 },
5055                 { 0x19, 0xffff, 0xfc00 },
5056                 { 0x1e, 0xffff, 0x20eb }
5057         };
5058
5059         rtl_hw_start_8168g(tp);
5060
5061         /* disable aspm and clock request before access ephy */
5062         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5063         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5064         rtl_ephy_init(tp, e_info_8168g_2);
5065 }
5066
5067 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5068 {
5069         static const struct ephy_info e_info_8411_2[] = {
5070                 { 0x00, 0x0000, 0x0008 },
5071                 { 0x0c, 0x3df0, 0x0200 },
5072                 { 0x0f, 0xffff, 0x5200 },
5073                 { 0x19, 0x0020, 0x0000 },
5074                 { 0x1e, 0x0000, 0x2000 }
5075         };
5076
5077         rtl_hw_start_8168g(tp);
5078
5079         /* disable aspm and clock request before access ephy */
5080         rtl_hw_aspm_clkreq_enable(tp, false);
5081         rtl_ephy_init(tp, e_info_8411_2);
5082         rtl_hw_aspm_clkreq_enable(tp, true);
5083 }
5084
5085 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5086 {
5087         int rg_saw_cnt;
5088         u32 data;
5089         static const struct ephy_info e_info_8168h_1[] = {
5090                 { 0x1e, 0x0800, 0x0001 },
5091                 { 0x1d, 0x0000, 0x0800 },
5092                 { 0x05, 0xffff, 0x2089 },
5093                 { 0x06, 0xffff, 0x5881 },
5094                 { 0x04, 0xffff, 0x154a },
5095                 { 0x01, 0xffff, 0x068b }
5096         };
5097
5098         /* disable aspm and clock request before access ephy */
5099         rtl_hw_aspm_clkreq_enable(tp, false);
5100         rtl_ephy_init(tp, e_info_8168h_1);
5101
5102         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5103         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5104
5105         rtl_set_def_aspm_entry_latency(tp);
5106
5107         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5108
5109         rtl_reset_packet_filter(tp);
5110
5111         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5112
5113         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5114
5115         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5116
5117         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5118         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5119
5120         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5121         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5122
5123         rtl8168_config_eee_mac(tp);
5124
5125         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5126         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5127
5128         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5129
5130         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5131
5132         rtl_pcie_state_l2l3_disable(tp);
5133
5134         rtl_writephy(tp, 0x1f, 0x0c42);
5135         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5136         rtl_writephy(tp, 0x1f, 0x0000);
5137         if (rg_saw_cnt > 0) {
5138                 u16 sw_cnt_1ms_ini;
5139
5140                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5141                 sw_cnt_1ms_ini &= 0x0fff;
5142                 data = r8168_mac_ocp_read(tp, 0xd412);
5143                 data &= ~0x0fff;
5144                 data |= sw_cnt_1ms_ini;
5145                 r8168_mac_ocp_write(tp, 0xd412, data);
5146         }
5147
5148         data = r8168_mac_ocp_read(tp, 0xe056);
5149         data &= ~0xf0;
5150         data |= 0x70;
5151         r8168_mac_ocp_write(tp, 0xe056, data);
5152
5153         data = r8168_mac_ocp_read(tp, 0xe052);
5154         data &= ~0x6000;
5155         data |= 0x8008;
5156         r8168_mac_ocp_write(tp, 0xe052, data);
5157
5158         data = r8168_mac_ocp_read(tp, 0xe0d6);
5159         data &= ~0x01ff;
5160         data |= 0x017f;
5161         r8168_mac_ocp_write(tp, 0xe0d6, data);
5162
5163         data = r8168_mac_ocp_read(tp, 0xd420);
5164         data &= ~0x0fff;
5165         data |= 0x047f;
5166         r8168_mac_ocp_write(tp, 0xd420, data);
5167
5168         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5169         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5170         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5171         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5172
5173         rtl_hw_aspm_clkreq_enable(tp, true);
5174 }
5175
5176 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5177 {
5178         rtl8168ep_stop_cmac(tp);
5179
5180         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5181         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5182
5183         rtl_set_def_aspm_entry_latency(tp);
5184
5185         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5186
5187         rtl_reset_packet_filter(tp);
5188
5189         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5190
5191         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5192
5193         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5194         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5195
5196         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5197         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5198
5199         rtl8168_config_eee_mac(tp);
5200
5201         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5202
5203         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5204
5205         rtl_pcie_state_l2l3_disable(tp);
5206 }
5207
5208 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5209 {
5210         static const struct ephy_info e_info_8168ep_1[] = {
5211                 { 0x00, 0xffff, 0x10ab },
5212                 { 0x06, 0xffff, 0xf030 },
5213                 { 0x08, 0xffff, 0x2006 },
5214                 { 0x0d, 0xffff, 0x1666 },
5215                 { 0x0c, 0x3ff0, 0x0000 }
5216         };
5217
5218         /* disable aspm and clock request before access ephy */
5219         rtl_hw_aspm_clkreq_enable(tp, false);
5220         rtl_ephy_init(tp, e_info_8168ep_1);
5221
5222         rtl_hw_start_8168ep(tp);
5223
5224         rtl_hw_aspm_clkreq_enable(tp, true);
5225 }
5226
5227 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5228 {
5229         static const struct ephy_info e_info_8168ep_2[] = {
5230                 { 0x00, 0xffff, 0x10a3 },
5231                 { 0x19, 0xffff, 0xfc00 },
5232                 { 0x1e, 0xffff, 0x20ea }
5233         };
5234
5235         /* disable aspm and clock request before access ephy */
5236         rtl_hw_aspm_clkreq_enable(tp, false);
5237         rtl_ephy_init(tp, e_info_8168ep_2);
5238
5239         rtl_hw_start_8168ep(tp);
5240
5241         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5242         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5243
5244         rtl_hw_aspm_clkreq_enable(tp, true);
5245 }
5246
5247 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5248 {
5249         u32 data;
5250         static const struct ephy_info e_info_8168ep_3[] = {
5251                 { 0x00, 0xffff, 0x10a3 },
5252                 { 0x19, 0xffff, 0x7c00 },
5253                 { 0x1e, 0xffff, 0x20eb },
5254                 { 0x0d, 0xffff, 0x1666 }
5255         };
5256
5257         /* disable aspm and clock request before access ephy */
5258         rtl_hw_aspm_clkreq_enable(tp, false);
5259         rtl_ephy_init(tp, e_info_8168ep_3);
5260
5261         rtl_hw_start_8168ep(tp);
5262
5263         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5264         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5265
5266         data = r8168_mac_ocp_read(tp, 0xd3e2);
5267         data &= 0xf000;
5268         data |= 0x0271;
5269         r8168_mac_ocp_write(tp, 0xd3e2, data);
5270
5271         data = r8168_mac_ocp_read(tp, 0xd3e4);
5272         data &= 0xff00;
5273         r8168_mac_ocp_write(tp, 0xd3e4, data);
5274
5275         data = r8168_mac_ocp_read(tp, 0xe860);
5276         data |= 0x0080;
5277         r8168_mac_ocp_write(tp, 0xe860, data);
5278
5279         rtl_hw_aspm_clkreq_enable(tp, true);
5280 }
5281
5282 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5283 {
5284         static const struct ephy_info e_info_8102e_1[] = {
5285                 { 0x01, 0, 0x6e65 },
5286                 { 0x02, 0, 0x091f },
5287                 { 0x03, 0, 0xc2f9 },
5288                 { 0x06, 0, 0xafb5 },
5289                 { 0x07, 0, 0x0e00 },
5290                 { 0x19, 0, 0xec80 },
5291                 { 0x01, 0, 0x2e65 },
5292                 { 0x01, 0, 0x6e65 }
5293         };
5294         u8 cfg1;
5295
5296         rtl_set_def_aspm_entry_latency(tp);
5297
5298         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5299
5300         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5301
5302         RTL_W8(tp, Config1,
5303                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5304         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5305
5306         cfg1 = RTL_R8(tp, Config1);
5307         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5308                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5309
5310         rtl_ephy_init(tp, e_info_8102e_1);
5311 }
5312
5313 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5314 {
5315         rtl_set_def_aspm_entry_latency(tp);
5316
5317         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5318
5319         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5320         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5321 }
5322
5323 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5324 {
5325         rtl_hw_start_8102e_2(tp);
5326
5327         rtl_ephy_write(tp, 0x03, 0xc2f9);
5328 }
5329
5330 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5331 {
5332         static const struct ephy_info e_info_8105e_1[] = {
5333                 { 0x07, 0, 0x4000 },
5334                 { 0x19, 0, 0x0200 },
5335                 { 0x19, 0, 0x0020 },
5336                 { 0x1e, 0, 0x2000 },
5337                 { 0x03, 0, 0x0001 },
5338                 { 0x19, 0, 0x0100 },
5339                 { 0x19, 0, 0x0004 },
5340                 { 0x0a, 0, 0x0020 }
5341         };
5342
5343         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5344         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5345
5346         /* Disable Early Tally Counter */
5347         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5348
5349         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5350         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5351
5352         rtl_ephy_init(tp, e_info_8105e_1);
5353
5354         rtl_pcie_state_l2l3_disable(tp);
5355 }
5356
5357 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5358 {
5359         rtl_hw_start_8105e_1(tp);
5360         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5361 }
5362
5363 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5364 {
5365         static const struct ephy_info e_info_8402[] = {
5366                 { 0x19, 0xffff, 0xff64 },
5367                 { 0x1e, 0, 0x4000 }
5368         };
5369
5370         rtl_set_def_aspm_entry_latency(tp);
5371
5372         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5373         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5374
5375         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5376
5377         rtl_ephy_init(tp, e_info_8402);
5378
5379         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5380
5381         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5382         rtl_reset_packet_filter(tp);
5383         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5384         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5385         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5386
5387         rtl_pcie_state_l2l3_disable(tp);
5388 }
5389
5390 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5391 {
5392         rtl_hw_aspm_clkreq_enable(tp, false);
5393
5394         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5395         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5396
5397         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5398         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5399         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5400
5401         rtl_pcie_state_l2l3_disable(tp);
5402         rtl_hw_aspm_clkreq_enable(tp, true);
5403 }
5404
5405 static void rtl_hw_config(struct rtl8169_private *tp)
5406 {
5407         static const rtl_generic_fct hw_configs[] = {
5408                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5409                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5410                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5411                 [RTL_GIGA_MAC_VER_10] = NULL,
5412                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5413                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5414                 [RTL_GIGA_MAC_VER_13] = NULL,
5415                 [RTL_GIGA_MAC_VER_14] = NULL,
5416                 [RTL_GIGA_MAC_VER_15] = NULL,
5417                 [RTL_GIGA_MAC_VER_16] = NULL,
5418                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5419                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5420                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5421                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5422                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5423                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5424                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5425                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5426                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5427                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5428                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5429                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5430                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5431                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5432                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5433                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5434                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5435                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5436                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5437                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5438                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5439                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5440                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5441                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5442                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5443                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5444                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5445                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5446                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5447                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5448                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5449                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5450                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5451                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5452                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5453         };
5454
5455         if (hw_configs[tp->mac_version])
5456                 hw_configs[tp->mac_version](tp);
5457 }
5458
5459 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5460 {
5461         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5462
5463         /* Workaround for RxFIFO overflow. */
5464         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5465                 tp->irq_mask |= RxFIFOOver;
5466                 tp->irq_mask &= ~RxOverflow;
5467         }
5468
5469         rtl_hw_config(tp);
5470 }
5471
5472 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5473 {
5474         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5475                 tp->irq_mask &= ~RxFIFOOver;
5476
5477         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5478             tp->mac_version == RTL_GIGA_MAC_VER_16)
5479                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5480                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5481
5482         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5483
5484         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5485         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5486
5487         rtl_hw_config(tp);
5488 }
5489
5490 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5491 {
5492         struct rtl8169_private *tp = netdev_priv(dev);
5493
5494         if (new_mtu > ETH_DATA_LEN)
5495                 rtl_hw_jumbo_enable(tp);
5496         else
5497                 rtl_hw_jumbo_disable(tp);
5498
5499         dev->mtu = new_mtu;
5500         netdev_update_features(dev);
5501
5502         return 0;
5503 }
5504
5505 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5506 {
5507         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5508         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5509 }
5510
5511 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5512                                      void **data_buff, struct RxDesc *desc)
5513 {
5514         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5515                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5516
5517         kfree(*data_buff);
5518         *data_buff = NULL;
5519         rtl8169_make_unusable_by_asic(desc);
5520 }
5521
5522 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5523 {
5524         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5525
5526         /* Force memory writes to complete before releasing descriptor */
5527         dma_wmb();
5528
5529         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5530 }
5531
5532 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5533                                              struct RxDesc *desc)
5534 {
5535         void *data;
5536         dma_addr_t mapping;
5537         struct device *d = tp_to_dev(tp);
5538         int node = dev_to_node(d);
5539
5540         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5541         if (!data)
5542                 return NULL;
5543
5544         /* Memory should be properly aligned, but better check. */
5545         if (!IS_ALIGNED((unsigned long)data, 8)) {
5546                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5547                 goto err_out;
5548         }
5549
5550         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5551         if (unlikely(dma_mapping_error(d, mapping))) {
5552                 if (net_ratelimit())
5553                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5554                 goto err_out;
5555         }
5556
5557         desc->addr = cpu_to_le64(mapping);
5558         rtl8169_mark_to_asic(desc);
5559         return data;
5560
5561 err_out:
5562         kfree(data);
5563         return NULL;
5564 }
5565
5566 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5567 {
5568         unsigned int i;
5569
5570         for (i = 0; i < NUM_RX_DESC; i++) {
5571                 if (tp->Rx_databuff[i]) {
5572                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5573                                             tp->RxDescArray + i);
5574                 }
5575         }
5576 }
5577
5578 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5579 {
5580         desc->opts1 |= cpu_to_le32(RingEnd);
5581 }
5582
5583 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5584 {
5585         unsigned int i;
5586
5587         for (i = 0; i < NUM_RX_DESC; i++) {
5588                 void *data;
5589
5590                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5591                 if (!data) {
5592                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5593                         goto err_out;
5594                 }
5595                 tp->Rx_databuff[i] = data;
5596         }
5597
5598         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5599         return 0;
5600
5601 err_out:
5602         rtl8169_rx_clear(tp);
5603         return -ENOMEM;
5604 }
5605
5606 static int rtl8169_init_ring(struct rtl8169_private *tp)
5607 {
5608         rtl8169_init_ring_indexes(tp);
5609
5610         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5611         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5612
5613         return rtl8169_rx_fill(tp);
5614 }
5615
5616 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5617                                  struct TxDesc *desc)
5618 {
5619         unsigned int len = tx_skb->len;
5620
5621         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5622
5623         desc->opts1 = 0x00;
5624         desc->opts2 = 0x00;
5625         desc->addr = 0x00;
5626         tx_skb->len = 0;
5627 }
5628
5629 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5630                                    unsigned int n)
5631 {
5632         unsigned int i;
5633
5634         for (i = 0; i < n; i++) {
5635                 unsigned int entry = (start + i) % NUM_TX_DESC;
5636                 struct ring_info *tx_skb = tp->tx_skb + entry;
5637                 unsigned int len = tx_skb->len;
5638
5639                 if (len) {
5640                         struct sk_buff *skb = tx_skb->skb;
5641
5642                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5643                                              tp->TxDescArray + entry);
5644                         if (skb) {
5645                                 dev_consume_skb_any(skb);
5646                                 tx_skb->skb = NULL;
5647                         }
5648                 }
5649         }
5650 }
5651
5652 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5653 {
5654         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5655         tp->cur_tx = tp->dirty_tx = 0;
5656         netdev_reset_queue(tp->dev);
5657 }
5658
5659 static void rtl_reset_work(struct rtl8169_private *tp)
5660 {
5661         struct net_device *dev = tp->dev;
5662         int i;
5663
5664         napi_disable(&tp->napi);
5665         netif_stop_queue(dev);
5666         synchronize_rcu();
5667
5668         rtl8169_hw_reset(tp);
5669
5670         for (i = 0; i < NUM_RX_DESC; i++)
5671                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5672
5673         rtl8169_tx_clear(tp);
5674         rtl8169_init_ring_indexes(tp);
5675
5676         napi_enable(&tp->napi);
5677         rtl_hw_start(tp);
5678         netif_wake_queue(dev);
5679 }
5680
5681 static void rtl8169_tx_timeout(struct net_device *dev)
5682 {
5683         struct rtl8169_private *tp = netdev_priv(dev);
5684
5685         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5686 }
5687
5688 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5689 {
5690         u32 status = opts0 | len;
5691
5692         if (entry == NUM_TX_DESC - 1)
5693                 status |= RingEnd;
5694
5695         return cpu_to_le32(status);
5696 }
5697
5698 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5699                               u32 *opts)
5700 {
5701         struct skb_shared_info *info = skb_shinfo(skb);
5702         unsigned int cur_frag, entry;
5703         struct TxDesc *uninitialized_var(txd);
5704         struct device *d = tp_to_dev(tp);
5705
5706         entry = tp->cur_tx;
5707         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5708                 const skb_frag_t *frag = info->frags + cur_frag;
5709                 dma_addr_t mapping;
5710                 u32 len;
5711                 void *addr;
5712
5713                 entry = (entry + 1) % NUM_TX_DESC;
5714
5715                 txd = tp->TxDescArray + entry;
5716                 len = skb_frag_size(frag);
5717                 addr = skb_frag_address(frag);
5718                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5719                 if (unlikely(dma_mapping_error(d, mapping))) {
5720                         if (net_ratelimit())
5721                                 netif_err(tp, drv, tp->dev,
5722                                           "Failed to map TX fragments DMA!\n");
5723                         goto err_out;
5724                 }
5725
5726                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5727                 txd->opts2 = cpu_to_le32(opts[1]);
5728                 txd->addr = cpu_to_le64(mapping);
5729
5730                 tp->tx_skb[entry].len = len;
5731         }
5732
5733         if (cur_frag) {
5734                 tp->tx_skb[entry].skb = skb;
5735                 txd->opts1 |= cpu_to_le32(LastFrag);
5736         }
5737
5738         return cur_frag;
5739
5740 err_out:
5741         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5742         return -EIO;
5743 }
5744
5745 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5746 {
5747         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5748 }
5749
5750 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5751                                       struct net_device *dev);
5752 /* r8169_csum_workaround()
5753  * The hw limites the value the transport offset. When the offset is out of the
5754  * range, calculate the checksum by sw.
5755  */
5756 static void r8169_csum_workaround(struct rtl8169_private *tp,
5757                                   struct sk_buff *skb)
5758 {
5759         if (skb_shinfo(skb)->gso_size) {
5760                 netdev_features_t features = tp->dev->features;
5761                 struct sk_buff *segs, *nskb;
5762
5763                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5764                 segs = skb_gso_segment(skb, features);
5765                 if (IS_ERR(segs) || !segs)
5766                         goto drop;
5767
5768                 do {
5769                         nskb = segs;
5770                         segs = segs->next;
5771                         nskb->next = NULL;
5772                         rtl8169_start_xmit(nskb, tp->dev);
5773                 } while (segs);
5774
5775                 dev_consume_skb_any(skb);
5776         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5777                 if (skb_checksum_help(skb) < 0)
5778                         goto drop;
5779
5780                 rtl8169_start_xmit(skb, tp->dev);
5781         } else {
5782                 struct net_device_stats *stats;
5783
5784 drop:
5785                 stats = &tp->dev->stats;
5786                 stats->tx_dropped++;
5787                 dev_kfree_skb_any(skb);
5788         }
5789 }
5790
5791 /* msdn_giant_send_check()
5792  * According to the document of microsoft, the TCP Pseudo Header excludes the
5793  * packet length for IPv6 TCP large packets.
5794  */
5795 static int msdn_giant_send_check(struct sk_buff *skb)
5796 {
5797         const struct ipv6hdr *ipv6h;
5798         struct tcphdr *th;
5799         int ret;
5800
5801         ret = skb_cow_head(skb, 0);
5802         if (ret)
5803                 return ret;
5804
5805         ipv6h = ipv6_hdr(skb);
5806         th = tcp_hdr(skb);
5807
5808         th->check = 0;
5809         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5810
5811         return ret;
5812 }
5813
5814 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5815                                 struct sk_buff *skb, u32 *opts)
5816 {
5817         u32 mss = skb_shinfo(skb)->gso_size;
5818
5819         if (mss) {
5820                 opts[0] |= TD_LSO;
5821                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5822         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5823                 const struct iphdr *ip = ip_hdr(skb);
5824
5825                 if (ip->protocol == IPPROTO_TCP)
5826                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5827                 else if (ip->protocol == IPPROTO_UDP)
5828                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5829                 else
5830                         WARN_ON_ONCE(1);
5831         }
5832
5833         return true;
5834 }
5835
5836 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5837                                 struct sk_buff *skb, u32 *opts)
5838 {
5839         u32 transport_offset = (u32)skb_transport_offset(skb);
5840         u32 mss = skb_shinfo(skb)->gso_size;
5841
5842         if (mss) {
5843                 if (transport_offset > GTTCPHO_MAX) {
5844                         netif_warn(tp, tx_err, tp->dev,
5845                                    "Invalid transport offset 0x%x for TSO\n",
5846                                    transport_offset);
5847                         return false;
5848                 }
5849
5850                 switch (vlan_get_protocol(skb)) {
5851                 case htons(ETH_P_IP):
5852                         opts[0] |= TD1_GTSENV4;
5853                         break;
5854
5855                 case htons(ETH_P_IPV6):
5856                         if (msdn_giant_send_check(skb))
5857                                 return false;
5858
5859                         opts[0] |= TD1_GTSENV6;
5860                         break;
5861
5862                 default:
5863                         WARN_ON_ONCE(1);
5864                         break;
5865                 }
5866
5867                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5868                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5869         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5870                 u8 ip_protocol;
5871
5872                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5873                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5874
5875                 if (transport_offset > TCPHO_MAX) {
5876                         netif_warn(tp, tx_err, tp->dev,
5877                                    "Invalid transport offset 0x%x\n",
5878                                    transport_offset);
5879                         return false;
5880                 }
5881
5882                 switch (vlan_get_protocol(skb)) {
5883                 case htons(ETH_P_IP):
5884                         opts[1] |= TD1_IPv4_CS;
5885                         ip_protocol = ip_hdr(skb)->protocol;
5886                         break;
5887
5888                 case htons(ETH_P_IPV6):
5889                         opts[1] |= TD1_IPv6_CS;
5890                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5891                         break;
5892
5893                 default:
5894                         ip_protocol = IPPROTO_RAW;
5895                         break;
5896                 }
5897
5898                 if (ip_protocol == IPPROTO_TCP)
5899                         opts[1] |= TD1_TCP_CS;
5900                 else if (ip_protocol == IPPROTO_UDP)
5901                         opts[1] |= TD1_UDP_CS;
5902                 else
5903                         WARN_ON_ONCE(1);
5904
5905                 opts[1] |= transport_offset << TCPHO_SHIFT;
5906         } else {
5907                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5908                         return !eth_skb_pad(skb);
5909         }
5910
5911         return true;
5912 }
5913
5914 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5915                                unsigned int nr_frags)
5916 {
5917         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5918
5919         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5920         return slots_avail > nr_frags;
5921 }
5922
5923 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5924                                       struct net_device *dev)
5925 {
5926         struct rtl8169_private *tp = netdev_priv(dev);
5927         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5928         struct TxDesc *txd = tp->TxDescArray + entry;
5929         struct device *d = tp_to_dev(tp);
5930         dma_addr_t mapping;
5931         u32 opts[2], len;
5932         int frags;
5933
5934         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5935                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5936                 goto err_stop_0;
5937         }
5938
5939         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5940                 goto err_stop_0;
5941
5942         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5943         opts[0] = DescOwn;
5944
5945         if (!tp->tso_csum(tp, skb, opts)) {
5946                 r8169_csum_workaround(tp, skb);
5947                 return NETDEV_TX_OK;
5948         }
5949
5950         len = skb_headlen(skb);
5951         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5952         if (unlikely(dma_mapping_error(d, mapping))) {
5953                 if (net_ratelimit())
5954                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5955                 goto err_dma_0;
5956         }
5957
5958         tp->tx_skb[entry].len = len;
5959         txd->addr = cpu_to_le64(mapping);
5960
5961         frags = rtl8169_xmit_frags(tp, skb, opts);
5962         if (frags < 0)
5963                 goto err_dma_1;
5964         else if (frags)
5965                 opts[0] |= FirstFrag;
5966         else {
5967                 opts[0] |= FirstFrag | LastFrag;
5968                 tp->tx_skb[entry].skb = skb;
5969         }
5970
5971         txd->opts2 = cpu_to_le32(opts[1]);
5972
5973         netdev_sent_queue(dev, skb->len);
5974
5975         skb_tx_timestamp(skb);
5976
5977         /* Force memory writes to complete before releasing descriptor */
5978         dma_wmb();
5979
5980         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5981
5982         /* Force all memory writes to complete before notifying device */
5983         wmb();
5984
5985         tp->cur_tx += frags + 1;
5986
5987         RTL_W8(tp, TxPoll, NPQ);
5988
5989         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5990                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5991                  * not miss a ring update when it notices a stopped queue.
5992                  */
5993                 smp_wmb();
5994                 netif_stop_queue(dev);
5995                 /* Sync with rtl_tx:
5996                  * - publish queue status and cur_tx ring index (write barrier)
5997                  * - refresh dirty_tx ring index (read barrier).
5998                  * May the current thread have a pessimistic view of the ring
5999                  * status and forget to wake up queue, a racing rtl_tx thread
6000                  * can't.
6001                  */
6002                 smp_mb();
6003                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6004                         netif_start_queue(dev);
6005         }
6006
6007         return NETDEV_TX_OK;
6008
6009 err_dma_1:
6010         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6011 err_dma_0:
6012         dev_kfree_skb_any(skb);
6013         dev->stats.tx_dropped++;
6014         return NETDEV_TX_OK;
6015
6016 err_stop_0:
6017         netif_stop_queue(dev);
6018         dev->stats.tx_dropped++;
6019         return NETDEV_TX_BUSY;
6020 }
6021
6022 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6023 {
6024         struct rtl8169_private *tp = netdev_priv(dev);
6025         struct pci_dev *pdev = tp->pci_dev;
6026         u16 pci_status, pci_cmd;
6027
6028         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6029         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6030
6031         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6032                   pci_cmd, pci_status);
6033
6034         /*
6035          * The recovery sequence below admits a very elaborated explanation:
6036          * - it seems to work;
6037          * - I did not see what else could be done;
6038          * - it makes iop3xx happy.
6039          *
6040          * Feel free to adjust to your needs.
6041          */
6042         if (pdev->broken_parity_status)
6043                 pci_cmd &= ~PCI_COMMAND_PARITY;
6044         else
6045                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6046
6047         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6048
6049         pci_write_config_word(pdev, PCI_STATUS,
6050                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6051                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6052                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6053
6054         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6055 }
6056
6057 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6058                    int budget)
6059 {
6060         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6061
6062         dirty_tx = tp->dirty_tx;
6063         smp_rmb();
6064         tx_left = tp->cur_tx - dirty_tx;
6065
6066         while (tx_left > 0) {
6067                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6068                 struct ring_info *tx_skb = tp->tx_skb + entry;
6069                 u32 status;
6070
6071                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6072                 if (status & DescOwn)
6073                         break;
6074
6075                 /* This barrier is needed to keep us from reading
6076                  * any other fields out of the Tx descriptor until
6077                  * we know the status of DescOwn
6078                  */
6079                 dma_rmb();
6080
6081                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6082                                      tp->TxDescArray + entry);
6083                 if (status & LastFrag) {
6084                         pkts_compl++;
6085                         bytes_compl += tx_skb->skb->len;
6086                         napi_consume_skb(tx_skb->skb, budget);
6087                         tx_skb->skb = NULL;
6088                 }
6089                 dirty_tx++;
6090                 tx_left--;
6091         }
6092
6093         if (tp->dirty_tx != dirty_tx) {
6094                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6095
6096                 u64_stats_update_begin(&tp->tx_stats.syncp);
6097                 tp->tx_stats.packets += pkts_compl;
6098                 tp->tx_stats.bytes += bytes_compl;
6099                 u64_stats_update_end(&tp->tx_stats.syncp);
6100
6101                 tp->dirty_tx = dirty_tx;
6102                 /* Sync with rtl8169_start_xmit:
6103                  * - publish dirty_tx ring index (write barrier)
6104                  * - refresh cur_tx ring index and queue status (read barrier)
6105                  * May the current thread miss the stopped queue condition,
6106                  * a racing xmit thread can only have a right view of the
6107                  * ring status.
6108                  */
6109                 smp_mb();
6110                 if (netif_queue_stopped(dev) &&
6111                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6112                         netif_wake_queue(dev);
6113                 }
6114                 /*
6115                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6116                  * too close. Let's kick an extra TxPoll request when a burst
6117                  * of start_xmit activity is detected (if it is not detected,
6118                  * it is slow enough). -- FR
6119                  */
6120                 if (tp->cur_tx != dirty_tx)
6121                         RTL_W8(tp, TxPoll, NPQ);
6122         }
6123 }
6124
6125 static inline int rtl8169_fragmented_frame(u32 status)
6126 {
6127         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6128 }
6129
6130 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6131 {
6132         u32 status = opts1 & RxProtoMask;
6133
6134         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6135             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6136                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6137         else
6138                 skb_checksum_none_assert(skb);
6139 }
6140
6141 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6142                                            struct rtl8169_private *tp,
6143                                            int pkt_size,
6144                                            dma_addr_t addr)
6145 {
6146         struct sk_buff *skb;
6147         struct device *d = tp_to_dev(tp);
6148
6149         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6150         prefetch(data);
6151         skb = napi_alloc_skb(&tp->napi, pkt_size);
6152         if (skb)
6153                 skb_copy_to_linear_data(skb, data, pkt_size);
6154         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6155
6156         return skb;
6157 }
6158
6159 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6160 {
6161         unsigned int cur_rx, rx_left;
6162         unsigned int count;
6163
6164         cur_rx = tp->cur_rx;
6165
6166         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6167                 unsigned int entry = cur_rx % NUM_RX_DESC;
6168                 struct RxDesc *desc = tp->RxDescArray + entry;
6169                 u32 status;
6170
6171                 status = le32_to_cpu(desc->opts1);
6172                 if (status & DescOwn)
6173                         break;
6174
6175                 /* This barrier is needed to keep us from reading
6176                  * any other fields out of the Rx descriptor until
6177                  * we know the status of DescOwn
6178                  */
6179                 dma_rmb();
6180
6181                 if (unlikely(status & RxRES)) {
6182                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6183                                    status);
6184                         dev->stats.rx_errors++;
6185                         if (status & (RxRWT | RxRUNT))
6186                                 dev->stats.rx_length_errors++;
6187                         if (status & RxCRC)
6188                                 dev->stats.rx_crc_errors++;
6189                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6190                             dev->features & NETIF_F_RXALL) {
6191                                 goto process_pkt;
6192                         }
6193                 } else {
6194                         struct sk_buff *skb;
6195                         dma_addr_t addr;
6196                         int pkt_size;
6197
6198 process_pkt:
6199                         addr = le64_to_cpu(desc->addr);
6200                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6201                                 pkt_size = (status & 0x00003fff) - 4;
6202                         else
6203                                 pkt_size = status & 0x00003fff;
6204
6205                         /*
6206                          * The driver does not support incoming fragmented
6207                          * frames. They are seen as a symptom of over-mtu
6208                          * sized frames.
6209                          */
6210                         if (unlikely(rtl8169_fragmented_frame(status))) {
6211                                 dev->stats.rx_dropped++;
6212                                 dev->stats.rx_length_errors++;
6213                                 goto release_descriptor;
6214                         }
6215
6216                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6217                                                   tp, pkt_size, addr);
6218                         if (!skb) {
6219                                 dev->stats.rx_dropped++;
6220                                 goto release_descriptor;
6221                         }
6222
6223                         rtl8169_rx_csum(skb, status);
6224                         skb_put(skb, pkt_size);
6225                         skb->protocol = eth_type_trans(skb, dev);
6226
6227                         rtl8169_rx_vlan_tag(desc, skb);
6228
6229                         if (skb->pkt_type == PACKET_MULTICAST)
6230                                 dev->stats.multicast++;
6231
6232                         napi_gro_receive(&tp->napi, skb);
6233
6234                         u64_stats_update_begin(&tp->rx_stats.syncp);
6235                         tp->rx_stats.packets++;
6236                         tp->rx_stats.bytes += pkt_size;
6237                         u64_stats_update_end(&tp->rx_stats.syncp);
6238                 }
6239 release_descriptor:
6240                 desc->opts2 = 0;
6241                 rtl8169_mark_to_asic(desc);
6242         }
6243
6244         count = cur_rx - tp->cur_rx;
6245         tp->cur_rx = cur_rx;
6246
6247         return count;
6248 }
6249
6250 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6251 {
6252         struct rtl8169_private *tp = dev_instance;
6253         u16 status = RTL_R16(tp, IntrStatus);
6254
6255         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6256                 return IRQ_NONE;
6257
6258         if (unlikely(status & SYSErr)) {
6259                 rtl8169_pcierr_interrupt(tp->dev);
6260                 goto out;
6261         }
6262
6263         if (status & LinkChg)
6264                 phy_mac_interrupt(tp->phydev);
6265
6266         if (unlikely(status & RxFIFOOver &&
6267             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6268                 netif_stop_queue(tp->dev);
6269                 /* XXX - Hack alert. See rtl_task(). */
6270                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6271         }
6272
6273         rtl_irq_disable(tp);
6274         napi_schedule_irqoff(&tp->napi);
6275 out:
6276         rtl_ack_events(tp, status);
6277
6278         return IRQ_HANDLED;
6279 }
6280
6281 static void rtl_task(struct work_struct *work)
6282 {
6283         static const struct {
6284                 int bitnr;
6285                 void (*action)(struct rtl8169_private *);
6286         } rtl_work[] = {
6287                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6288         };
6289         struct rtl8169_private *tp =
6290                 container_of(work, struct rtl8169_private, wk.work);
6291         struct net_device *dev = tp->dev;
6292         int i;
6293
6294         rtl_lock_work(tp);
6295
6296         if (!netif_running(dev) ||
6297             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6298                 goto out_unlock;
6299
6300         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6301                 bool pending;
6302
6303                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6304                 if (pending)
6305                         rtl_work[i].action(tp);
6306         }
6307
6308 out_unlock:
6309         rtl_unlock_work(tp);
6310 }
6311
6312 static int rtl8169_poll(struct napi_struct *napi, int budget)
6313 {
6314         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6315         struct net_device *dev = tp->dev;
6316         int work_done;
6317
6318         work_done = rtl_rx(dev, tp, (u32) budget);
6319
6320         rtl_tx(dev, tp, budget);
6321
6322         if (work_done < budget) {
6323                 napi_complete_done(napi, work_done);
6324                 rtl_irq_enable(tp);
6325         }
6326
6327         return work_done;
6328 }
6329
6330 static void rtl8169_rx_missed(struct net_device *dev)
6331 {
6332         struct rtl8169_private *tp = netdev_priv(dev);
6333
6334         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6335                 return;
6336
6337         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6338         RTL_W32(tp, RxMissed, 0);
6339 }
6340
6341 static void r8169_phylink_handler(struct net_device *ndev)
6342 {
6343         struct rtl8169_private *tp = netdev_priv(ndev);
6344
6345         if (netif_carrier_ok(ndev)) {
6346                 rtl_link_chg_patch(tp);
6347                 pm_request_resume(&tp->pci_dev->dev);
6348         } else {
6349                 pm_runtime_idle(&tp->pci_dev->dev);
6350         }
6351
6352         if (net_ratelimit())
6353                 phy_print_status(tp->phydev);
6354 }
6355
6356 static int r8169_phy_connect(struct rtl8169_private *tp)
6357 {
6358         struct phy_device *phydev = tp->phydev;
6359         phy_interface_t phy_mode;
6360         int ret;
6361
6362         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6363                    PHY_INTERFACE_MODE_MII;
6364
6365         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6366                                  phy_mode);
6367         if (ret)
6368                 return ret;
6369
6370         if (tp->supports_gmii)
6371                 phy_remove_link_mode(phydev,
6372                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6373         else
6374                 phy_set_max_speed(phydev, SPEED_100);
6375
6376         phy_support_asym_pause(phydev);
6377
6378         phy_attached_info(phydev);
6379
6380         return 0;
6381 }
6382
6383 static void rtl8169_down(struct net_device *dev)
6384 {
6385         struct rtl8169_private *tp = netdev_priv(dev);
6386
6387         phy_stop(tp->phydev);
6388
6389         napi_disable(&tp->napi);
6390         netif_stop_queue(dev);
6391
6392         rtl8169_hw_reset(tp);
6393         /*
6394          * At this point device interrupts can not be enabled in any function,
6395          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6396          * and napi is disabled (rtl8169_poll).
6397          */
6398         rtl8169_rx_missed(dev);
6399
6400         /* Give a racing hard_start_xmit a few cycles to complete. */
6401         synchronize_rcu();
6402
6403         rtl8169_tx_clear(tp);
6404
6405         rtl8169_rx_clear(tp);
6406
6407         rtl_pll_power_down(tp);
6408 }
6409
6410 static int rtl8169_close(struct net_device *dev)
6411 {
6412         struct rtl8169_private *tp = netdev_priv(dev);
6413         struct pci_dev *pdev = tp->pci_dev;
6414
6415         pm_runtime_get_sync(&pdev->dev);
6416
6417         /* Update counters before going down */
6418         rtl8169_update_counters(tp);
6419
6420         rtl_lock_work(tp);
6421         /* Clear all task flags */
6422         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6423
6424         rtl8169_down(dev);
6425         rtl_unlock_work(tp);
6426
6427         cancel_work_sync(&tp->wk.work);
6428
6429         phy_disconnect(tp->phydev);
6430
6431         pci_free_irq(pdev, 0, tp);
6432
6433         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6434                           tp->RxPhyAddr);
6435         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6436                           tp->TxPhyAddr);
6437         tp->TxDescArray = NULL;
6438         tp->RxDescArray = NULL;
6439
6440         pm_runtime_put_sync(&pdev->dev);
6441
6442         return 0;
6443 }
6444
6445 #ifdef CONFIG_NET_POLL_CONTROLLER
6446 static void rtl8169_netpoll(struct net_device *dev)
6447 {
6448         struct rtl8169_private *tp = netdev_priv(dev);
6449
6450         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6451 }
6452 #endif
6453
6454 static int rtl_open(struct net_device *dev)
6455 {
6456         struct rtl8169_private *tp = netdev_priv(dev);
6457         struct pci_dev *pdev = tp->pci_dev;
6458         int retval = -ENOMEM;
6459
6460         pm_runtime_get_sync(&pdev->dev);
6461
6462         /*
6463          * Rx and Tx descriptors needs 256 bytes alignment.
6464          * dma_alloc_coherent provides more.
6465          */
6466         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6467                                              &tp->TxPhyAddr, GFP_KERNEL);
6468         if (!tp->TxDescArray)
6469                 goto err_pm_runtime_put;
6470
6471         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6472                                              &tp->RxPhyAddr, GFP_KERNEL);
6473         if (!tp->RxDescArray)
6474                 goto err_free_tx_0;
6475
6476         retval = rtl8169_init_ring(tp);
6477         if (retval < 0)
6478                 goto err_free_rx_1;
6479
6480         rtl_request_firmware(tp);
6481
6482         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6483                                  dev->name);
6484         if (retval < 0)
6485                 goto err_release_fw_2;
6486
6487         retval = r8169_phy_connect(tp);
6488         if (retval)
6489                 goto err_free_irq;
6490
6491         rtl_lock_work(tp);
6492
6493         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6494
6495         napi_enable(&tp->napi);
6496
6497         rtl8169_init_phy(dev, tp);
6498
6499         rtl_pll_power_up(tp);
6500
6501         rtl_hw_start(tp);
6502
6503         if (!rtl8169_init_counter_offsets(tp))
6504                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6505
6506         phy_start(tp->phydev);
6507         netif_start_queue(dev);
6508
6509         rtl_unlock_work(tp);
6510
6511         pm_runtime_put_sync(&pdev->dev);
6512 out:
6513         return retval;
6514
6515 err_free_irq:
6516         pci_free_irq(pdev, 0, tp);
6517 err_release_fw_2:
6518         rtl_release_firmware(tp);
6519         rtl8169_rx_clear(tp);
6520 err_free_rx_1:
6521         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6522                           tp->RxPhyAddr);
6523         tp->RxDescArray = NULL;
6524 err_free_tx_0:
6525         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6526                           tp->TxPhyAddr);
6527         tp->TxDescArray = NULL;
6528 err_pm_runtime_put:
6529         pm_runtime_put_noidle(&pdev->dev);
6530         goto out;
6531 }
6532
6533 static void
6534 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6535 {
6536         struct rtl8169_private *tp = netdev_priv(dev);
6537         struct pci_dev *pdev = tp->pci_dev;
6538         struct rtl8169_counters *counters = tp->counters;
6539         unsigned int start;
6540
6541         pm_runtime_get_noresume(&pdev->dev);
6542
6543         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6544                 rtl8169_rx_missed(dev);
6545
6546         do {
6547                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6548                 stats->rx_packets = tp->rx_stats.packets;
6549                 stats->rx_bytes = tp->rx_stats.bytes;
6550         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6551
6552         do {
6553                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6554                 stats->tx_packets = tp->tx_stats.packets;
6555                 stats->tx_bytes = tp->tx_stats.bytes;
6556         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6557
6558         stats->rx_dropped       = dev->stats.rx_dropped;
6559         stats->tx_dropped       = dev->stats.tx_dropped;
6560         stats->rx_length_errors = dev->stats.rx_length_errors;
6561         stats->rx_errors        = dev->stats.rx_errors;
6562         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6563         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6564         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6565         stats->multicast        = dev->stats.multicast;
6566
6567         /*
6568          * Fetch additonal counter values missing in stats collected by driver
6569          * from tally counters.
6570          */
6571         if (pm_runtime_active(&pdev->dev))
6572                 rtl8169_update_counters(tp);
6573
6574         /*
6575          * Subtract values fetched during initalization.
6576          * See rtl8169_init_counter_offsets for a description why we do that.
6577          */
6578         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6579                 le64_to_cpu(tp->tc_offset.tx_errors);
6580         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6581                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6582         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6583                 le16_to_cpu(tp->tc_offset.tx_aborted);
6584
6585         pm_runtime_put_noidle(&pdev->dev);
6586 }
6587
6588 static void rtl8169_net_suspend(struct net_device *dev)
6589 {
6590         struct rtl8169_private *tp = netdev_priv(dev);
6591
6592         if (!netif_running(dev))
6593                 return;
6594
6595         phy_stop(tp->phydev);
6596         netif_device_detach(dev);
6597
6598         rtl_lock_work(tp);
6599         napi_disable(&tp->napi);
6600         /* Clear all task flags */
6601         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6602
6603         rtl_unlock_work(tp);
6604
6605         rtl_pll_power_down(tp);
6606 }
6607
6608 #ifdef CONFIG_PM
6609
6610 static int rtl8169_suspend(struct device *device)
6611 {
6612         struct net_device *dev = dev_get_drvdata(device);
6613         struct rtl8169_private *tp = netdev_priv(dev);
6614
6615         rtl8169_net_suspend(dev);
6616         clk_disable_unprepare(tp->clk);
6617
6618         return 0;
6619 }
6620
6621 static void __rtl8169_resume(struct net_device *dev)
6622 {
6623         struct rtl8169_private *tp = netdev_priv(dev);
6624
6625         netif_device_attach(dev);
6626
6627         rtl_pll_power_up(tp);
6628         rtl8169_init_phy(dev, tp);
6629
6630         phy_start(tp->phydev);
6631
6632         rtl_lock_work(tp);
6633         napi_enable(&tp->napi);
6634         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6635         rtl_reset_work(tp);
6636         rtl_unlock_work(tp);
6637 }
6638
6639 static int rtl8169_resume(struct device *device)
6640 {
6641         struct net_device *dev = dev_get_drvdata(device);
6642         struct rtl8169_private *tp = netdev_priv(dev);
6643
6644         rtl_rar_set(tp, dev->dev_addr);
6645
6646         clk_prepare_enable(tp->clk);
6647
6648         if (netif_running(dev))
6649                 __rtl8169_resume(dev);
6650
6651         return 0;
6652 }
6653
6654 static int rtl8169_runtime_suspend(struct device *device)
6655 {
6656         struct net_device *dev = dev_get_drvdata(device);
6657         struct rtl8169_private *tp = netdev_priv(dev);
6658
6659         if (!tp->TxDescArray)
6660                 return 0;
6661
6662         rtl_lock_work(tp);
6663         __rtl8169_set_wol(tp, WAKE_ANY);
6664         rtl_unlock_work(tp);
6665
6666         rtl8169_net_suspend(dev);
6667
6668         /* Update counters before going runtime suspend */
6669         rtl8169_rx_missed(dev);
6670         rtl8169_update_counters(tp);
6671
6672         return 0;
6673 }
6674
6675 static int rtl8169_runtime_resume(struct device *device)
6676 {
6677         struct net_device *dev = dev_get_drvdata(device);
6678         struct rtl8169_private *tp = netdev_priv(dev);
6679
6680         rtl_rar_set(tp, dev->dev_addr);
6681
6682         if (!tp->TxDescArray)
6683                 return 0;
6684
6685         rtl_lock_work(tp);
6686         __rtl8169_set_wol(tp, tp->saved_wolopts);
6687         rtl_unlock_work(tp);
6688
6689         __rtl8169_resume(dev);
6690
6691         return 0;
6692 }
6693
6694 static int rtl8169_runtime_idle(struct device *device)
6695 {
6696         struct net_device *dev = dev_get_drvdata(device);
6697
6698         if (!netif_running(dev) || !netif_carrier_ok(dev))
6699                 pm_schedule_suspend(device, 10000);
6700
6701         return -EBUSY;
6702 }
6703
6704 static const struct dev_pm_ops rtl8169_pm_ops = {
6705         .suspend                = rtl8169_suspend,
6706         .resume                 = rtl8169_resume,
6707         .freeze                 = rtl8169_suspend,
6708         .thaw                   = rtl8169_resume,
6709         .poweroff               = rtl8169_suspend,
6710         .restore                = rtl8169_resume,
6711         .runtime_suspend        = rtl8169_runtime_suspend,
6712         .runtime_resume         = rtl8169_runtime_resume,
6713         .runtime_idle           = rtl8169_runtime_idle,
6714 };
6715
6716 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6717
6718 #else /* !CONFIG_PM */
6719
6720 #define RTL8169_PM_OPS  NULL
6721
6722 #endif /* !CONFIG_PM */
6723
6724 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6725 {
6726         /* WoL fails with 8168b when the receiver is disabled. */
6727         switch (tp->mac_version) {
6728         case RTL_GIGA_MAC_VER_11:
6729         case RTL_GIGA_MAC_VER_12:
6730         case RTL_GIGA_MAC_VER_17:
6731                 pci_clear_master(tp->pci_dev);
6732
6733                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6734                 /* PCI commit */
6735                 RTL_R8(tp, ChipCmd);
6736                 break;
6737         default:
6738                 break;
6739         }
6740 }
6741
6742 static void rtl_shutdown(struct pci_dev *pdev)
6743 {
6744         struct net_device *dev = pci_get_drvdata(pdev);
6745         struct rtl8169_private *tp = netdev_priv(dev);
6746
6747         rtl8169_net_suspend(dev);
6748
6749         /* Restore original MAC address */
6750         rtl_rar_set(tp, dev->perm_addr);
6751
6752         rtl8169_hw_reset(tp);
6753
6754         if (system_state == SYSTEM_POWER_OFF) {
6755                 if (tp->saved_wolopts) {
6756                         rtl_wol_suspend_quirk(tp);
6757                         rtl_wol_shutdown_quirk(tp);
6758                 }
6759
6760                 pci_wake_from_d3(pdev, true);
6761                 pci_set_power_state(pdev, PCI_D3hot);
6762         }
6763 }
6764
6765 static void rtl_remove_one(struct pci_dev *pdev)
6766 {
6767         struct net_device *dev = pci_get_drvdata(pdev);
6768         struct rtl8169_private *tp = netdev_priv(dev);
6769
6770         if (r8168_check_dash(tp))
6771                 rtl8168_driver_stop(tp);
6772
6773         netif_napi_del(&tp->napi);
6774
6775         unregister_netdev(dev);
6776         mdiobus_unregister(tp->phydev->mdio.bus);
6777
6778         rtl_release_firmware(tp);
6779
6780         if (pci_dev_run_wake(pdev))
6781                 pm_runtime_get_noresume(&pdev->dev);
6782
6783         /* restore original MAC address */
6784         rtl_rar_set(tp, dev->perm_addr);
6785 }
6786
6787 static const struct net_device_ops rtl_netdev_ops = {
6788         .ndo_open               = rtl_open,
6789         .ndo_stop               = rtl8169_close,
6790         .ndo_get_stats64        = rtl8169_get_stats64,
6791         .ndo_start_xmit         = rtl8169_start_xmit,
6792         .ndo_tx_timeout         = rtl8169_tx_timeout,
6793         .ndo_validate_addr      = eth_validate_addr,
6794         .ndo_change_mtu         = rtl8169_change_mtu,
6795         .ndo_fix_features       = rtl8169_fix_features,
6796         .ndo_set_features       = rtl8169_set_features,
6797         .ndo_set_mac_address    = rtl_set_mac_address,
6798         .ndo_do_ioctl           = rtl8169_ioctl,
6799         .ndo_set_rx_mode        = rtl_set_rx_mode,
6800 #ifdef CONFIG_NET_POLL_CONTROLLER
6801         .ndo_poll_controller    = rtl8169_netpoll,
6802 #endif
6803
6804 };
6805
6806 static const struct rtl_cfg_info {
6807         void (*hw_start)(struct rtl8169_private *tp);
6808         u16 irq_mask;
6809         unsigned int has_gmii:1;
6810         const struct rtl_coalesce_info *coalesce_info;
6811 } rtl_cfg_infos [] = {
6812         [RTL_CFG_0] = {
6813                 .hw_start       = rtl_hw_start_8169,
6814                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6815                 .has_gmii       = 1,
6816                 .coalesce_info  = rtl_coalesce_info_8169,
6817         },
6818         [RTL_CFG_1] = {
6819                 .hw_start       = rtl_hw_start_8168,
6820                 .irq_mask       = LinkChg | RxOverflow,
6821                 .has_gmii       = 1,
6822                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6823         },
6824         [RTL_CFG_2] = {
6825                 .hw_start       = rtl_hw_start_8101,
6826                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6827                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6828         }
6829 };
6830
6831 static int rtl_alloc_irq(struct rtl8169_private *tp)
6832 {
6833         unsigned int flags;
6834
6835         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6836                 rtl_unlock_config_regs(tp);
6837                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6838                 rtl_lock_config_regs(tp);
6839                 flags = PCI_IRQ_LEGACY;
6840         } else {
6841                 flags = PCI_IRQ_ALL_TYPES;
6842         }
6843
6844         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6845 }
6846
6847 static void rtl_read_mac_address(struct rtl8169_private *tp,
6848                                  u8 mac_addr[ETH_ALEN])
6849 {
6850         u32 value;
6851
6852         /* Get MAC address */
6853         switch (tp->mac_version) {
6854         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6855         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6856                 value = rtl_eri_read(tp, 0xe0);
6857                 mac_addr[0] = (value >>  0) & 0xff;
6858                 mac_addr[1] = (value >>  8) & 0xff;
6859                 mac_addr[2] = (value >> 16) & 0xff;
6860                 mac_addr[3] = (value >> 24) & 0xff;
6861
6862                 value = rtl_eri_read(tp, 0xe4);
6863                 mac_addr[4] = (value >>  0) & 0xff;
6864                 mac_addr[5] = (value >>  8) & 0xff;
6865                 break;
6866         default:
6867                 break;
6868         }
6869 }
6870
6871 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6872 {
6873         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6874 }
6875
6876 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6877 {
6878         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6879 }
6880
6881 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6882 {
6883         struct rtl8169_private *tp = mii_bus->priv;
6884
6885         if (phyaddr > 0)
6886                 return -ENODEV;
6887
6888         return rtl_readphy(tp, phyreg);
6889 }
6890
6891 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6892                                 int phyreg, u16 val)
6893 {
6894         struct rtl8169_private *tp = mii_bus->priv;
6895
6896         if (phyaddr > 0)
6897                 return -ENODEV;
6898
6899         rtl_writephy(tp, phyreg, val);
6900
6901         return 0;
6902 }
6903
6904 static int r8169_mdio_register(struct rtl8169_private *tp)
6905 {
6906         struct pci_dev *pdev = tp->pci_dev;
6907         struct mii_bus *new_bus;
6908         int ret;
6909
6910         new_bus = devm_mdiobus_alloc(&pdev->dev);
6911         if (!new_bus)
6912                 return -ENOMEM;
6913
6914         new_bus->name = "r8169";
6915         new_bus->priv = tp;
6916         new_bus->parent = &pdev->dev;
6917         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6918         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6919
6920         new_bus->read = r8169_mdio_read_reg;
6921         new_bus->write = r8169_mdio_write_reg;
6922
6923         ret = mdiobus_register(new_bus);
6924         if (ret)
6925                 return ret;
6926
6927         tp->phydev = mdiobus_get_phy(new_bus, 0);
6928         if (!tp->phydev) {
6929                 mdiobus_unregister(new_bus);
6930                 return -ENODEV;
6931         }
6932
6933         /* PHY will be woken up in rtl_open() */
6934         phy_suspend(tp->phydev);
6935
6936         return 0;
6937 }
6938
6939 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6940 {
6941         u32 data;
6942
6943         tp->ocp_base = OCP_STD_PHY_BASE;
6944
6945         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6946
6947         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6948                 return;
6949
6950         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6951                 return;
6952
6953         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6954         msleep(1);
6955         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6956
6957         data = r8168_mac_ocp_read(tp, 0xe8de);
6958         data &= ~(1 << 14);
6959         r8168_mac_ocp_write(tp, 0xe8de, data);
6960
6961         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6962                 return;
6963
6964         data = r8168_mac_ocp_read(tp, 0xe8de);
6965         data |= (1 << 15);
6966         r8168_mac_ocp_write(tp, 0xe8de, data);
6967
6968         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6969 }
6970
6971 static void rtl_hw_initialize(struct rtl8169_private *tp)
6972 {
6973         switch (tp->mac_version) {
6974         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6975                 rtl8168ep_stop_cmac(tp);
6976                 /* fall through */
6977         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6978                 rtl_hw_init_8168g(tp);
6979                 break;
6980         default:
6981                 break;
6982         }
6983 }
6984
6985 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
6986 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
6987 {
6988         switch (tp->mac_version) {
6989         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6990         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
6991                 return false;
6992         default:
6993                 return true;
6994         }
6995 }
6996
6997 static int rtl_jumbo_max(struct rtl8169_private *tp)
6998 {
6999         /* Non-GBit versions don't support jumbo frames */
7000         if (!tp->supports_gmii)
7001                 return JUMBO_1K;
7002
7003         switch (tp->mac_version) {
7004         /* RTL8169 */
7005         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7006                 return JUMBO_7K;
7007         /* RTL8168b */
7008         case RTL_GIGA_MAC_VER_11:
7009         case RTL_GIGA_MAC_VER_12:
7010         case RTL_GIGA_MAC_VER_17:
7011                 return JUMBO_4K;
7012         /* RTL8168c */
7013         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7014                 return JUMBO_6K;
7015         default:
7016                 return JUMBO_9K;
7017         }
7018 }
7019
7020 static void rtl_disable_clk(void *data)
7021 {
7022         clk_disable_unprepare(data);
7023 }
7024
7025 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7026 {
7027         struct device *d = tp_to_dev(tp);
7028         struct clk *clk;
7029         int rc;
7030
7031         clk = devm_clk_get(d, "ether_clk");
7032         if (IS_ERR(clk)) {
7033                 rc = PTR_ERR(clk);
7034                 if (rc == -ENOENT)
7035                         /* clk-core allows NULL (for suspend / resume) */
7036                         rc = 0;
7037                 else if (rc != -EPROBE_DEFER)
7038                         dev_err(d, "failed to get clk: %d\n", rc);
7039         } else {
7040                 tp->clk = clk;
7041                 rc = clk_prepare_enable(clk);
7042                 if (rc)
7043                         dev_err(d, "failed to enable clk: %d\n", rc);
7044                 else
7045                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7046         }
7047
7048         return rc;
7049 }
7050
7051 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7052 {
7053         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7054         /* align to u16 for is_valid_ether_addr() */
7055         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7056         struct rtl8169_private *tp;
7057         struct net_device *dev;
7058         int chipset, region, i;
7059         int jumbo_max, rc;
7060
7061         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7062         if (!dev)
7063                 return -ENOMEM;
7064
7065         SET_NETDEV_DEV(dev, &pdev->dev);
7066         dev->netdev_ops = &rtl_netdev_ops;
7067         tp = netdev_priv(dev);
7068         tp->dev = dev;
7069         tp->pci_dev = pdev;
7070         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7071         tp->supports_gmii = cfg->has_gmii;
7072
7073         /* Get the *optional* external "ether_clk" used on some boards */
7074         rc = rtl_get_ether_clk(tp);
7075         if (rc)
7076                 return rc;
7077
7078         /* Disable ASPM completely as that cause random device stop working
7079          * problems as well as full system hangs for some PCIe devices users.
7080          */
7081         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7082
7083         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7084         rc = pcim_enable_device(pdev);
7085         if (rc < 0) {
7086                 dev_err(&pdev->dev, "enable failure\n");
7087                 return rc;
7088         }
7089
7090         if (pcim_set_mwi(pdev) < 0)
7091                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7092
7093         /* use first MMIO region */
7094         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7095         if (region < 0) {
7096                 dev_err(&pdev->dev, "no MMIO resource found\n");
7097                 return -ENODEV;
7098         }
7099
7100         /* check for weird/broken PCI region reporting */
7101         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7102                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7103                 return -ENODEV;
7104         }
7105
7106         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7107         if (rc < 0) {
7108                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7109                 return rc;
7110         }
7111
7112         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7113
7114         /* Identify chip attached to board */
7115         rtl8169_get_mac_version(tp);
7116         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7117                 return -ENODEV;
7118
7119         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7120
7121         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7122             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7123                 dev->features |= NETIF_F_HIGHDMA;
7124         } else {
7125                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7126                 if (rc < 0) {
7127                         dev_err(&pdev->dev, "DMA configuration failed\n");
7128                         return rc;
7129                 }
7130         }
7131
7132         rtl_init_rxcfg(tp);
7133
7134         rtl8169_irq_mask_and_ack(tp);
7135
7136         rtl_hw_initialize(tp);
7137
7138         rtl_hw_reset(tp);
7139
7140         pci_set_master(pdev);
7141
7142         rtl_init_mdio_ops(tp);
7143         rtl_init_jumbo_ops(tp);
7144
7145         chipset = tp->mac_version;
7146
7147         rc = rtl_alloc_irq(tp);
7148         if (rc < 0) {
7149                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7150                 return rc;
7151         }
7152
7153         mutex_init(&tp->wk.mutex);
7154         INIT_WORK(&tp->wk.work, rtl_task);
7155         u64_stats_init(&tp->rx_stats.syncp);
7156         u64_stats_init(&tp->tx_stats.syncp);
7157
7158         /* get MAC address */
7159         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7160         if (rc)
7161                 rtl_read_mac_address(tp, mac_addr);
7162
7163         if (is_valid_ether_addr(mac_addr))
7164                 rtl_rar_set(tp, mac_addr);
7165
7166         for (i = 0; i < ETH_ALEN; i++)
7167                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7168
7169         dev->ethtool_ops = &rtl8169_ethtool_ops;
7170
7171         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7172
7173         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7174          * properly for all devices */
7175         dev->features |= NETIF_F_RXCSUM |
7176                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7177
7178         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7179                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7180                 NETIF_F_HW_VLAN_CTAG_RX;
7181         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7182                 NETIF_F_HIGHDMA;
7183         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7184
7185         tp->cp_cmd |= RxChkSum | RxVlan;
7186
7187         /*
7188          * Pretend we are using VLANs; This bypasses a nasty bug where
7189          * Interrupts stop flowing on high load on 8110SCd controllers.
7190          */
7191         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7192                 /* Disallow toggling */
7193                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7194
7195         if (rtl_chip_supports_csum_v2(tp)) {
7196                 tp->tso_csum = rtl8169_tso_csum_v2;
7197                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7198         } else {
7199                 tp->tso_csum = rtl8169_tso_csum_v1;
7200         }
7201
7202         dev->hw_features |= NETIF_F_RXALL;
7203         dev->hw_features |= NETIF_F_RXFCS;
7204
7205         /* MTU range: 60 - hw-specific max */
7206         dev->min_mtu = ETH_ZLEN;
7207         jumbo_max = rtl_jumbo_max(tp);
7208         dev->max_mtu = jumbo_max;
7209
7210         tp->hw_start = cfg->hw_start;
7211         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7212         tp->coalesce_info = cfg->coalesce_info;
7213
7214         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7215
7216         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7217                                             &tp->counters_phys_addr,
7218                                             GFP_KERNEL);
7219         if (!tp->counters)
7220                 return -ENOMEM;
7221
7222         pci_set_drvdata(pdev, dev);
7223
7224         rc = r8169_mdio_register(tp);
7225         if (rc)
7226                 return rc;
7227
7228         /* chip gets powered up in rtl_open() */
7229         rtl_pll_power_down(tp);
7230
7231         rc = register_netdev(dev);
7232         if (rc)
7233                 goto err_mdio_unregister;
7234
7235         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7236                    rtl_chip_infos[chipset].name, dev->dev_addr,
7237                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7238                    pci_irq_vector(pdev, 0));
7239
7240         if (jumbo_max > JUMBO_1K)
7241                 netif_info(tp, probe, dev,
7242                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7243                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7244                            "ok" : "ko");
7245
7246         if (r8168_check_dash(tp))
7247                 rtl8168_driver_start(tp);
7248
7249         if (pci_dev_run_wake(pdev))
7250                 pm_runtime_put_sync(&pdev->dev);
7251
7252         return 0;
7253
7254 err_mdio_unregister:
7255         mdiobus_unregister(tp->phydev->mdio.bus);
7256         return rc;
7257 }
7258
7259 static struct pci_driver rtl8169_pci_driver = {
7260         .name           = MODULENAME,
7261         .id_table       = rtl8169_pci_tbl,
7262         .probe          = rtl_init_one,
7263         .remove         = rtl_remove_one,
7264         .shutdown       = rtl_shutdown,
7265         .driver.pm      = RTL8169_PM_OPS,
7266 };
7267
7268 module_pci_driver(rtl8169_pci_driver);