drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         void (*hw_start)(struct rtl8169_private *tp);
 659
 660         struct {
 661                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 662                 struct mutex mutex;
 663                 struct work_struct work;
 664         } wk;
 665
 666         unsigned irq_enabled:1;
 667         unsigned supports_gmii:1;
 668         dma_addr_t counters_phys_addr;
 669         struct rtl8169_counters *counters;
 670         struct rtl8169_tc_offsets tc_offset;
 671         u32 saved_wolopts;
 672
 673         const char *fw_name;
 674         struct rtl_fw {
 675                 rtl_fw_write_t phy_write;
 676                 rtl_fw_read_t phy_read;
 677                 rtl_fw_write_t mac_mcu_write;
 678                 rtl_fw_read_t mac_mcu_read;
 679                 const struct firmware *fw;
 680
 681 #define RTL_VER_SIZE            32
 682
 683                 char version[RTL_VER_SIZE];
 684
 685                 struct rtl_fw_phy_action {
 686                         __le32 *code;
 687                         size_t size;
 688                 } phy_action;
 689         } *rtl_fw;
 690
 691         u32 ocp_base;
 692 };
 693
 694 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 695
 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 698 module_param_named(debug, debug.msg_enable, int, 0);
 699 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 700 MODULE_SOFTDEP("pre: realtek");
 701 MODULE_LICENSE("GPL");
 702 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 703 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 704 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 707 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 708 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 710 MODULE_FIRMWARE(FIRMWARE_8402_1);
 711 MODULE_FIRMWARE(FIRMWARE_8411_1);
 712 MODULE_FIRMWARE(FIRMWARE_8411_2);
 713 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 716 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 717 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 719 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 721
 722 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 723 {
 724         return &tp->pci_dev->dev;
 725 }
 726
 727 static void rtl_lock_work(struct rtl8169_private *tp)
 728 {
 729         mutex_lock(&tp->wk.mutex);
 730 }
 731
 732 static void rtl_unlock_work(struct rtl8169_private *tp)
 733 {
 734         mutex_unlock(&tp->wk.mutex);
 735 }
 736
 737 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 738 {
 739         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 740 }
 741
 742 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 743 {
 744         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 745 }
 746
 747 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 748 {
 749         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 750                                            PCI_EXP_DEVCTL_READRQ, force);
 751 }
 752
 753 struct rtl_cond {
 754         bool (*check)(struct rtl8169_private *);
 755         const char *msg;
 756 };
 757
 758 static void rtl_udelay(unsigned int d)
 759 {
 760         udelay(d);
 761 }
 762
 763 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 764                           void (*delay)(unsigned int), unsigned int d, int n,
 765                           bool high)
 766 {
 767         int i;
 768
 769         for (i = 0; i < n; i++) {
 770                 if (c->check(tp) == high)
 771                         return true;
 772                 delay(d);
 773         }
 774         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 775                   c->msg, !high, n, d);
 776         return false;
 777 }
 778
 779 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 780                                       const struct rtl_cond *c,
 781                                       unsigned int d, int n)
 782 {
 783         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 784 }
 785
 786 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 787                                      const struct rtl_cond *c,
 788                                      unsigned int d, int n)
 789 {
 790         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 791 }
 792
 793 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 794                                       const struct rtl_cond *c,
 795                                       unsigned int d, int n)
 796 {
 797         return rtl_loop_wait(tp, c, msleep, d, n, true);
 798 }
 799
 800 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 801                                      const struct rtl_cond *c,
 802                                      unsigned int d, int n)
 803 {
 804         return rtl_loop_wait(tp, c, msleep, d, n, false);
 805 }
 806
 807 #define DECLARE_RTL_COND(name)                          \
 808 static bool name ## _check(struct rtl8169_private *);   \
 809                                                         \
 810 static const struct rtl_cond name = {                   \
 811         .check  = name ## _check,                       \
 812         .msg    = #name                                 \
 813 };                                                      \
 814                                                         \
 815 static bool name ## _check(struct rtl8169_private *tp)
 816
 817 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 818 {
 819         if (reg & 0xffff0001) {
 820                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 821                 return true;
 822         }
 823         return false;
 824 }
 825
 826 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 827 {
 828         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 829 }
 830
 831 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 832 {
 833         if (rtl_ocp_reg_failure(tp, reg))
 834                 return;
 835
 836         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 837
 838         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 839 }
 840
 841 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 842 {
 843         if (rtl_ocp_reg_failure(tp, reg))
 844                 return 0;
 845
 846         RTL_W32(tp, GPHY_OCP, reg << 15);
 847
 848         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 849                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 850 }
 851
 852 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 853 {
 854         if (rtl_ocp_reg_failure(tp, reg))
 855                 return;
 856
 857         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 858 }
 859
 860 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return 0;
 864
 865         RTL_W32(tp, OCPDR, reg << 15);
 866
 867         return RTL_R32(tp, OCPDR);
 868 }
 869
 870 #define OCP_STD_PHY_BASE        0xa400
 871
 872 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 873 {
 874         if (reg == 0x1f) {
 875                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 876                 return;
 877         }
 878
 879         if (tp->ocp_base != OCP_STD_PHY_BASE)
 880                 reg -= 0x10;
 881
 882         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 883 }
 884
 885 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 886 {
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 891 }
 892
 893 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 894 {
 895         if (reg == 0x1f) {
 896                 tp->ocp_base = value << 4;
 897                 return;
 898         }
 899
 900         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 901 }
 902
 903 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 904 {
 905         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 906 }
 907
 908 DECLARE_RTL_COND(rtl_phyar_cond)
 909 {
 910         return RTL_R32(tp, PHYAR) & 0x80000000;
 911 }
 912
 913 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 914 {
 915         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 916
 917         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 918         /*
 919          * According to hardware specs a 20us delay is required after write
 920          * complete indication, but before sending next command.
 921          */
 922         udelay(20);
 923 }
 924
 925 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 926 {
 927         int value;
 928
 929         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 930
 931         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 932                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 933
 934         /*
 935          * According to hardware specs a 20us delay is required after read
 936          * complete indication, but before sending next command.
 937          */
 938         udelay(20);
 939
 940         return value;
 941 }
 942
 943 DECLARE_RTL_COND(rtl_ocpar_cond)
 944 {
 945         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 946 }
 947
 948 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 949 {
 950         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 951         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 952         RTL_W32(tp, EPHY_RXER_NUM, 0);
 953
 954         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 955 }
 956
 957 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 958 {
 959         r8168dp_1_mdio_access(tp, reg,
 960                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 961 }
 962
 963 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 964 {
 965         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 966
 967         mdelay(1);
 968         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 969         RTL_W32(tp, EPHY_RXER_NUM, 0);
 970
 971         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 972                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 973 }
 974
 975 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 976
 977 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 978 {
 979         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 980 }
 981
 982 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 983 {
 984         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 985 }
 986
 987 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 988 {
 989         r8168dp_2_mdio_start(tp);
 990
 991         r8169_mdio_write(tp, reg, value);
 992
 993         r8168dp_2_mdio_stop(tp);
 994 }
 995
 996 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 997 {
 998         int value;
 999
1000         r8168dp_2_mdio_start(tp);
1001
1002         value = r8169_mdio_read(tp, reg);
1003
1004         r8168dp_2_mdio_stop(tp);
1005
1006         return value;
1007 }
1008
1009 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1010 {
1011         switch (tp->mac_version) {
1012         case RTL_GIGA_MAC_VER_27:
1013                 r8168dp_1_mdio_write(tp, location, val);
1014                 break;
1015         case RTL_GIGA_MAC_VER_28:
1016         case RTL_GIGA_MAC_VER_31:
1017                 r8168dp_2_mdio_write(tp, location, val);
1018                 break;
1019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1020                 r8168g_mdio_write(tp, location, val);
1021                 break;
1022         default:
1023                 r8169_mdio_write(tp, location, val);
1024                 break;
1025         }
1026 }
1027
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 {
1030         switch (tp->mac_version) {
1031         case RTL_GIGA_MAC_VER_27:
1032                 return r8168dp_1_mdio_read(tp, location);
1033         case RTL_GIGA_MAC_VER_28:
1034         case RTL_GIGA_MAC_VER_31:
1035                 return r8168dp_2_mdio_read(tp, location);
1036         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1037                 return r8168g_mdio_read(tp, location);
1038         default:
1039                 return r8169_mdio_read(tp, location);
1040         }
1041 }
1042
1043 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1046 }
1047
1048 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1049 {
1050         int val;
1051
1052         val = rtl_readphy(tp, reg_addr);
1053         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1054 }
1055
1056 DECLARE_RTL_COND(rtl_ephyar_cond)
1057 {
1058         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1059 }
1060
1061 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1062 {
1063         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1064                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065
1066         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1067
1068         udelay(10);
1069 }
1070
1071 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1072 {
1073         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1074
1075         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1076                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1077 }
1078
1079 DECLARE_RTL_COND(rtl_eriar_cond)
1080 {
1081         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1082 }
1083
1084 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1085                            u32 val, int type)
1086 {
1087         BUG_ON((addr & 3) || (mask == 0));
1088         RTL_W32(tp, ERIDR, val);
1089         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1090
1091         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1092 }
1093
1094 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1095                           u32 val)
1096 {
1097         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1098 }
1099
1100 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1101 {
1102         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1103
1104         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1105                 RTL_R32(tp, ERIDR) : ~0;
1106 }
1107
1108 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1109 {
1110         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1111 }
1112
1113 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1114                          u32 m)
1115 {
1116         u32 val;
1117
1118         val = rtl_eri_read(tp, addr);
1119         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1120 }
1121
1122 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1123                              u32 p)
1124 {
1125         rtl_w0w1_eri(tp, addr, mask, p, 0);
1126 }
1127
1128 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1129                                u32 m)
1130 {
1131         rtl_w0w1_eri(tp, addr, mask, 0, m);
1132 }
1133
1134 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1135 {
1136         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1137         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1138                 RTL_R32(tp, OCPDR) : ~0;
1139 }
1140
1141 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1142 {
1143         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1144 }
1145
1146 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1147                               u32 data)
1148 {
1149         RTL_W32(tp, OCPDR, data);
1150         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1151         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1152 }
1153
1154 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1155                               u32 data)
1156 {
1157         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1158                        data, ERIAR_OOB);
1159 }
1160
1161 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1162 {
1163         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1164
1165         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1166 }
1167
1168 #define OOB_CMD_RESET           0x00
1169 #define OOB_CMD_DRIVER_START    0x05
1170 #define OOB_CMD_DRIVER_STOP     0x06
1171
1172 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1173 {
1174         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1175 }
1176
1177 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1178 {
1179         u16 reg;
1180
1181         reg = rtl8168_get_ocp_reg(tp);
1182
1183         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1187 {
1188         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1189 }
1190
1191 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1192 {
1193         return RTL_R8(tp, IBISR0) & 0x20;
1194 }
1195
1196 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1197 {
1198         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1199         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1200         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1201         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1202 }
1203
1204 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1205 {
1206         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1207         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1208 }
1209
1210 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1211 {
1212         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1213         r8168ep_ocp_write(tp, 0x01, 0x30,
1214                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1215         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1216 }
1217
1218 static void rtl8168_driver_start(struct rtl8169_private *tp)
1219 {
1220         switch (tp->mac_version) {
1221         case RTL_GIGA_MAC_VER_27:
1222         case RTL_GIGA_MAC_VER_28:
1223         case RTL_GIGA_MAC_VER_31:
1224                 rtl8168dp_driver_start(tp);
1225                 break;
1226         case RTL_GIGA_MAC_VER_49:
1227         case RTL_GIGA_MAC_VER_50:
1228         case RTL_GIGA_MAC_VER_51:
1229                 rtl8168ep_driver_start(tp);
1230                 break;
1231         default:
1232                 BUG();
1233                 break;
1234         }
1235 }
1236
1237 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1238 {
1239         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1240         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1241 }
1242
1243 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1244 {
1245         rtl8168ep_stop_cmac(tp);
1246         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1247         r8168ep_ocp_write(tp, 0x01, 0x30,
1248                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1249         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1250 }
1251
1252 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1253 {
1254         switch (tp->mac_version) {
1255         case RTL_GIGA_MAC_VER_27:
1256         case RTL_GIGA_MAC_VER_28:
1257         case RTL_GIGA_MAC_VER_31:
1258                 rtl8168dp_driver_stop(tp);
1259                 break;
1260         case RTL_GIGA_MAC_VER_49:
1261         case RTL_GIGA_MAC_VER_50:
1262         case RTL_GIGA_MAC_VER_51:
1263                 rtl8168ep_driver_stop(tp);
1264                 break;
1265         default:
1266                 BUG();
1267                 break;
1268         }
1269 }
1270
1271 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1272 {
1273         u16 reg = rtl8168_get_ocp_reg(tp);
1274
1275         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1276 }
1277
1278 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1279 {
1280         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1281 }
1282
1283 static bool r8168_check_dash(struct rtl8169_private *tp)
1284 {
1285         switch (tp->mac_version) {
1286         case RTL_GIGA_MAC_VER_27:
1287         case RTL_GIGA_MAC_VER_28:
1288         case RTL_GIGA_MAC_VER_31:
1289                 return r8168dp_check_dash(tp);
1290         case RTL_GIGA_MAC_VER_49:
1291         case RTL_GIGA_MAC_VER_50:
1292         case RTL_GIGA_MAC_VER_51:
1293                 return r8168ep_check_dash(tp);
1294         default:
1295                 return false;
1296         }
1297 }
1298
1299 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1300 {
1301         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1302         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1303 }
1304
1305 DECLARE_RTL_COND(rtl_efusear_cond)
1306 {
1307         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1308 }
1309
1310 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1311 {
1312         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1313
1314         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1315                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1316 }
1317
1318 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1319 {
1320         RTL_W16(tp, IntrStatus, bits);
1321 }
1322
1323 static void rtl_irq_disable(struct rtl8169_private *tp)
1324 {
1325         RTL_W16(tp, IntrMask, 0);
1326         tp->irq_enabled = 0;
1327 }
1328
1329 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1330 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1331 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1332
1333 static void rtl_irq_enable(struct rtl8169_private *tp)
1334 {
1335         tp->irq_enabled = 1;
1336         RTL_W16(tp, IntrMask, tp->irq_mask);
1337 }
1338
1339 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1340 {
1341         rtl_irq_disable(tp);
1342         rtl_ack_events(tp, 0xffff);
1343         /* PCI commit */
1344         RTL_R8(tp, ChipCmd);
1345 }
1346
1347 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1348 {
1349         struct net_device *dev = tp->dev;
1350         struct phy_device *phydev = tp->phydev;
1351
1352         if (!netif_running(dev))
1353                 return;
1354
1355         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1356             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1357                 if (phydev->speed == SPEED_1000) {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1360                 } else if (phydev->speed == SPEED_100) {
1361                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1362                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1363                 } else {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1366                 }
1367                 rtl_reset_packet_filter(tp);
1368         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1369                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1370                 if (phydev->speed == SPEED_1000) {
1371                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1373                 } else {
1374                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1375                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1376                 }
1377         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1378                 if (phydev->speed == SPEED_10) {
1379                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1380                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1381                 } else {
1382                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1383                 }
1384         }
1385 }
1386
1387 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394         wol->supported = WAKE_ANY;
1395         wol->wolopts = tp->saved_wolopts;
1396         rtl_unlock_work(tp);
1397 }
1398
1399 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1400 {
1401         unsigned int i, tmp;
1402         static const struct {
1403                 u32 opt;
1404                 u16 reg;
1405                 u8  mask;
1406         } cfg[] = {
1407                 { WAKE_PHY,   Config3, LinkUp },
1408                 { WAKE_UCAST, Config5, UWF },
1409                 { WAKE_BCAST, Config5, BWF },
1410                 { WAKE_MCAST, Config5, MWF },
1411                 { WAKE_ANY,   Config5, LanWake },
1412                 { WAKE_MAGIC, Config3, MagicPacket }
1413         };
1414         u8 options;
1415
1416         rtl_unlock_config_regs(tp);
1417
1418         switch (tp->mac_version) {
1419         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1420         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1421                 tmp = ARRAY_SIZE(cfg) - 1;
1422                 if (wolopts & WAKE_MAGIC)
1423                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1424                                          MagicPacket_v2);
1425                 else
1426                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1427                                            MagicPacket_v2);
1428                 break;
1429         default:
1430                 tmp = ARRAY_SIZE(cfg);
1431                 break;
1432         }
1433
1434         for (i = 0; i < tmp; i++) {
1435                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1436                 if (wolopts & cfg[i].opt)
1437                         options |= cfg[i].mask;
1438                 RTL_W8(tp, cfg[i].reg, options);
1439         }
1440
1441         switch (tp->mac_version) {
1442         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1443                 options = RTL_R8(tp, Config1) & ~PMEnable;
1444                 if (wolopts)
1445                         options |= PMEnable;
1446                 RTL_W8(tp, Config1, options);
1447                 break;
1448         default:
1449                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1450                 if (wolopts)
1451                         options |= PME_SIGNAL;
1452                 RTL_W8(tp, Config2, options);
1453                 break;
1454         }
1455
1456         rtl_lock_config_regs(tp);
1457
1458         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1459 }
1460
1461 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1462 {
1463         struct rtl8169_private *tp = netdev_priv(dev);
1464         struct device *d = tp_to_dev(tp);
1465
1466         if (wol->wolopts & ~WAKE_ANY)
1467                 return -EINVAL;
1468
1469         pm_runtime_get_noresume(d);
1470
1471         rtl_lock_work(tp);
1472
1473         tp->saved_wolopts = wol->wolopts;
1474
1475         if (pm_runtime_active(d))
1476                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1477
1478         rtl_unlock_work(tp);
1479
1480         pm_runtime_put_noidle(d);
1481
1482         return 0;
1483 }
1484
1485 static void rtl8169_get_drvinfo(struct net_device *dev,
1486                                 struct ethtool_drvinfo *info)
1487 {
1488         struct rtl8169_private *tp = netdev_priv(dev);
1489         struct rtl_fw *rtl_fw = tp->rtl_fw;
1490
1491         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1492         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1493         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1494         if (rtl_fw)
1495                 strlcpy(info->fw_version, rtl_fw->version,
1496                         sizeof(info->fw_version));
1497 }
1498
1499 static int rtl8169_get_regs_len(struct net_device *dev)
1500 {
1501         return R8169_REGS_SIZE;
1502 }
1503
1504 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1505         netdev_features_t features)
1506 {
1507         struct rtl8169_private *tp = netdev_priv(dev);
1508
1509         if (dev->mtu > TD_MSS_MAX)
1510                 features &= ~NETIF_F_ALL_TSO;
1511
1512         if (dev->mtu > JUMBO_1K &&
1513             tp->mac_version > RTL_GIGA_MAC_VER_06)
1514                 features &= ~NETIF_F_IP_CSUM;
1515
1516         return features;
1517 }
1518
1519 static int rtl8169_set_features(struct net_device *dev,
1520                                 netdev_features_t features)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         u32 rx_config;
1524
1525         rtl_lock_work(tp);
1526
1527         rx_config = RTL_R32(tp, RxConfig);
1528         if (features & NETIF_F_RXALL)
1529                 rx_config |= (AcceptErr | AcceptRunt);
1530         else
1531                 rx_config &= ~(AcceptErr | AcceptRunt);
1532
1533         RTL_W32(tp, RxConfig, rx_config);
1534
1535         if (features & NETIF_F_RXCSUM)
1536                 tp->cp_cmd |= RxChkSum;
1537         else
1538                 tp->cp_cmd &= ~RxChkSum;
1539
1540         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1541                 tp->cp_cmd |= RxVlan;
1542         else
1543                 tp->cp_cmd &= ~RxVlan;
1544
1545         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1546         RTL_R16(tp, CPlusCmd);
1547
1548         rtl_unlock_work(tp);
1549
1550         return 0;
1551 }
1552
1553 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1554 {
1555         return (skb_vlan_tag_present(skb)) ?
1556                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1557 }
1558
1559 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1560 {
1561         u32 opts2 = le32_to_cpu(desc->opts2);
1562
1563         if (opts2 & RxVlanTag)
1564                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1565 }
1566
1567 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1568                              void *p)
1569 {
1570         struct rtl8169_private *tp = netdev_priv(dev);
1571         u32 __iomem *data = tp->mmio_addr;
1572         u32 *dw = p;
1573         int i;
1574
1575         rtl_lock_work(tp);
1576         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1577                 memcpy_fromio(dw++, data++, 4);
1578         rtl_unlock_work(tp);
1579 }
1580
1581 static u32 rtl8169_get_msglevel(struct net_device *dev)
1582 {
1583         struct rtl8169_private *tp = netdev_priv(dev);
1584
1585         return tp->msg_enable;
1586 }
1587
1588 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591
1592         tp->msg_enable = value;
1593 }
1594
1595 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1596         "tx_packets",
1597         "rx_packets",
1598         "tx_errors",
1599         "rx_errors",
1600         "rx_missed",
1601         "align_errors",
1602         "tx_single_collisions",
1603         "tx_multi_collisions",
1604         "unicast",
1605         "broadcast",
1606         "multicast",
1607         "tx_aborted",
1608         "tx_underrun",
1609 };
1610
1611 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1612 {
1613         switch (sset) {
1614         case ETH_SS_STATS:
1615                 return ARRAY_SIZE(rtl8169_gstrings);
1616         default:
1617                 return -EOPNOTSUPP;
1618         }
1619 }
1620
1621 DECLARE_RTL_COND(rtl_counters_cond)
1622 {
1623         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1624 }
1625
1626 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1627 {
1628         dma_addr_t paddr = tp->counters_phys_addr;
1629         u32 cmd;
1630
1631         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1632         RTL_R32(tp, CounterAddrHigh);
1633         cmd = (u64)paddr & DMA_BIT_MASK(32);
1634         RTL_W32(tp, CounterAddrLow, cmd);
1635         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1636
1637         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1638 }
1639
1640 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1641 {
1642         /*
1643          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1644          * tally counters.
1645          */
1646         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1647                 return true;
1648
1649         return rtl8169_do_counters(tp, CounterReset);
1650 }
1651
1652 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1653 {
1654         u8 val = RTL_R8(tp, ChipCmd);
1655
1656         /*
1657          * Some chips are unable to dump tally counters when the receiver
1658          * is disabled. If 0xff chip may be in a PCI power-save state.
1659          */
1660         if (!(val & CmdRxEnb) || val == 0xff)
1661                 return true;
1662
1663         return rtl8169_do_counters(tp, CounterDump);
1664 }
1665
1666 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1667 {
1668         struct rtl8169_counters *counters = tp->counters;
1669         bool ret = false;
1670
1671         /*
1672          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1673          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1674          * reset by a power cycle, while the counter values collected by the
1675          * driver are reset at every driver unload/load cycle.
1676          *
1677          * To make sure the HW values returned by @get_stats64 match the SW
1678          * values, we collect the initial values at first open(*) and use them
1679          * as offsets to normalize the values returned by @get_stats64.
1680          *
1681          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1682          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1683          * set at open time by rtl_hw_start.
1684          */
1685
1686         if (tp->tc_offset.inited)
1687                 return true;
1688
1689         /* If both, reset and update fail, propagate to caller. */
1690         if (rtl8169_reset_counters(tp))
1691                 ret = true;
1692
1693         if (rtl8169_update_counters(tp))
1694                 ret = true;
1695
1696         tp->tc_offset.tx_errors = counters->tx_errors;
1697         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1698         tp->tc_offset.tx_aborted = counters->tx_aborted;
1699         tp->tc_offset.inited = true;
1700
1701         return ret;
1702 }
1703
1704 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1705                                       struct ethtool_stats *stats, u64 *data)
1706 {
1707         struct rtl8169_private *tp = netdev_priv(dev);
1708         struct device *d = tp_to_dev(tp);
1709         struct rtl8169_counters *counters = tp->counters;
1710
1711         ASSERT_RTNL();
1712
1713         pm_runtime_get_noresume(d);
1714
1715         if (pm_runtime_active(d))
1716                 rtl8169_update_counters(tp);
1717
1718         pm_runtime_put_noidle(d);
1719
1720         data[0] = le64_to_cpu(counters->tx_packets);
1721         data[1] = le64_to_cpu(counters->rx_packets);
1722         data[2] = le64_to_cpu(counters->tx_errors);
1723         data[3] = le32_to_cpu(counters->rx_errors);
1724         data[4] = le16_to_cpu(counters->rx_missed);
1725         data[5] = le16_to_cpu(counters->align_errors);
1726         data[6] = le32_to_cpu(counters->tx_one_collision);
1727         data[7] = le32_to_cpu(counters->tx_multi_collision);
1728         data[8] = le64_to_cpu(counters->rx_unicast);
1729         data[9] = le64_to_cpu(counters->rx_broadcast);
1730         data[10] = le32_to_cpu(counters->rx_multicast);
1731         data[11] = le16_to_cpu(counters->tx_aborted);
1732         data[12] = le16_to_cpu(counters->tx_underun);
1733 }
1734
1735 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1736 {
1737         switch(stringset) {
1738         case ETH_SS_STATS:
1739                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1740                 break;
1741         }
1742 }
1743
1744 /*
1745  * Interrupt coalescing
1746  *
1747  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1748  * >     8169, 8168 and 810x line of chipsets
1749  *
1750  * 8169, 8168, and 8136(810x) serial chipsets support it.
1751  *
1752  * > 2 - the Tx timer unit at gigabit speed
1753  *
1754  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1755  * (0xe0) bit 1 and bit 0.
1756  *
1757  * For 8169
1758  * bit[1:0] \ speed        1000M           100M            10M
1759  * 0 0                     320ns           2.56us          40.96us
1760  * 0 1                     2.56us          20.48us         327.7us
1761  * 1 0                     5.12us          40.96us         655.4us
1762  * 1 1                     10.24us         81.92us         1.31ms
1763  *
1764  * For the other
1765  * bit[1:0] \ speed        1000M           100M            10M
1766  * 0 0                     5us             2.56us          40.96us
1767  * 0 1                     40us            20.48us         327.7us
1768  * 1 0                     80us            40.96us         655.4us
1769  * 1 1                     160us           81.92us         1.31ms
1770  */
1771
1772 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1773 struct rtl_coalesce_scale {
1774         /* Rx / Tx */
1775         u32 nsecs[2];
1776 };
1777
1778 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1779 struct rtl_coalesce_info {
1780         u32 speed;
1781         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1782 };
1783
1784 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1785 #define rxtx_x1822(r, t) {              \
1786         {{(r),          (t)}},          \
1787         {{(r)*8,        (t)*8}},        \
1788         {{(r)*8*2,      (t)*8*2}},      \
1789         {{(r)*8*2*2,    (t)*8*2*2}},    \
1790 }
1791 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1792         /* speed        delays:     rx00   tx00 */
1793         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1794         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1795         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1796         { 0 },
1797 };
1798
1799 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1800         /* speed        delays:     rx00   tx00 */
1801         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1802         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1803         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1804         { 0 },
1805 };
1806 #undef rxtx_x1822
1807
1808 /* get rx/tx scale vector corresponding to current speed */
1809 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1810 {
1811         struct rtl8169_private *tp = netdev_priv(dev);
1812         struct ethtool_link_ksettings ecmd;
1813         const struct rtl_coalesce_info *ci;
1814         int rc;
1815
1816         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1817         if (rc < 0)
1818                 return ERR_PTR(rc);
1819
1820         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1821                 if (ecmd.base.speed == ci->speed) {
1822                         return ci;
1823                 }
1824         }
1825
1826         return ERR_PTR(-ELNRNG);
1827 }
1828
1829 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1830 {
1831         struct rtl8169_private *tp = netdev_priv(dev);
1832         const struct rtl_coalesce_info *ci;
1833         const struct rtl_coalesce_scale *scale;
1834         struct {
1835                 u32 *max_frames;
1836                 u32 *usecs;
1837         } coal_settings [] = {
1838                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1839                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1840         }, *p = coal_settings;
1841         int i;
1842         u16 w;
1843
1844         memset(ec, 0, sizeof(*ec));
1845
1846         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1847         ci = rtl_coalesce_info(dev);
1848         if (IS_ERR(ci))
1849                 return PTR_ERR(ci);
1850
1851         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1852
1853         /* read IntrMitigate and adjust according to scale */
1854         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1855                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1856                 w >>= RTL_COALESCE_SHIFT;
1857                 *p->usecs = w & RTL_COALESCE_MASK;
1858         }
1859
1860         for (i = 0; i < 2; i++) {
1861                 p = coal_settings + i;
1862                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1863
1864                 /*
1865                  * ethtool_coalesce says it is illegal to set both usecs and
1866                  * max_frames to 0.
1867                  */
1868                 if (!*p->usecs && !*p->max_frames)
1869                         *p->max_frames = 1;
1870         }
1871
1872         return 0;
1873 }
1874
1875 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1876 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1877                         struct net_device *dev, u32 nsec, u16 *cp01)
1878 {
1879         const struct rtl_coalesce_info *ci;
1880         u16 i;
1881
1882         ci = rtl_coalesce_info(dev);
1883         if (IS_ERR(ci))
1884                 return ERR_CAST(ci);
1885
1886         for (i = 0; i < 4; i++) {
1887                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1888                                         ci->scalev[i].nsecs[1]);
1889                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1890                         *cp01 = i;
1891                         return &ci->scalev[i];
1892                 }
1893         }
1894
1895         return ERR_PTR(-EINVAL);
1896 }
1897
1898 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         const struct rtl_coalesce_scale *scale;
1902         struct {
1903                 u32 frames;
1904                 u32 usecs;
1905         } coal_settings [] = {
1906                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1907                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1908         }, *p = coal_settings;
1909         u16 w = 0, cp01;
1910         int i;
1911
1912         scale = rtl_coalesce_choose_scale(dev,
1913                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1914         if (IS_ERR(scale))
1915                 return PTR_ERR(scale);
1916
1917         for (i = 0; i < 2; i++, p++) {
1918                 u32 units;
1919
1920                 /*
1921                  * accept max_frames=1 we returned in rtl_get_coalesce.
1922                  * accept it not only when usecs=0 because of e.g. the following scenario:
1923                  *
1924                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1925                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1926                  * - then user does `ethtool -C eth0 rx-usecs 100`
1927                  *
1928                  * since ethtool sends to kernel whole ethtool_coalesce
1929                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1930                  * we'll reject it below in `frames % 4 != 0`.
1931                  */
1932                 if (p->frames == 1) {
1933                         p->frames = 0;
1934                 }
1935
1936                 units = p->usecs * 1000 / scale->nsecs[i];
1937                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1938                         return -EINVAL;
1939
1940                 w <<= RTL_COALESCE_SHIFT;
1941                 w |= units;
1942                 w <<= RTL_COALESCE_SHIFT;
1943                 w |= p->frames >> 2;
1944         }
1945
1946         rtl_lock_work(tp);
1947
1948         RTL_W16(tp, IntrMitigate, swab16(w));
1949
1950         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1951         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1952         RTL_R16(tp, CPlusCmd);
1953
1954         rtl_unlock_work(tp);
1955
1956         return 0;
1957 }
1958
1959 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1960 {
1961         struct phy_device *phydev = tp->phydev;
1962         int ret;
1963
1964         switch (tp->mac_version) {
1965         case RTL_GIGA_MAC_VER_34:
1966         case RTL_GIGA_MAC_VER_35:
1967         case RTL_GIGA_MAC_VER_36:
1968         case RTL_GIGA_MAC_VER_38:
1969                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1970                 break;
1971         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1972                 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1973                 break;
1974         default:
1975                 ret = -EPROTONOSUPPORT;
1976                 break;
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1983 {
1984         struct phy_device *phydev = tp->phydev;
1985         int ret;
1986
1987         switch (tp->mac_version) {
1988         case RTL_GIGA_MAC_VER_34:
1989         case RTL_GIGA_MAC_VER_35:
1990         case RTL_GIGA_MAC_VER_36:
1991         case RTL_GIGA_MAC_VER_38:
1992                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1993                 break;
1994         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1995                 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1996                 break;
1997         default:
1998                 ret = -EPROTONOSUPPORT;
1999                 break;
2000         }
2001
2002         return ret;
2003 }
2004
2005 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2006 {
2007         struct phy_device *phydev = tp->phydev;
2008         int ret;
2009
2010         switch (tp->mac_version) {
2011         case RTL_GIGA_MAC_VER_34:
2012         case RTL_GIGA_MAC_VER_35:
2013         case RTL_GIGA_MAC_VER_36:
2014         case RTL_GIGA_MAC_VER_38:
2015                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2016                 break;
2017         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2018                 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
2019                 break;
2020         default:
2021                 ret = -EPROTONOSUPPORT;
2022                 break;
2023         }
2024
2025         return ret;
2026 }
2027
2028 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2029 {
2030         struct phy_device *phydev = tp->phydev;
2031         int ret = 0;
2032
2033         switch (tp->mac_version) {
2034         case RTL_GIGA_MAC_VER_34:
2035         case RTL_GIGA_MAC_VER_35:
2036         case RTL_GIGA_MAC_VER_36:
2037         case RTL_GIGA_MAC_VER_38:
2038                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2039                 break;
2040         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2041                 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2042                 break;
2043         default:
2044                 ret = -EPROTONOSUPPORT;
2045                 break;
2046         }
2047
2048         return ret;
2049 }
2050
2051 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2052 {
2053         struct rtl8169_private *tp = netdev_priv(dev);
2054         struct device *d = tp_to_dev(tp);
2055         int ret;
2056
2057         pm_runtime_get_noresume(d);
2058
2059         if (!pm_runtime_active(d)) {
2060                 ret = -EOPNOTSUPP;
2061                 goto out;
2062         }
2063
2064         /* Get Supported EEE */
2065         ret = rtl_get_eee_supp(tp);
2066         if (ret < 0)
2067                 goto out;
2068         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2069
2070         /* Get advertisement EEE */
2071         ret = rtl_get_eee_adv(tp);
2072         if (ret < 0)
2073                 goto out;
2074         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2075         data->eee_enabled = !!data->advertised;
2076
2077         /* Get LP advertisement EEE */
2078         ret = rtl_get_eee_lpadv(tp);
2079         if (ret < 0)
2080                 goto out;
2081         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2082         data->eee_active = !!(data->advertised & data->lp_advertised);
2083 out:
2084         pm_runtime_put_noidle(d);
2085         return ret < 0 ? ret : 0;
2086 }
2087
2088 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2089 {
2090         struct rtl8169_private *tp = netdev_priv(dev);
2091         struct device *d = tp_to_dev(tp);
2092         int old_adv, adv = 0, cap, ret;
2093
2094         pm_runtime_get_noresume(d);
2095
2096         if (!dev->phydev || !pm_runtime_active(d)) {
2097                 ret = -EOPNOTSUPP;
2098                 goto out;
2099         }
2100
2101         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2102             dev->phydev->duplex != DUPLEX_FULL) {
2103                 ret = -EPROTONOSUPPORT;
2104                 goto out;
2105         }
2106
2107         /* Get Supported EEE */
2108         ret = rtl_get_eee_supp(tp);
2109         if (ret < 0)
2110                 goto out;
2111         cap = ret;
2112
2113         ret = rtl_get_eee_adv(tp);
2114         if (ret < 0)
2115                 goto out;
2116         old_adv = ret;
2117
2118         if (data->eee_enabled) {
2119                 adv = !data->advertised ? cap :
2120                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2121                 /* Mask prohibited EEE modes */
2122                 adv &= ~dev->phydev->eee_broken_modes;
2123         }
2124
2125         if (old_adv != adv) {
2126                 ret = rtl_set_eee_adv(tp, adv);
2127                 if (ret < 0)
2128                         goto out;
2129
2130                 /* Restart autonegotiation so the new modes get sent to the
2131                  * link partner.
2132                  */
2133                 ret = phy_restart_aneg(dev->phydev);
2134         }
2135
2136 out:
2137         pm_runtime_put_noidle(d);
2138         return ret < 0 ? ret : 0;
2139 }
2140
2141 static const struct ethtool_ops rtl8169_ethtool_ops = {
2142         .get_drvinfo            = rtl8169_get_drvinfo,
2143         .get_regs_len           = rtl8169_get_regs_len,
2144         .get_link               = ethtool_op_get_link,
2145         .get_coalesce           = rtl_get_coalesce,
2146         .set_coalesce           = rtl_set_coalesce,
2147         .get_msglevel           = rtl8169_get_msglevel,
2148         .set_msglevel           = rtl8169_set_msglevel,
2149         .get_regs               = rtl8169_get_regs,
2150         .get_wol                = rtl8169_get_wol,
2151         .set_wol                = rtl8169_set_wol,
2152         .get_strings            = rtl8169_get_strings,
2153         .get_sset_count         = rtl8169_get_sset_count,
2154         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2155         .get_ts_info            = ethtool_op_get_ts_info,
2156         .nway_reset             = phy_ethtool_nway_reset,
2157         .get_eee                = rtl8169_get_eee,
2158         .set_eee                = rtl8169_set_eee,
2159         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2160         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2161 };
2162
2163 static void rtl_enable_eee(struct rtl8169_private *tp)
2164 {
2165         int supported = rtl_get_eee_supp(tp);
2166
2167         if (supported > 0)
2168                 rtl_set_eee_adv(tp, supported);
2169 }
2170
2171 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2172 {
2173         /*
2174          * The driver currently handles the 8168Bf and the 8168Be identically
2175          * but they can be identified more specifically through the test below
2176          * if needed:
2177          *
2178          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2179          *
2180          * Same thing for the 8101Eb and the 8101Ec:
2181          *
2182          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2183          */
2184         static const struct rtl_mac_info {
2185                 u16 mask;
2186                 u16 val;
2187                 u16 mac_version;
2188         } mac_info[] = {
2189                 /* 8168EP family. */
2190                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2191                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2192                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2193
2194                 /* 8168H family. */
2195                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2196                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2197
2198                 /* 8168G family. */
2199                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2200                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2201                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2202                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2203
2204                 /* 8168F family. */
2205                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2206                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2207                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2208
2209                 /* 8168E family. */
2210                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2211                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2212                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2213
2214                 /* 8168D family. */
2215                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2216                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2217
2218                 /* 8168DP family. */
2219                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2220                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2221                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2222
2223                 /* 8168C family. */
2224                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2225                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2226                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2227                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2228                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2229                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2230                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2231
2232                 /* 8168B family. */
2233                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2234                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2235                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2236
2237                 /* 8101 family. */
2238                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2239                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2240                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2241                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2242                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2243                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2244                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2245                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2246                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2247                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2248                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2249                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2250                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2251                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2252                 /* FIXME: where did these entries come from ? -- FR */
2253                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2254                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2255
2256                 /* 8110 family. */
2257                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2258                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2259                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2260                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2261                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2262
2263                 /* Catch-all */
2264                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2265         };
2266         const struct rtl_mac_info *p = mac_info;
2267         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2268
2269         while ((reg & p->mask) != p->val)
2270                 p++;
2271         tp->mac_version = p->mac_version;
2272
2273         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2274                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2275         } else if (!tp->supports_gmii) {
2276                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2277                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2278                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2279                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2280                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2281                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2282         }
2283 }
2284
2285 struct phy_reg {
2286         u16 reg;
2287         u16 val;
2288 };
2289
2290 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2291                                  const struct phy_reg *regs, int len)
2292 {
2293         while (len-- > 0) {
2294                 rtl_writephy(tp, regs->reg, regs->val);
2295                 regs++;
2296         }
2297 }
2298
2299 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2300
2301 enum rtl_fw_opcode {
2302         PHY_READ                = 0x0,
2303         PHY_DATA_OR             = 0x1,
2304         PHY_DATA_AND            = 0x2,
2305         PHY_BJMPN               = 0x3,
2306         PHY_MDIO_CHG            = 0x4,
2307         PHY_CLEAR_READCOUNT     = 0x7,
2308         PHY_WRITE               = 0x8,
2309         PHY_READCOUNT_EQ_SKIP   = 0x9,
2310         PHY_COMP_EQ_SKIPN       = 0xa,
2311         PHY_COMP_NEQ_SKIPN      = 0xb,
2312         PHY_WRITE_PREVIOUS      = 0xc,
2313         PHY_SKIPN               = 0xd,
2314         PHY_DELAY_MS            = 0xe,
2315 };
2316
2317 struct fw_info {
2318         u32     magic;
2319         char    version[RTL_VER_SIZE];
2320         __le32  fw_start;
2321         __le32  fw_len;
2322         u8      chksum;
2323 } __packed;
2324
2325 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2326
2327 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2328 {
2329         const struct firmware *fw = rtl_fw->fw;
2330         struct fw_info *fw_info = (struct fw_info *)fw->data;
2331         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2332
2333         if (fw->size < FW_OPCODE_SIZE)
2334                 return false;
2335
2336         if (!fw_info->magic) {
2337                 size_t i, size, start;
2338                 u8 checksum = 0;
2339
2340                 if (fw->size < sizeof(*fw_info))
2341                         return false;
2342
2343                 for (i = 0; i < fw->size; i++)
2344                         checksum += fw->data[i];
2345                 if (checksum != 0)
2346                         return false;
2347
2348                 start = le32_to_cpu(fw_info->fw_start);
2349                 if (start > fw->size)
2350                         return false;
2351
2352                 size = le32_to_cpu(fw_info->fw_len);
2353                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2354                         return false;
2355
2356                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2357
2358                 pa->code = (__le32 *)(fw->data + start);
2359                 pa->size = size;
2360         } else {
2361                 if (fw->size % FW_OPCODE_SIZE)
2362                         return false;
2363
2364                 strscpy(rtl_fw->version, tp->fw_name, RTL_VER_SIZE);
2365
2366                 pa->code = (__le32 *)fw->data;
2367                 pa->size = fw->size / FW_OPCODE_SIZE;
2368         }
2369
2370         return true;
2371 }
2372
2373 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2374                            struct rtl_fw_phy_action *pa)
2375 {
2376         bool rc = false;
2377         size_t index;
2378
2379         for (index = 0; index < pa->size; index++) {
2380                 u32 action = le32_to_cpu(pa->code[index]);
2381                 u32 regno = (action & 0x0fff0000) >> 16;
2382
2383                 switch (action >> 28) {
2384                 case PHY_READ:
2385                 case PHY_DATA_OR:
2386                 case PHY_DATA_AND:
2387                 case PHY_MDIO_CHG:
2388                 case PHY_CLEAR_READCOUNT:
2389                 case PHY_WRITE:
2390                 case PHY_WRITE_PREVIOUS:
2391                 case PHY_DELAY_MS:
2392                         break;
2393
2394                 case PHY_BJMPN:
2395                         if (regno > index) {
2396                                 netif_err(tp, ifup, tp->dev,
2397                                           "Out of range of firmware\n");
2398                                 goto out;
2399                         }
2400                         break;
2401                 case PHY_READCOUNT_EQ_SKIP:
2402                         if (index + 2 >= pa->size) {
2403                                 netif_err(tp, ifup, tp->dev,
2404                                           "Out of range of firmware\n");
2405                                 goto out;
2406                         }
2407                         break;
2408                 case PHY_COMP_EQ_SKIPN:
2409                 case PHY_COMP_NEQ_SKIPN:
2410                 case PHY_SKIPN:
2411                         if (index + 1 + regno >= pa->size) {
2412                                 netif_err(tp, ifup, tp->dev,
2413                                           "Out of range of firmware\n");
2414                                 goto out;
2415                         }
2416                         break;
2417
2418                 default:
2419                         netif_err(tp, ifup, tp->dev,
2420                                   "Invalid action 0x%08x\n", action);
2421                         goto out;
2422                 }
2423         }
2424         rc = true;
2425 out:
2426         return rc;
2427 }
2428
2429 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2430 {
2431         struct net_device *dev = tp->dev;
2432         int rc = -EINVAL;
2433
2434         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2435                 netif_err(tp, ifup, dev, "invalid firmware\n");
2436                 goto out;
2437         }
2438
2439         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2440                 rc = 0;
2441 out:
2442         return rc;
2443 }
2444
2445 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2446                                   struct rtl_fw *rtl_fw)
2447 {
2448         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2449         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2450         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2451         int predata = 0, count = 0;
2452         size_t index;
2453
2454         for (index = 0; index < pa->size; ) {
2455                 u32 action = le32_to_cpu(pa->code[index]);
2456                 u32 data = action & 0x0000ffff;
2457                 u32 regno = (action & 0x0fff0000) >> 16;
2458                 enum rtl_fw_opcode opcode = action >> 28;
2459
2460                 if (!action)
2461                         break;
2462
2463                 switch (opcode) {
2464                 case PHY_READ:
2465                         predata = fw_read(tp, regno);
2466                         count++;
2467                         index++;
2468                         break;
2469                 case PHY_DATA_OR:
2470                         predata |= data;
2471                         index++;
2472                         break;
2473                 case PHY_DATA_AND:
2474                         predata &= data;
2475                         index++;
2476                         break;
2477                 case PHY_BJMPN:
2478                         index -= regno;
2479                         break;
2480                 case PHY_MDIO_CHG:
2481                         if (data == 0) {
2482                                 fw_write = rtl_fw->phy_write;
2483                                 fw_read = rtl_fw->phy_read;
2484                         } else if (data == 1) {
2485                                 fw_write = rtl_fw->mac_mcu_write;
2486                                 fw_read = rtl_fw->mac_mcu_read;
2487                         }
2488
2489                         index++;
2490                         break;
2491                 case PHY_CLEAR_READCOUNT:
2492                         count = 0;
2493                         index++;
2494                         break;
2495                 case PHY_WRITE:
2496                         fw_write(tp, regno, data);
2497                         index++;
2498                         break;
2499                 case PHY_READCOUNT_EQ_SKIP:
2500                         index += (count == data) ? 2 : 1;
2501                         break;
2502                 case PHY_COMP_EQ_SKIPN:
2503                         if (predata == data)
2504                                 index += regno;
2505                         index++;
2506                         break;
2507                 case PHY_COMP_NEQ_SKIPN:
2508                         if (predata != data)
2509                                 index += regno;
2510                         index++;
2511                         break;
2512                 case PHY_WRITE_PREVIOUS:
2513                         fw_write(tp, regno, predata);
2514                         index++;
2515                         break;
2516                 case PHY_SKIPN:
2517                         index += regno + 1;
2518                         break;
2519                 case PHY_DELAY_MS:
2520                         mdelay(data);
2521                         index++;
2522                         break;
2523                 }
2524         }
2525 }
2526
2527 static void rtl_release_firmware(struct rtl8169_private *tp)
2528 {
2529         if (tp->rtl_fw) {
2530                 release_firmware(tp->rtl_fw->fw);
2531                 kfree(tp->rtl_fw);
2532                 tp->rtl_fw = NULL;
2533         }
2534 }
2535
2536 static void rtl_apply_firmware(struct rtl8169_private *tp)
2537 {
2538         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2539         if (tp->rtl_fw)
2540                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2541 }
2542
2543 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2544 {
2545         if (rtl_readphy(tp, reg) != val)
2546                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2547         else
2548                 rtl_apply_firmware(tp);
2549 }
2550
2551 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2552 {
2553         /* Adjust EEE LED frequency */
2554         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2555                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2556
2557         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2558 }
2559
2560 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2561 {
2562         struct phy_device *phydev = tp->phydev;
2563
2564         phy_write(phydev, 0x1f, 0x0007);
2565         phy_write(phydev, 0x1e, 0x0020);
2566         phy_set_bits(phydev, 0x15, BIT(8));
2567
2568         phy_write(phydev, 0x1f, 0x0005);
2569         phy_write(phydev, 0x05, 0x8b85);
2570         phy_set_bits(phydev, 0x06, BIT(13));
2571
2572         phy_write(phydev, 0x1f, 0x0000);
2573 }
2574
2575 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2576 {
2577         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2578 }
2579
2580 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2581 {
2582         static const struct phy_reg phy_reg_init[] = {
2583                 { 0x1f, 0x0001 },
2584                 { 0x06, 0x006e },
2585                 { 0x08, 0x0708 },
2586                 { 0x15, 0x4000 },
2587                 { 0x18, 0x65c7 },
2588
2589                 { 0x1f, 0x0001 },
2590                 { 0x03, 0x00a1 },
2591                 { 0x02, 0x0008 },
2592                 { 0x01, 0x0120 },
2593                 { 0x00, 0x1000 },
2594                 { 0x04, 0x0800 },
2595                 { 0x04, 0x0000 },
2596
2597                 { 0x03, 0xff41 },
2598                 { 0x02, 0xdf60 },
2599                 { 0x01, 0x0140 },
2600                 { 0x00, 0x0077 },
2601                 { 0x04, 0x7800 },
2602                 { 0x04, 0x7000 },
2603
2604                 { 0x03, 0x802f },
2605                 { 0x02, 0x4f02 },
2606                 { 0x01, 0x0409 },
2607                 { 0x00, 0xf0f9 },
2608                 { 0x04, 0x9800 },
2609                 { 0x04, 0x9000 },
2610
2611                 { 0x03, 0xdf01 },
2612                 { 0x02, 0xdf20 },
2613                 { 0x01, 0xff95 },
2614                 { 0x00, 0xba00 },
2615                 { 0x04, 0xa800 },
2616                 { 0x04, 0xa000 },
2617
2618                 { 0x03, 0xff41 },
2619                 { 0x02, 0xdf20 },
2620                 { 0x01, 0x0140 },
2621                 { 0x00, 0x00bb },
2622                 { 0x04, 0xb800 },
2623                 { 0x04, 0xb000 },
2624
2625                 { 0x03, 0xdf41 },
2626                 { 0x02, 0xdc60 },
2627                 { 0x01, 0x6340 },
2628                 { 0x00, 0x007d },
2629                 { 0x04, 0xd800 },
2630                 { 0x04, 0xd000 },
2631
2632                 { 0x03, 0xdf01 },
2633                 { 0x02, 0xdf20 },
2634                 { 0x01, 0x100a },
2635                 { 0x00, 0xa0ff },
2636                 { 0x04, 0xf800 },
2637                 { 0x04, 0xf000 },
2638
2639                 { 0x1f, 0x0000 },
2640                 { 0x0b, 0x0000 },
2641                 { 0x00, 0x9200 }
2642         };
2643
2644         rtl_writephy_batch(tp, phy_reg_init);
2645 }
2646
2647 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2648 {
2649         static const struct phy_reg phy_reg_init[] = {
2650                 { 0x1f, 0x0002 },
2651                 { 0x01, 0x90d0 },
2652                 { 0x1f, 0x0000 }
2653         };
2654
2655         rtl_writephy_batch(tp, phy_reg_init);
2656 }
2657
2658 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2659 {
2660         struct pci_dev *pdev = tp->pci_dev;
2661
2662         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2663             (pdev->subsystem_device != 0xe000))
2664                 return;
2665
2666         rtl_writephy(tp, 0x1f, 0x0001);
2667         rtl_writephy(tp, 0x10, 0xf01b);
2668         rtl_writephy(tp, 0x1f, 0x0000);
2669 }
2670
2671 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2672 {
2673         static const struct phy_reg phy_reg_init[] = {
2674                 { 0x1f, 0x0001 },
2675                 { 0x04, 0x0000 },
2676                 { 0x03, 0x00a1 },
2677                 { 0x02, 0x0008 },
2678                 { 0x01, 0x0120 },
2679                 { 0x00, 0x1000 },
2680                 { 0x04, 0x0800 },
2681                 { 0x04, 0x9000 },
2682                 { 0x03, 0x802f },
2683                 { 0x02, 0x4f02 },
2684                 { 0x01, 0x0409 },
2685                 { 0x00, 0xf099 },
2686                 { 0x04, 0x9800 },
2687                 { 0x04, 0xa000 },
2688                 { 0x03, 0xdf01 },
2689                 { 0x02, 0xdf20 },
2690                 { 0x01, 0xff95 },
2691                 { 0x00, 0xba00 },
2692                 { 0x04, 0xa800 },
2693                 { 0x04, 0xf000 },
2694                 { 0x03, 0xdf01 },
2695                 { 0x02, 0xdf20 },
2696                 { 0x01, 0x101a },
2697                 { 0x00, 0xa0ff },
2698                 { 0x04, 0xf800 },
2699                 { 0x04, 0x0000 },
2700                 { 0x1f, 0x0000 },
2701
2702                 { 0x1f, 0x0001 },
2703                 { 0x10, 0xf41b },
2704                 { 0x14, 0xfb54 },
2705                 { 0x18, 0xf5c7 },
2706                 { 0x1f, 0x0000 },
2707
2708                 { 0x1f, 0x0001 },
2709                 { 0x17, 0x0cc0 },
2710                 { 0x1f, 0x0000 }
2711         };
2712
2713         rtl_writephy_batch(tp, phy_reg_init);
2714
2715         rtl8169scd_hw_phy_config_quirk(tp);
2716 }
2717
2718 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init[] = {
2721                 { 0x1f, 0x0001 },
2722                 { 0x04, 0x0000 },
2723                 { 0x03, 0x00a1 },
2724                 { 0x02, 0x0008 },
2725                 { 0x01, 0x0120 },
2726                 { 0x00, 0x1000 },
2727                 { 0x04, 0x0800 },
2728                 { 0x04, 0x9000 },
2729                 { 0x03, 0x802f },
2730                 { 0x02, 0x4f02 },
2731                 { 0x01, 0x0409 },
2732                 { 0x00, 0xf099 },
2733                 { 0x04, 0x9800 },
2734                 { 0x04, 0xa000 },
2735                 { 0x03, 0xdf01 },
2736                 { 0x02, 0xdf20 },
2737                 { 0x01, 0xff95 },
2738                 { 0x00, 0xba00 },
2739                 { 0x04, 0xa800 },
2740                 { 0x04, 0xf000 },
2741                 { 0x03, 0xdf01 },
2742                 { 0x02, 0xdf20 },
2743                 { 0x01, 0x101a },
2744                 { 0x00, 0xa0ff },
2745                 { 0x04, 0xf800 },
2746                 { 0x04, 0x0000 },
2747                 { 0x1f, 0x0000 },
2748
2749                 { 0x1f, 0x0001 },
2750                 { 0x0b, 0x8480 },
2751                 { 0x1f, 0x0000 },
2752
2753                 { 0x1f, 0x0001 },
2754                 { 0x18, 0x67c7 },
2755                 { 0x04, 0x2000 },
2756                 { 0x03, 0x002f },
2757                 { 0x02, 0x4360 },
2758                 { 0x01, 0x0109 },
2759                 { 0x00, 0x3022 },
2760                 { 0x04, 0x2800 },
2761                 { 0x1f, 0x0000 },
2762
2763                 { 0x1f, 0x0001 },
2764                 { 0x17, 0x0cc0 },
2765                 { 0x1f, 0x0000 }
2766         };
2767
2768         rtl_writephy_batch(tp, phy_reg_init);
2769 }
2770
2771 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2772 {
2773         static const struct phy_reg phy_reg_init[] = {
2774                 { 0x10, 0xf41b },
2775                 { 0x1f, 0x0000 }
2776         };
2777
2778         rtl_writephy(tp, 0x1f, 0x0001);
2779         rtl_patchphy(tp, 0x16, 1 << 0);
2780
2781         rtl_writephy_batch(tp, phy_reg_init);
2782 }
2783
2784 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2785 {
2786         static const struct phy_reg phy_reg_init[] = {
2787                 { 0x1f, 0x0001 },
2788                 { 0x10, 0xf41b },
2789                 { 0x1f, 0x0000 }
2790         };
2791
2792         rtl_writephy_batch(tp, phy_reg_init);
2793 }
2794
2795 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2796 {
2797         static const struct phy_reg phy_reg_init[] = {
2798                 { 0x1f, 0x0000 },
2799                 { 0x1d, 0x0f00 },
2800                 { 0x1f, 0x0002 },
2801                 { 0x0c, 0x1ec8 },
2802                 { 0x1f, 0x0000 }
2803         };
2804
2805         rtl_writephy_batch(tp, phy_reg_init);
2806 }
2807
2808 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2809 {
2810         static const struct phy_reg phy_reg_init[] = {
2811                 { 0x1f, 0x0001 },
2812                 { 0x1d, 0x3d98 },
2813                 { 0x1f, 0x0000 }
2814         };
2815
2816         rtl_writephy(tp, 0x1f, 0x0000);
2817         rtl_patchphy(tp, 0x14, 1 << 5);
2818         rtl_patchphy(tp, 0x0d, 1 << 5);
2819
2820         rtl_writephy_batch(tp, phy_reg_init);
2821 }
2822
2823 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2824 {
2825         static const struct phy_reg phy_reg_init[] = {
2826                 { 0x1f, 0x0001 },
2827                 { 0x12, 0x2300 },
2828                 { 0x1f, 0x0002 },
2829                 { 0x00, 0x88d4 },
2830                 { 0x01, 0x82b1 },
2831                 { 0x03, 0x7002 },
2832                 { 0x08, 0x9e30 },
2833                 { 0x09, 0x01f0 },
2834                 { 0x0a, 0x5500 },
2835                 { 0x0c, 0x00c8 },
2836                 { 0x1f, 0x0003 },
2837                 { 0x12, 0xc096 },
2838                 { 0x16, 0x000a },
2839                 { 0x1f, 0x0000 },
2840                 { 0x1f, 0x0000 },
2841                 { 0x09, 0x2000 },
2842                 { 0x09, 0x0000 }
2843         };
2844
2845         rtl_writephy_batch(tp, phy_reg_init);
2846
2847         rtl_patchphy(tp, 0x14, 1 << 5);
2848         rtl_patchphy(tp, 0x0d, 1 << 5);
2849         rtl_writephy(tp, 0x1f, 0x0000);
2850 }
2851
2852 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2853 {
2854         static const struct phy_reg phy_reg_init[] = {
2855                 { 0x1f, 0x0001 },
2856                 { 0x12, 0x2300 },
2857                 { 0x03, 0x802f },
2858                 { 0x02, 0x4f02 },
2859                 { 0x01, 0x0409 },
2860                 { 0x00, 0xf099 },
2861                 { 0x04, 0x9800 },
2862                 { 0x04, 0x9000 },
2863                 { 0x1d, 0x3d98 },
2864                 { 0x1f, 0x0002 },
2865                 { 0x0c, 0x7eb8 },
2866                 { 0x06, 0x0761 },
2867                 { 0x1f, 0x0003 },
2868                 { 0x16, 0x0f0a },
2869                 { 0x1f, 0x0000 }
2870         };
2871
2872         rtl_writephy_batch(tp, phy_reg_init);
2873
2874         rtl_patchphy(tp, 0x16, 1 << 0);
2875         rtl_patchphy(tp, 0x14, 1 << 5);
2876         rtl_patchphy(tp, 0x0d, 1 << 5);
2877         rtl_writephy(tp, 0x1f, 0x0000);
2878 }
2879
2880 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2881 {
2882         static const struct phy_reg phy_reg_init[] = {
2883                 { 0x1f, 0x0001 },
2884                 { 0x12, 0x2300 },
2885                 { 0x1d, 0x3d98 },
2886                 { 0x1f, 0x0002 },
2887                 { 0x0c, 0x7eb8 },
2888                 { 0x06, 0x5461 },
2889                 { 0x1f, 0x0003 },
2890                 { 0x16, 0x0f0a },
2891                 { 0x1f, 0x0000 }
2892         };
2893
2894         rtl_writephy_batch(tp, phy_reg_init);
2895
2896         rtl_patchphy(tp, 0x16, 1 << 0);
2897         rtl_patchphy(tp, 0x14, 1 << 5);
2898         rtl_patchphy(tp, 0x0d, 1 << 5);
2899         rtl_writephy(tp, 0x1f, 0x0000);
2900 }
2901
2902 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2903 {
2904         rtl8168c_3_hw_phy_config(tp);
2905 }
2906
2907 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2908         /* Channel Estimation */
2909         { 0x1f, 0x0001 },
2910         { 0x06, 0x4064 },
2911         { 0x07, 0x2863 },
2912         { 0x08, 0x059c },
2913         { 0x09, 0x26b4 },
2914         { 0x0a, 0x6a19 },
2915         { 0x0b, 0xdcc8 },
2916         { 0x10, 0xf06d },
2917         { 0x14, 0x7f68 },
2918         { 0x18, 0x7fd9 },
2919         { 0x1c, 0xf0ff },
2920         { 0x1d, 0x3d9c },
2921         { 0x1f, 0x0003 },
2922         { 0x12, 0xf49f },
2923         { 0x13, 0x070b },
2924         { 0x1a, 0x05ad },
2925         { 0x14, 0x94c0 },
2926
2927         /*
2928          * Tx Error Issue
2929          * Enhance line driver power
2930          */
2931         { 0x1f, 0x0002 },
2932         { 0x06, 0x5561 },
2933         { 0x1f, 0x0005 },
2934         { 0x05, 0x8332 },
2935         { 0x06, 0x5561 },
2936
2937         /*
2938          * Can not link to 1Gbps with bad cable
2939          * Decrease SNR threshold form 21.07dB to 19.04dB
2940          */
2941         { 0x1f, 0x0001 },
2942         { 0x17, 0x0cc0 },
2943
2944         { 0x1f, 0x0000 },
2945         { 0x0d, 0xf880 }
2946 };
2947
2948 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2949         { 0x1f, 0x0002 },
2950         { 0x05, 0x669a },
2951         { 0x1f, 0x0005 },
2952         { 0x05, 0x8330 },
2953         { 0x06, 0x669a },
2954         { 0x1f, 0x0002 }
2955 };
2956
2957 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2958 {
2959         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2960
2961         /*
2962          * Rx Error Issue
2963          * Fine Tune Switching regulator parameter
2964          */
2965         rtl_writephy(tp, 0x1f, 0x0002);
2966         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2967         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2968
2969         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2970                 int val;
2971
2972                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2973
2974                 val = rtl_readphy(tp, 0x0d);
2975
2976                 if ((val & 0x00ff) != 0x006c) {
2977                         static const u32 set[] = {
2978                                 0x0065, 0x0066, 0x0067, 0x0068,
2979                                 0x0069, 0x006a, 0x006b, 0x006c
2980                         };
2981                         int i;
2982
2983                         rtl_writephy(tp, 0x1f, 0x0002);
2984
2985                         val &= 0xff00;
2986                         for (i = 0; i < ARRAY_SIZE(set); i++)
2987                                 rtl_writephy(tp, 0x0d, val | set[i]);
2988                 }
2989         } else {
2990                 static const struct phy_reg phy_reg_init[] = {
2991                         { 0x1f, 0x0002 },
2992                         { 0x05, 0x6662 },
2993                         { 0x1f, 0x0005 },
2994                         { 0x05, 0x8330 },
2995                         { 0x06, 0x6662 }
2996                 };
2997
2998                 rtl_writephy_batch(tp, phy_reg_init);
2999         }
3000
3001         /* RSET couple improve */
3002         rtl_writephy(tp, 0x1f, 0x0002);
3003         rtl_patchphy(tp, 0x0d, 0x0300);
3004         rtl_patchphy(tp, 0x0f, 0x0010);
3005
3006         /* Fine tune PLL performance */
3007         rtl_writephy(tp, 0x1f, 0x0002);
3008         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3009         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3010
3011         rtl_writephy(tp, 0x1f, 0x0005);
3012         rtl_writephy(tp, 0x05, 0x001b);
3013
3014         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3015
3016         rtl_writephy(tp, 0x1f, 0x0000);
3017 }
3018
3019 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3020 {
3021         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3022
3023         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3024                 int val;
3025
3026                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3027
3028                 val = rtl_readphy(tp, 0x0d);
3029                 if ((val & 0x00ff) != 0x006c) {
3030                         static const u32 set[] = {
3031                                 0x0065, 0x0066, 0x0067, 0x0068,
3032                                 0x0069, 0x006a, 0x006b, 0x006c
3033                         };
3034                         int i;
3035
3036                         rtl_writephy(tp, 0x1f, 0x0002);
3037
3038                         val &= 0xff00;
3039                         for (i = 0; i < ARRAY_SIZE(set); i++)
3040                                 rtl_writephy(tp, 0x0d, val | set[i]);
3041                 }
3042         } else {
3043                 static const struct phy_reg phy_reg_init[] = {
3044                         { 0x1f, 0x0002 },
3045                         { 0x05, 0x2642 },
3046                         { 0x1f, 0x0005 },
3047                         { 0x05, 0x8330 },
3048                         { 0x06, 0x2642 }
3049                 };
3050
3051                 rtl_writephy_batch(tp, phy_reg_init);
3052         }
3053
3054         /* Fine tune PLL performance */
3055         rtl_writephy(tp, 0x1f, 0x0002);
3056         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3057         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3058
3059         /* Switching regulator Slew rate */
3060         rtl_writephy(tp, 0x1f, 0x0002);
3061         rtl_patchphy(tp, 0x0f, 0x0017);
3062
3063         rtl_writephy(tp, 0x1f, 0x0005);
3064         rtl_writephy(tp, 0x05, 0x001b);
3065
3066         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3067
3068         rtl_writephy(tp, 0x1f, 0x0000);
3069 }
3070
3071 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3072 {
3073         static const struct phy_reg phy_reg_init[] = {
3074                 { 0x1f, 0x0002 },
3075                 { 0x10, 0x0008 },
3076                 { 0x0d, 0x006c },
3077
3078                 { 0x1f, 0x0000 },
3079                 { 0x0d, 0xf880 },
3080
3081                 { 0x1f, 0x0001 },
3082                 { 0x17, 0x0cc0 },
3083
3084                 { 0x1f, 0x0001 },
3085                 { 0x0b, 0xa4d8 },
3086                 { 0x09, 0x281c },
3087                 { 0x07, 0x2883 },
3088                 { 0x0a, 0x6b35 },
3089                 { 0x1d, 0x3da4 },
3090                 { 0x1c, 0xeffd },
3091                 { 0x14, 0x7f52 },
3092                 { 0x18, 0x7fc6 },
3093                 { 0x08, 0x0601 },
3094                 { 0x06, 0x4063 },
3095                 { 0x10, 0xf074 },
3096                 { 0x1f, 0x0003 },
3097                 { 0x13, 0x0789 },
3098                 { 0x12, 0xf4bd },
3099                 { 0x1a, 0x04fd },
3100                 { 0x14, 0x84b0 },
3101                 { 0x1f, 0x0000 },
3102                 { 0x00, 0x9200 },
3103
3104                 { 0x1f, 0x0005 },
3105                 { 0x01, 0x0340 },
3106                 { 0x1f, 0x0001 },
3107                 { 0x04, 0x4000 },
3108                 { 0x03, 0x1d21 },
3109                 { 0x02, 0x0c32 },
3110                 { 0x01, 0x0200 },
3111                 { 0x00, 0x5554 },
3112                 { 0x04, 0x4800 },
3113                 { 0x04, 0x4000 },
3114                 { 0x04, 0xf000 },
3115                 { 0x03, 0xdf01 },
3116                 { 0x02, 0xdf20 },
3117                 { 0x01, 0x101a },
3118                 { 0x00, 0xa0ff },
3119                 { 0x04, 0xf800 },
3120                 { 0x04, 0xf000 },
3121                 { 0x1f, 0x0000 },
3122
3123                 { 0x1f, 0x0007 },
3124                 { 0x1e, 0x0023 },
3125                 { 0x16, 0x0000 },
3126                 { 0x1f, 0x0000 }
3127         };
3128
3129         rtl_writephy_batch(tp, phy_reg_init);
3130 }
3131
3132 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134         static const struct phy_reg phy_reg_init[] = {
3135                 { 0x1f, 0x0001 },
3136                 { 0x17, 0x0cc0 },
3137
3138                 { 0x1f, 0x0007 },
3139                 { 0x1e, 0x002d },
3140                 { 0x18, 0x0040 },
3141                 { 0x1f, 0x0000 }
3142         };
3143
3144         rtl_writephy_batch(tp, phy_reg_init);
3145         rtl_patchphy(tp, 0x0d, 1 << 5);
3146 }
3147
3148 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3149 {
3150         static const struct phy_reg phy_reg_init[] = {
3151                 /* Enable Delay cap */
3152                 { 0x1f, 0x0005 },
3153                 { 0x05, 0x8b80 },
3154                 { 0x06, 0xc896 },
3155                 { 0x1f, 0x0000 },
3156
3157                 /* Channel estimation fine tune */
3158                 { 0x1f, 0x0001 },
3159                 { 0x0b, 0x6c20 },
3160                 { 0x07, 0x2872 },
3161                 { 0x1c, 0xefff },
3162                 { 0x1f, 0x0003 },
3163                 { 0x14, 0x6420 },
3164                 { 0x1f, 0x0000 },
3165
3166                 /* Update PFM & 10M TX idle timer */
3167                 { 0x1f, 0x0007 },
3168                 { 0x1e, 0x002f },
3169                 { 0x15, 0x1919 },
3170                 { 0x1f, 0x0000 },
3171
3172                 { 0x1f, 0x0007 },
3173                 { 0x1e, 0x00ac },
3174                 { 0x18, 0x0006 },
3175                 { 0x1f, 0x0000 }
3176         };
3177
3178         rtl_apply_firmware(tp);
3179
3180         rtl_writephy_batch(tp, phy_reg_init);
3181
3182         /* DCO enable for 10M IDLE Power */
3183         rtl_writephy(tp, 0x1f, 0x0007);
3184         rtl_writephy(tp, 0x1e, 0x0023);
3185         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3186         rtl_writephy(tp, 0x1f, 0x0000);
3187
3188         /* For impedance matching */
3189         rtl_writephy(tp, 0x1f, 0x0002);
3190         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3191         rtl_writephy(tp, 0x1f, 0x0000);
3192
3193         /* PHY auto speed down */
3194         rtl_writephy(tp, 0x1f, 0x0007);
3195         rtl_writephy(tp, 0x1e, 0x002d);
3196         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3197         rtl_writephy(tp, 0x1f, 0x0000);
3198         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3199
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b86);
3202         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3203         rtl_writephy(tp, 0x1f, 0x0000);
3204
3205         rtl_writephy(tp, 0x1f, 0x0005);
3206         rtl_writephy(tp, 0x05, 0x8b85);
3207         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3208         rtl_writephy(tp, 0x1f, 0x0007);
3209         rtl_writephy(tp, 0x1e, 0x0020);
3210         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3211         rtl_writephy(tp, 0x1f, 0x0006);
3212         rtl_writephy(tp, 0x00, 0x5a00);
3213         rtl_writephy(tp, 0x1f, 0x0000);
3214         rtl_writephy(tp, 0x0d, 0x0007);
3215         rtl_writephy(tp, 0x0e, 0x003c);
3216         rtl_writephy(tp, 0x0d, 0x4007);
3217         rtl_writephy(tp, 0x0e, 0x0000);
3218         rtl_writephy(tp, 0x0d, 0x0000);
3219 }
3220
3221 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3222 {
3223         const u16 w[] = {
3224                 addr[0] | (addr[1] << 8),
3225                 addr[2] | (addr[3] << 8),
3226                 addr[4] | (addr[5] << 8)
3227         };
3228
3229         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3230         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3231         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3232         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3233 }
3234
3235 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3236 {
3237         static const struct phy_reg phy_reg_init[] = {
3238                 /* Enable Delay cap */
3239                 { 0x1f, 0x0004 },
3240                 { 0x1f, 0x0007 },
3241                 { 0x1e, 0x00ac },
3242                 { 0x18, 0x0006 },
3243                 { 0x1f, 0x0002 },
3244                 { 0x1f, 0x0000 },
3245                 { 0x1f, 0x0000 },
3246
3247                 /* Channel estimation fine tune */
3248                 { 0x1f, 0x0003 },
3249                 { 0x09, 0xa20f },
3250                 { 0x1f, 0x0000 },
3251                 { 0x1f, 0x0000 },
3252
3253                 /* Green Setting */
3254                 { 0x1f, 0x0005 },
3255                 { 0x05, 0x8b5b },
3256                 { 0x06, 0x9222 },
3257                 { 0x05, 0x8b6d },
3258                 { 0x06, 0x8000 },
3259                 { 0x05, 0x8b76 },
3260                 { 0x06, 0x8000 },
3261                 { 0x1f, 0x0000 }
3262         };
3263
3264         rtl_apply_firmware(tp);
3265
3266         rtl_writephy_batch(tp, phy_reg_init);
3267
3268         /* For 4-corner performance improve */
3269         rtl_writephy(tp, 0x1f, 0x0005);
3270         rtl_writephy(tp, 0x05, 0x8b80);
3271         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3272         rtl_writephy(tp, 0x1f, 0x0000);
3273
3274         /* PHY auto speed down */
3275         rtl_writephy(tp, 0x1f, 0x0004);
3276         rtl_writephy(tp, 0x1f, 0x0007);
3277         rtl_writephy(tp, 0x1e, 0x002d);
3278         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3279         rtl_writephy(tp, 0x1f, 0x0002);
3280         rtl_writephy(tp, 0x1f, 0x0000);
3281         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3282
3283         /* improve 10M EEE waveform */
3284         rtl_writephy(tp, 0x1f, 0x0005);
3285         rtl_writephy(tp, 0x05, 0x8b86);
3286         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3287         rtl_writephy(tp, 0x1f, 0x0000);
3288
3289         /* Improve 2-pair detection performance */
3290         rtl_writephy(tp, 0x1f, 0x0005);
3291         rtl_writephy(tp, 0x05, 0x8b85);
3292         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0000);
3294
3295         rtl8168f_config_eee_phy(tp);
3296         rtl_enable_eee(tp);
3297
3298         /* Green feature */
3299         rtl_writephy(tp, 0x1f, 0x0003);
3300         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3301         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3302         rtl_writephy(tp, 0x1f, 0x0000);
3303         rtl_writephy(tp, 0x1f, 0x0005);
3304         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3305         rtl_writephy(tp, 0x1f, 0x0000);
3306
3307         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3308         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3309 }
3310
3311 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3312 {
3313         /* For 4-corner performance improve */
3314         rtl_writephy(tp, 0x1f, 0x0005);
3315         rtl_writephy(tp, 0x05, 0x8b80);
3316         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3317         rtl_writephy(tp, 0x1f, 0x0000);
3318
3319         /* PHY auto speed down */
3320         rtl_writephy(tp, 0x1f, 0x0007);
3321         rtl_writephy(tp, 0x1e, 0x002d);
3322         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3323         rtl_writephy(tp, 0x1f, 0x0000);
3324         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3325
3326         /* Improve 10M EEE waveform */
3327         rtl_writephy(tp, 0x1f, 0x0005);
3328         rtl_writephy(tp, 0x05, 0x8b86);
3329         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3330         rtl_writephy(tp, 0x1f, 0x0000);
3331
3332         rtl8168f_config_eee_phy(tp);
3333         rtl_enable_eee(tp);
3334 }
3335
3336 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3337 {
3338         static const struct phy_reg phy_reg_init[] = {
3339                 /* Channel estimation fine tune */
3340                 { 0x1f, 0x0003 },
3341                 { 0x09, 0xa20f },
3342                 { 0x1f, 0x0000 },
3343
3344                 /* Modify green table for giga & fnet */
3345                 { 0x1f, 0x0005 },
3346                 { 0x05, 0x8b55 },
3347                 { 0x06, 0x0000 },
3348                 { 0x05, 0x8b5e },
3349                 { 0x06, 0x0000 },
3350                 { 0x05, 0x8b67 },
3351                 { 0x06, 0x0000 },
3352                 { 0x05, 0x8b70 },
3353                 { 0x06, 0x0000 },
3354                 { 0x1f, 0x0000 },
3355                 { 0x1f, 0x0007 },
3356                 { 0x1e, 0x0078 },
3357                 { 0x17, 0x0000 },
3358                 { 0x19, 0x00fb },
3359                 { 0x1f, 0x0000 },
3360
3361                 /* Modify green table for 10M */
3362                 { 0x1f, 0x0005 },
3363                 { 0x05, 0x8b79 },
3364                 { 0x06, 0xaa00 },
3365                 { 0x1f, 0x0000 },
3366
3367                 /* Disable hiimpedance detection (RTCT) */
3368                 { 0x1f, 0x0003 },
3369                 { 0x01, 0x328a },
3370                 { 0x1f, 0x0000 }
3371         };
3372
3373         rtl_apply_firmware(tp);
3374
3375         rtl_writephy_batch(tp, phy_reg_init);
3376
3377         rtl8168f_hw_phy_config(tp);
3378
3379         /* Improve 2-pair detection performance */
3380         rtl_writephy(tp, 0x1f, 0x0005);
3381         rtl_writephy(tp, 0x05, 0x8b85);
3382         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384 }
3385
3386 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3387 {
3388         rtl_apply_firmware(tp);
3389
3390         rtl8168f_hw_phy_config(tp);
3391 }
3392
3393 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3394 {
3395         static const struct phy_reg phy_reg_init[] = {
3396                 /* Channel estimation fine tune */
3397                 { 0x1f, 0x0003 },
3398                 { 0x09, 0xa20f },
3399                 { 0x1f, 0x0000 },
3400
3401                 /* Modify green table for giga & fnet */
3402                 { 0x1f, 0x0005 },
3403                 { 0x05, 0x8b55 },
3404                 { 0x06, 0x0000 },
3405                 { 0x05, 0x8b5e },
3406                 { 0x06, 0x0000 },
3407                 { 0x05, 0x8b67 },
3408                 { 0x06, 0x0000 },
3409                 { 0x05, 0x8b70 },
3410                 { 0x06, 0x0000 },
3411                 { 0x1f, 0x0000 },
3412                 { 0x1f, 0x0007 },
3413                 { 0x1e, 0x0078 },
3414                 { 0x17, 0x0000 },
3415                 { 0x19, 0x00aa },
3416                 { 0x1f, 0x0000 },
3417
3418                 /* Modify green table for 10M */
3419                 { 0x1f, 0x0005 },
3420                 { 0x05, 0x8b79 },
3421                 { 0x06, 0xaa00 },
3422                 { 0x1f, 0x0000 },
3423
3424                 /* Disable hiimpedance detection (RTCT) */
3425                 { 0x1f, 0x0003 },
3426                 { 0x01, 0x328a },
3427                 { 0x1f, 0x0000 }
3428         };
3429
3430
3431         rtl_apply_firmware(tp);
3432
3433         rtl8168f_hw_phy_config(tp);
3434
3435         /* Improve 2-pair detection performance */
3436         rtl_writephy(tp, 0x1f, 0x0005);
3437         rtl_writephy(tp, 0x05, 0x8b85);
3438         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3439         rtl_writephy(tp, 0x1f, 0x0000);
3440
3441         rtl_writephy_batch(tp, phy_reg_init);
3442
3443         /* Modify green table for giga */
3444         rtl_writephy(tp, 0x1f, 0x0005);
3445         rtl_writephy(tp, 0x05, 0x8b54);
3446         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3447         rtl_writephy(tp, 0x05, 0x8b5d);
3448         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3449         rtl_writephy(tp, 0x05, 0x8a7c);
3450         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3451         rtl_writephy(tp, 0x05, 0x8a7f);
3452         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3453         rtl_writephy(tp, 0x05, 0x8a82);
3454         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3455         rtl_writephy(tp, 0x05, 0x8a85);
3456         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3457         rtl_writephy(tp, 0x05, 0x8a88);
3458         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3459         rtl_writephy(tp, 0x1f, 0x0000);
3460
3461         /* uc same-seed solution */
3462         rtl_writephy(tp, 0x1f, 0x0005);
3463         rtl_writephy(tp, 0x05, 0x8b85);
3464         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3465         rtl_writephy(tp, 0x1f, 0x0000);
3466
3467         /* Green feature */
3468         rtl_writephy(tp, 0x1f, 0x0003);
3469         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3470         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3471         rtl_writephy(tp, 0x1f, 0x0000);
3472 }
3473
3474 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3475 {
3476         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3477 }
3478
3479 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3480 {
3481         struct phy_device *phydev = tp->phydev;
3482
3483         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3484         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3485         phy_write(phydev, 0x1f, 0x0a43);
3486         phy_write(phydev, 0x13, 0x8084);
3487         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3488         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3489
3490         phy_write(phydev, 0x1f, 0x0000);
3491 }
3492
3493 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3494 {
3495         int ret;
3496
3497         rtl_apply_firmware(tp);
3498
3499         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3500         if (ret & BIT(8))
3501                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3502         else
3503                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3504
3505         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3506         if (ret & BIT(8))
3507                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3508         else
3509                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3510
3511         /* Enable PHY auto speed down */
3512         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3513
3514         rtl8168g_phy_adjust_10m_aldps(tp);
3515
3516         /* EEE auto-fallback function */
3517         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3518
3519         /* Enable UC LPF tune function */
3520         rtl_writephy(tp, 0x1f, 0x0a43);
3521         rtl_writephy(tp, 0x13, 0x8012);
3522         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3523
3524         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3525
3526         /* Improve SWR Efficiency */
3527         rtl_writephy(tp, 0x1f, 0x0bcd);
3528         rtl_writephy(tp, 0x14, 0x5065);
3529         rtl_writephy(tp, 0x14, 0xd065);
3530         rtl_writephy(tp, 0x1f, 0x0bc8);
3531         rtl_writephy(tp, 0x11, 0x5655);
3532         rtl_writephy(tp, 0x1f, 0x0bcd);
3533         rtl_writephy(tp, 0x14, 0x1065);
3534         rtl_writephy(tp, 0x14, 0x9065);
3535         rtl_writephy(tp, 0x14, 0x1065);
3536         rtl_writephy(tp, 0x1f, 0x0000);
3537
3538         rtl8168g_disable_aldps(tp);
3539         rtl8168g_config_eee_phy(tp);
3540         rtl_enable_eee(tp);
3541 }
3542
3543 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3544 {
3545         rtl_apply_firmware(tp);
3546         rtl8168g_config_eee_phy(tp);
3547         rtl_enable_eee(tp);
3548 }
3549
3550 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3551 {
3552         u16 dout_tapbin;
3553         u32 data;
3554
3555         rtl_apply_firmware(tp);
3556
3557         /* CHN EST parameters adjust - giga master */
3558         rtl_writephy(tp, 0x1f, 0x0a43);
3559         rtl_writephy(tp, 0x13, 0x809b);
3560         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3561         rtl_writephy(tp, 0x13, 0x80a2);
3562         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3563         rtl_writephy(tp, 0x13, 0x80a4);
3564         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3565         rtl_writephy(tp, 0x13, 0x809c);
3566         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3567         rtl_writephy(tp, 0x1f, 0x0000);
3568
3569         /* CHN EST parameters adjust - giga slave */
3570         rtl_writephy(tp, 0x1f, 0x0a43);
3571         rtl_writephy(tp, 0x13, 0x80ad);
3572         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3573         rtl_writephy(tp, 0x13, 0x80b4);
3574         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3575         rtl_writephy(tp, 0x13, 0x80ac);
3576         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3577         rtl_writephy(tp, 0x1f, 0x0000);
3578
3579         /* CHN EST parameters adjust - fnet */
3580         rtl_writephy(tp, 0x1f, 0x0a43);
3581         rtl_writephy(tp, 0x13, 0x808e);
3582         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3583         rtl_writephy(tp, 0x13, 0x8090);
3584         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3585         rtl_writephy(tp, 0x13, 0x8092);
3586         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588
3589         /* enable R-tune & PGA-retune function */
3590         dout_tapbin = 0;
3591         rtl_writephy(tp, 0x1f, 0x0a46);
3592         data = rtl_readphy(tp, 0x13);
3593         data &= 3;
3594         data <<= 2;
3595         dout_tapbin |= data;
3596         data = rtl_readphy(tp, 0x12);
3597         data &= 0xc000;
3598         data >>= 14;
3599         dout_tapbin |= data;
3600         dout_tapbin = ~(dout_tapbin^0x08);
3601         dout_tapbin <<= 12;
3602         dout_tapbin &= 0xf000;
3603         rtl_writephy(tp, 0x1f, 0x0a43);
3604         rtl_writephy(tp, 0x13, 0x827a);
3605         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3606         rtl_writephy(tp, 0x13, 0x827b);
3607         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3608         rtl_writephy(tp, 0x13, 0x827c);
3609         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3610         rtl_writephy(tp, 0x13, 0x827d);
3611         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3612
3613         rtl_writephy(tp, 0x1f, 0x0a43);
3614         rtl_writephy(tp, 0x13, 0x0811);
3615         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3616         rtl_writephy(tp, 0x1f, 0x0a42);
3617         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3618         rtl_writephy(tp, 0x1f, 0x0000);
3619
3620         /* enable GPHY 10M */
3621         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3622
3623         /* SAR ADC performance */
3624         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3625
3626         rtl_writephy(tp, 0x1f, 0x0a43);
3627         rtl_writephy(tp, 0x13, 0x803f);
3628         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3629         rtl_writephy(tp, 0x13, 0x8047);
3630         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3631         rtl_writephy(tp, 0x13, 0x804f);
3632         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3633         rtl_writephy(tp, 0x13, 0x8057);
3634         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3635         rtl_writephy(tp, 0x13, 0x805f);
3636         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3637         rtl_writephy(tp, 0x13, 0x8067);
3638         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3639         rtl_writephy(tp, 0x13, 0x806f);
3640         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3641         rtl_writephy(tp, 0x1f, 0x0000);
3642
3643         /* disable phy pfm mode */
3644         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3645
3646         rtl8168g_disable_aldps(tp);
3647         rtl8168g_config_eee_phy(tp);
3648         rtl_enable_eee(tp);
3649 }
3650
3651 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3652 {
3653         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3654         u16 rlen;
3655         u32 data;
3656
3657         rtl_apply_firmware(tp);
3658
3659         /* CHIN EST parameter update */
3660         rtl_writephy(tp, 0x1f, 0x0a43);
3661         rtl_writephy(tp, 0x13, 0x808a);
3662         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3663         rtl_writephy(tp, 0x1f, 0x0000);
3664
3665         /* enable R-tune & PGA-retune function */
3666         rtl_writephy(tp, 0x1f, 0x0a43);
3667         rtl_writephy(tp, 0x13, 0x0811);
3668         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3669         rtl_writephy(tp, 0x1f, 0x0a42);
3670         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3671         rtl_writephy(tp, 0x1f, 0x0000);
3672
3673         /* enable GPHY 10M */
3674         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3675
3676         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3677         data = r8168_mac_ocp_read(tp, 0xdd02);
3678         ioffset_p3 = ((data & 0x80)>>7);
3679         ioffset_p3 <<= 3;
3680
3681         data = r8168_mac_ocp_read(tp, 0xdd00);
3682         ioffset_p3 |= ((data & (0xe000))>>13);
3683         ioffset_p2 = ((data & (0x1e00))>>9);
3684         ioffset_p1 = ((data & (0x01e0))>>5);
3685         ioffset_p0 = ((data & 0x0010)>>4);
3686         ioffset_p0 <<= 3;
3687         ioffset_p0 |= (data & (0x07));
3688         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3689
3690         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3691             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3692                 rtl_writephy(tp, 0x1f, 0x0bcf);
3693                 rtl_writephy(tp, 0x16, data);
3694                 rtl_writephy(tp, 0x1f, 0x0000);
3695         }
3696
3697         /* Modify rlen (TX LPF corner frequency) level */
3698         rtl_writephy(tp, 0x1f, 0x0bcd);
3699         data = rtl_readphy(tp, 0x16);
3700         data &= 0x000f;
3701         rlen = 0;
3702         if (data > 3)
3703                 rlen = data - 3;
3704         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3705         rtl_writephy(tp, 0x17, data);
3706         rtl_writephy(tp, 0x1f, 0x0bcd);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708
3709         /* disable phy pfm mode */
3710         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3711
3712         rtl8168g_disable_aldps(tp);
3713         rtl8168g_config_eee_phy(tp);
3714         rtl_enable_eee(tp);
3715 }
3716
3717 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3718 {
3719         /* Enable PHY auto speed down */
3720         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3721
3722         rtl8168g_phy_adjust_10m_aldps(tp);
3723
3724         /* Enable EEE auto-fallback function */
3725         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3726
3727         /* Enable UC LPF tune function */
3728         rtl_writephy(tp, 0x1f, 0x0a43);
3729         rtl_writephy(tp, 0x13, 0x8012);
3730         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3731         rtl_writephy(tp, 0x1f, 0x0000);
3732
3733         /* set rg_sel_sdm_rate */
3734         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3735
3736         rtl8168g_disable_aldps(tp);
3737         rtl8168g_config_eee_phy(tp);
3738         rtl_enable_eee(tp);
3739 }
3740
3741 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3742 {
3743         rtl8168g_phy_adjust_10m_aldps(tp);
3744
3745         /* Enable UC LPF tune function */
3746         rtl_writephy(tp, 0x1f, 0x0a43);
3747         rtl_writephy(tp, 0x13, 0x8012);
3748         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3749         rtl_writephy(tp, 0x1f, 0x0000);
3750
3751         /* Set rg_sel_sdm_rate */
3752         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3753
3754         /* Channel estimation parameters */
3755         rtl_writephy(tp, 0x1f, 0x0a43);
3756         rtl_writephy(tp, 0x13, 0x80f3);
3757         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3758         rtl_writephy(tp, 0x13, 0x80f0);
3759         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3760         rtl_writephy(tp, 0x13, 0x80ef);
3761         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3762         rtl_writephy(tp, 0x13, 0x80f6);
3763         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3764         rtl_writephy(tp, 0x13, 0x80ec);
3765         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3766         rtl_writephy(tp, 0x13, 0x80ed);
3767         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3768         rtl_writephy(tp, 0x13, 0x80f2);
3769         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3770         rtl_writephy(tp, 0x13, 0x80f4);
3771         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3772         rtl_writephy(tp, 0x1f, 0x0a43);
3773         rtl_writephy(tp, 0x13, 0x8110);
3774         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3775         rtl_writephy(tp, 0x13, 0x810f);
3776         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3777         rtl_writephy(tp, 0x13, 0x8111);
3778         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3779         rtl_writephy(tp, 0x13, 0x8113);
3780         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3781         rtl_writephy(tp, 0x13, 0x8115);
3782         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3783         rtl_writephy(tp, 0x13, 0x810e);
3784         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3785         rtl_writephy(tp, 0x13, 0x810c);
3786         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3787         rtl_writephy(tp, 0x13, 0x810b);
3788         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3789         rtl_writephy(tp, 0x1f, 0x0a43);
3790         rtl_writephy(tp, 0x13, 0x80d1);
3791         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3792         rtl_writephy(tp, 0x13, 0x80cd);
3793         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3794         rtl_writephy(tp, 0x13, 0x80d3);
3795         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3796         rtl_writephy(tp, 0x13, 0x80d5);
3797         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3798         rtl_writephy(tp, 0x13, 0x80d7);
3799         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3800
3801         /* Force PWM-mode */
3802         rtl_writephy(tp, 0x1f, 0x0bcd);
3803         rtl_writephy(tp, 0x14, 0x5065);
3804         rtl_writephy(tp, 0x14, 0xd065);
3805         rtl_writephy(tp, 0x1f, 0x0bc8);
3806         rtl_writephy(tp, 0x12, 0x00ed);
3807         rtl_writephy(tp, 0x1f, 0x0bcd);
3808         rtl_writephy(tp, 0x14, 0x1065);
3809         rtl_writephy(tp, 0x14, 0x9065);
3810         rtl_writephy(tp, 0x14, 0x1065);
3811         rtl_writephy(tp, 0x1f, 0x0000);
3812
3813         rtl8168g_disable_aldps(tp);
3814         rtl8168g_config_eee_phy(tp);
3815         rtl_enable_eee(tp);
3816 }
3817
3818 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3819 {
3820         static const struct phy_reg phy_reg_init[] = {
3821                 { 0x1f, 0x0003 },
3822                 { 0x08, 0x441d },
3823                 { 0x01, 0x9100 },
3824                 { 0x1f, 0x0000 }
3825         };
3826
3827         rtl_writephy(tp, 0x1f, 0x0000);
3828         rtl_patchphy(tp, 0x11, 1 << 12);
3829         rtl_patchphy(tp, 0x19, 1 << 13);
3830         rtl_patchphy(tp, 0x10, 1 << 15);
3831
3832         rtl_writephy_batch(tp, phy_reg_init);
3833 }
3834
3835 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3836 {
3837         static const struct phy_reg phy_reg_init[] = {
3838                 { 0x1f, 0x0005 },
3839                 { 0x1a, 0x0000 },
3840                 { 0x1f, 0x0000 },
3841
3842                 { 0x1f, 0x0004 },
3843                 { 0x1c, 0x0000 },
3844                 { 0x1f, 0x0000 },
3845
3846                 { 0x1f, 0x0001 },
3847                 { 0x15, 0x7701 },
3848                 { 0x1f, 0x0000 }
3849         };
3850
3851         /* Disable ALDPS before ram code */
3852         rtl_writephy(tp, 0x1f, 0x0000);
3853         rtl_writephy(tp, 0x18, 0x0310);
3854         msleep(100);
3855
3856         rtl_apply_firmware(tp);
3857
3858         rtl_writephy_batch(tp, phy_reg_init);
3859 }
3860
3861 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3862 {
3863         /* Disable ALDPS before setting firmware */
3864         rtl_writephy(tp, 0x1f, 0x0000);
3865         rtl_writephy(tp, 0x18, 0x0310);
3866         msleep(20);
3867
3868         rtl_apply_firmware(tp);
3869
3870         /* EEE setting */
3871         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3872         rtl_writephy(tp, 0x1f, 0x0004);
3873         rtl_writephy(tp, 0x10, 0x401f);
3874         rtl_writephy(tp, 0x19, 0x7030);
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876 }
3877
3878 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3879 {
3880         static const struct phy_reg phy_reg_init[] = {
3881                 { 0x1f, 0x0004 },
3882                 { 0x10, 0xc07f },
3883                 { 0x19, 0x7030 },
3884                 { 0x1f, 0x0000 }
3885         };
3886
3887         /* Disable ALDPS before ram code */
3888         rtl_writephy(tp, 0x1f, 0x0000);
3889         rtl_writephy(tp, 0x18, 0x0310);
3890         msleep(100);
3891
3892         rtl_apply_firmware(tp);
3893
3894         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3895         rtl_writephy_batch(tp, phy_reg_init);
3896
3897         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3898 }
3899
3900 static void rtl_hw_phy_config(struct net_device *dev)
3901 {
3902         static const rtl_generic_fct phy_configs[] = {
3903                 /* PCI devices. */
3904                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3905                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3906                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3907                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3908                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3909                 /* PCI-E devices. */
3910                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3911                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3912                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3913                 [RTL_GIGA_MAC_VER_10] = NULL,
3914                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3915                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3916                 [RTL_GIGA_MAC_VER_13] = NULL,
3917                 [RTL_GIGA_MAC_VER_14] = NULL,
3918                 [RTL_GIGA_MAC_VER_15] = NULL,
3919                 [RTL_GIGA_MAC_VER_16] = NULL,
3920                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3921                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3922                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3923                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3924                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3925                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3926                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3927                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3928                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3929                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3930                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3931                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3932                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3933                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3934                 [RTL_GIGA_MAC_VER_31] = NULL,
3935                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3936                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3937                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3938                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3939                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3940                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3941                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3942                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3943                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3944                 [RTL_GIGA_MAC_VER_41] = NULL,
3945                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3946                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3947                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3948                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3949                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3950                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3951                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3952                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3953                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3954                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3955         };
3956         struct rtl8169_private *tp = netdev_priv(dev);
3957
3958         if (phy_configs[tp->mac_version])
3959                 phy_configs[tp->mac_version](tp);
3960 }
3961
3962 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3963 {
3964         if (!test_and_set_bit(flag, tp->wk.flags))
3965                 schedule_work(&tp->wk.work);
3966 }
3967
3968 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3969 {
3970         rtl_hw_phy_config(dev);
3971
3972         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3973                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3974                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3975                 netif_dbg(tp, drv, dev,
3976                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3977                 RTL_W8(tp, 0x82, 0x01);
3978         }
3979
3980         /* We may have called phy_speed_down before */
3981         phy_speed_up(tp->phydev);
3982
3983         genphy_soft_reset(tp->phydev);
3984 }
3985
3986 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3987 {
3988         rtl_lock_work(tp);
3989
3990         rtl_unlock_config_regs(tp);
3991
3992         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3993         RTL_R32(tp, MAC4);
3994
3995         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3996         RTL_R32(tp, MAC0);
3997
3998         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3999                 rtl_rar_exgmac_set(tp, addr);
4000
4001         rtl_lock_config_regs(tp);
4002
4003         rtl_unlock_work(tp);
4004 }
4005
4006 static int rtl_set_mac_address(struct net_device *dev, void *p)
4007 {
4008         struct rtl8169_private *tp = netdev_priv(dev);
4009         struct device *d = tp_to_dev(tp);
4010         int ret;
4011
4012         ret = eth_mac_addr(dev, p);
4013         if (ret)
4014                 return ret;
4015
4016         pm_runtime_get_noresume(d);
4017
4018         if (pm_runtime_active(d))
4019                 rtl_rar_set(tp, dev->dev_addr);
4020
4021         pm_runtime_put_noidle(d);
4022
4023         return 0;
4024 }
4025
4026 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4027 {
4028         struct rtl8169_private *tp = netdev_priv(dev);
4029
4030         if (!netif_running(dev))
4031                 return -ENODEV;
4032
4033         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4034 }
4035
4036 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4037 {
4038         switch (tp->mac_version) {
4039         case RTL_GIGA_MAC_VER_25:
4040         case RTL_GIGA_MAC_VER_26:
4041         case RTL_GIGA_MAC_VER_29:
4042         case RTL_GIGA_MAC_VER_30:
4043         case RTL_GIGA_MAC_VER_32:
4044         case RTL_GIGA_MAC_VER_33:
4045         case RTL_GIGA_MAC_VER_34:
4046         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4047                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4048                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4049                 break;
4050         default:
4051                 break;
4052         }
4053 }
4054
4055 static void rtl_pll_power_down(struct rtl8169_private *tp)
4056 {
4057         if (r8168_check_dash(tp))
4058                 return;
4059
4060         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4061             tp->mac_version == RTL_GIGA_MAC_VER_33)
4062                 rtl_ephy_write(tp, 0x19, 0xff64);
4063
4064         if (device_may_wakeup(tp_to_dev(tp))) {
4065                 phy_speed_down(tp->phydev, false);
4066                 rtl_wol_suspend_quirk(tp);
4067                 return;
4068         }
4069
4070         switch (tp->mac_version) {
4071         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4072         case RTL_GIGA_MAC_VER_37:
4073         case RTL_GIGA_MAC_VER_39:
4074         case RTL_GIGA_MAC_VER_43:
4075         case RTL_GIGA_MAC_VER_44:
4076         case RTL_GIGA_MAC_VER_45:
4077         case RTL_GIGA_MAC_VER_46:
4078         case RTL_GIGA_MAC_VER_47:
4079         case RTL_GIGA_MAC_VER_48:
4080         case RTL_GIGA_MAC_VER_50:
4081         case RTL_GIGA_MAC_VER_51:
4082                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4083                 break;
4084         case RTL_GIGA_MAC_VER_40:
4085         case RTL_GIGA_MAC_VER_41:
4086         case RTL_GIGA_MAC_VER_49:
4087                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4088                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4089                 break;
4090         default:
4091                 break;
4092         }
4093 }
4094
4095 static void rtl_pll_power_up(struct rtl8169_private *tp)
4096 {
4097         switch (tp->mac_version) {
4098         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4099         case RTL_GIGA_MAC_VER_37:
4100         case RTL_GIGA_MAC_VER_39:
4101         case RTL_GIGA_MAC_VER_43:
4102                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4103                 break;
4104         case RTL_GIGA_MAC_VER_44:
4105         case RTL_GIGA_MAC_VER_45:
4106         case RTL_GIGA_MAC_VER_46:
4107         case RTL_GIGA_MAC_VER_47:
4108         case RTL_GIGA_MAC_VER_48:
4109         case RTL_GIGA_MAC_VER_50:
4110         case RTL_GIGA_MAC_VER_51:
4111                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4112                 break;
4113         case RTL_GIGA_MAC_VER_40:
4114         case RTL_GIGA_MAC_VER_41:
4115         case RTL_GIGA_MAC_VER_49:
4116                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4117                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4118                 break;
4119         default:
4120                 break;
4121         }
4122
4123         phy_resume(tp->phydev);
4124         /* give MAC/PHY some time to resume */
4125         msleep(20);
4126 }
4127
4128 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4129 {
4130         switch (tp->mac_version) {
4131         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4132         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4133                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4134                 break;
4135         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4136         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4137         case RTL_GIGA_MAC_VER_38:
4138                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4139                 break;
4140         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4141                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4142                 break;
4143         default:
4144                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4145                 break;
4146         }
4147 }
4148
4149 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4150 {
4151         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4152 }
4153
4154 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4155 {
4156         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4157         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4158         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4159 }
4160
4161 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4162 {
4163         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4164         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4165         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4166 }
4167
4168 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4169 {
4170         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4171 }
4172
4173 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4174 {
4175         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4176 }
4177
4178 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4179 {
4180         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4181         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4182         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4183         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4184 }
4185
4186 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4187 {
4188         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4189         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4190         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4191         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4192 }
4193
4194 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4195 {
4196         rtl_tx_performance_tweak(tp,
4197                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4198 }
4199
4200 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4201 {
4202         rtl_tx_performance_tweak(tp,
4203                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4204 }
4205
4206 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4207 {
4208         r8168b_0_hw_jumbo_enable(tp);
4209
4210         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4211 }
4212
4213 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4214 {
4215         r8168b_0_hw_jumbo_disable(tp);
4216
4217         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4218 }
4219
4220 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4221 {
4222         rtl_unlock_config_regs(tp);
4223         switch (tp->mac_version) {
4224         case RTL_GIGA_MAC_VER_11:
4225                 r8168b_0_hw_jumbo_enable(tp);
4226                 break;
4227         case RTL_GIGA_MAC_VER_12:
4228         case RTL_GIGA_MAC_VER_17:
4229                 r8168b_1_hw_jumbo_enable(tp);
4230                 break;
4231         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4232                 r8168c_hw_jumbo_enable(tp);
4233                 break;
4234         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4235                 r8168dp_hw_jumbo_enable(tp);
4236                 break;
4237         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4238                 r8168e_hw_jumbo_enable(tp);
4239                 break;
4240         default:
4241                 break;
4242         }
4243         rtl_lock_config_regs(tp);
4244 }
4245
4246 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4247 {
4248         rtl_unlock_config_regs(tp);
4249         switch (tp->mac_version) {
4250         case RTL_GIGA_MAC_VER_11:
4251                 r8168b_0_hw_jumbo_disable(tp);
4252                 break;
4253         case RTL_GIGA_MAC_VER_12:
4254         case RTL_GIGA_MAC_VER_17:
4255                 r8168b_1_hw_jumbo_disable(tp);
4256                 break;
4257         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4258                 r8168c_hw_jumbo_disable(tp);
4259                 break;
4260         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4261                 r8168dp_hw_jumbo_disable(tp);
4262                 break;
4263         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4264                 r8168e_hw_jumbo_disable(tp);
4265                 break;
4266         default:
4267                 break;
4268         }
4269         rtl_lock_config_regs(tp);
4270 }
4271
4272 DECLARE_RTL_COND(rtl_chipcmd_cond)
4273 {
4274         return RTL_R8(tp, ChipCmd) & CmdReset;
4275 }
4276
4277 static void rtl_hw_reset(struct rtl8169_private *tp)
4278 {
4279         RTL_W8(tp, ChipCmd, CmdReset);
4280
4281         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4282 }
4283
4284 static void rtl_request_firmware(struct rtl8169_private *tp)
4285 {
4286         struct rtl_fw *rtl_fw;
4287         int rc = -ENOMEM;
4288
4289         /* firmware loaded already or no firmware available */
4290         if (tp->rtl_fw || !tp->fw_name)
4291                 return;
4292
4293         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4294         if (!rtl_fw)
4295                 goto err_warn;
4296
4297         rtl_fw->phy_write = rtl_writephy;
4298         rtl_fw->phy_read = rtl_readphy;
4299         rtl_fw->mac_mcu_write = mac_mcu_write;
4300         rtl_fw->mac_mcu_read = mac_mcu_read;
4301
4302         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4303         if (rc < 0)
4304                 goto err_free;
4305
4306         rc = rtl_check_firmware(tp, rtl_fw);
4307         if (rc < 0)
4308                 goto err_release_firmware;
4309
4310         tp->rtl_fw = rtl_fw;
4311
4312         return;
4313
4314 err_release_firmware:
4315         release_firmware(rtl_fw->fw);
4316 err_free:
4317         kfree(rtl_fw);
4318 err_warn:
4319         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4320                    tp->fw_name, rc);
4321 }
4322
4323 static void rtl_rx_close(struct rtl8169_private *tp)
4324 {
4325         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4326 }
4327
4328 DECLARE_RTL_COND(rtl_npq_cond)
4329 {
4330         return RTL_R8(tp, TxPoll) & NPQ;
4331 }
4332
4333 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4334 {
4335         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4336 }
4337
4338 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4339 {
4340         /* Disable interrupts */
4341         rtl8169_irq_mask_and_ack(tp);
4342
4343         rtl_rx_close(tp);
4344
4345         switch (tp->mac_version) {
4346         case RTL_GIGA_MAC_VER_27:
4347         case RTL_GIGA_MAC_VER_28:
4348         case RTL_GIGA_MAC_VER_31:
4349                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4350                 break;
4351         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4352         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4353                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4354                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4355                 break;
4356         default:
4357                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4358                 udelay(100);
4359                 break;
4360         }
4361
4362         rtl_hw_reset(tp);
4363 }
4364
4365 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4366 {
4367         u32 val = TX_DMA_BURST << TxDMAShift |
4368                   InterFrameGap << TxInterFrameGapShift;
4369
4370         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4371             tp->mac_version != RTL_GIGA_MAC_VER_39)
4372                 val |= TXCFG_AUTO_FIFO;
4373
4374         RTL_W32(tp, TxConfig, val);
4375 }
4376
4377 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4378 {
4379         /* Low hurts. Let's disable the filtering. */
4380         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4381 }
4382
4383 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4384 {
4385         /*
4386          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4387          * register to be written before TxDescAddrLow to work.
4388          * Switching from MMIO to I/O access fixes the issue as well.
4389          */
4390         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4391         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4392         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4393         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4394 }
4395
4396 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4397 {
4398         u32 val;
4399
4400         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4401                 val = 0x000fff00;
4402         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4403                 val = 0x00ffff00;
4404         else
4405                 return;
4406
4407         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4408                 val |= 0xff;
4409
4410         RTL_W32(tp, 0x7c, val);
4411 }
4412
4413 static void rtl_set_rx_mode(struct net_device *dev)
4414 {
4415         struct rtl8169_private *tp = netdev_priv(dev);
4416         u32 mc_filter[2];       /* Multicast hash filter */
4417         int rx_mode;
4418         u32 tmp = 0;
4419
4420         if (dev->flags & IFF_PROMISC) {
4421                 /* Unconditionally log net taps. */
4422                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4423                 rx_mode =
4424                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4425                     AcceptAllPhys;
4426                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4427         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4428                    (dev->flags & IFF_ALLMULTI)) {
4429                 /* Too many to filter perfectly -- accept all multicasts. */
4430                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4431                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4432         } else {
4433                 struct netdev_hw_addr *ha;
4434
4435                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4436                 mc_filter[1] = mc_filter[0] = 0;
4437                 netdev_for_each_mc_addr(ha, dev) {
4438                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4439                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4440                         rx_mode |= AcceptMulticast;
4441                 }
4442         }
4443
4444         if (dev->features & NETIF_F_RXALL)
4445                 rx_mode |= (AcceptErr | AcceptRunt);
4446
4447         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4448
4449         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4450                 u32 data = mc_filter[0];
4451
4452                 mc_filter[0] = swab32(mc_filter[1]);
4453                 mc_filter[1] = swab32(data);
4454         }
4455
4456         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4457                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4458
4459         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4460         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4461
4462         RTL_W32(tp, RxConfig, tmp);
4463 }
4464
4465 static void rtl_hw_start(struct  rtl8169_private *tp)
4466 {
4467         rtl_unlock_config_regs(tp);
4468
4469         tp->hw_start(tp);
4470
4471         rtl_set_rx_max_size(tp);
4472         rtl_set_rx_tx_desc_registers(tp);
4473         rtl_lock_config_regs(tp);
4474
4475         /* disable interrupt coalescing */
4476         RTL_W16(tp, IntrMitigate, 0x0000);
4477         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4478         RTL_R8(tp, IntrMask);
4479         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4480         rtl_init_rxcfg(tp);
4481         rtl_set_tx_config_registers(tp);
4482
4483         rtl_set_rx_mode(tp->dev);
4484         /* no early-rx interrupts */
4485         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4486         rtl_irq_enable(tp);
4487 }
4488
4489 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4490 {
4491         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4492                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4493
4494         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4495
4496         tp->cp_cmd |= PCIMulRW;
4497
4498         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4499             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4500                 netif_dbg(tp, drv, tp->dev,
4501                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4502                 tp->cp_cmd |= (1 << 14);
4503         }
4504
4505         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4506
4507         rtl8169_set_magic_reg(tp, tp->mac_version);
4508
4509         RTL_W32(tp, RxMissed, 0);
4510 }
4511
4512 DECLARE_RTL_COND(rtl_csiar_cond)
4513 {
4514         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4515 }
4516
4517 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4518 {
4519         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4520
4521         RTL_W32(tp, CSIDR, value);
4522         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4523                 CSIAR_BYTE_ENABLE | func << 16);
4524
4525         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4526 }
4527
4528 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4529 {
4530         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4531
4532         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4533                 CSIAR_BYTE_ENABLE);
4534
4535         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4536                 RTL_R32(tp, CSIDR) : ~0;
4537 }
4538
4539 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4540 {
4541         struct pci_dev *pdev = tp->pci_dev;
4542         u32 csi;
4543
4544         /* According to Realtek the value at config space address 0x070f
4545          * controls the L0s/L1 entrance latency. We try standard ECAM access
4546          * first and if it fails fall back to CSI.
4547          */
4548         if (pdev->cfg_size > 0x070f &&
4549             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4550                 return;
4551
4552         netdev_notice_once(tp->dev,
4553                 "No native access to PCI extended config space, falling back to CSI\n");
4554         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4555         rtl_csi_write(tp, 0x070c, csi | val << 24);
4556 }
4557
4558 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4559 {
4560         rtl_csi_access_enable(tp, 0x27);
4561 }
4562
4563 struct ephy_info {
4564         unsigned int offset;
4565         u16 mask;
4566         u16 bits;
4567 };
4568
4569 static void __rtl_ephy_init(struct rtl8169_private *tp,
4570                             const struct ephy_info *e, int len)
4571 {
4572         u16 w;
4573
4574         while (len-- > 0) {
4575                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4576                 rtl_ephy_write(tp, e->offset, w);
4577                 e++;
4578         }
4579 }
4580
4581 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4582
4583 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4584 {
4585         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4586                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4587 }
4588
4589 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4590 {
4591         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4592                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4593 }
4594
4595 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4596 {
4597         /* work around an issue when PCI reset occurs during L2/L3 state */
4598         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4599 }
4600
4601 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4602 {
4603         if (enable) {
4604                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4605                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4606         } else {
4607                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4608                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4609         }
4610
4611         udelay(10);
4612 }
4613
4614 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4615                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4616 {
4617         /* Usage of dynamic vs. static FIFO is controlled by bit
4618          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4619          */
4620         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4621         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4622 }
4623
4624 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4625                                           u8 low, u8 high)
4626 {
4627         /* FIFO thresholds for pause flow control */
4628         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4629         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4630 }
4631
4632 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4633 {
4634         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4635
4636         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4637         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4638
4639         if (tp->dev->mtu <= ETH_DATA_LEN) {
4640                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4641                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4642         }
4643 }
4644
4645 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4646 {
4647         rtl_hw_start_8168bb(tp);
4648
4649         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4650
4651         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4652 }
4653
4654 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4655 {
4656         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4657
4658         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4659
4660         if (tp->dev->mtu <= ETH_DATA_LEN)
4661                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4662
4663         rtl_disable_clock_request(tp);
4664
4665         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4666         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4667 }
4668
4669 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4670 {
4671         static const struct ephy_info e_info_8168cp[] = {
4672                 { 0x01, 0,      0x0001 },
4673                 { 0x02, 0x0800, 0x1000 },
4674                 { 0x03, 0,      0x0042 },
4675                 { 0x06, 0x0080, 0x0000 },
4676                 { 0x07, 0,      0x2000 }
4677         };
4678
4679         rtl_set_def_aspm_entry_latency(tp);
4680
4681         rtl_ephy_init(tp, e_info_8168cp);
4682
4683         __rtl_hw_start_8168cp(tp);
4684 }
4685
4686 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4687 {
4688         rtl_set_def_aspm_entry_latency(tp);
4689
4690         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4691
4692         if (tp->dev->mtu <= ETH_DATA_LEN)
4693                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4694
4695         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4696         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4697 }
4698
4699 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4700 {
4701         rtl_set_def_aspm_entry_latency(tp);
4702
4703         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4704
4705         /* Magic. */
4706         RTL_W8(tp, DBG_REG, 0x20);
4707
4708         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4709
4710         if (tp->dev->mtu <= ETH_DATA_LEN)
4711                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4712
4713         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4714         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4715 }
4716
4717 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4718 {
4719         static const struct ephy_info e_info_8168c_1[] = {
4720                 { 0x02, 0x0800, 0x1000 },
4721                 { 0x03, 0,      0x0002 },
4722                 { 0x06, 0x0080, 0x0000 }
4723         };
4724
4725         rtl_set_def_aspm_entry_latency(tp);
4726
4727         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4728
4729         rtl_ephy_init(tp, e_info_8168c_1);
4730
4731         __rtl_hw_start_8168cp(tp);
4732 }
4733
4734 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4735 {
4736         static const struct ephy_info e_info_8168c_2[] = {
4737                 { 0x01, 0,      0x0001 },
4738                 { 0x03, 0x0400, 0x0220 }
4739         };
4740
4741         rtl_set_def_aspm_entry_latency(tp);
4742
4743         rtl_ephy_init(tp, e_info_8168c_2);
4744
4745         __rtl_hw_start_8168cp(tp);
4746 }
4747
4748 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4749 {
4750         rtl_hw_start_8168c_2(tp);
4751 }
4752
4753 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4754 {
4755         rtl_set_def_aspm_entry_latency(tp);
4756
4757         __rtl_hw_start_8168cp(tp);
4758 }
4759
4760 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4761 {
4762         rtl_set_def_aspm_entry_latency(tp);
4763
4764         rtl_disable_clock_request(tp);
4765
4766         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4767
4768         if (tp->dev->mtu <= ETH_DATA_LEN)
4769                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4770
4771         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4772         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4773 }
4774
4775 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4776 {
4777         rtl_set_def_aspm_entry_latency(tp);
4778
4779         if (tp->dev->mtu <= ETH_DATA_LEN)
4780                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4781
4782         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4783
4784         rtl_disable_clock_request(tp);
4785 }
4786
4787 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4788 {
4789         static const struct ephy_info e_info_8168d_4[] = {
4790                 { 0x0b, 0x0000, 0x0048 },
4791                 { 0x19, 0x0020, 0x0050 },
4792                 { 0x0c, 0x0100, 0x0020 }
4793         };
4794
4795         rtl_set_def_aspm_entry_latency(tp);
4796
4797         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4798
4799         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4800
4801         rtl_ephy_init(tp, e_info_8168d_4);
4802
4803         rtl_enable_clock_request(tp);
4804 }
4805
4806 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4807 {
4808         static const struct ephy_info e_info_8168e_1[] = {
4809                 { 0x00, 0x0200, 0x0100 },
4810                 { 0x00, 0x0000, 0x0004 },
4811                 { 0x06, 0x0002, 0x0001 },
4812                 { 0x06, 0x0000, 0x0030 },
4813                 { 0x07, 0x0000, 0x2000 },
4814                 { 0x00, 0x0000, 0x0020 },
4815                 { 0x03, 0x5800, 0x2000 },
4816                 { 0x03, 0x0000, 0x0001 },
4817                 { 0x01, 0x0800, 0x1000 },
4818                 { 0x07, 0x0000, 0x4000 },
4819                 { 0x1e, 0x0000, 0x2000 },
4820                 { 0x19, 0xffff, 0xfe6c },
4821                 { 0x0a, 0x0000, 0x0040 }
4822         };
4823
4824         rtl_set_def_aspm_entry_latency(tp);
4825
4826         rtl_ephy_init(tp, e_info_8168e_1);
4827
4828         if (tp->dev->mtu <= ETH_DATA_LEN)
4829                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4830
4831         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4832
4833         rtl_disable_clock_request(tp);
4834
4835         /* Reset tx FIFO pointer */
4836         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4837         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4838
4839         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4840 }
4841
4842 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4843 {
4844         static const struct ephy_info e_info_8168e_2[] = {
4845                 { 0x09, 0x0000, 0x0080 },
4846                 { 0x19, 0x0000, 0x0224 }
4847         };
4848
4849         rtl_set_def_aspm_entry_latency(tp);
4850
4851         rtl_ephy_init(tp, e_info_8168e_2);
4852
4853         if (tp->dev->mtu <= ETH_DATA_LEN)
4854                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4855
4856         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4857         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4858         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4859         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4860         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4861         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4862         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4863
4864         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4865
4866         rtl_disable_clock_request(tp);
4867
4868         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4869
4870         rtl8168_config_eee_mac(tp);
4871
4872         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4873         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4874         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4875
4876         rtl_hw_aspm_clkreq_enable(tp, true);
4877 }
4878
4879 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4880 {
4881         rtl_set_def_aspm_entry_latency(tp);
4882
4883         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4884
4885         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4886         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4887         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4888         rtl_reset_packet_filter(tp);
4889         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4890         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4891         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4892         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4893
4894         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4895
4896         rtl_disable_clock_request(tp);
4897
4898         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4899         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4900         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4901         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4902
4903         rtl8168_config_eee_mac(tp);
4904 }
4905
4906 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4907 {
4908         static const struct ephy_info e_info_8168f_1[] = {
4909                 { 0x06, 0x00c0, 0x0020 },
4910                 { 0x08, 0x0001, 0x0002 },
4911                 { 0x09, 0x0000, 0x0080 },
4912                 { 0x19, 0x0000, 0x0224 }
4913         };
4914
4915         rtl_hw_start_8168f(tp);
4916
4917         rtl_ephy_init(tp, e_info_8168f_1);
4918
4919         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4920 }
4921
4922 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4923 {
4924         static const struct ephy_info e_info_8168f_1[] = {
4925                 { 0x06, 0x00c0, 0x0020 },
4926                 { 0x0f, 0xffff, 0x5200 },
4927                 { 0x1e, 0x0000, 0x4000 },
4928                 { 0x19, 0x0000, 0x0224 }
4929         };
4930
4931         rtl_hw_start_8168f(tp);
4932         rtl_pcie_state_l2l3_disable(tp);
4933
4934         rtl_ephy_init(tp, e_info_8168f_1);
4935
4936         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4937 }
4938
4939 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4940 {
4941         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4942         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4943
4944         rtl_set_def_aspm_entry_latency(tp);
4945
4946         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4947
4948         rtl_reset_packet_filter(tp);
4949         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4950
4951         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4952         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4953
4954         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4955         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4956
4957         rtl8168_config_eee_mac(tp);
4958
4959         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4960         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4961
4962         rtl_pcie_state_l2l3_disable(tp);
4963 }
4964
4965 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4966 {
4967         static const struct ephy_info e_info_8168g_1[] = {
4968                 { 0x00, 0x0000, 0x0008 },
4969                 { 0x0c, 0x37d0, 0x0820 },
4970                 { 0x1e, 0x0000, 0x0001 },
4971                 { 0x19, 0x8000, 0x0000 }
4972         };
4973
4974         rtl_hw_start_8168g(tp);
4975
4976         /* disable aspm and clock request before access ephy */
4977         rtl_hw_aspm_clkreq_enable(tp, false);
4978         rtl_ephy_init(tp, e_info_8168g_1);
4979         rtl_hw_aspm_clkreq_enable(tp, true);
4980 }
4981
4982 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4983 {
4984         static const struct ephy_info e_info_8168g_2[] = {
4985                 { 0x00, 0x0000, 0x0008 },
4986                 { 0x0c, 0x3df0, 0x0200 },
4987                 { 0x19, 0xffff, 0xfc00 },
4988                 { 0x1e, 0xffff, 0x20eb }
4989         };
4990
4991         rtl_hw_start_8168g(tp);
4992
4993         /* disable aspm and clock request before access ephy */
4994         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4995         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4996         rtl_ephy_init(tp, e_info_8168g_2);
4997 }
4998
4999 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5000 {
5001         static const struct ephy_info e_info_8411_2[] = {
5002                 { 0x00, 0x0000, 0x0008 },
5003                 { 0x0c, 0x3df0, 0x0200 },
5004                 { 0x0f, 0xffff, 0x5200 },
5005                 { 0x19, 0x0020, 0x0000 },
5006                 { 0x1e, 0x0000, 0x2000 }
5007         };
5008
5009         rtl_hw_start_8168g(tp);
5010
5011         /* disable aspm and clock request before access ephy */
5012         rtl_hw_aspm_clkreq_enable(tp, false);
5013         rtl_ephy_init(tp, e_info_8411_2);
5014         rtl_hw_aspm_clkreq_enable(tp, true);
5015 }
5016
5017 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5018 {
5019         int rg_saw_cnt;
5020         u32 data;
5021         static const struct ephy_info e_info_8168h_1[] = {
5022                 { 0x1e, 0x0800, 0x0001 },
5023                 { 0x1d, 0x0000, 0x0800 },
5024                 { 0x05, 0xffff, 0x2089 },
5025                 { 0x06, 0xffff, 0x5881 },
5026                 { 0x04, 0xffff, 0x154a },
5027                 { 0x01, 0xffff, 0x068b }
5028         };
5029
5030         /* disable aspm and clock request before access ephy */
5031         rtl_hw_aspm_clkreq_enable(tp, false);
5032         rtl_ephy_init(tp, e_info_8168h_1);
5033
5034         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5035         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5036
5037         rtl_set_def_aspm_entry_latency(tp);
5038
5039         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5040
5041         rtl_reset_packet_filter(tp);
5042
5043         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5044
5045         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5046
5047         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5048
5049         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5050         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5051
5052         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5053         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5054
5055         rtl8168_config_eee_mac(tp);
5056
5057         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5058         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5059
5060         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5061
5062         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5063
5064         rtl_pcie_state_l2l3_disable(tp);
5065
5066         rtl_writephy(tp, 0x1f, 0x0c42);
5067         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5068         rtl_writephy(tp, 0x1f, 0x0000);
5069         if (rg_saw_cnt > 0) {
5070                 u16 sw_cnt_1ms_ini;
5071
5072                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5073                 sw_cnt_1ms_ini &= 0x0fff;
5074                 data = r8168_mac_ocp_read(tp, 0xd412);
5075                 data &= ~0x0fff;
5076                 data |= sw_cnt_1ms_ini;
5077                 r8168_mac_ocp_write(tp, 0xd412, data);
5078         }
5079
5080         data = r8168_mac_ocp_read(tp, 0xe056);
5081         data &= ~0xf0;
5082         data |= 0x70;
5083         r8168_mac_ocp_write(tp, 0xe056, data);
5084
5085         data = r8168_mac_ocp_read(tp, 0xe052);
5086         data &= ~0x6000;
5087         data |= 0x8008;
5088         r8168_mac_ocp_write(tp, 0xe052, data);
5089
5090         data = r8168_mac_ocp_read(tp, 0xe0d6);
5091         data &= ~0x01ff;
5092         data |= 0x017f;
5093         r8168_mac_ocp_write(tp, 0xe0d6, data);
5094
5095         data = r8168_mac_ocp_read(tp, 0xd420);
5096         data &= ~0x0fff;
5097         data |= 0x047f;
5098         r8168_mac_ocp_write(tp, 0xd420, data);
5099
5100         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5101         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5102         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5103         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5104
5105         rtl_hw_aspm_clkreq_enable(tp, true);
5106 }
5107
5108 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5109 {
5110         rtl8168ep_stop_cmac(tp);
5111
5112         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5113         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5114
5115         rtl_set_def_aspm_entry_latency(tp);
5116
5117         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5118
5119         rtl_reset_packet_filter(tp);
5120
5121         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5122
5123         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5124
5125         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5126         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5127
5128         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5129         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5130
5131         rtl8168_config_eee_mac(tp);
5132
5133         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5134
5135         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5136
5137         rtl_pcie_state_l2l3_disable(tp);
5138 }
5139
5140 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5141 {
5142         static const struct ephy_info e_info_8168ep_1[] = {
5143                 { 0x00, 0xffff, 0x10ab },
5144                 { 0x06, 0xffff, 0xf030 },
5145                 { 0x08, 0xffff, 0x2006 },
5146                 { 0x0d, 0xffff, 0x1666 },
5147                 { 0x0c, 0x3ff0, 0x0000 }
5148         };
5149
5150         /* disable aspm and clock request before access ephy */
5151         rtl_hw_aspm_clkreq_enable(tp, false);
5152         rtl_ephy_init(tp, e_info_8168ep_1);
5153
5154         rtl_hw_start_8168ep(tp);
5155
5156         rtl_hw_aspm_clkreq_enable(tp, true);
5157 }
5158
5159 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5160 {
5161         static const struct ephy_info e_info_8168ep_2[] = {
5162                 { 0x00, 0xffff, 0x10a3 },
5163                 { 0x19, 0xffff, 0xfc00 },
5164                 { 0x1e, 0xffff, 0x20ea }
5165         };
5166
5167         /* disable aspm and clock request before access ephy */
5168         rtl_hw_aspm_clkreq_enable(tp, false);
5169         rtl_ephy_init(tp, e_info_8168ep_2);
5170
5171         rtl_hw_start_8168ep(tp);
5172
5173         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5174         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5175
5176         rtl_hw_aspm_clkreq_enable(tp, true);
5177 }
5178
5179 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5180 {
5181         u32 data;
5182         static const struct ephy_info e_info_8168ep_3[] = {
5183                 { 0x00, 0xffff, 0x10a3 },
5184                 { 0x19, 0xffff, 0x7c00 },
5185                 { 0x1e, 0xffff, 0x20eb },
5186                 { 0x0d, 0xffff, 0x1666 }
5187         };
5188
5189         /* disable aspm and clock request before access ephy */
5190         rtl_hw_aspm_clkreq_enable(tp, false);
5191         rtl_ephy_init(tp, e_info_8168ep_3);
5192
5193         rtl_hw_start_8168ep(tp);
5194
5195         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5196         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5197
5198         data = r8168_mac_ocp_read(tp, 0xd3e2);
5199         data &= 0xf000;
5200         data |= 0x0271;
5201         r8168_mac_ocp_write(tp, 0xd3e2, data);
5202
5203         data = r8168_mac_ocp_read(tp, 0xd3e4);
5204         data &= 0xff00;
5205         r8168_mac_ocp_write(tp, 0xd3e4, data);
5206
5207         data = r8168_mac_ocp_read(tp, 0xe860);
5208         data |= 0x0080;
5209         r8168_mac_ocp_write(tp, 0xe860, data);
5210
5211         rtl_hw_aspm_clkreq_enable(tp, true);
5212 }
5213
5214 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5215 {
5216         static const struct ephy_info e_info_8102e_1[] = {
5217                 { 0x01, 0, 0x6e65 },
5218                 { 0x02, 0, 0x091f },
5219                 { 0x03, 0, 0xc2f9 },
5220                 { 0x06, 0, 0xafb5 },
5221                 { 0x07, 0, 0x0e00 },
5222                 { 0x19, 0, 0xec80 },
5223                 { 0x01, 0, 0x2e65 },
5224                 { 0x01, 0, 0x6e65 }
5225         };
5226         u8 cfg1;
5227
5228         rtl_set_def_aspm_entry_latency(tp);
5229
5230         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5231
5232         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5233
5234         RTL_W8(tp, Config1,
5235                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5236         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5237
5238         cfg1 = RTL_R8(tp, Config1);
5239         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5240                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5241
5242         rtl_ephy_init(tp, e_info_8102e_1);
5243 }
5244
5245 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5246 {
5247         rtl_set_def_aspm_entry_latency(tp);
5248
5249         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5250
5251         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5252         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5253 }
5254
5255 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5256 {
5257         rtl_hw_start_8102e_2(tp);
5258
5259         rtl_ephy_write(tp, 0x03, 0xc2f9);
5260 }
5261
5262 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5263 {
5264         static const struct ephy_info e_info_8105e_1[] = {
5265                 { 0x07, 0, 0x4000 },
5266                 { 0x19, 0, 0x0200 },
5267                 { 0x19, 0, 0x0020 },
5268                 { 0x1e, 0, 0x2000 },
5269                 { 0x03, 0, 0x0001 },
5270                 { 0x19, 0, 0x0100 },
5271                 { 0x19, 0, 0x0004 },
5272                 { 0x0a, 0, 0x0020 }
5273         };
5274
5275         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5276         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5277
5278         /* Disable Early Tally Counter */
5279         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5280
5281         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5282         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5283
5284         rtl_ephy_init(tp, e_info_8105e_1);
5285
5286         rtl_pcie_state_l2l3_disable(tp);
5287 }
5288
5289 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5290 {
5291         rtl_hw_start_8105e_1(tp);
5292         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5293 }
5294
5295 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5296 {
5297         static const struct ephy_info e_info_8402[] = {
5298                 { 0x19, 0xffff, 0xff64 },
5299                 { 0x1e, 0, 0x4000 }
5300         };
5301
5302         rtl_set_def_aspm_entry_latency(tp);
5303
5304         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5305         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5306
5307         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5308
5309         rtl_ephy_init(tp, e_info_8402);
5310
5311         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5312
5313         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5314         rtl_reset_packet_filter(tp);
5315         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5316         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5317         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5318
5319         rtl_pcie_state_l2l3_disable(tp);
5320 }
5321
5322 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5323 {
5324         rtl_hw_aspm_clkreq_enable(tp, false);
5325
5326         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5327         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5328
5329         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5330         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5331         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5332
5333         rtl_pcie_state_l2l3_disable(tp);
5334         rtl_hw_aspm_clkreq_enable(tp, true);
5335 }
5336
5337 static void rtl_hw_config(struct rtl8169_private *tp)
5338 {
5339         static const rtl_generic_fct hw_configs[] = {
5340                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5341                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5342                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5343                 [RTL_GIGA_MAC_VER_10] = NULL,
5344                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5345                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5346                 [RTL_GIGA_MAC_VER_13] = NULL,
5347                 [RTL_GIGA_MAC_VER_14] = NULL,
5348                 [RTL_GIGA_MAC_VER_15] = NULL,
5349                 [RTL_GIGA_MAC_VER_16] = NULL,
5350                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5351                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5352                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5353                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5354                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5355                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5356                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5357                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5358                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5359                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5360                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5361                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5362                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5363                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5364                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5365                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5366                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5367                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5368                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5369                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5370                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5371                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5372                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5373                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5374                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5375                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5376                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5377                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5378                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5379                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5380                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5381                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5382                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5383                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5384                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5385         };
5386
5387         if (hw_configs[tp->mac_version])
5388                 hw_configs[tp->mac_version](tp);
5389 }
5390
5391 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5392 {
5393         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5394
5395         /* Workaround for RxFIFO overflow. */
5396         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5397                 tp->irq_mask |= RxFIFOOver;
5398                 tp->irq_mask &= ~RxOverflow;
5399         }
5400
5401         rtl_hw_config(tp);
5402 }
5403
5404 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5405 {
5406         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5407                 tp->irq_mask &= ~RxFIFOOver;
5408
5409         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5410             tp->mac_version == RTL_GIGA_MAC_VER_16)
5411                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5412                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5413
5414         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5415
5416         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5417         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5418
5419         rtl_hw_config(tp);
5420 }
5421
5422 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5423 {
5424         struct rtl8169_private *tp = netdev_priv(dev);
5425
5426         if (new_mtu > ETH_DATA_LEN)
5427                 rtl_hw_jumbo_enable(tp);
5428         else
5429                 rtl_hw_jumbo_disable(tp);
5430
5431         dev->mtu = new_mtu;
5432         netdev_update_features(dev);
5433
5434         return 0;
5435 }
5436
5437 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5438 {
5439         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5440         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5441 }
5442
5443 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5444                                      void **data_buff, struct RxDesc *desc)
5445 {
5446         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5447                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5448
5449         kfree(*data_buff);
5450         *data_buff = NULL;
5451         rtl8169_make_unusable_by_asic(desc);
5452 }
5453
5454 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5455 {
5456         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5457
5458         /* Force memory writes to complete before releasing descriptor */
5459         dma_wmb();
5460
5461         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5462 }
5463
5464 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5465                                              struct RxDesc *desc)
5466 {
5467         void *data;
5468         dma_addr_t mapping;
5469         struct device *d = tp_to_dev(tp);
5470         int node = dev_to_node(d);
5471
5472         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5473         if (!data)
5474                 return NULL;
5475
5476         /* Memory should be properly aligned, but better check. */
5477         if (!IS_ALIGNED((unsigned long)data, 8)) {
5478                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5479                 goto err_out;
5480         }
5481
5482         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5483         if (unlikely(dma_mapping_error(d, mapping))) {
5484                 if (net_ratelimit())
5485                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5486                 goto err_out;
5487         }
5488
5489         desc->addr = cpu_to_le64(mapping);
5490         rtl8169_mark_to_asic(desc);
5491         return data;
5492
5493 err_out:
5494         kfree(data);
5495         return NULL;
5496 }
5497
5498 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5499 {
5500         unsigned int i;
5501
5502         for (i = 0; i < NUM_RX_DESC; i++) {
5503                 if (tp->Rx_databuff[i]) {
5504                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5505                                             tp->RxDescArray + i);
5506                 }
5507         }
5508 }
5509
5510 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5511 {
5512         desc->opts1 |= cpu_to_le32(RingEnd);
5513 }
5514
5515 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5516 {
5517         unsigned int i;
5518
5519         for (i = 0; i < NUM_RX_DESC; i++) {
5520                 void *data;
5521
5522                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5523                 if (!data) {
5524                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5525                         goto err_out;
5526                 }
5527                 tp->Rx_databuff[i] = data;
5528         }
5529
5530         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5531         return 0;
5532
5533 err_out:
5534         rtl8169_rx_clear(tp);
5535         return -ENOMEM;
5536 }
5537
5538 static int rtl8169_init_ring(struct rtl8169_private *tp)
5539 {
5540         rtl8169_init_ring_indexes(tp);
5541
5542         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5543         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5544
5545         return rtl8169_rx_fill(tp);
5546 }
5547
5548 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5549                                  struct TxDesc *desc)
5550 {
5551         unsigned int len = tx_skb->len;
5552
5553         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5554
5555         desc->opts1 = 0x00;
5556         desc->opts2 = 0x00;
5557         desc->addr = 0x00;
5558         tx_skb->len = 0;
5559 }
5560
5561 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5562                                    unsigned int n)
5563 {
5564         unsigned int i;
5565
5566         for (i = 0; i < n; i++) {
5567                 unsigned int entry = (start + i) % NUM_TX_DESC;
5568                 struct ring_info *tx_skb = tp->tx_skb + entry;
5569                 unsigned int len = tx_skb->len;
5570
5571                 if (len) {
5572                         struct sk_buff *skb = tx_skb->skb;
5573
5574                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5575                                              tp->TxDescArray + entry);
5576                         if (skb) {
5577                                 dev_consume_skb_any(skb);
5578                                 tx_skb->skb = NULL;
5579                         }
5580                 }
5581         }
5582 }
5583
5584 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5585 {
5586         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5587         tp->cur_tx = tp->dirty_tx = 0;
5588         netdev_reset_queue(tp->dev);
5589 }
5590
5591 static void rtl_reset_work(struct rtl8169_private *tp)
5592 {
5593         struct net_device *dev = tp->dev;
5594         int i;
5595
5596         napi_disable(&tp->napi);
5597         netif_stop_queue(dev);
5598         synchronize_rcu();
5599
5600         rtl8169_hw_reset(tp);
5601
5602         for (i = 0; i < NUM_RX_DESC; i++)
5603                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5604
5605         rtl8169_tx_clear(tp);
5606         rtl8169_init_ring_indexes(tp);
5607
5608         napi_enable(&tp->napi);
5609         rtl_hw_start(tp);
5610         netif_wake_queue(dev);
5611 }
5612
5613 static void rtl8169_tx_timeout(struct net_device *dev)
5614 {
5615         struct rtl8169_private *tp = netdev_priv(dev);
5616
5617         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5618 }
5619
5620 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5621 {
5622         u32 status = opts0 | len;
5623
5624         if (entry == NUM_TX_DESC - 1)
5625                 status |= RingEnd;
5626
5627         return cpu_to_le32(status);
5628 }
5629
5630 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5631                               u32 *opts)
5632 {
5633         struct skb_shared_info *info = skb_shinfo(skb);
5634         unsigned int cur_frag, entry;
5635         struct TxDesc *uninitialized_var(txd);
5636         struct device *d = tp_to_dev(tp);
5637
5638         entry = tp->cur_tx;
5639         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5640                 const skb_frag_t *frag = info->frags + cur_frag;
5641                 dma_addr_t mapping;
5642                 u32 len;
5643                 void *addr;
5644
5645                 entry = (entry + 1) % NUM_TX_DESC;
5646
5647                 txd = tp->TxDescArray + entry;
5648                 len = skb_frag_size(frag);
5649                 addr = skb_frag_address(frag);
5650                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5651                 if (unlikely(dma_mapping_error(d, mapping))) {
5652                         if (net_ratelimit())
5653                                 netif_err(tp, drv, tp->dev,
5654                                           "Failed to map TX fragments DMA!\n");
5655                         goto err_out;
5656                 }
5657
5658                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5659                 txd->opts2 = cpu_to_le32(opts[1]);
5660                 txd->addr = cpu_to_le64(mapping);
5661
5662                 tp->tx_skb[entry].len = len;
5663         }
5664
5665         if (cur_frag) {
5666                 tp->tx_skb[entry].skb = skb;
5667                 txd->opts1 |= cpu_to_le32(LastFrag);
5668         }
5669
5670         return cur_frag;
5671
5672 err_out:
5673         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5674         return -EIO;
5675 }
5676
5677 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5678 {
5679         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5680 }
5681
5682 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5683                                       struct net_device *dev);
5684 /* r8169_csum_workaround()
5685  * The hw limites the value the transport offset. When the offset is out of the
5686  * range, calculate the checksum by sw.
5687  */
5688 static void r8169_csum_workaround(struct rtl8169_private *tp,
5689                                   struct sk_buff *skb)
5690 {
5691         if (skb_is_gso(skb)) {
5692                 netdev_features_t features = tp->dev->features;
5693                 struct sk_buff *segs, *nskb;
5694
5695                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5696                 segs = skb_gso_segment(skb, features);
5697                 if (IS_ERR(segs) || !segs)
5698                         goto drop;
5699
5700                 do {
5701                         nskb = segs;
5702                         segs = segs->next;
5703                         nskb->next = NULL;
5704                         rtl8169_start_xmit(nskb, tp->dev);
5705                 } while (segs);
5706
5707                 dev_consume_skb_any(skb);
5708         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5709                 if (skb_checksum_help(skb) < 0)
5710                         goto drop;
5711
5712                 rtl8169_start_xmit(skb, tp->dev);
5713         } else {
5714 drop:
5715                 tp->dev->stats.tx_dropped++;
5716                 dev_kfree_skb_any(skb);
5717         }
5718 }
5719
5720 /* msdn_giant_send_check()
5721  * According to the document of microsoft, the TCP Pseudo Header excludes the
5722  * packet length for IPv6 TCP large packets.
5723  */
5724 static int msdn_giant_send_check(struct sk_buff *skb)
5725 {
5726         const struct ipv6hdr *ipv6h;
5727         struct tcphdr *th;
5728         int ret;
5729
5730         ret = skb_cow_head(skb, 0);
5731         if (ret)
5732                 return ret;
5733
5734         ipv6h = ipv6_hdr(skb);
5735         th = tcp_hdr(skb);
5736
5737         th->check = 0;
5738         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5739
5740         return ret;
5741 }
5742
5743 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5744 {
5745         u32 mss = skb_shinfo(skb)->gso_size;
5746
5747         if (mss) {
5748                 opts[0] |= TD_LSO;
5749                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5750         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5751                 const struct iphdr *ip = ip_hdr(skb);
5752
5753                 if (ip->protocol == IPPROTO_TCP)
5754                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5755                 else if (ip->protocol == IPPROTO_UDP)
5756                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5757                 else
5758                         WARN_ON_ONCE(1);
5759         }
5760 }
5761
5762 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5763                                 struct sk_buff *skb, u32 *opts)
5764 {
5765         u32 transport_offset = (u32)skb_transport_offset(skb);
5766         u32 mss = skb_shinfo(skb)->gso_size;
5767
5768         if (mss) {
5769                 if (transport_offset > GTTCPHO_MAX) {
5770                         netif_warn(tp, tx_err, tp->dev,
5771                                    "Invalid transport offset 0x%x for TSO\n",
5772                                    transport_offset);
5773                         return false;
5774                 }
5775
5776                 switch (vlan_get_protocol(skb)) {
5777                 case htons(ETH_P_IP):
5778                         opts[0] |= TD1_GTSENV4;
5779                         break;
5780
5781                 case htons(ETH_P_IPV6):
5782                         if (msdn_giant_send_check(skb))
5783                                 return false;
5784
5785                         opts[0] |= TD1_GTSENV6;
5786                         break;
5787
5788                 default:
5789                         WARN_ON_ONCE(1);
5790                         break;
5791                 }
5792
5793                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5794                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5795         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5796                 u8 ip_protocol;
5797
5798                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5799                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5800
5801                 if (transport_offset > TCPHO_MAX) {
5802                         netif_warn(tp, tx_err, tp->dev,
5803                                    "Invalid transport offset 0x%x\n",
5804                                    transport_offset);
5805                         return false;
5806                 }
5807
5808                 switch (vlan_get_protocol(skb)) {
5809                 case htons(ETH_P_IP):
5810                         opts[1] |= TD1_IPv4_CS;
5811                         ip_protocol = ip_hdr(skb)->protocol;
5812                         break;
5813
5814                 case htons(ETH_P_IPV6):
5815                         opts[1] |= TD1_IPv6_CS;
5816                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5817                         break;
5818
5819                 default:
5820                         ip_protocol = IPPROTO_RAW;
5821                         break;
5822                 }
5823
5824                 if (ip_protocol == IPPROTO_TCP)
5825                         opts[1] |= TD1_TCP_CS;
5826                 else if (ip_protocol == IPPROTO_UDP)
5827                         opts[1] |= TD1_UDP_CS;
5828                 else
5829                         WARN_ON_ONCE(1);
5830
5831                 opts[1] |= transport_offset << TCPHO_SHIFT;
5832         } else {
5833                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5834                         return !eth_skb_pad(skb);
5835         }
5836
5837         return true;
5838 }
5839
5840 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5841                                unsigned int nr_frags)
5842 {
5843         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5844
5845         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5846         return slots_avail > nr_frags;
5847 }
5848
5849 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5850 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5851 {
5852         switch (tp->mac_version) {
5853         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5854         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5855                 return false;
5856         default:
5857                 return true;
5858         }
5859 }
5860
5861 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5862                                       struct net_device *dev)
5863 {
5864         struct rtl8169_private *tp = netdev_priv(dev);
5865         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5866         struct TxDesc *txd = tp->TxDescArray + entry;
5867         struct device *d = tp_to_dev(tp);
5868         dma_addr_t mapping;
5869         u32 opts[2], len;
5870         int frags;
5871
5872         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5873                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5874                 goto err_stop_0;
5875         }
5876
5877         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5878                 goto err_stop_0;
5879
5880         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5881         opts[0] = DescOwn;
5882
5883         if (rtl_chip_supports_csum_v2(tp)) {
5884                 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5885                         r8169_csum_workaround(tp, skb);
5886                         return NETDEV_TX_OK;
5887                 }
5888         } else {
5889                 rtl8169_tso_csum_v1(skb, opts);
5890         }
5891
5892         len = skb_headlen(skb);
5893         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5894         if (unlikely(dma_mapping_error(d, mapping))) {
5895                 if (net_ratelimit())
5896                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5897                 goto err_dma_0;
5898         }
5899
5900         tp->tx_skb[entry].len = len;
5901         txd->addr = cpu_to_le64(mapping);
5902
5903         frags = rtl8169_xmit_frags(tp, skb, opts);
5904         if (frags < 0)
5905                 goto err_dma_1;
5906         else if (frags)
5907                 opts[0] |= FirstFrag;
5908         else {
5909                 opts[0] |= FirstFrag | LastFrag;
5910                 tp->tx_skb[entry].skb = skb;
5911         }
5912
5913         txd->opts2 = cpu_to_le32(opts[1]);
5914
5915         netdev_sent_queue(dev, skb->len);
5916
5917         skb_tx_timestamp(skb);
5918
5919         /* Force memory writes to complete before releasing descriptor */
5920         dma_wmb();
5921
5922         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5923
5924         /* Force all memory writes to complete before notifying device */
5925         wmb();
5926
5927         tp->cur_tx += frags + 1;
5928
5929         RTL_W8(tp, TxPoll, NPQ);
5930
5931         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5932                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5933                  * not miss a ring update when it notices a stopped queue.
5934                  */
5935                 smp_wmb();
5936                 netif_stop_queue(dev);
5937                 /* Sync with rtl_tx:
5938                  * - publish queue status and cur_tx ring index (write barrier)
5939                  * - refresh dirty_tx ring index (read barrier).
5940                  * May the current thread have a pessimistic view of the ring
5941                  * status and forget to wake up queue, a racing rtl_tx thread
5942                  * can't.
5943                  */
5944                 smp_mb();
5945                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5946                         netif_start_queue(dev);
5947         }
5948
5949         return NETDEV_TX_OK;
5950
5951 err_dma_1:
5952         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5953 err_dma_0:
5954         dev_kfree_skb_any(skb);
5955         dev->stats.tx_dropped++;
5956         return NETDEV_TX_OK;
5957
5958 err_stop_0:
5959         netif_stop_queue(dev);
5960         dev->stats.tx_dropped++;
5961         return NETDEV_TX_BUSY;
5962 }
5963
5964 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5965 {
5966         struct rtl8169_private *tp = netdev_priv(dev);
5967         struct pci_dev *pdev = tp->pci_dev;
5968         u16 pci_status, pci_cmd;
5969
5970         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5971         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5972
5973         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5974                   pci_cmd, pci_status);
5975
5976         /*
5977          * The recovery sequence below admits a very elaborated explanation:
5978          * - it seems to work;
5979          * - I did not see what else could be done;
5980          * - it makes iop3xx happy.
5981          *
5982          * Feel free to adjust to your needs.
5983          */
5984         if (pdev->broken_parity_status)
5985                 pci_cmd &= ~PCI_COMMAND_PARITY;
5986         else
5987                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5988
5989         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5990
5991         pci_write_config_word(pdev, PCI_STATUS,
5992                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5993                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5994                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5995
5996         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5997 }
5998
5999 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6000                    int budget)
6001 {
6002         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6003
6004         dirty_tx = tp->dirty_tx;
6005         smp_rmb();
6006         tx_left = tp->cur_tx - dirty_tx;
6007
6008         while (tx_left > 0) {
6009                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6010                 struct ring_info *tx_skb = tp->tx_skb + entry;
6011                 u32 status;
6012
6013                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6014                 if (status & DescOwn)
6015                         break;
6016
6017                 /* This barrier is needed to keep us from reading
6018                  * any other fields out of the Tx descriptor until
6019                  * we know the status of DescOwn
6020                  */
6021                 dma_rmb();
6022
6023                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6024                                      tp->TxDescArray + entry);
6025                 if (status & LastFrag) {
6026                         pkts_compl++;
6027                         bytes_compl += tx_skb->skb->len;
6028                         napi_consume_skb(tx_skb->skb, budget);
6029                         tx_skb->skb = NULL;
6030                 }
6031                 dirty_tx++;
6032                 tx_left--;
6033         }
6034
6035         if (tp->dirty_tx != dirty_tx) {
6036                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6037
6038                 u64_stats_update_begin(&tp->tx_stats.syncp);
6039                 tp->tx_stats.packets += pkts_compl;
6040                 tp->tx_stats.bytes += bytes_compl;
6041                 u64_stats_update_end(&tp->tx_stats.syncp);
6042
6043                 tp->dirty_tx = dirty_tx;
6044                 /* Sync with rtl8169_start_xmit:
6045                  * - publish dirty_tx ring index (write barrier)
6046                  * - refresh cur_tx ring index and queue status (read barrier)
6047                  * May the current thread miss the stopped queue condition,
6048                  * a racing xmit thread can only have a right view of the
6049                  * ring status.
6050                  */
6051                 smp_mb();
6052                 if (netif_queue_stopped(dev) &&
6053                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6054                         netif_wake_queue(dev);
6055                 }
6056                 /*
6057                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6058                  * too close. Let's kick an extra TxPoll request when a burst
6059                  * of start_xmit activity is detected (if it is not detected,
6060                  * it is slow enough). -- FR
6061                  */
6062                 if (tp->cur_tx != dirty_tx)
6063                         RTL_W8(tp, TxPoll, NPQ);
6064         }
6065 }
6066
6067 static inline int rtl8169_fragmented_frame(u32 status)
6068 {
6069         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6070 }
6071
6072 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6073 {
6074         u32 status = opts1 & RxProtoMask;
6075
6076         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6077             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6078                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6079         else
6080                 skb_checksum_none_assert(skb);
6081 }
6082
6083 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6084                                            struct rtl8169_private *tp,
6085                                            int pkt_size,
6086                                            dma_addr_t addr)
6087 {
6088         struct sk_buff *skb;
6089         struct device *d = tp_to_dev(tp);
6090
6091         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6092         prefetch(data);
6093         skb = napi_alloc_skb(&tp->napi, pkt_size);
6094         if (skb)
6095                 skb_copy_to_linear_data(skb, data, pkt_size);
6096         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6097
6098         return skb;
6099 }
6100
6101 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6102 {
6103         unsigned int cur_rx, rx_left;
6104         unsigned int count;
6105
6106         cur_rx = tp->cur_rx;
6107
6108         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6109                 unsigned int entry = cur_rx % NUM_RX_DESC;
6110                 struct RxDesc *desc = tp->RxDescArray + entry;
6111                 u32 status;
6112
6113                 status = le32_to_cpu(desc->opts1);
6114                 if (status & DescOwn)
6115                         break;
6116
6117                 /* This barrier is needed to keep us from reading
6118                  * any other fields out of the Rx descriptor until
6119                  * we know the status of DescOwn
6120                  */
6121                 dma_rmb();
6122
6123                 if (unlikely(status & RxRES)) {
6124                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6125                                    status);
6126                         dev->stats.rx_errors++;
6127                         if (status & (RxRWT | RxRUNT))
6128                                 dev->stats.rx_length_errors++;
6129                         if (status & RxCRC)
6130                                 dev->stats.rx_crc_errors++;
6131                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6132                             dev->features & NETIF_F_RXALL) {
6133                                 goto process_pkt;
6134                         }
6135                 } else {
6136                         struct sk_buff *skb;
6137                         dma_addr_t addr;
6138                         int pkt_size;
6139
6140 process_pkt:
6141                         addr = le64_to_cpu(desc->addr);
6142                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6143                                 pkt_size = (status & 0x00003fff) - 4;
6144                         else
6145                                 pkt_size = status & 0x00003fff;
6146
6147                         /*
6148                          * The driver does not support incoming fragmented
6149                          * frames. They are seen as a symptom of over-mtu
6150                          * sized frames.
6151                          */
6152                         if (unlikely(rtl8169_fragmented_frame(status))) {
6153                                 dev->stats.rx_dropped++;
6154                                 dev->stats.rx_length_errors++;
6155                                 goto release_descriptor;
6156                         }
6157
6158                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6159                                                   tp, pkt_size, addr);
6160                         if (!skb) {
6161                                 dev->stats.rx_dropped++;
6162                                 goto release_descriptor;
6163                         }
6164
6165                         rtl8169_rx_csum(skb, status);
6166                         skb_put(skb, pkt_size);
6167                         skb->protocol = eth_type_trans(skb, dev);
6168
6169                         rtl8169_rx_vlan_tag(desc, skb);
6170
6171                         if (skb->pkt_type == PACKET_MULTICAST)
6172                                 dev->stats.multicast++;
6173
6174                         napi_gro_receive(&tp->napi, skb);
6175
6176                         u64_stats_update_begin(&tp->rx_stats.syncp);
6177                         tp->rx_stats.packets++;
6178                         tp->rx_stats.bytes += pkt_size;
6179                         u64_stats_update_end(&tp->rx_stats.syncp);
6180                 }
6181 release_descriptor:
6182                 desc->opts2 = 0;
6183                 rtl8169_mark_to_asic(desc);
6184         }
6185
6186         count = cur_rx - tp->cur_rx;
6187         tp->cur_rx = cur_rx;
6188
6189         return count;
6190 }
6191
6192 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6193 {
6194         struct rtl8169_private *tp = dev_instance;
6195         u16 status = RTL_R16(tp, IntrStatus);
6196
6197         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6198                 return IRQ_NONE;
6199
6200         if (unlikely(status & SYSErr)) {
6201                 rtl8169_pcierr_interrupt(tp->dev);
6202                 goto out;
6203         }
6204
6205         if (status & LinkChg)
6206                 phy_mac_interrupt(tp->phydev);
6207
6208         if (unlikely(status & RxFIFOOver &&
6209             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6210                 netif_stop_queue(tp->dev);
6211                 /* XXX - Hack alert. See rtl_task(). */
6212                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6213         }
6214
6215         rtl_irq_disable(tp);
6216         napi_schedule_irqoff(&tp->napi);
6217 out:
6218         rtl_ack_events(tp, status);
6219
6220         return IRQ_HANDLED;
6221 }
6222
6223 static void rtl_task(struct work_struct *work)
6224 {
6225         static const struct {
6226                 int bitnr;
6227                 void (*action)(struct rtl8169_private *);
6228         } rtl_work[] = {
6229                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6230         };
6231         struct rtl8169_private *tp =
6232                 container_of(work, struct rtl8169_private, wk.work);
6233         struct net_device *dev = tp->dev;
6234         int i;
6235
6236         rtl_lock_work(tp);
6237
6238         if (!netif_running(dev) ||
6239             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6240                 goto out_unlock;
6241
6242         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6243                 bool pending;
6244
6245                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6246                 if (pending)
6247                         rtl_work[i].action(tp);
6248         }
6249
6250 out_unlock:
6251         rtl_unlock_work(tp);
6252 }
6253
6254 static int rtl8169_poll(struct napi_struct *napi, int budget)
6255 {
6256         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6257         struct net_device *dev = tp->dev;
6258         int work_done;
6259
6260         work_done = rtl_rx(dev, tp, (u32) budget);
6261
6262         rtl_tx(dev, tp, budget);
6263
6264         if (work_done < budget) {
6265                 napi_complete_done(napi, work_done);
6266                 rtl_irq_enable(tp);
6267         }
6268
6269         return work_done;
6270 }
6271
6272 static void rtl8169_rx_missed(struct net_device *dev)
6273 {
6274         struct rtl8169_private *tp = netdev_priv(dev);
6275
6276         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6277                 return;
6278
6279         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6280         RTL_W32(tp, RxMissed, 0);
6281 }
6282
6283 static void r8169_phylink_handler(struct net_device *ndev)
6284 {
6285         struct rtl8169_private *tp = netdev_priv(ndev);
6286
6287         if (netif_carrier_ok(ndev)) {
6288                 rtl_link_chg_patch(tp);
6289                 pm_request_resume(&tp->pci_dev->dev);
6290         } else {
6291                 pm_runtime_idle(&tp->pci_dev->dev);
6292         }
6293
6294         if (net_ratelimit())
6295                 phy_print_status(tp->phydev);
6296 }
6297
6298 static int r8169_phy_connect(struct rtl8169_private *tp)
6299 {
6300         struct phy_device *phydev = tp->phydev;
6301         phy_interface_t phy_mode;
6302         int ret;
6303
6304         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6305                    PHY_INTERFACE_MODE_MII;
6306
6307         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6308                                  phy_mode);
6309         if (ret)
6310                 return ret;
6311
6312         if (tp->supports_gmii)
6313                 phy_remove_link_mode(phydev,
6314                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6315         else
6316                 phy_set_max_speed(phydev, SPEED_100);
6317
6318         phy_support_asym_pause(phydev);
6319
6320         phy_attached_info(phydev);
6321
6322         return 0;
6323 }
6324
6325 static void rtl8169_down(struct net_device *dev)
6326 {
6327         struct rtl8169_private *tp = netdev_priv(dev);
6328
6329         phy_stop(tp->phydev);
6330
6331         napi_disable(&tp->napi);
6332         netif_stop_queue(dev);
6333
6334         rtl8169_hw_reset(tp);
6335         /*
6336          * At this point device interrupts can not be enabled in any function,
6337          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6338          * and napi is disabled (rtl8169_poll).
6339          */
6340         rtl8169_rx_missed(dev);
6341
6342         /* Give a racing hard_start_xmit a few cycles to complete. */
6343         synchronize_rcu();
6344
6345         rtl8169_tx_clear(tp);
6346
6347         rtl8169_rx_clear(tp);
6348
6349         rtl_pll_power_down(tp);
6350 }
6351
6352 static int rtl8169_close(struct net_device *dev)
6353 {
6354         struct rtl8169_private *tp = netdev_priv(dev);
6355         struct pci_dev *pdev = tp->pci_dev;
6356
6357         pm_runtime_get_sync(&pdev->dev);
6358
6359         /* Update counters before going down */
6360         rtl8169_update_counters(tp);
6361
6362         rtl_lock_work(tp);
6363         /* Clear all task flags */
6364         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6365
6366         rtl8169_down(dev);
6367         rtl_unlock_work(tp);
6368
6369         cancel_work_sync(&tp->wk.work);
6370
6371         phy_disconnect(tp->phydev);
6372
6373         pci_free_irq(pdev, 0, tp);
6374
6375         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6376                           tp->RxPhyAddr);
6377         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6378                           tp->TxPhyAddr);
6379         tp->TxDescArray = NULL;
6380         tp->RxDescArray = NULL;
6381
6382         pm_runtime_put_sync(&pdev->dev);
6383
6384         return 0;
6385 }
6386
6387 #ifdef CONFIG_NET_POLL_CONTROLLER
6388 static void rtl8169_netpoll(struct net_device *dev)
6389 {
6390         struct rtl8169_private *tp = netdev_priv(dev);
6391
6392         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6393 }
6394 #endif
6395
6396 static int rtl_open(struct net_device *dev)
6397 {
6398         struct rtl8169_private *tp = netdev_priv(dev);
6399         struct pci_dev *pdev = tp->pci_dev;
6400         int retval = -ENOMEM;
6401
6402         pm_runtime_get_sync(&pdev->dev);
6403
6404         /*
6405          * Rx and Tx descriptors needs 256 bytes alignment.
6406          * dma_alloc_coherent provides more.
6407          */
6408         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6409                                              &tp->TxPhyAddr, GFP_KERNEL);
6410         if (!tp->TxDescArray)
6411                 goto err_pm_runtime_put;
6412
6413         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6414                                              &tp->RxPhyAddr, GFP_KERNEL);
6415         if (!tp->RxDescArray)
6416                 goto err_free_tx_0;
6417
6418         retval = rtl8169_init_ring(tp);
6419         if (retval < 0)
6420                 goto err_free_rx_1;
6421
6422         rtl_request_firmware(tp);
6423
6424         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6425                                  dev->name);
6426         if (retval < 0)
6427                 goto err_release_fw_2;
6428
6429         retval = r8169_phy_connect(tp);
6430         if (retval)
6431                 goto err_free_irq;
6432
6433         rtl_lock_work(tp);
6434
6435         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6436
6437         napi_enable(&tp->napi);
6438
6439         rtl8169_init_phy(dev, tp);
6440
6441         rtl_pll_power_up(tp);
6442
6443         rtl_hw_start(tp);
6444
6445         if (!rtl8169_init_counter_offsets(tp))
6446                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6447
6448         phy_start(tp->phydev);
6449         netif_start_queue(dev);
6450
6451         rtl_unlock_work(tp);
6452
6453         pm_runtime_put_sync(&pdev->dev);
6454 out:
6455         return retval;
6456
6457 err_free_irq:
6458         pci_free_irq(pdev, 0, tp);
6459 err_release_fw_2:
6460         rtl_release_firmware(tp);
6461         rtl8169_rx_clear(tp);
6462 err_free_rx_1:
6463         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6464                           tp->RxPhyAddr);
6465         tp->RxDescArray = NULL;
6466 err_free_tx_0:
6467         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6468                           tp->TxPhyAddr);
6469         tp->TxDescArray = NULL;
6470 err_pm_runtime_put:
6471         pm_runtime_put_noidle(&pdev->dev);
6472         goto out;
6473 }
6474
6475 static void
6476 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6477 {
6478         struct rtl8169_private *tp = netdev_priv(dev);
6479         struct pci_dev *pdev = tp->pci_dev;
6480         struct rtl8169_counters *counters = tp->counters;
6481         unsigned int start;
6482
6483         pm_runtime_get_noresume(&pdev->dev);
6484
6485         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6486                 rtl8169_rx_missed(dev);
6487
6488         do {
6489                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6490                 stats->rx_packets = tp->rx_stats.packets;
6491                 stats->rx_bytes = tp->rx_stats.bytes;
6492         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6493
6494         do {
6495                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6496                 stats->tx_packets = tp->tx_stats.packets;
6497                 stats->tx_bytes = tp->tx_stats.bytes;
6498         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6499
6500         stats->rx_dropped       = dev->stats.rx_dropped;
6501         stats->tx_dropped       = dev->stats.tx_dropped;
6502         stats->rx_length_errors = dev->stats.rx_length_errors;
6503         stats->rx_errors        = dev->stats.rx_errors;
6504         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6505         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6506         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6507         stats->multicast        = dev->stats.multicast;
6508
6509         /*
6510          * Fetch additonal counter values missing in stats collected by driver
6511          * from tally counters.
6512          */
6513         if (pm_runtime_active(&pdev->dev))
6514                 rtl8169_update_counters(tp);
6515
6516         /*
6517          * Subtract values fetched during initalization.
6518          * See rtl8169_init_counter_offsets for a description why we do that.
6519          */
6520         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6521                 le64_to_cpu(tp->tc_offset.tx_errors);
6522         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6523                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6524         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6525                 le16_to_cpu(tp->tc_offset.tx_aborted);
6526
6527         pm_runtime_put_noidle(&pdev->dev);
6528 }
6529
6530 static void rtl8169_net_suspend(struct net_device *dev)
6531 {
6532         struct rtl8169_private *tp = netdev_priv(dev);
6533
6534         if (!netif_running(dev))
6535                 return;
6536
6537         phy_stop(tp->phydev);
6538         netif_device_detach(dev);
6539
6540         rtl_lock_work(tp);
6541         napi_disable(&tp->napi);
6542         /* Clear all task flags */
6543         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6544
6545         rtl_unlock_work(tp);
6546
6547         rtl_pll_power_down(tp);
6548 }
6549
6550 #ifdef CONFIG_PM
6551
6552 static int rtl8169_suspend(struct device *device)
6553 {
6554         struct net_device *dev = dev_get_drvdata(device);
6555         struct rtl8169_private *tp = netdev_priv(dev);
6556
6557         rtl8169_net_suspend(dev);
6558         clk_disable_unprepare(tp->clk);
6559
6560         return 0;
6561 }
6562
6563 static void __rtl8169_resume(struct net_device *dev)
6564 {
6565         struct rtl8169_private *tp = netdev_priv(dev);
6566
6567         netif_device_attach(dev);
6568
6569         rtl_pll_power_up(tp);
6570         rtl8169_init_phy(dev, tp);
6571
6572         phy_start(tp->phydev);
6573
6574         rtl_lock_work(tp);
6575         napi_enable(&tp->napi);
6576         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6577         rtl_reset_work(tp);
6578         rtl_unlock_work(tp);
6579 }
6580
6581 static int rtl8169_resume(struct device *device)
6582 {
6583         struct net_device *dev = dev_get_drvdata(device);
6584         struct rtl8169_private *tp = netdev_priv(dev);
6585
6586         rtl_rar_set(tp, dev->dev_addr);
6587
6588         clk_prepare_enable(tp->clk);
6589
6590         if (netif_running(dev))
6591                 __rtl8169_resume(dev);
6592
6593         return 0;
6594 }
6595
6596 static int rtl8169_runtime_suspend(struct device *device)
6597 {
6598         struct net_device *dev = dev_get_drvdata(device);
6599         struct rtl8169_private *tp = netdev_priv(dev);
6600
6601         if (!tp->TxDescArray)
6602                 return 0;
6603
6604         rtl_lock_work(tp);
6605         __rtl8169_set_wol(tp, WAKE_ANY);
6606         rtl_unlock_work(tp);
6607
6608         rtl8169_net_suspend(dev);
6609
6610         /* Update counters before going runtime suspend */
6611         rtl8169_rx_missed(dev);
6612         rtl8169_update_counters(tp);
6613
6614         return 0;
6615 }
6616
6617 static int rtl8169_runtime_resume(struct device *device)
6618 {
6619         struct net_device *dev = dev_get_drvdata(device);
6620         struct rtl8169_private *tp = netdev_priv(dev);
6621
6622         rtl_rar_set(tp, dev->dev_addr);
6623
6624         if (!tp->TxDescArray)
6625                 return 0;
6626
6627         rtl_lock_work(tp);
6628         __rtl8169_set_wol(tp, tp->saved_wolopts);
6629         rtl_unlock_work(tp);
6630
6631         __rtl8169_resume(dev);
6632
6633         return 0;
6634 }
6635
6636 static int rtl8169_runtime_idle(struct device *device)
6637 {
6638         struct net_device *dev = dev_get_drvdata(device);
6639
6640         if (!netif_running(dev) || !netif_carrier_ok(dev))
6641                 pm_schedule_suspend(device, 10000);
6642
6643         return -EBUSY;
6644 }
6645
6646 static const struct dev_pm_ops rtl8169_pm_ops = {
6647         .suspend                = rtl8169_suspend,
6648         .resume                 = rtl8169_resume,
6649         .freeze                 = rtl8169_suspend,
6650         .thaw                   = rtl8169_resume,
6651         .poweroff               = rtl8169_suspend,
6652         .restore                = rtl8169_resume,
6653         .runtime_suspend        = rtl8169_runtime_suspend,
6654         .runtime_resume         = rtl8169_runtime_resume,
6655         .runtime_idle           = rtl8169_runtime_idle,
6656 };
6657
6658 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6659
6660 #else /* !CONFIG_PM */
6661
6662 #define RTL8169_PM_OPS  NULL
6663
6664 #endif /* !CONFIG_PM */
6665
6666 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6667 {
6668         /* WoL fails with 8168b when the receiver is disabled. */
6669         switch (tp->mac_version) {
6670         case RTL_GIGA_MAC_VER_11:
6671         case RTL_GIGA_MAC_VER_12:
6672         case RTL_GIGA_MAC_VER_17:
6673                 pci_clear_master(tp->pci_dev);
6674
6675                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6676                 /* PCI commit */
6677                 RTL_R8(tp, ChipCmd);
6678                 break;
6679         default:
6680                 break;
6681         }
6682 }
6683
6684 static void rtl_shutdown(struct pci_dev *pdev)
6685 {
6686         struct net_device *dev = pci_get_drvdata(pdev);
6687         struct rtl8169_private *tp = netdev_priv(dev);
6688
6689         rtl8169_net_suspend(dev);
6690
6691         /* Restore original MAC address */
6692         rtl_rar_set(tp, dev->perm_addr);
6693
6694         rtl8169_hw_reset(tp);
6695
6696         if (system_state == SYSTEM_POWER_OFF) {
6697                 if (tp->saved_wolopts) {
6698                         rtl_wol_suspend_quirk(tp);
6699                         rtl_wol_shutdown_quirk(tp);
6700                 }
6701
6702                 pci_wake_from_d3(pdev, true);
6703                 pci_set_power_state(pdev, PCI_D3hot);
6704         }
6705 }
6706
6707 static void rtl_remove_one(struct pci_dev *pdev)
6708 {
6709         struct net_device *dev = pci_get_drvdata(pdev);
6710         struct rtl8169_private *tp = netdev_priv(dev);
6711
6712         if (r8168_check_dash(tp))
6713                 rtl8168_driver_stop(tp);
6714
6715         netif_napi_del(&tp->napi);
6716
6717         unregister_netdev(dev);
6718         mdiobus_unregister(tp->phydev->mdio.bus);
6719
6720         rtl_release_firmware(tp);
6721
6722         if (pci_dev_run_wake(pdev))
6723                 pm_runtime_get_noresume(&pdev->dev);
6724
6725         /* restore original MAC address */
6726         rtl_rar_set(tp, dev->perm_addr);
6727 }
6728
6729 static const struct net_device_ops rtl_netdev_ops = {
6730         .ndo_open               = rtl_open,
6731         .ndo_stop               = rtl8169_close,
6732         .ndo_get_stats64        = rtl8169_get_stats64,
6733         .ndo_start_xmit         = rtl8169_start_xmit,
6734         .ndo_tx_timeout         = rtl8169_tx_timeout,
6735         .ndo_validate_addr      = eth_validate_addr,
6736         .ndo_change_mtu         = rtl8169_change_mtu,
6737         .ndo_fix_features       = rtl8169_fix_features,
6738         .ndo_set_features       = rtl8169_set_features,
6739         .ndo_set_mac_address    = rtl_set_mac_address,
6740         .ndo_do_ioctl           = rtl8169_ioctl,
6741         .ndo_set_rx_mode        = rtl_set_rx_mode,
6742 #ifdef CONFIG_NET_POLL_CONTROLLER
6743         .ndo_poll_controller    = rtl8169_netpoll,
6744 #endif
6745
6746 };
6747
6748 static const struct rtl_cfg_info {
6749         void (*hw_start)(struct rtl8169_private *tp);
6750         u16 irq_mask;
6751         unsigned int has_gmii:1;
6752         const struct rtl_coalesce_info *coalesce_info;
6753 } rtl_cfg_infos [] = {
6754         [RTL_CFG_0] = {
6755                 .hw_start       = rtl_hw_start_8169,
6756                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6757                 .has_gmii       = 1,
6758                 .coalesce_info  = rtl_coalesce_info_8169,
6759         },
6760         [RTL_CFG_1] = {
6761                 .hw_start       = rtl_hw_start_8168,
6762                 .irq_mask       = LinkChg | RxOverflow,
6763                 .has_gmii       = 1,
6764                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6765         },
6766         [RTL_CFG_2] = {
6767                 .hw_start       = rtl_hw_start_8101,
6768                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6769                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6770         }
6771 };
6772
6773 static int rtl_alloc_irq(struct rtl8169_private *tp)
6774 {
6775         unsigned int flags;
6776
6777         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6778                 rtl_unlock_config_regs(tp);
6779                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6780                 rtl_lock_config_regs(tp);
6781                 flags = PCI_IRQ_LEGACY;
6782         } else {
6783                 flags = PCI_IRQ_ALL_TYPES;
6784         }
6785
6786         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6787 }
6788
6789 static void rtl_read_mac_address(struct rtl8169_private *tp,
6790                                  u8 mac_addr[ETH_ALEN])
6791 {
6792         u32 value;
6793
6794         /* Get MAC address */
6795         switch (tp->mac_version) {
6796         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6797         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6798                 value = rtl_eri_read(tp, 0xe0);
6799                 mac_addr[0] = (value >>  0) & 0xff;
6800                 mac_addr[1] = (value >>  8) & 0xff;
6801                 mac_addr[2] = (value >> 16) & 0xff;
6802                 mac_addr[3] = (value >> 24) & 0xff;
6803
6804                 value = rtl_eri_read(tp, 0xe4);
6805                 mac_addr[4] = (value >>  0) & 0xff;
6806                 mac_addr[5] = (value >>  8) & 0xff;
6807                 break;
6808         default:
6809                 break;
6810         }
6811 }
6812
6813 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6814 {
6815         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6816 }
6817
6818 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6819 {
6820         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6821 }
6822
6823 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6824 {
6825         struct rtl8169_private *tp = mii_bus->priv;
6826
6827         if (phyaddr > 0)
6828                 return -ENODEV;
6829
6830         return rtl_readphy(tp, phyreg);
6831 }
6832
6833 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6834                                 int phyreg, u16 val)
6835 {
6836         struct rtl8169_private *tp = mii_bus->priv;
6837
6838         if (phyaddr > 0)
6839                 return -ENODEV;
6840
6841         rtl_writephy(tp, phyreg, val);
6842
6843         return 0;
6844 }
6845
6846 static int r8169_mdio_register(struct rtl8169_private *tp)
6847 {
6848         struct pci_dev *pdev = tp->pci_dev;
6849         struct mii_bus *new_bus;
6850         int ret;
6851
6852         new_bus = devm_mdiobus_alloc(&pdev->dev);
6853         if (!new_bus)
6854                 return -ENOMEM;
6855
6856         new_bus->name = "r8169";
6857         new_bus->priv = tp;
6858         new_bus->parent = &pdev->dev;
6859         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6860         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6861
6862         new_bus->read = r8169_mdio_read_reg;
6863         new_bus->write = r8169_mdio_write_reg;
6864
6865         ret = mdiobus_register(new_bus);
6866         if (ret)
6867                 return ret;
6868
6869         tp->phydev = mdiobus_get_phy(new_bus, 0);
6870         if (!tp->phydev) {
6871                 mdiobus_unregister(new_bus);
6872                 return -ENODEV;
6873         }
6874
6875         /* PHY will be woken up in rtl_open() */
6876         phy_suspend(tp->phydev);
6877
6878         return 0;
6879 }
6880
6881 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6882 {
6883         u32 data;
6884
6885         tp->ocp_base = OCP_STD_PHY_BASE;
6886
6887         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6888
6889         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6890                 return;
6891
6892         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6893                 return;
6894
6895         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6896         msleep(1);
6897         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6898
6899         data = r8168_mac_ocp_read(tp, 0xe8de);
6900         data &= ~(1 << 14);
6901         r8168_mac_ocp_write(tp, 0xe8de, data);
6902
6903         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6904                 return;
6905
6906         data = r8168_mac_ocp_read(tp, 0xe8de);
6907         data |= (1 << 15);
6908         r8168_mac_ocp_write(tp, 0xe8de, data);
6909
6910         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6911 }
6912
6913 static void rtl_hw_initialize(struct rtl8169_private *tp)
6914 {
6915         switch (tp->mac_version) {
6916         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6917                 rtl8168ep_stop_cmac(tp);
6918                 /* fall through */
6919         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6920                 rtl_hw_init_8168g(tp);
6921                 break;
6922         default:
6923                 break;
6924         }
6925 }
6926
6927 static int rtl_jumbo_max(struct rtl8169_private *tp)
6928 {
6929         /* Non-GBit versions don't support jumbo frames */
6930         if (!tp->supports_gmii)
6931                 return JUMBO_1K;
6932
6933         switch (tp->mac_version) {
6934         /* RTL8169 */
6935         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6936                 return JUMBO_7K;
6937         /* RTL8168b */
6938         case RTL_GIGA_MAC_VER_11:
6939         case RTL_GIGA_MAC_VER_12:
6940         case RTL_GIGA_MAC_VER_17:
6941                 return JUMBO_4K;
6942         /* RTL8168c */
6943         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6944                 return JUMBO_6K;
6945         default:
6946                 return JUMBO_9K;
6947         }
6948 }
6949
6950 static void rtl_disable_clk(void *data)
6951 {
6952         clk_disable_unprepare(data);
6953 }
6954
6955 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6956 {
6957         struct device *d = tp_to_dev(tp);
6958         struct clk *clk;
6959         int rc;
6960
6961         clk = devm_clk_get(d, "ether_clk");
6962         if (IS_ERR(clk)) {
6963                 rc = PTR_ERR(clk);
6964                 if (rc == -ENOENT)
6965                         /* clk-core allows NULL (for suspend / resume) */
6966                         rc = 0;
6967                 else if (rc != -EPROBE_DEFER)
6968                         dev_err(d, "failed to get clk: %d\n", rc);
6969         } else {
6970                 tp->clk = clk;
6971                 rc = clk_prepare_enable(clk);
6972                 if (rc)
6973                         dev_err(d, "failed to enable clk: %d\n", rc);
6974                 else
6975                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6976         }
6977
6978         return rc;
6979 }
6980
6981 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6982 {
6983         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6984         /* align to u16 for is_valid_ether_addr() */
6985         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6986         struct rtl8169_private *tp;
6987         struct net_device *dev;
6988         int chipset, region, i;
6989         int jumbo_max, rc;
6990
6991         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6992         if (!dev)
6993                 return -ENOMEM;
6994
6995         SET_NETDEV_DEV(dev, &pdev->dev);
6996         dev->netdev_ops = &rtl_netdev_ops;
6997         tp = netdev_priv(dev);
6998         tp->dev = dev;
6999         tp->pci_dev = pdev;
7000         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7001         tp->supports_gmii = cfg->has_gmii;
7002
7003         /* Get the *optional* external "ether_clk" used on some boards */
7004         rc = rtl_get_ether_clk(tp);
7005         if (rc)
7006                 return rc;
7007
7008         /* Disable ASPM completely as that cause random device stop working
7009          * problems as well as full system hangs for some PCIe devices users.
7010          */
7011         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7012
7013         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7014         rc = pcim_enable_device(pdev);
7015         if (rc < 0) {
7016                 dev_err(&pdev->dev, "enable failure\n");
7017                 return rc;
7018         }
7019
7020         if (pcim_set_mwi(pdev) < 0)
7021                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7022
7023         /* use first MMIO region */
7024         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7025         if (region < 0) {
7026                 dev_err(&pdev->dev, "no MMIO resource found\n");
7027                 return -ENODEV;
7028         }
7029
7030         /* check for weird/broken PCI region reporting */
7031         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7032                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7033                 return -ENODEV;
7034         }
7035
7036         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7037         if (rc < 0) {
7038                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7039                 return rc;
7040         }
7041
7042         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7043
7044         /* Identify chip attached to board */
7045         rtl8169_get_mac_version(tp);
7046         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7047                 return -ENODEV;
7048
7049         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7050
7051         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7052             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7053                 dev->features |= NETIF_F_HIGHDMA;
7054         } else {
7055                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7056                 if (rc < 0) {
7057                         dev_err(&pdev->dev, "DMA configuration failed\n");
7058                         return rc;
7059                 }
7060         }
7061
7062         rtl_init_rxcfg(tp);
7063
7064         rtl8169_irq_mask_and_ack(tp);
7065
7066         rtl_hw_initialize(tp);
7067
7068         rtl_hw_reset(tp);
7069
7070         pci_set_master(pdev);
7071
7072         chipset = tp->mac_version;
7073
7074         rc = rtl_alloc_irq(tp);
7075         if (rc < 0) {
7076                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7077                 return rc;
7078         }
7079
7080         mutex_init(&tp->wk.mutex);
7081         INIT_WORK(&tp->wk.work, rtl_task);
7082         u64_stats_init(&tp->rx_stats.syncp);
7083         u64_stats_init(&tp->tx_stats.syncp);
7084
7085         /* get MAC address */
7086         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7087         if (rc)
7088                 rtl_read_mac_address(tp, mac_addr);
7089
7090         if (is_valid_ether_addr(mac_addr))
7091                 rtl_rar_set(tp, mac_addr);
7092
7093         for (i = 0; i < ETH_ALEN; i++)
7094                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7095
7096         dev->ethtool_ops = &rtl8169_ethtool_ops;
7097
7098         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7099
7100         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7101          * properly for all devices */
7102         dev->features |= NETIF_F_RXCSUM |
7103                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7104
7105         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7106                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7107                 NETIF_F_HW_VLAN_CTAG_RX;
7108         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7109                 NETIF_F_HIGHDMA;
7110         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7111
7112         tp->cp_cmd |= RxChkSum | RxVlan;
7113
7114         /*
7115          * Pretend we are using VLANs; This bypasses a nasty bug where
7116          * Interrupts stop flowing on high load on 8110SCd controllers.
7117          */
7118         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7119                 /* Disallow toggling */
7120                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7121
7122         if (rtl_chip_supports_csum_v2(tp))
7123                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7124
7125         dev->hw_features |= NETIF_F_RXALL;
7126         dev->hw_features |= NETIF_F_RXFCS;
7127
7128         /* MTU range: 60 - hw-specific max */
7129         dev->min_mtu = ETH_ZLEN;
7130         jumbo_max = rtl_jumbo_max(tp);
7131         dev->max_mtu = jumbo_max;
7132
7133         tp->hw_start = cfg->hw_start;
7134         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7135         tp->coalesce_info = cfg->coalesce_info;
7136
7137         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7138
7139         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7140                                             &tp->counters_phys_addr,
7141                                             GFP_KERNEL);
7142         if (!tp->counters)
7143                 return -ENOMEM;
7144
7145         pci_set_drvdata(pdev, dev);
7146
7147         rc = r8169_mdio_register(tp);
7148         if (rc)
7149                 return rc;
7150
7151         /* chip gets powered up in rtl_open() */
7152         rtl_pll_power_down(tp);
7153
7154         rc = register_netdev(dev);
7155         if (rc)
7156                 goto err_mdio_unregister;
7157
7158         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7159                    rtl_chip_infos[chipset].name, dev->dev_addr,
7160                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7161                    pci_irq_vector(pdev, 0));
7162
7163         if (jumbo_max > JUMBO_1K)
7164                 netif_info(tp, probe, dev,
7165                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7166                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7167                            "ok" : "ko");
7168
7169         if (r8168_check_dash(tp))
7170                 rtl8168_driver_start(tp);
7171
7172         if (pci_dev_run_wake(pdev))
7173                 pm_runtime_put_sync(&pdev->dev);
7174
7175         return 0;
7176
7177 err_mdio_unregister:
7178         mdiobus_unregister(tp->phydev->mdio.bus);
7179         return rc;
7180 }
7181
7182 static struct pci_driver rtl8169_pci_driver = {
7183         .name           = MODULENAME,
7184         .id_table       = rtl8169_pci_tbl,
7185         .probe          = rtl_init_one,
7186         .remove         = rtl_remove_one,
7187         .shutdown       = rtl_shutdown,
7188         .driver.pm      = RTL8169_PM_OPS,
7189 };
7190
7191 module_pci_driver(rtl8169_pci_driver);