drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_BUFFS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  76
  77 #define R8169_REGS_SIZE         256
  78 #define R8169_NAPI_WEIGHT       64
  79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  84
  85 #define RTL8169_TX_TIMEOUT      (6*HZ)
  86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  87
  88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  90 #define RTL_EEPROM_SIG_ADDR     0x0000
  91
  92 /* write/read MMIO register */
  93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  96 #define RTL_R8(reg)             readb (ioaddr + (reg))
  97 #define RTL_R16(reg)            readw (ioaddr + (reg))
  98 #define RTL_R32(reg)            readl (ioaddr + (reg))
  99
 100 enum mac_version {
 101         RTL_GIGA_MAC_VER_01 = 0,
 102         RTL_GIGA_MAC_VER_02,
 103         RTL_GIGA_MAC_VER_03,
 104         RTL_GIGA_MAC_VER_04,
 105         RTL_GIGA_MAC_VER_05,
 106         RTL_GIGA_MAC_VER_06,
 107         RTL_GIGA_MAC_VER_07,
 108         RTL_GIGA_MAC_VER_08,
 109         RTL_GIGA_MAC_VER_09,
 110         RTL_GIGA_MAC_VER_10,
 111         RTL_GIGA_MAC_VER_11,
 112         RTL_GIGA_MAC_VER_12,
 113         RTL_GIGA_MAC_VER_13,
 114         RTL_GIGA_MAC_VER_14,
 115         RTL_GIGA_MAC_VER_15,
 116         RTL_GIGA_MAC_VER_16,
 117         RTL_GIGA_MAC_VER_17,
 118         RTL_GIGA_MAC_VER_18,
 119         RTL_GIGA_MAC_VER_19,
 120         RTL_GIGA_MAC_VER_20,
 121         RTL_GIGA_MAC_VER_21,
 122         RTL_GIGA_MAC_VER_22,
 123         RTL_GIGA_MAC_VER_23,
 124         RTL_GIGA_MAC_VER_24,
 125         RTL_GIGA_MAC_VER_25,
 126         RTL_GIGA_MAC_VER_26,
 127         RTL_GIGA_MAC_VER_27,
 128         RTL_GIGA_MAC_VER_28,
 129         RTL_GIGA_MAC_VER_29,
 130         RTL_GIGA_MAC_VER_30,
 131         RTL_GIGA_MAC_VER_31,
 132         RTL_GIGA_MAC_VER_32,
 133         RTL_GIGA_MAC_VER_33,
 134         RTL_GIGA_MAC_VER_34,
 135         RTL_GIGA_MAC_VER_35,
 136         RTL_GIGA_MAC_VER_36,
 137         RTL_GIGA_MAC_NONE   = 0xff,
 138 };
 139
 140 enum rtl_tx_desc_version {
 141         RTL_TD_0        = 0,
 142         RTL_TD_1        = 1,
 143 };
 144
 145 #define JUMBO_1K        ETH_DATA_LEN
 146 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 147 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 148 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 149 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 150
 151 #define _R(NAME,TD,FW,SZ,B) {   \
 152         .name = NAME,           \
 153         .txd_version = TD,      \
 154         .fw_name = FW,          \
 155         .jumbo_max = SZ,        \
 156         .jumbo_tx_csum = B      \
 157 }
 158
 159 static const struct {
 160         const char *name;
 161         enum rtl_tx_desc_version txd_version;
 162         const char *fw_name;
 163         u16 jumbo_max;
 164         bool jumbo_tx_csum;
 165 } rtl_chip_infos[] = {
 166         /* PCI devices. */
 167         [RTL_GIGA_MAC_VER_01] =
 168                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 169         [RTL_GIGA_MAC_VER_02] =
 170                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_03] =
 172                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_04] =
 174                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_05] =
 176                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_06] =
 178                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 179         /* PCI-E devices. */
 180         [RTL_GIGA_MAC_VER_07] =
 181                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 182         [RTL_GIGA_MAC_VER_08] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_09] =
 185                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_10] =
 187                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_11] =
 189                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 190         [RTL_GIGA_MAC_VER_12] =
 191                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 192         [RTL_GIGA_MAC_VER_13] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_14] =
 195                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_15] =
 197                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_16] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_17] =
 201                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_18] =
 203                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 204         [RTL_GIGA_MAC_VER_19] =
 205                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_20] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_21] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_22] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_23] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_24] =
 215                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_25] =
 217                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 218                                                         JUMBO_9K, false),
 219         [RTL_GIGA_MAC_VER_26] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_27] =
 223                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_28] =
 225                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_29] =
 227                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 228                                                         JUMBO_1K, true),
 229         [RTL_GIGA_MAC_VER_30] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_31] =
 233                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_32] =
 235                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 236                                                         JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_33] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_34] =
 241                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_35] =
 244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_36] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 248                                                         JUMBO_9K, false),
 249 };
 250 #undef _R
 251
 252 enum cfg_version {
 253         RTL_CFG_0 = 0x00,
 254         RTL_CFG_1,
 255         RTL_CFG_2
 256 };
 257
 258 static void rtl_hw_start_8169(struct net_device *);
 259 static void rtl_hw_start_8168(struct net_device *);
 260 static void rtl_hw_start_8101(struct net_device *);
 261
 262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 272         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 273                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 274         { 0x0001,                               0x8168,
 275                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 276         {0,},
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 280
 281 static int rx_buf_sz = 16383;
 282 static int use_dac;
 283 static struct {
 284         u32 msg_enable;
 285 } debug = { -1 };
 286
 287 enum rtl_registers {
 288         MAC0            = 0,    /* Ethernet hardware address. */
 289         MAC4            = 4,
 290         MAR0            = 8,    /* Multicast filter. */
 291         CounterAddrLow          = 0x10,
 292         CounterAddrHigh         = 0x14,
 293         TxDescStartAddrLow      = 0x20,
 294         TxDescStartAddrHigh     = 0x24,
 295         TxHDescStartAddrLow     = 0x28,
 296         TxHDescStartAddrHigh    = 0x2c,
 297         FLASH           = 0x30,
 298         ERSR            = 0x36,
 299         ChipCmd         = 0x37,
 300         TxPoll          = 0x38,
 301         IntrMask        = 0x3c,
 302         IntrStatus      = 0x3e,
 303
 304         TxConfig        = 0x40,
 305 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 306 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 307
 308         RxConfig        = 0x44,
 309 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 310 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 311 #define RXCFG_FIFO_SHIFT                13
 312                                         /* No threshold before first PCI xfer */
 313 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 314 #define RXCFG_DMA_SHIFT                 8
 315                                         /* Unlimited maximum PCI burst. */
 316 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 317
 318         RxMissed        = 0x4c,
 319         Cfg9346         = 0x50,
 320         Config0         = 0x51,
 321         Config1         = 0x52,
 322         Config2         = 0x53,
 323         Config3         = 0x54,
 324         Config4         = 0x55,
 325         Config5         = 0x56,
 326         MultiIntr       = 0x5c,
 327         PHYAR           = 0x60,
 328         PHYstatus       = 0x6c,
 329         RxMaxSize       = 0xda,
 330         CPlusCmd        = 0xe0,
 331         IntrMitigate    = 0xe2,
 332         RxDescAddrLow   = 0xe4,
 333         RxDescAddrHigh  = 0xe8,
 334         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 335
 336 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 337
 338         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 339
 340 #define TxPacketMax     (8064 >> 7)
 341 #define EarlySize       0x27
 342
 343         FuncEvent       = 0xf0,
 344         FuncEventMask   = 0xf4,
 345         FuncPresetState = 0xf8,
 346         FuncForceEvent  = 0xfc,
 347 };
 348
 349 enum rtl8110_registers {
 350         TBICSR                  = 0x64,
 351         TBI_ANAR                = 0x68,
 352         TBI_LPAR                = 0x6a,
 353 };
 354
 355 enum rtl8168_8101_registers {
 356         CSIDR                   = 0x64,
 357         CSIAR                   = 0x68,
 358 #define CSIAR_FLAG                      0x80000000
 359 #define CSIAR_WRITE_CMD                 0x80000000
 360 #define CSIAR_BYTE_ENABLE               0x0f
 361 #define CSIAR_BYTE_ENABLE_SHIFT         12
 362 #define CSIAR_ADDR_MASK                 0x0fff
 363         PMCH                    = 0x6f,
 364         EPHYAR                  = 0x80,
 365 #define EPHYAR_FLAG                     0x80000000
 366 #define EPHYAR_WRITE_CMD                0x80000000
 367 #define EPHYAR_REG_MASK                 0x1f
 368 #define EPHYAR_REG_SHIFT                16
 369 #define EPHYAR_DATA_MASK                0xffff
 370         DLLPR                   = 0xd0,
 371 #define PFM_EN                          (1 << 6)
 372         DBG_REG                 = 0xd1,
 373 #define FIX_NAK_1                       (1 << 4)
 374 #define FIX_NAK_2                       (1 << 3)
 375         TWSI                    = 0xd2,
 376         MCU                     = 0xd3,
 377 #define NOW_IS_OOB                      (1 << 7)
 378 #define EN_NDP                          (1 << 3)
 379 #define EN_OOB_RESET                    (1 << 2)
 380         EFUSEAR                 = 0xdc,
 381 #define EFUSEAR_FLAG                    0x80000000
 382 #define EFUSEAR_WRITE_CMD               0x80000000
 383 #define EFUSEAR_READ_CMD                0x00000000
 384 #define EFUSEAR_REG_MASK                0x03ff
 385 #define EFUSEAR_REG_SHIFT               8
 386 #define EFUSEAR_DATA_MASK               0xff
 387 };
 388
 389 enum rtl8168_registers {
 390         LED_FREQ                = 0x1a,
 391         EEE_LED                 = 0x1b,
 392         ERIDR                   = 0x70,
 393         ERIAR                   = 0x74,
 394 #define ERIAR_FLAG                      0x80000000
 395 #define ERIAR_WRITE_CMD                 0x80000000
 396 #define ERIAR_READ_CMD                  0x00000000
 397 #define ERIAR_ADDR_BYTE_ALIGN           4
 398 #define ERIAR_TYPE_SHIFT                16
 399 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 402 #define ERIAR_MASK_SHIFT                12
 403 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 405 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 406         EPHY_RXER_NUM           = 0x7c,
 407         OCPDR                   = 0xb0, /* OCP GPHY access */
 408 #define OCPDR_WRITE_CMD                 0x80000000
 409 #define OCPDR_READ_CMD                  0x00000000
 410 #define OCPDR_REG_MASK                  0x7f
 411 #define OCPDR_GPHY_REG_SHIFT            16
 412 #define OCPDR_DATA_MASK                 0xffff
 413         OCPAR                   = 0xb4,
 414 #define OCPAR_FLAG                      0x80000000
 415 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 416 #define OCPAR_GPHY_READ_CMD             0x0000f060
 417         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 418         MISC                    = 0xf0, /* 8168e only. */
 419 #define TXPLA_RST                       (1 << 29)
 420 #define PWM_EN                          (1 << 22)
 421 };
 422
 423 enum rtl_register_content {
 424         /* InterruptStatusBits */
 425         SYSErr          = 0x8000,
 426         PCSTimeout      = 0x4000,
 427         SWInt           = 0x0100,
 428         TxDescUnavail   = 0x0080,
 429         RxFIFOOver      = 0x0040,
 430         LinkChg         = 0x0020,
 431         RxOverflow      = 0x0010,
 432         TxErr           = 0x0008,
 433         TxOK            = 0x0004,
 434         RxErr           = 0x0002,
 435         RxOK            = 0x0001,
 436
 437         /* RxStatusDesc */
 438         RxBOVF  = (1 << 24),
 439         RxFOVF  = (1 << 23),
 440         RxRWT   = (1 << 22),
 441         RxRES   = (1 << 21),
 442         RxRUNT  = (1 << 20),
 443         RxCRC   = (1 << 19),
 444
 445         /* ChipCmdBits */
 446         StopReq         = 0x80,
 447         CmdReset        = 0x10,
 448         CmdRxEnb        = 0x08,
 449         CmdTxEnb        = 0x04,
 450         RxBufEmpty      = 0x01,
 451
 452         /* TXPoll register p.5 */
 453         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 454         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 455         FSWInt          = 0x01,         /* Forced software interrupt */
 456
 457         /* Cfg9346Bits */
 458         Cfg9346_Lock    = 0x00,
 459         Cfg9346_Unlock  = 0xc0,
 460
 461         /* rx_mode_bits */
 462         AcceptErr       = 0x20,
 463         AcceptRunt      = 0x10,
 464         AcceptBroadcast = 0x08,
 465         AcceptMulticast = 0x04,
 466         AcceptMyPhys    = 0x02,
 467         AcceptAllPhys   = 0x01,
 468 #define RX_CONFIG_ACCEPT_MASK           0x3f
 469
 470         /* TxConfigBits */
 471         TxInterFrameGapShift = 24,
 472         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 473
 474         /* Config1 register p.24 */
 475         LEDS1           = (1 << 7),
 476         LEDS0           = (1 << 6),
 477         Speed_down      = (1 << 4),
 478         MEMMAP          = (1 << 3),
 479         IOMAP           = (1 << 2),
 480         VPD             = (1 << 1),
 481         PMEnable        = (1 << 0),     /* Power Management Enable */
 482
 483         /* Config2 register p. 25 */
 484         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 485         PCI_Clock_66MHz = 0x01,
 486         PCI_Clock_33MHz = 0x00,
 487
 488         /* Config3 register p.25 */
 489         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 490         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 491         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 492         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 493
 494         /* Config4 register */
 495         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 496
 497         /* Config5 register p.27 */
 498         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 499         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 500         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 501         Spi_en          = (1 << 3),
 502         LanWake         = (1 << 1),     /* LanWake enable/disable */
 503         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 504
 505         /* TBICSR p.28 */
 506         TBIReset        = 0x80000000,
 507         TBILoopback     = 0x40000000,
 508         TBINwEnable     = 0x20000000,
 509         TBINwRestart    = 0x10000000,
 510         TBILinkOk       = 0x02000000,
 511         TBINwComplete   = 0x01000000,
 512
 513         /* CPlusCmd p.31 */
 514         EnableBist      = (1 << 15),    // 8168 8101
 515         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 516         Normal_mode     = (1 << 13),    // unused
 517         Force_half_dup  = (1 << 12),    // 8168 8101
 518         Force_rxflow_en = (1 << 11),    // 8168 8101
 519         Force_txflow_en = (1 << 10),    // 8168 8101
 520         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 521         ASF             = (1 << 8),     // 8168 8101
 522         PktCntrDisable  = (1 << 7),     // 8168 8101
 523         Mac_dbgo_sel    = 0x001c,       // 8168
 524         RxVlan          = (1 << 6),
 525         RxChkSum        = (1 << 5),
 526         PCIDAC          = (1 << 4),
 527         PCIMulRW        = (1 << 3),
 528         INTT_0          = 0x0000,       // 8168
 529         INTT_1          = 0x0001,       // 8168
 530         INTT_2          = 0x0002,       // 8168
 531         INTT_3          = 0x0003,       // 8168
 532
 533         /* rtl8169_PHYstatus */
 534         TBI_Enable      = 0x80,
 535         TxFlowCtrl      = 0x40,
 536         RxFlowCtrl      = 0x20,
 537         _1000bpsF       = 0x10,
 538         _100bps         = 0x08,
 539         _10bps          = 0x04,
 540         LinkStatus      = 0x02,
 541         FullDup         = 0x01,
 542
 543         /* _TBICSRBit */
 544         TBILinkOK       = 0x02000000,
 545
 546         /* DumpCounterCommand */
 547         CounterDump     = 0x8,
 548 };
 549
 550 enum rtl_desc_bit {
 551         /* First doubleword. */
 552         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 553         RingEnd         = (1 << 30), /* End of descriptor ring */
 554         FirstFrag       = (1 << 29), /* First segment of a packet */
 555         LastFrag        = (1 << 28), /* Final segment of a packet */
 556 };
 557
 558 /* Generic case. */
 559 enum rtl_tx_desc_bit {
 560         /* First doubleword. */
 561         TD_LSO          = (1 << 27),            /* Large Send Offload */
 562 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 563
 564         /* Second doubleword. */
 565         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 566 };
 567
 568 /* 8169, 8168b and 810x except 8102e. */
 569 enum rtl_tx_desc_bit_0 {
 570         /* First doubleword. */
 571 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 572         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 573         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 574         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 575 };
 576
 577 /* 8102e, 8168c and beyond. */
 578 enum rtl_tx_desc_bit_1 {
 579         /* Second doubleword. */
 580 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 581         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 582         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 583         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 584 };
 585
 586 static const struct rtl_tx_desc_info {
 587         struct {
 588                 u32 udp;
 589                 u32 tcp;
 590         } checksum;
 591         u16 mss_shift;
 592         u16 opts_offset;
 593 } tx_desc_info [] = {
 594         [RTL_TD_0] = {
 595                 .checksum = {
 596                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 597                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 598                 },
 599                 .mss_shift      = TD0_MSS_SHIFT,
 600                 .opts_offset    = 0
 601         },
 602         [RTL_TD_1] = {
 603                 .checksum = {
 604                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 605                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 606                 },
 607                 .mss_shift      = TD1_MSS_SHIFT,
 608                 .opts_offset    = 1
 609         }
 610 };
 611
 612 enum rtl_rx_desc_bit {
 613         /* Rx private */
 614         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 615         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 616
 617 #define RxProtoUDP      (PID1)
 618 #define RxProtoTCP      (PID0)
 619 #define RxProtoIP       (PID1 | PID0)
 620 #define RxProtoMask     RxProtoIP
 621
 622         IPFail          = (1 << 16), /* IP checksum failed */
 623         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 624         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 625         RxVlanTag       = (1 << 16), /* VLAN tag available */
 626 };
 627
 628 #define RsvdMask        0x3fffc000
 629
 630 struct TxDesc {
 631         __le32 opts1;
 632         __le32 opts2;
 633         __le64 addr;
 634 };
 635
 636 struct RxDesc {
 637         __le32 opts1;
 638         __le32 opts2;
 639         __le64 addr;
 640 };
 641
 642 struct ring_info {
 643         struct sk_buff  *skb;
 644         u32             len;
 645         u8              __pad[sizeof(void *) - sizeof(u32)];
 646 };
 647
 648 enum features {
 649         RTL_FEATURE_WOL         = (1 << 0),
 650         RTL_FEATURE_MSI         = (1 << 1),
 651         RTL_FEATURE_GMII        = (1 << 2),
 652 };
 653
 654 struct rtl8169_counters {
 655         __le64  tx_packets;
 656         __le64  rx_packets;
 657         __le64  tx_errors;
 658         __le32  rx_errors;
 659         __le16  rx_missed;
 660         __le16  align_errors;
 661         __le32  tx_one_collision;
 662         __le32  tx_multi_collision;
 663         __le64  rx_unicast;
 664         __le64  rx_broadcast;
 665         __le32  rx_multicast;
 666         __le16  tx_aborted;
 667         __le16  tx_underun;
 668 };
 669
 670 enum rtl_flag {
 671         RTL_FLAG_TASK_ENABLED,
 672         RTL_FLAG_TASK_SLOW_PENDING,
 673         RTL_FLAG_TASK_RESET_PENDING,
 674         RTL_FLAG_TASK_PHY_PENDING,
 675         RTL_FLAG_MAX
 676 };
 677
 678 struct rtl8169_private {
 679         void __iomem *mmio_addr;        /* memory map physical address */
 680         struct pci_dev *pci_dev;
 681         struct net_device *dev;
 682         struct napi_struct napi;
 683         u32 msg_enable;
 684         u16 txd_version;
 685         u16 mac_version;
 686         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 687         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 688         u32 dirty_rx;
 689         u32 dirty_tx;
 690         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 691         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 692         dma_addr_t TxPhyAddr;
 693         dma_addr_t RxPhyAddr;
 694         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 695         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 696         struct timer_list timer;
 697         u16 cp_cmd;
 698
 699         u16 event_slow;
 700
 701         struct mdio_ops {
 702                 void (*write)(void __iomem *, int, int);
 703                 int (*read)(void __iomem *, int);
 704         } mdio_ops;
 705
 706         struct pll_power_ops {
 707                 void (*down)(struct rtl8169_private *);
 708                 void (*up)(struct rtl8169_private *);
 709         } pll_power_ops;
 710
 711         struct jumbo_ops {
 712                 void (*enable)(struct rtl8169_private *);
 713                 void (*disable)(struct rtl8169_private *);
 714         } jumbo_ops;
 715
 716         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 717         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 718         void (*phy_reset_enable)(struct rtl8169_private *tp);
 719         void (*hw_start)(struct net_device *);
 720         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 721         unsigned int (*link_ok)(void __iomem *);
 722         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 723
 724         struct {
 725                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 726                 struct mutex mutex;
 727                 struct work_struct work;
 728         } wk;
 729
 730         unsigned features;
 731
 732         struct mii_if_info mii;
 733         struct rtl8169_counters counters;
 734         u32 saved_wolopts;
 735         u32 opts1_mask;
 736
 737         struct rtl_fw {
 738                 const struct firmware *fw;
 739
 740 #define RTL_VER_SIZE            32
 741
 742                 char version[RTL_VER_SIZE];
 743
 744                 struct rtl_fw_phy_action {
 745                         __le32 *code;
 746                         size_t size;
 747                 } phy_action;
 748         } *rtl_fw;
 749 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 750 };
 751
 752 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 753 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 754 module_param(use_dac, int, 0);
 755 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 756 module_param_named(debug, debug.msg_enable, int, 0);
 757 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 758 MODULE_LICENSE("GPL");
 759 MODULE_VERSION(RTL8169_VERSION);
 760 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 761 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 762 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 763 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 764 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 765 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 766 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 767 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 768
 769 static int rtl8169_open(struct net_device *dev);
 770 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 771                                       struct net_device *dev);
 772 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 773 static int rtl8169_init_ring(struct net_device *dev);
 774 static void rtl_hw_start(struct net_device *dev);
 775 static int rtl8169_close(struct net_device *dev);
 776 static void rtl_set_rx_mode(struct net_device *dev);
 777 static void rtl8169_tx_timeout(struct net_device *dev);
 778 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 779 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 780 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 781 static int rtl8169_poll(struct napi_struct *napi, int budget);
 782
 783 static void rtl_lock_work(struct rtl8169_private *tp)
 784 {
 785         mutex_lock(&tp->wk.mutex);
 786 }
 787
 788 static void rtl_unlock_work(struct rtl8169_private *tp)
 789 {
 790         mutex_unlock(&tp->wk.mutex);
 791 }
 792
 793 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 794 {
 795         int cap = pci_pcie_cap(pdev);
 796
 797         if (cap) {
 798                 u16 ctl;
 799
 800                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 801                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 802                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 803         }
 804 }
 805
 806 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 807 {
 808         void __iomem *ioaddr = tp->mmio_addr;
 809         int i;
 810
 811         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 812         for (i = 0; i < 20; i++) {
 813                 udelay(100);
 814                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 815                         break;
 816         }
 817         return RTL_R32(OCPDR);
 818 }
 819
 820 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 821 {
 822         void __iomem *ioaddr = tp->mmio_addr;
 823         int i;
 824
 825         RTL_W32(OCPDR, data);
 826         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 827         for (i = 0; i < 20; i++) {
 828                 udelay(100);
 829                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 830                         break;
 831         }
 832 }
 833
 834 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 835 {
 836         void __iomem *ioaddr = tp->mmio_addr;
 837         int i;
 838
 839         RTL_W8(ERIDR, cmd);
 840         RTL_W32(ERIAR, 0x800010e8);
 841         msleep(2);
 842         for (i = 0; i < 5; i++) {
 843                 udelay(100);
 844                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 845                         break;
 846         }
 847
 848         ocp_write(tp, 0x1, 0x30, 0x00000001);
 849 }
 850
 851 #define OOB_CMD_RESET           0x00
 852 #define OOB_CMD_DRIVER_START    0x05
 853 #define OOB_CMD_DRIVER_STOP     0x06
 854
 855 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 856 {
 857         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 858 }
 859
 860 static void rtl8168_driver_start(struct rtl8169_private *tp)
 861 {
 862         u16 reg;
 863         int i;
 864
 865         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 866
 867         reg = rtl8168_get_ocp_reg(tp);
 868
 869         for (i = 0; i < 10; i++) {
 870                 msleep(10);
 871                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 872                         break;
 873         }
 874 }
 875
 876 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 877 {
 878         u16 reg;
 879         int i;
 880
 881         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 882
 883         reg = rtl8168_get_ocp_reg(tp);
 884
 885         for (i = 0; i < 10; i++) {
 886                 msleep(10);
 887                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 888                         break;
 889         }
 890 }
 891
 892 static int r8168dp_check_dash(struct rtl8169_private *tp)
 893 {
 894         u16 reg = rtl8168_get_ocp_reg(tp);
 895
 896         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 897 }
 898
 899 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 900 {
 901         int i;
 902
 903         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 904
 905         for (i = 20; i > 0; i--) {
 906                 /*
 907                  * Check if the RTL8169 has completed writing to the specified
 908                  * MII register.
 909                  */
 910                 if (!(RTL_R32(PHYAR) & 0x80000000))
 911                         break;
 912                 udelay(25);
 913         }
 914         /*
 915          * According to hardware specs a 20us delay is required after write
 916          * complete indication, but before sending next command.
 917          */
 918         udelay(20);
 919 }
 920
 921 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 922 {
 923         int i, value = -1;
 924
 925         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 926
 927         for (i = 20; i > 0; i--) {
 928                 /*
 929                  * Check if the RTL8169 has completed retrieving data from
 930                  * the specified MII register.
 931                  */
 932                 if (RTL_R32(PHYAR) & 0x80000000) {
 933                         value = RTL_R32(PHYAR) & 0xffff;
 934                         break;
 935                 }
 936                 udelay(25);
 937         }
 938         /*
 939          * According to hardware specs a 20us delay is required after read
 940          * complete indication, but before sending next command.
 941          */
 942         udelay(20);
 943
 944         return value;
 945 }
 946
 947 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 948 {
 949         int i;
 950
 951         RTL_W32(OCPDR, data |
 952                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 953         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 954         RTL_W32(EPHY_RXER_NUM, 0);
 955
 956         for (i = 0; i < 100; i++) {
 957                 mdelay(1);
 958                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 959                         break;
 960         }
 961 }
 962
 963 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 964 {
 965         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 966                 (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 970 {
 971         int i;
 972
 973         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(EPHY_RXER_NUM, 0);
 978
 979         for (i = 0; i < 100; i++) {
 980                 mdelay(1);
 981                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 982                         break;
 983         }
 984
 985         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 986 }
 987
 988 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 989
 990 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 991 {
 992         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 996 {
 997         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 998 }
 999
1000 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1001 {
1002         r8168dp_2_mdio_start(ioaddr);
1003
1004         r8169_mdio_write(ioaddr, reg_addr, value);
1005
1006         r8168dp_2_mdio_stop(ioaddr);
1007 }
1008
1009 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1010 {
1011         int value;
1012
1013         r8168dp_2_mdio_start(ioaddr);
1014
1015         value = r8169_mdio_read(ioaddr, reg_addr);
1016
1017         r8168dp_2_mdio_stop(ioaddr);
1018
1019         return value;
1020 }
1021
1022 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1023 {
1024         tp->mdio_ops.write(tp->mmio_addr, location, val);
1025 }
1026
1027 static int rtl_readphy(struct rtl8169_private *tp, int location)
1028 {
1029         return tp->mdio_ops.read(tp->mmio_addr, location);
1030 }
1031
1032 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1033 {
1034         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035 }
1036
1037 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1038 {
1039         int val;
1040
1041         val = rtl_readphy(tp, reg_addr);
1042         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1043 }
1044
1045 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1046                            int val)
1047 {
1048         struct rtl8169_private *tp = netdev_priv(dev);
1049
1050         rtl_writephy(tp, location, val);
1051 }
1052
1053 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1054 {
1055         struct rtl8169_private *tp = netdev_priv(dev);
1056
1057         return rtl_readphy(tp, location);
1058 }
1059
1060 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1061 {
1062         unsigned int i;
1063
1064         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1065                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1066
1067         for (i = 0; i < 100; i++) {
1068                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1069                         break;
1070                 udelay(10);
1071         }
1072 }
1073
1074 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1075 {
1076         u16 value = 0xffff;
1077         unsigned int i;
1078
1079         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1080
1081         for (i = 0; i < 100; i++) {
1082                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1083                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1084                         break;
1085                 }
1086                 udelay(10);
1087         }
1088
1089         return value;
1090 }
1091
1092 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1093 {
1094         unsigned int i;
1095
1096         RTL_W32(CSIDR, value);
1097         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1098                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099
1100         for (i = 0; i < 100; i++) {
1101                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1102                         break;
1103                 udelay(10);
1104         }
1105 }
1106
1107 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1108 {
1109         u32 value = ~0x00;
1110         unsigned int i;
1111
1112         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1113                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1114
1115         for (i = 0; i < 100; i++) {
1116                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1117                         value = RTL_R32(CSIDR);
1118                         break;
1119                 }
1120                 udelay(10);
1121         }
1122
1123         return value;
1124 }
1125
1126 static
1127 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1128 {
1129         unsigned int i;
1130
1131         BUG_ON((addr & 3) || (mask == 0));
1132         RTL_W32(ERIDR, val);
1133         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1134
1135         for (i = 0; i < 100; i++) {
1136                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1137                         break;
1138                 udelay(100);
1139         }
1140 }
1141
1142 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1143 {
1144         u32 value = ~0x00;
1145         unsigned int i;
1146
1147         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1148
1149         for (i = 0; i < 100; i++) {
1150                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1151                         value = RTL_R32(ERIDR);
1152                         break;
1153                 }
1154                 udelay(100);
1155         }
1156
1157         return value;
1158 }
1159
1160 static void
1161 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1162 {
1163         u32 val;
1164
1165         val = rtl_eri_read(ioaddr, addr, type);
1166         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1167 }
1168
1169 struct exgmac_reg {
1170         u16 addr;
1171         u16 mask;
1172         u32 val;
1173 };
1174
1175 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1176                                    const struct exgmac_reg *r, int len)
1177 {
1178         while (len-- > 0) {
1179                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1180                 r++;
1181         }
1182 }
1183
1184 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1185 {
1186         u8 value = 0xff;
1187         unsigned int i;
1188
1189         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1190
1191         for (i = 0; i < 300; i++) {
1192                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1193                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1194                         break;
1195                 }
1196                 udelay(100);
1197         }
1198
1199         return value;
1200 }
1201
1202 static u16 rtl_get_events(struct rtl8169_private *tp)
1203 {
1204         void __iomem *ioaddr = tp->mmio_addr;
1205
1206         return RTL_R16(IntrStatus);
1207 }
1208
1209 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         RTL_W16(IntrStatus, bits);
1214         mmiowb();
1215 }
1216
1217 static void rtl_irq_disable(struct rtl8169_private *tp)
1218 {
1219         void __iomem *ioaddr = tp->mmio_addr;
1220
1221         RTL_W16(IntrMask, 0);
1222         mmiowb();
1223 }
1224
1225 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1226 {
1227         void __iomem *ioaddr = tp->mmio_addr;
1228
1229         RTL_W16(IntrMask, bits);
1230 }
1231
1232 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1233 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1234 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1235
1236 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1237 {
1238         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1239 }
1240
1241 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1242 {
1243         void __iomem *ioaddr = tp->mmio_addr;
1244
1245         rtl_irq_disable(tp);
1246         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1247         RTL_R8(ChipCmd);
1248 }
1249
1250 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1251 {
1252         void __iomem *ioaddr = tp->mmio_addr;
1253
1254         return RTL_R32(TBICSR) & TBIReset;
1255 }
1256
1257 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1258 {
1259         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1260 }
1261
1262 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1263 {
1264         return RTL_R32(TBICSR) & TBILinkOk;
1265 }
1266
1267 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1268 {
1269         return RTL_R8(PHYstatus) & LinkStatus;
1270 }
1271
1272 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1277 }
1278
1279 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1280 {
1281         unsigned int val;
1282
1283         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1284         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1285 }
1286
1287 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1288 {
1289         void __iomem *ioaddr = tp->mmio_addr;
1290         struct net_device *dev = tp->dev;
1291
1292         if (!netif_running(dev))
1293                 return;
1294
1295         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1296                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1297                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298                                       0x00000011, ERIAR_EXGMAC);
1299                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300                                       0x00000005, ERIAR_EXGMAC);
1301                 } else if (RTL_R8(PHYstatus) & _100bps) {
1302                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1303                                       0x0000001f, ERIAR_EXGMAC);
1304                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1305                                       0x00000005, ERIAR_EXGMAC);
1306                 } else {
1307                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308                                       0x0000001f, ERIAR_EXGMAC);
1309                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310                                       0x0000003f, ERIAR_EXGMAC);
1311                 }
1312                 /* Reset packet filter */
1313                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1314                              ERIAR_EXGMAC);
1315                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1316                              ERIAR_EXGMAC);
1317         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1318                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1319                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1320                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1321                                       0x00000011, ERIAR_EXGMAC);
1322                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1323                                       0x00000005, ERIAR_EXGMAC);
1324                 } else {
1325                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1326                                       0x0000001f, ERIAR_EXGMAC);
1327                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1328                                       0x0000003f, ERIAR_EXGMAC);
1329                 }
1330         }
1331 }
1332
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334                                         struct rtl8169_private *tp,
1335                                         void __iomem *ioaddr, bool pm)
1336 {
1337         if (tp->link_ok(ioaddr)) {
1338                 rtl_link_chg_patch(tp);
1339                 /* This is to cancel a scheduled suspend if there's one. */
1340                 if (pm)
1341                         pm_request_resume(&tp->pci_dev->dev);
1342                 netif_carrier_on(dev);
1343                 if (net_ratelimit())
1344                         netif_info(tp, ifup, dev, "link up\n");
1345         } else {
1346                 netif_carrier_off(dev);
1347                 netif_info(tp, ifdown, dev, "link down\n");
1348                 if (pm)
1349                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1350         }
1351 }
1352
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354                                       struct rtl8169_private *tp,
1355                                       void __iomem *ioaddr)
1356 {
1357         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358 }
1359
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365         u8 options;
1366         u32 wolopts = 0;
1367
1368         options = RTL_R8(Config1);
1369         if (!(options & PMEnable))
1370                 return 0;
1371
1372         options = RTL_R8(Config3);
1373         if (options & LinkUp)
1374                 wolopts |= WAKE_PHY;
1375         if (options & MagicPacket)
1376                 wolopts |= WAKE_MAGIC;
1377
1378         options = RTL_R8(Config5);
1379         if (options & UWF)
1380                 wolopts |= WAKE_UCAST;
1381         if (options & BWF)
1382                 wolopts |= WAKE_BCAST;
1383         if (options & MWF)
1384                 wolopts |= WAKE_MCAST;
1385
1386         return wolopts;
1387 }
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394
1395         wol->supported = WAKE_ANY;
1396         wol->wolopts = __rtl8169_get_wol(tp);
1397
1398         rtl_unlock_work(tp);
1399 }
1400
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404         unsigned int i;
1405         static const struct {
1406                 u32 opt;
1407                 u16 reg;
1408                 u8  mask;
1409         } cfg[] = {
1410                 { WAKE_ANY,   Config1, PMEnable },
1411                 { WAKE_PHY,   Config3, LinkUp },
1412                 { WAKE_MAGIC, Config3, MagicPacket },
1413                 { WAKE_UCAST, Config5, UWF },
1414                 { WAKE_BCAST, Config5, BWF },
1415                 { WAKE_MCAST, Config5, MWF },
1416                 { WAKE_ANY,   Config5, LanWake }
1417         };
1418
1419         RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(cfg[i].reg, options);
1426         }
1427
1428         RTL_W8(Cfg9346, Cfg9346_Lock);
1429 }
1430
1431 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1432 {
1433         struct rtl8169_private *tp = netdev_priv(dev);
1434
1435         rtl_lock_work(tp);
1436
1437         if (wol->wolopts)
1438                 tp->features |= RTL_FEATURE_WOL;
1439         else
1440                 tp->features &= ~RTL_FEATURE_WOL;
1441         __rtl8169_set_wol(tp, wol->wolopts);
1442
1443         rtl_unlock_work(tp);
1444
1445         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1446
1447         return 0;
1448 }
1449
1450 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1451 {
1452         return rtl_chip_infos[tp->mac_version].fw_name;
1453 }
1454
1455 static void rtl8169_get_drvinfo(struct net_device *dev,
1456                                 struct ethtool_drvinfo *info)
1457 {
1458         struct rtl8169_private *tp = netdev_priv(dev);
1459         struct rtl_fw *rtl_fw = tp->rtl_fw;
1460
1461         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1462         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1463         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1464         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1465         if (!IS_ERR_OR_NULL(rtl_fw))
1466                 strlcpy(info->fw_version, rtl_fw->version,
1467                         sizeof(info->fw_version));
1468 }
1469
1470 static int rtl8169_get_regs_len(struct net_device *dev)
1471 {
1472         return R8169_REGS_SIZE;
1473 }
1474
1475 static int rtl8169_set_speed_tbi(struct net_device *dev,
1476                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         void __iomem *ioaddr = tp->mmio_addr;
1480         int ret = 0;
1481         u32 reg;
1482
1483         reg = RTL_R32(TBICSR);
1484         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1485             (duplex == DUPLEX_FULL)) {
1486                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1487         } else if (autoneg == AUTONEG_ENABLE)
1488                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1489         else {
1490                 netif_warn(tp, link, dev,
1491                            "incorrect speed setting refused in TBI mode\n");
1492                 ret = -EOPNOTSUPP;
1493         }
1494
1495         return ret;
1496 }
1497
1498 static int rtl8169_set_speed_xmii(struct net_device *dev,
1499                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1500 {
1501         struct rtl8169_private *tp = netdev_priv(dev);
1502         int giga_ctrl, bmcr;
1503         int rc = -EINVAL;
1504
1505         rtl_writephy(tp, 0x1f, 0x0000);
1506
1507         if (autoneg == AUTONEG_ENABLE) {
1508                 int auto_nego;
1509
1510                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1511                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1512                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1513
1514                 if (adv & ADVERTISED_10baseT_Half)
1515                         auto_nego |= ADVERTISE_10HALF;
1516                 if (adv & ADVERTISED_10baseT_Full)
1517                         auto_nego |= ADVERTISE_10FULL;
1518                 if (adv & ADVERTISED_100baseT_Half)
1519                         auto_nego |= ADVERTISE_100HALF;
1520                 if (adv & ADVERTISED_100baseT_Full)
1521                         auto_nego |= ADVERTISE_100FULL;
1522
1523                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1524
1525                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1526                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1527
1528                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1529                 if (tp->mii.supports_gmii) {
1530                         if (adv & ADVERTISED_1000baseT_Half)
1531                                 giga_ctrl |= ADVERTISE_1000HALF;
1532                         if (adv & ADVERTISED_1000baseT_Full)
1533                                 giga_ctrl |= ADVERTISE_1000FULL;
1534                 } else if (adv & (ADVERTISED_1000baseT_Half |
1535                                   ADVERTISED_1000baseT_Full)) {
1536                         netif_info(tp, link, dev,
1537                                    "PHY does not support 1000Mbps\n");
1538                         goto out;
1539                 }
1540
1541                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1542
1543                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1544                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1545         } else {
1546                 giga_ctrl = 0;
1547
1548                 if (speed == SPEED_10)
1549                         bmcr = 0;
1550                 else if (speed == SPEED_100)
1551                         bmcr = BMCR_SPEED100;
1552                 else
1553                         goto out;
1554
1555                 if (duplex == DUPLEX_FULL)
1556                         bmcr |= BMCR_FULLDPLX;
1557         }
1558
1559         rtl_writephy(tp, MII_BMCR, bmcr);
1560
1561         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1562             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1563                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1564                         rtl_writephy(tp, 0x17, 0x2138);
1565                         rtl_writephy(tp, 0x0e, 0x0260);
1566                 } else {
1567                         rtl_writephy(tp, 0x17, 0x2108);
1568                         rtl_writephy(tp, 0x0e, 0x0000);
1569                 }
1570         }
1571
1572         rc = 0;
1573 out:
1574         return rc;
1575 }
1576
1577 static int rtl8169_set_speed(struct net_device *dev,
1578                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581         int ret;
1582
1583         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1584         if (ret < 0)
1585                 goto out;
1586
1587         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1588             (advertising & ADVERTISED_1000baseT_Full)) {
1589                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1590         }
1591 out:
1592         return ret;
1593 }
1594
1595 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1596 {
1597         struct rtl8169_private *tp = netdev_priv(dev);
1598         int ret;
1599
1600         del_timer_sync(&tp->timer);
1601
1602         rtl_lock_work(tp);
1603         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1604                                 cmd->duplex, cmd->advertising);
1605         rtl_unlock_work(tp);
1606
1607         return ret;
1608 }
1609
1610 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1611         netdev_features_t features)
1612 {
1613         struct rtl8169_private *tp = netdev_priv(dev);
1614
1615         if (dev->mtu > TD_MSS_MAX)
1616                 features &= ~NETIF_F_ALL_TSO;
1617
1618         if (dev->mtu > JUMBO_1K &&
1619             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1620                 features &= ~NETIF_F_IP_CSUM;
1621
1622         return features;
1623 }
1624
1625 static void __rtl8169_set_features(struct net_device *dev,
1626                                    netdev_features_t features)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629         netdev_features_t changed = features ^ dev->features;
1630         void __iomem *ioaddr = tp->mmio_addr;
1631
1632         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1633                 return;
1634
1635         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1636                 if (features & NETIF_F_RXCSUM)
1637                         tp->cp_cmd |= RxChkSum;
1638                 else
1639                         tp->cp_cmd &= ~RxChkSum;
1640
1641                 if (dev->features & NETIF_F_HW_VLAN_RX)
1642                         tp->cp_cmd |= RxVlan;
1643                 else
1644                         tp->cp_cmd &= ~RxVlan;
1645
1646                 RTL_W16(CPlusCmd, tp->cp_cmd);
1647                 RTL_R16(CPlusCmd);
1648         }
1649         if (changed & NETIF_F_RXALL) {
1650                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1651                 if (features & NETIF_F_RXALL)
1652                         tmp |= (AcceptErr | AcceptRunt);
1653                 RTL_W32(RxConfig, tmp);
1654         }
1655 }
1656
1657 static int rtl8169_set_features(struct net_device *dev,
1658                                 netdev_features_t features)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         rtl_lock_work(tp);
1663         __rtl8169_set_features(dev, features);
1664         rtl_unlock_work(tp);
1665
1666         return 0;
1667 }
1668
1669
1670 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1671                                       struct sk_buff *skb)
1672 {
1673         return (vlan_tx_tag_present(skb)) ?
1674                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1675 }
1676
1677 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1678 {
1679         u32 opts2 = le32_to_cpu(desc->opts2);
1680
1681         if (opts2 & RxVlanTag)
1682                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1683
1684         desc->opts2 = 0;
1685 }
1686
1687 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1688 {
1689         struct rtl8169_private *tp = netdev_priv(dev);
1690         void __iomem *ioaddr = tp->mmio_addr;
1691         u32 status;
1692
1693         cmd->supported =
1694                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1695         cmd->port = PORT_FIBRE;
1696         cmd->transceiver = XCVR_INTERNAL;
1697
1698         status = RTL_R32(TBICSR);
1699         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1700         cmd->autoneg = !!(status & TBINwEnable);
1701
1702         ethtool_cmd_speed_set(cmd, SPEED_1000);
1703         cmd->duplex = DUPLEX_FULL; /* Always set */
1704
1705         return 0;
1706 }
1707
1708 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1709 {
1710         struct rtl8169_private *tp = netdev_priv(dev);
1711
1712         return mii_ethtool_gset(&tp->mii, cmd);
1713 }
1714
1715 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         int rc;
1719
1720         rtl_lock_work(tp);
1721         rc = tp->get_settings(dev, cmd);
1722         rtl_unlock_work(tp);
1723
1724         return rc;
1725 }
1726
1727 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1728                              void *p)
1729 {
1730         struct rtl8169_private *tp = netdev_priv(dev);
1731
1732         if (regs->len > R8169_REGS_SIZE)
1733                 regs->len = R8169_REGS_SIZE;
1734
1735         rtl_lock_work(tp);
1736         memcpy_fromio(p, tp->mmio_addr, regs->len);
1737         rtl_unlock_work(tp);
1738 }
1739
1740 static u32 rtl8169_get_msglevel(struct net_device *dev)
1741 {
1742         struct rtl8169_private *tp = netdev_priv(dev);
1743
1744         return tp->msg_enable;
1745 }
1746
1747 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1748 {
1749         struct rtl8169_private *tp = netdev_priv(dev);
1750
1751         tp->msg_enable = value;
1752 }
1753
1754 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1755         "tx_packets",
1756         "rx_packets",
1757         "tx_errors",
1758         "rx_errors",
1759         "rx_missed",
1760         "align_errors",
1761         "tx_single_collisions",
1762         "tx_multi_collisions",
1763         "unicast",
1764         "broadcast",
1765         "multicast",
1766         "tx_aborted",
1767         "tx_underrun",
1768 };
1769
1770 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1771 {
1772         switch (sset) {
1773         case ETH_SS_STATS:
1774                 return ARRAY_SIZE(rtl8169_gstrings);
1775         default:
1776                 return -EOPNOTSUPP;
1777         }
1778 }
1779
1780 static void rtl8169_update_counters(struct net_device *dev)
1781 {
1782         struct rtl8169_private *tp = netdev_priv(dev);
1783         void __iomem *ioaddr = tp->mmio_addr;
1784         struct device *d = &tp->pci_dev->dev;
1785         struct rtl8169_counters *counters;
1786         dma_addr_t paddr;
1787         u32 cmd;
1788         int wait = 1000;
1789
1790         /*
1791          * Some chips are unable to dump tally counters when the receiver
1792          * is disabled.
1793          */
1794         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1795                 return;
1796
1797         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1798         if (!counters)
1799                 return;
1800
1801         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1802         cmd = (u64)paddr & DMA_BIT_MASK(32);
1803         RTL_W32(CounterAddrLow, cmd);
1804         RTL_W32(CounterAddrLow, cmd | CounterDump);
1805
1806         while (wait--) {
1807                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1808                         memcpy(&tp->counters, counters, sizeof(*counters));
1809                         break;
1810                 }
1811                 udelay(10);
1812         }
1813
1814         RTL_W32(CounterAddrLow, 0);
1815         RTL_W32(CounterAddrHigh, 0);
1816
1817         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1818 }
1819
1820 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1821                                       struct ethtool_stats *stats, u64 *data)
1822 {
1823         struct rtl8169_private *tp = netdev_priv(dev);
1824
1825         ASSERT_RTNL();
1826
1827         rtl8169_update_counters(dev);
1828
1829         data[0] = le64_to_cpu(tp->counters.tx_packets);
1830         data[1] = le64_to_cpu(tp->counters.rx_packets);
1831         data[2] = le64_to_cpu(tp->counters.tx_errors);
1832         data[3] = le32_to_cpu(tp->counters.rx_errors);
1833         data[4] = le16_to_cpu(tp->counters.rx_missed);
1834         data[5] = le16_to_cpu(tp->counters.align_errors);
1835         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1836         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1837         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1838         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1839         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1840         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1841         data[12] = le16_to_cpu(tp->counters.tx_underun);
1842 }
1843
1844 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1845 {
1846         switch(stringset) {
1847         case ETH_SS_STATS:
1848                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1849                 break;
1850         }
1851 }
1852
1853 static const struct ethtool_ops rtl8169_ethtool_ops = {
1854         .get_drvinfo            = rtl8169_get_drvinfo,
1855         .get_regs_len           = rtl8169_get_regs_len,
1856         .get_link               = ethtool_op_get_link,
1857         .get_settings           = rtl8169_get_settings,
1858         .set_settings           = rtl8169_set_settings,
1859         .get_msglevel           = rtl8169_get_msglevel,
1860         .set_msglevel           = rtl8169_set_msglevel,
1861         .get_regs               = rtl8169_get_regs,
1862         .get_wol                = rtl8169_get_wol,
1863         .set_wol                = rtl8169_set_wol,
1864         .get_strings            = rtl8169_get_strings,
1865         .get_sset_count         = rtl8169_get_sset_count,
1866         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1867 };
1868
1869 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1870                                     struct net_device *dev, u8 default_version)
1871 {
1872         void __iomem *ioaddr = tp->mmio_addr;
1873         /*
1874          * The driver currently handles the 8168Bf and the 8168Be identically
1875          * but they can be identified more specifically through the test below
1876          * if needed:
1877          *
1878          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1879          *
1880          * Same thing for the 8101Eb and the 8101Ec:
1881          *
1882          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1883          */
1884         static const struct rtl_mac_info {
1885                 u32 mask;
1886                 u32 val;
1887                 int mac_version;
1888         } mac_info[] = {
1889                 /* 8168F family. */
1890                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1891                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1892
1893                 /* 8168E family. */
1894                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1895                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1896                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1897                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1898
1899                 /* 8168D family. */
1900                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1901                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1902                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1903
1904                 /* 8168DP family. */
1905                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1906                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1907                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1908
1909                 /* 8168C family. */
1910                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1911                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1912                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1913                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1914                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1915                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1916                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1917                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1918                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1919
1920                 /* 8168B family. */
1921                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1922                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1923                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1924                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1925
1926                 /* 8101 family. */
1927                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1928                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1929                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1930                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1931                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1932                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1933                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1934                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1935                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1936                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1937                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1938                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1939                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1940                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1941                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1942                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1943                 /* FIXME: where did these entries come from ? -- FR */
1944                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1945                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1946
1947                 /* 8110 family. */
1948                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1949                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1950                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1951                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1952                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1953                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1954
1955                 /* Catch-all */
1956                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1957         };
1958         const struct rtl_mac_info *p = mac_info;
1959         u32 reg;
1960
1961         reg = RTL_R32(TxConfig);
1962         while ((reg & p->mask) != p->val)
1963                 p++;
1964         tp->mac_version = p->mac_version;
1965
1966         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1967                 netif_notice(tp, probe, dev,
1968                              "unknown MAC, using family default\n");
1969                 tp->mac_version = default_version;
1970         }
1971 }
1972
1973 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1974 {
1975         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1976 }
1977
1978 struct phy_reg {
1979         u16 reg;
1980         u16 val;
1981 };
1982
1983 static void rtl_writephy_batch(struct rtl8169_private *tp,
1984                                const struct phy_reg *regs, int len)
1985 {
1986         while (len-- > 0) {
1987                 rtl_writephy(tp, regs->reg, regs->val);
1988                 regs++;
1989         }
1990 }
1991
1992 #define PHY_READ                0x00000000
1993 #define PHY_DATA_OR             0x10000000
1994 #define PHY_DATA_AND            0x20000000
1995 #define PHY_BJMPN               0x30000000
1996 #define PHY_READ_EFUSE          0x40000000
1997 #define PHY_READ_MAC_BYTE       0x50000000
1998 #define PHY_WRITE_MAC_BYTE      0x60000000
1999 #define PHY_CLEAR_READCOUNT     0x70000000
2000 #define PHY_WRITE               0x80000000
2001 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2002 #define PHY_COMP_EQ_SKIPN       0xa0000000
2003 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2004 #define PHY_WRITE_PREVIOUS      0xc0000000
2005 #define PHY_SKIPN               0xd0000000
2006 #define PHY_DELAY_MS            0xe0000000
2007 #define PHY_WRITE_ERI_WORD      0xf0000000
2008
2009 struct fw_info {
2010         u32     magic;
2011         char    version[RTL_VER_SIZE];
2012         __le32  fw_start;
2013         __le32  fw_len;
2014         u8      chksum;
2015 } __packed;
2016
2017 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2018
2019 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2020 {
2021         const struct firmware *fw = rtl_fw->fw;
2022         struct fw_info *fw_info = (struct fw_info *)fw->data;
2023         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2024         char *version = rtl_fw->version;
2025         bool rc = false;
2026
2027         if (fw->size < FW_OPCODE_SIZE)
2028                 goto out;
2029
2030         if (!fw_info->magic) {
2031                 size_t i, size, start;
2032                 u8 checksum = 0;
2033
2034                 if (fw->size < sizeof(*fw_info))
2035                         goto out;
2036
2037                 for (i = 0; i < fw->size; i++)
2038                         checksum += fw->data[i];
2039                 if (checksum != 0)
2040                         goto out;
2041
2042                 start = le32_to_cpu(fw_info->fw_start);
2043                 if (start > fw->size)
2044                         goto out;
2045
2046                 size = le32_to_cpu(fw_info->fw_len);
2047                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2048                         goto out;
2049
2050                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2051
2052                 pa->code = (__le32 *)(fw->data + start);
2053                 pa->size = size;
2054         } else {
2055                 if (fw->size % FW_OPCODE_SIZE)
2056                         goto out;
2057
2058                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2059
2060                 pa->code = (__le32 *)fw->data;
2061                 pa->size = fw->size / FW_OPCODE_SIZE;
2062         }
2063         version[RTL_VER_SIZE - 1] = 0;
2064
2065         rc = true;
2066 out:
2067         return rc;
2068 }
2069
2070 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2071                            struct rtl_fw_phy_action *pa)
2072 {
2073         bool rc = false;
2074         size_t index;
2075
2076         for (index = 0; index < pa->size; index++) {
2077                 u32 action = le32_to_cpu(pa->code[index]);
2078                 u32 regno = (action & 0x0fff0000) >> 16;
2079
2080                 switch(action & 0xf0000000) {
2081                 case PHY_READ:
2082                 case PHY_DATA_OR:
2083                 case PHY_DATA_AND:
2084                 case PHY_READ_EFUSE:
2085                 case PHY_CLEAR_READCOUNT:
2086                 case PHY_WRITE:
2087                 case PHY_WRITE_PREVIOUS:
2088                 case PHY_DELAY_MS:
2089                         break;
2090
2091                 case PHY_BJMPN:
2092                         if (regno > index) {
2093                                 netif_err(tp, ifup, tp->dev,
2094                                           "Out of range of firmware\n");
2095                                 goto out;
2096                         }
2097                         break;
2098                 case PHY_READCOUNT_EQ_SKIP:
2099                         if (index + 2 >= pa->size) {
2100                                 netif_err(tp, ifup, tp->dev,
2101                                           "Out of range of firmware\n");
2102                                 goto out;
2103                         }
2104                         break;
2105                 case PHY_COMP_EQ_SKIPN:
2106                 case PHY_COMP_NEQ_SKIPN:
2107                 case PHY_SKIPN:
2108                         if (index + 1 + regno >= pa->size) {
2109                                 netif_err(tp, ifup, tp->dev,
2110                                           "Out of range of firmware\n");
2111                                 goto out;
2112                         }
2113                         break;
2114
2115                 case PHY_READ_MAC_BYTE:
2116                 case PHY_WRITE_MAC_BYTE:
2117                 case PHY_WRITE_ERI_WORD:
2118                 default:
2119                         netif_err(tp, ifup, tp->dev,
2120                                   "Invalid action 0x%08x\n", action);
2121                         goto out;
2122                 }
2123         }
2124         rc = true;
2125 out:
2126         return rc;
2127 }
2128
2129 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2130 {
2131         struct net_device *dev = tp->dev;
2132         int rc = -EINVAL;
2133
2134         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2135                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2136                 goto out;
2137         }
2138
2139         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2140                 rc = 0;
2141 out:
2142         return rc;
2143 }
2144
2145 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2146 {
2147         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2148         u32 predata, count;
2149         size_t index;
2150
2151         predata = count = 0;
2152
2153         for (index = 0; index < pa->size; ) {
2154                 u32 action = le32_to_cpu(pa->code[index]);
2155                 u32 data = action & 0x0000ffff;
2156                 u32 regno = (action & 0x0fff0000) >> 16;
2157
2158                 if (!action)
2159                         break;
2160
2161                 switch(action & 0xf0000000) {
2162                 case PHY_READ:
2163                         predata = rtl_readphy(tp, regno);
2164                         count++;
2165                         index++;
2166                         break;
2167                 case PHY_DATA_OR:
2168                         predata |= data;
2169                         index++;
2170                         break;
2171                 case PHY_DATA_AND:
2172                         predata &= data;
2173                         index++;
2174                         break;
2175                 case PHY_BJMPN:
2176                         index -= regno;
2177                         break;
2178                 case PHY_READ_EFUSE:
2179                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2180                         index++;
2181                         break;
2182                 case PHY_CLEAR_READCOUNT:
2183                         count = 0;
2184                         index++;
2185                         break;
2186                 case PHY_WRITE:
2187                         rtl_writephy(tp, regno, data);
2188                         index++;
2189                         break;
2190                 case PHY_READCOUNT_EQ_SKIP:
2191                         index += (count == data) ? 2 : 1;
2192                         break;
2193                 case PHY_COMP_EQ_SKIPN:
2194                         if (predata == data)
2195                                 index += regno;
2196                         index++;
2197                         break;
2198                 case PHY_COMP_NEQ_SKIPN:
2199                         if (predata != data)
2200                                 index += regno;
2201                         index++;
2202                         break;
2203                 case PHY_WRITE_PREVIOUS:
2204                         rtl_writephy(tp, regno, predata);
2205                         index++;
2206                         break;
2207                 case PHY_SKIPN:
2208                         index += regno + 1;
2209                         break;
2210                 case PHY_DELAY_MS:
2211                         mdelay(data);
2212                         index++;
2213                         break;
2214
2215                 case PHY_READ_MAC_BYTE:
2216                 case PHY_WRITE_MAC_BYTE:
2217                 case PHY_WRITE_ERI_WORD:
2218                 default:
2219                         BUG();
2220                 }
2221         }
2222 }
2223
2224 static void rtl_release_firmware(struct rtl8169_private *tp)
2225 {
2226         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2227                 release_firmware(tp->rtl_fw->fw);
2228                 kfree(tp->rtl_fw);
2229         }
2230         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2231 }
2232
2233 static void rtl_apply_firmware(struct rtl8169_private *tp)
2234 {
2235         struct rtl_fw *rtl_fw = tp->rtl_fw;
2236
2237         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2238         if (!IS_ERR_OR_NULL(rtl_fw))
2239                 rtl_phy_write_fw(tp, rtl_fw);
2240 }
2241
2242 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2243 {
2244         if (rtl_readphy(tp, reg) != val)
2245                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2246         else
2247                 rtl_apply_firmware(tp);
2248 }
2249
2250 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2251 {
2252         static const struct phy_reg phy_reg_init[] = {
2253                 { 0x1f, 0x0001 },
2254                 { 0x06, 0x006e },
2255                 { 0x08, 0x0708 },
2256                 { 0x15, 0x4000 },
2257                 { 0x18, 0x65c7 },
2258
2259                 { 0x1f, 0x0001 },
2260                 { 0x03, 0x00a1 },
2261                 { 0x02, 0x0008 },
2262                 { 0x01, 0x0120 },
2263                 { 0x00, 0x1000 },
2264                 { 0x04, 0x0800 },
2265                 { 0x04, 0x0000 },
2266
2267                 { 0x03, 0xff41 },
2268                 { 0x02, 0xdf60 },
2269                 { 0x01, 0x0140 },
2270                 { 0x00, 0x0077 },
2271                 { 0x04, 0x7800 },
2272                 { 0x04, 0x7000 },
2273
2274                 { 0x03, 0x802f },
2275                 { 0x02, 0x4f02 },
2276                 { 0x01, 0x0409 },
2277                 { 0x00, 0xf0f9 },
2278                 { 0x04, 0x9800 },
2279                 { 0x04, 0x9000 },
2280
2281                 { 0x03, 0xdf01 },
2282                 { 0x02, 0xdf20 },
2283                 { 0x01, 0xff95 },
2284                 { 0x00, 0xba00 },
2285                 { 0x04, 0xa800 },
2286                 { 0x04, 0xa000 },
2287
2288                 { 0x03, 0xff41 },
2289                 { 0x02, 0xdf20 },
2290                 { 0x01, 0x0140 },
2291                 { 0x00, 0x00bb },
2292                 { 0x04, 0xb800 },
2293                 { 0x04, 0xb000 },
2294
2295                 { 0x03, 0xdf41 },
2296                 { 0x02, 0xdc60 },
2297                 { 0x01, 0x6340 },
2298                 { 0x00, 0x007d },
2299                 { 0x04, 0xd800 },
2300                 { 0x04, 0xd000 },
2301
2302                 { 0x03, 0xdf01 },
2303                 { 0x02, 0xdf20 },
2304                 { 0x01, 0x100a },
2305                 { 0x00, 0xa0ff },
2306                 { 0x04, 0xf800 },
2307                 { 0x04, 0xf000 },
2308
2309                 { 0x1f, 0x0000 },
2310                 { 0x0b, 0x0000 },
2311                 { 0x00, 0x9200 }
2312         };
2313
2314         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 }
2316
2317 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2318 {
2319         static const struct phy_reg phy_reg_init[] = {
2320                 { 0x1f, 0x0002 },
2321                 { 0x01, 0x90d0 },
2322                 { 0x1f, 0x0000 }
2323         };
2324
2325         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326 }
2327
2328 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2329 {
2330         struct pci_dev *pdev = tp->pci_dev;
2331
2332         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2333             (pdev->subsystem_device != 0xe000))
2334                 return;
2335
2336         rtl_writephy(tp, 0x1f, 0x0001);
2337         rtl_writephy(tp, 0x10, 0xf01b);
2338         rtl_writephy(tp, 0x1f, 0x0000);
2339 }
2340
2341 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2342 {
2343         static const struct phy_reg phy_reg_init[] = {
2344                 { 0x1f, 0x0001 },
2345                 { 0x04, 0x0000 },
2346                 { 0x03, 0x00a1 },
2347                 { 0x02, 0x0008 },
2348                 { 0x01, 0x0120 },
2349                 { 0x00, 0x1000 },
2350                 { 0x04, 0x0800 },
2351                 { 0x04, 0x9000 },
2352                 { 0x03, 0x802f },
2353                 { 0x02, 0x4f02 },
2354                 { 0x01, 0x0409 },
2355                 { 0x00, 0xf099 },
2356                 { 0x04, 0x9800 },
2357                 { 0x04, 0xa000 },
2358                 { 0x03, 0xdf01 },
2359                 { 0x02, 0xdf20 },
2360                 { 0x01, 0xff95 },
2361                 { 0x00, 0xba00 },
2362                 { 0x04, 0xa800 },
2363                 { 0x04, 0xf000 },
2364                 { 0x03, 0xdf01 },
2365                 { 0x02, 0xdf20 },
2366                 { 0x01, 0x101a },
2367                 { 0x00, 0xa0ff },
2368                 { 0x04, 0xf800 },
2369                 { 0x04, 0x0000 },
2370                 { 0x1f, 0x0000 },
2371
2372                 { 0x1f, 0x0001 },
2373                 { 0x10, 0xf41b },
2374                 { 0x14, 0xfb54 },
2375                 { 0x18, 0xf5c7 },
2376                 { 0x1f, 0x0000 },
2377
2378                 { 0x1f, 0x0001 },
2379                 { 0x17, 0x0cc0 },
2380                 { 0x1f, 0x0000 }
2381         };
2382
2383         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2384
2385         rtl8169scd_hw_phy_config_quirk(tp);
2386 }
2387
2388 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2389 {
2390         static const struct phy_reg phy_reg_init[] = {
2391                 { 0x1f, 0x0001 },
2392                 { 0x04, 0x0000 },
2393                 { 0x03, 0x00a1 },
2394                 { 0x02, 0x0008 },
2395                 { 0x01, 0x0120 },
2396                 { 0x00, 0x1000 },
2397                 { 0x04, 0x0800 },
2398                 { 0x04, 0x9000 },
2399                 { 0x03, 0x802f },
2400                 { 0x02, 0x4f02 },
2401                 { 0x01, 0x0409 },
2402                 { 0x00, 0xf099 },
2403                 { 0x04, 0x9800 },
2404                 { 0x04, 0xa000 },
2405                 { 0x03, 0xdf01 },
2406                 { 0x02, 0xdf20 },
2407                 { 0x01, 0xff95 },
2408                 { 0x00, 0xba00 },
2409                 { 0x04, 0xa800 },
2410                 { 0x04, 0xf000 },
2411                 { 0x03, 0xdf01 },
2412                 { 0x02, 0xdf20 },
2413                 { 0x01, 0x101a },
2414                 { 0x00, 0xa0ff },
2415                 { 0x04, 0xf800 },
2416                 { 0x04, 0x0000 },
2417                 { 0x1f, 0x0000 },
2418
2419                 { 0x1f, 0x0001 },
2420                 { 0x0b, 0x8480 },
2421                 { 0x1f, 0x0000 },
2422
2423                 { 0x1f, 0x0001 },
2424                 { 0x18, 0x67c7 },
2425                 { 0x04, 0x2000 },
2426                 { 0x03, 0x002f },
2427                 { 0x02, 0x4360 },
2428                 { 0x01, 0x0109 },
2429                 { 0x00, 0x3022 },
2430                 { 0x04, 0x2800 },
2431                 { 0x1f, 0x0000 },
2432
2433                 { 0x1f, 0x0001 },
2434                 { 0x17, 0x0cc0 },
2435                 { 0x1f, 0x0000 }
2436         };
2437
2438         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2439 }
2440
2441 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2442 {
2443         static const struct phy_reg phy_reg_init[] = {
2444                 { 0x10, 0xf41b },
2445                 { 0x1f, 0x0000 }
2446         };
2447
2448         rtl_writephy(tp, 0x1f, 0x0001);
2449         rtl_patchphy(tp, 0x16, 1 << 0);
2450
2451         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2452 }
2453
2454 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2455 {
2456         static const struct phy_reg phy_reg_init[] = {
2457                 { 0x1f, 0x0001 },
2458                 { 0x10, 0xf41b },
2459                 { 0x1f, 0x0000 }
2460         };
2461
2462         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2463 }
2464
2465 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2466 {
2467         static const struct phy_reg phy_reg_init[] = {
2468                 { 0x1f, 0x0000 },
2469                 { 0x1d, 0x0f00 },
2470                 { 0x1f, 0x0002 },
2471                 { 0x0c, 0x1ec8 },
2472                 { 0x1f, 0x0000 }
2473         };
2474
2475         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2476 }
2477
2478 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2479 {
2480         static const struct phy_reg phy_reg_init[] = {
2481                 { 0x1f, 0x0001 },
2482                 { 0x1d, 0x3d98 },
2483                 { 0x1f, 0x0000 }
2484         };
2485
2486         rtl_writephy(tp, 0x1f, 0x0000);
2487         rtl_patchphy(tp, 0x14, 1 << 5);
2488         rtl_patchphy(tp, 0x0d, 1 << 5);
2489
2490         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2491 }
2492
2493 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2494 {
2495         static const struct phy_reg phy_reg_init[] = {
2496                 { 0x1f, 0x0001 },
2497                 { 0x12, 0x2300 },
2498                 { 0x1f, 0x0002 },
2499                 { 0x00, 0x88d4 },
2500                 { 0x01, 0x82b1 },
2501                 { 0x03, 0x7002 },
2502                 { 0x08, 0x9e30 },
2503                 { 0x09, 0x01f0 },
2504                 { 0x0a, 0x5500 },
2505                 { 0x0c, 0x00c8 },
2506                 { 0x1f, 0x0003 },
2507                 { 0x12, 0xc096 },
2508                 { 0x16, 0x000a },
2509                 { 0x1f, 0x0000 },
2510                 { 0x1f, 0x0000 },
2511                 { 0x09, 0x2000 },
2512                 { 0x09, 0x0000 }
2513         };
2514
2515         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2516
2517         rtl_patchphy(tp, 0x14, 1 << 5);
2518         rtl_patchphy(tp, 0x0d, 1 << 5);
2519         rtl_writephy(tp, 0x1f, 0x0000);
2520 }
2521
2522 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2523 {
2524         static const struct phy_reg phy_reg_init[] = {
2525                 { 0x1f, 0x0001 },
2526                 { 0x12, 0x2300 },
2527                 { 0x03, 0x802f },
2528                 { 0x02, 0x4f02 },
2529                 { 0x01, 0x0409 },
2530                 { 0x00, 0xf099 },
2531                 { 0x04, 0x9800 },
2532                 { 0x04, 0x9000 },
2533                 { 0x1d, 0x3d98 },
2534                 { 0x1f, 0x0002 },
2535                 { 0x0c, 0x7eb8 },
2536                 { 0x06, 0x0761 },
2537                 { 0x1f, 0x0003 },
2538                 { 0x16, 0x0f0a },
2539                 { 0x1f, 0x0000 }
2540         };
2541
2542         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2543
2544         rtl_patchphy(tp, 0x16, 1 << 0);
2545         rtl_patchphy(tp, 0x14, 1 << 5);
2546         rtl_patchphy(tp, 0x0d, 1 << 5);
2547         rtl_writephy(tp, 0x1f, 0x0000);
2548 }
2549
2550 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2551 {
2552         static const struct phy_reg phy_reg_init[] = {
2553                 { 0x1f, 0x0001 },
2554                 { 0x12, 0x2300 },
2555                 { 0x1d, 0x3d98 },
2556                 { 0x1f, 0x0002 },
2557                 { 0x0c, 0x7eb8 },
2558                 { 0x06, 0x5461 },
2559                 { 0x1f, 0x0003 },
2560                 { 0x16, 0x0f0a },
2561                 { 0x1f, 0x0000 }
2562         };
2563
2564         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2565
2566         rtl_patchphy(tp, 0x16, 1 << 0);
2567         rtl_patchphy(tp, 0x14, 1 << 5);
2568         rtl_patchphy(tp, 0x0d, 1 << 5);
2569         rtl_writephy(tp, 0x1f, 0x0000);
2570 }
2571
2572 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2573 {
2574         rtl8168c_3_hw_phy_config(tp);
2575 }
2576
2577 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579         static const struct phy_reg phy_reg_init_0[] = {
2580                 /* Channel Estimation */
2581                 { 0x1f, 0x0001 },
2582                 { 0x06, 0x4064 },
2583                 { 0x07, 0x2863 },
2584                 { 0x08, 0x059c },
2585                 { 0x09, 0x26b4 },
2586                 { 0x0a, 0x6a19 },
2587                 { 0x0b, 0xdcc8 },
2588                 { 0x10, 0xf06d },
2589                 { 0x14, 0x7f68 },
2590                 { 0x18, 0x7fd9 },
2591                 { 0x1c, 0xf0ff },
2592                 { 0x1d, 0x3d9c },
2593                 { 0x1f, 0x0003 },
2594                 { 0x12, 0xf49f },
2595                 { 0x13, 0x070b },
2596                 { 0x1a, 0x05ad },
2597                 { 0x14, 0x94c0 },
2598
2599                 /*
2600                  * Tx Error Issue
2601                  * Enhance line driver power
2602                  */
2603                 { 0x1f, 0x0002 },
2604                 { 0x06, 0x5561 },
2605                 { 0x1f, 0x0005 },
2606                 { 0x05, 0x8332 },
2607                 { 0x06, 0x5561 },
2608
2609                 /*
2610                  * Can not link to 1Gbps with bad cable
2611                  * Decrease SNR threshold form 21.07dB to 19.04dB
2612                  */
2613                 { 0x1f, 0x0001 },
2614                 { 0x17, 0x0cc0 },
2615
2616                 { 0x1f, 0x0000 },
2617                 { 0x0d, 0xf880 }
2618         };
2619         void __iomem *ioaddr = tp->mmio_addr;
2620
2621         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2622
2623         /*
2624          * Rx Error Issue
2625          * Fine Tune Switching regulator parameter
2626          */
2627         rtl_writephy(tp, 0x1f, 0x0002);
2628         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2629         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2630
2631         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2632                 static const struct phy_reg phy_reg_init[] = {
2633                         { 0x1f, 0x0002 },
2634                         { 0x05, 0x669a },
2635                         { 0x1f, 0x0005 },
2636                         { 0x05, 0x8330 },
2637                         { 0x06, 0x669a },
2638                         { 0x1f, 0x0002 }
2639                 };
2640                 int val;
2641
2642                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2643
2644                 val = rtl_readphy(tp, 0x0d);
2645
2646                 if ((val & 0x00ff) != 0x006c) {
2647                         static const u32 set[] = {
2648                                 0x0065, 0x0066, 0x0067, 0x0068,
2649                                 0x0069, 0x006a, 0x006b, 0x006c
2650                         };
2651                         int i;
2652
2653                         rtl_writephy(tp, 0x1f, 0x0002);
2654
2655                         val &= 0xff00;
2656                         for (i = 0; i < ARRAY_SIZE(set); i++)
2657                                 rtl_writephy(tp, 0x0d, val | set[i]);
2658                 }
2659         } else {
2660                 static const struct phy_reg phy_reg_init[] = {
2661                         { 0x1f, 0x0002 },
2662                         { 0x05, 0x6662 },
2663                         { 0x1f, 0x0005 },
2664                         { 0x05, 0x8330 },
2665                         { 0x06, 0x6662 }
2666                 };
2667
2668                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2669         }
2670
2671         /* RSET couple improve */
2672         rtl_writephy(tp, 0x1f, 0x0002);
2673         rtl_patchphy(tp, 0x0d, 0x0300);
2674         rtl_patchphy(tp, 0x0f, 0x0010);
2675
2676         /* Fine tune PLL performance */
2677         rtl_writephy(tp, 0x1f, 0x0002);
2678         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2679         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2680
2681         rtl_writephy(tp, 0x1f, 0x0005);
2682         rtl_writephy(tp, 0x05, 0x001b);
2683
2684         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2685
2686         rtl_writephy(tp, 0x1f, 0x0000);
2687 }
2688
2689 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2690 {
2691         static const struct phy_reg phy_reg_init_0[] = {
2692                 /* Channel Estimation */
2693                 { 0x1f, 0x0001 },
2694                 { 0x06, 0x4064 },
2695                 { 0x07, 0x2863 },
2696                 { 0x08, 0x059c },
2697                 { 0x09, 0x26b4 },
2698                 { 0x0a, 0x6a19 },
2699                 { 0x0b, 0xdcc8 },
2700                 { 0x10, 0xf06d },
2701                 { 0x14, 0x7f68 },
2702                 { 0x18, 0x7fd9 },
2703                 { 0x1c, 0xf0ff },
2704                 { 0x1d, 0x3d9c },
2705                 { 0x1f, 0x0003 },
2706                 { 0x12, 0xf49f },
2707                 { 0x13, 0x070b },
2708                 { 0x1a, 0x05ad },
2709                 { 0x14, 0x94c0 },
2710
2711                 /*
2712                  * Tx Error Issue
2713                  * Enhance line driver power
2714                  */
2715                 { 0x1f, 0x0002 },
2716                 { 0x06, 0x5561 },
2717                 { 0x1f, 0x0005 },
2718                 { 0x05, 0x8332 },
2719                 { 0x06, 0x5561 },
2720
2721                 /*
2722                  * Can not link to 1Gbps with bad cable
2723                  * Decrease SNR threshold form 21.07dB to 19.04dB
2724                  */
2725                 { 0x1f, 0x0001 },
2726                 { 0x17, 0x0cc0 },
2727
2728                 { 0x1f, 0x0000 },
2729                 { 0x0d, 0xf880 }
2730         };
2731         void __iomem *ioaddr = tp->mmio_addr;
2732
2733         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2734
2735         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2736                 static const struct phy_reg phy_reg_init[] = {
2737                         { 0x1f, 0x0002 },
2738                         { 0x05, 0x669a },
2739                         { 0x1f, 0x0005 },
2740                         { 0x05, 0x8330 },
2741                         { 0x06, 0x669a },
2742
2743                         { 0x1f, 0x0002 }
2744                 };
2745                 int val;
2746
2747                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2748
2749                 val = rtl_readphy(tp, 0x0d);
2750                 if ((val & 0x00ff) != 0x006c) {
2751                         static const u32 set[] = {
2752                                 0x0065, 0x0066, 0x0067, 0x0068,
2753                                 0x0069, 0x006a, 0x006b, 0x006c
2754                         };
2755                         int i;
2756
2757                         rtl_writephy(tp, 0x1f, 0x0002);
2758
2759                         val &= 0xff00;
2760                         for (i = 0; i < ARRAY_SIZE(set); i++)
2761                                 rtl_writephy(tp, 0x0d, val | set[i]);
2762                 }
2763         } else {
2764                 static const struct phy_reg phy_reg_init[] = {
2765                         { 0x1f, 0x0002 },
2766                         { 0x05, 0x2642 },
2767                         { 0x1f, 0x0005 },
2768                         { 0x05, 0x8330 },
2769                         { 0x06, 0x2642 }
2770                 };
2771
2772                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2773         }
2774
2775         /* Fine tune PLL performance */
2776         rtl_writephy(tp, 0x1f, 0x0002);
2777         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2778         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2779
2780         /* Switching regulator Slew rate */
2781         rtl_writephy(tp, 0x1f, 0x0002);
2782         rtl_patchphy(tp, 0x0f, 0x0017);
2783
2784         rtl_writephy(tp, 0x1f, 0x0005);
2785         rtl_writephy(tp, 0x05, 0x001b);
2786
2787         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2788
2789         rtl_writephy(tp, 0x1f, 0x0000);
2790 }
2791
2792 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2793 {
2794         static const struct phy_reg phy_reg_init[] = {
2795                 { 0x1f, 0x0002 },
2796                 { 0x10, 0x0008 },
2797                 { 0x0d, 0x006c },
2798
2799                 { 0x1f, 0x0000 },
2800                 { 0x0d, 0xf880 },
2801
2802                 { 0x1f, 0x0001 },
2803                 { 0x17, 0x0cc0 },
2804
2805                 { 0x1f, 0x0001 },
2806                 { 0x0b, 0xa4d8 },
2807                 { 0x09, 0x281c },
2808                 { 0x07, 0x2883 },
2809                 { 0x0a, 0x6b35 },
2810                 { 0x1d, 0x3da4 },
2811                 { 0x1c, 0xeffd },
2812                 { 0x14, 0x7f52 },
2813                 { 0x18, 0x7fc6 },
2814                 { 0x08, 0x0601 },
2815                 { 0x06, 0x4063 },
2816                 { 0x10, 0xf074 },
2817                 { 0x1f, 0x0003 },
2818                 { 0x13, 0x0789 },
2819                 { 0x12, 0xf4bd },
2820                 { 0x1a, 0x04fd },
2821                 { 0x14, 0x84b0 },
2822                 { 0x1f, 0x0000 },
2823                 { 0x00, 0x9200 },
2824
2825                 { 0x1f, 0x0005 },
2826                 { 0x01, 0x0340 },
2827                 { 0x1f, 0x0001 },
2828                 { 0x04, 0x4000 },
2829                 { 0x03, 0x1d21 },
2830                 { 0x02, 0x0c32 },
2831                 { 0x01, 0x0200 },
2832                 { 0x00, 0x5554 },
2833                 { 0x04, 0x4800 },
2834                 { 0x04, 0x4000 },
2835                 { 0x04, 0xf000 },
2836                 { 0x03, 0xdf01 },
2837                 { 0x02, 0xdf20 },
2838                 { 0x01, 0x101a },
2839                 { 0x00, 0xa0ff },
2840                 { 0x04, 0xf800 },
2841                 { 0x04, 0xf000 },
2842                 { 0x1f, 0x0000 },
2843
2844                 { 0x1f, 0x0007 },
2845                 { 0x1e, 0x0023 },
2846                 { 0x16, 0x0000 },
2847                 { 0x1f, 0x0000 }
2848         };
2849
2850         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851 }
2852
2853 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2854 {
2855         static const struct phy_reg phy_reg_init[] = {
2856                 { 0x1f, 0x0001 },
2857                 { 0x17, 0x0cc0 },
2858
2859                 { 0x1f, 0x0007 },
2860                 { 0x1e, 0x002d },
2861                 { 0x18, 0x0040 },
2862                 { 0x1f, 0x0000 }
2863         };
2864
2865         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866         rtl_patchphy(tp, 0x0d, 1 << 5);
2867 }
2868
2869 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2870 {
2871         static const struct phy_reg phy_reg_init[] = {
2872                 /* Enable Delay cap */
2873                 { 0x1f, 0x0005 },
2874                 { 0x05, 0x8b80 },
2875                 { 0x06, 0xc896 },
2876                 { 0x1f, 0x0000 },
2877
2878                 /* Channel estimation fine tune */
2879                 { 0x1f, 0x0001 },
2880                 { 0x0b, 0x6c20 },
2881                 { 0x07, 0x2872 },
2882                 { 0x1c, 0xefff },
2883                 { 0x1f, 0x0003 },
2884                 { 0x14, 0x6420 },
2885                 { 0x1f, 0x0000 },
2886
2887                 /* Update PFM & 10M TX idle timer */
2888                 { 0x1f, 0x0007 },
2889                 { 0x1e, 0x002f },
2890                 { 0x15, 0x1919 },
2891                 { 0x1f, 0x0000 },
2892
2893                 { 0x1f, 0x0007 },
2894                 { 0x1e, 0x00ac },
2895                 { 0x18, 0x0006 },
2896                 { 0x1f, 0x0000 }
2897         };
2898
2899         rtl_apply_firmware(tp);
2900
2901         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2902
2903         /* DCO enable for 10M IDLE Power */
2904         rtl_writephy(tp, 0x1f, 0x0007);
2905         rtl_writephy(tp, 0x1e, 0x0023);
2906         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2907         rtl_writephy(tp, 0x1f, 0x0000);
2908
2909         /* For impedance matching */
2910         rtl_writephy(tp, 0x1f, 0x0002);
2911         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2912         rtl_writephy(tp, 0x1f, 0x0000);
2913
2914         /* PHY auto speed down */
2915         rtl_writephy(tp, 0x1f, 0x0007);
2916         rtl_writephy(tp, 0x1e, 0x002d);
2917         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2918         rtl_writephy(tp, 0x1f, 0x0000);
2919         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2920
2921         rtl_writephy(tp, 0x1f, 0x0005);
2922         rtl_writephy(tp, 0x05, 0x8b86);
2923         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2924         rtl_writephy(tp, 0x1f, 0x0000);
2925
2926         rtl_writephy(tp, 0x1f, 0x0005);
2927         rtl_writephy(tp, 0x05, 0x8b85);
2928         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2929         rtl_writephy(tp, 0x1f, 0x0007);
2930         rtl_writephy(tp, 0x1e, 0x0020);
2931         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2932         rtl_writephy(tp, 0x1f, 0x0006);
2933         rtl_writephy(tp, 0x00, 0x5a00);
2934         rtl_writephy(tp, 0x1f, 0x0000);
2935         rtl_writephy(tp, 0x0d, 0x0007);
2936         rtl_writephy(tp, 0x0e, 0x003c);
2937         rtl_writephy(tp, 0x0d, 0x4007);
2938         rtl_writephy(tp, 0x0e, 0x0000);
2939         rtl_writephy(tp, 0x0d, 0x0000);
2940 }
2941
2942 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2943 {
2944         static const struct phy_reg phy_reg_init[] = {
2945                 /* Enable Delay cap */
2946                 { 0x1f, 0x0004 },
2947                 { 0x1f, 0x0007 },
2948                 { 0x1e, 0x00ac },
2949                 { 0x18, 0x0006 },
2950                 { 0x1f, 0x0002 },
2951                 { 0x1f, 0x0000 },
2952                 { 0x1f, 0x0000 },
2953
2954                 /* Channel estimation fine tune */
2955                 { 0x1f, 0x0003 },
2956                 { 0x09, 0xa20f },
2957                 { 0x1f, 0x0000 },
2958                 { 0x1f, 0x0000 },
2959
2960                 /* Green Setting */
2961                 { 0x1f, 0x0005 },
2962                 { 0x05, 0x8b5b },
2963                 { 0x06, 0x9222 },
2964                 { 0x05, 0x8b6d },
2965                 { 0x06, 0x8000 },
2966                 { 0x05, 0x8b76 },
2967                 { 0x06, 0x8000 },
2968                 { 0x1f, 0x0000 }
2969         };
2970
2971         rtl_apply_firmware(tp);
2972
2973         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2974
2975         /* For 4-corner performance improve */
2976         rtl_writephy(tp, 0x1f, 0x0005);
2977         rtl_writephy(tp, 0x05, 0x8b80);
2978         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2979         rtl_writephy(tp, 0x1f, 0x0000);
2980
2981         /* PHY auto speed down */
2982         rtl_writephy(tp, 0x1f, 0x0004);
2983         rtl_writephy(tp, 0x1f, 0x0007);
2984         rtl_writephy(tp, 0x1e, 0x002d);
2985         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2986         rtl_writephy(tp, 0x1f, 0x0002);
2987         rtl_writephy(tp, 0x1f, 0x0000);
2988         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2989
2990         /* improve 10M EEE waveform */
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x8b86);
2993         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2994         rtl_writephy(tp, 0x1f, 0x0000);
2995
2996         /* Improve 2-pair detection performance */
2997         rtl_writephy(tp, 0x1f, 0x0005);
2998         rtl_writephy(tp, 0x05, 0x8b85);
2999         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3000         rtl_writephy(tp, 0x1f, 0x0000);
3001
3002         /* EEE setting */
3003         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3004                      ERIAR_EXGMAC);
3005         rtl_writephy(tp, 0x1f, 0x0005);
3006         rtl_writephy(tp, 0x05, 0x8b85);
3007         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3008         rtl_writephy(tp, 0x1f, 0x0004);
3009         rtl_writephy(tp, 0x1f, 0x0007);
3010         rtl_writephy(tp, 0x1e, 0x0020);
3011         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3012         rtl_writephy(tp, 0x1f, 0x0002);
3013         rtl_writephy(tp, 0x1f, 0x0000);
3014         rtl_writephy(tp, 0x0d, 0x0007);
3015         rtl_writephy(tp, 0x0e, 0x003c);
3016         rtl_writephy(tp, 0x0d, 0x4007);
3017         rtl_writephy(tp, 0x0e, 0x0000);
3018         rtl_writephy(tp, 0x0d, 0x0000);
3019
3020         /* Green feature */
3021         rtl_writephy(tp, 0x1f, 0x0003);
3022         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3023         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3024         rtl_writephy(tp, 0x1f, 0x0000);
3025 }
3026
3027 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3028 {
3029         static const struct phy_reg phy_reg_init[] = {
3030                 /* Channel estimation fine tune */
3031                 { 0x1f, 0x0003 },
3032                 { 0x09, 0xa20f },
3033                 { 0x1f, 0x0000 },
3034
3035                 /* Modify green table for giga & fnet */
3036                 { 0x1f, 0x0005 },
3037                 { 0x05, 0x8b55 },
3038                 { 0x06, 0x0000 },
3039                 { 0x05, 0x8b5e },
3040                 { 0x06, 0x0000 },
3041                 { 0x05, 0x8b67 },
3042                 { 0x06, 0x0000 },
3043                 { 0x05, 0x8b70 },
3044                 { 0x06, 0x0000 },
3045                 { 0x1f, 0x0000 },
3046                 { 0x1f, 0x0007 },
3047                 { 0x1e, 0x0078 },
3048                 { 0x17, 0x0000 },
3049                 { 0x19, 0x00fb },
3050                 { 0x1f, 0x0000 },
3051
3052                 /* Modify green table for 10M */
3053                 { 0x1f, 0x0005 },
3054                 { 0x05, 0x8b79 },
3055                 { 0x06, 0xaa00 },
3056                 { 0x1f, 0x0000 },
3057
3058                 /* Disable hiimpedance detection (RTCT) */
3059                 { 0x1f, 0x0003 },
3060                 { 0x01, 0x328a },
3061                 { 0x1f, 0x0000 }
3062         };
3063
3064         rtl_apply_firmware(tp);
3065
3066         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3067
3068         /* For 4-corner performance improve */
3069         rtl_writephy(tp, 0x1f, 0x0005);
3070         rtl_writephy(tp, 0x05, 0x8b80);
3071         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3072         rtl_writephy(tp, 0x1f, 0x0000);
3073
3074         /* PHY auto speed down */
3075         rtl_writephy(tp, 0x1f, 0x0007);
3076         rtl_writephy(tp, 0x1e, 0x002d);
3077         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3080
3081         /* Improve 10M EEE waveform */
3082         rtl_writephy(tp, 0x1f, 0x0005);
3083         rtl_writephy(tp, 0x05, 0x8b86);
3084         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3085         rtl_writephy(tp, 0x1f, 0x0000);
3086
3087         /* Improve 2-pair detection performance */
3088         rtl_writephy(tp, 0x1f, 0x0005);
3089         rtl_writephy(tp, 0x05, 0x8b85);
3090         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3091         rtl_writephy(tp, 0x1f, 0x0000);
3092 }
3093
3094 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3095 {
3096         rtl_apply_firmware(tp);
3097
3098         /* For 4-corner performance improve */
3099         rtl_writephy(tp, 0x1f, 0x0005);
3100         rtl_writephy(tp, 0x05, 0x8b80);
3101         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3102         rtl_writephy(tp, 0x1f, 0x0000);
3103
3104         /* PHY auto speed down */
3105         rtl_writephy(tp, 0x1f, 0x0007);
3106         rtl_writephy(tp, 0x1e, 0x002d);
3107         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3108         rtl_writephy(tp, 0x1f, 0x0000);
3109         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3110
3111         /* Improve 10M EEE waveform */
3112         rtl_writephy(tp, 0x1f, 0x0005);
3113         rtl_writephy(tp, 0x05, 0x8b86);
3114         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3115         rtl_writephy(tp, 0x1f, 0x0000);
3116 }
3117
3118 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3119 {
3120         static const struct phy_reg phy_reg_init[] = {
3121                 { 0x1f, 0x0003 },
3122                 { 0x08, 0x441d },
3123                 { 0x01, 0x9100 },
3124                 { 0x1f, 0x0000 }
3125         };
3126
3127         rtl_writephy(tp, 0x1f, 0x0000);
3128         rtl_patchphy(tp, 0x11, 1 << 12);
3129         rtl_patchphy(tp, 0x19, 1 << 13);
3130         rtl_patchphy(tp, 0x10, 1 << 15);
3131
3132         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3133 }
3134
3135 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3136 {
3137         static const struct phy_reg phy_reg_init[] = {
3138                 { 0x1f, 0x0005 },
3139                 { 0x1a, 0x0000 },
3140                 { 0x1f, 0x0000 },
3141
3142                 { 0x1f, 0x0004 },
3143                 { 0x1c, 0x0000 },
3144                 { 0x1f, 0x0000 },
3145
3146                 { 0x1f, 0x0001 },
3147                 { 0x15, 0x7701 },
3148                 { 0x1f, 0x0000 }
3149         };
3150
3151         /* Disable ALDPS before ram code */
3152         rtl_writephy(tp, 0x1f, 0x0000);
3153         rtl_writephy(tp, 0x18, 0x0310);
3154         msleep(100);
3155
3156         rtl_apply_firmware(tp);
3157
3158         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159 }
3160
3161 static void rtl_hw_phy_config(struct net_device *dev)
3162 {
3163         struct rtl8169_private *tp = netdev_priv(dev);
3164
3165         rtl8169_print_mac_version(tp);
3166
3167         switch (tp->mac_version) {
3168         case RTL_GIGA_MAC_VER_01:
3169                 break;
3170         case RTL_GIGA_MAC_VER_02:
3171         case RTL_GIGA_MAC_VER_03:
3172                 rtl8169s_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_04:
3175                 rtl8169sb_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_05:
3178                 rtl8169scd_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_06:
3181                 rtl8169sce_hw_phy_config(tp);
3182                 break;
3183         case RTL_GIGA_MAC_VER_07:
3184         case RTL_GIGA_MAC_VER_08:
3185         case RTL_GIGA_MAC_VER_09:
3186                 rtl8102e_hw_phy_config(tp);
3187                 break;
3188         case RTL_GIGA_MAC_VER_11:
3189                 rtl8168bb_hw_phy_config(tp);
3190                 break;
3191         case RTL_GIGA_MAC_VER_12:
3192                 rtl8168bef_hw_phy_config(tp);
3193                 break;
3194         case RTL_GIGA_MAC_VER_17:
3195                 rtl8168bef_hw_phy_config(tp);
3196                 break;
3197         case RTL_GIGA_MAC_VER_18:
3198                 rtl8168cp_1_hw_phy_config(tp);
3199                 break;
3200         case RTL_GIGA_MAC_VER_19:
3201                 rtl8168c_1_hw_phy_config(tp);
3202                 break;
3203         case RTL_GIGA_MAC_VER_20:
3204                 rtl8168c_2_hw_phy_config(tp);
3205                 break;
3206         case RTL_GIGA_MAC_VER_21:
3207                 rtl8168c_3_hw_phy_config(tp);
3208                 break;
3209         case RTL_GIGA_MAC_VER_22:
3210                 rtl8168c_4_hw_phy_config(tp);
3211                 break;
3212         case RTL_GIGA_MAC_VER_23:
3213         case RTL_GIGA_MAC_VER_24:
3214                 rtl8168cp_2_hw_phy_config(tp);
3215                 break;
3216         case RTL_GIGA_MAC_VER_25:
3217                 rtl8168d_1_hw_phy_config(tp);
3218                 break;
3219         case RTL_GIGA_MAC_VER_26:
3220                 rtl8168d_2_hw_phy_config(tp);
3221                 break;
3222         case RTL_GIGA_MAC_VER_27:
3223                 rtl8168d_3_hw_phy_config(tp);
3224                 break;
3225         case RTL_GIGA_MAC_VER_28:
3226                 rtl8168d_4_hw_phy_config(tp);
3227                 break;
3228         case RTL_GIGA_MAC_VER_29:
3229         case RTL_GIGA_MAC_VER_30:
3230                 rtl8105e_hw_phy_config(tp);
3231                 break;
3232         case RTL_GIGA_MAC_VER_31:
3233                 /* None. */
3234                 break;
3235         case RTL_GIGA_MAC_VER_32:
3236         case RTL_GIGA_MAC_VER_33:
3237                 rtl8168e_1_hw_phy_config(tp);
3238                 break;
3239         case RTL_GIGA_MAC_VER_34:
3240                 rtl8168e_2_hw_phy_config(tp);
3241                 break;
3242         case RTL_GIGA_MAC_VER_35:
3243                 rtl8168f_1_hw_phy_config(tp);
3244                 break;
3245         case RTL_GIGA_MAC_VER_36:
3246                 rtl8168f_2_hw_phy_config(tp);
3247                 break;
3248
3249         default:
3250                 break;
3251         }
3252 }
3253
3254 static void rtl_phy_work(struct rtl8169_private *tp)
3255 {
3256         struct timer_list *timer = &tp->timer;
3257         void __iomem *ioaddr = tp->mmio_addr;
3258         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3259
3260         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3261
3262         if (tp->phy_reset_pending(tp)) {
3263                 /*
3264                  * A busy loop could burn quite a few cycles on nowadays CPU.
3265                  * Let's delay the execution of the timer for a few ticks.
3266                  */
3267                 timeout = HZ/10;
3268                 goto out_mod_timer;
3269         }
3270
3271         if (tp->link_ok(ioaddr))
3272                 return;
3273
3274         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3275
3276         tp->phy_reset_enable(tp);
3277
3278 out_mod_timer:
3279         mod_timer(timer, jiffies + timeout);
3280 }
3281
3282 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3283 {
3284         if (!test_and_set_bit(flag, tp->wk.flags))
3285                 schedule_work(&tp->wk.work);
3286 }
3287
3288 static void rtl8169_phy_timer(unsigned long __opaque)
3289 {
3290         struct net_device *dev = (struct net_device *)__opaque;
3291         struct rtl8169_private *tp = netdev_priv(dev);
3292
3293         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3294 }
3295
3296 #ifdef CONFIG_NET_POLL_CONTROLLER
3297 static void rtl8169_netpoll(struct net_device *dev)
3298 {
3299         struct rtl8169_private *tp = netdev_priv(dev);
3300
3301         rtl8169_interrupt(tp->pci_dev->irq, dev);
3302 }
3303 #endif
3304
3305 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3306                                   void __iomem *ioaddr)
3307 {
3308         iounmap(ioaddr);
3309         pci_release_regions(pdev);
3310         pci_clear_mwi(pdev);
3311         pci_disable_device(pdev);
3312         free_netdev(dev);
3313 }
3314
3315 static void rtl8169_phy_reset(struct net_device *dev,
3316                               struct rtl8169_private *tp)
3317 {
3318         unsigned int i;
3319
3320         tp->phy_reset_enable(tp);
3321         for (i = 0; i < 100; i++) {
3322                 if (!tp->phy_reset_pending(tp))
3323                         return;
3324                 msleep(1);
3325         }
3326         netif_err(tp, link, dev, "PHY reset failed\n");
3327 }
3328
3329 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3330 {
3331         void __iomem *ioaddr = tp->mmio_addr;
3332
3333         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3334             (RTL_R8(PHYstatus) & TBI_Enable);
3335 }
3336
3337 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3338 {
3339         void __iomem *ioaddr = tp->mmio_addr;
3340
3341         rtl_hw_phy_config(dev);
3342
3343         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3344                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3345                 RTL_W8(0x82, 0x01);
3346         }
3347
3348         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3349
3350         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3351                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3352
3353         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3354                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3355                 RTL_W8(0x82, 0x01);
3356                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3357                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3358         }
3359
3360         rtl8169_phy_reset(dev, tp);
3361
3362         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3363                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3364                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3365                           (tp->mii.supports_gmii ?
3366                            ADVERTISED_1000baseT_Half |
3367                            ADVERTISED_1000baseT_Full : 0));
3368
3369         if (rtl_tbi_enabled(tp))
3370                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3371 }
3372
3373 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3374 {
3375         void __iomem *ioaddr = tp->mmio_addr;
3376         u32 high;
3377         u32 low;
3378
3379         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3380         high = addr[4] | (addr[5] << 8);
3381
3382         rtl_lock_work(tp);
3383
3384         RTL_W8(Cfg9346, Cfg9346_Unlock);
3385
3386         RTL_W32(MAC4, high);
3387         RTL_R32(MAC4);
3388
3389         RTL_W32(MAC0, low);
3390         RTL_R32(MAC0);
3391
3392         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3393                 const struct exgmac_reg e[] = {
3394                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3395                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3396                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3397                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3398                                                                 low  >> 16 },
3399                 };
3400
3401                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3402         }
3403
3404         RTL_W8(Cfg9346, Cfg9346_Lock);
3405
3406         rtl_unlock_work(tp);
3407 }
3408
3409 static int rtl_set_mac_address(struct net_device *dev, void *p)
3410 {
3411         struct rtl8169_private *tp = netdev_priv(dev);
3412         struct sockaddr *addr = p;
3413
3414         if (!is_valid_ether_addr(addr->sa_data))
3415                 return -EADDRNOTAVAIL;
3416
3417         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3418
3419         rtl_rar_set(tp, dev->dev_addr);
3420
3421         return 0;
3422 }
3423
3424 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3425 {
3426         struct rtl8169_private *tp = netdev_priv(dev);
3427         struct mii_ioctl_data *data = if_mii(ifr);
3428
3429         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3430 }
3431
3432 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3433                           struct mii_ioctl_data *data, int cmd)
3434 {
3435         switch (cmd) {
3436         case SIOCGMIIPHY:
3437                 data->phy_id = 32; /* Internal PHY */
3438                 return 0;
3439
3440         case SIOCGMIIREG:
3441                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3442                 return 0;
3443
3444         case SIOCSMIIREG:
3445                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3446                 return 0;
3447         }
3448         return -EOPNOTSUPP;
3449 }
3450
3451 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3452 {
3453         return -EOPNOTSUPP;
3454 }
3455
3456 static const struct rtl_cfg_info {
3457         void (*hw_start)(struct net_device *);
3458         unsigned int region;
3459         unsigned int align;
3460         u16 event_slow;
3461         unsigned features;
3462         u8 default_ver;
3463 } rtl_cfg_infos [] = {
3464         [RTL_CFG_0] = {
3465                 .hw_start       = rtl_hw_start_8169,
3466                 .region         = 1,
3467                 .align          = 0,
3468                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3469                 .features       = RTL_FEATURE_GMII,
3470                 .default_ver    = RTL_GIGA_MAC_VER_01,
3471         },
3472         [RTL_CFG_1] = {
3473                 .hw_start       = rtl_hw_start_8168,
3474                 .region         = 2,
3475                 .align          = 8,
3476                 .event_slow     = SYSErr | LinkChg | RxOverflow,
3477                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3478                 .default_ver    = RTL_GIGA_MAC_VER_11,
3479         },
3480         [RTL_CFG_2] = {
3481                 .hw_start       = rtl_hw_start_8101,
3482                 .region         = 2,
3483                 .align          = 8,
3484                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3485                                   PCSTimeout,
3486                 .features       = RTL_FEATURE_MSI,
3487                 .default_ver    = RTL_GIGA_MAC_VER_13,
3488         }
3489 };
3490
3491 /* Cfg9346_Unlock assumed. */
3492 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3493                             const struct rtl_cfg_info *cfg)
3494 {
3495         void __iomem *ioaddr = tp->mmio_addr;
3496         unsigned msi = 0;
3497         u8 cfg2;
3498
3499         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3500         if (cfg->features & RTL_FEATURE_MSI) {
3501                 if (pci_enable_msi(tp->pci_dev)) {
3502                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3503                 } else {
3504                         cfg2 |= MSIEnable;
3505                         msi = RTL_FEATURE_MSI;
3506                 }
3507         }
3508         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3509                 RTL_W8(Config2, cfg2);
3510         return msi;
3511 }
3512
3513 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3514 {
3515         if (tp->features & RTL_FEATURE_MSI) {
3516                 pci_disable_msi(pdev);
3517                 tp->features &= ~RTL_FEATURE_MSI;
3518         }
3519 }
3520
3521 static const struct net_device_ops rtl8169_netdev_ops = {
3522         .ndo_open               = rtl8169_open,
3523         .ndo_stop               = rtl8169_close,
3524         .ndo_get_stats          = rtl8169_get_stats,
3525         .ndo_start_xmit         = rtl8169_start_xmit,
3526         .ndo_tx_timeout         = rtl8169_tx_timeout,
3527         .ndo_validate_addr      = eth_validate_addr,
3528         .ndo_change_mtu         = rtl8169_change_mtu,
3529         .ndo_fix_features       = rtl8169_fix_features,
3530         .ndo_set_features       = rtl8169_set_features,
3531         .ndo_set_mac_address    = rtl_set_mac_address,
3532         .ndo_do_ioctl           = rtl8169_ioctl,
3533         .ndo_set_rx_mode        = rtl_set_rx_mode,
3534 #ifdef CONFIG_NET_POLL_CONTROLLER
3535         .ndo_poll_controller    = rtl8169_netpoll,
3536 #endif
3537
3538 };
3539
3540 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3541 {
3542         struct mdio_ops *ops = &tp->mdio_ops;
3543
3544         switch (tp->mac_version) {
3545         case RTL_GIGA_MAC_VER_27:
3546                 ops->write      = r8168dp_1_mdio_write;
3547                 ops->read       = r8168dp_1_mdio_read;
3548                 break;
3549         case RTL_GIGA_MAC_VER_28:
3550         case RTL_GIGA_MAC_VER_31:
3551                 ops->write      = r8168dp_2_mdio_write;
3552                 ops->read       = r8168dp_2_mdio_read;
3553                 break;
3554         default:
3555                 ops->write      = r8169_mdio_write;
3556                 ops->read       = r8169_mdio_read;
3557                 break;
3558         }
3559 }
3560
3561 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3562 {
3563         void __iomem *ioaddr = tp->mmio_addr;
3564
3565         switch (tp->mac_version) {
3566         case RTL_GIGA_MAC_VER_29:
3567         case RTL_GIGA_MAC_VER_30:
3568         case RTL_GIGA_MAC_VER_32:
3569         case RTL_GIGA_MAC_VER_33:
3570         case RTL_GIGA_MAC_VER_34:
3571                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3572                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3573                 break;
3574         default:
3575                 break;
3576         }
3577 }
3578
3579 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3580 {
3581         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3582                 return false;
3583
3584         rtl_writephy(tp, 0x1f, 0x0000);
3585         rtl_writephy(tp, MII_BMCR, 0x0000);
3586
3587         rtl_wol_suspend_quirk(tp);
3588
3589         return true;
3590 }
3591
3592 static void r810x_phy_power_down(struct rtl8169_private *tp)
3593 {
3594         rtl_writephy(tp, 0x1f, 0x0000);
3595         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3596 }
3597
3598 static void r810x_phy_power_up(struct rtl8169_private *tp)
3599 {
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3602 }
3603
3604 static void r810x_pll_power_down(struct rtl8169_private *tp)
3605 {
3606         if (rtl_wol_pll_power_down(tp))
3607                 return;
3608
3609         r810x_phy_power_down(tp);
3610 }
3611
3612 static void r810x_pll_power_up(struct rtl8169_private *tp)
3613 {
3614         r810x_phy_power_up(tp);
3615 }
3616
3617 static void r8168_phy_power_up(struct rtl8169_private *tp)
3618 {
3619         rtl_writephy(tp, 0x1f, 0x0000);
3620         switch (tp->mac_version) {
3621         case RTL_GIGA_MAC_VER_11:
3622         case RTL_GIGA_MAC_VER_12:
3623         case RTL_GIGA_MAC_VER_17:
3624         case RTL_GIGA_MAC_VER_18:
3625         case RTL_GIGA_MAC_VER_19:
3626         case RTL_GIGA_MAC_VER_20:
3627         case RTL_GIGA_MAC_VER_21:
3628         case RTL_GIGA_MAC_VER_22:
3629         case RTL_GIGA_MAC_VER_23:
3630         case RTL_GIGA_MAC_VER_24:
3631         case RTL_GIGA_MAC_VER_25:
3632         case RTL_GIGA_MAC_VER_26:
3633         case RTL_GIGA_MAC_VER_27:
3634         case RTL_GIGA_MAC_VER_28:
3635         case RTL_GIGA_MAC_VER_31:
3636                 rtl_writephy(tp, 0x0e, 0x0000);
3637                 break;
3638         default:
3639                 break;
3640         }
3641         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3642 }
3643
3644 static void r8168_phy_power_down(struct rtl8169_private *tp)
3645 {
3646         rtl_writephy(tp, 0x1f, 0x0000);
3647         switch (tp->mac_version) {
3648         case RTL_GIGA_MAC_VER_32:
3649         case RTL_GIGA_MAC_VER_33:
3650                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3651                 break;
3652
3653         case RTL_GIGA_MAC_VER_11:
3654         case RTL_GIGA_MAC_VER_12:
3655         case RTL_GIGA_MAC_VER_17:
3656         case RTL_GIGA_MAC_VER_18:
3657         case RTL_GIGA_MAC_VER_19:
3658         case RTL_GIGA_MAC_VER_20:
3659         case RTL_GIGA_MAC_VER_21:
3660         case RTL_GIGA_MAC_VER_22:
3661         case RTL_GIGA_MAC_VER_23:
3662         case RTL_GIGA_MAC_VER_24:
3663         case RTL_GIGA_MAC_VER_25:
3664         case RTL_GIGA_MAC_VER_26:
3665         case RTL_GIGA_MAC_VER_27:
3666         case RTL_GIGA_MAC_VER_28:
3667         case RTL_GIGA_MAC_VER_31:
3668                 rtl_writephy(tp, 0x0e, 0x0200);
3669         default:
3670                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3671                 break;
3672         }
3673 }
3674
3675 static void r8168_pll_power_down(struct rtl8169_private *tp)
3676 {
3677         void __iomem *ioaddr = tp->mmio_addr;
3678
3679         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3680              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3681              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3682             r8168dp_check_dash(tp)) {
3683                 return;
3684         }
3685
3686         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3687              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3688             (RTL_R16(CPlusCmd) & ASF)) {
3689                 return;
3690         }
3691
3692         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3693             tp->mac_version == RTL_GIGA_MAC_VER_33)
3694                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3695
3696         if (rtl_wol_pll_power_down(tp))
3697                 return;
3698
3699         r8168_phy_power_down(tp);
3700
3701         switch (tp->mac_version) {
3702         case RTL_GIGA_MAC_VER_25:
3703         case RTL_GIGA_MAC_VER_26:
3704         case RTL_GIGA_MAC_VER_27:
3705         case RTL_GIGA_MAC_VER_28:
3706         case RTL_GIGA_MAC_VER_31:
3707         case RTL_GIGA_MAC_VER_32:
3708         case RTL_GIGA_MAC_VER_33:
3709                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3710                 break;
3711         }
3712 }
3713
3714 static void r8168_pll_power_up(struct rtl8169_private *tp)
3715 {
3716         void __iomem *ioaddr = tp->mmio_addr;
3717
3718         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3719              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3720              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3721             r8168dp_check_dash(tp)) {
3722                 return;
3723         }
3724
3725         switch (tp->mac_version) {
3726         case RTL_GIGA_MAC_VER_25:
3727         case RTL_GIGA_MAC_VER_26:
3728         case RTL_GIGA_MAC_VER_27:
3729         case RTL_GIGA_MAC_VER_28:
3730         case RTL_GIGA_MAC_VER_31:
3731         case RTL_GIGA_MAC_VER_32:
3732         case RTL_GIGA_MAC_VER_33:
3733                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3734                 break;
3735         }
3736
3737         r8168_phy_power_up(tp);
3738 }
3739
3740 static void rtl_generic_op(struct rtl8169_private *tp,
3741                            void (*op)(struct rtl8169_private *))
3742 {
3743         if (op)
3744                 op(tp);
3745 }
3746
3747 static void rtl_pll_power_down(struct rtl8169_private *tp)
3748 {
3749         rtl_generic_op(tp, tp->pll_power_ops.down);
3750 }
3751
3752 static void rtl_pll_power_up(struct rtl8169_private *tp)
3753 {
3754         rtl_generic_op(tp, tp->pll_power_ops.up);
3755 }
3756
3757 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3758 {
3759         struct pll_power_ops *ops = &tp->pll_power_ops;
3760
3761         switch (tp->mac_version) {
3762         case RTL_GIGA_MAC_VER_07:
3763         case RTL_GIGA_MAC_VER_08:
3764         case RTL_GIGA_MAC_VER_09:
3765         case RTL_GIGA_MAC_VER_10:
3766         case RTL_GIGA_MAC_VER_16:
3767         case RTL_GIGA_MAC_VER_29:
3768         case RTL_GIGA_MAC_VER_30:
3769                 ops->down       = r810x_pll_power_down;
3770                 ops->up         = r810x_pll_power_up;
3771                 break;
3772
3773         case RTL_GIGA_MAC_VER_11:
3774         case RTL_GIGA_MAC_VER_12:
3775         case RTL_GIGA_MAC_VER_17:
3776         case RTL_GIGA_MAC_VER_18:
3777         case RTL_GIGA_MAC_VER_19:
3778         case RTL_GIGA_MAC_VER_20:
3779         case RTL_GIGA_MAC_VER_21:
3780         case RTL_GIGA_MAC_VER_22:
3781         case RTL_GIGA_MAC_VER_23:
3782         case RTL_GIGA_MAC_VER_24:
3783         case RTL_GIGA_MAC_VER_25:
3784         case RTL_GIGA_MAC_VER_26:
3785         case RTL_GIGA_MAC_VER_27:
3786         case RTL_GIGA_MAC_VER_28:
3787         case RTL_GIGA_MAC_VER_31:
3788         case RTL_GIGA_MAC_VER_32:
3789         case RTL_GIGA_MAC_VER_33:
3790         case RTL_GIGA_MAC_VER_34:
3791         case RTL_GIGA_MAC_VER_35:
3792         case RTL_GIGA_MAC_VER_36:
3793                 ops->down       = r8168_pll_power_down;
3794                 ops->up         = r8168_pll_power_up;
3795                 break;
3796
3797         default:
3798                 ops->down       = NULL;
3799                 ops->up         = NULL;
3800                 break;
3801         }
3802 }
3803
3804 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3805 {
3806         void __iomem *ioaddr = tp->mmio_addr;
3807
3808         switch (tp->mac_version) {
3809         case RTL_GIGA_MAC_VER_01:
3810         case RTL_GIGA_MAC_VER_02:
3811         case RTL_GIGA_MAC_VER_03:
3812         case RTL_GIGA_MAC_VER_04:
3813         case RTL_GIGA_MAC_VER_05:
3814         case RTL_GIGA_MAC_VER_06:
3815         case RTL_GIGA_MAC_VER_10:
3816         case RTL_GIGA_MAC_VER_11:
3817         case RTL_GIGA_MAC_VER_12:
3818         case RTL_GIGA_MAC_VER_13:
3819         case RTL_GIGA_MAC_VER_14:
3820         case RTL_GIGA_MAC_VER_15:
3821         case RTL_GIGA_MAC_VER_16:
3822         case RTL_GIGA_MAC_VER_17:
3823                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3824                 break;
3825         case RTL_GIGA_MAC_VER_18:
3826         case RTL_GIGA_MAC_VER_19:
3827         case RTL_GIGA_MAC_VER_20:
3828         case RTL_GIGA_MAC_VER_21:
3829         case RTL_GIGA_MAC_VER_22:
3830         case RTL_GIGA_MAC_VER_23:
3831         case RTL_GIGA_MAC_VER_24:
3832                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3833                 break;
3834         default:
3835                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3836                 break;
3837         }
3838 }
3839
3840 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3841 {
3842         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3843 }
3844
3845 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3846 {
3847         rtl_generic_op(tp, tp->jumbo_ops.enable);
3848 }
3849
3850 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3851 {
3852         rtl_generic_op(tp, tp->jumbo_ops.disable);
3853 }
3854
3855 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3856 {
3857         void __iomem *ioaddr = tp->mmio_addr;
3858
3859         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3860         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3861         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3862 }
3863
3864 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3865 {
3866         void __iomem *ioaddr = tp->mmio_addr;
3867
3868         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3869         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3870         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3871 }
3872
3873 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3874 {
3875         void __iomem *ioaddr = tp->mmio_addr;
3876
3877         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3878 }
3879
3880 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3881 {
3882         void __iomem *ioaddr = tp->mmio_addr;
3883
3884         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3885 }
3886
3887 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3888 {
3889         void __iomem *ioaddr = tp->mmio_addr;
3890
3891         RTL_W8(MaxTxPacketSize, 0x3f);
3892         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3893         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3894         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3895 }
3896
3897 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3898 {
3899         void __iomem *ioaddr = tp->mmio_addr;
3900
3901         RTL_W8(MaxTxPacketSize, 0x0c);
3902         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3903         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3904         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3905 }
3906
3907 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3908 {
3909         rtl_tx_performance_tweak(tp->pci_dev,
3910                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3911 }
3912
3913 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3914 {
3915         rtl_tx_performance_tweak(tp->pci_dev,
3916                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3917 }
3918
3919 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3920 {
3921         void __iomem *ioaddr = tp->mmio_addr;
3922
3923         r8168b_0_hw_jumbo_enable(tp);
3924
3925         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3926 }
3927
3928 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3929 {
3930         void __iomem *ioaddr = tp->mmio_addr;
3931
3932         r8168b_0_hw_jumbo_disable(tp);
3933
3934         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3935 }
3936
3937 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3938 {
3939         struct jumbo_ops *ops = &tp->jumbo_ops;
3940
3941         switch (tp->mac_version) {
3942         case RTL_GIGA_MAC_VER_11:
3943                 ops->disable    = r8168b_0_hw_jumbo_disable;
3944                 ops->enable     = r8168b_0_hw_jumbo_enable;
3945                 break;
3946         case RTL_GIGA_MAC_VER_12:
3947         case RTL_GIGA_MAC_VER_17:
3948                 ops->disable    = r8168b_1_hw_jumbo_disable;
3949                 ops->enable     = r8168b_1_hw_jumbo_enable;
3950                 break;
3951         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3952         case RTL_GIGA_MAC_VER_19:
3953         case RTL_GIGA_MAC_VER_20:
3954         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3955         case RTL_GIGA_MAC_VER_22:
3956         case RTL_GIGA_MAC_VER_23:
3957         case RTL_GIGA_MAC_VER_24:
3958         case RTL_GIGA_MAC_VER_25:
3959         case RTL_GIGA_MAC_VER_26:
3960                 ops->disable    = r8168c_hw_jumbo_disable;
3961                 ops->enable     = r8168c_hw_jumbo_enable;
3962                 break;
3963         case RTL_GIGA_MAC_VER_27:
3964         case RTL_GIGA_MAC_VER_28:
3965                 ops->disable    = r8168dp_hw_jumbo_disable;
3966                 ops->enable     = r8168dp_hw_jumbo_enable;
3967                 break;
3968         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3969         case RTL_GIGA_MAC_VER_32:
3970         case RTL_GIGA_MAC_VER_33:
3971         case RTL_GIGA_MAC_VER_34:
3972                 ops->disable    = r8168e_hw_jumbo_disable;
3973                 ops->enable     = r8168e_hw_jumbo_enable;
3974                 break;
3975
3976         /*
3977          * No action needed for jumbo frames with 8169.
3978          * No jumbo for 810x at all.
3979          */
3980         default:
3981                 ops->disable    = NULL;
3982                 ops->enable     = NULL;
3983                 break;
3984         }
3985 }
3986
3987 static void rtl_hw_reset(struct rtl8169_private *tp)
3988 {
3989         void __iomem *ioaddr = tp->mmio_addr;
3990         int i;
3991
3992         /* Soft reset the chip. */
3993         RTL_W8(ChipCmd, CmdReset);
3994
3995         /* Check that the chip has finished the reset. */
3996         for (i = 0; i < 100; i++) {
3997                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3998                         break;
3999                 udelay(100);
4000         }
4001 }
4002
4003 static int __devinit
4004 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4005 {
4006         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4007         const unsigned int region = cfg->region;
4008         struct rtl8169_private *tp;
4009         struct mii_if_info *mii;
4010         struct net_device *dev;
4011         void __iomem *ioaddr;
4012         int chipset, i;
4013         int rc;
4014
4015         if (netif_msg_drv(&debug)) {
4016                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4017                        MODULENAME, RTL8169_VERSION);
4018         }
4019
4020         dev = alloc_etherdev(sizeof (*tp));
4021         if (!dev) {
4022                 rc = -ENOMEM;
4023                 goto out;
4024         }
4025
4026         SET_NETDEV_DEV(dev, &pdev->dev);
4027         dev->netdev_ops = &rtl8169_netdev_ops;
4028         tp = netdev_priv(dev);
4029         tp->dev = dev;
4030         tp->pci_dev = pdev;
4031         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
4032
4033         mii = &tp->mii;
4034         mii->dev = dev;
4035         mii->mdio_read = rtl_mdio_read;
4036         mii->mdio_write = rtl_mdio_write;
4037         mii->phy_id_mask = 0x1f;
4038         mii->reg_num_mask = 0x1f;
4039         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4040
4041         /* disable ASPM completely as that cause random device stop working
4042          * problems as well as full system hangs for some PCIe devices users */
4043         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4044                                      PCIE_LINK_STATE_CLKPM);
4045
4046         /* enable device (incl. PCI PM wakeup and hotplug setup) */
4047         rc = pci_enable_device(pdev);
4048         if (rc < 0) {
4049                 netif_err(tp, probe, dev, "enable failure\n");
4050                 goto err_out_free_dev_1;
4051         }
4052
4053         if (pci_set_mwi(pdev) < 0)
4054                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4055
4056         /* make sure PCI base addr 1 is MMIO */
4057         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4058                 netif_err(tp, probe, dev,
4059                           "region #%d not an MMIO resource, aborting\n",
4060                           region);
4061                 rc = -ENODEV;
4062                 goto err_out_mwi_2;
4063         }
4064
4065         /* check for weird/broken PCI region reporting */
4066         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4067                 netif_err(tp, probe, dev,
4068                           "Invalid PCI region size(s), aborting\n");
4069                 rc = -ENODEV;
4070                 goto err_out_mwi_2;
4071         }
4072
4073         rc = pci_request_regions(pdev, MODULENAME);
4074         if (rc < 0) {
4075                 netif_err(tp, probe, dev, "could not request regions\n");
4076                 goto err_out_mwi_2;
4077         }
4078
4079         tp->cp_cmd = RxChkSum;
4080
4081         if ((sizeof(dma_addr_t) > 4) &&
4082             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4083                 tp->cp_cmd |= PCIDAC;
4084                 dev->features |= NETIF_F_HIGHDMA;
4085         } else {
4086                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4087                 if (rc < 0) {
4088                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4089                         goto err_out_free_res_3;
4090                 }
4091         }
4092
4093         /* ioremap MMIO region */
4094         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4095         if (!ioaddr) {
4096                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4097                 rc = -EIO;
4098                 goto err_out_free_res_3;
4099         }
4100         tp->mmio_addr = ioaddr;
4101
4102         if (!pci_is_pcie(pdev))
4103                 netif_info(tp, probe, dev, "not PCI Express\n");
4104
4105         /* Identify chip attached to board */
4106         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4107
4108         rtl_init_rxcfg(tp);
4109
4110         rtl_irq_disable(tp);
4111
4112         rtl_hw_reset(tp);
4113
4114         rtl_ack_events(tp, 0xffff);
4115
4116         pci_set_master(pdev);
4117
4118         /*
4119          * Pretend we are using VLANs; This bypasses a nasty bug where
4120          * Interrupts stop flowing on high load on 8110SCd controllers.
4121          */
4122         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4123                 tp->cp_cmd |= RxVlan;
4124
4125         rtl_init_mdio_ops(tp);
4126         rtl_init_pll_power_ops(tp);
4127         rtl_init_jumbo_ops(tp);
4128
4129         rtl8169_print_mac_version(tp);
4130
4131         chipset = tp->mac_version;
4132         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4133
4134         RTL_W8(Cfg9346, Cfg9346_Unlock);
4135         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4136         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4137         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4138                 tp->features |= RTL_FEATURE_WOL;
4139         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4140                 tp->features |= RTL_FEATURE_WOL;
4141         tp->features |= rtl_try_msi(tp, cfg);
4142         RTL_W8(Cfg9346, Cfg9346_Lock);
4143
4144         if (rtl_tbi_enabled(tp)) {
4145                 tp->set_speed = rtl8169_set_speed_tbi;
4146                 tp->get_settings = rtl8169_gset_tbi;
4147                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4148                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4149                 tp->link_ok = rtl8169_tbi_link_ok;
4150                 tp->do_ioctl = rtl_tbi_ioctl;
4151         } else {
4152                 tp->set_speed = rtl8169_set_speed_xmii;
4153                 tp->get_settings = rtl8169_gset_xmii;
4154                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4155                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4156                 tp->link_ok = rtl8169_xmii_link_ok;
4157                 tp->do_ioctl = rtl_xmii_ioctl;
4158         }
4159
4160         mutex_init(&tp->wk.mutex);
4161
4162         /* Get MAC address */
4163         for (i = 0; i < ETH_ALEN; i++)
4164                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4165         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4166
4167         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4168         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4169         dev->irq = pdev->irq;
4170         dev->base_addr = (unsigned long) ioaddr;
4171
4172         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4173
4174         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4175          * properly for all devices */
4176         dev->features |= NETIF_F_RXCSUM |
4177                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4178
4179         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4180                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4181         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4182                 NETIF_F_HIGHDMA;
4183
4184         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4185                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4186                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4187
4188         dev->hw_features |= NETIF_F_RXALL;
4189
4190         tp->hw_start = cfg->hw_start;
4191         tp->event_slow = cfg->event_slow;
4192
4193         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4194                 ~(RxBOVF | RxFOVF) : ~0;
4195
4196         init_timer(&tp->timer);
4197         tp->timer.data = (unsigned long) dev;
4198         tp->timer.function = rtl8169_phy_timer;
4199
4200         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4201
4202         rc = register_netdev(dev);
4203         if (rc < 0)
4204                 goto err_out_msi_4;
4205
4206         pci_set_drvdata(pdev, dev);
4207
4208         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4209                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4210                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4211         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4212                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4213                            "tx checksumming: %s]\n",
4214                            rtl_chip_infos[chipset].jumbo_max,
4215                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4216         }
4217
4218         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4219             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4220             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4221                 rtl8168_driver_start(tp);
4222         }
4223
4224         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4225
4226         if (pci_dev_run_wake(pdev))
4227                 pm_runtime_put_noidle(&pdev->dev);
4228
4229         netif_carrier_off(dev);
4230
4231 out:
4232         return rc;
4233
4234 err_out_msi_4:
4235         rtl_disable_msi(pdev, tp);
4236         iounmap(ioaddr);
4237 err_out_free_res_3:
4238         pci_release_regions(pdev);
4239 err_out_mwi_2:
4240         pci_clear_mwi(pdev);
4241         pci_disable_device(pdev);
4242 err_out_free_dev_1:
4243         free_netdev(dev);
4244         goto out;
4245 }
4246
4247 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4248 {
4249         struct net_device *dev = pci_get_drvdata(pdev);
4250         struct rtl8169_private *tp = netdev_priv(dev);
4251
4252         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4253             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4254             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4255                 rtl8168_driver_stop(tp);
4256         }
4257
4258         cancel_work_sync(&tp->wk.work);
4259
4260         unregister_netdev(dev);
4261
4262         rtl_release_firmware(tp);
4263
4264         if (pci_dev_run_wake(pdev))
4265                 pm_runtime_get_noresume(&pdev->dev);
4266
4267         /* restore original MAC address */
4268         rtl_rar_set(tp, dev->perm_addr);
4269
4270         rtl_disable_msi(pdev, tp);
4271         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4272         pci_set_drvdata(pdev, NULL);
4273 }
4274
4275 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4276 {
4277         struct rtl_fw *rtl_fw;
4278         const char *name;
4279         int rc = -ENOMEM;
4280
4281         name = rtl_lookup_firmware_name(tp);
4282         if (!name)
4283                 goto out_no_firmware;
4284
4285         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4286         if (!rtl_fw)
4287                 goto err_warn;
4288
4289         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4290         if (rc < 0)
4291                 goto err_free;
4292
4293         rc = rtl_check_firmware(tp, rtl_fw);
4294         if (rc < 0)
4295                 goto err_release_firmware;
4296
4297         tp->rtl_fw = rtl_fw;
4298 out:
4299         return;
4300
4301 err_release_firmware:
4302         release_firmware(rtl_fw->fw);
4303 err_free:
4304         kfree(rtl_fw);
4305 err_warn:
4306         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4307                    name, rc);
4308 out_no_firmware:
4309         tp->rtl_fw = NULL;
4310         goto out;
4311 }
4312
4313 static void rtl_request_firmware(struct rtl8169_private *tp)
4314 {
4315         if (IS_ERR(tp->rtl_fw))
4316                 rtl_request_uncached_firmware(tp);
4317 }
4318
4319 static void rtl_task(struct work_struct *);
4320
4321 static int rtl8169_open(struct net_device *dev)
4322 {
4323         struct rtl8169_private *tp = netdev_priv(dev);
4324         void __iomem *ioaddr = tp->mmio_addr;
4325         struct pci_dev *pdev = tp->pci_dev;
4326         int retval = -ENOMEM;
4327
4328         pm_runtime_get_sync(&pdev->dev);
4329
4330         /*
4331          * Rx and Tx desscriptors needs 256 bytes alignment.
4332          * dma_alloc_coherent provides more.
4333          */
4334         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4335                                              &tp->TxPhyAddr, GFP_KERNEL);
4336         if (!tp->TxDescArray)
4337                 goto err_pm_runtime_put;
4338
4339         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4340                                              &tp->RxPhyAddr, GFP_KERNEL);
4341         if (!tp->RxDescArray)
4342                 goto err_free_tx_0;
4343
4344         retval = rtl8169_init_ring(dev);
4345         if (retval < 0)
4346                 goto err_free_rx_1;
4347
4348         INIT_WORK(&tp->wk.work, rtl_task);
4349
4350         smp_mb();
4351
4352         rtl_request_firmware(tp);
4353
4354         retval = request_irq(dev->irq, rtl8169_interrupt,
4355                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4356                              dev->name, dev);
4357         if (retval < 0)
4358                 goto err_release_fw_2;
4359
4360         rtl_lock_work(tp);
4361
4362         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4363
4364         napi_enable(&tp->napi);
4365
4366         rtl8169_init_phy(dev, tp);
4367
4368         __rtl8169_set_features(dev, dev->features);
4369
4370         rtl_pll_power_up(tp);
4371
4372         rtl_hw_start(dev);
4373
4374         netif_start_queue(dev);
4375
4376         rtl_unlock_work(tp);
4377
4378         tp->saved_wolopts = 0;
4379         pm_runtime_put_noidle(&pdev->dev);
4380
4381         rtl8169_check_link_status(dev, tp, ioaddr);
4382 out:
4383         return retval;
4384
4385 err_release_fw_2:
4386         rtl_release_firmware(tp);
4387         rtl8169_rx_clear(tp);
4388 err_free_rx_1:
4389         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4390                           tp->RxPhyAddr);
4391         tp->RxDescArray = NULL;
4392 err_free_tx_0:
4393         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4394                           tp->TxPhyAddr);
4395         tp->TxDescArray = NULL;
4396 err_pm_runtime_put:
4397         pm_runtime_put_noidle(&pdev->dev);
4398         goto out;
4399 }
4400
4401 static void rtl_rx_close(struct rtl8169_private *tp)
4402 {
4403         void __iomem *ioaddr = tp->mmio_addr;
4404
4405         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4406 }
4407
4408 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4409 {
4410         void __iomem *ioaddr = tp->mmio_addr;
4411
4412         /* Disable interrupts */
4413         rtl8169_irq_mask_and_ack(tp);
4414
4415         rtl_rx_close(tp);
4416
4417         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4418             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4419             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4420                 while (RTL_R8(TxPoll) & NPQ)
4421                         udelay(20);
4422         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4423                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4424                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4425                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4426                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4427                         udelay(100);
4428         } else {
4429                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4430                 udelay(100);
4431         }
4432
4433         rtl_hw_reset(tp);
4434 }
4435
4436 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4437 {
4438         void __iomem *ioaddr = tp->mmio_addr;
4439
4440         /* Set DMA burst size and Interframe Gap Time */
4441         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4442                 (InterFrameGap << TxInterFrameGapShift));
4443 }
4444
4445 static void rtl_hw_start(struct net_device *dev)
4446 {
4447         struct rtl8169_private *tp = netdev_priv(dev);
4448
4449         tp->hw_start(dev);
4450
4451         rtl_irq_enable_all(tp);
4452 }
4453
4454 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4455                                          void __iomem *ioaddr)
4456 {
4457         /*
4458          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4459          * register to be written before TxDescAddrLow to work.
4460          * Switching from MMIO to I/O access fixes the issue as well.
4461          */
4462         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4463         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4464         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4465         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4466 }
4467
4468 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4469 {
4470         u16 cmd;
4471
4472         cmd = RTL_R16(CPlusCmd);
4473         RTL_W16(CPlusCmd, cmd);
4474         return cmd;
4475 }
4476
4477 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4478 {
4479         /* Low hurts. Let's disable the filtering. */
4480         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4481 }
4482
4483 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4484 {
4485         static const struct rtl_cfg2_info {
4486                 u32 mac_version;
4487                 u32 clk;
4488                 u32 val;
4489         } cfg2_info [] = {
4490                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4491                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4492                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4493                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4494         };
4495         const struct rtl_cfg2_info *p = cfg2_info;
4496         unsigned int i;
4497         u32 clk;
4498
4499         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4500         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4501                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4502                         RTL_W32(0x7c, p->val);
4503                         break;
4504                 }
4505         }
4506 }
4507
4508 static void rtl_hw_start_8169(struct net_device *dev)
4509 {
4510         struct rtl8169_private *tp = netdev_priv(dev);
4511         void __iomem *ioaddr = tp->mmio_addr;
4512         struct pci_dev *pdev = tp->pci_dev;
4513
4514         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4515                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4516                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4517         }
4518
4519         RTL_W8(Cfg9346, Cfg9346_Unlock);
4520         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4521             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4522             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4523             tp->mac_version == RTL_GIGA_MAC_VER_04)
4524                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4525
4526         rtl_init_rxcfg(tp);
4527
4528         RTL_W8(EarlyTxThres, NoEarlyTx);
4529
4530         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4531
4532         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4533             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4534             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4535             tp->mac_version == RTL_GIGA_MAC_VER_04)
4536                 rtl_set_rx_tx_config_registers(tp);
4537
4538         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4539
4540         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4541             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4542                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4543                         "Bit-3 and bit-14 MUST be 1\n");
4544                 tp->cp_cmd |= (1 << 14);
4545         }
4546
4547         RTL_W16(CPlusCmd, tp->cp_cmd);
4548
4549         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4550
4551         /*
4552          * Undocumented corner. Supposedly:
4553          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4554          */
4555         RTL_W16(IntrMitigate, 0x0000);
4556
4557         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4558
4559         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4560             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4561             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4562             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4563                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4564                 rtl_set_rx_tx_config_registers(tp);
4565         }
4566
4567         RTL_W8(Cfg9346, Cfg9346_Lock);
4568
4569         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4570         RTL_R8(IntrMask);
4571
4572         RTL_W32(RxMissed, 0);
4573
4574         rtl_set_rx_mode(dev);
4575
4576         /* no early-rx interrupts */
4577         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4578 }
4579
4580 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4581 {
4582         u32 csi;
4583
4584         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4585         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4586 }
4587
4588 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4589 {
4590         rtl_csi_access_enable(ioaddr, 0x17000000);
4591 }
4592
4593 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4594 {
4595         rtl_csi_access_enable(ioaddr, 0x27000000);
4596 }
4597
4598 struct ephy_info {
4599         unsigned int offset;
4600         u16 mask;
4601         u16 bits;
4602 };
4603
4604 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4605 {
4606         u16 w;
4607
4608         while (len-- > 0) {
4609                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4610                 rtl_ephy_write(ioaddr, e->offset, w);
4611                 e++;
4612         }
4613 }
4614
4615 static void rtl_disable_clock_request(struct pci_dev *pdev)
4616 {
4617         int cap = pci_pcie_cap(pdev);
4618
4619         if (cap) {
4620                 u16 ctl;
4621
4622                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4623                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4624                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4625         }
4626 }
4627
4628 static void rtl_enable_clock_request(struct pci_dev *pdev)
4629 {
4630         int cap = pci_pcie_cap(pdev);
4631
4632         if (cap) {
4633                 u16 ctl;
4634
4635                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4636                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4637                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4638         }
4639 }
4640
4641 #define R8168_CPCMD_QUIRK_MASK (\
4642         EnableBist | \
4643         Mac_dbgo_oe | \
4644         Force_half_dup | \
4645         Force_rxflow_en | \
4646         Force_txflow_en | \
4647         Cxpl_dbg_sel | \
4648         ASF | \
4649         PktCntrDisable | \
4650         Mac_dbgo_sel)
4651
4652 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4653 {
4654         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4655
4656         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4657
4658         rtl_tx_performance_tweak(pdev,
4659                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4660 }
4661
4662 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4663 {
4664         rtl_hw_start_8168bb(ioaddr, pdev);
4665
4666         RTL_W8(MaxTxPacketSize, TxPacketMax);
4667
4668         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4669 }
4670
4671 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4672 {
4673         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4674
4675         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4676
4677         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4678
4679         rtl_disable_clock_request(pdev);
4680
4681         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4682 }
4683
4684 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4685 {
4686         static const struct ephy_info e_info_8168cp[] = {
4687                 { 0x01, 0,      0x0001 },
4688                 { 0x02, 0x0800, 0x1000 },
4689                 { 0x03, 0,      0x0042 },
4690                 { 0x06, 0x0080, 0x0000 },
4691                 { 0x07, 0,      0x2000 }
4692         };
4693
4694         rtl_csi_access_enable_2(ioaddr);
4695
4696         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4697
4698         __rtl_hw_start_8168cp(ioaddr, pdev);
4699 }
4700
4701 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4702 {
4703         rtl_csi_access_enable_2(ioaddr);
4704
4705         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4706
4707         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4708
4709         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4710 }
4711
4712 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4713 {
4714         rtl_csi_access_enable_2(ioaddr);
4715
4716         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4717
4718         /* Magic. */
4719         RTL_W8(DBG_REG, 0x20);
4720
4721         RTL_W8(MaxTxPacketSize, TxPacketMax);
4722
4723         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4724
4725         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4726 }
4727
4728 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4729 {
4730         static const struct ephy_info e_info_8168c_1[] = {
4731                 { 0x02, 0x0800, 0x1000 },
4732                 { 0x03, 0,      0x0002 },
4733                 { 0x06, 0x0080, 0x0000 }
4734         };
4735
4736         rtl_csi_access_enable_2(ioaddr);
4737
4738         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4739
4740         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4741
4742         __rtl_hw_start_8168cp(ioaddr, pdev);
4743 }
4744
4745 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4746 {
4747         static const struct ephy_info e_info_8168c_2[] = {
4748                 { 0x01, 0,      0x0001 },
4749                 { 0x03, 0x0400, 0x0220 }
4750         };
4751
4752         rtl_csi_access_enable_2(ioaddr);
4753
4754         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4755
4756         __rtl_hw_start_8168cp(ioaddr, pdev);
4757 }
4758
4759 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4760 {
4761         rtl_hw_start_8168c_2(ioaddr, pdev);
4762 }
4763
4764 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4765 {
4766         rtl_csi_access_enable_2(ioaddr);
4767
4768         __rtl_hw_start_8168cp(ioaddr, pdev);
4769 }
4770
4771 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4772 {
4773         rtl_csi_access_enable_2(ioaddr);
4774
4775         rtl_disable_clock_request(pdev);
4776
4777         RTL_W8(MaxTxPacketSize, TxPacketMax);
4778
4779         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4780
4781         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4782 }
4783
4784 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4785 {
4786         rtl_csi_access_enable_1(ioaddr);
4787
4788         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4789
4790         RTL_W8(MaxTxPacketSize, TxPacketMax);
4791
4792         rtl_disable_clock_request(pdev);
4793 }
4794
4795 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4796 {
4797         static const struct ephy_info e_info_8168d_4[] = {
4798                 { 0x0b, ~0,     0x48 },
4799                 { 0x19, 0x20,   0x50 },
4800                 { 0x0c, ~0,     0x20 }
4801         };
4802         int i;
4803
4804         rtl_csi_access_enable_1(ioaddr);
4805
4806         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4807
4808         RTL_W8(MaxTxPacketSize, TxPacketMax);
4809
4810         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4811                 const struct ephy_info *e = e_info_8168d_4 + i;
4812                 u16 w;
4813
4814                 w = rtl_ephy_read(ioaddr, e->offset);
4815                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4816         }
4817
4818         rtl_enable_clock_request(pdev);
4819 }
4820
4821 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4822 {
4823         static const struct ephy_info e_info_8168e_1[] = {
4824                 { 0x00, 0x0200, 0x0100 },
4825                 { 0x00, 0x0000, 0x0004 },
4826                 { 0x06, 0x0002, 0x0001 },
4827                 { 0x06, 0x0000, 0x0030 },
4828                 { 0x07, 0x0000, 0x2000 },
4829                 { 0x00, 0x0000, 0x0020 },
4830                 { 0x03, 0x5800, 0x2000 },
4831                 { 0x03, 0x0000, 0x0001 },
4832                 { 0x01, 0x0800, 0x1000 },
4833                 { 0x07, 0x0000, 0x4000 },
4834                 { 0x1e, 0x0000, 0x2000 },
4835                 { 0x19, 0xffff, 0xfe6c },
4836                 { 0x0a, 0x0000, 0x0040 }
4837         };
4838
4839         rtl_csi_access_enable_2(ioaddr);
4840
4841         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4842
4843         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4844
4845         RTL_W8(MaxTxPacketSize, TxPacketMax);
4846
4847         rtl_disable_clock_request(pdev);
4848
4849         /* Reset tx FIFO pointer */
4850         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4851         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4852
4853         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4854 }
4855
4856 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4857 {
4858         static const struct ephy_info e_info_8168e_2[] = {
4859                 { 0x09, 0x0000, 0x0080 },
4860                 { 0x19, 0x0000, 0x0224 }
4861         };
4862
4863         rtl_csi_access_enable_1(ioaddr);
4864
4865         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4866
4867         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4868
4869         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4870         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4871         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4872         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4873         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4874         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4875         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4876         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4877                      ERIAR_EXGMAC);
4878
4879         RTL_W8(MaxTxPacketSize, EarlySize);
4880
4881         rtl_disable_clock_request(pdev);
4882
4883         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4884         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4885
4886         /* Adjust EEE LED frequency */
4887         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4888
4889         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4890         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4891         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4892 }
4893
4894 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4895 {
4896         static const struct ephy_info e_info_8168f_1[] = {
4897                 { 0x06, 0x00c0, 0x0020 },
4898                 { 0x08, 0x0001, 0x0002 },
4899                 { 0x09, 0x0000, 0x0080 },
4900                 { 0x19, 0x0000, 0x0224 }
4901         };
4902
4903         rtl_csi_access_enable_1(ioaddr);
4904
4905         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4906
4907         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4908
4909         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4910         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4911         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4912         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4913         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4914         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4915         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4916         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4917         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4918         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4919         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4920                      ERIAR_EXGMAC);
4921
4922         RTL_W8(MaxTxPacketSize, EarlySize);
4923
4924         rtl_disable_clock_request(pdev);
4925
4926         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4927         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4928
4929         /* Adjust EEE LED frequency */
4930         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4931
4932         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4933         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4934         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4935 }
4936
4937 static void rtl_hw_start_8168(struct net_device *dev)
4938 {
4939         struct rtl8169_private *tp = netdev_priv(dev);
4940         void __iomem *ioaddr = tp->mmio_addr;
4941         struct pci_dev *pdev = tp->pci_dev;
4942
4943         RTL_W8(Cfg9346, Cfg9346_Unlock);
4944
4945         RTL_W8(MaxTxPacketSize, TxPacketMax);
4946
4947         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4948
4949         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4950
4951         RTL_W16(CPlusCmd, tp->cp_cmd);
4952
4953         RTL_W16(IntrMitigate, 0x5151);
4954
4955         /* Work around for RxFIFO overflow. */
4956         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4957                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4958                 tp->event_slow &= ~RxOverflow;
4959         }
4960
4961         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4962
4963         rtl_set_rx_mode(dev);
4964
4965         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4966                 (InterFrameGap << TxInterFrameGapShift));
4967
4968         RTL_R8(IntrMask);
4969
4970         switch (tp->mac_version) {
4971         case RTL_GIGA_MAC_VER_11:
4972                 rtl_hw_start_8168bb(ioaddr, pdev);
4973                 break;
4974
4975         case RTL_GIGA_MAC_VER_12:
4976         case RTL_GIGA_MAC_VER_17:
4977                 rtl_hw_start_8168bef(ioaddr, pdev);
4978                 break;
4979
4980         case RTL_GIGA_MAC_VER_18:
4981                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4982                 break;
4983
4984         case RTL_GIGA_MAC_VER_19:
4985                 rtl_hw_start_8168c_1(ioaddr, pdev);
4986                 break;
4987
4988         case RTL_GIGA_MAC_VER_20:
4989                 rtl_hw_start_8168c_2(ioaddr, pdev);
4990                 break;
4991
4992         case RTL_GIGA_MAC_VER_21:
4993                 rtl_hw_start_8168c_3(ioaddr, pdev);
4994                 break;
4995
4996         case RTL_GIGA_MAC_VER_22:
4997                 rtl_hw_start_8168c_4(ioaddr, pdev);
4998                 break;
4999
5000         case RTL_GIGA_MAC_VER_23:
5001                 rtl_hw_start_8168cp_2(ioaddr, pdev);
5002                 break;
5003
5004         case RTL_GIGA_MAC_VER_24:
5005                 rtl_hw_start_8168cp_3(ioaddr, pdev);
5006                 break;
5007
5008         case RTL_GIGA_MAC_VER_25:
5009         case RTL_GIGA_MAC_VER_26:
5010         case RTL_GIGA_MAC_VER_27:
5011                 rtl_hw_start_8168d(ioaddr, pdev);
5012                 break;
5013
5014         case RTL_GIGA_MAC_VER_28:
5015                 rtl_hw_start_8168d_4(ioaddr, pdev);
5016                 break;
5017
5018         case RTL_GIGA_MAC_VER_31:
5019                 rtl_hw_start_8168dp(ioaddr, pdev);
5020                 break;
5021
5022         case RTL_GIGA_MAC_VER_32:
5023         case RTL_GIGA_MAC_VER_33:
5024                 rtl_hw_start_8168e_1(ioaddr, pdev);
5025                 break;
5026         case RTL_GIGA_MAC_VER_34:
5027                 rtl_hw_start_8168e_2(ioaddr, pdev);
5028                 break;
5029
5030         case RTL_GIGA_MAC_VER_35:
5031         case RTL_GIGA_MAC_VER_36:
5032                 rtl_hw_start_8168f_1(ioaddr, pdev);
5033                 break;
5034
5035         default:
5036                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5037                         dev->name, tp->mac_version);
5038                 break;
5039         }
5040
5041         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5042
5043         RTL_W8(Cfg9346, Cfg9346_Lock);
5044
5045         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5046 }
5047
5048 #define R810X_CPCMD_QUIRK_MASK (\
5049         EnableBist | \
5050         Mac_dbgo_oe | \
5051         Force_half_dup | \
5052         Force_rxflow_en | \
5053         Force_txflow_en | \
5054         Cxpl_dbg_sel | \
5055         ASF | \
5056         PktCntrDisable | \
5057         Mac_dbgo_sel)
5058
5059 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5060 {
5061         static const struct ephy_info e_info_8102e_1[] = {
5062                 { 0x01, 0, 0x6e65 },
5063                 { 0x02, 0, 0x091f },
5064                 { 0x03, 0, 0xc2f9 },
5065                 { 0x06, 0, 0xafb5 },
5066                 { 0x07, 0, 0x0e00 },
5067                 { 0x19, 0, 0xec80 },
5068                 { 0x01, 0, 0x2e65 },
5069                 { 0x01, 0, 0x6e65 }
5070         };
5071         u8 cfg1;
5072
5073         rtl_csi_access_enable_2(ioaddr);
5074
5075         RTL_W8(DBG_REG, FIX_NAK_1);
5076
5077         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5078
5079         RTL_W8(Config1,
5080                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5081         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5082
5083         cfg1 = RTL_R8(Config1);
5084         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5085                 RTL_W8(Config1, cfg1 & ~LEDS0);
5086
5087         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5088 }
5089
5090 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5091 {
5092         rtl_csi_access_enable_2(ioaddr);
5093
5094         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5095
5096         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5097         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5098 }
5099
5100 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5101 {
5102         rtl_hw_start_8102e_2(ioaddr, pdev);
5103
5104         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5105 }
5106
5107 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5108 {
5109         static const struct ephy_info e_info_8105e_1[] = {
5110                 { 0x07, 0, 0x4000 },
5111                 { 0x19, 0, 0x0200 },
5112                 { 0x19, 0, 0x0020 },
5113                 { 0x1e, 0, 0x2000 },
5114                 { 0x03, 0, 0x0001 },
5115                 { 0x19, 0, 0x0100 },
5116                 { 0x19, 0, 0x0004 },
5117                 { 0x0a, 0, 0x0020 }
5118         };
5119
5120         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5121         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5122
5123         /* Disable Early Tally Counter */
5124         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5125
5126         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5127         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5128
5129         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5130 }
5131
5132 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5133 {
5134         rtl_hw_start_8105e_1(ioaddr, pdev);
5135         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5136 }
5137
5138 static void rtl_hw_start_8101(struct net_device *dev)
5139 {
5140         struct rtl8169_private *tp = netdev_priv(dev);
5141         void __iomem *ioaddr = tp->mmio_addr;
5142         struct pci_dev *pdev = tp->pci_dev;
5143
5144         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5145                 tp->event_slow &= ~RxFIFOOver;
5146
5147         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5148             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5149                 int cap = pci_pcie_cap(pdev);
5150
5151                 if (cap) {
5152                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5153                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5154                 }
5155         }
5156
5157         RTL_W8(Cfg9346, Cfg9346_Unlock);
5158
5159         switch (tp->mac_version) {
5160         case RTL_GIGA_MAC_VER_07:
5161                 rtl_hw_start_8102e_1(ioaddr, pdev);
5162                 break;
5163
5164         case RTL_GIGA_MAC_VER_08:
5165                 rtl_hw_start_8102e_3(ioaddr, pdev);
5166                 break;
5167
5168         case RTL_GIGA_MAC_VER_09:
5169                 rtl_hw_start_8102e_2(ioaddr, pdev);
5170                 break;
5171
5172         case RTL_GIGA_MAC_VER_29:
5173                 rtl_hw_start_8105e_1(ioaddr, pdev);
5174                 break;
5175         case RTL_GIGA_MAC_VER_30:
5176                 rtl_hw_start_8105e_2(ioaddr, pdev);
5177                 break;
5178         }
5179
5180         RTL_W8(Cfg9346, Cfg9346_Lock);
5181
5182         RTL_W8(MaxTxPacketSize, TxPacketMax);
5183
5184         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5185
5186         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5187         RTL_W16(CPlusCmd, tp->cp_cmd);
5188
5189         RTL_W16(IntrMitigate, 0x0000);
5190
5191         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5192
5193         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5194         rtl_set_rx_tx_config_registers(tp);
5195
5196         RTL_R8(IntrMask);
5197
5198         rtl_set_rx_mode(dev);
5199
5200         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5201 }
5202
5203 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5204 {
5205         struct rtl8169_private *tp = netdev_priv(dev);
5206
5207         if (new_mtu < ETH_ZLEN ||
5208             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5209                 return -EINVAL;
5210
5211         if (new_mtu > ETH_DATA_LEN)
5212                 rtl_hw_jumbo_enable(tp);
5213         else
5214                 rtl_hw_jumbo_disable(tp);
5215
5216         dev->mtu = new_mtu;
5217         netdev_update_features(dev);
5218
5219         return 0;
5220 }
5221
5222 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5223 {
5224         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5225         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5226 }
5227
5228 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5229                                      void **data_buff, struct RxDesc *desc)
5230 {
5231         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5232                          DMA_FROM_DEVICE);
5233
5234         kfree(*data_buff);
5235         *data_buff = NULL;
5236         rtl8169_make_unusable_by_asic(desc);
5237 }
5238
5239 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5240 {
5241         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5242
5243         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5244 }
5245
5246 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5247                                        u32 rx_buf_sz)
5248 {
5249         desc->addr = cpu_to_le64(mapping);
5250         wmb();
5251         rtl8169_mark_to_asic(desc, rx_buf_sz);
5252 }
5253
5254 static inline void *rtl8169_align(void *data)
5255 {
5256         return (void *)ALIGN((long)data, 16);
5257 }
5258
5259 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5260                                              struct RxDesc *desc)
5261 {
5262         void *data;
5263         dma_addr_t mapping;
5264         struct device *d = &tp->pci_dev->dev;
5265         struct net_device *dev = tp->dev;
5266         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5267
5268         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5269         if (!data)
5270                 return NULL;
5271
5272         if (rtl8169_align(data) != data) {
5273                 kfree(data);
5274                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5275                 if (!data)
5276                         return NULL;
5277         }
5278
5279         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5280                                  DMA_FROM_DEVICE);
5281         if (unlikely(dma_mapping_error(d, mapping))) {
5282                 if (net_ratelimit())
5283                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5284                 goto err_out;
5285         }
5286
5287         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5288         return data;
5289
5290 err_out:
5291         kfree(data);
5292         return NULL;
5293 }
5294
5295 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5296 {
5297         unsigned int i;
5298
5299         for (i = 0; i < NUM_RX_DESC; i++) {
5300                 if (tp->Rx_databuff[i]) {
5301                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5302                                             tp->RxDescArray + i);
5303                 }
5304         }
5305 }
5306
5307 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5308 {
5309         desc->opts1 |= cpu_to_le32(RingEnd);
5310 }
5311
5312 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5313 {
5314         unsigned int i;
5315
5316         for (i = 0; i < NUM_RX_DESC; i++) {
5317                 void *data;
5318
5319                 if (tp->Rx_databuff[i])
5320                         continue;
5321
5322                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5323                 if (!data) {
5324                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5325                         goto err_out;
5326                 }
5327                 tp->Rx_databuff[i] = data;
5328         }
5329
5330         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5331         return 0;
5332
5333 err_out:
5334         rtl8169_rx_clear(tp);
5335         return -ENOMEM;
5336 }
5337
5338 static int rtl8169_init_ring(struct net_device *dev)
5339 {
5340         struct rtl8169_private *tp = netdev_priv(dev);
5341
5342         rtl8169_init_ring_indexes(tp);
5343
5344         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5345         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5346
5347         return rtl8169_rx_fill(tp);
5348 }
5349
5350 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5351                                  struct TxDesc *desc)
5352 {
5353         unsigned int len = tx_skb->len;
5354
5355         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5356
5357         desc->opts1 = 0x00;
5358         desc->opts2 = 0x00;
5359         desc->addr = 0x00;
5360         tx_skb->len = 0;
5361 }
5362
5363 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5364                                    unsigned int n)
5365 {
5366         unsigned int i;
5367
5368         for (i = 0; i < n; i++) {
5369                 unsigned int entry = (start + i) % NUM_TX_DESC;
5370                 struct ring_info *tx_skb = tp->tx_skb + entry;
5371                 unsigned int len = tx_skb->len;
5372
5373                 if (len) {
5374                         struct sk_buff *skb = tx_skb->skb;
5375
5376                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5377                                              tp->TxDescArray + entry);
5378                         if (skb) {
5379                                 tp->dev->stats.tx_dropped++;
5380                                 dev_kfree_skb(skb);
5381                                 tx_skb->skb = NULL;
5382                         }
5383                 }
5384         }
5385 }
5386
5387 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5388 {
5389         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5390         tp->cur_tx = tp->dirty_tx = 0;
5391 }
5392
5393 static void rtl_reset_work(struct rtl8169_private *tp)
5394 {
5395         struct net_device *dev = tp->dev;
5396         int i;
5397
5398         napi_disable(&tp->napi);
5399         netif_stop_queue(dev);
5400         synchronize_sched();
5401
5402         rtl8169_hw_reset(tp);
5403
5404         for (i = 0; i < NUM_RX_DESC; i++)
5405                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5406
5407         rtl8169_tx_clear(tp);
5408         rtl8169_init_ring_indexes(tp);
5409
5410         napi_enable(&tp->napi);
5411         rtl_hw_start(dev);
5412         netif_wake_queue(dev);
5413         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5414 }
5415
5416 static void rtl8169_tx_timeout(struct net_device *dev)
5417 {
5418         struct rtl8169_private *tp = netdev_priv(dev);
5419
5420         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5421 }
5422
5423 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5424                               u32 *opts)
5425 {
5426         struct skb_shared_info *info = skb_shinfo(skb);
5427         unsigned int cur_frag, entry;
5428         struct TxDesc * uninitialized_var(txd);
5429         struct device *d = &tp->pci_dev->dev;
5430
5431         entry = tp->cur_tx;
5432         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5433                 const skb_frag_t *frag = info->frags + cur_frag;
5434                 dma_addr_t mapping;
5435                 u32 status, len;
5436                 void *addr;
5437
5438                 entry = (entry + 1) % NUM_TX_DESC;
5439
5440                 txd = tp->TxDescArray + entry;
5441                 len = skb_frag_size(frag);
5442                 addr = skb_frag_address(frag);
5443                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5444                 if (unlikely(dma_mapping_error(d, mapping))) {
5445                         if (net_ratelimit())
5446                                 netif_err(tp, drv, tp->dev,
5447                                           "Failed to map TX fragments DMA!\n");
5448                         goto err_out;
5449                 }
5450
5451                 /* Anti gcc 2.95.3 bugware (sic) */
5452                 status = opts[0] | len |
5453                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5454
5455                 txd->opts1 = cpu_to_le32(status);
5456                 txd->opts2 = cpu_to_le32(opts[1]);
5457                 txd->addr = cpu_to_le64(mapping);
5458
5459                 tp->tx_skb[entry].len = len;
5460         }
5461
5462         if (cur_frag) {
5463                 tp->tx_skb[entry].skb = skb;
5464                 txd->opts1 |= cpu_to_le32(LastFrag);
5465         }
5466
5467         return cur_frag;
5468
5469 err_out:
5470         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5471         return -EIO;
5472 }
5473
5474 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5475                                     struct sk_buff *skb, u32 *opts)
5476 {
5477         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5478         u32 mss = skb_shinfo(skb)->gso_size;
5479         int offset = info->opts_offset;
5480
5481         if (mss) {
5482                 opts[0] |= TD_LSO;
5483                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5484         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5485                 const struct iphdr *ip = ip_hdr(skb);
5486
5487                 if (ip->protocol == IPPROTO_TCP)
5488                         opts[offset] |= info->checksum.tcp;
5489                 else if (ip->protocol == IPPROTO_UDP)
5490                         opts[offset] |= info->checksum.udp;
5491                 else
5492                         WARN_ON_ONCE(1);
5493         }
5494 }
5495
5496 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5497                                       struct net_device *dev)
5498 {
5499         struct rtl8169_private *tp = netdev_priv(dev);
5500         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5501         struct TxDesc *txd = tp->TxDescArray + entry;
5502         void __iomem *ioaddr = tp->mmio_addr;
5503         struct device *d = &tp->pci_dev->dev;
5504         dma_addr_t mapping;
5505         u32 status, len;
5506         u32 opts[2];
5507         int frags;
5508
5509         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5510                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5511                 goto err_stop_0;
5512         }
5513
5514         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5515                 goto err_stop_0;
5516
5517         len = skb_headlen(skb);
5518         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5519         if (unlikely(dma_mapping_error(d, mapping))) {
5520                 if (net_ratelimit())
5521                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5522                 goto err_dma_0;
5523         }
5524
5525         tp->tx_skb[entry].len = len;
5526         txd->addr = cpu_to_le64(mapping);
5527
5528         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5529         opts[0] = DescOwn;
5530
5531         rtl8169_tso_csum(tp, skb, opts);
5532
5533         frags = rtl8169_xmit_frags(tp, skb, opts);
5534         if (frags < 0)
5535                 goto err_dma_1;
5536         else if (frags)
5537                 opts[0] |= FirstFrag;
5538         else {
5539                 opts[0] |= FirstFrag | LastFrag;
5540                 tp->tx_skb[entry].skb = skb;
5541         }
5542
5543         txd->opts2 = cpu_to_le32(opts[1]);
5544
5545         wmb();
5546
5547         /* Anti gcc 2.95.3 bugware (sic) */
5548         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5549         txd->opts1 = cpu_to_le32(status);
5550
5551         tp->cur_tx += frags + 1;
5552
5553         wmb();
5554
5555         RTL_W8(TxPoll, NPQ);
5556
5557         mmiowb();
5558
5559         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5560                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5561                  * not miss a ring update when it notices a stopped queue.
5562                  */
5563                 smp_wmb();
5564                 netif_stop_queue(dev);
5565                 /* Sync with rtl_tx:
5566                  * - publish queue status and cur_tx ring index (write barrier)
5567                  * - refresh dirty_tx ring index (read barrier).
5568                  * May the current thread have a pessimistic view of the ring
5569                  * status and forget to wake up queue, a racing rtl_tx thread
5570                  * can't.
5571                  */
5572                 smp_mb();
5573                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5574                         netif_wake_queue(dev);
5575         }
5576
5577         return NETDEV_TX_OK;
5578
5579 err_dma_1:
5580         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5581 err_dma_0:
5582         dev_kfree_skb(skb);
5583         dev->stats.tx_dropped++;
5584         return NETDEV_TX_OK;
5585
5586 err_stop_0:
5587         netif_stop_queue(dev);
5588         dev->stats.tx_dropped++;
5589         return NETDEV_TX_BUSY;
5590 }
5591
5592 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5593 {
5594         struct rtl8169_private *tp = netdev_priv(dev);
5595         struct pci_dev *pdev = tp->pci_dev;
5596         u16 pci_status, pci_cmd;
5597
5598         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5599         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5600
5601         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5602                   pci_cmd, pci_status);
5603
5604         /*
5605          * The recovery sequence below admits a very elaborated explanation:
5606          * - it seems to work;
5607          * - I did not see what else could be done;
5608          * - it makes iop3xx happy.
5609          *
5610          * Feel free to adjust to your needs.
5611          */
5612         if (pdev->broken_parity_status)
5613                 pci_cmd &= ~PCI_COMMAND_PARITY;
5614         else
5615                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5616
5617         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5618
5619         pci_write_config_word(pdev, PCI_STATUS,
5620                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5621                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5622                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5623
5624         /* The infamous DAC f*ckup only happens at boot time */
5625         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5626                 void __iomem *ioaddr = tp->mmio_addr;
5627
5628                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5629                 tp->cp_cmd &= ~PCIDAC;
5630                 RTL_W16(CPlusCmd, tp->cp_cmd);
5631                 dev->features &= ~NETIF_F_HIGHDMA;
5632         }
5633
5634         rtl8169_hw_reset(tp);
5635
5636         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5637 }
5638
5639 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5640 {
5641         unsigned int dirty_tx, tx_left;
5642
5643         dirty_tx = tp->dirty_tx;
5644         smp_rmb();
5645         tx_left = tp->cur_tx - dirty_tx;
5646
5647         while (tx_left > 0) {
5648                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5649                 struct ring_info *tx_skb = tp->tx_skb + entry;
5650                 u32 status;
5651
5652                 rmb();
5653                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5654                 if (status & DescOwn)
5655                         break;
5656
5657                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5658                                      tp->TxDescArray + entry);
5659                 if (status & LastFrag) {
5660                         dev->stats.tx_packets++;
5661                         dev->stats.tx_bytes += tx_skb->skb->len;
5662                         dev_kfree_skb(tx_skb->skb);
5663                         tx_skb->skb = NULL;
5664                 }
5665                 dirty_tx++;
5666                 tx_left--;
5667         }
5668
5669         if (tp->dirty_tx != dirty_tx) {
5670                 tp->dirty_tx = dirty_tx;
5671                 /* Sync with rtl8169_start_xmit:
5672                  * - publish dirty_tx ring index (write barrier)
5673                  * - refresh cur_tx ring index and queue status (read barrier)
5674                  * May the current thread miss the stopped queue condition,
5675                  * a racing xmit thread can only have a right view of the
5676                  * ring status.
5677                  */
5678                 smp_mb();
5679                 if (netif_queue_stopped(dev) &&
5680                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5681                         netif_wake_queue(dev);
5682                 }
5683                 /*
5684                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5685                  * too close. Let's kick an extra TxPoll request when a burst
5686                  * of start_xmit activity is detected (if it is not detected,
5687                  * it is slow enough). -- FR
5688                  */
5689                 if (tp->cur_tx != dirty_tx) {
5690                         void __iomem *ioaddr = tp->mmio_addr;
5691
5692                         RTL_W8(TxPoll, NPQ);
5693                 }
5694         }
5695 }
5696
5697 static inline int rtl8169_fragmented_frame(u32 status)
5698 {
5699         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5700 }
5701
5702 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5703 {
5704         u32 status = opts1 & RxProtoMask;
5705
5706         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5707             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5708                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5709         else
5710                 skb_checksum_none_assert(skb);
5711 }
5712
5713 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5714                                            struct rtl8169_private *tp,
5715                                            int pkt_size,
5716                                            dma_addr_t addr)
5717 {
5718         struct sk_buff *skb;
5719         struct device *d = &tp->pci_dev->dev;
5720
5721         data = rtl8169_align(data);
5722         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5723         prefetch(data);
5724         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5725         if (skb)
5726                 memcpy(skb->data, data, pkt_size);
5727         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5728
5729         return skb;
5730 }
5731
5732 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5733 {
5734         unsigned int cur_rx, rx_left;
5735         unsigned int count;
5736
5737         cur_rx = tp->cur_rx;
5738         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5739         rx_left = min(rx_left, budget);
5740
5741         for (; rx_left > 0; rx_left--, cur_rx++) {
5742                 unsigned int entry = cur_rx % NUM_RX_DESC;
5743                 struct RxDesc *desc = tp->RxDescArray + entry;
5744                 u32 status;
5745
5746                 rmb();
5747                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5748
5749                 if (status & DescOwn)
5750                         break;
5751                 if (unlikely(status & RxRES)) {
5752                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5753                                    status);
5754                         dev->stats.rx_errors++;
5755                         if (status & (RxRWT | RxRUNT))
5756                                 dev->stats.rx_length_errors++;
5757                         if (status & RxCRC)
5758                                 dev->stats.rx_crc_errors++;
5759                         if (status & RxFOVF) {
5760                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5761                                 dev->stats.rx_fifo_errors++;
5762                         }
5763                         if ((status & (RxRUNT | RxCRC)) &&
5764                             !(status & (RxRWT | RxFOVF)) &&
5765                             (dev->features & NETIF_F_RXALL))
5766                                 goto process_pkt;
5767
5768                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5769                 } else {
5770                         struct sk_buff *skb;
5771                         dma_addr_t addr;
5772                         int pkt_size;
5773
5774 process_pkt:
5775                         addr = le64_to_cpu(desc->addr);
5776                         pkt_size = (status & 0x00003fff) - 4;
5777
5778                         /*
5779                          * The driver does not support incoming fragmented
5780                          * frames. They are seen as a symptom of over-mtu
5781                          * sized frames.
5782                          */
5783                         if (unlikely(rtl8169_fragmented_frame(status))) {
5784                                 dev->stats.rx_dropped++;
5785                                 dev->stats.rx_length_errors++;
5786                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5787                                 continue;
5788                         }
5789
5790                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5791                                                   tp, pkt_size, addr);
5792                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5793                         if (!skb) {
5794                                 dev->stats.rx_dropped++;
5795                                 continue;
5796                         }
5797
5798                         rtl8169_rx_csum(skb, status);
5799                         skb_put(skb, pkt_size);
5800                         skb->protocol = eth_type_trans(skb, dev);
5801
5802                         rtl8169_rx_vlan_tag(desc, skb);
5803
5804                         napi_gro_receive(&tp->napi, skb);
5805
5806                         dev->stats.rx_bytes += pkt_size;
5807                         dev->stats.rx_packets++;
5808                 }
5809
5810                 /* Work around for AMD plateform. */
5811                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5812                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5813                         desc->opts2 = 0;
5814                         cur_rx++;
5815                 }
5816         }
5817
5818         count = cur_rx - tp->cur_rx;
5819         tp->cur_rx = cur_rx;
5820
5821         tp->dirty_rx += count;
5822
5823         return count;
5824 }
5825
5826 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5827 {
5828         struct net_device *dev = dev_instance;
5829         struct rtl8169_private *tp = netdev_priv(dev);
5830         int handled = 0;
5831         u16 status;
5832
5833         status = rtl_get_events(tp);
5834         if (status && status != 0xffff) {
5835                 status &= RTL_EVENT_NAPI | tp->event_slow;
5836                 if (status) {
5837                         handled = 1;
5838
5839                         rtl_irq_disable(tp);
5840                         napi_schedule(&tp->napi);
5841                 }
5842         }
5843         return IRQ_RETVAL(handled);
5844 }
5845
5846 /*
5847  * Workqueue context.
5848  */
5849 static void rtl_slow_event_work(struct rtl8169_private *tp)
5850 {
5851         struct net_device *dev = tp->dev;
5852         u16 status;
5853
5854         status = rtl_get_events(tp) & tp->event_slow;
5855         rtl_ack_events(tp, status);
5856
5857         if (unlikely(status & RxFIFOOver)) {
5858                 switch (tp->mac_version) {
5859                 /* Work around for rx fifo overflow */
5860                 case RTL_GIGA_MAC_VER_11:
5861                         netif_stop_queue(dev);
5862                         /* XXX - Hack alert. See rtl_task(). */
5863                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5864                 default:
5865                         break;
5866                 }
5867         }
5868
5869         if (unlikely(status & SYSErr))
5870                 rtl8169_pcierr_interrupt(dev);
5871
5872         if (status & LinkChg)
5873                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5874
5875         napi_disable(&tp->napi);
5876         rtl_irq_disable(tp);
5877
5878         napi_enable(&tp->napi);
5879         napi_schedule(&tp->napi);
5880 }
5881
5882 static void rtl_task(struct work_struct *work)
5883 {
5884         static const struct {
5885                 int bitnr;
5886                 void (*action)(struct rtl8169_private *);
5887         } rtl_work[] = {
5888                 /* XXX - keep rtl_slow_event_work() as first element. */
5889                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5890                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5891                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5892         };
5893         struct rtl8169_private *tp =
5894                 container_of(work, struct rtl8169_private, wk.work);
5895         struct net_device *dev = tp->dev;
5896         int i;
5897
5898         rtl_lock_work(tp);
5899
5900         if (!netif_running(dev) ||
5901             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5902                 goto out_unlock;
5903
5904         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5905                 bool pending;
5906
5907                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5908                 if (pending)
5909                         rtl_work[i].action(tp);
5910         }
5911
5912 out_unlock:
5913         rtl_unlock_work(tp);
5914 }
5915
5916 static int rtl8169_poll(struct napi_struct *napi, int budget)
5917 {
5918         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5919         struct net_device *dev = tp->dev;
5920         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5921         int work_done= 0;
5922         u16 status;
5923
5924         status = rtl_get_events(tp);
5925         rtl_ack_events(tp, status & ~tp->event_slow);
5926
5927         if (status & RTL_EVENT_NAPI_RX)
5928                 work_done = rtl_rx(dev, tp, (u32) budget);
5929
5930         if (status & RTL_EVENT_NAPI_TX)
5931                 rtl_tx(dev, tp);
5932
5933         if (status & tp->event_slow) {
5934                 enable_mask &= ~tp->event_slow;
5935
5936                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5937         }
5938
5939         if (work_done < budget) {
5940                 napi_complete(napi);
5941
5942                 rtl_irq_enable(tp, enable_mask);
5943                 mmiowb();
5944         }
5945
5946         return work_done;
5947 }
5948
5949 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5950 {
5951         struct rtl8169_private *tp = netdev_priv(dev);
5952
5953         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5954                 return;
5955
5956         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5957         RTL_W32(RxMissed, 0);
5958 }
5959
5960 static void rtl8169_down(struct net_device *dev)
5961 {
5962         struct rtl8169_private *tp = netdev_priv(dev);
5963         void __iomem *ioaddr = tp->mmio_addr;
5964
5965         del_timer_sync(&tp->timer);
5966
5967         napi_disable(&tp->napi);
5968         netif_stop_queue(dev);
5969
5970         rtl8169_hw_reset(tp);
5971         /*
5972          * At this point device interrupts can not be enabled in any function,
5973          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5974          * and napi is disabled (rtl8169_poll).
5975          */
5976         rtl8169_rx_missed(dev, ioaddr);
5977
5978         /* Give a racing hard_start_xmit a few cycles to complete. */
5979         synchronize_sched();
5980
5981         rtl8169_tx_clear(tp);
5982
5983         rtl8169_rx_clear(tp);
5984
5985         rtl_pll_power_down(tp);
5986 }
5987
5988 static int rtl8169_close(struct net_device *dev)
5989 {
5990         struct rtl8169_private *tp = netdev_priv(dev);
5991         struct pci_dev *pdev = tp->pci_dev;
5992
5993         pm_runtime_get_sync(&pdev->dev);
5994
5995         /* Update counters before going down */
5996         rtl8169_update_counters(dev);
5997
5998         rtl_lock_work(tp);
5999         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6000
6001         rtl8169_down(dev);
6002         rtl_unlock_work(tp);
6003
6004         free_irq(dev->irq, dev);
6005
6006         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6007                           tp->RxPhyAddr);
6008         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6009                           tp->TxPhyAddr);
6010         tp->TxDescArray = NULL;
6011         tp->RxDescArray = NULL;
6012
6013         pm_runtime_put_sync(&pdev->dev);
6014
6015         return 0;
6016 }
6017
6018 static void rtl_set_rx_mode(struct net_device *dev)
6019 {
6020         struct rtl8169_private *tp = netdev_priv(dev);
6021         void __iomem *ioaddr = tp->mmio_addr;
6022         u32 mc_filter[2];       /* Multicast hash filter */
6023         int rx_mode;
6024         u32 tmp = 0;
6025
6026         if (dev->flags & IFF_PROMISC) {
6027                 /* Unconditionally log net taps. */
6028                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6029                 rx_mode =
6030                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6031                     AcceptAllPhys;
6032                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6033         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6034                    (dev->flags & IFF_ALLMULTI)) {
6035                 /* Too many to filter perfectly -- accept all multicasts. */
6036                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6037                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6038         } else {
6039                 struct netdev_hw_addr *ha;
6040
6041                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6042                 mc_filter[1] = mc_filter[0] = 0;
6043                 netdev_for_each_mc_addr(ha, dev) {
6044                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6045                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6046                         rx_mode |= AcceptMulticast;
6047                 }
6048         }
6049
6050         if (dev->features & NETIF_F_RXALL)
6051                 rx_mode |= (AcceptErr | AcceptRunt);
6052
6053         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6054
6055         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6056                 u32 data = mc_filter[0];
6057
6058                 mc_filter[0] = swab32(mc_filter[1]);
6059                 mc_filter[1] = swab32(data);
6060         }
6061
6062         RTL_W32(MAR0 + 4, mc_filter[1]);
6063         RTL_W32(MAR0 + 0, mc_filter[0]);
6064
6065         RTL_W32(RxConfig, tmp);
6066 }
6067
6068 /**
6069  *  rtl8169_get_stats - Get rtl8169 read/write statistics
6070  *  @dev: The Ethernet Device to get statistics for
6071  *
6072  *  Get TX/RX statistics for rtl8169
6073  */
6074 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6075 {
6076         struct rtl8169_private *tp = netdev_priv(dev);
6077         void __iomem *ioaddr = tp->mmio_addr;
6078
6079         if (netif_running(dev))
6080                 rtl8169_rx_missed(dev, ioaddr);
6081
6082         return &dev->stats;
6083 }
6084
6085 static void rtl8169_net_suspend(struct net_device *dev)
6086 {
6087         struct rtl8169_private *tp = netdev_priv(dev);
6088
6089         if (!netif_running(dev))
6090                 return;
6091
6092         netif_device_detach(dev);
6093         netif_stop_queue(dev);
6094
6095         rtl_lock_work(tp);
6096         napi_disable(&tp->napi);
6097         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6098         rtl_unlock_work(tp);
6099
6100         rtl_pll_power_down(tp);
6101 }
6102
6103 #ifdef CONFIG_PM
6104
6105 static int rtl8169_suspend(struct device *device)
6106 {
6107         struct pci_dev *pdev = to_pci_dev(device);
6108         struct net_device *dev = pci_get_drvdata(pdev);
6109
6110         rtl8169_net_suspend(dev);
6111
6112         return 0;
6113 }
6114
6115 static void __rtl8169_resume(struct net_device *dev)
6116 {
6117         struct rtl8169_private *tp = netdev_priv(dev);
6118
6119         netif_device_attach(dev);
6120
6121         rtl_pll_power_up(tp);
6122
6123         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6124
6125         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6126 }
6127
6128 static int rtl8169_resume(struct device *device)
6129 {
6130         struct pci_dev *pdev = to_pci_dev(device);
6131         struct net_device *dev = pci_get_drvdata(pdev);
6132         struct rtl8169_private *tp = netdev_priv(dev);
6133
6134         rtl8169_init_phy(dev, tp);
6135
6136         if (netif_running(dev))
6137                 __rtl8169_resume(dev);
6138
6139         return 0;
6140 }
6141
6142 static int rtl8169_runtime_suspend(struct device *device)
6143 {
6144         struct pci_dev *pdev = to_pci_dev(device);
6145         struct net_device *dev = pci_get_drvdata(pdev);
6146         struct rtl8169_private *tp = netdev_priv(dev);
6147
6148         if (!tp->TxDescArray)
6149                 return 0;
6150
6151         rtl_lock_work(tp);
6152         tp->saved_wolopts = __rtl8169_get_wol(tp);
6153         __rtl8169_set_wol(tp, WAKE_ANY);
6154         rtl_unlock_work(tp);
6155
6156         rtl8169_net_suspend(dev);
6157
6158         return 0;
6159 }
6160
6161 static int rtl8169_runtime_resume(struct device *device)
6162 {
6163         struct pci_dev *pdev = to_pci_dev(device);
6164         struct net_device *dev = pci_get_drvdata(pdev);
6165         struct rtl8169_private *tp = netdev_priv(dev);
6166
6167         if (!tp->TxDescArray)
6168                 return 0;
6169
6170         rtl_lock_work(tp);
6171         __rtl8169_set_wol(tp, tp->saved_wolopts);
6172         tp->saved_wolopts = 0;
6173         rtl_unlock_work(tp);
6174
6175         rtl8169_init_phy(dev, tp);
6176
6177         __rtl8169_resume(dev);
6178
6179         return 0;
6180 }
6181
6182 static int rtl8169_runtime_idle(struct device *device)
6183 {
6184         struct pci_dev *pdev = to_pci_dev(device);
6185         struct net_device *dev = pci_get_drvdata(pdev);
6186         struct rtl8169_private *tp = netdev_priv(dev);
6187
6188         return tp->TxDescArray ? -EBUSY : 0;
6189 }
6190
6191 static const struct dev_pm_ops rtl8169_pm_ops = {
6192         .suspend                = rtl8169_suspend,
6193         .resume                 = rtl8169_resume,
6194         .freeze                 = rtl8169_suspend,
6195         .thaw                   = rtl8169_resume,
6196         .poweroff               = rtl8169_suspend,
6197         .restore                = rtl8169_resume,
6198         .runtime_suspend        = rtl8169_runtime_suspend,
6199         .runtime_resume         = rtl8169_runtime_resume,
6200         .runtime_idle           = rtl8169_runtime_idle,
6201 };
6202
6203 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6204
6205 #else /* !CONFIG_PM */
6206
6207 #define RTL8169_PM_OPS  NULL
6208
6209 #endif /* !CONFIG_PM */
6210
6211 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6212 {
6213         void __iomem *ioaddr = tp->mmio_addr;
6214
6215         /* WoL fails with 8168b when the receiver is disabled. */
6216         switch (tp->mac_version) {
6217         case RTL_GIGA_MAC_VER_11:
6218         case RTL_GIGA_MAC_VER_12:
6219         case RTL_GIGA_MAC_VER_17:
6220                 pci_clear_master(tp->pci_dev);
6221
6222                 RTL_W8(ChipCmd, CmdRxEnb);
6223                 /* PCI commit */
6224                 RTL_R8(ChipCmd);
6225                 break;
6226         default:
6227                 break;
6228         }
6229 }
6230
6231 static void rtl_shutdown(struct pci_dev *pdev)
6232 {
6233         struct net_device *dev = pci_get_drvdata(pdev);
6234         struct rtl8169_private *tp = netdev_priv(dev);
6235
6236         rtl8169_net_suspend(dev);
6237
6238         /* Restore original MAC address */
6239         rtl_rar_set(tp, dev->perm_addr);
6240
6241         rtl8169_hw_reset(tp);
6242
6243         if (system_state == SYSTEM_POWER_OFF) {
6244                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6245                         rtl_wol_suspend_quirk(tp);
6246                         rtl_wol_shutdown_quirk(tp);
6247                 }
6248
6249                 pci_wake_from_d3(pdev, true);
6250                 pci_set_power_state(pdev, PCI_D3hot);
6251         }
6252 }
6253
6254 static struct pci_driver rtl8169_pci_driver = {
6255         .name           = MODULENAME,
6256         .id_table       = rtl8169_pci_tbl,
6257         .probe          = rtl8169_init_one,
6258         .remove         = __devexit_p(rtl8169_remove_one),
6259         .shutdown       = rtl_shutdown,
6260         .driver.pm      = RTL8169_PM_OPS,
6261 };
6262
6263 static int __init rtl8169_init_module(void)
6264 {
6265         return pci_register_driver(&rtl8169_pci_driver);
6266 }
6267
6268 static void __exit rtl8169_cleanup_module(void)
6269 {
6270         pci_unregister_driver(&rtl8169_pci_driver);
6271 }
6272
6273 module_init(rtl8169_init_module);
6274 module_exit(rtl8169_cleanup_module);