drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         adapter->netdev->trans_start = jiffies;
 386
 387         return 0;
 388 }
 389
 390 /**
 391  * qlcnic_83xx_idc_detach_driver
 392  *
 393  * @adapter: adapter structure
 394  * Detach net interface, stop TX and cleanup resources before the HW reset.
 395  * Returns: None
 396  *
 397  **/
 398 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 399 {
 400         int i;
 401         struct net_device *netdev = adapter->netdev;
 402
 403         netif_device_detach(netdev);
 404
 405         /* Disable mailbox interrupt */
 406         qlcnic_83xx_disable_mbx_intr(adapter);
 407         qlcnic_down(adapter, netdev);
 408         for (i = 0; i < adapter->ahw->num_msix; i++) {
 409                 adapter->ahw->intr_tbl[i].id = i;
 410                 adapter->ahw->intr_tbl[i].enabled = 0;
 411                 adapter->ahw->intr_tbl[i].src = 0;
 412         }
 413
 414         if (qlcnic_sriov_pf_check(adapter))
 415                 qlcnic_sriov_pf_reset(adapter);
 416 }
 417
 418 /**
 419  * qlcnic_83xx_idc_attach_driver
 420  *
 421  * @adapter: adapter structure
 422  *
 423  * Re-attach and re-enable net interface
 424  * Returns: None
 425  *
 426  **/
 427 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 428 {
 429         struct net_device *netdev = adapter->netdev;
 430
 431         if (netif_running(netdev)) {
 432                 if (qlcnic_up(adapter, netdev))
 433                         goto done;
 434                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 435         }
 436 done:
 437         netif_device_attach(netdev);
 438 }
 439
 440 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 441                                               int lock)
 442 {
 443         if (lock) {
 444                 if (qlcnic_83xx_lock_driver(adapter))
 445                         return -EBUSY;
 446         }
 447
 448         qlcnic_83xx_idc_clear_registers(adapter, 0);
 449         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 450         if (lock)
 451                 qlcnic_83xx_unlock_driver(adapter);
 452
 453         qlcnic_83xx_idc_log_state_history(adapter);
 454         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 455
 456         return 0;
 457 }
 458
 459 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 460                                             int lock)
 461 {
 462         if (lock) {
 463                 if (qlcnic_83xx_lock_driver(adapter))
 464                         return -EBUSY;
 465         }
 466
 467         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 468
 469         if (lock)
 470                 qlcnic_83xx_unlock_driver(adapter);
 471
 472         return 0;
 473 }
 474
 475 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 476                                               int lock)
 477 {
 478         if (lock) {
 479                 if (qlcnic_83xx_lock_driver(adapter))
 480                         return -EBUSY;
 481         }
 482
 483         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 484                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 485
 486         if (lock)
 487                 qlcnic_83xx_unlock_driver(adapter);
 488
 489         return 0;
 490 }
 491
 492 static int
 493 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 494 {
 495         if (lock) {
 496                 if (qlcnic_83xx_lock_driver(adapter))
 497                         return -EBUSY;
 498         }
 499
 500         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 501                QLC_83XX_IDC_DEV_NEED_RESET);
 502
 503         if (lock)
 504                 qlcnic_83xx_unlock_driver(adapter);
 505
 506         return 0;
 507 }
 508
 509 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 510                                              int lock)
 511 {
 512         if (lock) {
 513                 if (qlcnic_83xx_lock_driver(adapter))
 514                         return -EBUSY;
 515         }
 516
 517         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 518         if (lock)
 519                 qlcnic_83xx_unlock_driver(adapter);
 520
 521         return 0;
 522 }
 523
 524 /**
 525  * qlcnic_83xx_idc_find_reset_owner_id
 526  *
 527  * @adapter: adapter structure
 528  *
 529  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 530  * Within the same class, function with lowest PCI ID assumes ownership
 531  *
 532  * Returns: reset owner id or failure indication (-EIO)
 533  *
 534  **/
 535 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 536 {
 537         u32 reg, reg1, reg2, i, j, owner, class;
 538
 539         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 540         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 541         owner = QLCNIC_TYPE_NIC;
 542         i = 0;
 543         j = 0;
 544         reg = reg1;
 545
 546         do {
 547                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 548                 if (class == owner)
 549                         break;
 550                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 551                         reg = reg2;
 552                         j = 0;
 553                 } else {
 554                         j++;
 555                 }
 556
 557                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 558                         if (owner == QLCNIC_TYPE_NIC)
 559                                 owner = QLCNIC_TYPE_ISCSI;
 560                         else if (owner == QLCNIC_TYPE_ISCSI)
 561                                 owner = QLCNIC_TYPE_FCOE;
 562                         else if (owner == QLCNIC_TYPE_FCOE)
 563                                 return -EIO;
 564                         reg = reg1;
 565                         j = 0;
 566                         i = 0;
 567                 }
 568         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 569
 570         return i;
 571 }
 572
 573 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 574 {
 575         int ret = 0;
 576
 577         ret = qlcnic_83xx_restart_hw(adapter);
 578
 579         if (ret) {
 580                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 581         } else {
 582                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 583                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 584         }
 585
 586         return ret;
 587 }
 588
 589 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 590 {
 591         u32 status;
 592
 593         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 594
 595         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 596                 dev_err(&adapter->pdev->dev,
 597                         "peg halt status1=0x%x\n", status);
 598                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 599                         dev_err(&adapter->pdev->dev,
 600                                 "On board active cooling fan failed. "
 601                                 "Device has been halted.\n");
 602                         dev_err(&adapter->pdev->dev,
 603                                 "Replace the adapter.\n");
 604                         return -EIO;
 605                 }
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 612 {
 613         int err;
 614
 615         /* register for NIC IDC AEN Events */
 616         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 617
 618         err = qlcnic_sriov_pf_reinit(adapter);
 619         if (err)
 620                 return err;
 621
 622         qlcnic_83xx_enable_mbx_intrpt(adapter);
 623
 624         if (qlcnic_83xx_configure_opmode(adapter)) {
 625                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 626                 return -EIO;
 627         }
 628
 629         if (adapter->nic_ops->init_driver(adapter)) {
 630                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 631                 return -EIO;
 632         }
 633
 634         qlcnic_83xx_idc_attach_driver(adapter);
 635
 636         return 0;
 637 }
 638
 639 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 640 {
 641         struct qlcnic_hardware_context *ahw = adapter->ahw;
 642
 643         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 644         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 645         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 646         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 647
 648         ahw->idc.quiesce_req = 0;
 649         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 650         ahw->idc.err_code = 0;
 651         ahw->idc.collect_dump = 0;
 652         ahw->reset_context = 0;
 653         adapter->tx_timeo_cnt = 0;
 654
 655         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 656 }
 657
 658 /**
 659  * qlcnic_83xx_idc_ready_state_entry
 660  *
 661  * @adapter: adapter structure
 662  *
 663  * Perform ready state initialization, this routine will get invoked only
 664  * once from READY state.
 665  *
 666  * Returns: Error code or Success(0)
 667  *
 668  **/
 669 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 670 {
 671         struct qlcnic_hardware_context *ahw = adapter->ahw;
 672
 673         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 674                 qlcnic_83xx_idc_update_idc_params(adapter);
 675                 /* Re-attach the device if required */
 676                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 677                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 678                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 679                                 return -EIO;
 680                 }
 681         }
 682
 683         return 0;
 684 }
 685
 686 /**
 687  * qlcnic_83xx_idc_vnic_pf_entry
 688  *
 689  * @adapter: adapter structure
 690  *
 691  * Ensure vNIC mode privileged function starts only after vNIC mode is
 692  * enabled by management function.
 693  * If vNIC mode is ready, start initialization.
 694  *
 695  * Returns: -EIO or 0
 696  *
 697  **/
 698 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 699 {
 700         u32 state;
 701         struct qlcnic_hardware_context *ahw = adapter->ahw;
 702
 703         /* Privileged function waits till mgmt function enables VNIC mode */
 704         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 705         if (state != QLCNIC_DEV_NPAR_OPER) {
 706                 if (!ahw->idc.vnic_wait_limit--) {
 707                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 708                         return -EIO;
 709                 }
 710                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 711                 return -EIO;
 712
 713         } else {
 714                 /* Perform one time initialization from ready state */
 715                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 716                         qlcnic_83xx_idc_update_idc_params(adapter);
 717
 718                         /* If the previous state is UNKNOWN, device will be
 719                            already attached properly by Init routine*/
 720                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 721                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 722                                         return -EIO;
 723                         }
 724                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 725                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 726                 }
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 733 {
 734         adapter->ahw->idc.err_code = -EIO;
 735         dev_err(&adapter->pdev->dev,
 736                 "%s: Device in unknown state\n", __func__);
 737         return 0;
 738 }
 739
 740 /**
 741  * qlcnic_83xx_idc_cold_state
 742  *
 743  * @adapter: adapter structure
 744  *
 745  * If HW is up and running device will enter READY state.
 746  * If firmware image from host needs to be loaded, device is
 747  * forced to start with the file firmware image.
 748  *
 749  * Returns: Error code or Success(0)
 750  *
 751  **/
 752 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 753 {
 754         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 755         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 756
 757         if (qlcnic_load_fw_file) {
 758                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 759         } else {
 760                 if (qlcnic_83xx_check_hw_status(adapter)) {
 761                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 762                         return -EIO;
 763                 } else {
 764                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 765                 }
 766         }
 767         return 0;
 768 }
 769
 770 /**
 771  * qlcnic_83xx_idc_init_state
 772  *
 773  * @adapter: adapter structure
 774  *
 775  * Reset owner will restart the device from this state.
 776  * Device will enter failed state if it remains
 777  * in this state for more than DEV_INIT time limit.
 778  *
 779  * Returns: Error code or Success(0)
 780  *
 781  **/
 782 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 783 {
 784         int timeout, ret = 0;
 785         u32 owner;
 786
 787         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 788         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 789                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 790                 if (adapter->ahw->pci_func == owner)
 791                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 792         } else {
 793                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 794                 return ret;
 795         }
 796
 797         return ret;
 798 }
 799
 800 /**
 801  * qlcnic_83xx_idc_ready_state
 802  *
 803  * @adapter: adapter structure
 804  *
 805  * Perform IDC protocol specicifed actions after monitoring device state and
 806  * events.
 807  *
 808  * Returns: Error code or Success(0)
 809  *
 810  **/
 811 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 812 {
 813         u32 val;
 814         struct qlcnic_hardware_context *ahw = adapter->ahw;
 815         int ret = 0;
 816
 817         /* Perform NIC configuration based ready state entry actions */
 818         if (ahw->idc.state_entry(adapter))
 819                 return -EIO;
 820
 821         if (qlcnic_check_temp(adapter)) {
 822                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 823                         qlcnic_83xx_idc_check_fan_failure(adapter);
 824                         dev_err(&adapter->pdev->dev,
 825                                 "Error: device temperature %d above limits\n",
 826                                 adapter->ahw->temp);
 827                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 828                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 829                         qlcnic_83xx_idc_detach_driver(adapter);
 830                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 831                         return -EIO;
 832                 }
 833         }
 834
 835         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 836         ret = qlcnic_83xx_check_heartbeat(adapter);
 837         if (ret) {
 838                 adapter->flags |= QLCNIC_FW_HANG;
 839                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 840                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 841                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 842                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 843                 }
 844                 return -EIO;
 845         }
 846
 847         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 848                 /* Move to need reset state and prepare for reset */
 849                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 850                 return ret;
 851         }
 852
 853         /* Check for soft reset request */
 854         if (ahw->reset_context &&
 855             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 856                 adapter->ahw->reset_context = 0;
 857                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 858                 return ret;
 859         }
 860
 861         /* Move to need quiesce state if requested */
 862         if (adapter->ahw->idc.quiesce_req) {
 863                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 864                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 865                 return ret;
 866         }
 867
 868         return ret;
 869 }
 870
 871 /**
 872  * qlcnic_83xx_idc_need_reset_state
 873  *
 874  * @adapter: adapter structure
 875  *
 876  * Device will remain in this state until:
 877  *      Reset request ACK's are recieved from all the functions
 878  *      Wait time exceeds max time limit
 879  *
 880  * Returns: Error code or Success(0)
 881  *
 882  **/
 883 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 884 {
 885         int ret = 0;
 886
 887         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 888                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 889                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 890                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 891                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 892                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 893                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 894                 qlcnic_83xx_idc_detach_driver(adapter);
 895         }
 896
 897         /* Check ACK from other functions */
 898         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 899         if (ret) {
 900                 dev_info(&adapter->pdev->dev,
 901                          "%s: Waiting for reset ACK\n", __func__);
 902                 return 0;
 903         }
 904
 905         /* Transit to INIT state and restart the HW */
 906         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 907
 908         return ret;
 909 }
 910
 911 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 912 {
 913         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 914         return 0;
 915 }
 916
 917 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 918 {
 919         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 920         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 921         adapter->ahw->idc.err_code = -EIO;
 922
 923         return 0;
 924 }
 925
 926 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 927 {
 928         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 929         return 0;
 930 }
 931
 932 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 933                                                 u32 state)
 934 {
 935         u32 cur, prev, next;
 936
 937         cur = adapter->ahw->idc.curr_state;
 938         prev = adapter->ahw->idc.prev_state;
 939         next = state;
 940
 941         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 942             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 943                 dev_err(&adapter->pdev->dev,
 944                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 945                         __func__, cur, prev, state);
 946                 return 1;
 947         }
 948
 949         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 950             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 951                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 952                     (next != QLC_83XX_IDC_DEV_READY)) {
 953                         dev_err(&adapter->pdev->dev,
 954                                 "%s: failed, cur %d prev %d next %d\n",
 955                                 __func__, cur, prev, next);
 956                         return 1;
 957                 }
 958         }
 959
 960         if (next == QLC_83XX_IDC_DEV_INIT) {
 961                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 962                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 963                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 964                         dev_err(&adapter->pdev->dev,
 965                                 "%s: failed, cur %d prev %d next %d\n",
 966                                 __func__, cur, prev, next);
 967                         return 1;
 968                 }
 969         }
 970
 971         return 0;
 972 }
 973
 974 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 975 {
 976         if (adapter->fhash.fnum)
 977                 qlcnic_prune_lb_filters(adapter);
 978 }
 979
 980 /**
 981  * qlcnic_83xx_idc_poll_dev_state
 982  *
 983  * @work: kernel work queue structure used to schedule the function
 984  *
 985  * Poll device state periodically and perform state specific
 986  * actions defined by Inter Driver Communication (IDC) protocol.
 987  *
 988  * Returns: None
 989  *
 990  **/
 991 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 992 {
 993         struct qlcnic_adapter *adapter;
 994         u32 state;
 995
 996         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 997         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 998
 999         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1000                 qlcnic_83xx_idc_log_state_history(adapter);
1001                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1002         } else {
1003                 adapter->ahw->idc.curr_state = state;
1004         }
1005
1006         switch (adapter->ahw->idc.curr_state) {
1007         case QLC_83XX_IDC_DEV_READY:
1008                 qlcnic_83xx_idc_ready_state(adapter);
1009                 break;
1010         case QLC_83XX_IDC_DEV_NEED_RESET:
1011                 qlcnic_83xx_idc_need_reset_state(adapter);
1012                 break;
1013         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1014                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1015                 break;
1016         case QLC_83XX_IDC_DEV_FAILED:
1017                 qlcnic_83xx_idc_failed_state(adapter);
1018                 return;
1019         case QLC_83XX_IDC_DEV_INIT:
1020                 qlcnic_83xx_idc_init_state(adapter);
1021                 break;
1022         case QLC_83XX_IDC_DEV_QUISCENT:
1023                 qlcnic_83xx_idc_quiesce_state(adapter);
1024                 break;
1025         default:
1026                 qlcnic_83xx_idc_unknown_state(adapter);
1027                 return;
1028         }
1029         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1030         qlcnic_83xx_periodic_tasks(adapter);
1031
1032         /* Re-schedule the function */
1033         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1034                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1035                                      adapter->ahw->idc.delay);
1036 }
1037
1038 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1039 {
1040         u32 idc_params, val;
1041
1042         if (qlcnic_83xx_lockless_flash_read32(adapter,
1043                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1044                                               (u8 *)&idc_params, 1)) {
1045                 dev_info(&adapter->pdev->dev,
1046                          "%s:failed to get IDC params from flash\n", __func__);
1047                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1048                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1049         } else {
1050                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1051                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1052         }
1053
1054         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1055         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1056         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1057         adapter->ahw->idc.err_code = 0;
1058         adapter->ahw->idc.collect_dump = 0;
1059         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1060
1061         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1062         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1063         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1064
1065         /* Check if reset recovery is disabled */
1066         if (!qlcnic_auto_fw_reset) {
1067                 /* Propagate do not reset request to other functions */
1068                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1069                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1070                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1071         }
1072 }
1073
1074 static int
1075 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1076 {
1077         u32 state, val;
1078
1079         if (qlcnic_83xx_lock_driver(adapter))
1080                 return -EIO;
1081
1082         /* Clear driver lock register */
1083         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1084         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1085                 qlcnic_83xx_unlock_driver(adapter);
1086                 return -EIO;
1087         }
1088
1089         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1090         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1091                 qlcnic_83xx_unlock_driver(adapter);
1092                 return -EIO;
1093         }
1094
1095         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1096                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1097                        QLC_83XX_IDC_DEV_COLD);
1098                 state = QLC_83XX_IDC_DEV_COLD;
1099         }
1100
1101         adapter->ahw->idc.curr_state = state;
1102         /* First to load function should cold boot the device */
1103         if (state == QLC_83XX_IDC_DEV_COLD)
1104                 qlcnic_83xx_idc_cold_state_handler(adapter);
1105
1106         /* Check if reset recovery is enabled */
1107         if (qlcnic_auto_fw_reset) {
1108                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1109                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1110                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1111         }
1112
1113         qlcnic_83xx_unlock_driver(adapter);
1114
1115         return 0;
1116 }
1117
1118 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1119 {
1120         int ret = -EIO;
1121
1122         qlcnic_83xx_setup_idc_parameters(adapter);
1123
1124         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1125                 return ret;
1126
1127         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1128                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1129                         return -EIO;
1130         } else {
1131                 if (qlcnic_83xx_idc_check_major_version(adapter))
1132                         return -EIO;
1133         }
1134
1135         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1136
1137         return 0;
1138 }
1139
1140 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1141 {
1142         int id;
1143         u32 val;
1144
1145         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1146                 usleep_range(10000, 11000);
1147
1148         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1149         id = id & 0xFF;
1150
1151         if (id == adapter->portnum) {
1152                 dev_err(&adapter->pdev->dev,
1153                         "%s: wait for lock recovery.. %d\n", __func__, id);
1154                 msleep(20);
1155                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1156                 id = id & 0xFF;
1157         }
1158
1159         /* Clear driver presence bit */
1160         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1161         val = val & ~(1 << adapter->portnum);
1162         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1163         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1164         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1165
1166         cancel_delayed_work_sync(&adapter->fw_work);
1167 }
1168
1169 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1170 {
1171         u32 val;
1172
1173         if (qlcnic_83xx_lock_driver(adapter)) {
1174                 dev_err(&adapter->pdev->dev,
1175                         "%s:failed, please retry\n", __func__);
1176                 return;
1177         }
1178
1179         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1180         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1181             !qlcnic_auto_fw_reset) {
1182                 dev_err(&adapter->pdev->dev,
1183                         "%s:failed, device in non reset mode\n", __func__);
1184                 qlcnic_83xx_unlock_driver(adapter);
1185                 return;
1186         }
1187
1188         if (key == QLCNIC_FORCE_FW_RESET) {
1189                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1190                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1191                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1192         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1193                 adapter->ahw->idc.collect_dump = 1;
1194         }
1195
1196         qlcnic_83xx_unlock_driver(adapter);
1197         return;
1198 }
1199
1200 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1201 {
1202         u8 *p_cache;
1203         u32 src, size;
1204         u64 dest;
1205         int ret = -EIO;
1206
1207         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1208         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1209         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1210
1211         /* alignment check */
1212         if (size & 0xF)
1213                 size = (size + 16) & ~0xF;
1214
1215         p_cache = kzalloc(size, GFP_KERNEL);
1216         if (p_cache == NULL)
1217                 return -ENOMEM;
1218
1219         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1220                                                 size / sizeof(u32));
1221         if (ret) {
1222                 kfree(p_cache);
1223                 return ret;
1224         }
1225         /* 16 byte write to MS memory */
1226         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1227                                           size / 16);
1228         if (ret) {
1229                 kfree(p_cache);
1230                 return ret;
1231         }
1232         kfree(p_cache);
1233
1234         return ret;
1235 }
1236
1237 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1238 {
1239         u32 dest, *p_cache;
1240         u64 addr;
1241         u8 data[16];
1242         size_t size;
1243         int i, ret = -EIO;
1244
1245         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1246         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1247         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1248         addr = (u64)dest;
1249
1250         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1251                                           (u32 *)p_cache, size / 16);
1252         if (ret) {
1253                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1254                 release_firmware(adapter->ahw->fw_info.fw);
1255                 adapter->ahw->fw_info.fw = NULL;
1256                 return -EIO;
1257         }
1258
1259         /* alignment check */
1260         if (adapter->ahw->fw_info.fw->size & 0xF) {
1261                 addr = dest + size;
1262                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1263                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1264                 for (; i < 16; i++)
1265                         data[i] = 0;
1266                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1267                                                   (u32 *)data, 1);
1268                 if (ret) {
1269                         dev_err(&adapter->pdev->dev,
1270                                 "MS memory write failed\n");
1271                         release_firmware(adapter->ahw->fw_info.fw);
1272                         adapter->ahw->fw_info.fw = NULL;
1273                         return -EIO;
1274                 }
1275         }
1276         release_firmware(adapter->ahw->fw_info.fw);
1277         adapter->ahw->fw_info.fw = NULL;
1278
1279         return 0;
1280 }
1281
1282 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1283 {
1284         int i, j;
1285         u32 val = 0, val1 = 0, reg = 0;
1286
1287         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1288         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1289
1290         for (j = 0; j < 2; j++) {
1291                 if (j == 0) {
1292                         dev_info(&adapter->pdev->dev,
1293                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1294                         reg = QLC_83XX_PORT0_THRESHOLD;
1295                 } else if (j == 1) {
1296                         dev_info(&adapter->pdev->dev,
1297                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1298                         reg = QLC_83XX_PORT1_THRESHOLD;
1299                 }
1300                 for (i = 0; i < 8; i++) {
1301                         val = QLCRD32(adapter, reg + (i * 0x4));
1302                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1303                 }
1304                 dev_info(&adapter->pdev->dev, "\n");
1305         }
1306
1307         for (j = 0; j < 2; j++) {
1308                 if (j == 0) {
1309                         dev_info(&adapter->pdev->dev,
1310                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1311                         reg = QLC_83XX_PORT0_TC_MC_REG;
1312                 } else if (j == 1) {
1313                         dev_info(&adapter->pdev->dev,
1314                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1315                         reg = QLC_83XX_PORT1_TC_MC_REG;
1316                 }
1317                 for (i = 0; i < 4; i++) {
1318                         val = QLCRD32(adapter, reg + (i * 0x4));
1319                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1320                 }
1321                 dev_info(&adapter->pdev->dev, "\n");
1322         }
1323
1324         for (j = 0; j < 2; j++) {
1325                 if (j == 0) {
1326                         dev_info(&adapter->pdev->dev,
1327                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1328                         reg = QLC_83XX_PORT0_TC_STATS;
1329                 } else if (j == 1) {
1330                         dev_info(&adapter->pdev->dev,
1331                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1332                         reg = QLC_83XX_PORT1_TC_STATS;
1333                 }
1334                 for (i = 7; i >= 0; i--) {
1335                         val = QLCRD32(adapter, reg);
1336                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1337                         QLCWR32(adapter, reg, (val | (i << 29)));
1338                         val = QLCRD32(adapter, reg);
1339                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1340                 }
1341                 dev_info(&adapter->pdev->dev, "\n");
1342         }
1343
1344         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1345         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1346         dev_info(&adapter->pdev->dev,
1347                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1348                  val, val1);
1349 }
1350
1351
1352 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1353 {
1354         u32 reg = 0, i, j;
1355
1356         if (qlcnic_83xx_lock_driver(adapter)) {
1357                 dev_err(&adapter->pdev->dev,
1358                         "%s:failed to acquire driver lock\n", __func__);
1359                 return;
1360         }
1361
1362         qlcnic_83xx_dump_pause_control_regs(adapter);
1363         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1364
1365         for (j = 0; j < 2; j++) {
1366                 if (j == 0)
1367                         reg = QLC_83XX_PORT0_THRESHOLD;
1368                 else if (j == 1)
1369                         reg = QLC_83XX_PORT1_THRESHOLD;
1370
1371                 for (i = 0; i < 8; i++)
1372                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1373         }
1374
1375         for (j = 0; j < 2; j++) {
1376                 if (j == 0)
1377                         reg = QLC_83XX_PORT0_TC_MC_REG;
1378                 else if (j == 1)
1379                         reg = QLC_83XX_PORT1_TC_MC_REG;
1380
1381                 for (i = 0; i < 4; i++)
1382                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1383         }
1384
1385         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1386         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1387         dev_info(&adapter->pdev->dev,
1388                  "Disabled pause frames successfully on all ports\n");
1389         qlcnic_83xx_unlock_driver(adapter);
1390 }
1391
1392 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1393 {
1394         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1395         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1396         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1397         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1398         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1399         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1400         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1401         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1402         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1403 }
1404
1405 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1406 {
1407         u32 heartbeat, peg_status;
1408         int retries, ret = -EIO;
1409
1410         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1411         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1412                                                QLCNIC_PEG_ALIVE_COUNTER);
1413
1414         do {
1415                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1416                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1417                                                 QLCNIC_PEG_ALIVE_COUNTER);
1418                 if (heartbeat != p_dev->heartbeat) {
1419                         ret = QLCNIC_RCODE_SUCCESS;
1420                         break;
1421                 }
1422         } while (--retries);
1423
1424         if (ret) {
1425                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1426                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1427                 qlcnic_83xx_disable_pause_frames(p_dev);
1428                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1429                                                  QLCNIC_PEG_HALT_STATUS1);
1430                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1431                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1432                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1433                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1434                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1435                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1436                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1437                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1438                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1439                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1440                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1441
1442                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1443                         dev_err(&p_dev->pdev->dev,
1444                                 "Device is being reset err code 0x00006700.\n");
1445         }
1446
1447         return ret;
1448 }
1449
1450 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1451 {
1452         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1453         u32 val;
1454
1455         do {
1456                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1457                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1458                         return 0;
1459                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1460         } while (--retries);
1461
1462         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1463         return -EIO;
1464 }
1465
1466 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1467 {
1468         int err;
1469
1470         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1471         if (err)
1472                 return err;
1473
1474         err = qlcnic_83xx_check_heartbeat(p_dev);
1475         if (err)
1476                 return err;
1477
1478         return err;
1479 }
1480
1481 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1482                                 int duration, u32 mask, u32 status)
1483 {
1484         u32 value;
1485         int timeout_error;
1486         u8 retries;
1487
1488         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1489         retries = duration / 10;
1490
1491         do {
1492                 if ((value & mask) != status) {
1493                         timeout_error = 1;
1494                         msleep(duration / 10);
1495                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1496                 } else {
1497                         timeout_error = 0;
1498                         break;
1499                 }
1500         } while (retries--);
1501
1502         if (timeout_error) {
1503                 p_dev->ahw->reset.seq_error++;
1504                 dev_err(&p_dev->pdev->dev,
1505                         "%s: Timeout Err, entry_num = %d\n",
1506                         __func__, p_dev->ahw->reset.seq_index);
1507                 dev_err(&p_dev->pdev->dev,
1508                         "0x%08x 0x%08x 0x%08x\n",
1509                         value, mask, status);
1510         }
1511
1512         return timeout_error;
1513 }
1514
1515 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1516 {
1517         u32 sum = 0;
1518         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1519         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1520
1521         while (count-- > 0)
1522                 sum += *buff++;
1523
1524         while (sum >> 16)
1525                 sum = (sum & 0xFFFF) + (sum >> 16);
1526
1527         if (~sum) {
1528                 return 0;
1529         } else {
1530                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1531                 return -1;
1532         }
1533 }
1534
1535 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1536 {
1537         u8 *p_buff;
1538         u32 addr, count;
1539         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1540
1541         ahw->reset.seq_error = 0;
1542         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1543         if (p_dev->ahw->reset.buff == NULL)
1544                 return -ENOMEM;
1545
1546         p_buff = p_dev->ahw->reset.buff;
1547         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1548         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1549
1550         /* Copy template header from flash */
1551         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1552                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1553                 return -EIO;
1554         }
1555         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1556         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1557         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1558         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1559
1560         /* Copy rest of the template */
1561         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1562                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1563                 return -EIO;
1564         }
1565
1566         if (qlcnic_83xx_reset_template_checksum(p_dev))
1567                 return -EIO;
1568         /* Get Stop, Start and Init command offsets */
1569         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1570         ahw->reset.start_offset = ahw->reset.buff +
1571                                   ahw->reset.hdr->start_offset;
1572         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1573         return 0;
1574 }
1575
1576 /* Read Write HW register command */
1577 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1578                                            u32 raddr, u32 waddr)
1579 {
1580         int value;
1581
1582         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1583         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1584 }
1585
1586 /* Read Modify Write HW register command */
1587 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1588                                     u32 raddr, u32 waddr,
1589                                     struct qlc_83xx_rmw *p_rmw_hdr)
1590 {
1591         int value;
1592
1593         if (p_rmw_hdr->index_a)
1594                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1595         else
1596                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1597
1598         value &= p_rmw_hdr->mask;
1599         value <<= p_rmw_hdr->shl;
1600         value >>= p_rmw_hdr->shr;
1601         value |= p_rmw_hdr->or_value;
1602         value ^= p_rmw_hdr->xor_value;
1603         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1604 }
1605
1606 /* Write HW register command */
1607 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1608                                    struct qlc_83xx_entry_hdr *p_hdr)
1609 {
1610         int i;
1611         struct qlc_83xx_entry *entry;
1612
1613         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1614                                           sizeof(struct qlc_83xx_entry_hdr));
1615
1616         for (i = 0; i < p_hdr->count; i++, entry++) {
1617                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1618                                              entry->arg2);
1619                 if (p_hdr->delay)
1620                         udelay((u32)(p_hdr->delay));
1621         }
1622 }
1623
1624 /* Read and Write instruction */
1625 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1626                                         struct qlc_83xx_entry_hdr *p_hdr)
1627 {
1628         int i;
1629         struct qlc_83xx_entry *entry;
1630
1631         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1632                                           sizeof(struct qlc_83xx_entry_hdr));
1633
1634         for (i = 0; i < p_hdr->count; i++, entry++) {
1635                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1636                                                entry->arg2);
1637                 if (p_hdr->delay)
1638                         udelay((u32)(p_hdr->delay));
1639         }
1640 }
1641
1642 /* Poll HW register command */
1643 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1644                                   struct qlc_83xx_entry_hdr *p_hdr)
1645 {
1646         long delay;
1647         struct qlc_83xx_entry *entry;
1648         struct qlc_83xx_poll *poll;
1649         int i;
1650         unsigned long arg1, arg2;
1651
1652         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1653                                         sizeof(struct qlc_83xx_entry_hdr));
1654
1655         entry = (struct qlc_83xx_entry *)((char *)poll +
1656                                           sizeof(struct qlc_83xx_poll));
1657         delay = (long)p_hdr->delay;
1658
1659         if (!delay) {
1660                 for (i = 0; i < p_hdr->count; i++, entry++)
1661                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1662                                              delay, poll->mask,
1663                                              poll->status);
1664         } else {
1665                 for (i = 0; i < p_hdr->count; i++, entry++) {
1666                         arg1 = entry->arg1;
1667                         arg2 = entry->arg2;
1668                         if (delay) {
1669                                 if (qlcnic_83xx_poll_reg(p_dev,
1670                                                          arg1, delay,
1671                                                          poll->mask,
1672                                                          poll->status)){
1673                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1674                                                                     arg1);
1675                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1676                                                                     arg2);
1677                                 }
1678                         }
1679                 }
1680         }
1681 }
1682
1683 /* Poll and write HW register command */
1684 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1685                                         struct qlc_83xx_entry_hdr *p_hdr)
1686 {
1687         int i;
1688         long delay;
1689         struct qlc_83xx_quad_entry *entry;
1690         struct qlc_83xx_poll *poll;
1691
1692         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1693                                         sizeof(struct qlc_83xx_entry_hdr));
1694         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1695                                                sizeof(struct qlc_83xx_poll));
1696         delay = (long)p_hdr->delay;
1697
1698         for (i = 0; i < p_hdr->count; i++, entry++) {
1699                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1700                                              entry->dr_value);
1701                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1702                                              entry->ar_value);
1703                 if (delay)
1704                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1705                                              poll->mask, poll->status);
1706         }
1707 }
1708
1709 /* Read Modify Write register command */
1710 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1711                                           struct qlc_83xx_entry_hdr *p_hdr)
1712 {
1713         int i;
1714         struct qlc_83xx_entry *entry;
1715         struct qlc_83xx_rmw *rmw_hdr;
1716
1717         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1718                                           sizeof(struct qlc_83xx_entry_hdr));
1719
1720         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1721                                           sizeof(struct qlc_83xx_rmw));
1722
1723         for (i = 0; i < p_hdr->count; i++, entry++) {
1724                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1725                                         entry->arg2, rmw_hdr);
1726                 if (p_hdr->delay)
1727                         udelay((u32)(p_hdr->delay));
1728         }
1729 }
1730
1731 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1732 {
1733         if (p_hdr->delay)
1734                 mdelay((u32)((long)p_hdr->delay));
1735 }
1736
1737 /* Read and poll register command */
1738 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1739                                        struct qlc_83xx_entry_hdr *p_hdr)
1740 {
1741         long delay;
1742         int index, i, j;
1743         struct qlc_83xx_quad_entry *entry;
1744         struct qlc_83xx_poll *poll;
1745         unsigned long addr;
1746
1747         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1748                                         sizeof(struct qlc_83xx_entry_hdr));
1749
1750         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1751                                                sizeof(struct qlc_83xx_poll));
1752         delay = (long)p_hdr->delay;
1753
1754         for (i = 0; i < p_hdr->count; i++, entry++) {
1755                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1756                                              entry->ar_value);
1757                 if (delay) {
1758                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1759                                                   poll->mask, poll->status)){
1760                                 index = p_dev->ahw->reset.array_index;
1761                                 addr = entry->dr_addr;
1762                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1763                                 p_dev->ahw->reset.array[index++] = j;
1764
1765                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1766                                         p_dev->ahw->reset.array_index = 1;
1767                         }
1768                 }
1769         }
1770 }
1771
1772 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1773 {
1774         p_dev->ahw->reset.seq_end = 1;
1775 }
1776
1777 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1778 {
1779         p_dev->ahw->reset.template_end = 1;
1780         if (p_dev->ahw->reset.seq_error == 0)
1781                 dev_err(&p_dev->pdev->dev,
1782                         "HW restart process completed successfully.\n");
1783         else
1784                 dev_err(&p_dev->pdev->dev,
1785                         "HW restart completed with timeout errors.\n");
1786 }
1787
1788 /**
1789 * qlcnic_83xx_exec_template_cmd
1790 *
1791 * @p_dev: adapter structure
1792 * @p_buff: Poiter to instruction template
1793 *
1794 * Template provides instructions to stop, restart and initalize firmware.
1795 * These instructions are abstracted as a series of read, write and
1796 * poll operations on hardware registers. Register information and operation
1797 * specifics are not exposed to the driver. Driver reads the template from
1798 * flash and executes the instructions located at pre-defined offsets.
1799 *
1800 * Returns: None
1801 * */
1802 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1803                                           char *p_buff)
1804 {
1805         int index, entries;
1806         struct qlc_83xx_entry_hdr *p_hdr;
1807         char *entry = p_buff;
1808
1809         p_dev->ahw->reset.seq_end = 0;
1810         p_dev->ahw->reset.template_end = 0;
1811         entries = p_dev->ahw->reset.hdr->entries;
1812         index = p_dev->ahw->reset.seq_index;
1813
1814         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1815                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1816
1817                 switch (p_hdr->cmd) {
1818                 case QLC_83XX_OPCODE_NOP:
1819                         break;
1820                 case QLC_83XX_OPCODE_WRITE_LIST:
1821                         qlcnic_83xx_write_list(p_dev, p_hdr);
1822                         break;
1823                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1824                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1825                         break;
1826                 case QLC_83XX_OPCODE_POLL_LIST:
1827                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1828                         break;
1829                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1830                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1831                         break;
1832                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1833                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1834                         break;
1835                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1836                         qlcnic_83xx_pause(p_hdr);
1837                         break;
1838                 case QLC_83XX_OPCODE_SEQ_END:
1839                         qlcnic_83xx_seq_end(p_dev);
1840                         break;
1841                 case QLC_83XX_OPCODE_TMPL_END:
1842                         qlcnic_83xx_template_end(p_dev);
1843                         break;
1844                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1845                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1846                         break;
1847                 default:
1848                         dev_err(&p_dev->pdev->dev,
1849                                 "%s: Unknown opcode 0x%04x in template %d\n",
1850                                 __func__, p_hdr->cmd, index);
1851                         break;
1852                 }
1853                 entry += p_hdr->size;
1854         }
1855         p_dev->ahw->reset.seq_index = index;
1856 }
1857
1858 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1859 {
1860         p_dev->ahw->reset.seq_index = 0;
1861
1862         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1863         if (p_dev->ahw->reset.seq_end != 1)
1864                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1865 }
1866
1867 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1868 {
1869         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1870         if (p_dev->ahw->reset.template_end != 1)
1871                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1872 }
1873
1874 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1875 {
1876         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1877         if (p_dev->ahw->reset.seq_end != 1)
1878                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1879 }
1880
1881 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1882 {
1883         int err = -EIO;
1884
1885         if (request_firmware(&adapter->ahw->fw_info.fw,
1886                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1887                 dev_err(&adapter->pdev->dev,
1888                         "No file FW image, loading flash FW image.\n");
1889                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1890                                     QLC_83XX_BOOT_FROM_FLASH);
1891         } else {
1892                 if (qlcnic_83xx_copy_fw_file(adapter))
1893                         return err;
1894                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1895                                     QLC_83XX_BOOT_FROM_FILE);
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1902 {
1903         u32 val;
1904         int err = -EIO;
1905
1906         qlcnic_83xx_stop_hw(adapter);
1907
1908         /* Collect FW register dump if required */
1909         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1910         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1911                 qlcnic_dump_fw(adapter);
1912         qlcnic_83xx_init_hw(adapter);
1913
1914         if (qlcnic_83xx_copy_bootloader(adapter))
1915                 return err;
1916         /* Boot either flash image or firmware image from host file system */
1917         if (qlcnic_load_fw_file) {
1918                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1919                         return err;
1920         } else {
1921                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1922                                     QLC_83XX_BOOT_FROM_FLASH);
1923         }
1924
1925         qlcnic_83xx_start_hw(adapter);
1926         if (qlcnic_83xx_check_hw_status(adapter))
1927                 return -EIO;
1928
1929         return 0;
1930 }
1931
1932 /**
1933 * qlcnic_83xx_config_default_opmode
1934 *
1935 * @adapter: adapter structure
1936 *
1937 * Configure default driver operating mode
1938 *
1939 * Returns: Error code or Success(0)
1940 * */
1941 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1942 {
1943         u32 op_mode;
1944         struct qlcnic_hardware_context *ahw = adapter->ahw;
1945
1946         qlcnic_get_func_no(adapter);
1947         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1948
1949         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1950                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1951
1952         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1953                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1954                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1955         } else {
1956                 return -EIO;
1957         }
1958
1959         return 0;
1960 }
1961
1962 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1963 {
1964         int err;
1965         struct qlcnic_info nic_info;
1966         struct qlcnic_hardware_context *ahw = adapter->ahw;
1967
1968         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1969         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1970         if (err)
1971                 return -EIO;
1972
1973         ahw->physical_port = (u8) nic_info.phys_port;
1974         ahw->switch_mode = nic_info.switch_mode;
1975         ahw->max_tx_ques = nic_info.max_tx_ques;
1976         ahw->max_rx_ques = nic_info.max_rx_ques;
1977         ahw->capabilities = nic_info.capabilities;
1978         ahw->max_mac_filters = nic_info.max_mac_filters;
1979         ahw->max_mtu = nic_info.max_mtu;
1980
1981         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1982          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1983          * exclusive. So in case of sriov capable device load driver in
1984          * default mode
1985          */
1986         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1987                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1988                 return ahw->nic_mode;
1989         }
1990
1991         if (ahw->capabilities & BIT_23)
1992                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1993         else
1994                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1995
1996         return ahw->nic_mode;
1997 }
1998
1999 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2000 {
2001         int ret;
2002
2003         ret = qlcnic_83xx_get_nic_configuration(adapter);
2004         if (ret == -EIO)
2005                 return -EIO;
2006
2007         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2008                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2009                         return -EIO;
2010         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2011                 if (qlcnic_83xx_config_default_opmode(adapter))
2012                         return -EIO;
2013         }
2014
2015         return 0;
2016 }
2017
2018 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2019 {
2020         struct qlcnic_hardware_context *ahw = adapter->ahw;
2021
2022         if (ahw->port_type == QLCNIC_XGBE) {
2023                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2024                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2025                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2026                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2027
2028         } else if (ahw->port_type == QLCNIC_GBE) {
2029                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2030                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2031                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2032                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2033         }
2034         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2035         adapter->max_rds_rings = MAX_RDS_RINGS;
2036 }
2037
2038 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2039 {
2040         int err = -EIO;
2041
2042         qlcnic_83xx_get_minidump_template(adapter);
2043         if (qlcnic_83xx_get_port_info(adapter))
2044                 return err;
2045
2046         qlcnic_83xx_config_buff_descriptors(adapter);
2047         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2048         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2049
2050         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2051                  adapter->ahw->fw_hal_version);
2052
2053         return 0;
2054 }
2055
2056 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2057 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2058 {
2059         struct qlcnic_cmd_args cmd;
2060         u32 presence_mask, audit_mask;
2061         int status;
2062
2063         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2064         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2065
2066         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2067                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2068                 cmd.req.arg[1] = BIT_31;
2069                 status = qlcnic_issue_cmd(adapter, &cmd);
2070                 if (status)
2071                         dev_err(&adapter->pdev->dev,
2072                                 "Failed to clean up the function resources\n");
2073                 qlcnic_free_mbx_args(&cmd);
2074         }
2075 }
2076
2077 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2078 {
2079         struct qlcnic_hardware_context *ahw = adapter->ahw;
2080
2081         if (qlcnic_sriov_vf_check(adapter))
2082                 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2083
2084         if (qlcnic_83xx_check_hw_status(adapter))
2085                 return -EIO;
2086
2087         /* Initilaize 83xx mailbox spinlock */
2088         spin_lock_init(&ahw->mbx_lock);
2089
2090         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2091         qlcnic_83xx_clear_function_resources(adapter);
2092
2093         /* register for NIC IDC AEN Events */
2094         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2095
2096         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2097                 qlcnic_83xx_read_flash_mfg_id(adapter);
2098
2099         if (qlcnic_83xx_idc_init(adapter))
2100                 return -EIO;
2101
2102         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2103         if (qlcnic_83xx_configure_opmode(adapter))
2104                 return -EIO;
2105
2106         /* Perform operating mode specific initialization */
2107         if (adapter->nic_ops->init_driver(adapter))
2108                 return -EIO;
2109
2110         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2111
2112         /* Periodically monitor device status */
2113         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2114
2115         return adapter->ahw->idc.err_code;
2116 }