2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
44 struct qlc_83xx_reset_hdr {
45 #if defined(__LITTLE_ENDIAN)
54 #elif defined(__BIG_ENDIAN)
66 /* Command entry header. */
67 struct qlc_83xx_entry_hdr {
68 #if defined(__LITTLE_ENDIAN)
73 #elif defined(__BIG_ENDIAN)
81 /* Generic poll command */
82 struct qlc_83xx_poll {
87 /* Read modify write command */
92 #if defined(__LITTLE_ENDIAN)
97 #elif defined(__BIG_ENDIAN)
105 /* Generic command with 2 DWORD */
106 struct qlc_83xx_entry {
111 /* Generic command with 4 DWORD */
112 struct qlc_83xx_quad_entry {
118 static const char *const qlc_83xx_idc_states[] = {
130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
160 if (qlcnic_83xx_lock_driver(adapter))
164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
170 seconds = jiffies / HZ;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
177 qlcnic_83xx_unlock_driver(adapter);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
198 if (qlcnic_83xx_lock_driver(adapter))
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
208 qlcnic_83xx_unlock_driver(adapter);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
220 if (qlcnic_83xx_lock_driver(adapter))
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
227 val = val | (1 << adapter->portnum);
229 val = val & ~(1 << adapter->portnum);
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
235 qlcnic_83xx_unlock_driver(adapter);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
264 if (qlcnic_83xx_lock_driver(adapter))
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
275 qlcnic_83xx_unlock_driver(adapter);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
286 if (qlcnic_83xx_lock_driver(adapter))
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
292 val = val | (1 << adapter->portnum);
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
298 qlcnic_83xx_unlock_driver(adapter);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
327 u32 ack, presence, val;
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter);
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
373 struct net_device *netdev = adapter->netdev;
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
385 adapter->netdev->trans_start = jiffies;
391 * qlcnic_83xx_idc_detach_driver
393 * @adapter: adapter structure
394 * Detach net interface, stop TX and cleanup resources before the HW reset.
398 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
401 struct net_device *netdev = adapter->netdev;
403 netif_device_detach(netdev);
405 /* Disable mailbox interrupt */
406 qlcnic_83xx_disable_mbx_intr(adapter);
407 qlcnic_down(adapter, netdev);
408 for (i = 0; i < adapter->ahw->num_msix; i++) {
409 adapter->ahw->intr_tbl[i].id = i;
410 adapter->ahw->intr_tbl[i].enabled = 0;
411 adapter->ahw->intr_tbl[i].src = 0;
414 if (qlcnic_sriov_pf_check(adapter))
415 qlcnic_sriov_pf_reset(adapter);
419 * qlcnic_83xx_idc_attach_driver
421 * @adapter: adapter structure
423 * Re-attach and re-enable net interface
427 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
429 struct net_device *netdev = adapter->netdev;
431 if (netif_running(netdev)) {
432 if (qlcnic_up(adapter, netdev))
434 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
437 netif_device_attach(netdev);
438 if (netif_running(netdev)) {
439 netif_carrier_on(netdev);
440 netif_wake_queue(netdev);
444 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
448 if (qlcnic_83xx_lock_driver(adapter))
452 qlcnic_83xx_idc_clear_registers(adapter, 0);
453 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
455 qlcnic_83xx_unlock_driver(adapter);
457 qlcnic_83xx_idc_log_state_history(adapter);
458 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
463 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
467 if (qlcnic_83xx_lock_driver(adapter))
471 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
474 qlcnic_83xx_unlock_driver(adapter);
479 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
483 if (qlcnic_83xx_lock_driver(adapter))
487 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
488 QLC_83XX_IDC_DEV_NEED_QUISCENT);
491 qlcnic_83xx_unlock_driver(adapter);
497 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
500 if (qlcnic_83xx_lock_driver(adapter))
504 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
505 QLC_83XX_IDC_DEV_NEED_RESET);
508 qlcnic_83xx_unlock_driver(adapter);
513 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
517 if (qlcnic_83xx_lock_driver(adapter))
521 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
523 qlcnic_83xx_unlock_driver(adapter);
529 * qlcnic_83xx_idc_find_reset_owner_id
531 * @adapter: adapter structure
533 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
534 * Within the same class, function with lowest PCI ID assumes ownership
536 * Returns: reset owner id or failure indication (-EIO)
539 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
541 u32 reg, reg1, reg2, i, j, owner, class;
543 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
544 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
545 owner = QLCNIC_TYPE_NIC;
551 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
554 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
561 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
562 if (owner == QLCNIC_TYPE_NIC)
563 owner = QLCNIC_TYPE_ISCSI;
564 else if (owner == QLCNIC_TYPE_ISCSI)
565 owner = QLCNIC_TYPE_FCOE;
566 else if (owner == QLCNIC_TYPE_FCOE)
572 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
577 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
581 ret = qlcnic_83xx_restart_hw(adapter);
584 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
586 qlcnic_83xx_idc_clear_registers(adapter, lock);
587 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
593 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
597 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
599 if (status & QLCNIC_RCODE_FATAL_ERROR) {
600 dev_err(&adapter->pdev->dev,
601 "peg halt status1=0x%x\n", status);
602 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
603 dev_err(&adapter->pdev->dev,
604 "On board active cooling fan failed. "
605 "Device has been halted.\n");
606 dev_err(&adapter->pdev->dev,
607 "Replace the adapter.\n");
615 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
619 /* register for NIC IDC AEN Events */
620 qlcnic_83xx_register_nic_idc_func(adapter, 1);
622 err = qlcnic_sriov_pf_reinit(adapter);
626 qlcnic_83xx_enable_mbx_intrpt(adapter);
628 if (qlcnic_83xx_configure_opmode(adapter)) {
629 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
633 if (adapter->nic_ops->init_driver(adapter)) {
634 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
638 qlcnic_83xx_idc_attach_driver(adapter);
643 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
645 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
646 clear_bit(__QLCNIC_RESETTING, &adapter->state);
647 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
648 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
649 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
650 adapter->ahw->idc.quiesce_req = 0;
651 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
652 adapter->ahw->idc.err_code = 0;
653 adapter->ahw->idc.collect_dump = 0;
657 * qlcnic_83xx_idc_ready_state_entry
659 * @adapter: adapter structure
661 * Perform ready state initialization, this routine will get invoked only
662 * once from READY state.
664 * Returns: Error code or Success(0)
667 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
669 struct qlcnic_hardware_context *ahw = adapter->ahw;
671 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
672 qlcnic_83xx_idc_update_idc_params(adapter);
673 /* Re-attach the device if required */
674 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
675 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
676 if (qlcnic_83xx_idc_reattach_driver(adapter))
685 * qlcnic_83xx_idc_vnic_pf_entry
687 * @adapter: adapter structure
689 * Ensure vNIC mode privileged function starts only after vNIC mode is
690 * enabled by management function.
691 * If vNIC mode is ready, start initialization.
696 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
699 struct qlcnic_hardware_context *ahw = adapter->ahw;
701 /* Privileged function waits till mgmt function enables VNIC mode */
702 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
703 if (state != QLCNIC_DEV_NPAR_OPER) {
704 if (!ahw->idc.vnic_wait_limit--) {
705 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
708 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
712 /* Perform one time initialization from ready state */
713 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
714 qlcnic_83xx_idc_update_idc_params(adapter);
716 /* If the previous state is UNKNOWN, device will be
717 already attached properly by Init routine*/
718 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
719 if (qlcnic_83xx_idc_reattach_driver(adapter))
722 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
723 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
730 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
732 adapter->ahw->idc.err_code = -EIO;
733 dev_err(&adapter->pdev->dev,
734 "%s: Device in unknown state\n", __func__);
739 * qlcnic_83xx_idc_cold_state
741 * @adapter: adapter structure
743 * If HW is up and running device will enter READY state.
744 * If firmware image from host needs to be loaded, device is
745 * forced to start with the file firmware image.
747 * Returns: Error code or Success(0)
750 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
752 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
753 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
755 if (qlcnic_load_fw_file) {
756 qlcnic_83xx_idc_restart_hw(adapter, 0);
758 if (qlcnic_83xx_check_hw_status(adapter)) {
759 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
762 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
769 * qlcnic_83xx_idc_init_state
771 * @adapter: adapter structure
773 * Reset owner will restart the device from this state.
774 * Device will enter failed state if it remains
775 * in this state for more than DEV_INIT time limit.
777 * Returns: Error code or Success(0)
780 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
782 int timeout, ret = 0;
785 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
786 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
787 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
788 if (adapter->ahw->pci_func == owner)
789 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
791 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
799 * qlcnic_83xx_idc_ready_state
801 * @adapter: adapter structure
803 * Perform IDC protocol specicifed actions after monitoring device state and
806 * Returns: Error code or Success(0)
809 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
812 struct qlcnic_hardware_context *ahw = adapter->ahw;
815 /* Perform NIC configuration based ready state entry actions */
816 if (ahw->idc.state_entry(adapter))
819 if (qlcnic_check_temp(adapter)) {
820 if (ahw->temp == QLCNIC_TEMP_PANIC) {
821 qlcnic_83xx_idc_check_fan_failure(adapter);
822 dev_err(&adapter->pdev->dev,
823 "Error: device temperature %d above limits\n",
825 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
826 set_bit(__QLCNIC_RESETTING, &adapter->state);
827 qlcnic_83xx_idc_detach_driver(adapter);
828 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
833 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
834 ret = qlcnic_83xx_check_heartbeat(adapter);
836 adapter->flags |= QLCNIC_FW_HANG;
837 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
838 clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
839 set_bit(__QLCNIC_RESETTING, &adapter->state);
840 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
845 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
846 /* Move to need reset state and prepare for reset */
847 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
851 /* Check for soft reset request */
852 if (ahw->reset_context &&
853 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
854 qlcnic_83xx_idc_tx_soft_reset(adapter);
858 /* Move to need quiesce state if requested */
859 if (adapter->ahw->idc.quiesce_req) {
860 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
861 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
869 * qlcnic_83xx_idc_need_reset_state
871 * @adapter: adapter structure
873 * Device will remain in this state until:
874 * Reset request ACK's are recieved from all the functions
875 * Wait time exceeds max time limit
877 * Returns: Error code or Success(0)
880 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
884 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
885 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
886 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
887 set_bit(__QLCNIC_RESETTING, &adapter->state);
888 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
889 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
890 qlcnic_83xx_disable_vnic_mode(adapter, 1);
891 qlcnic_83xx_idc_detach_driver(adapter);
894 /* Check ACK from other functions */
895 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
897 dev_info(&adapter->pdev->dev,
898 "%s: Waiting for reset ACK\n", __func__);
902 /* Transit to INIT state and restart the HW */
903 qlcnic_83xx_idc_enter_init_state(adapter, 1);
908 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
910 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
914 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
916 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
917 adapter->ahw->idc.err_code = -EIO;
922 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
924 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
928 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
933 cur = adapter->ahw->idc.curr_state;
934 prev = adapter->ahw->idc.prev_state;
937 if ((next < QLC_83XX_IDC_DEV_COLD) ||
938 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
939 dev_err(&adapter->pdev->dev,
940 "%s: curr %d, prev %d, next state %d is invalid\n",
941 __func__, cur, prev, state);
945 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
946 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
947 if ((next != QLC_83XX_IDC_DEV_COLD) &&
948 (next != QLC_83XX_IDC_DEV_READY)) {
949 dev_err(&adapter->pdev->dev,
950 "%s: failed, cur %d prev %d next %d\n",
951 __func__, cur, prev, next);
956 if (next == QLC_83XX_IDC_DEV_INIT) {
957 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
958 (prev != QLC_83XX_IDC_DEV_COLD) &&
959 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
960 dev_err(&adapter->pdev->dev,
961 "%s: failed, cur %d prev %d next %d\n",
962 __func__, cur, prev, next);
970 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
972 if (adapter->fhash.fnum)
973 qlcnic_prune_lb_filters(adapter);
977 * qlcnic_83xx_idc_poll_dev_state
979 * @work: kernel work queue structure used to schedule the function
981 * Poll device state periodically and perform state specific
982 * actions defined by Inter Driver Communication (IDC) protocol.
987 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
989 struct qlcnic_adapter *adapter;
992 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
993 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
995 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
996 qlcnic_83xx_idc_log_state_history(adapter);
997 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
999 adapter->ahw->idc.curr_state = state;
1002 switch (adapter->ahw->idc.curr_state) {
1003 case QLC_83XX_IDC_DEV_READY:
1004 qlcnic_83xx_idc_ready_state(adapter);
1006 case QLC_83XX_IDC_DEV_NEED_RESET:
1007 qlcnic_83xx_idc_need_reset_state(adapter);
1009 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1010 qlcnic_83xx_idc_need_quiesce_state(adapter);
1012 case QLC_83XX_IDC_DEV_FAILED:
1013 qlcnic_83xx_idc_failed_state(adapter);
1015 case QLC_83XX_IDC_DEV_INIT:
1016 qlcnic_83xx_idc_init_state(adapter);
1018 case QLC_83XX_IDC_DEV_QUISCENT:
1019 qlcnic_83xx_idc_quiesce_state(adapter);
1022 qlcnic_83xx_idc_unknown_state(adapter);
1025 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1026 qlcnic_83xx_periodic_tasks(adapter);
1028 /* Re-schedule the function */
1029 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1030 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1031 adapter->ahw->idc.delay);
1034 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1036 u32 idc_params, val;
1038 if (qlcnic_83xx_lockless_flash_read32(adapter,
1039 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1040 (u8 *)&idc_params, 1)) {
1041 dev_info(&adapter->pdev->dev,
1042 "%s:failed to get IDC params from flash\n", __func__);
1043 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1044 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1046 adapter->dev_init_timeo = idc_params & 0xFFFF;
1047 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1050 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1051 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1052 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1053 adapter->ahw->idc.err_code = 0;
1054 adapter->ahw->idc.collect_dump = 0;
1055 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1057 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1058 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1059 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1061 /* Check if reset recovery is disabled */
1062 if (!qlcnic_auto_fw_reset) {
1063 /* Propagate do not reset request to other functions */
1064 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1065 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1066 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1071 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1075 if (qlcnic_83xx_lock_driver(adapter))
1078 /* Clear driver lock register */
1079 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1080 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1081 qlcnic_83xx_unlock_driver(adapter);
1085 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1086 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1087 qlcnic_83xx_unlock_driver(adapter);
1091 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1092 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1093 QLC_83XX_IDC_DEV_COLD);
1094 state = QLC_83XX_IDC_DEV_COLD;
1097 adapter->ahw->idc.curr_state = state;
1098 /* First to load function should cold boot the device */
1099 if (state == QLC_83XX_IDC_DEV_COLD)
1100 qlcnic_83xx_idc_cold_state_handler(adapter);
1102 /* Check if reset recovery is enabled */
1103 if (qlcnic_auto_fw_reset) {
1104 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1105 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1106 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1109 qlcnic_83xx_unlock_driver(adapter);
1114 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1118 qlcnic_83xx_setup_idc_parameters(adapter);
1120 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1123 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1124 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1127 if (qlcnic_83xx_idc_check_major_version(adapter))
1131 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1136 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1141 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1142 usleep_range(10000, 11000);
1144 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1147 if (id == adapter->portnum) {
1148 dev_err(&adapter->pdev->dev,
1149 "%s: wait for lock recovery.. %d\n", __func__, id);
1151 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1155 /* Clear driver presence bit */
1156 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1157 val = val & ~(1 << adapter->portnum);
1158 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1159 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1160 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1162 cancel_delayed_work_sync(&adapter->fw_work);
1165 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1169 if (qlcnic_83xx_lock_driver(adapter)) {
1170 dev_err(&adapter->pdev->dev,
1171 "%s:failed, please retry\n", __func__);
1175 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1176 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1177 !qlcnic_auto_fw_reset) {
1178 dev_err(&adapter->pdev->dev,
1179 "%s:failed, device in non reset mode\n", __func__);
1180 qlcnic_83xx_unlock_driver(adapter);
1184 if (key == QLCNIC_FORCE_FW_RESET) {
1185 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1186 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1187 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1188 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1189 adapter->ahw->idc.collect_dump = 1;
1192 qlcnic_83xx_unlock_driver(adapter);
1196 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1203 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1204 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1205 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1207 /* alignment check */
1209 size = (size + 16) & ~0xF;
1211 p_cache = kzalloc(size, GFP_KERNEL);
1212 if (p_cache == NULL)
1215 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1216 size / sizeof(u32));
1221 /* 16 byte write to MS memory */
1222 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1233 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1241 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1242 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1243 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1246 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1247 (u32 *)p_cache, size / 16);
1249 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1250 release_firmware(adapter->ahw->fw_info.fw);
1251 adapter->ahw->fw_info.fw = NULL;
1255 /* alignment check */
1256 if (adapter->ahw->fw_info.fw->size & 0xF) {
1258 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1259 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1262 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1265 dev_err(&adapter->pdev->dev,
1266 "MS memory write failed\n");
1267 release_firmware(adapter->ahw->fw_info.fw);
1268 adapter->ahw->fw_info.fw = NULL;
1272 release_firmware(adapter->ahw->fw_info.fw);
1273 adapter->ahw->fw_info.fw = NULL;
1278 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1281 u32 val = 0, val1 = 0, reg = 0;
1283 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1284 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1286 for (j = 0; j < 2; j++) {
1288 dev_info(&adapter->pdev->dev,
1289 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1290 reg = QLC_83XX_PORT0_THRESHOLD;
1291 } else if (j == 1) {
1292 dev_info(&adapter->pdev->dev,
1293 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1294 reg = QLC_83XX_PORT1_THRESHOLD;
1296 for (i = 0; i < 8; i++) {
1297 val = QLCRD32(adapter, reg + (i * 0x4));
1298 dev_info(&adapter->pdev->dev, "0x%x ", val);
1300 dev_info(&adapter->pdev->dev, "\n");
1303 for (j = 0; j < 2; j++) {
1305 dev_info(&adapter->pdev->dev,
1306 "Port 0 RxB TC Max Cell Registers[4..1]:");
1307 reg = QLC_83XX_PORT0_TC_MC_REG;
1308 } else if (j == 1) {
1309 dev_info(&adapter->pdev->dev,
1310 "Port 1 RxB TC Max Cell Registers[4..1]:");
1311 reg = QLC_83XX_PORT1_TC_MC_REG;
1313 for (i = 0; i < 4; i++) {
1314 val = QLCRD32(adapter, reg + (i * 0x4));
1315 dev_info(&adapter->pdev->dev, "0x%x ", val);
1317 dev_info(&adapter->pdev->dev, "\n");
1320 for (j = 0; j < 2; j++) {
1322 dev_info(&adapter->pdev->dev,
1323 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1324 reg = QLC_83XX_PORT0_TC_STATS;
1325 } else if (j == 1) {
1326 dev_info(&adapter->pdev->dev,
1327 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1328 reg = QLC_83XX_PORT1_TC_STATS;
1330 for (i = 7; i >= 0; i--) {
1331 val = QLCRD32(adapter, reg);
1332 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1333 QLCWR32(adapter, reg, (val | (i << 29)));
1334 val = QLCRD32(adapter, reg);
1335 dev_info(&adapter->pdev->dev, "0x%x ", val);
1337 dev_info(&adapter->pdev->dev, "\n");
1340 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1341 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1342 dev_info(&adapter->pdev->dev,
1343 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1348 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1352 if (qlcnic_83xx_lock_driver(adapter)) {
1353 dev_err(&adapter->pdev->dev,
1354 "%s:failed to acquire driver lock\n", __func__);
1358 qlcnic_83xx_dump_pause_control_regs(adapter);
1359 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1361 for (j = 0; j < 2; j++) {
1363 reg = QLC_83XX_PORT0_THRESHOLD;
1365 reg = QLC_83XX_PORT1_THRESHOLD;
1367 for (i = 0; i < 8; i++)
1368 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1371 for (j = 0; j < 2; j++) {
1373 reg = QLC_83XX_PORT0_TC_MC_REG;
1375 reg = QLC_83XX_PORT1_TC_MC_REG;
1377 for (i = 0; i < 4; i++)
1378 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1381 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1382 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1383 dev_info(&adapter->pdev->dev,
1384 "Disabled pause frames successfully on all ports\n");
1385 qlcnic_83xx_unlock_driver(adapter);
1388 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1390 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1391 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1392 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1393 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1394 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1395 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1396 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1397 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1398 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1401 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1403 u32 heartbeat, peg_status;
1404 int retries, ret = -EIO;
1406 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1407 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1408 QLCNIC_PEG_ALIVE_COUNTER);
1411 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1412 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1413 QLCNIC_PEG_ALIVE_COUNTER);
1414 if (heartbeat != p_dev->heartbeat) {
1415 ret = QLCNIC_RCODE_SUCCESS;
1418 } while (--retries);
1421 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1422 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1423 qlcnic_83xx_disable_pause_frames(p_dev);
1424 peg_status = QLC_SHARED_REG_RD32(p_dev,
1425 QLCNIC_PEG_HALT_STATUS1);
1426 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1427 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1428 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1429 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1430 "PEG_NET_4_PC: 0x%x\n", peg_status,
1431 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1432 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1433 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1434 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1435 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1436 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1438 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1439 dev_err(&p_dev->pdev->dev,
1440 "Device is being reset err code 0x00006700.\n");
1446 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1448 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1452 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1453 if (val == QLC_83XX_CMDPEG_COMPLETE)
1455 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1456 } while (--retries);
1458 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1462 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1466 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1470 err = qlcnic_83xx_check_heartbeat(p_dev);
1477 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1478 int duration, u32 mask, u32 status)
1484 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1485 retries = duration / 10;
1488 if ((value & mask) != status) {
1490 msleep(duration / 10);
1491 value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1496 } while (retries--);
1498 if (timeout_error) {
1499 p_dev->ahw->reset.seq_error++;
1500 dev_err(&p_dev->pdev->dev,
1501 "%s: Timeout Err, entry_num = %d\n",
1502 __func__, p_dev->ahw->reset.seq_index);
1503 dev_err(&p_dev->pdev->dev,
1504 "0x%08x 0x%08x 0x%08x\n",
1505 value, mask, status);
1508 return timeout_error;
1511 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1514 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1515 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1521 sum = (sum & 0xFFFF) + (sum >> 16);
1526 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1531 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1535 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1537 ahw->reset.seq_error = 0;
1538 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1539 if (p_dev->ahw->reset.buff == NULL)
1542 p_buff = p_dev->ahw->reset.buff;
1543 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1544 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1546 /* Copy template header from flash */
1547 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1548 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1551 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1552 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1553 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1554 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1556 /* Copy rest of the template */
1557 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1558 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1562 if (qlcnic_83xx_reset_template_checksum(p_dev))
1564 /* Get Stop, Start and Init command offsets */
1565 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1566 ahw->reset.start_offset = ahw->reset.buff +
1567 ahw->reset.hdr->start_offset;
1568 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1572 /* Read Write HW register command */
1573 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1574 u32 raddr, u32 waddr)
1578 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1579 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1582 /* Read Modify Write HW register command */
1583 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1584 u32 raddr, u32 waddr,
1585 struct qlc_83xx_rmw *p_rmw_hdr)
1589 if (p_rmw_hdr->index_a)
1590 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1592 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1594 value &= p_rmw_hdr->mask;
1595 value <<= p_rmw_hdr->shl;
1596 value >>= p_rmw_hdr->shr;
1597 value |= p_rmw_hdr->or_value;
1598 value ^= p_rmw_hdr->xor_value;
1599 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1602 /* Write HW register command */
1603 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1604 struct qlc_83xx_entry_hdr *p_hdr)
1607 struct qlc_83xx_entry *entry;
1609 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1610 sizeof(struct qlc_83xx_entry_hdr));
1612 for (i = 0; i < p_hdr->count; i++, entry++) {
1613 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1616 udelay((u32)(p_hdr->delay));
1620 /* Read and Write instruction */
1621 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1622 struct qlc_83xx_entry_hdr *p_hdr)
1625 struct qlc_83xx_entry *entry;
1627 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1628 sizeof(struct qlc_83xx_entry_hdr));
1630 for (i = 0; i < p_hdr->count; i++, entry++) {
1631 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1634 udelay((u32)(p_hdr->delay));
1638 /* Poll HW register command */
1639 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1640 struct qlc_83xx_entry_hdr *p_hdr)
1643 struct qlc_83xx_entry *entry;
1644 struct qlc_83xx_poll *poll;
1646 unsigned long arg1, arg2;
1648 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1649 sizeof(struct qlc_83xx_entry_hdr));
1651 entry = (struct qlc_83xx_entry *)((char *)poll +
1652 sizeof(struct qlc_83xx_poll));
1653 delay = (long)p_hdr->delay;
1656 for (i = 0; i < p_hdr->count; i++, entry++)
1657 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1661 for (i = 0; i < p_hdr->count; i++, entry++) {
1665 if (qlcnic_83xx_poll_reg(p_dev,
1669 qlcnic_83xx_rd_reg_indirect(p_dev,
1671 qlcnic_83xx_rd_reg_indirect(p_dev,
1679 /* Poll and write HW register command */
1680 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1681 struct qlc_83xx_entry_hdr *p_hdr)
1685 struct qlc_83xx_quad_entry *entry;
1686 struct qlc_83xx_poll *poll;
1688 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1689 sizeof(struct qlc_83xx_entry_hdr));
1690 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1691 sizeof(struct qlc_83xx_poll));
1692 delay = (long)p_hdr->delay;
1694 for (i = 0; i < p_hdr->count; i++, entry++) {
1695 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1697 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1700 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1701 poll->mask, poll->status);
1705 /* Read Modify Write register command */
1706 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1707 struct qlc_83xx_entry_hdr *p_hdr)
1710 struct qlc_83xx_entry *entry;
1711 struct qlc_83xx_rmw *rmw_hdr;
1713 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1714 sizeof(struct qlc_83xx_entry_hdr));
1716 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1717 sizeof(struct qlc_83xx_rmw));
1719 for (i = 0; i < p_hdr->count; i++, entry++) {
1720 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1721 entry->arg2, rmw_hdr);
1723 udelay((u32)(p_hdr->delay));
1727 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1730 mdelay((u32)((long)p_hdr->delay));
1733 /* Read and poll register command */
1734 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1735 struct qlc_83xx_entry_hdr *p_hdr)
1739 struct qlc_83xx_quad_entry *entry;
1740 struct qlc_83xx_poll *poll;
1743 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1744 sizeof(struct qlc_83xx_entry_hdr));
1746 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1747 sizeof(struct qlc_83xx_poll));
1748 delay = (long)p_hdr->delay;
1750 for (i = 0; i < p_hdr->count; i++, entry++) {
1751 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1754 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1755 poll->mask, poll->status)){
1756 index = p_dev->ahw->reset.array_index;
1757 addr = entry->dr_addr;
1758 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1759 p_dev->ahw->reset.array[index++] = j;
1761 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1762 p_dev->ahw->reset.array_index = 1;
1768 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1770 p_dev->ahw->reset.seq_end = 1;
1773 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1775 p_dev->ahw->reset.template_end = 1;
1776 if (p_dev->ahw->reset.seq_error == 0)
1777 dev_err(&p_dev->pdev->dev,
1778 "HW restart process completed successfully.\n");
1780 dev_err(&p_dev->pdev->dev,
1781 "HW restart completed with timeout errors.\n");
1785 * qlcnic_83xx_exec_template_cmd
1787 * @p_dev: adapter structure
1788 * @p_buff: Poiter to instruction template
1790 * Template provides instructions to stop, restart and initalize firmware.
1791 * These instructions are abstracted as a series of read, write and
1792 * poll operations on hardware registers. Register information and operation
1793 * specifics are not exposed to the driver. Driver reads the template from
1794 * flash and executes the instructions located at pre-defined offsets.
1798 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1802 struct qlc_83xx_entry_hdr *p_hdr;
1803 char *entry = p_buff;
1805 p_dev->ahw->reset.seq_end = 0;
1806 p_dev->ahw->reset.template_end = 0;
1807 entries = p_dev->ahw->reset.hdr->entries;
1808 index = p_dev->ahw->reset.seq_index;
1810 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1811 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1813 switch (p_hdr->cmd) {
1814 case QLC_83XX_OPCODE_NOP:
1816 case QLC_83XX_OPCODE_WRITE_LIST:
1817 qlcnic_83xx_write_list(p_dev, p_hdr);
1819 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1820 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1822 case QLC_83XX_OPCODE_POLL_LIST:
1823 qlcnic_83xx_poll_list(p_dev, p_hdr);
1825 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1826 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1828 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1829 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1831 case QLC_83XX_OPCODE_SEQ_PAUSE:
1832 qlcnic_83xx_pause(p_hdr);
1834 case QLC_83XX_OPCODE_SEQ_END:
1835 qlcnic_83xx_seq_end(p_dev);
1837 case QLC_83XX_OPCODE_TMPL_END:
1838 qlcnic_83xx_template_end(p_dev);
1840 case QLC_83XX_OPCODE_POLL_READ_LIST:
1841 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1844 dev_err(&p_dev->pdev->dev,
1845 "%s: Unknown opcode 0x%04x in template %d\n",
1846 __func__, p_hdr->cmd, index);
1849 entry += p_hdr->size;
1851 p_dev->ahw->reset.seq_index = index;
1854 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1856 p_dev->ahw->reset.seq_index = 0;
1858 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1859 if (p_dev->ahw->reset.seq_end != 1)
1860 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1863 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1865 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1866 if (p_dev->ahw->reset.template_end != 1)
1867 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1870 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1872 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1873 if (p_dev->ahw->reset.seq_end != 1)
1874 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1877 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1881 if (request_firmware(&adapter->ahw->fw_info.fw,
1882 QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1883 dev_err(&adapter->pdev->dev,
1884 "No file FW image, loading flash FW image.\n");
1885 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1886 QLC_83XX_BOOT_FROM_FLASH);
1888 if (qlcnic_83xx_copy_fw_file(adapter))
1890 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1891 QLC_83XX_BOOT_FROM_FILE);
1897 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1902 qlcnic_83xx_stop_hw(adapter);
1904 /* Collect FW register dump if required */
1905 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1906 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1907 qlcnic_dump_fw(adapter);
1908 qlcnic_83xx_init_hw(adapter);
1910 if (qlcnic_83xx_copy_bootloader(adapter))
1912 /* Boot either flash image or firmware image from host file system */
1913 if (qlcnic_load_fw_file) {
1914 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1917 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1918 QLC_83XX_BOOT_FROM_FLASH);
1921 qlcnic_83xx_start_hw(adapter);
1922 if (qlcnic_83xx_check_hw_status(adapter))
1929 * qlcnic_83xx_config_default_opmode
1931 * @adapter: adapter structure
1933 * Configure default driver operating mode
1935 * Returns: Error code or Success(0)
1937 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1940 struct qlcnic_hardware_context *ahw = adapter->ahw;
1942 qlcnic_get_func_no(adapter);
1943 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1945 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1946 op_mode = QLC_83XX_DEFAULT_OPMODE;
1948 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1949 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1950 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1958 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1961 struct qlcnic_info nic_info;
1962 struct qlcnic_hardware_context *ahw = adapter->ahw;
1964 memset(&nic_info, 0, sizeof(struct qlcnic_info));
1965 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1969 ahw->physical_port = (u8) nic_info.phys_port;
1970 ahw->switch_mode = nic_info.switch_mode;
1971 ahw->max_tx_ques = nic_info.max_tx_ques;
1972 ahw->max_rx_ques = nic_info.max_rx_ques;
1973 ahw->capabilities = nic_info.capabilities;
1974 ahw->max_mac_filters = nic_info.max_mac_filters;
1975 ahw->max_mtu = nic_info.max_mtu;
1977 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1978 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1979 * exclusive. So in case of sriov capable device load driver in
1982 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1983 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1984 return ahw->nic_mode;
1987 if (ahw->capabilities & BIT_23)
1988 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1990 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1992 return ahw->nic_mode;
1995 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1999 ret = qlcnic_83xx_get_nic_configuration(adapter);
2003 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2004 if (qlcnic_83xx_config_vnic_opmode(adapter))
2006 } else if (ret == QLC_83XX_DEFAULT_MODE) {
2007 if (qlcnic_83xx_config_default_opmode(adapter))
2014 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2016 struct qlcnic_hardware_context *ahw = adapter->ahw;
2018 if (ahw->port_type == QLCNIC_XGBE) {
2019 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2020 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2021 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2022 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2024 } else if (ahw->port_type == QLCNIC_GBE) {
2025 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2026 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2027 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2028 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2030 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2031 adapter->max_rds_rings = MAX_RDS_RINGS;
2034 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2038 qlcnic_83xx_get_minidump_template(adapter);
2039 if (qlcnic_83xx_get_port_info(adapter))
2042 qlcnic_83xx_config_buff_descriptors(adapter);
2043 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2044 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2046 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2047 adapter->ahw->fw_hal_version);
2052 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2053 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2055 struct qlcnic_cmd_args cmd;
2056 u32 presence_mask, audit_mask;
2059 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2060 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2062 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2063 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2064 cmd.req.arg[1] = BIT_31;
2065 status = qlcnic_issue_cmd(adapter, &cmd);
2067 dev_err(&adapter->pdev->dev,
2068 "Failed to clean up the function resources\n");
2069 qlcnic_free_mbx_args(&cmd);
2073 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2075 struct qlcnic_hardware_context *ahw = adapter->ahw;
2077 if (qlcnic_sriov_vf_check(adapter))
2078 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2080 if (qlcnic_83xx_check_hw_status(adapter))
2083 /* Initilaize 83xx mailbox spinlock */
2084 spin_lock_init(&ahw->mbx_lock);
2086 set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2087 qlcnic_83xx_clear_function_resources(adapter);
2089 /* register for NIC IDC AEN Events */
2090 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2092 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2093 qlcnic_83xx_read_flash_mfg_id(adapter);
2095 if (qlcnic_83xx_idc_init(adapter))
2098 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2099 if (qlcnic_83xx_configure_opmode(adapter))
2102 /* Perform operating mode specific initialization */
2103 if (adapter->nic_ops->init_driver(adapter))
2106 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2108 /* Periodically monitor device status */
2109 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2111 return adapter->ahw->idc.err_code;