drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         adapter->netdev->trans_start = jiffies;
 386
 387         return 0;
 388 }
 389
 390 /**
 391  * qlcnic_83xx_idc_detach_driver
 392  *
 393  * @adapter: adapter structure
 394  * Detach net interface, stop TX and cleanup resources before the HW reset.
 395  * Returns: None
 396  *
 397  **/
 398 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 399 {
 400         int i;
 401         struct net_device *netdev = adapter->netdev;
 402
 403         netif_device_detach(netdev);
 404
 405         /* Disable mailbox interrupt */
 406         qlcnic_83xx_disable_mbx_intr(adapter);
 407         qlcnic_down(adapter, netdev);
 408         for (i = 0; i < adapter->ahw->num_msix; i++) {
 409                 adapter->ahw->intr_tbl[i].id = i;
 410                 adapter->ahw->intr_tbl[i].enabled = 0;
 411                 adapter->ahw->intr_tbl[i].src = 0;
 412         }
 413
 414         if (qlcnic_sriov_pf_check(adapter))
 415                 qlcnic_sriov_pf_reset(adapter);
 416 }
 417
 418 /**
 419  * qlcnic_83xx_idc_attach_driver
 420  *
 421  * @adapter: adapter structure
 422  *
 423  * Re-attach and re-enable net interface
 424  * Returns: None
 425  *
 426  **/
 427 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 428 {
 429         struct net_device *netdev = adapter->netdev;
 430
 431         if (netif_running(netdev)) {
 432                 if (qlcnic_up(adapter, netdev))
 433                         goto done;
 434                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 435         }
 436 done:
 437         netif_device_attach(netdev);
 438         if (netif_running(netdev)) {
 439                 netif_carrier_on(netdev);
 440                 netif_wake_queue(netdev);
 441         }
 442 }
 443
 444 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 445                                               int lock)
 446 {
 447         if (lock) {
 448                 if (qlcnic_83xx_lock_driver(adapter))
 449                         return -EBUSY;
 450         }
 451
 452         qlcnic_83xx_idc_clear_registers(adapter, 0);
 453         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 454         if (lock)
 455                 qlcnic_83xx_unlock_driver(adapter);
 456
 457         qlcnic_83xx_idc_log_state_history(adapter);
 458         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 459
 460         return 0;
 461 }
 462
 463 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 464                                             int lock)
 465 {
 466         if (lock) {
 467                 if (qlcnic_83xx_lock_driver(adapter))
 468                         return -EBUSY;
 469         }
 470
 471         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 472
 473         if (lock)
 474                 qlcnic_83xx_unlock_driver(adapter);
 475
 476         return 0;
 477 }
 478
 479 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 480                                               int lock)
 481 {
 482         if (lock) {
 483                 if (qlcnic_83xx_lock_driver(adapter))
 484                         return -EBUSY;
 485         }
 486
 487         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 488                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 489
 490         if (lock)
 491                 qlcnic_83xx_unlock_driver(adapter);
 492
 493         return 0;
 494 }
 495
 496 static int
 497 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 498 {
 499         if (lock) {
 500                 if (qlcnic_83xx_lock_driver(adapter))
 501                         return -EBUSY;
 502         }
 503
 504         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 505                QLC_83XX_IDC_DEV_NEED_RESET);
 506
 507         if (lock)
 508                 qlcnic_83xx_unlock_driver(adapter);
 509
 510         return 0;
 511 }
 512
 513 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 514                                              int lock)
 515 {
 516         if (lock) {
 517                 if (qlcnic_83xx_lock_driver(adapter))
 518                         return -EBUSY;
 519         }
 520
 521         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 522         if (lock)
 523                 qlcnic_83xx_unlock_driver(adapter);
 524
 525         return 0;
 526 }
 527
 528 /**
 529  * qlcnic_83xx_idc_find_reset_owner_id
 530  *
 531  * @adapter: adapter structure
 532  *
 533  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 534  * Within the same class, function with lowest PCI ID assumes ownership
 535  *
 536  * Returns: reset owner id or failure indication (-EIO)
 537  *
 538  **/
 539 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 540 {
 541         u32 reg, reg1, reg2, i, j, owner, class;
 542
 543         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 544         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 545         owner = QLCNIC_TYPE_NIC;
 546         i = 0;
 547         j = 0;
 548         reg = reg1;
 549
 550         do {
 551                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 552                 if (class == owner)
 553                         break;
 554                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 555                         reg = reg2;
 556                         j = 0;
 557                 } else {
 558                         j++;
 559                 }
 560
 561                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 562                         if (owner == QLCNIC_TYPE_NIC)
 563                                 owner = QLCNIC_TYPE_ISCSI;
 564                         else if (owner == QLCNIC_TYPE_ISCSI)
 565                                 owner = QLCNIC_TYPE_FCOE;
 566                         else if (owner == QLCNIC_TYPE_FCOE)
 567                                 return -EIO;
 568                         reg = reg1;
 569                         j = 0;
 570                         i = 0;
 571                 }
 572         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 573
 574         return i;
 575 }
 576
 577 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 578 {
 579         int ret = 0;
 580
 581         ret = qlcnic_83xx_restart_hw(adapter);
 582
 583         if (ret) {
 584                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 585         } else {
 586                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 587                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 588         }
 589
 590         return ret;
 591 }
 592
 593 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 594 {
 595         u32 status;
 596
 597         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 598
 599         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 600                 dev_err(&adapter->pdev->dev,
 601                         "peg halt status1=0x%x\n", status);
 602                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 603                         dev_err(&adapter->pdev->dev,
 604                                 "On board active cooling fan failed. "
 605                                 "Device has been halted.\n");
 606                         dev_err(&adapter->pdev->dev,
 607                                 "Replace the adapter.\n");
 608                         return -EIO;
 609                 }
 610         }
 611
 612         return 0;
 613 }
 614
 615 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 616 {
 617         int err;
 618
 619         /* register for NIC IDC AEN Events */
 620         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 621
 622         err = qlcnic_sriov_pf_reinit(adapter);
 623         if (err)
 624                 return err;
 625
 626         qlcnic_83xx_enable_mbx_intrpt(adapter);
 627
 628         if (qlcnic_83xx_configure_opmode(adapter)) {
 629                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 630                 return -EIO;
 631         }
 632
 633         if (adapter->nic_ops->init_driver(adapter)) {
 634                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 635                 return -EIO;
 636         }
 637
 638         qlcnic_83xx_idc_attach_driver(adapter);
 639
 640         return 0;
 641 }
 642
 643 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 644 {
 645         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 646         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 647         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 648         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 649         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 650         adapter->ahw->idc.quiesce_req = 0;
 651         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 652         adapter->ahw->idc.err_code = 0;
 653         adapter->ahw->idc.collect_dump = 0;
 654 }
 655
 656 /**
 657  * qlcnic_83xx_idc_ready_state_entry
 658  *
 659  * @adapter: adapter structure
 660  *
 661  * Perform ready state initialization, this routine will get invoked only
 662  * once from READY state.
 663  *
 664  * Returns: Error code or Success(0)
 665  *
 666  **/
 667 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 668 {
 669         struct qlcnic_hardware_context *ahw = adapter->ahw;
 670
 671         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 672                 qlcnic_83xx_idc_update_idc_params(adapter);
 673                 /* Re-attach the device if required */
 674                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 675                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 676                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 677                                 return -EIO;
 678                 }
 679         }
 680
 681         return 0;
 682 }
 683
 684 /**
 685  * qlcnic_83xx_idc_vnic_pf_entry
 686  *
 687  * @adapter: adapter structure
 688  *
 689  * Ensure vNIC mode privileged function starts only after vNIC mode is
 690  * enabled by management function.
 691  * If vNIC mode is ready, start initialization.
 692  *
 693  * Returns: -EIO or 0
 694  *
 695  **/
 696 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 697 {
 698         u32 state;
 699         struct qlcnic_hardware_context *ahw = adapter->ahw;
 700
 701         /* Privileged function waits till mgmt function enables VNIC mode */
 702         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 703         if (state != QLCNIC_DEV_NPAR_OPER) {
 704                 if (!ahw->idc.vnic_wait_limit--) {
 705                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 706                         return -EIO;
 707                 }
 708                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 709                 return -EIO;
 710
 711         } else {
 712                 /* Perform one time initialization from ready state */
 713                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 714                         qlcnic_83xx_idc_update_idc_params(adapter);
 715
 716                         /* If the previous state is UNKNOWN, device will be
 717                            already attached properly by Init routine*/
 718                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 719                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 720                                         return -EIO;
 721                         }
 722                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 723                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 724                 }
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 731 {
 732         adapter->ahw->idc.err_code = -EIO;
 733         dev_err(&adapter->pdev->dev,
 734                 "%s: Device in unknown state\n", __func__);
 735         return 0;
 736 }
 737
 738 /**
 739  * qlcnic_83xx_idc_cold_state
 740  *
 741  * @adapter: adapter structure
 742  *
 743  * If HW is up and running device will enter READY state.
 744  * If firmware image from host needs to be loaded, device is
 745  * forced to start with the file firmware image.
 746  *
 747  * Returns: Error code or Success(0)
 748  *
 749  **/
 750 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 751 {
 752         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 753         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 754
 755         if (qlcnic_load_fw_file) {
 756                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 757         } else {
 758                 if (qlcnic_83xx_check_hw_status(adapter)) {
 759                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 760                         return -EIO;
 761                 } else {
 762                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 763                 }
 764         }
 765         return 0;
 766 }
 767
 768 /**
 769  * qlcnic_83xx_idc_init_state
 770  *
 771  * @adapter: adapter structure
 772  *
 773  * Reset owner will restart the device from this state.
 774  * Device will enter failed state if it remains
 775  * in this state for more than DEV_INIT time limit.
 776  *
 777  * Returns: Error code or Success(0)
 778  *
 779  **/
 780 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 781 {
 782         int timeout, ret = 0;
 783         u32 owner;
 784
 785         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 786         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 787                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 788                 if (adapter->ahw->pci_func == owner)
 789                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 790         } else {
 791                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 792                 return ret;
 793         }
 794
 795         return ret;
 796 }
 797
 798 /**
 799  * qlcnic_83xx_idc_ready_state
 800  *
 801  * @adapter: adapter structure
 802  *
 803  * Perform IDC protocol specicifed actions after monitoring device state and
 804  * events.
 805  *
 806  * Returns: Error code or Success(0)
 807  *
 808  **/
 809 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 810 {
 811         u32 val;
 812         struct qlcnic_hardware_context *ahw = adapter->ahw;
 813         int ret = 0;
 814
 815         /* Perform NIC configuration based ready state entry actions */
 816         if (ahw->idc.state_entry(adapter))
 817                 return -EIO;
 818
 819         if (qlcnic_check_temp(adapter)) {
 820                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 821                         qlcnic_83xx_idc_check_fan_failure(adapter);
 822                         dev_err(&adapter->pdev->dev,
 823                                 "Error: device temperature %d above limits\n",
 824                                 adapter->ahw->temp);
 825                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 826                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 827                         qlcnic_83xx_idc_detach_driver(adapter);
 828                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 829                         return -EIO;
 830                 }
 831         }
 832
 833         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 834         ret = qlcnic_83xx_check_heartbeat(adapter);
 835         if (ret) {
 836                 adapter->flags |= QLCNIC_FW_HANG;
 837                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 838                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 839                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 840                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 841                 }
 842                 return -EIO;
 843         }
 844
 845         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 846                 /* Move to need reset state and prepare for reset */
 847                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 848                 return ret;
 849         }
 850
 851         /* Check for soft reset request */
 852         if (ahw->reset_context &&
 853             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 854                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 855                 return ret;
 856         }
 857
 858         /* Move to need quiesce state if requested */
 859         if (adapter->ahw->idc.quiesce_req) {
 860                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 861                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 862                 return ret;
 863         }
 864
 865         return ret;
 866 }
 867
 868 /**
 869  * qlcnic_83xx_idc_need_reset_state
 870  *
 871  * @adapter: adapter structure
 872  *
 873  * Device will remain in this state until:
 874  *      Reset request ACK's are recieved from all the functions
 875  *      Wait time exceeds max time limit
 876  *
 877  * Returns: Error code or Success(0)
 878  *
 879  **/
 880 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 881 {
 882         int ret = 0;
 883
 884         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 885                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 886                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 887                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 888                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 889                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 890                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 891                 qlcnic_83xx_idc_detach_driver(adapter);
 892         }
 893
 894         /* Check ACK from other functions */
 895         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 896         if (ret) {
 897                 dev_info(&adapter->pdev->dev,
 898                          "%s: Waiting for reset ACK\n", __func__);
 899                 return 0;
 900         }
 901
 902         /* Transit to INIT state and restart the HW */
 903         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 904
 905         return ret;
 906 }
 907
 908 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 909 {
 910         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 911         return 0;
 912 }
 913
 914 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 915 {
 916         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 917         adapter->ahw->idc.err_code = -EIO;
 918
 919         return 0;
 920 }
 921
 922 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 923 {
 924         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 925         return 0;
 926 }
 927
 928 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 929                                                 u32 state)
 930 {
 931         u32 cur, prev, next;
 932
 933         cur = adapter->ahw->idc.curr_state;
 934         prev = adapter->ahw->idc.prev_state;
 935         next = state;
 936
 937         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 938             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 939                 dev_err(&adapter->pdev->dev,
 940                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 941                         __func__, cur, prev, state);
 942                 return 1;
 943         }
 944
 945         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 946             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 947                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 948                     (next != QLC_83XX_IDC_DEV_READY)) {
 949                         dev_err(&adapter->pdev->dev,
 950                                 "%s: failed, cur %d prev %d next %d\n",
 951                                 __func__, cur, prev, next);
 952                         return 1;
 953                 }
 954         }
 955
 956         if (next == QLC_83XX_IDC_DEV_INIT) {
 957                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 958                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 959                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 960                         dev_err(&adapter->pdev->dev,
 961                                 "%s: failed, cur %d prev %d next %d\n",
 962                                 __func__, cur, prev, next);
 963                         return 1;
 964                 }
 965         }
 966
 967         return 0;
 968 }
 969
 970 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 971 {
 972         if (adapter->fhash.fnum)
 973                 qlcnic_prune_lb_filters(adapter);
 974 }
 975
 976 /**
 977  * qlcnic_83xx_idc_poll_dev_state
 978  *
 979  * @work: kernel work queue structure used to schedule the function
 980  *
 981  * Poll device state periodically and perform state specific
 982  * actions defined by Inter Driver Communication (IDC) protocol.
 983  *
 984  * Returns: None
 985  *
 986  **/
 987 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 988 {
 989         struct qlcnic_adapter *adapter;
 990         u32 state;
 991
 992         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 993         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 994
 995         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
 996                 qlcnic_83xx_idc_log_state_history(adapter);
 997                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
 998         } else {
 999                 adapter->ahw->idc.curr_state = state;
1000         }
1001
1002         switch (adapter->ahw->idc.curr_state) {
1003         case QLC_83XX_IDC_DEV_READY:
1004                 qlcnic_83xx_idc_ready_state(adapter);
1005                 break;
1006         case QLC_83XX_IDC_DEV_NEED_RESET:
1007                 qlcnic_83xx_idc_need_reset_state(adapter);
1008                 break;
1009         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1010                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1011                 break;
1012         case QLC_83XX_IDC_DEV_FAILED:
1013                 qlcnic_83xx_idc_failed_state(adapter);
1014                 return;
1015         case QLC_83XX_IDC_DEV_INIT:
1016                 qlcnic_83xx_idc_init_state(adapter);
1017                 break;
1018         case QLC_83XX_IDC_DEV_QUISCENT:
1019                 qlcnic_83xx_idc_quiesce_state(adapter);
1020                 break;
1021         default:
1022                 qlcnic_83xx_idc_unknown_state(adapter);
1023                 return;
1024         }
1025         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1026         qlcnic_83xx_periodic_tasks(adapter);
1027
1028         /* Re-schedule the function */
1029         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1030                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1031                                      adapter->ahw->idc.delay);
1032 }
1033
1034 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1035 {
1036         u32 idc_params, val;
1037
1038         if (qlcnic_83xx_lockless_flash_read32(adapter,
1039                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1040                                               (u8 *)&idc_params, 1)) {
1041                 dev_info(&adapter->pdev->dev,
1042                          "%s:failed to get IDC params from flash\n", __func__);
1043                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1044                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1045         } else {
1046                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1047                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1048         }
1049
1050         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1051         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1052         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1053         adapter->ahw->idc.err_code = 0;
1054         adapter->ahw->idc.collect_dump = 0;
1055         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1056
1057         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1058         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1059         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1060
1061         /* Check if reset recovery is disabled */
1062         if (!qlcnic_auto_fw_reset) {
1063                 /* Propagate do not reset request to other functions */
1064                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1065                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1066                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1067         }
1068 }
1069
1070 static int
1071 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1072 {
1073         u32 state, val;
1074
1075         if (qlcnic_83xx_lock_driver(adapter))
1076                 return -EIO;
1077
1078         /* Clear driver lock register */
1079         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1080         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1081                 qlcnic_83xx_unlock_driver(adapter);
1082                 return -EIO;
1083         }
1084
1085         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1086         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1087                 qlcnic_83xx_unlock_driver(adapter);
1088                 return -EIO;
1089         }
1090
1091         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1092                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1093                        QLC_83XX_IDC_DEV_COLD);
1094                 state = QLC_83XX_IDC_DEV_COLD;
1095         }
1096
1097         adapter->ahw->idc.curr_state = state;
1098         /* First to load function should cold boot the device */
1099         if (state == QLC_83XX_IDC_DEV_COLD)
1100                 qlcnic_83xx_idc_cold_state_handler(adapter);
1101
1102         /* Check if reset recovery is enabled */
1103         if (qlcnic_auto_fw_reset) {
1104                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1105                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1106                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1107         }
1108
1109         qlcnic_83xx_unlock_driver(adapter);
1110
1111         return 0;
1112 }
1113
1114 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1115 {
1116         int ret = -EIO;
1117
1118         qlcnic_83xx_setup_idc_parameters(adapter);
1119
1120         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1121                 return ret;
1122
1123         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1124                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1125                         return -EIO;
1126         } else {
1127                 if (qlcnic_83xx_idc_check_major_version(adapter))
1128                         return -EIO;
1129         }
1130
1131         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1132
1133         return 0;
1134 }
1135
1136 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1137 {
1138         int id;
1139         u32 val;
1140
1141         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1142                 usleep_range(10000, 11000);
1143
1144         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1145         id = id & 0xFF;
1146
1147         if (id == adapter->portnum) {
1148                 dev_err(&adapter->pdev->dev,
1149                         "%s: wait for lock recovery.. %d\n", __func__, id);
1150                 msleep(20);
1151                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1152                 id = id & 0xFF;
1153         }
1154
1155         /* Clear driver presence bit */
1156         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1157         val = val & ~(1 << adapter->portnum);
1158         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1159         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1160         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1161
1162         cancel_delayed_work_sync(&adapter->fw_work);
1163 }
1164
1165 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1166 {
1167         u32 val;
1168
1169         if (qlcnic_83xx_lock_driver(adapter)) {
1170                 dev_err(&adapter->pdev->dev,
1171                         "%s:failed, please retry\n", __func__);
1172                 return;
1173         }
1174
1175         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1176         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1177             !qlcnic_auto_fw_reset) {
1178                 dev_err(&adapter->pdev->dev,
1179                         "%s:failed, device in non reset mode\n", __func__);
1180                 qlcnic_83xx_unlock_driver(adapter);
1181                 return;
1182         }
1183
1184         if (key == QLCNIC_FORCE_FW_RESET) {
1185                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1186                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1187                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1188         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1189                 adapter->ahw->idc.collect_dump = 1;
1190         }
1191
1192         qlcnic_83xx_unlock_driver(adapter);
1193         return;
1194 }
1195
1196 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1197 {
1198         u8 *p_cache;
1199         u32 src, size;
1200         u64 dest;
1201         int ret = -EIO;
1202
1203         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1204         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1205         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1206
1207         /* alignment check */
1208         if (size & 0xF)
1209                 size = (size + 16) & ~0xF;
1210
1211         p_cache = kzalloc(size, GFP_KERNEL);
1212         if (p_cache == NULL)
1213                 return -ENOMEM;
1214
1215         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1216                                                 size / sizeof(u32));
1217         if (ret) {
1218                 kfree(p_cache);
1219                 return ret;
1220         }
1221         /* 16 byte write to MS memory */
1222         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1223                                           size / 16);
1224         if (ret) {
1225                 kfree(p_cache);
1226                 return ret;
1227         }
1228         kfree(p_cache);
1229
1230         return ret;
1231 }
1232
1233 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1234 {
1235         u32 dest, *p_cache;
1236         u64 addr;
1237         u8 data[16];
1238         size_t size;
1239         int i, ret = -EIO;
1240
1241         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1242         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1243         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1244         addr = (u64)dest;
1245
1246         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1247                                           (u32 *)p_cache, size / 16);
1248         if (ret) {
1249                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1250                 release_firmware(adapter->ahw->fw_info.fw);
1251                 adapter->ahw->fw_info.fw = NULL;
1252                 return -EIO;
1253         }
1254
1255         /* alignment check */
1256         if (adapter->ahw->fw_info.fw->size & 0xF) {
1257                 addr = dest + size;
1258                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1259                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1260                 for (; i < 16; i++)
1261                         data[i] = 0;
1262                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1263                                                   (u32 *)data, 1);
1264                 if (ret) {
1265                         dev_err(&adapter->pdev->dev,
1266                                 "MS memory write failed\n");
1267                         release_firmware(adapter->ahw->fw_info.fw);
1268                         adapter->ahw->fw_info.fw = NULL;
1269                         return -EIO;
1270                 }
1271         }
1272         release_firmware(adapter->ahw->fw_info.fw);
1273         adapter->ahw->fw_info.fw = NULL;
1274
1275         return 0;
1276 }
1277
1278 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1279 {
1280         int i, j;
1281         u32 val = 0, val1 = 0, reg = 0;
1282
1283         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1284         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1285
1286         for (j = 0; j < 2; j++) {
1287                 if (j == 0) {
1288                         dev_info(&adapter->pdev->dev,
1289                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1290                         reg = QLC_83XX_PORT0_THRESHOLD;
1291                 } else if (j == 1) {
1292                         dev_info(&adapter->pdev->dev,
1293                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1294                         reg = QLC_83XX_PORT1_THRESHOLD;
1295                 }
1296                 for (i = 0; i < 8; i++) {
1297                         val = QLCRD32(adapter, reg + (i * 0x4));
1298                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1299                 }
1300                 dev_info(&adapter->pdev->dev, "\n");
1301         }
1302
1303         for (j = 0; j < 2; j++) {
1304                 if (j == 0) {
1305                         dev_info(&adapter->pdev->dev,
1306                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1307                         reg = QLC_83XX_PORT0_TC_MC_REG;
1308                 } else if (j == 1) {
1309                         dev_info(&adapter->pdev->dev,
1310                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1311                         reg = QLC_83XX_PORT1_TC_MC_REG;
1312                 }
1313                 for (i = 0; i < 4; i++) {
1314                         val = QLCRD32(adapter, reg + (i * 0x4));
1315                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1316                 }
1317                 dev_info(&adapter->pdev->dev, "\n");
1318         }
1319
1320         for (j = 0; j < 2; j++) {
1321                 if (j == 0) {
1322                         dev_info(&adapter->pdev->dev,
1323                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1324                         reg = QLC_83XX_PORT0_TC_STATS;
1325                 } else if (j == 1) {
1326                         dev_info(&adapter->pdev->dev,
1327                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1328                         reg = QLC_83XX_PORT1_TC_STATS;
1329                 }
1330                 for (i = 7; i >= 0; i--) {
1331                         val = QLCRD32(adapter, reg);
1332                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1333                         QLCWR32(adapter, reg, (val | (i << 29)));
1334                         val = QLCRD32(adapter, reg);
1335                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1336                 }
1337                 dev_info(&adapter->pdev->dev, "\n");
1338         }
1339
1340         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1341         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1342         dev_info(&adapter->pdev->dev,
1343                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1344                  val, val1);
1345 }
1346
1347
1348 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1349 {
1350         u32 reg = 0, i, j;
1351
1352         if (qlcnic_83xx_lock_driver(adapter)) {
1353                 dev_err(&adapter->pdev->dev,
1354                         "%s:failed to acquire driver lock\n", __func__);
1355                 return;
1356         }
1357
1358         qlcnic_83xx_dump_pause_control_regs(adapter);
1359         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1360
1361         for (j = 0; j < 2; j++) {
1362                 if (j == 0)
1363                         reg = QLC_83XX_PORT0_THRESHOLD;
1364                 else if (j == 1)
1365                         reg = QLC_83XX_PORT1_THRESHOLD;
1366
1367                 for (i = 0; i < 8; i++)
1368                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1369         }
1370
1371         for (j = 0; j < 2; j++) {
1372                 if (j == 0)
1373                         reg = QLC_83XX_PORT0_TC_MC_REG;
1374                 else if (j == 1)
1375                         reg = QLC_83XX_PORT1_TC_MC_REG;
1376
1377                 for (i = 0; i < 4; i++)
1378                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1379         }
1380
1381         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1382         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1383         dev_info(&adapter->pdev->dev,
1384                  "Disabled pause frames successfully on all ports\n");
1385         qlcnic_83xx_unlock_driver(adapter);
1386 }
1387
1388 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1389 {
1390         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1391         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1392         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1393         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1394         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1395         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1396         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1397         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1398         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1399 }
1400
1401 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1402 {
1403         u32 heartbeat, peg_status;
1404         int retries, ret = -EIO;
1405
1406         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1407         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1408                                                QLCNIC_PEG_ALIVE_COUNTER);
1409
1410         do {
1411                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1412                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1413                                                 QLCNIC_PEG_ALIVE_COUNTER);
1414                 if (heartbeat != p_dev->heartbeat) {
1415                         ret = QLCNIC_RCODE_SUCCESS;
1416                         break;
1417                 }
1418         } while (--retries);
1419
1420         if (ret) {
1421                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1422                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1423                 qlcnic_83xx_disable_pause_frames(p_dev);
1424                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1425                                                  QLCNIC_PEG_HALT_STATUS1);
1426                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1427                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1428                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1429                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1430                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1431                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1432                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1433                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1434                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1435                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1436                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1437
1438                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1439                         dev_err(&p_dev->pdev->dev,
1440                                 "Device is being reset err code 0x00006700.\n");
1441         }
1442
1443         return ret;
1444 }
1445
1446 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1447 {
1448         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1449         u32 val;
1450
1451         do {
1452                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1453                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1454                         return 0;
1455                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1456         } while (--retries);
1457
1458         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1459         return -EIO;
1460 }
1461
1462 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1463 {
1464         int err;
1465
1466         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1467         if (err)
1468                 return err;
1469
1470         err = qlcnic_83xx_check_heartbeat(p_dev);
1471         if (err)
1472                 return err;
1473
1474         return err;
1475 }
1476
1477 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1478                                 int duration, u32 mask, u32 status)
1479 {
1480         u32 value;
1481         int timeout_error;
1482         u8 retries;
1483
1484         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1485         retries = duration / 10;
1486
1487         do {
1488                 if ((value & mask) != status) {
1489                         timeout_error = 1;
1490                         msleep(duration / 10);
1491                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1492                 } else {
1493                         timeout_error = 0;
1494                         break;
1495                 }
1496         } while (retries--);
1497
1498         if (timeout_error) {
1499                 p_dev->ahw->reset.seq_error++;
1500                 dev_err(&p_dev->pdev->dev,
1501                         "%s: Timeout Err, entry_num = %d\n",
1502                         __func__, p_dev->ahw->reset.seq_index);
1503                 dev_err(&p_dev->pdev->dev,
1504                         "0x%08x 0x%08x 0x%08x\n",
1505                         value, mask, status);
1506         }
1507
1508         return timeout_error;
1509 }
1510
1511 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1512 {
1513         u32 sum = 0;
1514         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1515         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1516
1517         while (count-- > 0)
1518                 sum += *buff++;
1519
1520         while (sum >> 16)
1521                 sum = (sum & 0xFFFF) + (sum >> 16);
1522
1523         if (~sum) {
1524                 return 0;
1525         } else {
1526                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1527                 return -1;
1528         }
1529 }
1530
1531 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1532 {
1533         u8 *p_buff;
1534         u32 addr, count;
1535         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1536
1537         ahw->reset.seq_error = 0;
1538         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1539         if (p_dev->ahw->reset.buff == NULL)
1540                 return -ENOMEM;
1541
1542         p_buff = p_dev->ahw->reset.buff;
1543         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1544         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1545
1546         /* Copy template header from flash */
1547         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1548                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1549                 return -EIO;
1550         }
1551         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1552         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1553         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1554         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1555
1556         /* Copy rest of the template */
1557         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1558                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1559                 return -EIO;
1560         }
1561
1562         if (qlcnic_83xx_reset_template_checksum(p_dev))
1563                 return -EIO;
1564         /* Get Stop, Start and Init command offsets */
1565         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1566         ahw->reset.start_offset = ahw->reset.buff +
1567                                   ahw->reset.hdr->start_offset;
1568         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1569         return 0;
1570 }
1571
1572 /* Read Write HW register command */
1573 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1574                                            u32 raddr, u32 waddr)
1575 {
1576         int value;
1577
1578         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1579         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1580 }
1581
1582 /* Read Modify Write HW register command */
1583 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1584                                     u32 raddr, u32 waddr,
1585                                     struct qlc_83xx_rmw *p_rmw_hdr)
1586 {
1587         int value;
1588
1589         if (p_rmw_hdr->index_a)
1590                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1591         else
1592                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1593
1594         value &= p_rmw_hdr->mask;
1595         value <<= p_rmw_hdr->shl;
1596         value >>= p_rmw_hdr->shr;
1597         value |= p_rmw_hdr->or_value;
1598         value ^= p_rmw_hdr->xor_value;
1599         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1600 }
1601
1602 /* Write HW register command */
1603 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1604                                    struct qlc_83xx_entry_hdr *p_hdr)
1605 {
1606         int i;
1607         struct qlc_83xx_entry *entry;
1608
1609         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1610                                           sizeof(struct qlc_83xx_entry_hdr));
1611
1612         for (i = 0; i < p_hdr->count; i++, entry++) {
1613                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1614                                              entry->arg2);
1615                 if (p_hdr->delay)
1616                         udelay((u32)(p_hdr->delay));
1617         }
1618 }
1619
1620 /* Read and Write instruction */
1621 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1622                                         struct qlc_83xx_entry_hdr *p_hdr)
1623 {
1624         int i;
1625         struct qlc_83xx_entry *entry;
1626
1627         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1628                                           sizeof(struct qlc_83xx_entry_hdr));
1629
1630         for (i = 0; i < p_hdr->count; i++, entry++) {
1631                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1632                                                entry->arg2);
1633                 if (p_hdr->delay)
1634                         udelay((u32)(p_hdr->delay));
1635         }
1636 }
1637
1638 /* Poll HW register command */
1639 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1640                                   struct qlc_83xx_entry_hdr *p_hdr)
1641 {
1642         long delay;
1643         struct qlc_83xx_entry *entry;
1644         struct qlc_83xx_poll *poll;
1645         int i;
1646         unsigned long arg1, arg2;
1647
1648         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1649                                         sizeof(struct qlc_83xx_entry_hdr));
1650
1651         entry = (struct qlc_83xx_entry *)((char *)poll +
1652                                           sizeof(struct qlc_83xx_poll));
1653         delay = (long)p_hdr->delay;
1654
1655         if (!delay) {
1656                 for (i = 0; i < p_hdr->count; i++, entry++)
1657                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1658                                              delay, poll->mask,
1659                                              poll->status);
1660         } else {
1661                 for (i = 0; i < p_hdr->count; i++, entry++) {
1662                         arg1 = entry->arg1;
1663                         arg2 = entry->arg2;
1664                         if (delay) {
1665                                 if (qlcnic_83xx_poll_reg(p_dev,
1666                                                          arg1, delay,
1667                                                          poll->mask,
1668                                                          poll->status)){
1669                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1670                                                                     arg1);
1671                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1672                                                                     arg2);
1673                                 }
1674                         }
1675                 }
1676         }
1677 }
1678
1679 /* Poll and write HW register command */
1680 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1681                                         struct qlc_83xx_entry_hdr *p_hdr)
1682 {
1683         int i;
1684         long delay;
1685         struct qlc_83xx_quad_entry *entry;
1686         struct qlc_83xx_poll *poll;
1687
1688         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1689                                         sizeof(struct qlc_83xx_entry_hdr));
1690         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1691                                                sizeof(struct qlc_83xx_poll));
1692         delay = (long)p_hdr->delay;
1693
1694         for (i = 0; i < p_hdr->count; i++, entry++) {
1695                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1696                                              entry->dr_value);
1697                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1698                                              entry->ar_value);
1699                 if (delay)
1700                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1701                                              poll->mask, poll->status);
1702         }
1703 }
1704
1705 /* Read Modify Write register command */
1706 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1707                                           struct qlc_83xx_entry_hdr *p_hdr)
1708 {
1709         int i;
1710         struct qlc_83xx_entry *entry;
1711         struct qlc_83xx_rmw *rmw_hdr;
1712
1713         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1714                                           sizeof(struct qlc_83xx_entry_hdr));
1715
1716         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1717                                           sizeof(struct qlc_83xx_rmw));
1718
1719         for (i = 0; i < p_hdr->count; i++, entry++) {
1720                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1721                                         entry->arg2, rmw_hdr);
1722                 if (p_hdr->delay)
1723                         udelay((u32)(p_hdr->delay));
1724         }
1725 }
1726
1727 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1728 {
1729         if (p_hdr->delay)
1730                 mdelay((u32)((long)p_hdr->delay));
1731 }
1732
1733 /* Read and poll register command */
1734 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1735                                        struct qlc_83xx_entry_hdr *p_hdr)
1736 {
1737         long delay;
1738         int index, i, j;
1739         struct qlc_83xx_quad_entry *entry;
1740         struct qlc_83xx_poll *poll;
1741         unsigned long addr;
1742
1743         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1744                                         sizeof(struct qlc_83xx_entry_hdr));
1745
1746         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1747                                                sizeof(struct qlc_83xx_poll));
1748         delay = (long)p_hdr->delay;
1749
1750         for (i = 0; i < p_hdr->count; i++, entry++) {
1751                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1752                                              entry->ar_value);
1753                 if (delay) {
1754                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1755                                                   poll->mask, poll->status)){
1756                                 index = p_dev->ahw->reset.array_index;
1757                                 addr = entry->dr_addr;
1758                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1759                                 p_dev->ahw->reset.array[index++] = j;
1760
1761                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1762                                         p_dev->ahw->reset.array_index = 1;
1763                         }
1764                 }
1765         }
1766 }
1767
1768 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1769 {
1770         p_dev->ahw->reset.seq_end = 1;
1771 }
1772
1773 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1774 {
1775         p_dev->ahw->reset.template_end = 1;
1776         if (p_dev->ahw->reset.seq_error == 0)
1777                 dev_err(&p_dev->pdev->dev,
1778                         "HW restart process completed successfully.\n");
1779         else
1780                 dev_err(&p_dev->pdev->dev,
1781                         "HW restart completed with timeout errors.\n");
1782 }
1783
1784 /**
1785 * qlcnic_83xx_exec_template_cmd
1786 *
1787 * @p_dev: adapter structure
1788 * @p_buff: Poiter to instruction template
1789 *
1790 * Template provides instructions to stop, restart and initalize firmware.
1791 * These instructions are abstracted as a series of read, write and
1792 * poll operations on hardware registers. Register information and operation
1793 * specifics are not exposed to the driver. Driver reads the template from
1794 * flash and executes the instructions located at pre-defined offsets.
1795 *
1796 * Returns: None
1797 * */
1798 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1799                                           char *p_buff)
1800 {
1801         int index, entries;
1802         struct qlc_83xx_entry_hdr *p_hdr;
1803         char *entry = p_buff;
1804
1805         p_dev->ahw->reset.seq_end = 0;
1806         p_dev->ahw->reset.template_end = 0;
1807         entries = p_dev->ahw->reset.hdr->entries;
1808         index = p_dev->ahw->reset.seq_index;
1809
1810         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1811                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1812
1813                 switch (p_hdr->cmd) {
1814                 case QLC_83XX_OPCODE_NOP:
1815                         break;
1816                 case QLC_83XX_OPCODE_WRITE_LIST:
1817                         qlcnic_83xx_write_list(p_dev, p_hdr);
1818                         break;
1819                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1820                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1821                         break;
1822                 case QLC_83XX_OPCODE_POLL_LIST:
1823                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1824                         break;
1825                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1826                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1827                         break;
1828                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1829                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1830                         break;
1831                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1832                         qlcnic_83xx_pause(p_hdr);
1833                         break;
1834                 case QLC_83XX_OPCODE_SEQ_END:
1835                         qlcnic_83xx_seq_end(p_dev);
1836                         break;
1837                 case QLC_83XX_OPCODE_TMPL_END:
1838                         qlcnic_83xx_template_end(p_dev);
1839                         break;
1840                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1841                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1842                         break;
1843                 default:
1844                         dev_err(&p_dev->pdev->dev,
1845                                 "%s: Unknown opcode 0x%04x in template %d\n",
1846                                 __func__, p_hdr->cmd, index);
1847                         break;
1848                 }
1849                 entry += p_hdr->size;
1850         }
1851         p_dev->ahw->reset.seq_index = index;
1852 }
1853
1854 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1855 {
1856         p_dev->ahw->reset.seq_index = 0;
1857
1858         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1859         if (p_dev->ahw->reset.seq_end != 1)
1860                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1861 }
1862
1863 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1864 {
1865         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1866         if (p_dev->ahw->reset.template_end != 1)
1867                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1868 }
1869
1870 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1871 {
1872         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1873         if (p_dev->ahw->reset.seq_end != 1)
1874                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1875 }
1876
1877 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1878 {
1879         int err = -EIO;
1880
1881         if (request_firmware(&adapter->ahw->fw_info.fw,
1882                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1883                 dev_err(&adapter->pdev->dev,
1884                         "No file FW image, loading flash FW image.\n");
1885                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1886                                     QLC_83XX_BOOT_FROM_FLASH);
1887         } else {
1888                 if (qlcnic_83xx_copy_fw_file(adapter))
1889                         return err;
1890                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1891                                     QLC_83XX_BOOT_FROM_FILE);
1892         }
1893
1894         return 0;
1895 }
1896
1897 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1898 {
1899         u32 val;
1900         int err = -EIO;
1901
1902         qlcnic_83xx_stop_hw(adapter);
1903
1904         /* Collect FW register dump if required */
1905         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1906         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1907                 qlcnic_dump_fw(adapter);
1908         qlcnic_83xx_init_hw(adapter);
1909
1910         if (qlcnic_83xx_copy_bootloader(adapter))
1911                 return err;
1912         /* Boot either flash image or firmware image from host file system */
1913         if (qlcnic_load_fw_file) {
1914                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1915                         return err;
1916         } else {
1917                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1918                                     QLC_83XX_BOOT_FROM_FLASH);
1919         }
1920
1921         qlcnic_83xx_start_hw(adapter);
1922         if (qlcnic_83xx_check_hw_status(adapter))
1923                 return -EIO;
1924
1925         return 0;
1926 }
1927
1928 /**
1929 * qlcnic_83xx_config_default_opmode
1930 *
1931 * @adapter: adapter structure
1932 *
1933 * Configure default driver operating mode
1934 *
1935 * Returns: Error code or Success(0)
1936 * */
1937 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1938 {
1939         u32 op_mode;
1940         struct qlcnic_hardware_context *ahw = adapter->ahw;
1941
1942         qlcnic_get_func_no(adapter);
1943         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1944
1945         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1946                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1947
1948         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1949                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1950                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1951         } else {
1952                 return -EIO;
1953         }
1954
1955         return 0;
1956 }
1957
1958 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1959 {
1960         int err;
1961         struct qlcnic_info nic_info;
1962         struct qlcnic_hardware_context *ahw = adapter->ahw;
1963
1964         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1965         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1966         if (err)
1967                 return -EIO;
1968
1969         ahw->physical_port = (u8) nic_info.phys_port;
1970         ahw->switch_mode = nic_info.switch_mode;
1971         ahw->max_tx_ques = nic_info.max_tx_ques;
1972         ahw->max_rx_ques = nic_info.max_rx_ques;
1973         ahw->capabilities = nic_info.capabilities;
1974         ahw->max_mac_filters = nic_info.max_mac_filters;
1975         ahw->max_mtu = nic_info.max_mtu;
1976
1977         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1978          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1979          * exclusive. So in case of sriov capable device load driver in
1980          * default mode
1981          */
1982         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1983                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1984                 return ahw->nic_mode;
1985         }
1986
1987         if (ahw->capabilities & BIT_23)
1988                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1989         else
1990                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1991
1992         return ahw->nic_mode;
1993 }
1994
1995 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1996 {
1997         int ret;
1998
1999         ret = qlcnic_83xx_get_nic_configuration(adapter);
2000         if (ret == -EIO)
2001                 return -EIO;
2002
2003         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2004                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2005                         return -EIO;
2006         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2007                 if (qlcnic_83xx_config_default_opmode(adapter))
2008                         return -EIO;
2009         }
2010
2011         return 0;
2012 }
2013
2014 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2015 {
2016         struct qlcnic_hardware_context *ahw = adapter->ahw;
2017
2018         if (ahw->port_type == QLCNIC_XGBE) {
2019                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2020                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2021                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2022                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2023
2024         } else if (ahw->port_type == QLCNIC_GBE) {
2025                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2026                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2027                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2028                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2029         }
2030         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2031         adapter->max_rds_rings = MAX_RDS_RINGS;
2032 }
2033
2034 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2035 {
2036         int err = -EIO;
2037
2038         qlcnic_83xx_get_minidump_template(adapter);
2039         if (qlcnic_83xx_get_port_info(adapter))
2040                 return err;
2041
2042         qlcnic_83xx_config_buff_descriptors(adapter);
2043         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2044         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2045
2046         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2047                  adapter->ahw->fw_hal_version);
2048
2049         return 0;
2050 }
2051
2052 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2053 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2054 {
2055         struct qlcnic_cmd_args cmd;
2056         u32 presence_mask, audit_mask;
2057         int status;
2058
2059         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2060         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2061
2062         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2063                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2064                 cmd.req.arg[1] = BIT_31;
2065                 status = qlcnic_issue_cmd(adapter, &cmd);
2066                 if (status)
2067                         dev_err(&adapter->pdev->dev,
2068                                 "Failed to clean up the function resources\n");
2069                 qlcnic_free_mbx_args(&cmd);
2070         }
2071 }
2072
2073 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2074 {
2075         struct qlcnic_hardware_context *ahw = adapter->ahw;
2076
2077         if (qlcnic_sriov_vf_check(adapter))
2078                 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2079
2080         if (qlcnic_83xx_check_hw_status(adapter))
2081                 return -EIO;
2082
2083         /* Initilaize 83xx mailbox spinlock */
2084         spin_lock_init(&ahw->mbx_lock);
2085
2086         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2087         qlcnic_83xx_clear_function_resources(adapter);
2088
2089         /* register for NIC IDC AEN Events */
2090         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2091
2092         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2093                 qlcnic_83xx_read_flash_mfg_id(adapter);
2094
2095         if (qlcnic_83xx_idc_init(adapter))
2096                 return -EIO;
2097
2098         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2099         if (qlcnic_83xx_configure_opmode(adapter))
2100                 return -EIO;
2101
2102         /* Perform operating mode specific initialization */
2103         if (adapter->nic_ops->init_driver(adapter))
2104                 return -EIO;
2105
2106         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2107
2108         /* Periodically monitor device status */
2109         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2110
2111         return adapter->ahw->idc.err_code;
2112 }