drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402         qlcnic_83xx_detach_mailbox_work(adapter);
 403
 404         /* Disable mailbox interrupt */
 405         qlcnic_83xx_disable_mbx_intr(adapter);
 406         qlcnic_down(adapter, netdev);
 407         for (i = 0; i < adapter->ahw->num_msix; i++) {
 408                 adapter->ahw->intr_tbl[i].id = i;
 409                 adapter->ahw->intr_tbl[i].enabled = 0;
 410                 adapter->ahw->intr_tbl[i].src = 0;
 411         }
 412
 413         if (qlcnic_sriov_pf_check(adapter))
 414                 qlcnic_sriov_pf_reset(adapter);
 415 }
 416
 417 /**
 418  * qlcnic_83xx_idc_attach_driver
 419  *
 420  * @adapter: adapter structure
 421  *
 422  * Re-attach and re-enable net interface
 423  * Returns: None
 424  *
 425  **/
 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 427 {
 428         struct net_device *netdev = adapter->netdev;
 429
 430         if (netif_running(netdev)) {
 431                 if (qlcnic_up(adapter, netdev))
 432                         goto done;
 433                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 434         }
 435 done:
 436         netif_device_attach(netdev);
 437 }
 438
 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 440                                               int lock)
 441 {
 442         if (lock) {
 443                 if (qlcnic_83xx_lock_driver(adapter))
 444                         return -EBUSY;
 445         }
 446
 447         qlcnic_83xx_idc_clear_registers(adapter, 0);
 448         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 449         if (lock)
 450                 qlcnic_83xx_unlock_driver(adapter);
 451
 452         qlcnic_83xx_idc_log_state_history(adapter);
 453         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 454
 455         return 0;
 456 }
 457
 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 459                                             int lock)
 460 {
 461         if (lock) {
 462                 if (qlcnic_83xx_lock_driver(adapter))
 463                         return -EBUSY;
 464         }
 465
 466         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 467
 468         if (lock)
 469                 qlcnic_83xx_unlock_driver(adapter);
 470
 471         return 0;
 472 }
 473
 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 475                                               int lock)
 476 {
 477         if (lock) {
 478                 if (qlcnic_83xx_lock_driver(adapter))
 479                         return -EBUSY;
 480         }
 481
 482         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 483                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 484
 485         if (lock)
 486                 qlcnic_83xx_unlock_driver(adapter);
 487
 488         return 0;
 489 }
 490
 491 static int
 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 493 {
 494         if (lock) {
 495                 if (qlcnic_83xx_lock_driver(adapter))
 496                         return -EBUSY;
 497         }
 498
 499         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 500                QLC_83XX_IDC_DEV_NEED_RESET);
 501
 502         if (lock)
 503                 qlcnic_83xx_unlock_driver(adapter);
 504
 505         return 0;
 506 }
 507
 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 509                                              int lock)
 510 {
 511         if (lock) {
 512                 if (qlcnic_83xx_lock_driver(adapter))
 513                         return -EBUSY;
 514         }
 515
 516         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 517         if (lock)
 518                 qlcnic_83xx_unlock_driver(adapter);
 519
 520         return 0;
 521 }
 522
 523 /**
 524  * qlcnic_83xx_idc_find_reset_owner_id
 525  *
 526  * @adapter: adapter structure
 527  *
 528  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 529  * Within the same class, function with lowest PCI ID assumes ownership
 530  *
 531  * Returns: reset owner id or failure indication (-EIO)
 532  *
 533  **/
 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 535 {
 536         u32 reg, reg1, reg2, i, j, owner, class;
 537
 538         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 539         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 540         owner = QLCNIC_TYPE_NIC;
 541         i = 0;
 542         j = 0;
 543         reg = reg1;
 544
 545         do {
 546                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 547                 if (class == owner)
 548                         break;
 549                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 550                         reg = reg2;
 551                         j = 0;
 552                 } else {
 553                         j++;
 554                 }
 555
 556                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 557                         if (owner == QLCNIC_TYPE_NIC)
 558                                 owner = QLCNIC_TYPE_ISCSI;
 559                         else if (owner == QLCNIC_TYPE_ISCSI)
 560                                 owner = QLCNIC_TYPE_FCOE;
 561                         else if (owner == QLCNIC_TYPE_FCOE)
 562                                 return -EIO;
 563                         reg = reg1;
 564                         j = 0;
 565                         i = 0;
 566                 }
 567         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 568
 569         return i;
 570 }
 571
 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 573 {
 574         int ret = 0;
 575
 576         ret = qlcnic_83xx_restart_hw(adapter);
 577
 578         if (ret) {
 579                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 580         } else {
 581                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 582                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 583         }
 584
 585         return ret;
 586 }
 587
 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 589 {
 590         u32 status;
 591
 592         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 593
 594         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 595                 dev_err(&adapter->pdev->dev,
 596                         "peg halt status1=0x%x\n", status);
 597                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 598                         dev_err(&adapter->pdev->dev,
 599                                 "On board active cooling fan failed. "
 600                                 "Device has been halted.\n");
 601                         dev_err(&adapter->pdev->dev,
 602                                 "Replace the adapter.\n");
 603                         return -EIO;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 611 {
 612         int err;
 613
 614         qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
 615         qlcnic_83xx_enable_mbx_interrupt(adapter);
 616
 617         /* register for NIC IDC AEN Events */
 618         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 619
 620         err = qlcnic_sriov_pf_reinit(adapter);
 621         if (err)
 622                 return err;
 623
 624         qlcnic_83xx_enable_mbx_interrupt(adapter);
 625
 626         if (qlcnic_83xx_configure_opmode(adapter)) {
 627                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 628                 return -EIO;
 629         }
 630
 631         if (adapter->nic_ops->init_driver(adapter)) {
 632                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 633                 return -EIO;
 634         }
 635
 636         if (adapter->portnum == 0)
 637                 qlcnic_set_drv_version(adapter);
 638
 639         qlcnic_dcb_get_info(adapter);
 640         qlcnic_83xx_idc_attach_driver(adapter);
 641
 642         return 0;
 643 }
 644
 645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 646 {
 647         struct qlcnic_hardware_context *ahw = adapter->ahw;
 648
 649         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 650         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 651         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 652
 653         ahw->idc.quiesce_req = 0;
 654         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 655         ahw->idc.err_code = 0;
 656         ahw->idc.collect_dump = 0;
 657         ahw->reset_context = 0;
 658         adapter->tx_timeo_cnt = 0;
 659         ahw->idc.delay_reset = 0;
 660
 661         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 662 }
 663
 664 /**
 665  * qlcnic_83xx_idc_ready_state_entry
 666  *
 667  * @adapter: adapter structure
 668  *
 669  * Perform ready state initialization, this routine will get invoked only
 670  * once from READY state.
 671  *
 672  * Returns: Error code or Success(0)
 673  *
 674  **/
 675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 676 {
 677         struct qlcnic_hardware_context *ahw = adapter->ahw;
 678
 679         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 680                 qlcnic_83xx_idc_update_idc_params(adapter);
 681                 /* Re-attach the device if required */
 682                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 683                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 684                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 685                                 return -EIO;
 686                 }
 687         }
 688
 689         return 0;
 690 }
 691
 692 /**
 693  * qlcnic_83xx_idc_vnic_pf_entry
 694  *
 695  * @adapter: adapter structure
 696  *
 697  * Ensure vNIC mode privileged function starts only after vNIC mode is
 698  * enabled by management function.
 699  * If vNIC mode is ready, start initialization.
 700  *
 701  * Returns: -EIO or 0
 702  *
 703  **/
 704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 705 {
 706         u32 state;
 707         struct qlcnic_hardware_context *ahw = adapter->ahw;
 708
 709         /* Privileged function waits till mgmt function enables VNIC mode */
 710         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 711         if (state != QLCNIC_DEV_NPAR_OPER) {
 712                 if (!ahw->idc.vnic_wait_limit--) {
 713                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 714                         return -EIO;
 715                 }
 716                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 717                 return -EIO;
 718
 719         } else {
 720                 /* Perform one time initialization from ready state */
 721                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 722                         qlcnic_83xx_idc_update_idc_params(adapter);
 723
 724                         /* If the previous state is UNKNOWN, device will be
 725                            already attached properly by Init routine*/
 726                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 727                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 728                                         return -EIO;
 729                         }
 730                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 731                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 739 {
 740         adapter->ahw->idc.err_code = -EIO;
 741         dev_err(&adapter->pdev->dev,
 742                 "%s: Device in unknown state\n", __func__);
 743         return 0;
 744 }
 745
 746 /**
 747  * qlcnic_83xx_idc_cold_state
 748  *
 749  * @adapter: adapter structure
 750  *
 751  * If HW is up and running device will enter READY state.
 752  * If firmware image from host needs to be loaded, device is
 753  * forced to start with the file firmware image.
 754  *
 755  * Returns: Error code or Success(0)
 756  *
 757  **/
 758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 759 {
 760         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 761         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 762
 763         if (qlcnic_load_fw_file) {
 764                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 765         } else {
 766                 if (qlcnic_83xx_check_hw_status(adapter)) {
 767                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 768                         return -EIO;
 769                 } else {
 770                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 771                 }
 772         }
 773         return 0;
 774 }
 775
 776 /**
 777  * qlcnic_83xx_idc_init_state
 778  *
 779  * @adapter: adapter structure
 780  *
 781  * Reset owner will restart the device from this state.
 782  * Device will enter failed state if it remains
 783  * in this state for more than DEV_INIT time limit.
 784  *
 785  * Returns: Error code or Success(0)
 786  *
 787  **/
 788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 789 {
 790         int timeout, ret = 0;
 791         u32 owner;
 792
 793         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 794         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 795                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 796                 if (adapter->ahw->pci_func == owner)
 797                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 798         } else {
 799                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 800                 return ret;
 801         }
 802
 803         return ret;
 804 }
 805
 806 /**
 807  * qlcnic_83xx_idc_ready_state
 808  *
 809  * @adapter: adapter structure
 810  *
 811  * Perform IDC protocol specicifed actions after monitoring device state and
 812  * events.
 813  *
 814  * Returns: Error code or Success(0)
 815  *
 816  **/
 817 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 818 {
 819         struct qlcnic_hardware_context *ahw = adapter->ahw;
 820         struct qlcnic_mailbox *mbx = ahw->mailbox;
 821         int ret = 0;
 822         u32 val;
 823
 824         /* Perform NIC configuration based ready state entry actions */
 825         if (ahw->idc.state_entry(adapter))
 826                 return -EIO;
 827
 828         if (qlcnic_check_temp(adapter)) {
 829                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 830                         qlcnic_83xx_idc_check_fan_failure(adapter);
 831                         dev_err(&adapter->pdev->dev,
 832                                 "Error: device temperature %d above limits\n",
 833                                 adapter->ahw->temp);
 834                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 835                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 836                         qlcnic_83xx_idc_detach_driver(adapter);
 837                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 838                         return -EIO;
 839                 }
 840         }
 841
 842         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 843         ret = qlcnic_83xx_check_heartbeat(adapter);
 844         if (ret) {
 845                 adapter->flags |= QLCNIC_FW_HANG;
 846                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 847                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 848                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 849                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 850                 }
 851                 return -EIO;
 852         }
 853
 854         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 855                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 856
 857                 /* Move to need reset state and prepare for reset */
 858                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 859                 return ret;
 860         }
 861
 862         /* Check for soft reset request */
 863         if (ahw->reset_context &&
 864             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 865                 adapter->ahw->reset_context = 0;
 866                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 867                 return ret;
 868         }
 869
 870         /* Move to need quiesce state if requested */
 871         if (adapter->ahw->idc.quiesce_req) {
 872                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 873                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 874                 return ret;
 875         }
 876
 877         return ret;
 878 }
 879
 880 /**
 881  * qlcnic_83xx_idc_need_reset_state
 882  *
 883  * @adapter: adapter structure
 884  *
 885  * Device will remain in this state until:
 886  *      Reset request ACK's are recieved from all the functions
 887  *      Wait time exceeds max time limit
 888  *
 889  * Returns: Error code or Success(0)
 890  *
 891  **/
 892 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 893 {
 894         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 895         int ret = 0;
 896
 897         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 898                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 899                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 900                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 901                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 902                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 903
 904                 if (qlcnic_check_diag_status(adapter)) {
 905                         dev_info(&adapter->pdev->dev,
 906                                  "%s: Wait for diag completion\n", __func__);
 907                         adapter->ahw->idc.delay_reset = 1;
 908                         return 0;
 909                 } else {
 910                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 911                         qlcnic_83xx_idc_detach_driver(adapter);
 912                 }
 913         }
 914
 915         if (qlcnic_check_diag_status(adapter)) {
 916                 dev_info(&adapter->pdev->dev,
 917                          "%s: Wait for diag completion\n", __func__);
 918                 return  -1;
 919         } else {
 920                 if (adapter->ahw->idc.delay_reset) {
 921                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 922                         qlcnic_83xx_idc_detach_driver(adapter);
 923                         adapter->ahw->idc.delay_reset = 0;
 924                 }
 925
 926                 /* Check for ACK from other functions */
 927                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 928                 if (ret) {
 929                         dev_info(&adapter->pdev->dev,
 930                                  "%s: Waiting for reset ACK\n", __func__);
 931                         return -1;
 932                 }
 933         }
 934
 935         /* Transit to INIT state and restart the HW */
 936         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 937
 938         return ret;
 939 }
 940
 941 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 942 {
 943         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 944         return 0;
 945 }
 946
 947 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 948 {
 949         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 950         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 951         adapter->ahw->idc.err_code = -EIO;
 952
 953         return 0;
 954 }
 955
 956 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 957 {
 958         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 959         return 0;
 960 }
 961
 962 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 963                                                 u32 state)
 964 {
 965         u32 cur, prev, next;
 966
 967         cur = adapter->ahw->idc.curr_state;
 968         prev = adapter->ahw->idc.prev_state;
 969         next = state;
 970
 971         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 972             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 973                 dev_err(&adapter->pdev->dev,
 974                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 975                         __func__, cur, prev, state);
 976                 return 1;
 977         }
 978
 979         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 980             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 981                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 982                     (next != QLC_83XX_IDC_DEV_READY)) {
 983                         dev_err(&adapter->pdev->dev,
 984                                 "%s: failed, cur %d prev %d next %d\n",
 985                                 __func__, cur, prev, next);
 986                         return 1;
 987                 }
 988         }
 989
 990         if (next == QLC_83XX_IDC_DEV_INIT) {
 991                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 992                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 993                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 994                         dev_err(&adapter->pdev->dev,
 995                                 "%s: failed, cur %d prev %d next %d\n",
 996                                 __func__, cur, prev, next);
 997                         return 1;
 998                 }
 999         }
1000
1001         return 0;
1002 }
1003
1004 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1005 {
1006         if (adapter->fhash.fnum)
1007                 qlcnic_prune_lb_filters(adapter);
1008 }
1009
1010 /**
1011  * qlcnic_83xx_idc_poll_dev_state
1012  *
1013  * @work: kernel work queue structure used to schedule the function
1014  *
1015  * Poll device state periodically and perform state specific
1016  * actions defined by Inter Driver Communication (IDC) protocol.
1017  *
1018  * Returns: None
1019  *
1020  **/
1021 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1022 {
1023         struct qlcnic_adapter *adapter;
1024         u32 state;
1025
1026         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1027         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1028
1029         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1030                 qlcnic_83xx_idc_log_state_history(adapter);
1031                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1032         } else {
1033                 adapter->ahw->idc.curr_state = state;
1034         }
1035
1036         switch (adapter->ahw->idc.curr_state) {
1037         case QLC_83XX_IDC_DEV_READY:
1038                 qlcnic_83xx_idc_ready_state(adapter);
1039                 break;
1040         case QLC_83XX_IDC_DEV_NEED_RESET:
1041                 qlcnic_83xx_idc_need_reset_state(adapter);
1042                 break;
1043         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1044                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1045                 break;
1046         case QLC_83XX_IDC_DEV_FAILED:
1047                 qlcnic_83xx_idc_failed_state(adapter);
1048                 return;
1049         case QLC_83XX_IDC_DEV_INIT:
1050                 qlcnic_83xx_idc_init_state(adapter);
1051                 break;
1052         case QLC_83XX_IDC_DEV_QUISCENT:
1053                 qlcnic_83xx_idc_quiesce_state(adapter);
1054                 break;
1055         default:
1056                 qlcnic_83xx_idc_unknown_state(adapter);
1057                 return;
1058         }
1059         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1060         qlcnic_83xx_periodic_tasks(adapter);
1061
1062         /* Re-schedule the function */
1063         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1064                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1065                                      adapter->ahw->idc.delay);
1066 }
1067
1068 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1069 {
1070         u32 idc_params, val;
1071
1072         if (qlcnic_83xx_lockless_flash_read32(adapter,
1073                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1074                                               (u8 *)&idc_params, 1)) {
1075                 dev_info(&adapter->pdev->dev,
1076                          "%s:failed to get IDC params from flash\n", __func__);
1077                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1078                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1079         } else {
1080                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1081                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1082         }
1083
1084         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1085         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1086         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1087         adapter->ahw->idc.err_code = 0;
1088         adapter->ahw->idc.collect_dump = 0;
1089         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1090
1091         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1092         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1093
1094         /* Check if reset recovery is disabled */
1095         if (!qlcnic_auto_fw_reset) {
1096                 /* Propagate do not reset request to other functions */
1097                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1098                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1099                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1100         }
1101 }
1102
1103 static int
1104 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1105 {
1106         u32 state, val;
1107
1108         if (qlcnic_83xx_lock_driver(adapter))
1109                 return -EIO;
1110
1111         /* Clear driver lock register */
1112         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1113         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1114                 qlcnic_83xx_unlock_driver(adapter);
1115                 return -EIO;
1116         }
1117
1118         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1119         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1120                 qlcnic_83xx_unlock_driver(adapter);
1121                 return -EIO;
1122         }
1123
1124         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1125                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1126                        QLC_83XX_IDC_DEV_COLD);
1127                 state = QLC_83XX_IDC_DEV_COLD;
1128         }
1129
1130         adapter->ahw->idc.curr_state = state;
1131         /* First to load function should cold boot the device */
1132         if (state == QLC_83XX_IDC_DEV_COLD)
1133                 qlcnic_83xx_idc_cold_state_handler(adapter);
1134
1135         /* Check if reset recovery is enabled */
1136         if (qlcnic_auto_fw_reset) {
1137                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1138                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1139                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1140         }
1141
1142         qlcnic_83xx_unlock_driver(adapter);
1143
1144         return 0;
1145 }
1146
1147 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1148 {
1149         int ret = -EIO;
1150
1151         qlcnic_83xx_setup_idc_parameters(adapter);
1152
1153         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1154                 return ret;
1155
1156         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1157                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1158                         return -EIO;
1159         } else {
1160                 if (qlcnic_83xx_idc_check_major_version(adapter))
1161                         return -EIO;
1162         }
1163
1164         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1165
1166         return 0;
1167 }
1168
1169 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1170 {
1171         int id;
1172         u32 val;
1173
1174         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1175                 usleep_range(10000, 11000);
1176
1177         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1178         id = id & 0xFF;
1179
1180         if (id == adapter->portnum) {
1181                 dev_err(&adapter->pdev->dev,
1182                         "%s: wait for lock recovery.. %d\n", __func__, id);
1183                 msleep(20);
1184                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1185                 id = id & 0xFF;
1186         }
1187
1188         /* Clear driver presence bit */
1189         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1190         val = val & ~(1 << adapter->portnum);
1191         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1192         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1193         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1194
1195         cancel_delayed_work_sync(&adapter->fw_work);
1196 }
1197
1198 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1199 {
1200         u32 val;
1201
1202         if (qlcnic_sriov_vf_check(adapter))
1203                 return;
1204
1205         if (qlcnic_83xx_lock_driver(adapter)) {
1206                 dev_err(&adapter->pdev->dev,
1207                         "%s:failed, please retry\n", __func__);
1208                 return;
1209         }
1210
1211         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1212         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1213             !qlcnic_auto_fw_reset) {
1214                 dev_err(&adapter->pdev->dev,
1215                         "%s:failed, device in non reset mode\n", __func__);
1216                 qlcnic_83xx_unlock_driver(adapter);
1217                 return;
1218         }
1219
1220         if (key == QLCNIC_FORCE_FW_RESET) {
1221                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1222                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1223                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1224         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1225                 adapter->ahw->idc.collect_dump = 1;
1226         }
1227
1228         qlcnic_83xx_unlock_driver(adapter);
1229         return;
1230 }
1231
1232 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1233 {
1234         u8 *p_cache;
1235         u32 src, size;
1236         u64 dest;
1237         int ret = -EIO;
1238
1239         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1240         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1241         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1242
1243         /* alignment check */
1244         if (size & 0xF)
1245                 size = (size + 16) & ~0xF;
1246
1247         p_cache = kzalloc(size, GFP_KERNEL);
1248         if (p_cache == NULL)
1249                 return -ENOMEM;
1250
1251         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1252                                                 size / sizeof(u32));
1253         if (ret) {
1254                 kfree(p_cache);
1255                 return ret;
1256         }
1257         /* 16 byte write to MS memory */
1258         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1259                                           size / 16);
1260         if (ret) {
1261                 kfree(p_cache);
1262                 return ret;
1263         }
1264         kfree(p_cache);
1265
1266         return ret;
1267 }
1268
1269 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1270 {
1271         u32 dest, *p_cache;
1272         u64 addr;
1273         u8 data[16];
1274         size_t size;
1275         int i, ret = -EIO;
1276
1277         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1278         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1279         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1280         addr = (u64)dest;
1281
1282         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1283                                           (u32 *)p_cache, size / 16);
1284         if (ret) {
1285                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1286                 release_firmware(adapter->ahw->fw_info.fw);
1287                 adapter->ahw->fw_info.fw = NULL;
1288                 return -EIO;
1289         }
1290
1291         /* alignment check */
1292         if (adapter->ahw->fw_info.fw->size & 0xF) {
1293                 addr = dest + size;
1294                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1295                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1296                 for (; i < 16; i++)
1297                         data[i] = 0;
1298                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1299                                                   (u32 *)data, 1);
1300                 if (ret) {
1301                         dev_err(&adapter->pdev->dev,
1302                                 "MS memory write failed\n");
1303                         release_firmware(adapter->ahw->fw_info.fw);
1304                         adapter->ahw->fw_info.fw = NULL;
1305                         return -EIO;
1306                 }
1307         }
1308         release_firmware(adapter->ahw->fw_info.fw);
1309         adapter->ahw->fw_info.fw = NULL;
1310
1311         return 0;
1312 }
1313
1314 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1315 {
1316         int i, j;
1317         u32 val = 0, val1 = 0, reg = 0;
1318         int err = 0;
1319
1320         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1321         if (err == -EIO)
1322                 return;
1323         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1324
1325         for (j = 0; j < 2; j++) {
1326                 if (j == 0) {
1327                         dev_info(&adapter->pdev->dev,
1328                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1329                         reg = QLC_83XX_PORT0_THRESHOLD;
1330                 } else if (j == 1) {
1331                         dev_info(&adapter->pdev->dev,
1332                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1333                         reg = QLC_83XX_PORT1_THRESHOLD;
1334                 }
1335                 for (i = 0; i < 8; i++) {
1336                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1337                         if (err == -EIO)
1338                                 return;
1339                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1340                 }
1341                 dev_info(&adapter->pdev->dev, "\n");
1342         }
1343
1344         for (j = 0; j < 2; j++) {
1345                 if (j == 0) {
1346                         dev_info(&adapter->pdev->dev,
1347                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1348                         reg = QLC_83XX_PORT0_TC_MC_REG;
1349                 } else if (j == 1) {
1350                         dev_info(&adapter->pdev->dev,
1351                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1352                         reg = QLC_83XX_PORT1_TC_MC_REG;
1353                 }
1354                 for (i = 0; i < 4; i++) {
1355                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1356                         if (err == -EIO)
1357                                 return;
1358                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1359                 }
1360                 dev_info(&adapter->pdev->dev, "\n");
1361         }
1362
1363         for (j = 0; j < 2; j++) {
1364                 if (j == 0) {
1365                         dev_info(&adapter->pdev->dev,
1366                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1367                         reg = QLC_83XX_PORT0_TC_STATS;
1368                 } else if (j == 1) {
1369                         dev_info(&adapter->pdev->dev,
1370                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1371                         reg = QLC_83XX_PORT1_TC_STATS;
1372                 }
1373                 for (i = 7; i >= 0; i--) {
1374                         val = QLCRD32(adapter, reg, &err);
1375                         if (err == -EIO)
1376                                 return;
1377                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1378                         QLCWR32(adapter, reg, (val | (i << 29)));
1379                         val = QLCRD32(adapter, reg, &err);
1380                         if (err == -EIO)
1381                                 return;
1382                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1383                 }
1384                 dev_info(&adapter->pdev->dev, "\n");
1385         }
1386
1387         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1388         if (err == -EIO)
1389                 return;
1390         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1391         if (err == -EIO)
1392                 return;
1393         dev_info(&adapter->pdev->dev,
1394                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1395                  val, val1);
1396 }
1397
1398
1399 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1400 {
1401         u32 reg = 0, i, j;
1402
1403         if (qlcnic_83xx_lock_driver(adapter)) {
1404                 dev_err(&adapter->pdev->dev,
1405                         "%s:failed to acquire driver lock\n", __func__);
1406                 return;
1407         }
1408
1409         qlcnic_83xx_dump_pause_control_regs(adapter);
1410         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1411
1412         for (j = 0; j < 2; j++) {
1413                 if (j == 0)
1414                         reg = QLC_83XX_PORT0_THRESHOLD;
1415                 else if (j == 1)
1416                         reg = QLC_83XX_PORT1_THRESHOLD;
1417
1418                 for (i = 0; i < 8; i++)
1419                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1420         }
1421
1422         for (j = 0; j < 2; j++) {
1423                 if (j == 0)
1424                         reg = QLC_83XX_PORT0_TC_MC_REG;
1425                 else if (j == 1)
1426                         reg = QLC_83XX_PORT1_TC_MC_REG;
1427
1428                 for (i = 0; i < 4; i++)
1429                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1430         }
1431
1432         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1433         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1434         dev_info(&adapter->pdev->dev,
1435                  "Disabled pause frames successfully on all ports\n");
1436         qlcnic_83xx_unlock_driver(adapter);
1437 }
1438
1439 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1440 {
1441         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1442         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1443         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1444         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1445         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1446         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1447         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1448         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1449         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1450 }
1451
1452 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1453 {
1454         u32 heartbeat, peg_status;
1455         int retries, ret = -EIO, err = 0;
1456
1457         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1458         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1459                                                QLCNIC_PEG_ALIVE_COUNTER);
1460
1461         do {
1462                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1463                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1464                                                 QLCNIC_PEG_ALIVE_COUNTER);
1465                 if (heartbeat != p_dev->heartbeat) {
1466                         ret = QLCNIC_RCODE_SUCCESS;
1467                         break;
1468                 }
1469         } while (--retries);
1470
1471         if (ret) {
1472                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1473                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1474                 qlcnic_83xx_disable_pause_frames(p_dev);
1475                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1476                                                  QLCNIC_PEG_HALT_STATUS1);
1477                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1478                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1479                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1480                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1481                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1482                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1483                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1484                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1485                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1486                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1487                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1488
1489                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1490                         dev_err(&p_dev->pdev->dev,
1491                                 "Device is being reset err code 0x00006700.\n");
1492         }
1493
1494         return ret;
1495 }
1496
1497 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1498 {
1499         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1500         u32 val;
1501
1502         do {
1503                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1504                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1505                         return 0;
1506                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1507         } while (--retries);
1508
1509         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1510         return -EIO;
1511 }
1512
1513 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1514 {
1515         int err;
1516
1517         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1518         if (err)
1519                 return err;
1520
1521         err = qlcnic_83xx_check_heartbeat(p_dev);
1522         if (err)
1523                 return err;
1524
1525         return err;
1526 }
1527
1528 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1529                                 int duration, u32 mask, u32 status)
1530 {
1531         int timeout_error, err = 0;
1532         u32 value;
1533         u8 retries;
1534
1535         value = QLCRD32(p_dev, addr, &err);
1536         if (err == -EIO)
1537                 return err;
1538         retries = duration / 10;
1539
1540         do {
1541                 if ((value & mask) != status) {
1542                         timeout_error = 1;
1543                         msleep(duration / 10);
1544                         value = QLCRD32(p_dev, addr, &err);
1545                         if (err == -EIO)
1546                                 return err;
1547                 } else {
1548                         timeout_error = 0;
1549                         break;
1550                 }
1551         } while (retries--);
1552
1553         if (timeout_error) {
1554                 p_dev->ahw->reset.seq_error++;
1555                 dev_err(&p_dev->pdev->dev,
1556                         "%s: Timeout Err, entry_num = %d\n",
1557                         __func__, p_dev->ahw->reset.seq_index);
1558                 dev_err(&p_dev->pdev->dev,
1559                         "0x%08x 0x%08x 0x%08x\n",
1560                         value, mask, status);
1561         }
1562
1563         return timeout_error;
1564 }
1565
1566 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1567 {
1568         u32 sum = 0;
1569         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1570         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1571
1572         while (count-- > 0)
1573                 sum += *buff++;
1574
1575         while (sum >> 16)
1576                 sum = (sum & 0xFFFF) + (sum >> 16);
1577
1578         if (~sum) {
1579                 return 0;
1580         } else {
1581                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1582                 return -1;
1583         }
1584 }
1585
1586 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1587 {
1588         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1589         u32 addr, count, prev_ver, curr_ver;
1590         u8 *p_buff;
1591
1592         if (ahw->reset.buff != NULL) {
1593                 prev_ver = p_dev->fw_version;
1594                 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1595                 if (curr_ver > prev_ver)
1596                         kfree(ahw->reset.buff);
1597                 else
1598                         return 0;
1599         }
1600
1601         ahw->reset.seq_error = 0;
1602         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1603         if (p_dev->ahw->reset.buff == NULL)
1604                 return -ENOMEM;
1605
1606         p_buff = p_dev->ahw->reset.buff;
1607         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1608         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1609
1610         /* Copy template header from flash */
1611         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1612                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1613                 return -EIO;
1614         }
1615         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1616         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1617         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1618         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1619
1620         /* Copy rest of the template */
1621         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1622                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1623                 return -EIO;
1624         }
1625
1626         if (qlcnic_83xx_reset_template_checksum(p_dev))
1627                 return -EIO;
1628         /* Get Stop, Start and Init command offsets */
1629         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1630         ahw->reset.start_offset = ahw->reset.buff +
1631                                   ahw->reset.hdr->start_offset;
1632         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1633         return 0;
1634 }
1635
1636 /* Read Write HW register command */
1637 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1638                                            u32 raddr, u32 waddr)
1639 {
1640         int err = 0;
1641         u32 value;
1642
1643         value = QLCRD32(p_dev, raddr, &err);
1644         if (err == -EIO)
1645                 return;
1646         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1647 }
1648
1649 /* Read Modify Write HW register command */
1650 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1651                                     u32 raddr, u32 waddr,
1652                                     struct qlc_83xx_rmw *p_rmw_hdr)
1653 {
1654         int err = 0;
1655         u32 value;
1656
1657         if (p_rmw_hdr->index_a) {
1658                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1659         } else {
1660                 value = QLCRD32(p_dev, raddr, &err);
1661                 if (err == -EIO)
1662                         return;
1663         }
1664
1665         value &= p_rmw_hdr->mask;
1666         value <<= p_rmw_hdr->shl;
1667         value >>= p_rmw_hdr->shr;
1668         value |= p_rmw_hdr->or_value;
1669         value ^= p_rmw_hdr->xor_value;
1670         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1671 }
1672
1673 /* Write HW register command */
1674 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1675                                    struct qlc_83xx_entry_hdr *p_hdr)
1676 {
1677         int i;
1678         struct qlc_83xx_entry *entry;
1679
1680         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1681                                           sizeof(struct qlc_83xx_entry_hdr));
1682
1683         for (i = 0; i < p_hdr->count; i++, entry++) {
1684                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1685                                              entry->arg2);
1686                 if (p_hdr->delay)
1687                         udelay((u32)(p_hdr->delay));
1688         }
1689 }
1690
1691 /* Read and Write instruction */
1692 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1693                                         struct qlc_83xx_entry_hdr *p_hdr)
1694 {
1695         int i;
1696         struct qlc_83xx_entry *entry;
1697
1698         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1699                                           sizeof(struct qlc_83xx_entry_hdr));
1700
1701         for (i = 0; i < p_hdr->count; i++, entry++) {
1702                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1703                                                entry->arg2);
1704                 if (p_hdr->delay)
1705                         udelay((u32)(p_hdr->delay));
1706         }
1707 }
1708
1709 /* Poll HW register command */
1710 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1711                                   struct qlc_83xx_entry_hdr *p_hdr)
1712 {
1713         long delay;
1714         struct qlc_83xx_entry *entry;
1715         struct qlc_83xx_poll *poll;
1716         int i, err = 0;
1717         unsigned long arg1, arg2;
1718
1719         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1720                                         sizeof(struct qlc_83xx_entry_hdr));
1721
1722         entry = (struct qlc_83xx_entry *)((char *)poll +
1723                                           sizeof(struct qlc_83xx_poll));
1724         delay = (long)p_hdr->delay;
1725
1726         if (!delay) {
1727                 for (i = 0; i < p_hdr->count; i++, entry++)
1728                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1729                                              delay, poll->mask,
1730                                              poll->status);
1731         } else {
1732                 for (i = 0; i < p_hdr->count; i++, entry++) {
1733                         arg1 = entry->arg1;
1734                         arg2 = entry->arg2;
1735                         if (delay) {
1736                                 if (qlcnic_83xx_poll_reg(p_dev,
1737                                                          arg1, delay,
1738                                                          poll->mask,
1739                                                          poll->status)){
1740                                         QLCRD32(p_dev, arg1, &err);
1741                                         if (err == -EIO)
1742                                                 return;
1743                                         QLCRD32(p_dev, arg2, &err);
1744                                         if (err == -EIO)
1745                                                 return;
1746                                 }
1747                         }
1748                 }
1749         }
1750 }
1751
1752 /* Poll and write HW register command */
1753 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1754                                         struct qlc_83xx_entry_hdr *p_hdr)
1755 {
1756         int i;
1757         long delay;
1758         struct qlc_83xx_quad_entry *entry;
1759         struct qlc_83xx_poll *poll;
1760
1761         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1762                                         sizeof(struct qlc_83xx_entry_hdr));
1763         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1764                                                sizeof(struct qlc_83xx_poll));
1765         delay = (long)p_hdr->delay;
1766
1767         for (i = 0; i < p_hdr->count; i++, entry++) {
1768                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1769                                              entry->dr_value);
1770                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1771                                              entry->ar_value);
1772                 if (delay)
1773                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1774                                              poll->mask, poll->status);
1775         }
1776 }
1777
1778 /* Read Modify Write register command */
1779 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1780                                           struct qlc_83xx_entry_hdr *p_hdr)
1781 {
1782         int i;
1783         struct qlc_83xx_entry *entry;
1784         struct qlc_83xx_rmw *rmw_hdr;
1785
1786         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1787                                           sizeof(struct qlc_83xx_entry_hdr));
1788
1789         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1790                                           sizeof(struct qlc_83xx_rmw));
1791
1792         for (i = 0; i < p_hdr->count; i++, entry++) {
1793                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1794                                         entry->arg2, rmw_hdr);
1795                 if (p_hdr->delay)
1796                         udelay((u32)(p_hdr->delay));
1797         }
1798 }
1799
1800 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1801 {
1802         if (p_hdr->delay)
1803                 mdelay((u32)((long)p_hdr->delay));
1804 }
1805
1806 /* Read and poll register command */
1807 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1808                                        struct qlc_83xx_entry_hdr *p_hdr)
1809 {
1810         long delay;
1811         int index, i, j, err;
1812         struct qlc_83xx_quad_entry *entry;
1813         struct qlc_83xx_poll *poll;
1814         unsigned long addr;
1815
1816         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1817                                         sizeof(struct qlc_83xx_entry_hdr));
1818
1819         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1820                                                sizeof(struct qlc_83xx_poll));
1821         delay = (long)p_hdr->delay;
1822
1823         for (i = 0; i < p_hdr->count; i++, entry++) {
1824                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1825                                              entry->ar_value);
1826                 if (delay) {
1827                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1828                                                   poll->mask, poll->status)){
1829                                 index = p_dev->ahw->reset.array_index;
1830                                 addr = entry->dr_addr;
1831                                 j = QLCRD32(p_dev, addr, &err);
1832                                 if (err == -EIO)
1833                                         return;
1834
1835                                 p_dev->ahw->reset.array[index++] = j;
1836
1837                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1838                                         p_dev->ahw->reset.array_index = 1;
1839                         }
1840                 }
1841         }
1842 }
1843
1844 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1845 {
1846         p_dev->ahw->reset.seq_end = 1;
1847 }
1848
1849 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1850 {
1851         p_dev->ahw->reset.template_end = 1;
1852         if (p_dev->ahw->reset.seq_error == 0)
1853                 dev_err(&p_dev->pdev->dev,
1854                         "HW restart process completed successfully.\n");
1855         else
1856                 dev_err(&p_dev->pdev->dev,
1857                         "HW restart completed with timeout errors.\n");
1858 }
1859
1860 /**
1861 * qlcnic_83xx_exec_template_cmd
1862 *
1863 * @p_dev: adapter structure
1864 * @p_buff: Poiter to instruction template
1865 *
1866 * Template provides instructions to stop, restart and initalize firmware.
1867 * These instructions are abstracted as a series of read, write and
1868 * poll operations on hardware registers. Register information and operation
1869 * specifics are not exposed to the driver. Driver reads the template from
1870 * flash and executes the instructions located at pre-defined offsets.
1871 *
1872 * Returns: None
1873 * */
1874 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1875                                           char *p_buff)
1876 {
1877         int index, entries;
1878         struct qlc_83xx_entry_hdr *p_hdr;
1879         char *entry = p_buff;
1880
1881         p_dev->ahw->reset.seq_end = 0;
1882         p_dev->ahw->reset.template_end = 0;
1883         entries = p_dev->ahw->reset.hdr->entries;
1884         index = p_dev->ahw->reset.seq_index;
1885
1886         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1887                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1888
1889                 switch (p_hdr->cmd) {
1890                 case QLC_83XX_OPCODE_NOP:
1891                         break;
1892                 case QLC_83XX_OPCODE_WRITE_LIST:
1893                         qlcnic_83xx_write_list(p_dev, p_hdr);
1894                         break;
1895                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1896                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1897                         break;
1898                 case QLC_83XX_OPCODE_POLL_LIST:
1899                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1900                         break;
1901                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1902                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1903                         break;
1904                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1905                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1906                         break;
1907                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1908                         qlcnic_83xx_pause(p_hdr);
1909                         break;
1910                 case QLC_83XX_OPCODE_SEQ_END:
1911                         qlcnic_83xx_seq_end(p_dev);
1912                         break;
1913                 case QLC_83XX_OPCODE_TMPL_END:
1914                         qlcnic_83xx_template_end(p_dev);
1915                         break;
1916                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1917                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1918                         break;
1919                 default:
1920                         dev_err(&p_dev->pdev->dev,
1921                                 "%s: Unknown opcode 0x%04x in template %d\n",
1922                                 __func__, p_hdr->cmd, index);
1923                         break;
1924                 }
1925                 entry += p_hdr->size;
1926         }
1927         p_dev->ahw->reset.seq_index = index;
1928 }
1929
1930 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1931 {
1932         p_dev->ahw->reset.seq_index = 0;
1933
1934         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1935         if (p_dev->ahw->reset.seq_end != 1)
1936                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1937 }
1938
1939 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1940 {
1941         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1942         if (p_dev->ahw->reset.template_end != 1)
1943                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1944 }
1945
1946 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1947 {
1948         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1949         if (p_dev->ahw->reset.seq_end != 1)
1950                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1951 }
1952
1953 static void qlcnic_83xx_get_fw_file_name(struct qlcnic_adapter *adapter,
1954                                          char *file_name)
1955 {
1956         struct pci_dev *pdev = adapter->pdev;
1957
1958         memset(file_name, 0, QLC_FW_FILE_NAME_LEN);
1959
1960         switch (pdev->device) {
1961         case PCI_DEVICE_ID_QLOGIC_QLE834X:
1962                 strncpy(file_name, QLC_83XX_FW_FILE_NAME,
1963                         QLC_FW_FILE_NAME_LEN);
1964                 break;
1965         case PCI_DEVICE_ID_QLOGIC_QLE844X:
1966                 strncpy(file_name, QLC_84XX_FW_FILE_NAME,
1967                         QLC_FW_FILE_NAME_LEN);
1968                 break;
1969         default:
1970                 dev_err(&pdev->dev, "%s: Invalid device id\n",
1971                         __func__);
1972         }
1973 }
1974
1975 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1976 {
1977         char fw_file_name[QLC_FW_FILE_NAME_LEN];
1978         int err = -EIO;
1979
1980         qlcnic_83xx_get_fw_file_name(adapter, fw_file_name);
1981         if (request_firmware(&adapter->ahw->fw_info.fw, fw_file_name,
1982                              &(adapter->pdev->dev))) {
1983                 dev_err(&adapter->pdev->dev,
1984                         "No file FW image, loading flash FW image.\n");
1985                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1986                                     QLC_83XX_BOOT_FROM_FLASH);
1987         } else {
1988                 if (qlcnic_83xx_copy_fw_file(adapter))
1989                         return err;
1990                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1991                                     QLC_83XX_BOOT_FROM_FILE);
1992         }
1993
1994         return 0;
1995 }
1996
1997 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1998 {
1999         u32 val;
2000         int err = -EIO;
2001
2002         qlcnic_83xx_stop_hw(adapter);
2003
2004         /* Collect FW register dump if required */
2005         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2006         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2007                 qlcnic_dump_fw(adapter);
2008         qlcnic_83xx_init_hw(adapter);
2009
2010         if (qlcnic_83xx_copy_bootloader(adapter))
2011                 return err;
2012         /* Boot either flash image or firmware image from host file system */
2013         if (qlcnic_load_fw_file) {
2014                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2015                         return err;
2016         } else {
2017                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2018                                     QLC_83XX_BOOT_FROM_FLASH);
2019         }
2020
2021         qlcnic_83xx_start_hw(adapter);
2022         if (qlcnic_83xx_check_hw_status(adapter))
2023                 return -EIO;
2024
2025         return 0;
2026 }
2027
2028 /**
2029 * qlcnic_83xx_config_default_opmode
2030 *
2031 * @adapter: adapter structure
2032 *
2033 * Configure default driver operating mode
2034 *
2035 * Returns: Error code or Success(0)
2036 * */
2037 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
2038 {
2039         u32 op_mode;
2040         struct qlcnic_hardware_context *ahw = adapter->ahw;
2041
2042         qlcnic_get_func_no(adapter);
2043         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
2044
2045         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2046                 op_mode = QLC_83XX_DEFAULT_OPMODE;
2047
2048         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
2049                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2050                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2051         } else {
2052                 return -EIO;
2053         }
2054
2055         return 0;
2056 }
2057
2058 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2059 {
2060         int err;
2061         struct qlcnic_info nic_info;
2062         struct qlcnic_hardware_context *ahw = adapter->ahw;
2063
2064         memset(&nic_info, 0, sizeof(struct qlcnic_info));
2065         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2066         if (err)
2067                 return -EIO;
2068
2069         ahw->physical_port = (u8) nic_info.phys_port;
2070         ahw->switch_mode = nic_info.switch_mode;
2071         ahw->max_tx_ques = nic_info.max_tx_ques;
2072         ahw->max_rx_ques = nic_info.max_rx_ques;
2073         ahw->capabilities = nic_info.capabilities;
2074         ahw->max_mac_filters = nic_info.max_mac_filters;
2075         ahw->max_mtu = nic_info.max_mtu;
2076
2077         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2078          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2079          * exclusive. So in case of sriov capable device load driver in
2080          * default mode
2081          */
2082         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2083                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2084                 return ahw->nic_mode;
2085         }
2086
2087         if (ahw->capabilities & BIT_23)
2088                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2089         else
2090                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2091
2092         return ahw->nic_mode;
2093 }
2094
2095 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2096 {
2097         int ret;
2098
2099         ret = qlcnic_83xx_get_nic_configuration(adapter);
2100         if (ret == -EIO)
2101                 return -EIO;
2102
2103         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2104                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2105                         return -EIO;
2106         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2107                 if (qlcnic_83xx_config_default_opmode(adapter))
2108                         return -EIO;
2109         }
2110
2111         return 0;
2112 }
2113
2114 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2115 {
2116         struct qlcnic_hardware_context *ahw = adapter->ahw;
2117
2118         if (ahw->port_type == QLCNIC_XGBE) {
2119                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2120                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2121                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2122                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2123
2124         } else if (ahw->port_type == QLCNIC_GBE) {
2125                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2126                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2127                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2128                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2129         }
2130         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2131         adapter->max_rds_rings = MAX_RDS_RINGS;
2132 }
2133
2134 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2135 {
2136         int err = -EIO;
2137
2138         qlcnic_83xx_get_minidump_template(adapter);
2139         if (qlcnic_83xx_get_port_info(adapter))
2140                 return err;
2141
2142         qlcnic_83xx_config_buff_descriptors(adapter);
2143         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2144         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2145
2146         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2147                  adapter->ahw->fw_hal_version);
2148
2149         return 0;
2150 }
2151
2152 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2153 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2154 {
2155         struct qlcnic_cmd_args cmd;
2156         u32 presence_mask, audit_mask;
2157         int status;
2158
2159         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2160         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2161
2162         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2163                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2164                                                QLCNIC_CMD_STOP_NIC_FUNC);
2165                 if (status)
2166                         return;
2167
2168                 cmd.req.arg[1] = BIT_31;
2169                 status = qlcnic_issue_cmd(adapter, &cmd);
2170                 if (status)
2171                         dev_err(&adapter->pdev->dev,
2172                                 "Failed to clean up the function resources\n");
2173                 qlcnic_free_mbx_args(&cmd);
2174         }
2175 }
2176
2177 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2178 {
2179         struct qlcnic_hardware_context *ahw = adapter->ahw;
2180         int err = 0;
2181
2182         ahw->msix_supported = !!qlcnic_use_msi_x;
2183         err = qlcnic_83xx_init_mailbox_work(adapter);
2184         if (err)
2185                 goto exit;
2186
2187         if (qlcnic_sriov_vf_check(adapter)) {
2188                 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2189                 if (err)
2190                         goto detach_mbx;
2191                 else
2192                         return err;
2193         }
2194
2195         err = qlcnic_83xx_check_hw_status(adapter);
2196         if (err)
2197                 goto detach_mbx;
2198
2199         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2200                 qlcnic_83xx_read_flash_mfg_id(adapter);
2201
2202         err = qlcnic_83xx_idc_init(adapter);
2203         if (err)
2204                 goto detach_mbx;
2205
2206         err = qlcnic_setup_intr(adapter, 0, 0);
2207         if (err) {
2208                 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2209                 goto disable_intr;
2210         }
2211
2212         err = qlcnic_83xx_setup_mbx_intr(adapter);
2213         if (err)
2214                 goto disable_mbx_intr;
2215
2216         qlcnic_83xx_clear_function_resources(adapter);
2217
2218         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2219
2220         /* register for NIC IDC AEN Events */
2221         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2222
2223         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2224         err = qlcnic_83xx_configure_opmode(adapter);
2225         if (err)
2226                 goto disable_mbx_intr;
2227
2228         /* Perform operating mode specific initialization */
2229         err = adapter->nic_ops->init_driver(adapter);
2230         if (err)
2231                 goto disable_mbx_intr;
2232
2233         if (adapter->dcb && qlcnic_dcb_attach(adapter))
2234                 qlcnic_clear_dcb_ops(adapter);
2235
2236         /* Periodically monitor device status */
2237         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2238         return 0;
2239
2240 disable_mbx_intr:
2241         qlcnic_83xx_free_mbx_intr(adapter);
2242
2243 disable_intr:
2244         qlcnic_teardown_intr(adapter);
2245
2246 detach_mbx:
2247         qlcnic_83xx_detach_mailbox_work(adapter);
2248         qlcnic_83xx_free_mailbox(ahw->mailbox);
2249 exit:
2250         return err;
2251 }