2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
44 struct qlc_83xx_reset_hdr {
45 #if defined(__LITTLE_ENDIAN)
54 #elif defined(__BIG_ENDIAN)
66 /* Command entry header. */
67 struct qlc_83xx_entry_hdr {
68 #if defined(__LITTLE_ENDIAN)
73 #elif defined(__BIG_ENDIAN)
81 /* Generic poll command */
82 struct qlc_83xx_poll {
87 /* Read modify write command */
92 #if defined(__LITTLE_ENDIAN)
97 #elif defined(__BIG_ENDIAN)
105 /* Generic command with 2 DWORD */
106 struct qlc_83xx_entry {
111 /* Generic command with 4 DWORD */
112 struct qlc_83xx_quad_entry {
118 static const char *const qlc_83xx_idc_states[] = {
130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
160 if (qlcnic_83xx_lock_driver(adapter))
164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
170 seconds = jiffies / HZ;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
177 qlcnic_83xx_unlock_driver(adapter);
182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
198 if (qlcnic_83xx_lock_driver(adapter))
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
208 qlcnic_83xx_unlock_driver(adapter);
214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
220 if (qlcnic_83xx_lock_driver(adapter))
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
227 val = val | (1 << adapter->portnum);
229 val = val & ~(1 << adapter->portnum);
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
235 qlcnic_83xx_unlock_driver(adapter);
240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
264 if (qlcnic_83xx_lock_driver(adapter))
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
275 qlcnic_83xx_unlock_driver(adapter);
280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
286 if (qlcnic_83xx_lock_driver(adapter))
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
292 val = val | (1 << adapter->portnum);
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
298 qlcnic_83xx_unlock_driver(adapter);
303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
316 * qlcnic_83xx_idc_check_reset_ack_reg
318 * @adapter: adapter structure
320 * Check ACK wait limit and clear the functions which failed to ACK
322 * Return 0 if all functions have acknowledged the reset request.
324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
327 u32 ack, presence, val;
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
347 qlcnic_83xx_unlock_driver(adapter);
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
362 * qlcnic_83xx_idc_tx_soft_reset
364 * @adapter: adapter structure
366 * Handle context deletion and recreation request from transmit routine
368 * Returns -EBUSY or Success (0)
371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
373 struct net_device *netdev = adapter->netdev;
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
389 * qlcnic_83xx_idc_detach_driver
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
399 struct net_device *netdev = adapter->netdev;
401 netif_device_detach(netdev);
402 qlcnic_83xx_detach_mailbox_work(adapter);
404 /* Disable mailbox interrupt */
405 qlcnic_83xx_disable_mbx_intr(adapter);
406 qlcnic_down(adapter, netdev);
407 for (i = 0; i < adapter->ahw->num_msix; i++) {
408 adapter->ahw->intr_tbl[i].id = i;
409 adapter->ahw->intr_tbl[i].enabled = 0;
410 adapter->ahw->intr_tbl[i].src = 0;
413 if (qlcnic_sriov_pf_check(adapter))
414 qlcnic_sriov_pf_reset(adapter);
418 * qlcnic_83xx_idc_attach_driver
420 * @adapter: adapter structure
422 * Re-attach and re-enable net interface
426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
428 struct net_device *netdev = adapter->netdev;
430 if (netif_running(netdev)) {
431 if (qlcnic_up(adapter, netdev))
433 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
436 netif_device_attach(netdev);
439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
443 if (qlcnic_83xx_lock_driver(adapter))
447 qlcnic_83xx_idc_clear_registers(adapter, 0);
448 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
450 qlcnic_83xx_unlock_driver(adapter);
452 qlcnic_83xx_idc_log_state_history(adapter);
453 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
462 if (qlcnic_83xx_lock_driver(adapter))
466 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
469 qlcnic_83xx_unlock_driver(adapter);
474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
478 if (qlcnic_83xx_lock_driver(adapter))
482 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
483 QLC_83XX_IDC_DEV_NEED_QUISCENT);
486 qlcnic_83xx_unlock_driver(adapter);
492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
495 if (qlcnic_83xx_lock_driver(adapter))
499 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
500 QLC_83XX_IDC_DEV_NEED_RESET);
503 qlcnic_83xx_unlock_driver(adapter);
508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
512 if (qlcnic_83xx_lock_driver(adapter))
516 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
518 qlcnic_83xx_unlock_driver(adapter);
524 * qlcnic_83xx_idc_find_reset_owner_id
526 * @adapter: adapter structure
528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
529 * Within the same class, function with lowest PCI ID assumes ownership
531 * Returns: reset owner id or failure indication (-EIO)
534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
536 u32 reg, reg1, reg2, i, j, owner, class;
538 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
539 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
540 owner = QLCNIC_TYPE_NIC;
546 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
549 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
556 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
557 if (owner == QLCNIC_TYPE_NIC)
558 owner = QLCNIC_TYPE_ISCSI;
559 else if (owner == QLCNIC_TYPE_ISCSI)
560 owner = QLCNIC_TYPE_FCOE;
561 else if (owner == QLCNIC_TYPE_FCOE)
567 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
576 ret = qlcnic_83xx_restart_hw(adapter);
579 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
581 qlcnic_83xx_idc_clear_registers(adapter, lock);
582 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
592 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
594 if (status & QLCNIC_RCODE_FATAL_ERROR) {
595 dev_err(&adapter->pdev->dev,
596 "peg halt status1=0x%x\n", status);
597 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
598 dev_err(&adapter->pdev->dev,
599 "On board active cooling fan failed. "
600 "Device has been halted.\n");
601 dev_err(&adapter->pdev->dev,
602 "Replace the adapter.\n");
610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
614 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
615 qlcnic_83xx_enable_mbx_interrupt(adapter);
617 /* register for NIC IDC AEN Events */
618 qlcnic_83xx_register_nic_idc_func(adapter, 1);
620 err = qlcnic_sriov_pf_reinit(adapter);
624 qlcnic_83xx_enable_mbx_interrupt(adapter);
626 if (qlcnic_83xx_configure_opmode(adapter)) {
627 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
631 if (adapter->nic_ops->init_driver(adapter)) {
632 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
636 if (adapter->portnum == 0)
637 qlcnic_set_drv_version(adapter);
639 qlcnic_dcb_get_info(adapter);
640 qlcnic_83xx_idc_attach_driver(adapter);
645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
647 struct qlcnic_hardware_context *ahw = adapter->ahw;
649 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
650 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
651 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
653 ahw->idc.quiesce_req = 0;
654 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
655 ahw->idc.err_code = 0;
656 ahw->idc.collect_dump = 0;
657 ahw->reset_context = 0;
658 adapter->tx_timeo_cnt = 0;
659 ahw->idc.delay_reset = 0;
661 clear_bit(__QLCNIC_RESETTING, &adapter->state);
665 * qlcnic_83xx_idc_ready_state_entry
667 * @adapter: adapter structure
669 * Perform ready state initialization, this routine will get invoked only
670 * once from READY state.
672 * Returns: Error code or Success(0)
675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
677 struct qlcnic_hardware_context *ahw = adapter->ahw;
679 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
680 qlcnic_83xx_idc_update_idc_params(adapter);
681 /* Re-attach the device if required */
682 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
683 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
684 if (qlcnic_83xx_idc_reattach_driver(adapter))
693 * qlcnic_83xx_idc_vnic_pf_entry
695 * @adapter: adapter structure
697 * Ensure vNIC mode privileged function starts only after vNIC mode is
698 * enabled by management function.
699 * If vNIC mode is ready, start initialization.
704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
707 struct qlcnic_hardware_context *ahw = adapter->ahw;
709 /* Privileged function waits till mgmt function enables VNIC mode */
710 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
711 if (state != QLCNIC_DEV_NPAR_OPER) {
712 if (!ahw->idc.vnic_wait_limit--) {
713 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
716 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
720 /* Perform one time initialization from ready state */
721 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
722 qlcnic_83xx_idc_update_idc_params(adapter);
724 /* If the previous state is UNKNOWN, device will be
725 already attached properly by Init routine*/
726 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
727 if (qlcnic_83xx_idc_reattach_driver(adapter))
730 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
731 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
740 adapter->ahw->idc.err_code = -EIO;
741 dev_err(&adapter->pdev->dev,
742 "%s: Device in unknown state\n", __func__);
747 * qlcnic_83xx_idc_cold_state
749 * @adapter: adapter structure
751 * If HW is up and running device will enter READY state.
752 * If firmware image from host needs to be loaded, device is
753 * forced to start with the file firmware image.
755 * Returns: Error code or Success(0)
758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
760 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
761 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
763 if (qlcnic_load_fw_file) {
764 qlcnic_83xx_idc_restart_hw(adapter, 0);
766 if (qlcnic_83xx_check_hw_status(adapter)) {
767 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
770 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
777 * qlcnic_83xx_idc_init_state
779 * @adapter: adapter structure
781 * Reset owner will restart the device from this state.
782 * Device will enter failed state if it remains
783 * in this state for more than DEV_INIT time limit.
785 * Returns: Error code or Success(0)
788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
790 int timeout, ret = 0;
793 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
794 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
795 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
796 if (adapter->ahw->pci_func == owner)
797 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
799 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
807 * qlcnic_83xx_idc_ready_state
809 * @adapter: adapter structure
811 * Perform IDC protocol specicifed actions after monitoring device state and
814 * Returns: Error code or Success(0)
817 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
819 struct qlcnic_hardware_context *ahw = adapter->ahw;
820 struct qlcnic_mailbox *mbx = ahw->mailbox;
824 /* Perform NIC configuration based ready state entry actions */
825 if (ahw->idc.state_entry(adapter))
828 if (qlcnic_check_temp(adapter)) {
829 if (ahw->temp == QLCNIC_TEMP_PANIC) {
830 qlcnic_83xx_idc_check_fan_failure(adapter);
831 dev_err(&adapter->pdev->dev,
832 "Error: device temperature %d above limits\n",
834 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
835 set_bit(__QLCNIC_RESETTING, &adapter->state);
836 qlcnic_83xx_idc_detach_driver(adapter);
837 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
842 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
843 ret = qlcnic_83xx_check_heartbeat(adapter);
845 adapter->flags |= QLCNIC_FW_HANG;
846 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
847 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
848 set_bit(__QLCNIC_RESETTING, &adapter->state);
849 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
854 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
855 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
857 /* Move to need reset state and prepare for reset */
858 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
862 /* Check for soft reset request */
863 if (ahw->reset_context &&
864 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
865 adapter->ahw->reset_context = 0;
866 qlcnic_83xx_idc_tx_soft_reset(adapter);
870 /* Move to need quiesce state if requested */
871 if (adapter->ahw->idc.quiesce_req) {
872 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
873 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
881 * qlcnic_83xx_idc_need_reset_state
883 * @adapter: adapter structure
885 * Device will remain in this state until:
886 * Reset request ACK's are recieved from all the functions
887 * Wait time exceeds max time limit
889 * Returns: Error code or Success(0)
892 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
894 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
897 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
898 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
899 set_bit(__QLCNIC_RESETTING, &adapter->state);
900 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
901 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
902 qlcnic_83xx_disable_vnic_mode(adapter, 1);
904 if (qlcnic_check_diag_status(adapter)) {
905 dev_info(&adapter->pdev->dev,
906 "%s: Wait for diag completion\n", __func__);
907 adapter->ahw->idc.delay_reset = 1;
910 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
911 qlcnic_83xx_idc_detach_driver(adapter);
915 if (qlcnic_check_diag_status(adapter)) {
916 dev_info(&adapter->pdev->dev,
917 "%s: Wait for diag completion\n", __func__);
920 if (adapter->ahw->idc.delay_reset) {
921 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
922 qlcnic_83xx_idc_detach_driver(adapter);
923 adapter->ahw->idc.delay_reset = 0;
926 /* Check for ACK from other functions */
927 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
929 dev_info(&adapter->pdev->dev,
930 "%s: Waiting for reset ACK\n", __func__);
935 /* Transit to INIT state and restart the HW */
936 qlcnic_83xx_idc_enter_init_state(adapter, 1);
941 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
943 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
947 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
949 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
950 clear_bit(__QLCNIC_RESETTING, &adapter->state);
951 adapter->ahw->idc.err_code = -EIO;
956 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
958 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
962 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
967 cur = adapter->ahw->idc.curr_state;
968 prev = adapter->ahw->idc.prev_state;
971 if ((next < QLC_83XX_IDC_DEV_COLD) ||
972 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
973 dev_err(&adapter->pdev->dev,
974 "%s: curr %d, prev %d, next state %d is invalid\n",
975 __func__, cur, prev, state);
979 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
980 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
981 if ((next != QLC_83XX_IDC_DEV_COLD) &&
982 (next != QLC_83XX_IDC_DEV_READY)) {
983 dev_err(&adapter->pdev->dev,
984 "%s: failed, cur %d prev %d next %d\n",
985 __func__, cur, prev, next);
990 if (next == QLC_83XX_IDC_DEV_INIT) {
991 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
992 (prev != QLC_83XX_IDC_DEV_COLD) &&
993 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
994 dev_err(&adapter->pdev->dev,
995 "%s: failed, cur %d prev %d next %d\n",
996 __func__, cur, prev, next);
1004 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1006 if (adapter->fhash.fnum)
1007 qlcnic_prune_lb_filters(adapter);
1011 * qlcnic_83xx_idc_poll_dev_state
1013 * @work: kernel work queue structure used to schedule the function
1015 * Poll device state periodically and perform state specific
1016 * actions defined by Inter Driver Communication (IDC) protocol.
1021 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1023 struct qlcnic_adapter *adapter;
1026 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1027 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1029 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1030 qlcnic_83xx_idc_log_state_history(adapter);
1031 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1033 adapter->ahw->idc.curr_state = state;
1036 switch (adapter->ahw->idc.curr_state) {
1037 case QLC_83XX_IDC_DEV_READY:
1038 qlcnic_83xx_idc_ready_state(adapter);
1040 case QLC_83XX_IDC_DEV_NEED_RESET:
1041 qlcnic_83xx_idc_need_reset_state(adapter);
1043 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1044 qlcnic_83xx_idc_need_quiesce_state(adapter);
1046 case QLC_83XX_IDC_DEV_FAILED:
1047 qlcnic_83xx_idc_failed_state(adapter);
1049 case QLC_83XX_IDC_DEV_INIT:
1050 qlcnic_83xx_idc_init_state(adapter);
1052 case QLC_83XX_IDC_DEV_QUISCENT:
1053 qlcnic_83xx_idc_quiesce_state(adapter);
1056 qlcnic_83xx_idc_unknown_state(adapter);
1059 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1060 qlcnic_83xx_periodic_tasks(adapter);
1062 /* Re-schedule the function */
1063 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1064 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1065 adapter->ahw->idc.delay);
1068 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1070 u32 idc_params, val;
1072 if (qlcnic_83xx_lockless_flash_read32(adapter,
1073 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1074 (u8 *)&idc_params, 1)) {
1075 dev_info(&adapter->pdev->dev,
1076 "%s:failed to get IDC params from flash\n", __func__);
1077 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1078 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1080 adapter->dev_init_timeo = idc_params & 0xFFFF;
1081 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1084 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1085 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1086 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1087 adapter->ahw->idc.err_code = 0;
1088 adapter->ahw->idc.collect_dump = 0;
1089 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1091 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1092 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1094 /* Check if reset recovery is disabled */
1095 if (!qlcnic_auto_fw_reset) {
1096 /* Propagate do not reset request to other functions */
1097 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1098 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1099 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1104 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1108 if (qlcnic_83xx_lock_driver(adapter))
1111 /* Clear driver lock register */
1112 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1113 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1114 qlcnic_83xx_unlock_driver(adapter);
1118 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1119 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1120 qlcnic_83xx_unlock_driver(adapter);
1124 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1125 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1126 QLC_83XX_IDC_DEV_COLD);
1127 state = QLC_83XX_IDC_DEV_COLD;
1130 adapter->ahw->idc.curr_state = state;
1131 /* First to load function should cold boot the device */
1132 if (state == QLC_83XX_IDC_DEV_COLD)
1133 qlcnic_83xx_idc_cold_state_handler(adapter);
1135 /* Check if reset recovery is enabled */
1136 if (qlcnic_auto_fw_reset) {
1137 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1138 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1139 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1142 qlcnic_83xx_unlock_driver(adapter);
1147 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1151 qlcnic_83xx_setup_idc_parameters(adapter);
1153 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1156 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1157 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1160 if (qlcnic_83xx_idc_check_major_version(adapter))
1164 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1169 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1174 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1175 usleep_range(10000, 11000);
1177 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1180 if (id == adapter->portnum) {
1181 dev_err(&adapter->pdev->dev,
1182 "%s: wait for lock recovery.. %d\n", __func__, id);
1184 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1188 /* Clear driver presence bit */
1189 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1190 val = val & ~(1 << adapter->portnum);
1191 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1192 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1193 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1195 cancel_delayed_work_sync(&adapter->fw_work);
1198 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1202 if (qlcnic_sriov_vf_check(adapter))
1205 if (qlcnic_83xx_lock_driver(adapter)) {
1206 dev_err(&adapter->pdev->dev,
1207 "%s:failed, please retry\n", __func__);
1211 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1212 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1213 !qlcnic_auto_fw_reset) {
1214 dev_err(&adapter->pdev->dev,
1215 "%s:failed, device in non reset mode\n", __func__);
1216 qlcnic_83xx_unlock_driver(adapter);
1220 if (key == QLCNIC_FORCE_FW_RESET) {
1221 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1222 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1223 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1224 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1225 adapter->ahw->idc.collect_dump = 1;
1228 qlcnic_83xx_unlock_driver(adapter);
1232 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1239 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1240 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1241 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1243 /* alignment check */
1245 size = (size + 16) & ~0xF;
1247 p_cache = kzalloc(size, GFP_KERNEL);
1248 if (p_cache == NULL)
1251 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1252 size / sizeof(u32));
1257 /* 16 byte write to MS memory */
1258 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1269 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1277 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1278 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1279 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1282 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1283 (u32 *)p_cache, size / 16);
1285 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1286 release_firmware(adapter->ahw->fw_info.fw);
1287 adapter->ahw->fw_info.fw = NULL;
1291 /* alignment check */
1292 if (adapter->ahw->fw_info.fw->size & 0xF) {
1294 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1295 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1298 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1301 dev_err(&adapter->pdev->dev,
1302 "MS memory write failed\n");
1303 release_firmware(adapter->ahw->fw_info.fw);
1304 adapter->ahw->fw_info.fw = NULL;
1308 release_firmware(adapter->ahw->fw_info.fw);
1309 adapter->ahw->fw_info.fw = NULL;
1314 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1317 u32 val = 0, val1 = 0, reg = 0;
1320 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1323 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1325 for (j = 0; j < 2; j++) {
1327 dev_info(&adapter->pdev->dev,
1328 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1329 reg = QLC_83XX_PORT0_THRESHOLD;
1330 } else if (j == 1) {
1331 dev_info(&adapter->pdev->dev,
1332 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1333 reg = QLC_83XX_PORT1_THRESHOLD;
1335 for (i = 0; i < 8; i++) {
1336 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1339 dev_info(&adapter->pdev->dev, "0x%x ", val);
1341 dev_info(&adapter->pdev->dev, "\n");
1344 for (j = 0; j < 2; j++) {
1346 dev_info(&adapter->pdev->dev,
1347 "Port 0 RxB TC Max Cell Registers[4..1]:");
1348 reg = QLC_83XX_PORT0_TC_MC_REG;
1349 } else if (j == 1) {
1350 dev_info(&adapter->pdev->dev,
1351 "Port 1 RxB TC Max Cell Registers[4..1]:");
1352 reg = QLC_83XX_PORT1_TC_MC_REG;
1354 for (i = 0; i < 4; i++) {
1355 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1358 dev_info(&adapter->pdev->dev, "0x%x ", val);
1360 dev_info(&adapter->pdev->dev, "\n");
1363 for (j = 0; j < 2; j++) {
1365 dev_info(&adapter->pdev->dev,
1366 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1367 reg = QLC_83XX_PORT0_TC_STATS;
1368 } else if (j == 1) {
1369 dev_info(&adapter->pdev->dev,
1370 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1371 reg = QLC_83XX_PORT1_TC_STATS;
1373 for (i = 7; i >= 0; i--) {
1374 val = QLCRD32(adapter, reg, &err);
1377 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1378 QLCWR32(adapter, reg, (val | (i << 29)));
1379 val = QLCRD32(adapter, reg, &err);
1382 dev_info(&adapter->pdev->dev, "0x%x ", val);
1384 dev_info(&adapter->pdev->dev, "\n");
1387 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1390 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1393 dev_info(&adapter->pdev->dev,
1394 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1399 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1403 if (qlcnic_83xx_lock_driver(adapter)) {
1404 dev_err(&adapter->pdev->dev,
1405 "%s:failed to acquire driver lock\n", __func__);
1409 qlcnic_83xx_dump_pause_control_regs(adapter);
1410 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1412 for (j = 0; j < 2; j++) {
1414 reg = QLC_83XX_PORT0_THRESHOLD;
1416 reg = QLC_83XX_PORT1_THRESHOLD;
1418 for (i = 0; i < 8; i++)
1419 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1422 for (j = 0; j < 2; j++) {
1424 reg = QLC_83XX_PORT0_TC_MC_REG;
1426 reg = QLC_83XX_PORT1_TC_MC_REG;
1428 for (i = 0; i < 4; i++)
1429 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1432 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1433 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1434 dev_info(&adapter->pdev->dev,
1435 "Disabled pause frames successfully on all ports\n");
1436 qlcnic_83xx_unlock_driver(adapter);
1439 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1441 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1442 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1443 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1444 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1445 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1446 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1447 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1448 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1449 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1452 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1454 u32 heartbeat, peg_status;
1455 int retries, ret = -EIO, err = 0;
1457 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1458 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1459 QLCNIC_PEG_ALIVE_COUNTER);
1462 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1463 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1464 QLCNIC_PEG_ALIVE_COUNTER);
1465 if (heartbeat != p_dev->heartbeat) {
1466 ret = QLCNIC_RCODE_SUCCESS;
1469 } while (--retries);
1472 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1473 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1474 qlcnic_83xx_disable_pause_frames(p_dev);
1475 peg_status = QLC_SHARED_REG_RD32(p_dev,
1476 QLCNIC_PEG_HALT_STATUS1);
1477 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1478 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1479 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1480 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1481 "PEG_NET_4_PC: 0x%x\n", peg_status,
1482 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1483 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1484 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1485 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1486 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1487 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1489 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1490 dev_err(&p_dev->pdev->dev,
1491 "Device is being reset err code 0x00006700.\n");
1497 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1499 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1503 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1504 if (val == QLC_83XX_CMDPEG_COMPLETE)
1506 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1507 } while (--retries);
1509 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1513 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1517 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1521 err = qlcnic_83xx_check_heartbeat(p_dev);
1528 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1529 int duration, u32 mask, u32 status)
1531 int timeout_error, err = 0;
1535 value = QLCRD32(p_dev, addr, &err);
1538 retries = duration / 10;
1541 if ((value & mask) != status) {
1543 msleep(duration / 10);
1544 value = QLCRD32(p_dev, addr, &err);
1551 } while (retries--);
1553 if (timeout_error) {
1554 p_dev->ahw->reset.seq_error++;
1555 dev_err(&p_dev->pdev->dev,
1556 "%s: Timeout Err, entry_num = %d\n",
1557 __func__, p_dev->ahw->reset.seq_index);
1558 dev_err(&p_dev->pdev->dev,
1559 "0x%08x 0x%08x 0x%08x\n",
1560 value, mask, status);
1563 return timeout_error;
1566 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1569 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1570 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1576 sum = (sum & 0xFFFF) + (sum >> 16);
1581 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1586 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1588 struct qlcnic_hardware_context *ahw = p_dev->ahw;
1589 u32 addr, count, prev_ver, curr_ver;
1592 if (ahw->reset.buff != NULL) {
1593 prev_ver = p_dev->fw_version;
1594 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1595 if (curr_ver > prev_ver)
1596 kfree(ahw->reset.buff);
1601 ahw->reset.seq_error = 0;
1602 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1603 if (p_dev->ahw->reset.buff == NULL)
1606 p_buff = p_dev->ahw->reset.buff;
1607 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1608 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1610 /* Copy template header from flash */
1611 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1612 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1615 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1616 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1617 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1618 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1620 /* Copy rest of the template */
1621 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1622 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1626 if (qlcnic_83xx_reset_template_checksum(p_dev))
1628 /* Get Stop, Start and Init command offsets */
1629 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1630 ahw->reset.start_offset = ahw->reset.buff +
1631 ahw->reset.hdr->start_offset;
1632 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1636 /* Read Write HW register command */
1637 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1638 u32 raddr, u32 waddr)
1643 value = QLCRD32(p_dev, raddr, &err);
1646 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1649 /* Read Modify Write HW register command */
1650 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1651 u32 raddr, u32 waddr,
1652 struct qlc_83xx_rmw *p_rmw_hdr)
1657 if (p_rmw_hdr->index_a) {
1658 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1660 value = QLCRD32(p_dev, raddr, &err);
1665 value &= p_rmw_hdr->mask;
1666 value <<= p_rmw_hdr->shl;
1667 value >>= p_rmw_hdr->shr;
1668 value |= p_rmw_hdr->or_value;
1669 value ^= p_rmw_hdr->xor_value;
1670 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1673 /* Write HW register command */
1674 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1675 struct qlc_83xx_entry_hdr *p_hdr)
1678 struct qlc_83xx_entry *entry;
1680 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1681 sizeof(struct qlc_83xx_entry_hdr));
1683 for (i = 0; i < p_hdr->count; i++, entry++) {
1684 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1687 udelay((u32)(p_hdr->delay));
1691 /* Read and Write instruction */
1692 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1693 struct qlc_83xx_entry_hdr *p_hdr)
1696 struct qlc_83xx_entry *entry;
1698 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1699 sizeof(struct qlc_83xx_entry_hdr));
1701 for (i = 0; i < p_hdr->count; i++, entry++) {
1702 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1705 udelay((u32)(p_hdr->delay));
1709 /* Poll HW register command */
1710 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1711 struct qlc_83xx_entry_hdr *p_hdr)
1714 struct qlc_83xx_entry *entry;
1715 struct qlc_83xx_poll *poll;
1717 unsigned long arg1, arg2;
1719 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1720 sizeof(struct qlc_83xx_entry_hdr));
1722 entry = (struct qlc_83xx_entry *)((char *)poll +
1723 sizeof(struct qlc_83xx_poll));
1724 delay = (long)p_hdr->delay;
1727 for (i = 0; i < p_hdr->count; i++, entry++)
1728 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1732 for (i = 0; i < p_hdr->count; i++, entry++) {
1736 if (qlcnic_83xx_poll_reg(p_dev,
1740 QLCRD32(p_dev, arg1, &err);
1743 QLCRD32(p_dev, arg2, &err);
1752 /* Poll and write HW register command */
1753 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1754 struct qlc_83xx_entry_hdr *p_hdr)
1758 struct qlc_83xx_quad_entry *entry;
1759 struct qlc_83xx_poll *poll;
1761 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1762 sizeof(struct qlc_83xx_entry_hdr));
1763 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1764 sizeof(struct qlc_83xx_poll));
1765 delay = (long)p_hdr->delay;
1767 for (i = 0; i < p_hdr->count; i++, entry++) {
1768 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1770 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1773 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1774 poll->mask, poll->status);
1778 /* Read Modify Write register command */
1779 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1780 struct qlc_83xx_entry_hdr *p_hdr)
1783 struct qlc_83xx_entry *entry;
1784 struct qlc_83xx_rmw *rmw_hdr;
1786 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1787 sizeof(struct qlc_83xx_entry_hdr));
1789 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1790 sizeof(struct qlc_83xx_rmw));
1792 for (i = 0; i < p_hdr->count; i++, entry++) {
1793 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1794 entry->arg2, rmw_hdr);
1796 udelay((u32)(p_hdr->delay));
1800 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1803 mdelay((u32)((long)p_hdr->delay));
1806 /* Read and poll register command */
1807 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1808 struct qlc_83xx_entry_hdr *p_hdr)
1811 int index, i, j, err;
1812 struct qlc_83xx_quad_entry *entry;
1813 struct qlc_83xx_poll *poll;
1816 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1817 sizeof(struct qlc_83xx_entry_hdr));
1819 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1820 sizeof(struct qlc_83xx_poll));
1821 delay = (long)p_hdr->delay;
1823 for (i = 0; i < p_hdr->count; i++, entry++) {
1824 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1827 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1828 poll->mask, poll->status)){
1829 index = p_dev->ahw->reset.array_index;
1830 addr = entry->dr_addr;
1831 j = QLCRD32(p_dev, addr, &err);
1835 p_dev->ahw->reset.array[index++] = j;
1837 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1838 p_dev->ahw->reset.array_index = 1;
1844 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1846 p_dev->ahw->reset.seq_end = 1;
1849 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1851 p_dev->ahw->reset.template_end = 1;
1852 if (p_dev->ahw->reset.seq_error == 0)
1853 dev_err(&p_dev->pdev->dev,
1854 "HW restart process completed successfully.\n");
1856 dev_err(&p_dev->pdev->dev,
1857 "HW restart completed with timeout errors.\n");
1861 * qlcnic_83xx_exec_template_cmd
1863 * @p_dev: adapter structure
1864 * @p_buff: Poiter to instruction template
1866 * Template provides instructions to stop, restart and initalize firmware.
1867 * These instructions are abstracted as a series of read, write and
1868 * poll operations on hardware registers. Register information and operation
1869 * specifics are not exposed to the driver. Driver reads the template from
1870 * flash and executes the instructions located at pre-defined offsets.
1874 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1878 struct qlc_83xx_entry_hdr *p_hdr;
1879 char *entry = p_buff;
1881 p_dev->ahw->reset.seq_end = 0;
1882 p_dev->ahw->reset.template_end = 0;
1883 entries = p_dev->ahw->reset.hdr->entries;
1884 index = p_dev->ahw->reset.seq_index;
1886 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1887 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1889 switch (p_hdr->cmd) {
1890 case QLC_83XX_OPCODE_NOP:
1892 case QLC_83XX_OPCODE_WRITE_LIST:
1893 qlcnic_83xx_write_list(p_dev, p_hdr);
1895 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1896 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1898 case QLC_83XX_OPCODE_POLL_LIST:
1899 qlcnic_83xx_poll_list(p_dev, p_hdr);
1901 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1902 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1904 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1905 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1907 case QLC_83XX_OPCODE_SEQ_PAUSE:
1908 qlcnic_83xx_pause(p_hdr);
1910 case QLC_83XX_OPCODE_SEQ_END:
1911 qlcnic_83xx_seq_end(p_dev);
1913 case QLC_83XX_OPCODE_TMPL_END:
1914 qlcnic_83xx_template_end(p_dev);
1916 case QLC_83XX_OPCODE_POLL_READ_LIST:
1917 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1920 dev_err(&p_dev->pdev->dev,
1921 "%s: Unknown opcode 0x%04x in template %d\n",
1922 __func__, p_hdr->cmd, index);
1925 entry += p_hdr->size;
1927 p_dev->ahw->reset.seq_index = index;
1930 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1932 p_dev->ahw->reset.seq_index = 0;
1934 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1935 if (p_dev->ahw->reset.seq_end != 1)
1936 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1939 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1941 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1942 if (p_dev->ahw->reset.template_end != 1)
1943 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1946 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1948 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1949 if (p_dev->ahw->reset.seq_end != 1)
1950 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1953 static void qlcnic_83xx_get_fw_file_name(struct qlcnic_adapter *adapter,
1956 struct pci_dev *pdev = adapter->pdev;
1958 memset(file_name, 0, QLC_FW_FILE_NAME_LEN);
1960 switch (pdev->device) {
1961 case PCI_DEVICE_ID_QLOGIC_QLE834X:
1962 strncpy(file_name, QLC_83XX_FW_FILE_NAME,
1963 QLC_FW_FILE_NAME_LEN);
1965 case PCI_DEVICE_ID_QLOGIC_QLE844X:
1966 strncpy(file_name, QLC_84XX_FW_FILE_NAME,
1967 QLC_FW_FILE_NAME_LEN);
1970 dev_err(&pdev->dev, "%s: Invalid device id\n",
1975 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1977 char fw_file_name[QLC_FW_FILE_NAME_LEN];
1980 qlcnic_83xx_get_fw_file_name(adapter, fw_file_name);
1981 if (request_firmware(&adapter->ahw->fw_info.fw, fw_file_name,
1982 &(adapter->pdev->dev))) {
1983 dev_err(&adapter->pdev->dev,
1984 "No file FW image, loading flash FW image.\n");
1985 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1986 QLC_83XX_BOOT_FROM_FLASH);
1988 if (qlcnic_83xx_copy_fw_file(adapter))
1990 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1991 QLC_83XX_BOOT_FROM_FILE);
1997 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
2002 qlcnic_83xx_stop_hw(adapter);
2004 /* Collect FW register dump if required */
2005 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2006 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2007 qlcnic_dump_fw(adapter);
2008 qlcnic_83xx_init_hw(adapter);
2010 if (qlcnic_83xx_copy_bootloader(adapter))
2012 /* Boot either flash image or firmware image from host file system */
2013 if (qlcnic_load_fw_file) {
2014 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2017 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2018 QLC_83XX_BOOT_FROM_FLASH);
2021 qlcnic_83xx_start_hw(adapter);
2022 if (qlcnic_83xx_check_hw_status(adapter))
2029 * qlcnic_83xx_config_default_opmode
2031 * @adapter: adapter structure
2033 * Configure default driver operating mode
2035 * Returns: Error code or Success(0)
2037 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
2040 struct qlcnic_hardware_context *ahw = adapter->ahw;
2042 qlcnic_get_func_no(adapter);
2043 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
2045 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2046 op_mode = QLC_83XX_DEFAULT_OPMODE;
2048 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
2049 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2050 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2058 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2061 struct qlcnic_info nic_info;
2062 struct qlcnic_hardware_context *ahw = adapter->ahw;
2064 memset(&nic_info, 0, sizeof(struct qlcnic_info));
2065 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2069 ahw->physical_port = (u8) nic_info.phys_port;
2070 ahw->switch_mode = nic_info.switch_mode;
2071 ahw->max_tx_ques = nic_info.max_tx_ques;
2072 ahw->max_rx_ques = nic_info.max_rx_ques;
2073 ahw->capabilities = nic_info.capabilities;
2074 ahw->max_mac_filters = nic_info.max_mac_filters;
2075 ahw->max_mtu = nic_info.max_mtu;
2077 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2078 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2079 * exclusive. So in case of sriov capable device load driver in
2082 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2083 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2084 return ahw->nic_mode;
2087 if (ahw->capabilities & BIT_23)
2088 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2090 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2092 return ahw->nic_mode;
2095 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2099 ret = qlcnic_83xx_get_nic_configuration(adapter);
2103 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2104 if (qlcnic_83xx_config_vnic_opmode(adapter))
2106 } else if (ret == QLC_83XX_DEFAULT_MODE) {
2107 if (qlcnic_83xx_config_default_opmode(adapter))
2114 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2116 struct qlcnic_hardware_context *ahw = adapter->ahw;
2118 if (ahw->port_type == QLCNIC_XGBE) {
2119 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2120 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2121 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2122 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2124 } else if (ahw->port_type == QLCNIC_GBE) {
2125 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2126 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2127 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2128 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2130 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2131 adapter->max_rds_rings = MAX_RDS_RINGS;
2134 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2138 qlcnic_83xx_get_minidump_template(adapter);
2139 if (qlcnic_83xx_get_port_info(adapter))
2142 qlcnic_83xx_config_buff_descriptors(adapter);
2143 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2144 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2146 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2147 adapter->ahw->fw_hal_version);
2152 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2153 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2155 struct qlcnic_cmd_args cmd;
2156 u32 presence_mask, audit_mask;
2159 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2160 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2162 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2163 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2164 QLCNIC_CMD_STOP_NIC_FUNC);
2168 cmd.req.arg[1] = BIT_31;
2169 status = qlcnic_issue_cmd(adapter, &cmd);
2171 dev_err(&adapter->pdev->dev,
2172 "Failed to clean up the function resources\n");
2173 qlcnic_free_mbx_args(&cmd);
2177 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2179 struct qlcnic_hardware_context *ahw = adapter->ahw;
2182 ahw->msix_supported = !!qlcnic_use_msi_x;
2183 err = qlcnic_83xx_init_mailbox_work(adapter);
2187 if (qlcnic_sriov_vf_check(adapter)) {
2188 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2195 err = qlcnic_83xx_check_hw_status(adapter);
2199 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2200 qlcnic_83xx_read_flash_mfg_id(adapter);
2202 err = qlcnic_83xx_idc_init(adapter);
2206 err = qlcnic_setup_intr(adapter, 0, 0);
2208 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2212 err = qlcnic_83xx_setup_mbx_intr(adapter);
2214 goto disable_mbx_intr;
2216 qlcnic_83xx_clear_function_resources(adapter);
2218 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2220 /* register for NIC IDC AEN Events */
2221 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2223 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2224 err = qlcnic_83xx_configure_opmode(adapter);
2226 goto disable_mbx_intr;
2228 /* Perform operating mode specific initialization */
2229 err = adapter->nic_ops->init_driver(adapter);
2231 goto disable_mbx_intr;
2233 if (adapter->dcb && qlcnic_dcb_attach(adapter))
2234 qlcnic_clear_dcb_ops(adapter);
2236 /* Periodically monitor device status */
2237 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2241 qlcnic_83xx_free_mbx_intr(adapter);
2244 qlcnic_teardown_intr(adapter);
2247 qlcnic_83xx_detach_mailbox_work(adapter);
2248 qlcnic_83xx_free_mailbox(ahw->mailbox);