drivers/net/ethernet/pensando/ionic/ionic_lif.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
   3
   4 #include <linux/printk.h>
   5 #include <linux/dynamic_debug.h>
   6 #include <linux/netdevice.h>
   7 #include <linux/etherdevice.h>
   8 #include <linux/if_vlan.h>
   9 #include <linux/rtnetlink.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/cpumask.h>
  13
  14 #include "ionic.h"
  15 #include "ionic_bus.h"
  16 #include "ionic_lif.h"
  17 #include "ionic_txrx.h"
  18 #include "ionic_ethtool.h"
  19 #include "ionic_debugfs.h"
  20
  21 /* queuetype support level */
  22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
  23         [IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
  24         [IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
  25         [IONIC_QTYPE_RXQ]     = 0,   /* 0 = Base version with CQ+SG support */
  26         [IONIC_QTYPE_TXQ]     = 1,   /* 0 = Base version with CQ+SG support
  27                                       * 1 =   ... with Tx SG version 1
  28                                       */
  29 };
  30
  31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode);
  32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr);
  33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr);
  34 static void ionic_link_status_check(struct ionic_lif *lif);
  35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
  36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
  37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
  38
  39 static int ionic_start_queues(struct ionic_lif *lif);
  40 static void ionic_stop_queues(struct ionic_lif *lif);
  41 static void ionic_lif_queue_identify(struct ionic_lif *lif);
  42
  43 static void ionic_lif_deferred_work(struct work_struct *work)
  44 {
  45         struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
  46         struct ionic_deferred *def = &lif->deferred;
  47         struct ionic_deferred_work *w = NULL;
  48
  49         spin_lock_bh(&def->lock);
  50         if (!list_empty(&def->list)) {
  51                 w = list_first_entry(&def->list,
  52                                      struct ionic_deferred_work, list);
  53                 list_del(&w->list);
  54         }
  55         spin_unlock_bh(&def->lock);
  56
  57         if (w) {
  58                 switch (w->type) {
  59                 case IONIC_DW_TYPE_RX_MODE:
  60                         ionic_lif_rx_mode(lif, w->rx_mode);
  61                         break;
  62                 case IONIC_DW_TYPE_RX_ADDR_ADD:
  63                         ionic_lif_addr_add(lif, w->addr);
  64                         break;
  65                 case IONIC_DW_TYPE_RX_ADDR_DEL:
  66                         ionic_lif_addr_del(lif, w->addr);
  67                         break;
  68                 case IONIC_DW_TYPE_LINK_STATUS:
  69                         ionic_link_status_check(lif);
  70                         break;
  71                 case IONIC_DW_TYPE_LIF_RESET:
  72                         if (w->fw_status)
  73                                 ionic_lif_handle_fw_up(lif);
  74                         else
  75                                 ionic_lif_handle_fw_down(lif);
  76                         break;
  77                 default:
  78                         break;
  79                 }
  80                 kfree(w);
  81                 schedule_work(&def->work);
  82         }
  83 }
  84
  85 void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
  86                                 struct ionic_deferred_work *work)
  87 {
  88         spin_lock_bh(&def->lock);
  89         list_add_tail(&work->list, &def->list);
  90         spin_unlock_bh(&def->lock);
  91         schedule_work(&def->work);
  92 }
  93
  94 static void ionic_link_status_check(struct ionic_lif *lif)
  95 {
  96         struct net_device *netdev = lif->netdev;
  97         u16 link_status;
  98         bool link_up;
  99
 100         if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 101                 return;
 102
 103         link_status = le16_to_cpu(lif->info->status.link_status);
 104         link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
 105
 106         if (link_up) {
 107                 if (!netif_carrier_ok(netdev)) {
 108                         u32 link_speed;
 109
 110                         ionic_port_identify(lif->ionic);
 111                         link_speed = le32_to_cpu(lif->info->status.link_speed);
 112                         netdev_info(netdev, "Link up - %d Gbps\n",
 113                                     link_speed / 1000);
 114                         netif_carrier_on(netdev);
 115                 }
 116
 117                 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) {
 118                         mutex_lock(&lif->queue_lock);
 119                         ionic_start_queues(lif);
 120                         mutex_unlock(&lif->queue_lock);
 121                 }
 122         } else {
 123                 if (netif_carrier_ok(netdev)) {
 124                         netdev_info(netdev, "Link down\n");
 125                         netif_carrier_off(netdev);
 126                 }
 127
 128                 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) {
 129                         mutex_lock(&lif->queue_lock);
 130                         ionic_stop_queues(lif);
 131                         mutex_unlock(&lif->queue_lock);
 132                 }
 133         }
 134
 135         clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 136 }
 137
 138 void ionic_link_status_check_request(struct ionic_lif *lif)
 139 {
 140         struct ionic_deferred_work *work;
 141
 142         /* we only need one request outstanding at a time */
 143         if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 144                 return;
 145
 146         if (in_interrupt()) {
 147                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 148                 if (!work)
 149                         return;
 150
 151                 work->type = IONIC_DW_TYPE_LINK_STATUS;
 152                 ionic_lif_deferred_enqueue(&lif->deferred, work);
 153         } else {
 154                 ionic_link_status_check(lif);
 155         }
 156 }
 157
 158 static irqreturn_t ionic_isr(int irq, void *data)
 159 {
 160         struct napi_struct *napi = data;
 161
 162         napi_schedule_irqoff(napi);
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
 168 {
 169         struct ionic_intr_info *intr = &qcq->intr;
 170         struct device *dev = lif->ionic->dev;
 171         struct ionic_queue *q = &qcq->q;
 172         const char *name;
 173
 174         if (lif->registered)
 175                 name = lif->netdev->name;
 176         else
 177                 name = dev_name(dev);
 178
 179         snprintf(intr->name, sizeof(intr->name),
 180                  "%s-%s-%s", IONIC_DRV_NAME, name, q->name);
 181
 182         return devm_request_irq(dev, intr->vector, ionic_isr,
 183                                 0, intr->name, &qcq->napi);
 184 }
 185
 186 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 187 {
 188         struct ionic *ionic = lif->ionic;
 189         int index;
 190
 191         index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
 192         if (index == ionic->nintrs) {
 193                 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
 194                             __func__, index, ionic->nintrs);
 195                 return -ENOSPC;
 196         }
 197
 198         set_bit(index, ionic->intrs);
 199         ionic_intr_init(&ionic->idev, intr, index);
 200
 201         return 0;
 202 }
 203
 204 static void ionic_intr_free(struct ionic *ionic, int index)
 205 {
 206         if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
 207                 clear_bit(index, ionic->intrs);
 208 }
 209
 210 static int ionic_qcq_enable(struct ionic_qcq *qcq)
 211 {
 212         struct ionic_queue *q = &qcq->q;
 213         struct ionic_lif *lif = q->lif;
 214         struct ionic_dev *idev;
 215         struct device *dev;
 216
 217         struct ionic_admin_ctx ctx = {
 218                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 219                 .cmd.q_control = {
 220                         .opcode = IONIC_CMD_Q_CONTROL,
 221                         .lif_index = cpu_to_le16(lif->index),
 222                         .type = q->type,
 223                         .index = cpu_to_le32(q->index),
 224                         .oper = IONIC_Q_ENABLE,
 225                 },
 226         };
 227
 228         idev = &lif->ionic->idev;
 229         dev = lif->ionic->dev;
 230
 231         dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
 232                 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 233
 234         if (qcq->flags & IONIC_QCQ_F_INTR) {
 235                 irq_set_affinity_hint(qcq->intr.vector,
 236                                       &qcq->intr.affinity_mask);
 237                 napi_enable(&qcq->napi);
 238                 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
 239                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 240                                 IONIC_INTR_MASK_CLEAR);
 241         }
 242
 243         return ionic_adminq_post_wait(lif, &ctx);
 244 }
 245
 246 static int ionic_qcq_disable(struct ionic_qcq *qcq)
 247 {
 248         struct ionic_queue *q = &qcq->q;
 249         struct ionic_lif *lif = q->lif;
 250         struct ionic_dev *idev;
 251         struct device *dev;
 252
 253         struct ionic_admin_ctx ctx = {
 254                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 255                 .cmd.q_control = {
 256                         .opcode = IONIC_CMD_Q_CONTROL,
 257                         .lif_index = cpu_to_le16(lif->index),
 258                         .type = q->type,
 259                         .index = cpu_to_le32(q->index),
 260                         .oper = IONIC_Q_DISABLE,
 261                 },
 262         };
 263
 264         idev = &lif->ionic->idev;
 265         dev = lif->ionic->dev;
 266
 267         dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n",
 268                 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 269
 270         if (qcq->flags & IONIC_QCQ_F_INTR) {
 271                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 272                                 IONIC_INTR_MASK_SET);
 273                 synchronize_irq(qcq->intr.vector);
 274                 irq_set_affinity_hint(qcq->intr.vector, NULL);
 275                 napi_disable(&qcq->napi);
 276         }
 277
 278         return ionic_adminq_post_wait(lif, &ctx);
 279 }
 280
 281 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 282 {
 283         struct ionic_dev *idev = &lif->ionic->idev;
 284
 285         if (!qcq)
 286                 return;
 287
 288         if (!(qcq->flags & IONIC_QCQ_F_INITED))
 289                 return;
 290
 291         if (qcq->flags & IONIC_QCQ_F_INTR) {
 292                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 293                                 IONIC_INTR_MASK_SET);
 294                 netif_napi_del(&qcq->napi);
 295         }
 296
 297         qcq->flags &= ~IONIC_QCQ_F_INITED;
 298 }
 299
 300 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
 301 {
 302         struct device *dev = lif->ionic->dev;
 303
 304         if (!qcq)
 305                 return;
 306
 307         ionic_debugfs_del_qcq(qcq);
 308
 309         dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa);
 310         qcq->base = NULL;
 311         qcq->base_pa = 0;
 312
 313         if (qcq->flags & IONIC_QCQ_F_INTR) {
 314                 irq_set_affinity_hint(qcq->intr.vector, NULL);
 315                 devm_free_irq(dev, qcq->intr.vector, &qcq->napi);
 316                 qcq->intr.vector = 0;
 317                 ionic_intr_free(lif->ionic, qcq->intr.index);
 318         }
 319
 320         devm_kfree(dev, qcq->cq.info);
 321         qcq->cq.info = NULL;
 322         devm_kfree(dev, qcq->q.info);
 323         qcq->q.info = NULL;
 324         devm_kfree(dev, qcq);
 325 }
 326
 327 static void ionic_qcqs_free(struct ionic_lif *lif)
 328 {
 329         struct device *dev = lif->ionic->dev;
 330         unsigned int i;
 331
 332         if (lif->notifyqcq) {
 333                 ionic_qcq_free(lif, lif->notifyqcq);
 334                 lif->notifyqcq = NULL;
 335         }
 336
 337         if (lif->adminqcq) {
 338                 ionic_qcq_free(lif, lif->adminqcq);
 339                 lif->adminqcq = NULL;
 340         }
 341
 342         if (lif->rxqcqs) {
 343                 for (i = 0; i < lif->nxqs; i++)
 344                         if (lif->rxqcqs[i].stats)
 345                                 devm_kfree(dev, lif->rxqcqs[i].stats);
 346                 devm_kfree(dev, lif->rxqcqs);
 347                 lif->rxqcqs = NULL;
 348         }
 349
 350         if (lif->txqcqs) {
 351                 for (i = 0; i < lif->nxqs; i++)
 352                         if (lif->txqcqs[i].stats)
 353                                 devm_kfree(dev, lif->txqcqs[i].stats);
 354                 devm_kfree(dev, lif->txqcqs);
 355                 lif->txqcqs = NULL;
 356         }
 357 }
 358
 359 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
 360                                       struct ionic_qcq *n_qcq)
 361 {
 362         if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
 363                 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
 364                 n_qcq->flags &= ~IONIC_QCQ_F_INTR;
 365         }
 366
 367         n_qcq->intr.vector = src_qcq->intr.vector;
 368         n_qcq->intr.index = src_qcq->intr.index;
 369 }
 370
 371 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
 372                            unsigned int index,
 373                            const char *name, unsigned int flags,
 374                            unsigned int num_descs, unsigned int desc_size,
 375                            unsigned int cq_desc_size,
 376                            unsigned int sg_desc_size,
 377                            unsigned int pid, struct ionic_qcq **qcq)
 378 {
 379         struct ionic_dev *idev = &lif->ionic->idev;
 380         u32 q_size, cq_size, sg_size, total_size;
 381         struct device *dev = lif->ionic->dev;
 382         void *q_base, *cq_base, *sg_base;
 383         dma_addr_t cq_base_pa = 0;
 384         dma_addr_t sg_base_pa = 0;
 385         dma_addr_t q_base_pa = 0;
 386         struct ionic_qcq *new;
 387         int err;
 388
 389         *qcq = NULL;
 390
 391         q_size  = num_descs * desc_size;
 392         cq_size = num_descs * cq_desc_size;
 393         sg_size = num_descs * sg_desc_size;
 394
 395         total_size = ALIGN(q_size, PAGE_SIZE) + ALIGN(cq_size, PAGE_SIZE);
 396         /* Note: aligning q_size/cq_size is not enough due to cq_base
 397          * address aligning as q_base could be not aligned to the page.
 398          * Adding PAGE_SIZE.
 399          */
 400         total_size += PAGE_SIZE;
 401         if (flags & IONIC_QCQ_F_SG) {
 402                 total_size += ALIGN(sg_size, PAGE_SIZE);
 403                 total_size += PAGE_SIZE;
 404         }
 405
 406         new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
 407         if (!new) {
 408                 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
 409                 err = -ENOMEM;
 410                 goto err_out;
 411         }
 412
 413         new->flags = flags;
 414
 415         new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info),
 416                                    GFP_KERNEL);
 417         if (!new->q.info) {
 418                 netdev_err(lif->netdev, "Cannot allocate queue info\n");
 419                 err = -ENOMEM;
 420                 goto err_out;
 421         }
 422
 423         new->q.type = type;
 424
 425         err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
 426                            desc_size, sg_desc_size, pid);
 427         if (err) {
 428                 netdev_err(lif->netdev, "Cannot initialize queue\n");
 429                 goto err_out;
 430         }
 431
 432         if (flags & IONIC_QCQ_F_INTR) {
 433                 err = ionic_intr_alloc(lif, &new->intr);
 434                 if (err) {
 435                         netdev_warn(lif->netdev, "no intr for %s: %d\n",
 436                                     new->q.name, err);
 437                         goto err_out;
 438                 }
 439
 440                 err = ionic_bus_get_irq(lif->ionic, new->intr.index);
 441                 if (err < 0) {
 442                         netdev_warn(lif->netdev, "no vector for %s: %d\n",
 443                                     new->q.name, err);
 444                         goto err_out_free_intr;
 445                 }
 446                 new->intr.vector = err;
 447                 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
 448                                        IONIC_INTR_MASK_SET);
 449
 450                 err = ionic_request_irq(lif, new);
 451                 if (err) {
 452                         netdev_warn(lif->netdev, "irq request failed for %s: %d\n",
 453                                     new->q.name, err);
 454                         goto err_out_free_intr;
 455                 }
 456
 457                 new->intr.cpu = cpumask_local_spread(new->intr.index,
 458                                                      dev_to_node(dev));
 459                 if (new->intr.cpu != -1)
 460                         cpumask_set_cpu(new->intr.cpu,
 461                                         &new->intr.affinity_mask);
 462         } else {
 463                 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 464         }
 465
 466         new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info),
 467                                     GFP_KERNEL);
 468         if (!new->cq.info) {
 469                 netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
 470                 err = -ENOMEM;
 471                 goto err_out_free_irq;
 472         }
 473
 474         err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
 475         if (err) {
 476                 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
 477                 goto err_out_free_irq;
 478         }
 479
 480         new->base = dma_alloc_coherent(dev, total_size, &new->base_pa,
 481                                        GFP_KERNEL);
 482         if (!new->base) {
 483                 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
 484                 err = -ENOMEM;
 485                 goto err_out_free_irq;
 486         }
 487
 488         new->total_size = total_size;
 489
 490         q_base = new->base;
 491         q_base_pa = new->base_pa;
 492
 493         cq_base = (void *)ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
 494         cq_base_pa = ALIGN(q_base_pa + q_size, PAGE_SIZE);
 495
 496         if (flags & IONIC_QCQ_F_SG) {
 497                 sg_base = (void *)ALIGN((uintptr_t)cq_base + cq_size,
 498                                         PAGE_SIZE);
 499                 sg_base_pa = ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
 500                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 501         }
 502
 503         ionic_q_map(&new->q, q_base, q_base_pa);
 504         ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 505         ionic_cq_bind(&new->cq, &new->q);
 506
 507         *qcq = new;
 508
 509         return 0;
 510
 511 err_out_free_irq:
 512         if (flags & IONIC_QCQ_F_INTR)
 513                 devm_free_irq(dev, new->intr.vector, &new->napi);
 514 err_out_free_intr:
 515         if (flags & IONIC_QCQ_F_INTR)
 516                 ionic_intr_free(lif->ionic, new->intr.index);
 517 err_out:
 518         dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
 519         return err;
 520 }
 521
 522 static int ionic_qcqs_alloc(struct ionic_lif *lif)
 523 {
 524         struct device *dev = lif->ionic->dev;
 525         unsigned int flags;
 526         int err;
 527         int i;
 528
 529         flags = IONIC_QCQ_F_INTR;
 530         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 531                               IONIC_ADMINQ_LENGTH,
 532                               sizeof(struct ionic_admin_cmd),
 533                               sizeof(struct ionic_admin_comp),
 534                               0, lif->kern_pid, &lif->adminqcq);
 535         if (err)
 536                 return err;
 537         ionic_debugfs_add_qcq(lif, lif->adminqcq);
 538
 539         if (lif->ionic->nnqs_per_lif) {
 540                 flags = IONIC_QCQ_F_NOTIFYQ;
 541                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
 542                                       flags, IONIC_NOTIFYQ_LENGTH,
 543                                       sizeof(struct ionic_notifyq_cmd),
 544                                       sizeof(union ionic_notifyq_comp),
 545                                       0, lif->kern_pid, &lif->notifyqcq);
 546                 if (err)
 547                         goto err_out_free_adminqcq;
 548                 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
 549
 550                 /* Let the notifyq ride on the adminq interrupt */
 551                 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
 552         }
 553
 554         err = -ENOMEM;
 555         lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
 556                                    sizeof(*lif->txqcqs), GFP_KERNEL);
 557         if (!lif->txqcqs)
 558                 goto err_out_free_notifyqcq;
 559         for (i = 0; i < lif->nxqs; i++) {
 560                 lif->txqcqs[i].stats = devm_kzalloc(dev,
 561                                                     sizeof(struct ionic_q_stats),
 562                                                     GFP_KERNEL);
 563                 if (!lif->txqcqs[i].stats)
 564                         goto err_out_free_tx_stats;
 565         }
 566
 567         lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
 568                                    sizeof(*lif->rxqcqs), GFP_KERNEL);
 569         if (!lif->rxqcqs)
 570                 goto err_out_free_tx_stats;
 571         for (i = 0; i < lif->nxqs; i++) {
 572                 lif->rxqcqs[i].stats = devm_kzalloc(dev,
 573                                                     sizeof(struct ionic_q_stats),
 574                                                     GFP_KERNEL);
 575                 if (!lif->rxqcqs[i].stats)
 576                         goto err_out_free_rx_stats;
 577         }
 578
 579         return 0;
 580
 581 err_out_free_rx_stats:
 582         for (i = 0; i < lif->nxqs; i++)
 583                 if (lif->rxqcqs[i].stats)
 584                         devm_kfree(dev, lif->rxqcqs[i].stats);
 585         devm_kfree(dev, lif->rxqcqs);
 586         lif->rxqcqs = NULL;
 587 err_out_free_tx_stats:
 588         for (i = 0; i < lif->nxqs; i++)
 589                 if (lif->txqcqs[i].stats)
 590                         devm_kfree(dev, lif->txqcqs[i].stats);
 591         devm_kfree(dev, lif->txqcqs);
 592         lif->txqcqs = NULL;
 593 err_out_free_notifyqcq:
 594         if (lif->notifyqcq) {
 595                 ionic_qcq_free(lif, lif->notifyqcq);
 596                 lif->notifyqcq = NULL;
 597         }
 598 err_out_free_adminqcq:
 599         ionic_qcq_free(lif, lif->adminqcq);
 600         lif->adminqcq = NULL;
 601
 602         return err;
 603 }
 604
 605 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 606 {
 607         struct device *dev = lif->ionic->dev;
 608         struct ionic_queue *q = &qcq->q;
 609         struct ionic_cq *cq = &qcq->cq;
 610         struct ionic_admin_ctx ctx = {
 611                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 612                 .cmd.q_init = {
 613                         .opcode = IONIC_CMD_Q_INIT,
 614                         .lif_index = cpu_to_le16(lif->index),
 615                         .type = q->type,
 616                         .ver = lif->qtype_info[q->type].version,
 617                         .index = cpu_to_le32(q->index),
 618                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
 619                                              IONIC_QINIT_F_SG),
 620                         .pid = cpu_to_le16(q->pid),
 621                         .ring_size = ilog2(q->num_descs),
 622                         .ring_base = cpu_to_le64(q->base_pa),
 623                         .cq_ring_base = cpu_to_le64(cq->base_pa),
 624                         .sg_ring_base = cpu_to_le64(q->sg_base_pa),
 625                 },
 626         };
 627         unsigned int intr_index;
 628         int err;
 629
 630         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 631                 intr_index = qcq->intr.index;
 632         else
 633                 intr_index = lif->rxqcqs[q->index].qcq->intr.index;
 634         ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);
 635
 636         dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
 637         dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
 638         dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 639         dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 640         dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 641         dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
 642         dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 643
 644         q->tail = q->info;
 645         q->head = q->tail;
 646         cq->tail = cq->info;
 647
 648         err = ionic_adminq_post_wait(lif, &ctx);
 649         if (err)
 650                 return err;
 651
 652         q->hw_type = ctx.comp.q_init.hw_type;
 653         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 654         q->dbval = IONIC_DBELL_QID(q->hw_index);
 655
 656         dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
 657         dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
 658
 659         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 660                 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
 661                                NAPI_POLL_WEIGHT);
 662
 663         qcq->flags |= IONIC_QCQ_F_INITED;
 664
 665         return 0;
 666 }
 667
 668 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 669 {
 670         struct device *dev = lif->ionic->dev;
 671         struct ionic_queue *q = &qcq->q;
 672         struct ionic_cq *cq = &qcq->cq;
 673         struct ionic_admin_ctx ctx = {
 674                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 675                 .cmd.q_init = {
 676                         .opcode = IONIC_CMD_Q_INIT,
 677                         .lif_index = cpu_to_le16(lif->index),
 678                         .type = q->type,
 679                         .ver = lif->qtype_info[q->type].version,
 680                         .index = cpu_to_le32(q->index),
 681                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
 682                                              IONIC_QINIT_F_SG),
 683                         .intr_index = cpu_to_le16(cq->bound_intr->index),
 684                         .pid = cpu_to_le16(q->pid),
 685                         .ring_size = ilog2(q->num_descs),
 686                         .ring_base = cpu_to_le64(q->base_pa),
 687                         .cq_ring_base = cpu_to_le64(cq->base_pa),
 688                         .sg_ring_base = cpu_to_le64(q->sg_base_pa),
 689                 },
 690         };
 691         int err;
 692
 693         dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
 694         dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
 695         dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 696         dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 697         dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 698         dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
 699         dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 700
 701         q->tail = q->info;
 702         q->head = q->tail;
 703         cq->tail = cq->info;
 704
 705         err = ionic_adminq_post_wait(lif, &ctx);
 706         if (err)
 707                 return err;
 708
 709         q->hw_type = ctx.comp.q_init.hw_type;
 710         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 711         q->dbval = IONIC_DBELL_QID(q->hw_index);
 712
 713         dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
 714         dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
 715
 716         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 717                 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
 718                                NAPI_POLL_WEIGHT);
 719         else
 720                 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
 721                                NAPI_POLL_WEIGHT);
 722
 723         qcq->flags |= IONIC_QCQ_F_INITED;
 724
 725         return 0;
 726 }
 727
 728 static bool ionic_notifyq_service(struct ionic_cq *cq,
 729                                   struct ionic_cq_info *cq_info)
 730 {
 731         union ionic_notifyq_comp *comp = cq_info->cq_desc;
 732         struct ionic_deferred_work *work;
 733         struct net_device *netdev;
 734         struct ionic_queue *q;
 735         struct ionic_lif *lif;
 736         u64 eid;
 737
 738         q = cq->bound_q;
 739         lif = q->info[0].cb_arg;
 740         netdev = lif->netdev;
 741         eid = le64_to_cpu(comp->event.eid);
 742
 743         /* Have we run out of new completions to process? */
 744         if ((s64)(eid - lif->last_eid) <= 0)
 745                 return false;
 746
 747         lif->last_eid = eid;
 748
 749         dev_dbg(lif->ionic->dev, "notifyq event:\n");
 750         dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
 751                          comp, sizeof(*comp), true);
 752
 753         switch (le16_to_cpu(comp->event.ecode)) {
 754         case IONIC_EVENT_LINK_CHANGE:
 755                 ionic_link_status_check_request(lif);
 756                 break;
 757         case IONIC_EVENT_RESET:
 758                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 759                 if (!work) {
 760                         netdev_err(lif->netdev, "%s OOM\n", __func__);
 761                 } else {
 762                         work->type = IONIC_DW_TYPE_LIF_RESET;
 763                         ionic_lif_deferred_enqueue(&lif->deferred, work);
 764                 }
 765                 break;
 766         default:
 767                 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
 768                             comp->event.ecode, eid);
 769                 break;
 770         }
 771
 772         return true;
 773 }
 774
 775 static int ionic_notifyq_clean(struct ionic_lif *lif, int budget)
 776 {
 777         struct ionic_dev *idev = &lif->ionic->idev;
 778         struct ionic_cq *cq = &lif->notifyqcq->cq;
 779         u32 work_done;
 780
 781         work_done = ionic_cq_service(cq, budget, ionic_notifyq_service,
 782                                      NULL, NULL);
 783         if (work_done)
 784                 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
 785                                    work_done, IONIC_INTR_CRED_RESET_COALESCE);
 786
 787         return work_done;
 788 }
 789
 790 static bool ionic_adminq_service(struct ionic_cq *cq,
 791                                  struct ionic_cq_info *cq_info)
 792 {
 793         struct ionic_admin_comp *comp = cq_info->cq_desc;
 794
 795         if (!color_match(comp->color, cq->done_color))
 796                 return false;
 797
 798         ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
 799
 800         return true;
 801 }
 802
 803 static int ionic_adminq_napi(struct napi_struct *napi, int budget)
 804 {
 805         struct ionic_lif *lif = napi_to_cq(napi)->lif;
 806         int n_work = 0;
 807         int a_work = 0;
 808
 809         if (likely(lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED))
 810                 n_work = ionic_notifyq_clean(lif, budget);
 811         a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL);
 812
 813         return max(n_work, a_work);
 814 }
 815
 816 void ionic_get_stats64(struct net_device *netdev,
 817                        struct rtnl_link_stats64 *ns)
 818 {
 819         struct ionic_lif *lif = netdev_priv(netdev);
 820         struct ionic_lif_stats *ls;
 821
 822         memset(ns, 0, sizeof(*ns));
 823         ls = &lif->info->stats;
 824
 825         ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
 826                          le64_to_cpu(ls->rx_mcast_packets) +
 827                          le64_to_cpu(ls->rx_bcast_packets);
 828
 829         ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
 830                          le64_to_cpu(ls->tx_mcast_packets) +
 831                          le64_to_cpu(ls->tx_bcast_packets);
 832
 833         ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
 834                        le64_to_cpu(ls->rx_mcast_bytes) +
 835                        le64_to_cpu(ls->rx_bcast_bytes);
 836
 837         ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
 838                        le64_to_cpu(ls->tx_mcast_bytes) +
 839                        le64_to_cpu(ls->tx_bcast_bytes);
 840
 841         ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
 842                          le64_to_cpu(ls->rx_mcast_drop_packets) +
 843                          le64_to_cpu(ls->rx_bcast_drop_packets);
 844
 845         ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
 846                          le64_to_cpu(ls->tx_mcast_drop_packets) +
 847                          le64_to_cpu(ls->tx_bcast_drop_packets);
 848
 849         ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
 850
 851         ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
 852
 853         ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
 854                                le64_to_cpu(ls->rx_queue_disabled) +
 855                                le64_to_cpu(ls->rx_desc_fetch_error) +
 856                                le64_to_cpu(ls->rx_desc_data_error);
 857
 858         ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
 859                                 le64_to_cpu(ls->tx_queue_disabled) +
 860                                 le64_to_cpu(ls->tx_desc_fetch_error) +
 861                                 le64_to_cpu(ls->tx_desc_data_error);
 862
 863         ns->rx_errors = ns->rx_over_errors +
 864                         ns->rx_missed_errors;
 865
 866         ns->tx_errors = ns->tx_aborted_errors;
 867 }
 868
 869 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr)
 870 {
 871         struct ionic_admin_ctx ctx = {
 872                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 873                 .cmd.rx_filter_add = {
 874                         .opcode = IONIC_CMD_RX_FILTER_ADD,
 875                         .lif_index = cpu_to_le16(lif->index),
 876                         .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC),
 877                 },
 878         };
 879         struct ionic_rx_filter *f;
 880         int err;
 881
 882         /* don't bother if we already have it */
 883         spin_lock_bh(&lif->rx_filters.lock);
 884         f = ionic_rx_filter_by_addr(lif, addr);
 885         spin_unlock_bh(&lif->rx_filters.lock);
 886         if (f)
 887                 return 0;
 888
 889         netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr);
 890
 891         memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
 892         err = ionic_adminq_post_wait(lif, &ctx);
 893         if (err && err != -EEXIST)
 894                 return err;
 895
 896         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
 897 }
 898
 899 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr)
 900 {
 901         struct ionic_admin_ctx ctx = {
 902                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 903                 .cmd.rx_filter_del = {
 904                         .opcode = IONIC_CMD_RX_FILTER_DEL,
 905                         .lif_index = cpu_to_le16(lif->index),
 906                 },
 907         };
 908         struct ionic_rx_filter *f;
 909         int err;
 910
 911         spin_lock_bh(&lif->rx_filters.lock);
 912         f = ionic_rx_filter_by_addr(lif, addr);
 913         if (!f) {
 914                 spin_unlock_bh(&lif->rx_filters.lock);
 915                 return -ENOENT;
 916         }
 917
 918         netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n",
 919                    addr, f->filter_id);
 920
 921         ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
 922         ionic_rx_filter_free(lif, f);
 923         spin_unlock_bh(&lif->rx_filters.lock);
 924
 925         err = ionic_adminq_post_wait(lif, &ctx);
 926         if (err && err != -EEXIST)
 927                 return err;
 928
 929         return 0;
 930 }
 931
 932 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add)
 933 {
 934         struct ionic *ionic = lif->ionic;
 935         struct ionic_deferred_work *work;
 936         unsigned int nmfilters;
 937         unsigned int nufilters;
 938
 939         if (add) {
 940                 /* Do we have space for this filter?  We test the counters
 941                  * here before checking the need for deferral so that we
 942                  * can return an overflow error to the stack.
 943                  */
 944                 nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters);
 945                 nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters);
 946
 947                 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters))
 948                         lif->nmcast++;
 949                 else if (!is_multicast_ether_addr(addr) &&
 950                          lif->nucast < nufilters)
 951                         lif->nucast++;
 952                 else
 953                         return -ENOSPC;
 954         } else {
 955                 if (is_multicast_ether_addr(addr) && lif->nmcast)
 956                         lif->nmcast--;
 957                 else if (!is_multicast_ether_addr(addr) && lif->nucast)
 958                         lif->nucast--;
 959         }
 960
 961         if (in_interrupt()) {
 962                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 963                 if (!work) {
 964                         netdev_err(lif->netdev, "%s OOM\n", __func__);
 965                         return -ENOMEM;
 966                 }
 967                 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD :
 968                                    IONIC_DW_TYPE_RX_ADDR_DEL;
 969                 memcpy(work->addr, addr, ETH_ALEN);
 970                 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
 971                            add ? "add" : "del", addr);
 972                 ionic_lif_deferred_enqueue(&lif->deferred, work);
 973         } else {
 974                 netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
 975                            add ? "add" : "del", addr);
 976                 if (add)
 977                         return ionic_lif_addr_add(lif, addr);
 978                 else
 979                         return ionic_lif_addr_del(lif, addr);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
 986 {
 987         return ionic_lif_addr(netdev_priv(netdev), addr, true);
 988 }
 989
 990 static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
 991 {
 992         return ionic_lif_addr(netdev_priv(netdev), addr, false);
 993 }
 994
 995 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode)
 996 {
 997         struct ionic_admin_ctx ctx = {
 998                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 999                 .cmd.rx_mode_set = {
1000                         .opcode = IONIC_CMD_RX_MODE_SET,
1001                         .lif_index = cpu_to_le16(lif->index),
1002                         .rx_mode = cpu_to_le16(rx_mode),
1003                 },
1004         };
1005         char buf[128];
1006         int err;
1007         int i;
1008 #define REMAIN(__x) (sizeof(buf) - (__x))
1009
1010         i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1011                       lif->rx_mode, rx_mode);
1012         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1013                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1014         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1015                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1016         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1017                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1018         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1019                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1020         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1021                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1022         netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
1023
1024         err = ionic_adminq_post_wait(lif, &ctx);
1025         if (err)
1026                 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n",
1027                             rx_mode, err);
1028         else
1029                 lif->rx_mode = rx_mode;
1030 }
1031
1032 static void _ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode)
1033 {
1034         struct ionic_deferred_work *work;
1035
1036         if (in_interrupt()) {
1037                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1038                 if (!work) {
1039                         netdev_err(lif->netdev, "%s OOM\n", __func__);
1040                         return;
1041                 }
1042                 work->type = IONIC_DW_TYPE_RX_MODE;
1043                 work->rx_mode = rx_mode;
1044                 netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1045                 ionic_lif_deferred_enqueue(&lif->deferred, work);
1046         } else {
1047                 ionic_lif_rx_mode(lif, rx_mode);
1048         }
1049 }
1050
1051 static void ionic_set_rx_mode(struct net_device *netdev)
1052 {
1053         struct ionic_lif *lif = netdev_priv(netdev);
1054         struct ionic_identity *ident;
1055         unsigned int nfilters;
1056         unsigned int rx_mode;
1057
1058         ident = &lif->ionic->ident;
1059
1060         rx_mode = IONIC_RX_MODE_F_UNICAST;
1061         rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1062         rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1063         rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1064         rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1065
1066         /* sync unicast addresses
1067          * next check to see if we're in an overflow state
1068          *    if so, we track that we overflowed and enable NIC PROMISC
1069          *    else if the overflow is set and not needed
1070          *       we remove our overflow flag and check the netdev flags
1071          *       to see if we can disable NIC PROMISC
1072          */
1073         __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1074         nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters);
1075         if (netdev_uc_count(netdev) + 1 > nfilters) {
1076                 rx_mode |= IONIC_RX_MODE_F_PROMISC;
1077                 lif->uc_overflow = true;
1078         } else if (lif->uc_overflow) {
1079                 lif->uc_overflow = false;
1080                 if (!(netdev->flags & IFF_PROMISC))
1081                         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1082         }
1083
1084         /* same for multicast */
1085         __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1086         nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters);
1087         if (netdev_mc_count(netdev) > nfilters) {
1088                 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1089                 lif->mc_overflow = true;
1090         } else if (lif->mc_overflow) {
1091                 lif->mc_overflow = false;
1092                 if (!(netdev->flags & IFF_ALLMULTI))
1093                         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1094         }
1095
1096         if (lif->rx_mode != rx_mode)
1097                 _ionic_lif_rx_mode(lif, rx_mode);
1098 }
1099
1100 static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1101 {
1102         u64 wanted = 0;
1103
1104         if (features & NETIF_F_HW_VLAN_CTAG_TX)
1105                 wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1106         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1107                 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1108         if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1109                 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1110         if (features & NETIF_F_RXHASH)
1111                 wanted |= IONIC_ETH_HW_RX_HASH;
1112         if (features & NETIF_F_RXCSUM)
1113                 wanted |= IONIC_ETH_HW_RX_CSUM;
1114         if (features & NETIF_F_SG)
1115                 wanted |= IONIC_ETH_HW_TX_SG;
1116         if (features & NETIF_F_HW_CSUM)
1117                 wanted |= IONIC_ETH_HW_TX_CSUM;
1118         if (features & NETIF_F_TSO)
1119                 wanted |= IONIC_ETH_HW_TSO;
1120         if (features & NETIF_F_TSO6)
1121                 wanted |= IONIC_ETH_HW_TSO_IPV6;
1122         if (features & NETIF_F_TSO_ECN)
1123                 wanted |= IONIC_ETH_HW_TSO_ECN;
1124         if (features & NETIF_F_GSO_GRE)
1125                 wanted |= IONIC_ETH_HW_TSO_GRE;
1126         if (features & NETIF_F_GSO_GRE_CSUM)
1127                 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1128         if (features & NETIF_F_GSO_IPXIP4)
1129                 wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1130         if (features & NETIF_F_GSO_IPXIP6)
1131                 wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1132         if (features & NETIF_F_GSO_UDP_TUNNEL)
1133                 wanted |= IONIC_ETH_HW_TSO_UDP;
1134         if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1135                 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1136
1137         return cpu_to_le64(wanted);
1138 }
1139
1140 static int ionic_set_nic_features(struct ionic_lif *lif,
1141                                   netdev_features_t features)
1142 {
1143         struct device *dev = lif->ionic->dev;
1144         struct ionic_admin_ctx ctx = {
1145                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1146                 .cmd.lif_setattr = {
1147                         .opcode = IONIC_CMD_LIF_SETATTR,
1148                         .index = cpu_to_le16(lif->index),
1149                         .attr = IONIC_LIF_ATTR_FEATURES,
1150                 },
1151         };
1152         u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1153                          IONIC_ETH_HW_VLAN_RX_STRIP |
1154                          IONIC_ETH_HW_VLAN_RX_FILTER;
1155         u64 old_hw_features;
1156         int err;
1157
1158         ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
1159         err = ionic_adminq_post_wait(lif, &ctx);
1160         if (err)
1161                 return err;
1162
1163         old_hw_features = lif->hw_features;
1164         lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1165                                        ctx.comp.lif_setattr.features);
1166
1167         if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1168                 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1169
1170         if ((vlan_flags & features) &&
1171             !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1172                 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1173
1174         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1175                 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1176         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1177                 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1178         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1179                 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1180         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1181                 dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1182         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1183                 dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1184         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1185                 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1186         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1187                 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1188         if (lif->hw_features & IONIC_ETH_HW_TSO)
1189                 dev_dbg(dev, "feature ETH_HW_TSO\n");
1190         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1191                 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1192         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1193                 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1194         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1195                 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1196         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1197                 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1198         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1199                 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1200         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1201                 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1202         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1203                 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1204         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1205                 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
1206
1207         return 0;
1208 }
1209
1210 static int ionic_init_nic_features(struct ionic_lif *lif)
1211 {
1212         struct net_device *netdev = lif->netdev;
1213         netdev_features_t features;
1214         int err;
1215
1216         /* set up what we expect to support by default */
1217         features = NETIF_F_HW_VLAN_CTAG_TX |
1218                    NETIF_F_HW_VLAN_CTAG_RX |
1219                    NETIF_F_HW_VLAN_CTAG_FILTER |
1220                    NETIF_F_RXHASH |
1221                    NETIF_F_SG |
1222                    NETIF_F_HW_CSUM |
1223                    NETIF_F_RXCSUM |
1224                    NETIF_F_TSO |
1225                    NETIF_F_TSO6 |
1226                    NETIF_F_TSO_ECN;
1227
1228         err = ionic_set_nic_features(lif, features);
1229         if (err)
1230                 return err;
1231
1232         /* tell the netdev what we actually can support */
1233         netdev->features |= NETIF_F_HIGHDMA;
1234
1235         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1236                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1237         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1238                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1239         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1240                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1241         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1242                 netdev->hw_features |= NETIF_F_RXHASH;
1243         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1244                 netdev->hw_features |= NETIF_F_SG;
1245
1246         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1247                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1248         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1249                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
1250         if (lif->hw_features & IONIC_ETH_HW_TSO)
1251                 netdev->hw_enc_features |= NETIF_F_TSO;
1252         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1253                 netdev->hw_enc_features |= NETIF_F_TSO6;
1254         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1255                 netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1256         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1257                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1258         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1259                 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1260         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1261                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1262         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1263                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1264         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1265                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1266         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1267                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1268
1269         netdev->hw_features |= netdev->hw_enc_features;
1270         netdev->features |= netdev->hw_features;
1271         netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
1272
1273         netdev->priv_flags |= IFF_UNICAST_FLT |
1274                               IFF_LIVE_ADDR_CHANGE;
1275
1276         return 0;
1277 }
1278
1279 static int ionic_set_features(struct net_device *netdev,
1280                               netdev_features_t features)
1281 {
1282         struct ionic_lif *lif = netdev_priv(netdev);
1283         int err;
1284
1285         netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1286                    __func__, (u64)lif->netdev->features, (u64)features);
1287
1288         err = ionic_set_nic_features(lif, features);
1289
1290         return err;
1291 }
1292
1293 static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1294 {
1295         struct sockaddr *addr = sa;
1296         u8 *mac;
1297         int err;
1298
1299         mac = (u8 *)addr->sa_data;
1300         if (ether_addr_equal(netdev->dev_addr, mac))
1301                 return 0;
1302
1303         err = eth_prepare_mac_addr_change(netdev, addr);
1304         if (err)
1305                 return err;
1306
1307         if (!is_zero_ether_addr(netdev->dev_addr)) {
1308                 netdev_info(netdev, "deleting mac addr %pM\n",
1309                             netdev->dev_addr);
1310                 ionic_addr_del(netdev, netdev->dev_addr);
1311         }
1312
1313         eth_commit_mac_addr_change(netdev, addr);
1314         netdev_info(netdev, "updating mac addr %pM\n", mac);
1315
1316         return ionic_addr_add(netdev, mac);
1317 }
1318
1319 static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1320 {
1321         struct ionic_lif *lif = netdev_priv(netdev);
1322         struct ionic_admin_ctx ctx = {
1323                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1324                 .cmd.lif_setattr = {
1325                         .opcode = IONIC_CMD_LIF_SETATTR,
1326                         .index = cpu_to_le16(lif->index),
1327                         .attr = IONIC_LIF_ATTR_MTU,
1328                         .mtu = cpu_to_le32(new_mtu),
1329                 },
1330         };
1331         int err;
1332
1333         err = ionic_adminq_post_wait(lif, &ctx);
1334         if (err)
1335                 return err;
1336
1337         netdev->mtu = new_mtu;
1338         err = ionic_reset_queues(lif, NULL, NULL);
1339
1340         return err;
1341 }
1342
1343 static void ionic_tx_timeout_work(struct work_struct *ws)
1344 {
1345         struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1346
1347         netdev_info(lif->netdev, "Tx Timeout recovery\n");
1348
1349         rtnl_lock();
1350         ionic_reset_queues(lif, NULL, NULL);
1351         rtnl_unlock();
1352 }
1353
1354 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1355 {
1356         struct ionic_lif *lif = netdev_priv(netdev);
1357
1358         schedule_work(&lif->tx_timeout_work);
1359 }
1360
1361 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1362                                  u16 vid)
1363 {
1364         struct ionic_lif *lif = netdev_priv(netdev);
1365         struct ionic_admin_ctx ctx = {
1366                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1367                 .cmd.rx_filter_add = {
1368                         .opcode = IONIC_CMD_RX_FILTER_ADD,
1369                         .lif_index = cpu_to_le16(lif->index),
1370                         .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN),
1371                         .vlan.vlan = cpu_to_le16(vid),
1372                 },
1373         };
1374         int err;
1375
1376         netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid);
1377         err = ionic_adminq_post_wait(lif, &ctx);
1378         if (err)
1379                 return err;
1380
1381         return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
1382 }
1383
1384 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1385                                   u16 vid)
1386 {
1387         struct ionic_lif *lif = netdev_priv(netdev);
1388         struct ionic_admin_ctx ctx = {
1389                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1390                 .cmd.rx_filter_del = {
1391                         .opcode = IONIC_CMD_RX_FILTER_DEL,
1392                         .lif_index = cpu_to_le16(lif->index),
1393                 },
1394         };
1395         struct ionic_rx_filter *f;
1396
1397         spin_lock_bh(&lif->rx_filters.lock);
1398
1399         f = ionic_rx_filter_by_vlan(lif, vid);
1400         if (!f) {
1401                 spin_unlock_bh(&lif->rx_filters.lock);
1402                 return -ENOENT;
1403         }
1404
1405         netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n",
1406                    vid, f->filter_id);
1407
1408         ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
1409         ionic_rx_filter_free(lif, f);
1410         spin_unlock_bh(&lif->rx_filters.lock);
1411
1412         return ionic_adminq_post_wait(lif, &ctx);
1413 }
1414
1415 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1416                          const u8 *key, const u32 *indir)
1417 {
1418         struct ionic_admin_ctx ctx = {
1419                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1420                 .cmd.lif_setattr = {
1421                         .opcode = IONIC_CMD_LIF_SETATTR,
1422                         .attr = IONIC_LIF_ATTR_RSS,
1423                         .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1424                 },
1425         };
1426         unsigned int i, tbl_sz;
1427
1428         if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1429                 lif->rss_types = types;
1430                 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1431         }
1432
1433         if (key)
1434                 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1435
1436         if (indir) {
1437                 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1438                 for (i = 0; i < tbl_sz; i++)
1439                         lif->rss_ind_tbl[i] = indir[i];
1440         }
1441
1442         memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1443                IONIC_RSS_HASH_KEY_SIZE);
1444
1445         return ionic_adminq_post_wait(lif, &ctx);
1446 }
1447
1448 static int ionic_lif_rss_init(struct ionic_lif *lif)
1449 {
1450         unsigned int tbl_sz;
1451         unsigned int i;
1452
1453         lif->rss_types = IONIC_RSS_TYPE_IPV4     |
1454                          IONIC_RSS_TYPE_IPV4_TCP |
1455                          IONIC_RSS_TYPE_IPV4_UDP |
1456                          IONIC_RSS_TYPE_IPV6     |
1457                          IONIC_RSS_TYPE_IPV6_TCP |
1458                          IONIC_RSS_TYPE_IPV6_UDP;
1459
1460         /* Fill indirection table with 'default' values */
1461         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1462         for (i = 0; i < tbl_sz; i++)
1463                 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1464
1465         return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1466 }
1467
1468 static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1469 {
1470         int tbl_sz;
1471
1472         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1473         memset(lif->rss_ind_tbl, 0, tbl_sz);
1474         memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1475
1476         ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1477 }
1478
1479 static void ionic_txrx_disable(struct ionic_lif *lif)
1480 {
1481         unsigned int i;
1482         int err;
1483
1484         if (lif->txqcqs) {
1485                 for (i = 0; i < lif->nxqs; i++) {
1486                         err = ionic_qcq_disable(lif->txqcqs[i].qcq);
1487                         if (err == -ETIMEDOUT)
1488                                 break;
1489                 }
1490         }
1491
1492         if (lif->rxqcqs) {
1493                 for (i = 0; i < lif->nxqs; i++) {
1494                         err = ionic_qcq_disable(lif->rxqcqs[i].qcq);
1495                         if (err == -ETIMEDOUT)
1496                                 break;
1497                 }
1498         }
1499 }
1500
1501 static void ionic_txrx_deinit(struct ionic_lif *lif)
1502 {
1503         unsigned int i;
1504
1505         if (lif->txqcqs) {
1506                 for (i = 0; i < lif->nxqs; i++) {
1507                         ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq);
1508                         ionic_tx_flush(&lif->txqcqs[i].qcq->cq);
1509                         ionic_tx_empty(&lif->txqcqs[i].qcq->q);
1510                 }
1511         }
1512
1513         if (lif->rxqcqs) {
1514                 for (i = 0; i < lif->nxqs; i++) {
1515                         ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq);
1516                         ionic_rx_flush(&lif->rxqcqs[i].qcq->cq);
1517                         ionic_rx_empty(&lif->rxqcqs[i].qcq->q);
1518                 }
1519         }
1520         lif->rx_mode = 0;
1521 }
1522
1523 static void ionic_txrx_free(struct ionic_lif *lif)
1524 {
1525         unsigned int i;
1526
1527         if (lif->txqcqs) {
1528                 for (i = 0; i < lif->nxqs; i++) {
1529                         ionic_qcq_free(lif, lif->txqcqs[i].qcq);
1530                         lif->txqcqs[i].qcq = NULL;
1531                 }
1532         }
1533
1534         if (lif->rxqcqs) {
1535                 for (i = 0; i < lif->nxqs; i++) {
1536                         ionic_qcq_free(lif, lif->rxqcqs[i].qcq);
1537                         lif->rxqcqs[i].qcq = NULL;
1538                 }
1539         }
1540 }
1541
1542 static int ionic_txrx_alloc(struct ionic_lif *lif)
1543 {
1544         unsigned int sg_desc_sz;
1545         unsigned int flags;
1546         unsigned int i;
1547         int err = 0;
1548
1549         if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
1550             lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
1551                                           sizeof(struct ionic_txq_sg_desc_v1))
1552                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
1553         else
1554                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
1555
1556         flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
1557         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1558                 flags |= IONIC_QCQ_F_INTR;
1559         for (i = 0; i < lif->nxqs; i++) {
1560                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
1561                                       lif->ntxq_descs,
1562                                       sizeof(struct ionic_txq_desc),
1563                                       sizeof(struct ionic_txq_comp),
1564                                       sg_desc_sz,
1565                                       lif->kern_pid, &lif->txqcqs[i].qcq);
1566                 if (err)
1567                         goto err_out;
1568
1569                 if (flags & IONIC_QCQ_F_INTR)
1570                         ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1571                                              lif->txqcqs[i].qcq->intr.index,
1572                                              lif->tx_coalesce_hw);
1573
1574                 lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats;
1575                 ionic_debugfs_add_qcq(lif, lif->txqcqs[i].qcq);
1576         }
1577
1578         flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
1579         for (i = 0; i < lif->nxqs; i++) {
1580                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
1581                                       lif->nrxq_descs,
1582                                       sizeof(struct ionic_rxq_desc),
1583                                       sizeof(struct ionic_rxq_comp),
1584                                       sizeof(struct ionic_rxq_sg_desc),
1585                                       lif->kern_pid, &lif->rxqcqs[i].qcq);
1586                 if (err)
1587                         goto err_out;
1588
1589                 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1590                                      lif->rxqcqs[i].qcq->intr.index,
1591                                      lif->rx_coalesce_hw);
1592
1593                 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1594                         ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq,
1595                                                   lif->txqcqs[i].qcq);
1596
1597                 lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats;
1598                 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i].qcq);
1599         }
1600
1601         return 0;
1602
1603 err_out:
1604         ionic_txrx_free(lif);
1605
1606         return err;
1607 }
1608
1609 static int ionic_txrx_init(struct ionic_lif *lif)
1610 {
1611         unsigned int i;
1612         int err;
1613
1614         for (i = 0; i < lif->nxqs; i++) {
1615                 err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq);
1616                 if (err)
1617                         goto err_out;
1618
1619                 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq);
1620                 if (err) {
1621                         ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq);
1622                         goto err_out;
1623                 }
1624         }
1625
1626         if (lif->netdev->features & NETIF_F_RXHASH)
1627                 ionic_lif_rss_init(lif);
1628
1629         ionic_set_rx_mode(lif->netdev);
1630
1631         return 0;
1632
1633 err_out:
1634         while (i--) {
1635                 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq);
1636                 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq);
1637         }
1638
1639         return err;
1640 }
1641
1642 static int ionic_txrx_enable(struct ionic_lif *lif)
1643 {
1644         int i, err;
1645
1646         for (i = 0; i < lif->nxqs; i++) {
1647                 ionic_rx_fill(&lif->rxqcqs[i].qcq->q);
1648                 err = ionic_qcq_enable(lif->rxqcqs[i].qcq);
1649                 if (err)
1650                         goto err_out;
1651
1652                 err = ionic_qcq_enable(lif->txqcqs[i].qcq);
1653                 if (err) {
1654                         if (err != -ETIMEDOUT)
1655                                 ionic_qcq_disable(lif->rxqcqs[i].qcq);
1656                         goto err_out;
1657                 }
1658         }
1659
1660         return 0;
1661
1662 err_out:
1663         while (i--) {
1664                 err = ionic_qcq_disable(lif->txqcqs[i].qcq);
1665                 if (err == -ETIMEDOUT)
1666                         break;
1667                 err = ionic_qcq_disable(lif->rxqcqs[i].qcq);
1668                 if (err == -ETIMEDOUT)
1669                         break;
1670         }
1671
1672         return err;
1673 }
1674
1675 static int ionic_start_queues(struct ionic_lif *lif)
1676 {
1677         int err;
1678
1679         if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
1680                 return 0;
1681
1682         err = ionic_txrx_enable(lif);
1683         if (err) {
1684                 clear_bit(IONIC_LIF_F_UP, lif->state);
1685                 return err;
1686         }
1687         netif_tx_wake_all_queues(lif->netdev);
1688
1689         return 0;
1690 }
1691
1692 int ionic_open(struct net_device *netdev)
1693 {
1694         struct ionic_lif *lif = netdev_priv(netdev);
1695         int err;
1696
1697         err = ionic_txrx_alloc(lif);
1698         if (err)
1699                 return err;
1700
1701         err = ionic_txrx_init(lif);
1702         if (err)
1703                 goto err_out;
1704
1705         err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
1706         if (err)
1707                 goto err_txrx_deinit;
1708
1709         err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
1710         if (err)
1711                 goto err_txrx_deinit;
1712
1713         /* don't start the queues until we have link */
1714         if (netif_carrier_ok(netdev)) {
1715                 err = ionic_start_queues(lif);
1716                 if (err)
1717                         goto err_txrx_deinit;
1718         }
1719
1720         return 0;
1721
1722 err_txrx_deinit:
1723         ionic_txrx_deinit(lif);
1724 err_out:
1725         ionic_txrx_free(lif);
1726         return err;
1727 }
1728
1729 static void ionic_stop_queues(struct ionic_lif *lif)
1730 {
1731         if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
1732                 return;
1733
1734         netif_tx_disable(lif->netdev);
1735         ionic_txrx_disable(lif);
1736 }
1737
1738 int ionic_stop(struct net_device *netdev)
1739 {
1740         struct ionic_lif *lif = netdev_priv(netdev);
1741
1742         if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1743                 return 0;
1744
1745         ionic_stop_queues(lif);
1746         ionic_txrx_deinit(lif);
1747         ionic_txrx_free(lif);
1748
1749         return 0;
1750 }
1751
1752 static int ionic_get_vf_config(struct net_device *netdev,
1753                                int vf, struct ifla_vf_info *ivf)
1754 {
1755         struct ionic_lif *lif = netdev_priv(netdev);
1756         struct ionic *ionic = lif->ionic;
1757         int ret = 0;
1758
1759         if (!netif_device_present(netdev))
1760                 return -EBUSY;
1761
1762         down_read(&ionic->vf_op_lock);
1763
1764         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1765                 ret = -EINVAL;
1766         } else {
1767                 ivf->vf           = vf;
1768                 ivf->vlan         = ionic->vfs[vf].vlanid;
1769                 ivf->qos          = 0;
1770                 ivf->spoofchk     = ionic->vfs[vf].spoofchk;
1771                 ivf->linkstate    = ionic->vfs[vf].linkstate;
1772                 ivf->max_tx_rate  = ionic->vfs[vf].maxrate;
1773                 ivf->trusted      = ionic->vfs[vf].trusted;
1774                 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr);
1775         }
1776
1777         up_read(&ionic->vf_op_lock);
1778         return ret;
1779 }
1780
1781 static int ionic_get_vf_stats(struct net_device *netdev, int vf,
1782                               struct ifla_vf_stats *vf_stats)
1783 {
1784         struct ionic_lif *lif = netdev_priv(netdev);
1785         struct ionic *ionic = lif->ionic;
1786         struct ionic_lif_stats *vs;
1787         int ret = 0;
1788
1789         if (!netif_device_present(netdev))
1790                 return -EBUSY;
1791
1792         down_read(&ionic->vf_op_lock);
1793
1794         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1795                 ret = -EINVAL;
1796         } else {
1797                 memset(vf_stats, 0, sizeof(*vf_stats));
1798                 vs = &ionic->vfs[vf].stats;
1799
1800                 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
1801                 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
1802                 vf_stats->rx_bytes   = le64_to_cpu(vs->rx_ucast_bytes);
1803                 vf_stats->tx_bytes   = le64_to_cpu(vs->tx_ucast_bytes);
1804                 vf_stats->broadcast  = le64_to_cpu(vs->rx_bcast_packets);
1805                 vf_stats->multicast  = le64_to_cpu(vs->rx_mcast_packets);
1806                 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
1807                                        le64_to_cpu(vs->rx_mcast_drop_packets) +
1808                                        le64_to_cpu(vs->rx_bcast_drop_packets);
1809                 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
1810                                        le64_to_cpu(vs->tx_mcast_drop_packets) +
1811                                        le64_to_cpu(vs->tx_bcast_drop_packets);
1812         }
1813
1814         up_read(&ionic->vf_op_lock);
1815         return ret;
1816 }
1817
1818 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
1819 {
1820         struct ionic_lif *lif = netdev_priv(netdev);
1821         struct ionic *ionic = lif->ionic;
1822         int ret;
1823
1824         if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
1825                 return -EINVAL;
1826
1827         if (!netif_device_present(netdev))
1828                 return -EBUSY;
1829
1830         down_write(&ionic->vf_op_lock);
1831
1832         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1833                 ret = -EINVAL;
1834         } else {
1835                 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac);
1836                 if (!ret)
1837                         ether_addr_copy(ionic->vfs[vf].macaddr, mac);
1838         }
1839
1840         up_write(&ionic->vf_op_lock);
1841         return ret;
1842 }
1843
1844 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1845                              u8 qos, __be16 proto)
1846 {
1847         struct ionic_lif *lif = netdev_priv(netdev);
1848         struct ionic *ionic = lif->ionic;
1849         int ret;
1850
1851         /* until someday when we support qos */
1852         if (qos)
1853                 return -EINVAL;
1854
1855         if (vlan > 4095)
1856                 return -EINVAL;
1857
1858         if (proto != htons(ETH_P_8021Q))
1859                 return -EPROTONOSUPPORT;
1860
1861         if (!netif_device_present(netdev))
1862                 return -EBUSY;
1863
1864         down_write(&ionic->vf_op_lock);
1865
1866         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1867                 ret = -EINVAL;
1868         } else {
1869                 ret = ionic_set_vf_config(ionic, vf,
1870                                           IONIC_VF_ATTR_VLAN, (u8 *)&vlan);
1871                 if (!ret)
1872                         ionic->vfs[vf].vlanid = vlan;
1873         }
1874
1875         up_write(&ionic->vf_op_lock);
1876         return ret;
1877 }
1878
1879 static int ionic_set_vf_rate(struct net_device *netdev, int vf,
1880                              int tx_min, int tx_max)
1881 {
1882         struct ionic_lif *lif = netdev_priv(netdev);
1883         struct ionic *ionic = lif->ionic;
1884         int ret;
1885
1886         /* setting the min just seems silly */
1887         if (tx_min)
1888                 return -EINVAL;
1889
1890         if (!netif_device_present(netdev))
1891                 return -EBUSY;
1892
1893         down_write(&ionic->vf_op_lock);
1894
1895         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1896                 ret = -EINVAL;
1897         } else {
1898                 ret = ionic_set_vf_config(ionic, vf,
1899                                           IONIC_VF_ATTR_RATE, (u8 *)&tx_max);
1900                 if (!ret)
1901                         lif->ionic->vfs[vf].maxrate = tx_max;
1902         }
1903
1904         up_write(&ionic->vf_op_lock);
1905         return ret;
1906 }
1907
1908 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
1909 {
1910         struct ionic_lif *lif = netdev_priv(netdev);
1911         struct ionic *ionic = lif->ionic;
1912         u8 data = set;  /* convert to u8 for config */
1913         int ret;
1914
1915         if (!netif_device_present(netdev))
1916                 return -EBUSY;
1917
1918         down_write(&ionic->vf_op_lock);
1919
1920         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1921                 ret = -EINVAL;
1922         } else {
1923                 ret = ionic_set_vf_config(ionic, vf,
1924                                           IONIC_VF_ATTR_SPOOFCHK, &data);
1925                 if (!ret)
1926                         ionic->vfs[vf].spoofchk = data;
1927         }
1928
1929         up_write(&ionic->vf_op_lock);
1930         return ret;
1931 }
1932
1933 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
1934 {
1935         struct ionic_lif *lif = netdev_priv(netdev);
1936         struct ionic *ionic = lif->ionic;
1937         u8 data = set;  /* convert to u8 for config */
1938         int ret;
1939
1940         if (!netif_device_present(netdev))
1941                 return -EBUSY;
1942
1943         down_write(&ionic->vf_op_lock);
1944
1945         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1946                 ret = -EINVAL;
1947         } else {
1948                 ret = ionic_set_vf_config(ionic, vf,
1949                                           IONIC_VF_ATTR_TRUST, &data);
1950                 if (!ret)
1951                         ionic->vfs[vf].trusted = data;
1952         }
1953
1954         up_write(&ionic->vf_op_lock);
1955         return ret;
1956 }
1957
1958 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
1959 {
1960         struct ionic_lif *lif = netdev_priv(netdev);
1961         struct ionic *ionic = lif->ionic;
1962         u8 data;
1963         int ret;
1964
1965         switch (set) {
1966         case IFLA_VF_LINK_STATE_ENABLE:
1967                 data = IONIC_VF_LINK_STATUS_UP;
1968                 break;
1969         case IFLA_VF_LINK_STATE_DISABLE:
1970                 data = IONIC_VF_LINK_STATUS_DOWN;
1971                 break;
1972         case IFLA_VF_LINK_STATE_AUTO:
1973                 data = IONIC_VF_LINK_STATUS_AUTO;
1974                 break;
1975         default:
1976                 return -EINVAL;
1977         }
1978
1979         if (!netif_device_present(netdev))
1980                 return -EBUSY;
1981
1982         down_write(&ionic->vf_op_lock);
1983
1984         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1985                 ret = -EINVAL;
1986         } else {
1987                 ret = ionic_set_vf_config(ionic, vf,
1988                                           IONIC_VF_ATTR_LINKSTATE, &data);
1989                 if (!ret)
1990                         ionic->vfs[vf].linkstate = set;
1991         }
1992
1993         up_write(&ionic->vf_op_lock);
1994         return ret;
1995 }
1996
1997 static const struct net_device_ops ionic_netdev_ops = {
1998         .ndo_open               = ionic_open,
1999         .ndo_stop               = ionic_stop,
2000         .ndo_start_xmit         = ionic_start_xmit,
2001         .ndo_get_stats64        = ionic_get_stats64,
2002         .ndo_set_rx_mode        = ionic_set_rx_mode,
2003         .ndo_set_features       = ionic_set_features,
2004         .ndo_set_mac_address    = ionic_set_mac_address,
2005         .ndo_validate_addr      = eth_validate_addr,
2006         .ndo_tx_timeout         = ionic_tx_timeout,
2007         .ndo_change_mtu         = ionic_change_mtu,
2008         .ndo_vlan_rx_add_vid    = ionic_vlan_rx_add_vid,
2009         .ndo_vlan_rx_kill_vid   = ionic_vlan_rx_kill_vid,
2010         .ndo_set_vf_vlan        = ionic_set_vf_vlan,
2011         .ndo_set_vf_trust       = ionic_set_vf_trust,
2012         .ndo_set_vf_mac         = ionic_set_vf_mac,
2013         .ndo_set_vf_rate        = ionic_set_vf_rate,
2014         .ndo_set_vf_spoofchk    = ionic_set_vf_spoofchk,
2015         .ndo_get_vf_config      = ionic_get_vf_config,
2016         .ndo_set_vf_link_state  = ionic_set_vf_link_state,
2017         .ndo_get_vf_stats       = ionic_get_vf_stats,
2018 };
2019
2020 int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg)
2021 {
2022         bool running;
2023         int err = 0;
2024
2025         mutex_lock(&lif->queue_lock);
2026         running = netif_running(lif->netdev);
2027         if (running) {
2028                 netif_device_detach(lif->netdev);
2029                 err = ionic_stop(lif->netdev);
2030                 if (err)
2031                         goto reset_out;
2032         }
2033
2034         if (cb)
2035                 cb(lif, arg);
2036
2037         if (running) {
2038                 err = ionic_open(lif->netdev);
2039                 netif_device_attach(lif->netdev);
2040         }
2041
2042 reset_out:
2043         mutex_unlock(&lif->queue_lock);
2044
2045         return err;
2046 }
2047
2048 int ionic_lif_alloc(struct ionic *ionic)
2049 {
2050         struct device *dev = ionic->dev;
2051         union ionic_lif_identity *lid;
2052         struct net_device *netdev;
2053         struct ionic_lif *lif;
2054         int tbl_sz;
2055         int err;
2056
2057         lid = kzalloc(sizeof(*lid), GFP_KERNEL);
2058         if (!lid)
2059                 return -ENOMEM;
2060
2061         netdev = alloc_etherdev_mqs(sizeof(*lif),
2062                                     ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
2063         if (!netdev) {
2064                 dev_err(dev, "Cannot allocate netdev, aborting\n");
2065                 err = -ENOMEM;
2066                 goto err_out_free_lid;
2067         }
2068
2069         SET_NETDEV_DEV(netdev, dev);
2070
2071         lif = netdev_priv(netdev);
2072         lif->netdev = netdev;
2073         ionic->lif = lif;
2074         netdev->netdev_ops = &ionic_netdev_ops;
2075         ionic_ethtool_set_ops(netdev);
2076
2077         netdev->watchdog_timeo = 2 * HZ;
2078         netif_carrier_off(netdev);
2079
2080         lif->identity = lid;
2081         lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
2082         ionic_lif_identify(ionic, lif->lif_type, lif->identity);
2083         lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
2084                                      le32_to_cpu(lif->identity->eth.min_frame_size));
2085         lif->netdev->max_mtu =
2086                 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN;
2087
2088         lif->neqs = ionic->neqs_per_lif;
2089         lif->nxqs = ionic->ntxqs_per_lif;
2090
2091         lif->ionic = ionic;
2092         lif->index = 0;
2093         lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
2094         lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
2095         lif->tx_budget = IONIC_TX_BUDGET_DEFAULT;
2096
2097         /* Convert the default coalesce value to actual hw resolution */
2098         lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
2099         lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
2100                                                     lif->rx_coalesce_usecs);
2101         lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2102         lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2103
2104         snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
2105
2106         spin_lock_init(&lif->adminq_lock);
2107
2108         spin_lock_init(&lif->deferred.lock);
2109         INIT_LIST_HEAD(&lif->deferred.list);
2110         INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
2111
2112         /* allocate lif info */
2113         lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
2114         lif->info = dma_alloc_coherent(dev, lif->info_sz,
2115                                        &lif->info_pa, GFP_KERNEL);
2116         if (!lif->info) {
2117                 dev_err(dev, "Failed to allocate lif info, aborting\n");
2118                 err = -ENOMEM;
2119                 goto err_out_free_netdev;
2120         }
2121
2122         ionic_debugfs_add_lif(lif);
2123
2124         /* allocate control queues and txrx queue arrays */
2125         ionic_lif_queue_identify(lif);
2126         err = ionic_qcqs_alloc(lif);
2127         if (err)
2128                 goto err_out_free_lif_info;
2129
2130         /* allocate rss indirection table */
2131         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
2132         lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
2133         lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
2134                                               &lif->rss_ind_tbl_pa,
2135                                               GFP_KERNEL);
2136
2137         if (!lif->rss_ind_tbl) {
2138                 err = -ENOMEM;
2139                 dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
2140                 goto err_out_free_qcqs;
2141         }
2142         netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
2143
2144         return 0;
2145
2146 err_out_free_qcqs:
2147         ionic_qcqs_free(lif);
2148 err_out_free_lif_info:
2149         dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2150         lif->info = NULL;
2151         lif->info_pa = 0;
2152 err_out_free_netdev:
2153         free_netdev(lif->netdev);
2154         lif = NULL;
2155 err_out_free_lid:
2156         kfree(lid);
2157
2158         return err;
2159 }
2160
2161 static void ionic_lif_reset(struct ionic_lif *lif)
2162 {
2163         struct ionic_dev *idev = &lif->ionic->idev;
2164
2165         mutex_lock(&lif->ionic->dev_cmd_lock);
2166         ionic_dev_cmd_lif_reset(idev, lif->index);
2167         ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2168         mutex_unlock(&lif->ionic->dev_cmd_lock);
2169 }
2170
2171 static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
2172 {
2173         struct ionic *ionic = lif->ionic;
2174
2175         if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
2176                 return;
2177
2178         dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
2179
2180         netif_device_detach(lif->netdev);
2181
2182         if (test_bit(IONIC_LIF_F_UP, lif->state)) {
2183                 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
2184                 mutex_lock(&lif->queue_lock);
2185                 ionic_stop_queues(lif);
2186                 mutex_unlock(&lif->queue_lock);
2187         }
2188
2189         if (netif_running(lif->netdev)) {
2190                 ionic_txrx_deinit(lif);
2191                 ionic_txrx_free(lif);
2192         }
2193         ionic_lif_deinit(lif);
2194         ionic_reset(ionic);
2195         ionic_qcqs_free(lif);
2196
2197         dev_info(ionic->dev, "FW Down: LIFs stopped\n");
2198 }
2199
2200 static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
2201 {
2202         struct ionic *ionic = lif->ionic;
2203         int err;
2204
2205         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2206                 return;
2207
2208         dev_info(ionic->dev, "FW Up: restarting LIFs\n");
2209
2210         ionic_init_devinfo(ionic);
2211         ionic_port_init(ionic);
2212         err = ionic_qcqs_alloc(lif);
2213         if (err)
2214                 goto err_out;
2215
2216         err = ionic_lif_init(lif);
2217         if (err)
2218                 goto err_qcqs_free;
2219
2220         if (lif->registered)
2221                 ionic_lif_set_netdev_info(lif);
2222
2223         ionic_rx_filter_replay(lif);
2224
2225         if (netif_running(lif->netdev)) {
2226                 err = ionic_txrx_alloc(lif);
2227                 if (err)
2228                         goto err_lifs_deinit;
2229
2230                 err = ionic_txrx_init(lif);
2231                 if (err)
2232                         goto err_txrx_free;
2233         }
2234
2235         clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
2236         ionic_link_status_check_request(lif);
2237         netif_device_attach(lif->netdev);
2238         dev_info(ionic->dev, "FW Up: LIFs restarted\n");
2239
2240         return;
2241
2242 err_txrx_free:
2243         ionic_txrx_free(lif);
2244 err_lifs_deinit:
2245         ionic_lif_deinit(lif);
2246 err_qcqs_free:
2247         ionic_qcqs_free(lif);
2248 err_out:
2249         dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
2250 }
2251
2252 void ionic_lif_free(struct ionic_lif *lif)
2253 {
2254         struct device *dev = lif->ionic->dev;
2255
2256         /* free rss indirection table */
2257         dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
2258                           lif->rss_ind_tbl_pa);
2259         lif->rss_ind_tbl = NULL;
2260         lif->rss_ind_tbl_pa = 0;
2261
2262         /* free queues */
2263         ionic_qcqs_free(lif);
2264         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2265                 ionic_lif_reset(lif);
2266
2267         /* free lif info */
2268         kfree(lif->identity);
2269         dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2270         lif->info = NULL;
2271         lif->info_pa = 0;
2272
2273         /* unmap doorbell page */
2274         ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
2275         lif->kern_dbpage = NULL;
2276         kfree(lif->dbid_inuse);
2277         lif->dbid_inuse = NULL;
2278
2279         /* free netdev & lif */
2280         ionic_debugfs_del_lif(lif);
2281         free_netdev(lif->netdev);
2282 }
2283
2284 void ionic_lif_deinit(struct ionic_lif *lif)
2285 {
2286         if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
2287                 return;
2288
2289         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
2290                 cancel_work_sync(&lif->deferred.work);
2291                 cancel_work_sync(&lif->tx_timeout_work);
2292                 ionic_rx_filters_deinit(lif);
2293                 if (lif->netdev->features & NETIF_F_RXHASH)
2294                         ionic_lif_rss_deinit(lif);
2295         }
2296
2297         napi_disable(&lif->adminqcq->napi);
2298         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
2299         ionic_lif_qcq_deinit(lif, lif->adminqcq);
2300
2301         mutex_destroy(&lif->queue_lock);
2302         ionic_lif_reset(lif);
2303 }
2304
2305 static int ionic_lif_adminq_init(struct ionic_lif *lif)
2306 {
2307         struct device *dev = lif->ionic->dev;
2308         struct ionic_q_init_comp comp;
2309         struct ionic_dev *idev;
2310         struct ionic_qcq *qcq;
2311         struct ionic_queue *q;
2312         int err;
2313
2314         idev = &lif->ionic->idev;
2315         qcq = lif->adminqcq;
2316         q = &qcq->q;
2317
2318         mutex_lock(&lif->ionic->dev_cmd_lock);
2319         ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
2320         err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2321         ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
2322         mutex_unlock(&lif->ionic->dev_cmd_lock);
2323         if (err) {
2324                 netdev_err(lif->netdev, "adminq init failed %d\n", err);
2325                 return err;
2326         }
2327
2328         q->hw_type = comp.hw_type;
2329         q->hw_index = le32_to_cpu(comp.hw_index);
2330         q->dbval = IONIC_DBELL_QID(q->hw_index);
2331
2332         dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
2333         dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
2334
2335         netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
2336                        NAPI_POLL_WEIGHT);
2337
2338         napi_enable(&qcq->napi);
2339
2340         if (qcq->flags & IONIC_QCQ_F_INTR)
2341                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
2342                                 IONIC_INTR_MASK_CLEAR);
2343
2344         qcq->flags |= IONIC_QCQ_F_INITED;
2345
2346         return 0;
2347 }
2348
2349 static int ionic_lif_notifyq_init(struct ionic_lif *lif)
2350 {
2351         struct ionic_qcq *qcq = lif->notifyqcq;
2352         struct device *dev = lif->ionic->dev;
2353         struct ionic_queue *q = &qcq->q;
2354         int err;
2355
2356         struct ionic_admin_ctx ctx = {
2357                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2358                 .cmd.q_init = {
2359                         .opcode = IONIC_CMD_Q_INIT,
2360                         .lif_index = cpu_to_le16(lif->index),
2361                         .type = q->type,
2362                         .ver = lif->qtype_info[q->type].version,
2363                         .index = cpu_to_le32(q->index),
2364                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
2365                                              IONIC_QINIT_F_ENA),
2366                         .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
2367                         .pid = cpu_to_le16(q->pid),
2368                         .ring_size = ilog2(q->num_descs),
2369                         .ring_base = cpu_to_le64(q->base_pa),
2370                 }
2371         };
2372
2373         dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
2374         dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
2375         dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
2376         dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
2377
2378         err = ionic_adminq_post_wait(lif, &ctx);
2379         if (err)
2380                 return err;
2381
2382         lif->last_eid = 0;
2383         q->hw_type = ctx.comp.q_init.hw_type;
2384         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
2385         q->dbval = IONIC_DBELL_QID(q->hw_index);
2386
2387         dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
2388         dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
2389
2390         /* preset the callback info */
2391         q->info[0].cb_arg = lif;
2392
2393         qcq->flags |= IONIC_QCQ_F_INITED;
2394
2395         return 0;
2396 }
2397
2398 static int ionic_station_set(struct ionic_lif *lif)
2399 {
2400         struct net_device *netdev = lif->netdev;
2401         struct ionic_admin_ctx ctx = {
2402                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2403                 .cmd.lif_getattr = {
2404                         .opcode = IONIC_CMD_LIF_GETATTR,
2405                         .index = cpu_to_le16(lif->index),
2406                         .attr = IONIC_LIF_ATTR_MAC,
2407                 },
2408         };
2409         struct sockaddr addr;
2410         int err;
2411
2412         err = ionic_adminq_post_wait(lif, &ctx);
2413         if (err)
2414                 return err;
2415         netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
2416                    ctx.comp.lif_getattr.mac);
2417         if (is_zero_ether_addr(ctx.comp.lif_getattr.mac))
2418                 return 0;
2419
2420         if (!is_zero_ether_addr(netdev->dev_addr)) {
2421                 /* If the netdev mac is non-zero and doesn't match the default
2422                  * device address, it was set by something earlier and we're
2423                  * likely here again after a fw-upgrade reset.  We need to be
2424                  * sure the netdev mac is in our filter list.
2425                  */
2426                 if (!ether_addr_equal(ctx.comp.lif_getattr.mac,
2427                                       netdev->dev_addr))
2428                         ionic_lif_addr(lif, netdev->dev_addr, true);
2429         } else {
2430                 /* Update the netdev mac with the device's mac */
2431                 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);
2432                 addr.sa_family = AF_INET;
2433                 err = eth_prepare_mac_addr_change(netdev, &addr);
2434                 if (err) {
2435                         netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
2436                                     addr.sa_data, err);
2437                         return 0;
2438                 }
2439
2440                 eth_commit_mac_addr_change(netdev, &addr);
2441         }
2442
2443         netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
2444                    netdev->dev_addr);
2445         ionic_lif_addr(lif, netdev->dev_addr, true);
2446
2447         return 0;
2448 }
2449
2450 int ionic_lif_init(struct ionic_lif *lif)
2451 {
2452         struct ionic_dev *idev = &lif->ionic->idev;
2453         struct device *dev = lif->ionic->dev;
2454         struct ionic_lif_init_comp comp;
2455         int dbpage_num;
2456         int err;
2457
2458         mutex_lock(&lif->ionic->dev_cmd_lock);
2459         ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
2460         err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2461         ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
2462         mutex_unlock(&lif->ionic->dev_cmd_lock);
2463         if (err)
2464                 return err;
2465
2466         lif->hw_index = le16_to_cpu(comp.hw_index);
2467         mutex_init(&lif->queue_lock);
2468
2469         /* now that we have the hw_index we can figure out our doorbell page */
2470         lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
2471         if (!lif->dbid_count) {
2472                 dev_err(dev, "No doorbell pages, aborting\n");
2473                 return -EINVAL;
2474         }
2475
2476         lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL);
2477         if (!lif->dbid_inuse) {
2478                 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n");
2479                 return -ENOMEM;
2480         }
2481
2482         /* first doorbell id reserved for kernel (dbid aka pid == zero) */
2483         set_bit(0, lif->dbid_inuse);
2484         lif->kern_pid = 0;
2485
2486         dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
2487         lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
2488         if (!lif->kern_dbpage) {
2489                 dev_err(dev, "Cannot map dbpage, aborting\n");
2490                 err = -ENOMEM;
2491                 goto err_out_free_dbid;
2492         }
2493
2494         err = ionic_lif_adminq_init(lif);
2495         if (err)
2496                 goto err_out_adminq_deinit;
2497
2498         if (lif->ionic->nnqs_per_lif) {
2499                 err = ionic_lif_notifyq_init(lif);
2500                 if (err)
2501                         goto err_out_notifyq_deinit;
2502         }
2503
2504         err = ionic_init_nic_features(lif);
2505         if (err)
2506                 goto err_out_notifyq_deinit;
2507
2508         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
2509                 err = ionic_rx_filters_init(lif);
2510                 if (err)
2511                         goto err_out_notifyq_deinit;
2512         }
2513
2514         err = ionic_station_set(lif);
2515         if (err)
2516                 goto err_out_notifyq_deinit;
2517
2518         lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
2519
2520         set_bit(IONIC_LIF_F_INITED, lif->state);
2521
2522         INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
2523
2524         return 0;
2525
2526 err_out_notifyq_deinit:
2527         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
2528 err_out_adminq_deinit:
2529         ionic_lif_qcq_deinit(lif, lif->adminqcq);
2530         ionic_lif_reset(lif);
2531         ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
2532         lif->kern_dbpage = NULL;
2533 err_out_free_dbid:
2534         kfree(lif->dbid_inuse);
2535         lif->dbid_inuse = NULL;
2536
2537         return err;
2538 }
2539
2540 static void ionic_lif_notify_work(struct work_struct *ws)
2541 {
2542 }
2543
2544 static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
2545 {
2546         struct ionic_admin_ctx ctx = {
2547                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2548                 .cmd.lif_setattr = {
2549                         .opcode = IONIC_CMD_LIF_SETATTR,
2550                         .index = cpu_to_le16(lif->index),
2551                         .attr = IONIC_LIF_ATTR_NAME,
2552                 },
2553         };
2554
2555         strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
2556                 sizeof(ctx.cmd.lif_setattr.name));
2557
2558         ionic_adminq_post_wait(lif, &ctx);
2559 }
2560
2561 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
2562 {
2563         if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
2564                 return NULL;
2565
2566         return netdev_priv(netdev);
2567 }
2568
2569 static int ionic_lif_notify(struct notifier_block *nb,
2570                             unsigned long event, void *info)
2571 {
2572         struct net_device *ndev = netdev_notifier_info_to_dev(info);
2573         struct ionic *ionic = container_of(nb, struct ionic, nb);
2574         struct ionic_lif *lif = ionic_netdev_lif(ndev);
2575
2576         if (!lif || lif->ionic != ionic)
2577                 return NOTIFY_DONE;
2578
2579         switch (event) {
2580         case NETDEV_CHANGENAME:
2581                 ionic_lif_set_netdev_info(lif);
2582                 break;
2583         }
2584
2585         return NOTIFY_DONE;
2586 }
2587
2588 int ionic_lif_register(struct ionic_lif *lif)
2589 {
2590         int err;
2591
2592         INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work);
2593
2594         lif->ionic->nb.notifier_call = ionic_lif_notify;
2595
2596         err = register_netdevice_notifier(&lif->ionic->nb);
2597         if (err)
2598                 lif->ionic->nb.notifier_call = NULL;
2599
2600         /* only register LIF0 for now */
2601         err = register_netdev(lif->netdev);
2602         if (err) {
2603                 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n");
2604                 return err;
2605         }
2606         lif->registered = true;
2607         ionic_lif_set_netdev_info(lif);
2608
2609         return 0;
2610 }
2611
2612 void ionic_lif_unregister(struct ionic_lif *lif)
2613 {
2614         if (lif->ionic->nb.notifier_call) {
2615                 unregister_netdevice_notifier(&lif->ionic->nb);
2616                 cancel_work_sync(&lif->ionic->nb_work);
2617                 lif->ionic->nb.notifier_call = NULL;
2618         }
2619
2620         if (lif->netdev->reg_state == NETREG_REGISTERED)
2621                 unregister_netdev(lif->netdev);
2622         lif->registered = false;
2623 }
2624
2625 static void ionic_lif_queue_identify(struct ionic_lif *lif)
2626 {
2627         struct ionic *ionic = lif->ionic;
2628         union ionic_q_identity *q_ident;
2629         struct ionic_dev *idev;
2630         int qtype;
2631         int err;
2632
2633         idev = &lif->ionic->idev;
2634         q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data;
2635
2636         for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
2637                 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
2638
2639                 /* filter out the ones we know about */
2640                 switch (qtype) {
2641                 case IONIC_QTYPE_ADMINQ:
2642                 case IONIC_QTYPE_NOTIFYQ:
2643                 case IONIC_QTYPE_RXQ:
2644                 case IONIC_QTYPE_TXQ:
2645                         break;
2646                 default:
2647                         continue;
2648                 }
2649
2650                 memset(qti, 0, sizeof(*qti));
2651
2652                 mutex_lock(&ionic->dev_cmd_lock);
2653                 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
2654                                              ionic_qtype_versions[qtype]);
2655                 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
2656                 if (!err) {
2657                         qti->version   = q_ident->version;
2658                         qti->supported = q_ident->supported;
2659                         qti->features  = le64_to_cpu(q_ident->features);
2660                         qti->desc_sz   = le16_to_cpu(q_ident->desc_sz);
2661                         qti->comp_sz   = le16_to_cpu(q_ident->comp_sz);
2662                         qti->sg_desc_sz   = le16_to_cpu(q_ident->sg_desc_sz);
2663                         qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems);
2664                         qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride);
2665                 }
2666                 mutex_unlock(&ionic->dev_cmd_lock);
2667
2668                 if (err == -EINVAL) {
2669                         dev_err(ionic->dev, "qtype %d not supported\n", qtype);
2670                         continue;
2671                 } else if (err == -EIO) {
2672                         dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
2673                         return;
2674                 } else if (err) {
2675                         dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
2676                                 qtype, err);
2677                         return;
2678                 }
2679
2680                 dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
2681                         qtype, qti->version);
2682                 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
2683                         qtype, qti->supported);
2684                 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
2685                         qtype, qti->features);
2686                 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
2687                         qtype, qti->desc_sz);
2688                 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
2689                         qtype, qti->comp_sz);
2690                 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
2691                         qtype, qti->sg_desc_sz);
2692                 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
2693                         qtype, qti->max_sg_elems);
2694                 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
2695                         qtype, qti->sg_desc_stride);
2696         }
2697 }
2698
2699 int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
2700                        union ionic_lif_identity *lid)
2701 {
2702         struct ionic_dev *idev = &ionic->idev;
2703         size_t sz;
2704         int err;
2705
2706         sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
2707
2708         mutex_lock(&ionic->dev_cmd_lock);
2709         ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
2710         err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
2711         memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
2712         mutex_unlock(&ionic->dev_cmd_lock);
2713         if (err)
2714                 return (err);
2715
2716         dev_dbg(ionic->dev, "capabilities 0x%llx\n",
2717                 le64_to_cpu(lid->capabilities));
2718
2719         dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
2720                 le32_to_cpu(lid->eth.max_ucast_filters));
2721         dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
2722                 le32_to_cpu(lid->eth.max_mcast_filters));
2723         dev_dbg(ionic->dev, "eth.features 0x%llx\n",
2724                 le64_to_cpu(lid->eth.config.features));
2725         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
2726                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
2727         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
2728                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
2729         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
2730                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
2731         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
2732                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
2733         dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
2734         dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
2735         dev_dbg(ionic->dev, "eth.config.mtu %d\n",
2736                 le32_to_cpu(lid->eth.config.mtu));
2737
2738         return 0;
2739 }
2740
2741 int ionic_lif_size(struct ionic *ionic)
2742 {
2743         struct ionic_identity *ident = &ionic->ident;
2744         unsigned int nintrs, dev_nintrs;
2745         union ionic_lif_config *lc;
2746         unsigned int ntxqs_per_lif;
2747         unsigned int nrxqs_per_lif;
2748         unsigned int neqs_per_lif;
2749         unsigned int nnqs_per_lif;
2750         unsigned int nxqs, neqs;
2751         unsigned int min_intrs;
2752         int err;
2753
2754         lc = &ident->lif.eth.config;
2755         dev_nintrs = le32_to_cpu(ident->dev.nintrs);
2756         neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
2757         nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
2758         ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
2759         nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
2760
2761         nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
2762         nxqs = min(nxqs, num_online_cpus());
2763         neqs = min(neqs_per_lif, num_online_cpus());
2764
2765 try_again:
2766         /* interrupt usage:
2767          *    1 for master lif adminq/notifyq
2768          *    1 for each CPU for master lif TxRx queue pairs
2769          *    whatever's left is for RDMA queues
2770          */
2771         nintrs = 1 + nxqs + neqs;
2772         min_intrs = 2;  /* adminq + 1 TxRx queue pair */
2773
2774         if (nintrs > dev_nintrs)
2775                 goto try_fewer;
2776
2777         err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
2778         if (err < 0 && err != -ENOSPC) {
2779                 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
2780                 return err;
2781         }
2782         if (err == -ENOSPC)
2783                 goto try_fewer;
2784
2785         if (err != nintrs) {
2786                 ionic_bus_free_irq_vectors(ionic);
2787                 goto try_fewer;
2788         }
2789
2790         ionic->nnqs_per_lif = nnqs_per_lif;
2791         ionic->neqs_per_lif = neqs;
2792         ionic->ntxqs_per_lif = nxqs;
2793         ionic->nrxqs_per_lif = nxqs;
2794         ionic->nintrs = nintrs;
2795
2796         ionic_debugfs_add_sizes(ionic);
2797
2798         return 0;
2799
2800 try_fewer:
2801         if (nnqs_per_lif > 1) {
2802                 nnqs_per_lif >>= 1;
2803                 goto try_again;
2804         }
2805         if (neqs > 1) {
2806                 neqs >>= 1;
2807                 goto try_again;
2808         }
2809         if (nxqs > 1) {
2810                 nxqs >>= 1;
2811                 goto try_again;
2812         }
2813         dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
2814         return -ENOSPC;
2815 }