drivers/net/ethernet/pensando/ionic/ionic_lif.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
   3
   4 #include <linux/ethtool.h>
   5 #include <linux/printk.h>
   6 #include <linux/dynamic_debug.h>
   7 #include <linux/netdevice.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/if_vlan.h>
  10 #include <linux/rtnetlink.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/pci.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/crash_dump.h>
  15
  16 #include "ionic.h"
  17 #include "ionic_bus.h"
  18 #include "ionic_lif.h"
  19 #include "ionic_txrx.h"
  20 #include "ionic_ethtool.h"
  21 #include "ionic_debugfs.h"
  22
  23 /* queuetype support level */
  24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
  25         [IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
  26         [IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
  27         [IONIC_QTYPE_RXQ]     = 0,   /* 0 = Base version with CQ+SG support */
  28         [IONIC_QTYPE_TXQ]     = 1,   /* 0 = Base version with CQ+SG support
  29                                       * 1 =   ... with Tx SG version 1
  30                                       */
  31 };
  32
  33 static void ionic_link_status_check(struct ionic_lif *lif);
  34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
  35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
  36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
  37
  38 static void ionic_txrx_deinit(struct ionic_lif *lif);
  39 static int ionic_txrx_init(struct ionic_lif *lif);
  40 static int ionic_start_queues(struct ionic_lif *lif);
  41 static void ionic_stop_queues(struct ionic_lif *lif);
  42 static void ionic_lif_queue_identify(struct ionic_lif *lif);
  43
  44 static void ionic_dim_work(struct work_struct *work)
  45 {
  46         struct dim *dim = container_of(work, struct dim, work);
  47         struct dim_cq_moder cur_moder;
  48         struct ionic_qcq *qcq;
  49         u32 new_coal;
  50
  51         cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
  52         qcq = container_of(dim, struct ionic_qcq, dim);
  53         new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
  54         new_coal = new_coal ? new_coal : 1;
  55
  56         if (qcq->intr.dim_coal_hw != new_coal) {
  57                 unsigned int qi = qcq->cq.bound_q->index;
  58                 struct ionic_lif *lif = qcq->q.lif;
  59
  60                 qcq->intr.dim_coal_hw = new_coal;
  61
  62                 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
  63                                      lif->rxqcqs[qi]->intr.index,
  64                                      qcq->intr.dim_coal_hw);
  65         }
  66
  67         dim->state = DIM_START_MEASURE;
  68 }
  69
  70 static void ionic_lif_deferred_work(struct work_struct *work)
  71 {
  72         struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
  73         struct ionic_deferred *def = &lif->deferred;
  74         struct ionic_deferred_work *w = NULL;
  75
  76         do {
  77                 spin_lock_bh(&def->lock);
  78                 if (!list_empty(&def->list)) {
  79                         w = list_first_entry(&def->list,
  80                                              struct ionic_deferred_work, list);
  81                         list_del(&w->list);
  82                 }
  83                 spin_unlock_bh(&def->lock);
  84
  85                 if (!w)
  86                         break;
  87
  88                 switch (w->type) {
  89                 case IONIC_DW_TYPE_RX_MODE:
  90                         ionic_lif_rx_mode(lif);
  91                         break;
  92                 case IONIC_DW_TYPE_LINK_STATUS:
  93                         ionic_link_status_check(lif);
  94                         break;
  95                 case IONIC_DW_TYPE_LIF_RESET:
  96                         if (w->fw_status) {
  97                                 ionic_lif_handle_fw_up(lif);
  98                         } else {
  99                                 ionic_lif_handle_fw_down(lif);
 100
 101                                 /* Fire off another watchdog to see
 102                                  * if the FW is already back rather than
 103                                  * waiting another whole cycle
 104                                  */
 105                                 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1);
 106                         }
 107                         break;
 108                 default:
 109                         break;
 110                 }
 111                 kfree(w);
 112                 w = NULL;
 113         } while (true);
 114 }
 115
 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
 117                                 struct ionic_deferred_work *work)
 118 {
 119         spin_lock_bh(&def->lock);
 120         list_add_tail(&work->list, &def->list);
 121         spin_unlock_bh(&def->lock);
 122         schedule_work(&def->work);
 123 }
 124
 125 static void ionic_link_status_check(struct ionic_lif *lif)
 126 {
 127         struct net_device *netdev = lif->netdev;
 128         u16 link_status;
 129         bool link_up;
 130
 131         if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 132                 return;
 133
 134         /* Don't put carrier back up if we're in a broken state */
 135         if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
 136                 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 137                 return;
 138         }
 139
 140         link_status = le16_to_cpu(lif->info->status.link_status);
 141         link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
 142
 143         if (link_up) {
 144                 int err = 0;
 145
 146                 if (netdev->flags & IFF_UP && netif_running(netdev)) {
 147                         mutex_lock(&lif->queue_lock);
 148                         err = ionic_start_queues(lif);
 149                         if (err && err != -EBUSY) {
 150                                 netdev_err(lif->netdev,
 151                                            "Failed to start queues: %d\n", err);
 152                                 set_bit(IONIC_LIF_F_BROKEN, lif->state);
 153                                 netif_carrier_off(lif->netdev);
 154                         }
 155                         mutex_unlock(&lif->queue_lock);
 156                 }
 157
 158                 if (!err && !netif_carrier_ok(netdev)) {
 159                         ionic_port_identify(lif->ionic);
 160                         netdev_info(netdev, "Link up - %d Gbps\n",
 161                                     le32_to_cpu(lif->info->status.link_speed) / 1000);
 162                         netif_carrier_on(netdev);
 163                 }
 164         } else {
 165                 if (netif_carrier_ok(netdev)) {
 166                         netdev_info(netdev, "Link down\n");
 167                         netif_carrier_off(netdev);
 168                 }
 169
 170                 if (netdev->flags & IFF_UP && netif_running(netdev)) {
 171                         mutex_lock(&lif->queue_lock);
 172                         ionic_stop_queues(lif);
 173                         mutex_unlock(&lif->queue_lock);
 174                 }
 175         }
 176
 177         clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 178 }
 179
 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
 181 {
 182         struct ionic_deferred_work *work;
 183
 184         /* we only need one request outstanding at a time */
 185         if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
 186                 return;
 187
 188         if (!can_sleep) {
 189                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 190                 if (!work) {
 191                         clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
 192                         return;
 193                 }
 194
 195                 work->type = IONIC_DW_TYPE_LINK_STATUS;
 196                 ionic_lif_deferred_enqueue(&lif->deferred, work);
 197         } else {
 198                 ionic_link_status_check(lif);
 199         }
 200 }
 201
 202 static irqreturn_t ionic_isr(int irq, void *data)
 203 {
 204         struct napi_struct *napi = data;
 205
 206         napi_schedule_irqoff(napi);
 207
 208         return IRQ_HANDLED;
 209 }
 210
 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
 212 {
 213         struct ionic_intr_info *intr = &qcq->intr;
 214         struct device *dev = lif->ionic->dev;
 215         struct ionic_queue *q = &qcq->q;
 216         const char *name;
 217
 218         if (lif->registered)
 219                 name = lif->netdev->name;
 220         else
 221                 name = dev_name(dev);
 222
 223         snprintf(intr->name, sizeof(intr->name),
 224                  "%s-%s-%s", IONIC_DRV_NAME, name, q->name);
 225
 226         return devm_request_irq(dev, intr->vector, ionic_isr,
 227                                 0, intr->name, &qcq->napi);
 228 }
 229
 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
 231 {
 232         struct ionic *ionic = lif->ionic;
 233         int index;
 234
 235         index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
 236         if (index == ionic->nintrs) {
 237                 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
 238                             __func__, index, ionic->nintrs);
 239                 return -ENOSPC;
 240         }
 241
 242         set_bit(index, ionic->intrs);
 243         ionic_intr_init(&ionic->idev, intr, index);
 244
 245         return 0;
 246 }
 247
 248 static void ionic_intr_free(struct ionic *ionic, int index)
 249 {
 250         if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
 251                 clear_bit(index, ionic->intrs);
 252 }
 253
 254 static int ionic_qcq_enable(struct ionic_qcq *qcq)
 255 {
 256         struct ionic_queue *q = &qcq->q;
 257         struct ionic_lif *lif = q->lif;
 258         struct ionic_dev *idev;
 259         struct device *dev;
 260
 261         struct ionic_admin_ctx ctx = {
 262                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 263                 .cmd.q_control = {
 264                         .opcode = IONIC_CMD_Q_CONTROL,
 265                         .lif_index = cpu_to_le16(lif->index),
 266                         .type = q->type,
 267                         .index = cpu_to_le32(q->index),
 268                         .oper = IONIC_Q_ENABLE,
 269                 },
 270         };
 271
 272         idev = &lif->ionic->idev;
 273         dev = lif->ionic->dev;
 274
 275         dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
 276                 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 277
 278         if (qcq->flags & IONIC_QCQ_F_INTR) {
 279                 irq_set_affinity_hint(qcq->intr.vector,
 280                                       &qcq->intr.affinity_mask);
 281                 napi_enable(&qcq->napi);
 282                 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
 283                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 284                                 IONIC_INTR_MASK_CLEAR);
 285         }
 286
 287         return ionic_adminq_post_wait(lif, &ctx);
 288 }
 289
 290 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err)
 291 {
 292         struct ionic_queue *q;
 293
 294         struct ionic_admin_ctx ctx = {
 295                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 296                 .cmd.q_control = {
 297                         .opcode = IONIC_CMD_Q_CONTROL,
 298                         .oper = IONIC_Q_DISABLE,
 299                 },
 300         };
 301
 302         if (!qcq) {
 303                 netdev_err(lif->netdev, "%s: bad qcq\n", __func__);
 304                 return -ENXIO;
 305         }
 306
 307         q = &qcq->q;
 308
 309         if (qcq->flags & IONIC_QCQ_F_INTR) {
 310                 struct ionic_dev *idev = &lif->ionic->idev;
 311
 312                 cancel_work_sync(&qcq->dim.work);
 313                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 314                                 IONIC_INTR_MASK_SET);
 315                 synchronize_irq(qcq->intr.vector);
 316                 irq_set_affinity_hint(qcq->intr.vector, NULL);
 317                 napi_disable(&qcq->napi);
 318         }
 319
 320         /* If there was a previous fw communcation error, don't bother with
 321          * sending the adminq command and just return the same error value.
 322          */
 323         if (fw_err == -ETIMEDOUT || fw_err == -ENXIO)
 324                 return fw_err;
 325
 326         ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
 327         ctx.cmd.q_control.type = q->type;
 328         ctx.cmd.q_control.index = cpu_to_le32(q->index);
 329         dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
 330                 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
 331
 332         return ionic_adminq_post_wait(lif, &ctx);
 333 }
 334
 335 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
 336 {
 337         struct ionic_dev *idev = &lif->ionic->idev;
 338
 339         if (!qcq)
 340                 return;
 341
 342         if (!(qcq->flags & IONIC_QCQ_F_INITED))
 343                 return;
 344
 345         if (qcq->flags & IONIC_QCQ_F_INTR) {
 346                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
 347                                 IONIC_INTR_MASK_SET);
 348                 netif_napi_del(&qcq->napi);
 349         }
 350
 351         qcq->flags &= ~IONIC_QCQ_F_INITED;
 352 }
 353
 354 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
 355 {
 356         if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
 357                 return;
 358
 359         irq_set_affinity_hint(qcq->intr.vector, NULL);
 360         devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
 361         qcq->intr.vector = 0;
 362         ionic_intr_free(lif->ionic, qcq->intr.index);
 363         qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 364 }
 365
 366 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
 367 {
 368         struct device *dev = lif->ionic->dev;
 369
 370         if (!qcq)
 371                 return;
 372
 373         ionic_debugfs_del_qcq(qcq);
 374
 375         if (qcq->q_base) {
 376                 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
 377                 qcq->q_base = NULL;
 378                 qcq->q_base_pa = 0;
 379         }
 380
 381         if (qcq->cq_base) {
 382                 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
 383                 qcq->cq_base = NULL;
 384                 qcq->cq_base_pa = 0;
 385         }
 386
 387         if (qcq->sg_base) {
 388                 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
 389                 qcq->sg_base = NULL;
 390                 qcq->sg_base_pa = 0;
 391         }
 392
 393         ionic_qcq_intr_free(lif, qcq);
 394
 395         if (qcq->cq.info) {
 396                 devm_kfree(dev, qcq->cq.info);
 397                 qcq->cq.info = NULL;
 398         }
 399         if (qcq->q.info) {
 400                 devm_kfree(dev, qcq->q.info);
 401                 qcq->q.info = NULL;
 402         }
 403 }
 404
 405 static void ionic_qcqs_free(struct ionic_lif *lif)
 406 {
 407         struct device *dev = lif->ionic->dev;
 408         struct ionic_qcq *adminqcq;
 409         unsigned long irqflags;
 410
 411         if (lif->notifyqcq) {
 412                 ionic_qcq_free(lif, lif->notifyqcq);
 413                 devm_kfree(dev, lif->notifyqcq);
 414                 lif->notifyqcq = NULL;
 415         }
 416
 417         if (lif->adminqcq) {
 418                 spin_lock_irqsave(&lif->adminq_lock, irqflags);
 419                 adminqcq = READ_ONCE(lif->adminqcq);
 420                 lif->adminqcq = NULL;
 421                 spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
 422                 if (adminqcq) {
 423                         ionic_qcq_free(lif, adminqcq);
 424                         devm_kfree(dev, adminqcq);
 425                 }
 426         }
 427
 428         if (lif->rxqcqs) {
 429                 devm_kfree(dev, lif->rxqstats);
 430                 lif->rxqstats = NULL;
 431                 devm_kfree(dev, lif->rxqcqs);
 432                 lif->rxqcqs = NULL;
 433         }
 434
 435         if (lif->txqcqs) {
 436                 devm_kfree(dev, lif->txqstats);
 437                 lif->txqstats = NULL;
 438                 devm_kfree(dev, lif->txqcqs);
 439                 lif->txqcqs = NULL;
 440         }
 441 }
 442
 443 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
 444                                       struct ionic_qcq *n_qcq)
 445 {
 446         if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
 447                 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
 448                 n_qcq->flags &= ~IONIC_QCQ_F_INTR;
 449         }
 450
 451         n_qcq->intr.vector = src_qcq->intr.vector;
 452         n_qcq->intr.index = src_qcq->intr.index;
 453 }
 454
 455 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
 456 {
 457         int err;
 458
 459         if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
 460                 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
 461                 return 0;
 462         }
 463
 464         err = ionic_intr_alloc(lif, &qcq->intr);
 465         if (err) {
 466                 netdev_warn(lif->netdev, "no intr for %s: %d\n",
 467                             qcq->q.name, err);
 468                 goto err_out;
 469         }
 470
 471         err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
 472         if (err < 0) {
 473                 netdev_warn(lif->netdev, "no vector for %s: %d\n",
 474                             qcq->q.name, err);
 475                 goto err_out_free_intr;
 476         }
 477         qcq->intr.vector = err;
 478         ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
 479                                IONIC_INTR_MASK_SET);
 480
 481         err = ionic_request_irq(lif, qcq);
 482         if (err) {
 483                 netdev_warn(lif->netdev, "irq request failed %d\n", err);
 484                 goto err_out_free_intr;
 485         }
 486
 487         /* try to get the irq on the local numa node first */
 488         qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
 489                                              dev_to_node(lif->ionic->dev));
 490         if (qcq->intr.cpu != -1)
 491                 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);
 492
 493         netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
 494         return 0;
 495
 496 err_out_free_intr:
 497         ionic_intr_free(lif->ionic, qcq->intr.index);
 498 err_out:
 499         return err;
 500 }
 501
 502 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
 503                            unsigned int index,
 504                            const char *name, unsigned int flags,
 505                            unsigned int num_descs, unsigned int desc_size,
 506                            unsigned int cq_desc_size,
 507                            unsigned int sg_desc_size,
 508                            unsigned int pid, struct ionic_qcq **qcq)
 509 {
 510         struct ionic_dev *idev = &lif->ionic->idev;
 511         struct device *dev = lif->ionic->dev;
 512         void *q_base, *cq_base, *sg_base;
 513         dma_addr_t cq_base_pa = 0;
 514         dma_addr_t sg_base_pa = 0;
 515         dma_addr_t q_base_pa = 0;
 516         struct ionic_qcq *new;
 517         int err;
 518
 519         *qcq = NULL;
 520
 521         new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
 522         if (!new) {
 523                 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
 524                 err = -ENOMEM;
 525                 goto err_out;
 526         }
 527
 528         new->q.dev = dev;
 529         new->flags = flags;
 530
 531         new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info),
 532                                    GFP_KERNEL);
 533         if (!new->q.info) {
 534                 netdev_err(lif->netdev, "Cannot allocate queue info\n");
 535                 err = -ENOMEM;
 536                 goto err_out_free_qcq;
 537         }
 538
 539         new->q.type = type;
 540         new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;
 541
 542         err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
 543                            desc_size, sg_desc_size, pid);
 544         if (err) {
 545                 netdev_err(lif->netdev, "Cannot initialize queue\n");
 546                 goto err_out_free_q_info;
 547         }
 548
 549         err = ionic_alloc_qcq_interrupt(lif, new);
 550         if (err)
 551                 goto err_out;
 552
 553         new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info),
 554                                     GFP_KERNEL);
 555         if (!new->cq.info) {
 556                 netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
 557                 err = -ENOMEM;
 558                 goto err_out_free_irq;
 559         }
 560
 561         err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
 562         if (err) {
 563                 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
 564                 goto err_out_free_cq_info;
 565         }
 566
 567         if (flags & IONIC_QCQ_F_NOTIFYQ) {
 568                 int q_size, cq_size;
 569
 570                 /* q & cq need to be contiguous in case of notifyq */
 571                 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
 572                 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE);
 573
 574                 new->q_size = PAGE_SIZE + q_size + cq_size;
 575                 new->q_base = dma_alloc_coherent(dev, new->q_size,
 576                                                  &new->q_base_pa, GFP_KERNEL);
 577                 if (!new->q_base) {
 578                         netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
 579                         err = -ENOMEM;
 580                         goto err_out_free_cq_info;
 581                 }
 582                 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
 583                 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
 584                 ionic_q_map(&new->q, q_base, q_base_pa);
 585
 586                 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE);
 587                 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
 588                 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 589                 ionic_cq_bind(&new->cq, &new->q);
 590         } else {
 591                 new->q_size = PAGE_SIZE + (num_descs * desc_size);
 592                 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
 593                                                  GFP_KERNEL);
 594                 if (!new->q_base) {
 595                         netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
 596                         err = -ENOMEM;
 597                         goto err_out_free_cq_info;
 598                 }
 599                 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
 600                 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
 601                 ionic_q_map(&new->q, q_base, q_base_pa);
 602
 603                 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
 604                 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
 605                                                   GFP_KERNEL);
 606                 if (!new->cq_base) {
 607                         netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
 608                         err = -ENOMEM;
 609                         goto err_out_free_q;
 610                 }
 611                 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
 612                 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
 613                 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
 614                 ionic_cq_bind(&new->cq, &new->q);
 615         }
 616
 617         if (flags & IONIC_QCQ_F_SG) {
 618                 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
 619                 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
 620                                                   GFP_KERNEL);
 621                 if (!new->sg_base) {
 622                         netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
 623                         err = -ENOMEM;
 624                         goto err_out_free_cq;
 625                 }
 626                 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
 627                 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
 628                 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
 629         }
 630
 631         INIT_WORK(&new->dim.work, ionic_dim_work);
 632         new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 633
 634         *qcq = new;
 635
 636         return 0;
 637
 638 err_out_free_cq:
 639         dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
 640 err_out_free_q:
 641         dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
 642 err_out_free_cq_info:
 643         devm_kfree(dev, new->cq.info);
 644 err_out_free_irq:
 645         if (flags & IONIC_QCQ_F_INTR) {
 646                 devm_free_irq(dev, new->intr.vector, &new->napi);
 647                 ionic_intr_free(lif->ionic, new->intr.index);
 648         }
 649 err_out_free_q_info:
 650         devm_kfree(dev, new->q.info);
 651 err_out_free_qcq:
 652         devm_kfree(dev, new);
 653 err_out:
 654         dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
 655         return err;
 656 }
 657
 658 static int ionic_qcqs_alloc(struct ionic_lif *lif)
 659 {
 660         struct device *dev = lif->ionic->dev;
 661         unsigned int flags;
 662         int err;
 663
 664         flags = IONIC_QCQ_F_INTR;
 665         err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
 666                               IONIC_ADMINQ_LENGTH,
 667                               sizeof(struct ionic_admin_cmd),
 668                               sizeof(struct ionic_admin_comp),
 669                               0, lif->kern_pid, &lif->adminqcq);
 670         if (err)
 671                 return err;
 672         ionic_debugfs_add_qcq(lif, lif->adminqcq);
 673
 674         if (lif->ionic->nnqs_per_lif) {
 675                 flags = IONIC_QCQ_F_NOTIFYQ;
 676                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
 677                                       flags, IONIC_NOTIFYQ_LENGTH,
 678                                       sizeof(struct ionic_notifyq_cmd),
 679                                       sizeof(union ionic_notifyq_comp),
 680                                       0, lif->kern_pid, &lif->notifyqcq);
 681                 if (err)
 682                         goto err_out;
 683                 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
 684
 685                 /* Let the notifyq ride on the adminq interrupt */
 686                 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
 687         }
 688
 689         err = -ENOMEM;
 690         lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
 691                                    sizeof(*lif->txqcqs), GFP_KERNEL);
 692         if (!lif->txqcqs)
 693                 goto err_out;
 694         lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
 695                                    sizeof(*lif->rxqcqs), GFP_KERNEL);
 696         if (!lif->rxqcqs)
 697                 goto err_out;
 698
 699         lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
 700                                      sizeof(*lif->txqstats), GFP_KERNEL);
 701         if (!lif->txqstats)
 702                 goto err_out;
 703         lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
 704                                      sizeof(*lif->rxqstats), GFP_KERNEL);
 705         if (!lif->rxqstats)
 706                 goto err_out;
 707
 708         return 0;
 709
 710 err_out:
 711         ionic_qcqs_free(lif);
 712         return err;
 713 }
 714
 715 static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
 716 {
 717         qcq->q.tail_idx = 0;
 718         qcq->q.head_idx = 0;
 719         qcq->cq.tail_idx = 0;
 720         qcq->cq.done_color = 1;
 721         memset(qcq->q_base, 0, qcq->q_size);
 722         memset(qcq->cq_base, 0, qcq->cq_size);
 723         memset(qcq->sg_base, 0, qcq->sg_size);
 724 }
 725
 726 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 727 {
 728         struct device *dev = lif->ionic->dev;
 729         struct ionic_queue *q = &qcq->q;
 730         struct ionic_cq *cq = &qcq->cq;
 731         struct ionic_admin_ctx ctx = {
 732                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 733                 .cmd.q_init = {
 734                         .opcode = IONIC_CMD_Q_INIT,
 735                         .lif_index = cpu_to_le16(lif->index),
 736                         .type = q->type,
 737                         .ver = lif->qtype_info[q->type].version,
 738                         .index = cpu_to_le32(q->index),
 739                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
 740                                              IONIC_QINIT_F_SG),
 741                         .pid = cpu_to_le16(q->pid),
 742                         .ring_size = ilog2(q->num_descs),
 743                         .ring_base = cpu_to_le64(q->base_pa),
 744                         .cq_ring_base = cpu_to_le64(cq->base_pa),
 745                         .sg_ring_base = cpu_to_le64(q->sg_base_pa),
 746                         .features = cpu_to_le64(q->features),
 747                 },
 748         };
 749         unsigned int intr_index;
 750         int err;
 751
 752         intr_index = qcq->intr.index;
 753
 754         ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);
 755
 756         dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
 757         dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
 758         dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 759         dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 760         dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 761         dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
 762         dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 763
 764         ionic_qcq_sanitize(qcq);
 765
 766         err = ionic_adminq_post_wait(lif, &ctx);
 767         if (err)
 768                 return err;
 769
 770         q->hw_type = ctx.comp.q_init.hw_type;
 771         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 772         q->dbval = IONIC_DBELL_QID(q->hw_index);
 773
 774         dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
 775         dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
 776
 777         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 778                 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
 779                                NAPI_POLL_WEIGHT);
 780
 781         qcq->flags |= IONIC_QCQ_F_INITED;
 782
 783         return 0;
 784 }
 785
 786 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
 787 {
 788         struct device *dev = lif->ionic->dev;
 789         struct ionic_queue *q = &qcq->q;
 790         struct ionic_cq *cq = &qcq->cq;
 791         struct ionic_admin_ctx ctx = {
 792                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 793                 .cmd.q_init = {
 794                         .opcode = IONIC_CMD_Q_INIT,
 795                         .lif_index = cpu_to_le16(lif->index),
 796                         .type = q->type,
 797                         .ver = lif->qtype_info[q->type].version,
 798                         .index = cpu_to_le32(q->index),
 799                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
 800                                              IONIC_QINIT_F_SG),
 801                         .intr_index = cpu_to_le16(cq->bound_intr->index),
 802                         .pid = cpu_to_le16(q->pid),
 803                         .ring_size = ilog2(q->num_descs),
 804                         .ring_base = cpu_to_le64(q->base_pa),
 805                         .cq_ring_base = cpu_to_le64(cq->base_pa),
 806                         .sg_ring_base = cpu_to_le64(q->sg_base_pa),
 807                         .features = cpu_to_le64(q->features),
 808                 },
 809         };
 810         int err;
 811
 812         dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
 813         dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
 814         dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
 815         dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
 816         dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
 817         dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
 818         dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
 819
 820         ionic_qcq_sanitize(qcq);
 821
 822         err = ionic_adminq_post_wait(lif, &ctx);
 823         if (err)
 824                 return err;
 825
 826         q->hw_type = ctx.comp.q_init.hw_type;
 827         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
 828         q->dbval = IONIC_DBELL_QID(q->hw_index);
 829
 830         dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
 831         dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
 832
 833         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
 834                 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
 835                                NAPI_POLL_WEIGHT);
 836         else
 837                 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
 838                                NAPI_POLL_WEIGHT);
 839
 840         qcq->flags |= IONIC_QCQ_F_INITED;
 841
 842         return 0;
 843 }
 844
 845 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
 846 {
 847         unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
 848         unsigned int txq_i, flags;
 849         struct ionic_qcq *txq;
 850         u64 features;
 851         int err;
 852
 853         if (lif->hwstamp_txq)
 854                 return 0;
 855
 856         features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP;
 857
 858         num_desc = IONIC_MIN_TXRX_DESC;
 859         desc_sz = sizeof(struct ionic_txq_desc);
 860         comp_sz = 2 * sizeof(struct ionic_txq_comp);
 861
 862         if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
 863             lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
 864                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
 865         else
 866                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
 867
 868         txq_i = lif->ionic->ntxqs_per_lif;
 869         flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
 870
 871         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
 872                               num_desc, desc_sz, comp_sz, sg_desc_sz,
 873                               lif->kern_pid, &txq);
 874         if (err)
 875                 goto err_qcq_alloc;
 876
 877         txq->q.features = features;
 878
 879         ionic_link_qcq_interrupts(lif->adminqcq, txq);
 880         ionic_debugfs_add_qcq(lif, txq);
 881
 882         lif->hwstamp_txq = txq;
 883
 884         if (netif_running(lif->netdev)) {
 885                 err = ionic_lif_txq_init(lif, txq);
 886                 if (err)
 887                         goto err_qcq_init;
 888
 889                 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
 890                         err = ionic_qcq_enable(txq);
 891                         if (err)
 892                                 goto err_qcq_enable;
 893                 }
 894         }
 895
 896         return 0;
 897
 898 err_qcq_enable:
 899         ionic_lif_qcq_deinit(lif, txq);
 900 err_qcq_init:
 901         lif->hwstamp_txq = NULL;
 902         ionic_debugfs_del_qcq(txq);
 903         ionic_qcq_free(lif, txq);
 904         devm_kfree(lif->ionic->dev, txq);
 905 err_qcq_alloc:
 906         return err;
 907 }
 908
 909 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
 910 {
 911         unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
 912         unsigned int rxq_i, flags;
 913         struct ionic_qcq *rxq;
 914         u64 features;
 915         int err;
 916
 917         if (lif->hwstamp_rxq)
 918                 return 0;
 919
 920         features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
 921
 922         num_desc = IONIC_MIN_TXRX_DESC;
 923         desc_sz = sizeof(struct ionic_rxq_desc);
 924         comp_sz = 2 * sizeof(struct ionic_rxq_comp);
 925         sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
 926
 927         rxq_i = lif->ionic->nrxqs_per_lif;
 928         flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;
 929
 930         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
 931                               num_desc, desc_sz, comp_sz, sg_desc_sz,
 932                               lif->kern_pid, &rxq);
 933         if (err)
 934                 goto err_qcq_alloc;
 935
 936         rxq->q.features = features;
 937
 938         ionic_link_qcq_interrupts(lif->adminqcq, rxq);
 939         ionic_debugfs_add_qcq(lif, rxq);
 940
 941         lif->hwstamp_rxq = rxq;
 942
 943         if (netif_running(lif->netdev)) {
 944                 err = ionic_lif_rxq_init(lif, rxq);
 945                 if (err)
 946                         goto err_qcq_init;
 947
 948                 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
 949                         ionic_rx_fill(&rxq->q);
 950                         err = ionic_qcq_enable(rxq);
 951                         if (err)
 952                                 goto err_qcq_enable;
 953                 }
 954         }
 955
 956         return 0;
 957
 958 err_qcq_enable:
 959         ionic_lif_qcq_deinit(lif, rxq);
 960 err_qcq_init:
 961         lif->hwstamp_rxq = NULL;
 962         ionic_debugfs_del_qcq(rxq);
 963         ionic_qcq_free(lif, rxq);
 964         devm_kfree(lif->ionic->dev, rxq);
 965 err_qcq_alloc:
 966         return err;
 967 }
 968
 969 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
 970 {
 971         struct ionic_queue_params qparam;
 972
 973         ionic_init_queue_params(lif, &qparam);
 974
 975         if (rx_all)
 976                 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
 977         else
 978                 qparam.rxq_features = 0;
 979
 980         /* if we're not running, just set the values and return */
 981         if (!netif_running(lif->netdev)) {
 982                 lif->rxq_features = qparam.rxq_features;
 983                 return 0;
 984         }
 985
 986         return ionic_reconfigure_queues(lif, &qparam);
 987 }
 988
 989 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
 990 {
 991         struct ionic_admin_ctx ctx = {
 992                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
 993                 .cmd.lif_setattr = {
 994                         .opcode = IONIC_CMD_LIF_SETATTR,
 995                         .index = cpu_to_le16(lif->index),
 996                         .attr = IONIC_LIF_ATTR_TXSTAMP,
 997                         .txstamp_mode = cpu_to_le16(txstamp_mode),
 998                 },
 999         };
1000
1001         return ionic_adminq_post_wait(lif, &ctx);
1002 }
1003
1004 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
1005 {
1006         struct ionic_admin_ctx ctx = {
1007                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1008                 .cmd.rx_filter_del = {
1009                         .opcode = IONIC_CMD_RX_FILTER_DEL,
1010                         .lif_index = cpu_to_le16(lif->index),
1011                 },
1012         };
1013         struct ionic_rx_filter *f;
1014         u32 filter_id;
1015         int err;
1016
1017         spin_lock_bh(&lif->rx_filters.lock);
1018
1019         f = ionic_rx_filter_rxsteer(lif);
1020         if (!f) {
1021                 spin_unlock_bh(&lif->rx_filters.lock);
1022                 return;
1023         }
1024
1025         filter_id = f->filter_id;
1026         ionic_rx_filter_free(lif, f);
1027
1028         spin_unlock_bh(&lif->rx_filters.lock);
1029
1030         netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);
1031
1032         ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id);
1033
1034         err = ionic_adminq_post_wait(lif, &ctx);
1035         if (err && err != -EEXIST)
1036                 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
1037 }
1038
1039 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1040 {
1041         struct ionic_admin_ctx ctx = {
1042                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1043                 .cmd.rx_filter_add = {
1044                         .opcode = IONIC_CMD_RX_FILTER_ADD,
1045                         .lif_index = cpu_to_le16(lif->index),
1046                         .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS),
1047                         .pkt_class = cpu_to_le64(pkt_class),
1048                 },
1049         };
1050         u8 qtype;
1051         u32 qid;
1052         int err;
1053
1054         if (!lif->hwstamp_rxq)
1055                 return -EINVAL;
1056
1057         qtype = lif->hwstamp_rxq->q.type;
1058         ctx.cmd.rx_filter_add.qtype = qtype;
1059
1060         qid = lif->hwstamp_rxq->q.index;
1061         ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid);
1062
1063         netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
1064         err = ionic_adminq_post_wait(lif, &ctx);
1065         if (err && err != -EEXIST)
1066                 return err;
1067
1068         spin_lock_bh(&lif->rx_filters.lock);
1069         err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED);
1070         spin_unlock_bh(&lif->rx_filters.lock);
1071
1072         return err;
1073 }
1074
1075 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
1076 {
1077         ionic_lif_del_hwstamp_rxfilt(lif);
1078
1079         if (!pkt_class)
1080                 return 0;
1081
1082         return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
1083 }
1084
1085 static bool ionic_notifyq_service(struct ionic_cq *cq,
1086                                   struct ionic_cq_info *cq_info)
1087 {
1088         union ionic_notifyq_comp *comp = cq_info->cq_desc;
1089         struct ionic_deferred_work *work;
1090         struct net_device *netdev;
1091         struct ionic_queue *q;
1092         struct ionic_lif *lif;
1093         u64 eid;
1094
1095         q = cq->bound_q;
1096         lif = q->info[0].cb_arg;
1097         netdev = lif->netdev;
1098         eid = le64_to_cpu(comp->event.eid);
1099
1100         /* Have we run out of new completions to process? */
1101         if ((s64)(eid - lif->last_eid) <= 0)
1102                 return false;
1103
1104         lif->last_eid = eid;
1105
1106         dev_dbg(lif->ionic->dev, "notifyq event:\n");
1107         dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
1108                          comp, sizeof(*comp), true);
1109
1110         switch (le16_to_cpu(comp->event.ecode)) {
1111         case IONIC_EVENT_LINK_CHANGE:
1112                 ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1113                 break;
1114         case IONIC_EVENT_RESET:
1115                 if (lif->ionic->idev.fw_status_ready &&
1116                     !test_bit(IONIC_LIF_F_FW_RESET, lif->state) &&
1117                     !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) {
1118                         work = kzalloc(sizeof(*work), GFP_ATOMIC);
1119                         if (!work) {
1120                                 netdev_err(lif->netdev, "Reset event dropped\n");
1121                                 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
1122                         } else {
1123                                 work->type = IONIC_DW_TYPE_LIF_RESET;
1124                                 ionic_lif_deferred_enqueue(&lif->deferred, work);
1125                         }
1126                 }
1127                 break;
1128         default:
1129                 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
1130                             comp->event.ecode, eid);
1131                 break;
1132         }
1133
1134         return true;
1135 }
1136
1137 static bool ionic_adminq_service(struct ionic_cq *cq,
1138                                  struct ionic_cq_info *cq_info)
1139 {
1140         struct ionic_admin_comp *comp = cq_info->cq_desc;
1141
1142         if (!color_match(comp->color, cq->done_color))
1143                 return false;
1144
1145         ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
1146
1147         return true;
1148 }
1149
1150 static int ionic_adminq_napi(struct napi_struct *napi, int budget)
1151 {
1152         struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
1153         struct ionic_lif *lif = napi_to_cq(napi)->lif;
1154         struct ionic_dev *idev = &lif->ionic->idev;
1155         unsigned long irqflags;
1156         unsigned int flags = 0;
1157         int rx_work = 0;
1158         int tx_work = 0;
1159         int n_work = 0;
1160         int a_work = 0;
1161         int work_done;
1162         int credits;
1163
1164         if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
1165                 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
1166                                           ionic_notifyq_service, NULL, NULL);
1167
1168         spin_lock_irqsave(&lif->adminq_lock, irqflags);
1169         if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
1170                 a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
1171                                           ionic_adminq_service, NULL, NULL);
1172         spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
1173
1174         if (lif->hwstamp_rxq)
1175                 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
1176                                            ionic_rx_service, NULL, NULL);
1177
1178         if (lif->hwstamp_txq)
1179                 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget,
1180                                            ionic_tx_service, NULL, NULL);
1181
1182         work_done = max(max(n_work, a_work), max(rx_work, tx_work));
1183         if (work_done < budget && napi_complete_done(napi, work_done)) {
1184                 flags |= IONIC_INTR_CRED_UNMASK;
1185                 intr->rearm_count++;
1186         }
1187
1188         if (work_done || flags) {
1189                 flags |= IONIC_INTR_CRED_RESET_COALESCE;
1190                 credits = n_work + a_work + rx_work + tx_work;
1191                 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags);
1192         }
1193
1194         return work_done;
1195 }
1196
1197 void ionic_get_stats64(struct net_device *netdev,
1198                        struct rtnl_link_stats64 *ns)
1199 {
1200         struct ionic_lif *lif = netdev_priv(netdev);
1201         struct ionic_lif_stats *ls;
1202
1203         memset(ns, 0, sizeof(*ns));
1204         ls = &lif->info->stats;
1205
1206         ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
1207                          le64_to_cpu(ls->rx_mcast_packets) +
1208                          le64_to_cpu(ls->rx_bcast_packets);
1209
1210         ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
1211                          le64_to_cpu(ls->tx_mcast_packets) +
1212                          le64_to_cpu(ls->tx_bcast_packets);
1213
1214         ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
1215                        le64_to_cpu(ls->rx_mcast_bytes) +
1216                        le64_to_cpu(ls->rx_bcast_bytes);
1217
1218         ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
1219                        le64_to_cpu(ls->tx_mcast_bytes) +
1220                        le64_to_cpu(ls->tx_bcast_bytes);
1221
1222         ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
1223                          le64_to_cpu(ls->rx_mcast_drop_packets) +
1224                          le64_to_cpu(ls->rx_bcast_drop_packets);
1225
1226         ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
1227                          le64_to_cpu(ls->tx_mcast_drop_packets) +
1228                          le64_to_cpu(ls->tx_bcast_drop_packets);
1229
1230         ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
1231
1232         ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
1233
1234         ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
1235                                le64_to_cpu(ls->rx_queue_disabled) +
1236                                le64_to_cpu(ls->rx_desc_fetch_error) +
1237                                le64_to_cpu(ls->rx_desc_data_error);
1238
1239         ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
1240                                 le64_to_cpu(ls->tx_queue_disabled) +
1241                                 le64_to_cpu(ls->tx_desc_fetch_error) +
1242                                 le64_to_cpu(ls->tx_desc_data_error);
1243
1244         ns->rx_errors = ns->rx_over_errors +
1245                         ns->rx_missed_errors;
1246
1247         ns->tx_errors = ns->tx_aborted_errors;
1248 }
1249
1250 static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
1251 {
1252         return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR);
1253 }
1254
1255 static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
1256 {
1257         /* Don't delete our own address from the uc list */
1258         if (ether_addr_equal(addr, netdev->dev_addr))
1259                 return 0;
1260
1261         return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR);
1262 }
1263
1264 void ionic_lif_rx_mode(struct ionic_lif *lif)
1265 {
1266         struct net_device *netdev = lif->netdev;
1267         unsigned int nfilters;
1268         unsigned int nd_flags;
1269         char buf[128];
1270         u16 rx_mode;
1271         int i;
1272 #define REMAIN(__x) (sizeof(buf) - (__x))
1273
1274         mutex_lock(&lif->config_lock);
1275
1276         /* grab the flags once for local use */
1277         nd_flags = netdev->flags;
1278
1279         rx_mode = IONIC_RX_MODE_F_UNICAST;
1280         rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1281         rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1282         rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1283         rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1284
1285         /* sync the filters */
1286         ionic_rx_filter_sync(lif);
1287
1288         /* check for overflow state
1289          *    if so, we track that we overflowed and enable NIC PROMISC
1290          *    else if the overflow is set and not needed
1291          *       we remove our overflow flag and check the netdev flags
1292          *       to see if we can disable NIC PROMISC
1293          */
1294         nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1295
1296         if (((lif->nucast + lif->nmcast) >= nfilters) ||
1297             (lif->max_vlans && lif->nvlans >= lif->max_vlans)) {
1298                 rx_mode |= IONIC_RX_MODE_F_PROMISC;
1299                 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1300         } else {
1301                 if (!(nd_flags & IFF_PROMISC))
1302                         rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1303                 if (!(nd_flags & IFF_ALLMULTI))
1304                         rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1305         }
1306
1307         i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1308                       lif->rx_mode, rx_mode);
1309         if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1310                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1311         if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1312                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1313         if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1314                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1315         if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1316                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1317         if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1318                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1319         if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER)
1320                 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER");
1321         netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);
1322
1323         if (lif->rx_mode != rx_mode) {
1324                 struct ionic_admin_ctx ctx = {
1325                         .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1326                         .cmd.rx_mode_set = {
1327                                 .opcode = IONIC_CMD_RX_MODE_SET,
1328                                 .lif_index = cpu_to_le16(lif->index),
1329                         },
1330                 };
1331                 int err;
1332
1333                 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode);
1334                 err = ionic_adminq_post_wait(lif, &ctx);
1335                 if (err)
1336                         netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n",
1337                                     rx_mode, err);
1338                 else
1339                         lif->rx_mode = rx_mode;
1340         }
1341
1342         mutex_unlock(&lif->config_lock);
1343 }
1344
1345 static void ionic_ndo_set_rx_mode(struct net_device *netdev)
1346 {
1347         struct ionic_lif *lif = netdev_priv(netdev);
1348         struct ionic_deferred_work *work;
1349
1350         /* Sync the kernel filter list with the driver filter list */
1351         __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1352         __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1353
1354         /* Shove off the rest of the rxmode work to the work task
1355          * which will include syncing the filters to the firmware.
1356          */
1357         work = kzalloc(sizeof(*work), GFP_ATOMIC);
1358         if (!work) {
1359                 netdev_err(lif->netdev, "rxmode change dropped\n");
1360                 return;
1361         }
1362         work->type = IONIC_DW_TYPE_RX_MODE;
1363         netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1364         ionic_lif_deferred_enqueue(&lif->deferred, work);
1365 }
1366
1367 static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1368 {
1369         u64 wanted = 0;
1370
1371         if (features & NETIF_F_HW_VLAN_CTAG_TX)
1372                 wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1373         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1374                 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1375         if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1376                 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1377         if (features & NETIF_F_RXHASH)
1378                 wanted |= IONIC_ETH_HW_RX_HASH;
1379         if (features & NETIF_F_RXCSUM)
1380                 wanted |= IONIC_ETH_HW_RX_CSUM;
1381         if (features & NETIF_F_SG)
1382                 wanted |= IONIC_ETH_HW_TX_SG;
1383         if (features & NETIF_F_HW_CSUM)
1384                 wanted |= IONIC_ETH_HW_TX_CSUM;
1385         if (features & NETIF_F_TSO)
1386                 wanted |= IONIC_ETH_HW_TSO;
1387         if (features & NETIF_F_TSO6)
1388                 wanted |= IONIC_ETH_HW_TSO_IPV6;
1389         if (features & NETIF_F_TSO_ECN)
1390                 wanted |= IONIC_ETH_HW_TSO_ECN;
1391         if (features & NETIF_F_GSO_GRE)
1392                 wanted |= IONIC_ETH_HW_TSO_GRE;
1393         if (features & NETIF_F_GSO_GRE_CSUM)
1394                 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1395         if (features & NETIF_F_GSO_IPXIP4)
1396                 wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1397         if (features & NETIF_F_GSO_IPXIP6)
1398                 wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1399         if (features & NETIF_F_GSO_UDP_TUNNEL)
1400                 wanted |= IONIC_ETH_HW_TSO_UDP;
1401         if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1402                 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1403
1404         return cpu_to_le64(wanted);
1405 }
1406
1407 static int ionic_set_nic_features(struct ionic_lif *lif,
1408                                   netdev_features_t features)
1409 {
1410         struct device *dev = lif->ionic->dev;
1411         struct ionic_admin_ctx ctx = {
1412                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1413                 .cmd.lif_setattr = {
1414                         .opcode = IONIC_CMD_LIF_SETATTR,
1415                         .index = cpu_to_le16(lif->index),
1416                         .attr = IONIC_LIF_ATTR_FEATURES,
1417                 },
1418         };
1419         u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1420                          IONIC_ETH_HW_VLAN_RX_STRIP |
1421                          IONIC_ETH_HW_VLAN_RX_FILTER;
1422         u64 old_hw_features;
1423         int err;
1424
1425         ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
1426
1427         if (lif->phc)
1428                 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);
1429
1430         err = ionic_adminq_post_wait(lif, &ctx);
1431         if (err)
1432                 return err;
1433
1434         old_hw_features = lif->hw_features;
1435         lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1436                                        ctx.comp.lif_setattr.features);
1437
1438         if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1439                 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1440
1441         if ((vlan_flags & features) &&
1442             !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1443                 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1444
1445         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1446                 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1447         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1448                 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1449         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1450                 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1451         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1452                 dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1453         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1454                 dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1455         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1456                 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1457         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1458                 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1459         if (lif->hw_features & IONIC_ETH_HW_TSO)
1460                 dev_dbg(dev, "feature ETH_HW_TSO\n");
1461         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1462                 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1463         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1464                 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1465         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1466                 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1467         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1468                 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1469         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1470                 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1471         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1472                 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1473         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1474                 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1475         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1476                 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
1477         if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
1478                 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");
1479
1480         return 0;
1481 }
1482
1483 static int ionic_init_nic_features(struct ionic_lif *lif)
1484 {
1485         struct net_device *netdev = lif->netdev;
1486         netdev_features_t features;
1487         int err;
1488
1489         /* set up what we expect to support by default */
1490         features = NETIF_F_HW_VLAN_CTAG_TX |
1491                    NETIF_F_HW_VLAN_CTAG_RX |
1492                    NETIF_F_HW_VLAN_CTAG_FILTER |
1493                    NETIF_F_SG |
1494                    NETIF_F_HW_CSUM |
1495                    NETIF_F_RXCSUM |
1496                    NETIF_F_TSO |
1497                    NETIF_F_TSO6 |
1498                    NETIF_F_TSO_ECN;
1499
1500         if (lif->nxqs > 1)
1501                 features |= NETIF_F_RXHASH;
1502
1503         err = ionic_set_nic_features(lif, features);
1504         if (err)
1505                 return err;
1506
1507         /* tell the netdev what we actually can support */
1508         netdev->features |= NETIF_F_HIGHDMA;
1509
1510         if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1511                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1512         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1513                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1514         if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1515                 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1516         if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1517                 netdev->hw_features |= NETIF_F_RXHASH;
1518         if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1519                 netdev->hw_features |= NETIF_F_SG;
1520
1521         if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1522                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1523         if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1524                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
1525         if (lif->hw_features & IONIC_ETH_HW_TSO)
1526                 netdev->hw_enc_features |= NETIF_F_TSO;
1527         if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1528                 netdev->hw_enc_features |= NETIF_F_TSO6;
1529         if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1530                 netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1531         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1532                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1533         if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1534                 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1535         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1536                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1537         if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1538                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1539         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1540                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1541         if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1542                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1543
1544         netdev->hw_features |= netdev->hw_enc_features;
1545         netdev->features |= netdev->hw_features;
1546         netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
1547
1548         netdev->priv_flags |= IFF_UNICAST_FLT |
1549                               IFF_LIVE_ADDR_CHANGE;
1550
1551         return 0;
1552 }
1553
1554 static int ionic_set_features(struct net_device *netdev,
1555                               netdev_features_t features)
1556 {
1557         struct ionic_lif *lif = netdev_priv(netdev);
1558         int err;
1559
1560         netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1561                    __func__, (u64)lif->netdev->features, (u64)features);
1562
1563         err = ionic_set_nic_features(lif, features);
1564
1565         return err;
1566 }
1567
1568 static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1569 {
1570         struct sockaddr *addr = sa;
1571         u8 *mac;
1572         int err;
1573
1574         mac = (u8 *)addr->sa_data;
1575         if (ether_addr_equal(netdev->dev_addr, mac))
1576                 return 0;
1577
1578         err = eth_prepare_mac_addr_change(netdev, addr);
1579         if (err)
1580                 return err;
1581
1582         if (!is_zero_ether_addr(netdev->dev_addr)) {
1583                 netdev_info(netdev, "deleting mac addr %pM\n",
1584                             netdev->dev_addr);
1585                 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr);
1586         }
1587
1588         eth_commit_mac_addr_change(netdev, addr);
1589         netdev_info(netdev, "updating mac addr %pM\n", mac);
1590
1591         return ionic_lif_addr_add(netdev_priv(netdev), mac);
1592 }
1593
1594 static void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1595 {
1596         /* Stop and clean the queues before reconfiguration */
1597         netif_device_detach(lif->netdev);
1598         ionic_stop_queues(lif);
1599         ionic_txrx_deinit(lif);
1600 }
1601
1602 static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1603 {
1604         int err;
1605
1606         /* Re-init the queues after reconfiguration */
1607
1608         /* The only way txrx_init can fail here is if communication
1609          * with FW is suddenly broken.  There's not much we can do
1610          * at this point - error messages have already been printed,
1611          * so we can continue on and the user can eventually do a
1612          * DOWN and UP to try to reset and clear the issue.
1613          */
1614         err = ionic_txrx_init(lif);
1615         ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
1616         netif_device_attach(lif->netdev);
1617
1618         return err;
1619 }
1620
1621 static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1622 {
1623         struct ionic_lif *lif = netdev_priv(netdev);
1624         struct ionic_admin_ctx ctx = {
1625                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1626                 .cmd.lif_setattr = {
1627                         .opcode = IONIC_CMD_LIF_SETATTR,
1628                         .index = cpu_to_le16(lif->index),
1629                         .attr = IONIC_LIF_ATTR_MTU,
1630                         .mtu = cpu_to_le32(new_mtu),
1631                 },
1632         };
1633         int err;
1634
1635         err = ionic_adminq_post_wait(lif, &ctx);
1636         if (err)
1637                 return err;
1638
1639         /* if we're not running, nothing more to do */
1640         if (!netif_running(netdev)) {
1641                 netdev->mtu = new_mtu;
1642                 return 0;
1643         }
1644
1645         mutex_lock(&lif->queue_lock);
1646         ionic_stop_queues_reconfig(lif);
1647         netdev->mtu = new_mtu;
1648         err = ionic_start_queues_reconfig(lif);
1649         mutex_unlock(&lif->queue_lock);
1650
1651         return err;
1652 }
1653
1654 static void ionic_tx_timeout_work(struct work_struct *ws)
1655 {
1656         struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1657
1658         if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1659                 return;
1660
1661         /* if we were stopped before this scheduled job was launched,
1662          * don't bother the queues as they are already stopped.
1663          */
1664         if (!netif_running(lif->netdev))
1665                 return;
1666
1667         mutex_lock(&lif->queue_lock);
1668         ionic_stop_queues_reconfig(lif);
1669         ionic_start_queues_reconfig(lif);
1670         mutex_unlock(&lif->queue_lock);
1671 }
1672
1673 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1674 {
1675         struct ionic_lif *lif = netdev_priv(netdev);
1676
1677         netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
1678         schedule_work(&lif->tx_timeout_work);
1679 }
1680
1681 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1682                                  u16 vid)
1683 {
1684         struct ionic_lif *lif = netdev_priv(netdev);
1685         int err;
1686
1687         err = ionic_lif_vlan_add(lif, vid);
1688         if (err)
1689                 return err;
1690
1691         ionic_lif_rx_mode(lif);
1692
1693         return 0;
1694 }
1695
1696 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1697                                   u16 vid)
1698 {
1699         struct ionic_lif *lif = netdev_priv(netdev);
1700         int err;
1701
1702         err = ionic_lif_vlan_del(lif, vid);
1703         if (err)
1704                 return err;
1705
1706         ionic_lif_rx_mode(lif);
1707
1708         return 0;
1709 }
1710
1711 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1712                          const u8 *key, const u32 *indir)
1713 {
1714         struct ionic_admin_ctx ctx = {
1715                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1716                 .cmd.lif_setattr = {
1717                         .opcode = IONIC_CMD_LIF_SETATTR,
1718                         .attr = IONIC_LIF_ATTR_RSS,
1719                         .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1720                 },
1721         };
1722         unsigned int i, tbl_sz;
1723
1724         if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1725                 lif->rss_types = types;
1726                 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1727         }
1728
1729         if (key)
1730                 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1731
1732         if (indir) {
1733                 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1734                 for (i = 0; i < tbl_sz; i++)
1735                         lif->rss_ind_tbl[i] = indir[i];
1736         }
1737
1738         memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1739                IONIC_RSS_HASH_KEY_SIZE);
1740
1741         return ionic_adminq_post_wait(lif, &ctx);
1742 }
1743
1744 static int ionic_lif_rss_init(struct ionic_lif *lif)
1745 {
1746         unsigned int tbl_sz;
1747         unsigned int i;
1748
1749         lif->rss_types = IONIC_RSS_TYPE_IPV4     |
1750                          IONIC_RSS_TYPE_IPV4_TCP |
1751                          IONIC_RSS_TYPE_IPV4_UDP |
1752                          IONIC_RSS_TYPE_IPV6     |
1753                          IONIC_RSS_TYPE_IPV6_TCP |
1754                          IONIC_RSS_TYPE_IPV6_UDP;
1755
1756         /* Fill indirection table with 'default' values */
1757         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1758         for (i = 0; i < tbl_sz; i++)
1759                 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1760
1761         return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1762 }
1763
1764 static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1765 {
1766         int tbl_sz;
1767
1768         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1769         memset(lif->rss_ind_tbl, 0, tbl_sz);
1770         memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1771
1772         ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1773 }
1774
1775 static void ionic_lif_quiesce(struct ionic_lif *lif)
1776 {
1777         struct ionic_admin_ctx ctx = {
1778                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1779                 .cmd.lif_setattr = {
1780                         .opcode = IONIC_CMD_LIF_SETATTR,
1781                         .index = cpu_to_le16(lif->index),
1782                         .attr = IONIC_LIF_ATTR_STATE,
1783                         .state = IONIC_LIF_QUIESCE,
1784                 },
1785         };
1786         int err;
1787
1788         err = ionic_adminq_post_wait(lif, &ctx);
1789         if (err)
1790                 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err);
1791 }
1792
1793 static void ionic_txrx_disable(struct ionic_lif *lif)
1794 {
1795         unsigned int i;
1796         int err = 0;
1797
1798         if (lif->txqcqs) {
1799                 for (i = 0; i < lif->nxqs; i++)
1800                         err = ionic_qcq_disable(lif, lif->txqcqs[i], err);
1801         }
1802
1803         if (lif->hwstamp_txq)
1804                 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err);
1805
1806         if (lif->rxqcqs) {
1807                 for (i = 0; i < lif->nxqs; i++)
1808                         err = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
1809         }
1810
1811         if (lif->hwstamp_rxq)
1812                 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err);
1813
1814         ionic_lif_quiesce(lif);
1815 }
1816
1817 static void ionic_txrx_deinit(struct ionic_lif *lif)
1818 {
1819         unsigned int i;
1820
1821         if (lif->txqcqs) {
1822                 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
1823                         ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1824                         ionic_tx_flush(&lif->txqcqs[i]->cq);
1825                         ionic_tx_empty(&lif->txqcqs[i]->q);
1826                 }
1827         }
1828
1829         if (lif->rxqcqs) {
1830                 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
1831                         ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
1832                         ionic_rx_empty(&lif->rxqcqs[i]->q);
1833                 }
1834         }
1835         lif->rx_mode = 0;
1836
1837         if (lif->hwstamp_txq) {
1838                 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
1839                 ionic_tx_flush(&lif->hwstamp_txq->cq);
1840                 ionic_tx_empty(&lif->hwstamp_txq->q);
1841         }
1842
1843         if (lif->hwstamp_rxq) {
1844                 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
1845                 ionic_rx_empty(&lif->hwstamp_rxq->q);
1846         }
1847 }
1848
1849 static void ionic_txrx_free(struct ionic_lif *lif)
1850 {
1851         unsigned int i;
1852
1853         if (lif->txqcqs) {
1854                 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
1855                         ionic_qcq_free(lif, lif->txqcqs[i]);
1856                         devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
1857                         lif->txqcqs[i] = NULL;
1858                 }
1859         }
1860
1861         if (lif->rxqcqs) {
1862                 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
1863                         ionic_qcq_free(lif, lif->rxqcqs[i]);
1864                         devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
1865                         lif->rxqcqs[i] = NULL;
1866                 }
1867         }
1868
1869         if (lif->hwstamp_txq) {
1870                 ionic_qcq_free(lif, lif->hwstamp_txq);
1871                 devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
1872                 lif->hwstamp_txq = NULL;
1873         }
1874
1875         if (lif->hwstamp_rxq) {
1876                 ionic_qcq_free(lif, lif->hwstamp_rxq);
1877                 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq);
1878                 lif->hwstamp_rxq = NULL;
1879         }
1880 }
1881
1882 static int ionic_txrx_alloc(struct ionic_lif *lif)
1883 {
1884         unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
1885         unsigned int flags, i;
1886         int err = 0;
1887
1888         num_desc = lif->ntxq_descs;
1889         desc_sz = sizeof(struct ionic_txq_desc);
1890         comp_sz = sizeof(struct ionic_txq_comp);
1891
1892         if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
1893             lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
1894                                           sizeof(struct ionic_txq_sg_desc_v1))
1895                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
1896         else
1897                 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
1898
1899         flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
1900         if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1901                 flags |= IONIC_QCQ_F_INTR;
1902         for (i = 0; i < lif->nxqs; i++) {
1903                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
1904                                       num_desc, desc_sz, comp_sz, sg_desc_sz,
1905                                       lif->kern_pid, &lif->txqcqs[i]);
1906                 if (err)
1907                         goto err_out;
1908
1909                 if (flags & IONIC_QCQ_F_INTR) {
1910                         ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1911                                              lif->txqcqs[i]->intr.index,
1912                                              lif->tx_coalesce_hw);
1913                         if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
1914                                 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
1915                 }
1916
1917                 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
1918         }
1919
1920         flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
1921
1922         num_desc = lif->nrxq_descs;
1923         desc_sz = sizeof(struct ionic_rxq_desc);
1924         comp_sz = sizeof(struct ionic_rxq_comp);
1925         sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
1926
1927         if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC)
1928                 comp_sz *= 2;
1929
1930         for (i = 0; i < lif->nxqs; i++) {
1931                 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
1932                                       num_desc, desc_sz, comp_sz, sg_desc_sz,
1933                                       lif->kern_pid, &lif->rxqcqs[i]);
1934                 if (err)
1935                         goto err_out;
1936
1937                 lif->rxqcqs[i]->q.features = lif->rxq_features;
1938
1939                 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1940                                      lif->rxqcqs[i]->intr.index,
1941                                      lif->rx_coalesce_hw);
1942                 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
1943                         lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
1944
1945                 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1946                         ionic_link_qcq_interrupts(lif->rxqcqs[i],
1947                                                   lif->txqcqs[i]);
1948
1949                 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
1950         }
1951
1952         return 0;
1953
1954 err_out:
1955         ionic_txrx_free(lif);
1956
1957         return err;
1958 }
1959
1960 static int ionic_txrx_init(struct ionic_lif *lif)
1961 {
1962         unsigned int i;
1963         int err;
1964
1965         for (i = 0; i < lif->nxqs; i++) {
1966                 err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
1967                 if (err)
1968                         goto err_out;
1969
1970                 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
1971                 if (err) {
1972                         ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1973                         goto err_out;
1974                 }
1975         }
1976
1977         if (lif->netdev->features & NETIF_F_RXHASH)
1978                 ionic_lif_rss_init(lif);
1979
1980         ionic_lif_rx_mode(lif);
1981
1982         return 0;
1983
1984 err_out:
1985         while (i--) {
1986                 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1987                 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
1988         }
1989
1990         return err;
1991 }
1992
1993 static int ionic_txrx_enable(struct ionic_lif *lif)
1994 {
1995         int derr = 0;
1996         int i, err;
1997
1998         for (i = 0; i < lif->nxqs; i++) {
1999                 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
2000                         dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
2001                         err = -ENXIO;
2002                         goto err_out;
2003                 }
2004
2005                 ionic_rx_fill(&lif->rxqcqs[i]->q);
2006                 err = ionic_qcq_enable(lif->rxqcqs[i]);
2007                 if (err)
2008                         goto err_out;
2009
2010                 err = ionic_qcq_enable(lif->txqcqs[i]);
2011                 if (err) {
2012                         derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err);
2013                         goto err_out;
2014                 }
2015         }
2016
2017         if (lif->hwstamp_rxq) {
2018                 ionic_rx_fill(&lif->hwstamp_rxq->q);
2019                 err = ionic_qcq_enable(lif->hwstamp_rxq);
2020                 if (err)
2021                         goto err_out_hwstamp_rx;
2022         }
2023
2024         if (lif->hwstamp_txq) {
2025                 err = ionic_qcq_enable(lif->hwstamp_txq);
2026                 if (err)
2027                         goto err_out_hwstamp_tx;
2028         }
2029
2030         return 0;
2031
2032 err_out_hwstamp_tx:
2033         if (lif->hwstamp_rxq)
2034                 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr);
2035 err_out_hwstamp_rx:
2036         i = lif->nxqs;
2037 err_out:
2038         while (i--) {
2039                 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr);
2040                 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr);
2041         }
2042
2043         return err;
2044 }
2045
2046 static int ionic_start_queues(struct ionic_lif *lif)
2047 {
2048         int err;
2049
2050         if (test_bit(IONIC_LIF_F_BROKEN, lif->state))
2051                 return -EIO;
2052
2053         if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2054                 return -EBUSY;
2055
2056         if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
2057                 return 0;
2058
2059         err = ionic_txrx_enable(lif);
2060         if (err) {
2061                 clear_bit(IONIC_LIF_F_UP, lif->state);
2062                 return err;
2063         }
2064         netif_tx_wake_all_queues(lif->netdev);
2065
2066         return 0;
2067 }
2068
2069 static int ionic_open(struct net_device *netdev)
2070 {
2071         struct ionic_lif *lif = netdev_priv(netdev);
2072         int err;
2073
2074         /* If recovering from a broken state, clear the bit and we'll try again */
2075         if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state))
2076                 netdev_info(netdev, "clearing broken state\n");
2077
2078         mutex_lock(&lif->queue_lock);
2079
2080         err = ionic_txrx_alloc(lif);
2081         if (err)
2082                 goto err_unlock;
2083
2084         err = ionic_txrx_init(lif);
2085         if (err)
2086                 goto err_txrx_free;
2087
2088         err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
2089         if (err)
2090                 goto err_txrx_deinit;
2091
2092         err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
2093         if (err)
2094                 goto err_txrx_deinit;
2095
2096         /* don't start the queues until we have link */
2097         if (netif_carrier_ok(netdev)) {
2098                 err = ionic_start_queues(lif);
2099                 if (err)
2100                         goto err_txrx_deinit;
2101         }
2102
2103         /* If hardware timestamping is enabled, but the queues were freed by
2104          * ionic_stop, those need to be reallocated and initialized, too.
2105          */
2106         ionic_lif_hwstamp_recreate_queues(lif);
2107
2108         mutex_unlock(&lif->queue_lock);
2109
2110         return 0;
2111
2112 err_txrx_deinit:
2113         ionic_txrx_deinit(lif);
2114 err_txrx_free:
2115         ionic_txrx_free(lif);
2116 err_unlock:
2117         mutex_unlock(&lif->queue_lock);
2118         return err;
2119 }
2120
2121 static void ionic_stop_queues(struct ionic_lif *lif)
2122 {
2123         if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
2124                 return;
2125
2126         netif_tx_disable(lif->netdev);
2127         ionic_txrx_disable(lif);
2128 }
2129
2130 static int ionic_stop(struct net_device *netdev)
2131 {
2132         struct ionic_lif *lif = netdev_priv(netdev);
2133
2134         if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2135                 return 0;
2136
2137         mutex_lock(&lif->queue_lock);
2138         ionic_stop_queues(lif);
2139         ionic_txrx_deinit(lif);
2140         ionic_txrx_free(lif);
2141         mutex_unlock(&lif->queue_lock);
2142
2143         return 0;
2144 }
2145
2146 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2147 {
2148         struct ionic_lif *lif = netdev_priv(netdev);
2149
2150         switch (cmd) {
2151         case SIOCSHWTSTAMP:
2152                 return ionic_lif_hwstamp_set(lif, ifr);
2153         case SIOCGHWTSTAMP:
2154                 return ionic_lif_hwstamp_get(lif, ifr);
2155         default:
2156                 return -EOPNOTSUPP;
2157         }
2158 }
2159
2160 static int ionic_update_cached_vf_config(struct ionic *ionic, int vf)
2161 {
2162         struct ionic_vf_getattr_comp comp = { 0 };
2163         int err;
2164         u8 attr;
2165
2166         attr = IONIC_VF_ATTR_VLAN;
2167         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2168         if (err && comp.status != IONIC_RC_ENOSUPP)
2169                 goto err_out;
2170         if (!err)
2171                 ionic->vfs[vf].vlanid = comp.vlanid;
2172
2173         attr = IONIC_VF_ATTR_SPOOFCHK;
2174         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2175         if (err && comp.status != IONIC_RC_ENOSUPP)
2176                 goto err_out;
2177         if (!err)
2178                 ionic->vfs[vf].spoofchk = comp.spoofchk;
2179
2180         attr = IONIC_VF_ATTR_LINKSTATE;
2181         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2182         if (err && comp.status != IONIC_RC_ENOSUPP)
2183                 goto err_out;
2184         if (!err) {
2185                 switch (comp.linkstate) {
2186                 case IONIC_VF_LINK_STATUS_UP:
2187                         ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_ENABLE;
2188                         break;
2189                 case IONIC_VF_LINK_STATUS_DOWN:
2190                         ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_DISABLE;
2191                         break;
2192                 case IONIC_VF_LINK_STATUS_AUTO:
2193                         ionic->vfs[vf].linkstate = IFLA_VF_LINK_STATE_AUTO;
2194                         break;
2195                 default:
2196                         dev_warn(ionic->dev, "Unexpected link state %u\n", comp.linkstate);
2197                         break;
2198                 }
2199         }
2200
2201         attr = IONIC_VF_ATTR_RATE;
2202         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2203         if (err && comp.status != IONIC_RC_ENOSUPP)
2204                 goto err_out;
2205         if (!err)
2206                 ionic->vfs[vf].maxrate = comp.maxrate;
2207
2208         attr = IONIC_VF_ATTR_TRUST;
2209         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2210         if (err && comp.status != IONIC_RC_ENOSUPP)
2211                 goto err_out;
2212         if (!err)
2213                 ionic->vfs[vf].trusted = comp.trust;
2214
2215         attr = IONIC_VF_ATTR_MAC;
2216         err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp);
2217         if (err && comp.status != IONIC_RC_ENOSUPP)
2218                 goto err_out;
2219         if (!err)
2220                 ether_addr_copy(ionic->vfs[vf].macaddr, comp.macaddr);
2221
2222 err_out:
2223         if (err)
2224                 dev_err(ionic->dev, "Failed to get %s for VF %d\n",
2225                         ionic_vf_attr_to_str(attr), vf);
2226
2227         return err;
2228 }
2229
2230 static int ionic_get_vf_config(struct net_device *netdev,
2231                                int vf, struct ifla_vf_info *ivf)
2232 {
2233         struct ionic_lif *lif = netdev_priv(netdev);
2234         struct ionic *ionic = lif->ionic;
2235         int ret = 0;
2236
2237         if (!netif_device_present(netdev))
2238                 return -EBUSY;
2239
2240         down_read(&ionic->vf_op_lock);
2241
2242         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2243                 ret = -EINVAL;
2244         } else {
2245                 ivf->vf = vf;
2246                 ivf->qos = 0;
2247
2248                 ret = ionic_update_cached_vf_config(ionic, vf);
2249                 if (!ret) {
2250                         ivf->vlan         = le16_to_cpu(ionic->vfs[vf].vlanid);
2251                         ivf->spoofchk     = ionic->vfs[vf].spoofchk;
2252                         ivf->linkstate    = ionic->vfs[vf].linkstate;
2253                         ivf->max_tx_rate  = le32_to_cpu(ionic->vfs[vf].maxrate);
2254                         ivf->trusted      = ionic->vfs[vf].trusted;
2255                         ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr);
2256                 }
2257         }
2258
2259         up_read(&ionic->vf_op_lock);
2260         return ret;
2261 }
2262
2263 static int ionic_get_vf_stats(struct net_device *netdev, int vf,
2264                               struct ifla_vf_stats *vf_stats)
2265 {
2266         struct ionic_lif *lif = netdev_priv(netdev);
2267         struct ionic *ionic = lif->ionic;
2268         struct ionic_lif_stats *vs;
2269         int ret = 0;
2270
2271         if (!netif_device_present(netdev))
2272                 return -EBUSY;
2273
2274         down_read(&ionic->vf_op_lock);
2275
2276         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2277                 ret = -EINVAL;
2278         } else {
2279                 memset(vf_stats, 0, sizeof(*vf_stats));
2280                 vs = &ionic->vfs[vf].stats;
2281
2282                 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
2283                 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
2284                 vf_stats->rx_bytes   = le64_to_cpu(vs->rx_ucast_bytes);
2285                 vf_stats->tx_bytes   = le64_to_cpu(vs->tx_ucast_bytes);
2286                 vf_stats->broadcast  = le64_to_cpu(vs->rx_bcast_packets);
2287                 vf_stats->multicast  = le64_to_cpu(vs->rx_mcast_packets);
2288                 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
2289                                        le64_to_cpu(vs->rx_mcast_drop_packets) +
2290                                        le64_to_cpu(vs->rx_bcast_drop_packets);
2291                 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
2292                                        le64_to_cpu(vs->tx_mcast_drop_packets) +
2293                                        le64_to_cpu(vs->tx_bcast_drop_packets);
2294         }
2295
2296         up_read(&ionic->vf_op_lock);
2297         return ret;
2298 }
2299
2300 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
2301 {
2302         struct ionic_lif *lif = netdev_priv(netdev);
2303         struct ionic *ionic = lif->ionic;
2304         int ret;
2305
2306         if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
2307                 return -EINVAL;
2308
2309         if (!netif_device_present(netdev))
2310                 return -EBUSY;
2311
2312         down_write(&ionic->vf_op_lock);
2313
2314         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2315                 ret = -EINVAL;
2316         } else {
2317                 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac);
2318                 if (!ret)
2319                         ether_addr_copy(ionic->vfs[vf].macaddr, mac);
2320         }
2321
2322         up_write(&ionic->vf_op_lock);
2323         return ret;
2324 }
2325
2326 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2327                              u8 qos, __be16 proto)
2328 {
2329         struct ionic_lif *lif = netdev_priv(netdev);
2330         struct ionic *ionic = lif->ionic;
2331         int ret;
2332
2333         /* until someday when we support qos */
2334         if (qos)
2335                 return -EINVAL;
2336
2337         if (vlan > 4095)
2338                 return -EINVAL;
2339
2340         if (proto != htons(ETH_P_8021Q))
2341                 return -EPROTONOSUPPORT;
2342
2343         if (!netif_device_present(netdev))
2344                 return -EBUSY;
2345
2346         down_write(&ionic->vf_op_lock);
2347
2348         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2349                 ret = -EINVAL;
2350         } else {
2351                 ret = ionic_set_vf_config(ionic, vf,
2352                                           IONIC_VF_ATTR_VLAN, (u8 *)&vlan);
2353                 if (!ret)
2354                         ionic->vfs[vf].vlanid = cpu_to_le16(vlan);
2355         }
2356
2357         up_write(&ionic->vf_op_lock);
2358         return ret;
2359 }
2360
2361 static int ionic_set_vf_rate(struct net_device *netdev, int vf,
2362                              int tx_min, int tx_max)
2363 {
2364         struct ionic_lif *lif = netdev_priv(netdev);
2365         struct ionic *ionic = lif->ionic;
2366         int ret;
2367
2368         /* setting the min just seems silly */
2369         if (tx_min)
2370                 return -EINVAL;
2371
2372         if (!netif_device_present(netdev))
2373                 return -EBUSY;
2374
2375         down_write(&ionic->vf_op_lock);
2376
2377         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2378                 ret = -EINVAL;
2379         } else {
2380                 ret = ionic_set_vf_config(ionic, vf,
2381                                           IONIC_VF_ATTR_RATE, (u8 *)&tx_max);
2382                 if (!ret)
2383                         lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max);
2384         }
2385
2386         up_write(&ionic->vf_op_lock);
2387         return ret;
2388 }
2389
2390 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
2391 {
2392         struct ionic_lif *lif = netdev_priv(netdev);
2393         struct ionic *ionic = lif->ionic;
2394         u8 data = set;  /* convert to u8 for config */
2395         int ret;
2396
2397         if (!netif_device_present(netdev))
2398                 return -EBUSY;
2399
2400         down_write(&ionic->vf_op_lock);
2401
2402         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2403                 ret = -EINVAL;
2404         } else {
2405                 ret = ionic_set_vf_config(ionic, vf,
2406                                           IONIC_VF_ATTR_SPOOFCHK, &data);
2407                 if (!ret)
2408                         ionic->vfs[vf].spoofchk = data;
2409         }
2410
2411         up_write(&ionic->vf_op_lock);
2412         return ret;
2413 }
2414
2415 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
2416 {
2417         struct ionic_lif *lif = netdev_priv(netdev);
2418         struct ionic *ionic = lif->ionic;
2419         u8 data = set;  /* convert to u8 for config */
2420         int ret;
2421
2422         if (!netif_device_present(netdev))
2423                 return -EBUSY;
2424
2425         down_write(&ionic->vf_op_lock);
2426
2427         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2428                 ret = -EINVAL;
2429         } else {
2430                 ret = ionic_set_vf_config(ionic, vf,
2431                                           IONIC_VF_ATTR_TRUST, &data);
2432                 if (!ret)
2433                         ionic->vfs[vf].trusted = data;
2434         }
2435
2436         up_write(&ionic->vf_op_lock);
2437         return ret;
2438 }
2439
2440 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
2441 {
2442         struct ionic_lif *lif = netdev_priv(netdev);
2443         struct ionic *ionic = lif->ionic;
2444         u8 data;
2445         int ret;
2446
2447         switch (set) {
2448         case IFLA_VF_LINK_STATE_ENABLE:
2449                 data = IONIC_VF_LINK_STATUS_UP;
2450                 break;
2451         case IFLA_VF_LINK_STATE_DISABLE:
2452                 data = IONIC_VF_LINK_STATUS_DOWN;
2453                 break;
2454         case IFLA_VF_LINK_STATE_AUTO:
2455                 data = IONIC_VF_LINK_STATUS_AUTO;
2456                 break;
2457         default:
2458                 return -EINVAL;
2459         }
2460
2461         if (!netif_device_present(netdev))
2462                 return -EBUSY;
2463
2464         down_write(&ionic->vf_op_lock);
2465
2466         if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2467                 ret = -EINVAL;
2468         } else {
2469                 ret = ionic_set_vf_config(ionic, vf,
2470                                           IONIC_VF_ATTR_LINKSTATE, &data);
2471                 if (!ret)
2472                         ionic->vfs[vf].linkstate = set;
2473         }
2474
2475         up_write(&ionic->vf_op_lock);
2476         return ret;
2477 }
2478
2479 static const struct net_device_ops ionic_netdev_ops = {
2480         .ndo_open               = ionic_open,
2481         .ndo_stop               = ionic_stop,
2482         .ndo_eth_ioctl          = ionic_eth_ioctl,
2483         .ndo_start_xmit         = ionic_start_xmit,
2484         .ndo_get_stats64        = ionic_get_stats64,
2485         .ndo_set_rx_mode        = ionic_ndo_set_rx_mode,
2486         .ndo_set_features       = ionic_set_features,
2487         .ndo_set_mac_address    = ionic_set_mac_address,
2488         .ndo_validate_addr      = eth_validate_addr,
2489         .ndo_tx_timeout         = ionic_tx_timeout,
2490         .ndo_change_mtu         = ionic_change_mtu,
2491         .ndo_vlan_rx_add_vid    = ionic_vlan_rx_add_vid,
2492         .ndo_vlan_rx_kill_vid   = ionic_vlan_rx_kill_vid,
2493         .ndo_set_vf_vlan        = ionic_set_vf_vlan,
2494         .ndo_set_vf_trust       = ionic_set_vf_trust,
2495         .ndo_set_vf_mac         = ionic_set_vf_mac,
2496         .ndo_set_vf_rate        = ionic_set_vf_rate,
2497         .ndo_set_vf_spoofchk    = ionic_set_vf_spoofchk,
2498         .ndo_get_vf_config      = ionic_get_vf_config,
2499         .ndo_set_vf_link_state  = ionic_set_vf_link_state,
2500         .ndo_get_vf_stats       = ionic_get_vf_stats,
2501 };
2502
2503 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b)
2504 {
2505         /* only swapping the queues, not the napi, flags, or other stuff */
2506         swap(a->q.features,   b->q.features);
2507         swap(a->q.num_descs,  b->q.num_descs);
2508         swap(a->q.desc_size,  b->q.desc_size);
2509         swap(a->q.base,       b->q.base);
2510         swap(a->q.base_pa,    b->q.base_pa);
2511         swap(a->q.info,       b->q.info);
2512         swap(a->q_base,       b->q_base);
2513         swap(a->q_base_pa,    b->q_base_pa);
2514         swap(a->q_size,       b->q_size);
2515
2516         swap(a->q.sg_desc_size, b->q.sg_desc_size);
2517         swap(a->q.sg_base,    b->q.sg_base);
2518         swap(a->q.sg_base_pa, b->q.sg_base_pa);
2519         swap(a->sg_base,      b->sg_base);
2520         swap(a->sg_base_pa,   b->sg_base_pa);
2521         swap(a->sg_size,      b->sg_size);
2522
2523         swap(a->cq.num_descs, b->cq.num_descs);
2524         swap(a->cq.desc_size, b->cq.desc_size);
2525         swap(a->cq.base,      b->cq.base);
2526         swap(a->cq.base_pa,   b->cq.base_pa);
2527         swap(a->cq.info,      b->cq.info);
2528         swap(a->cq_base,      b->cq_base);
2529         swap(a->cq_base_pa,   b->cq_base_pa);
2530         swap(a->cq_size,      b->cq_size);
2531
2532         ionic_debugfs_del_qcq(a);
2533         ionic_debugfs_add_qcq(a->q.lif, a);
2534 }
2535
2536 int ionic_reconfigure_queues(struct ionic_lif *lif,
2537                              struct ionic_queue_params *qparam)
2538 {
2539         unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz;
2540         struct ionic_qcq **tx_qcqs = NULL;
2541         struct ionic_qcq **rx_qcqs = NULL;
2542         unsigned int flags, i;
2543         int err = 0;
2544
2545         /* allocate temporary qcq arrays to hold new queue structs */
2546         if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2547                 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
2548                                        sizeof(struct ionic_qcq *), GFP_KERNEL);
2549                 if (!tx_qcqs) {
2550                         err = -ENOMEM;
2551                         goto err_out;
2552                 }
2553         }
2554         if (qparam->nxqs != lif->nxqs ||
2555             qparam->nrxq_descs != lif->nrxq_descs ||
2556             qparam->rxq_features != lif->rxq_features) {
2557                 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
2558                                        sizeof(struct ionic_qcq *), GFP_KERNEL);
2559                 if (!rx_qcqs) {
2560                         err = -ENOMEM;
2561                         goto err_out;
2562                 }
2563         }
2564
2565         /* allocate new desc_info and rings, but leave the interrupt setup
2566          * until later so as to not mess with the still-running queues
2567          */
2568         if (tx_qcqs) {
2569                 num_desc = qparam->ntxq_descs;
2570                 desc_sz = sizeof(struct ionic_txq_desc);
2571                 comp_sz = sizeof(struct ionic_txq_comp);
2572
2573                 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2574                     lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2575                     sizeof(struct ionic_txq_sg_desc_v1))
2576                         sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2577                 else
2578                         sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2579
2580                 for (i = 0; i < qparam->nxqs; i++) {
2581                         flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2582                         err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2583                                               num_desc, desc_sz, comp_sz, sg_desc_sz,
2584                                               lif->kern_pid, &tx_qcqs[i]);
2585                         if (err)
2586                                 goto err_out;
2587                 }
2588         }
2589
2590         if (rx_qcqs) {
2591                 num_desc = qparam->nrxq_descs;
2592                 desc_sz = sizeof(struct ionic_rxq_desc);
2593                 comp_sz = sizeof(struct ionic_rxq_comp);
2594                 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);
2595
2596                 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC)
2597                         comp_sz *= 2;
2598
2599                 for (i = 0; i < qparam->nxqs; i++) {
2600                         flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2601                         err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
2602                                               num_desc, desc_sz, comp_sz, sg_desc_sz,
2603                                               lif->kern_pid, &rx_qcqs[i]);
2604                         if (err)
2605                                 goto err_out;
2606
2607                         rx_qcqs[i]->q.features = qparam->rxq_features;
2608                 }
2609         }
2610
2611         /* stop and clean the queues */
2612         ionic_stop_queues_reconfig(lif);
2613
2614         if (qparam->nxqs != lif->nxqs) {
2615                 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
2616                 if (err)
2617                         goto err_out_reinit_unlock;
2618                 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
2619                 if (err) {
2620                         netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
2621                         goto err_out_reinit_unlock;
2622                 }
2623         }
2624
2625         /* swap new desc_info and rings, keeping existing interrupt config */
2626         if (tx_qcqs) {
2627                 lif->ntxq_descs = qparam->ntxq_descs;
2628                 for (i = 0; i < qparam->nxqs; i++)
2629                         ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
2630         }
2631
2632         if (rx_qcqs) {
2633                 lif->nrxq_descs = qparam->nrxq_descs;
2634                 for (i = 0; i < qparam->nxqs; i++)
2635                         ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
2636         }
2637
2638         /* if we need to change the interrupt layout, this is the time */
2639         if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
2640             qparam->nxqs != lif->nxqs) {
2641                 if (qparam->intr_split) {
2642                         set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2643                 } else {
2644                         clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2645                         lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2646                         lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2647                 }
2648
2649                 /* clear existing interrupt assignments */
2650                 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
2651                         ionic_qcq_intr_free(lif, lif->txqcqs[i]);
2652                         ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
2653                 }
2654
2655                 /* re-assign the interrupts */
2656                 for (i = 0; i < qparam->nxqs; i++) {
2657                         lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2658                         err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
2659                         ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2660                                              lif->rxqcqs[i]->intr.index,
2661                                              lif->rx_coalesce_hw);
2662
2663                         if (qparam->intr_split) {
2664                                 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2665                                 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
2666                                 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2667                                                      lif->txqcqs[i]->intr.index,
2668                                                      lif->tx_coalesce_hw);
2669                                 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2670                                         lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2671                         } else {
2672                                 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2673                                 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
2674                         }
2675                 }
2676         }
2677
2678         /* now we can rework the debugfs mappings */
2679         if (tx_qcqs) {
2680                 for (i = 0; i < qparam->nxqs; i++) {
2681                         ionic_debugfs_del_qcq(lif->txqcqs[i]);
2682                         ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2683                 }
2684         }
2685
2686         if (rx_qcqs) {
2687                 for (i = 0; i < qparam->nxqs; i++) {
2688                         ionic_debugfs_del_qcq(lif->rxqcqs[i]);
2689                         ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2690                 }
2691         }
2692
2693         swap(lif->nxqs, qparam->nxqs);
2694         swap(lif->rxq_features, qparam->rxq_features);
2695
2696 err_out_reinit_unlock:
2697         /* re-init the queues, but don't lose an error code */
2698         if (err)
2699                 ionic_start_queues_reconfig(lif);
2700         else
2701                 err = ionic_start_queues_reconfig(lif);
2702
2703 err_out:
2704         /* free old allocs without cleaning intr */
2705         for (i = 0; i < qparam->nxqs; i++) {
2706                 if (tx_qcqs && tx_qcqs[i]) {
2707                         tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2708                         ionic_qcq_free(lif, tx_qcqs[i]);
2709                         devm_kfree(lif->ionic->dev, tx_qcqs[i]);
2710                         tx_qcqs[i] = NULL;
2711                 }
2712                 if (rx_qcqs && rx_qcqs[i]) {
2713                         rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2714                         ionic_qcq_free(lif, rx_qcqs[i]);
2715                         devm_kfree(lif->ionic->dev, rx_qcqs[i]);
2716                         rx_qcqs[i] = NULL;
2717                 }
2718         }
2719
2720         /* free q array */
2721         if (rx_qcqs) {
2722                 devm_kfree(lif->ionic->dev, rx_qcqs);
2723                 rx_qcqs = NULL;
2724         }
2725         if (tx_qcqs) {
2726                 devm_kfree(lif->ionic->dev, tx_qcqs);
2727                 tx_qcqs = NULL;
2728         }
2729
2730         /* clean the unused dma and info allocations when new set is smaller
2731          * than the full array, but leave the qcq shells in place
2732          */
2733         for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
2734                 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2735                 ionic_qcq_free(lif, lif->txqcqs[i]);
2736
2737                 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2738                 ionic_qcq_free(lif, lif->rxqcqs[i]);
2739         }
2740
2741         if (err)
2742                 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err);
2743
2744         return err;
2745 }
2746
2747 int ionic_lif_alloc(struct ionic *ionic)
2748 {
2749         struct device *dev = ionic->dev;
2750         union ionic_lif_identity *lid;
2751         struct net_device *netdev;
2752         struct ionic_lif *lif;
2753         int tbl_sz;
2754         int err;
2755
2756         lid = kzalloc(sizeof(*lid), GFP_KERNEL);
2757         if (!lid)
2758                 return -ENOMEM;
2759
2760         netdev = alloc_etherdev_mqs(sizeof(*lif),
2761                                     ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
2762         if (!netdev) {
2763                 dev_err(dev, "Cannot allocate netdev, aborting\n");
2764                 err = -ENOMEM;
2765                 goto err_out_free_lid;
2766         }
2767
2768         SET_NETDEV_DEV(netdev, dev);
2769
2770         lif = netdev_priv(netdev);
2771         lif->netdev = netdev;
2772         ionic->lif = lif;
2773         netdev->netdev_ops = &ionic_netdev_ops;
2774         ionic_ethtool_set_ops(netdev);
2775
2776         netdev->watchdog_timeo = 2 * HZ;
2777         netif_carrier_off(netdev);
2778
2779         lif->identity = lid;
2780         lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
2781         err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
2782         if (err) {
2783                 dev_err(ionic->dev, "Cannot identify type %d: %d\n",
2784                         lif->lif_type, err);
2785                 goto err_out_free_netdev;
2786         }
2787         lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
2788                                      le32_to_cpu(lif->identity->eth.min_frame_size));
2789         lif->netdev->max_mtu =
2790                 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN;
2791
2792         lif->neqs = ionic->neqs_per_lif;
2793         lif->nxqs = ionic->ntxqs_per_lif;
2794
2795         lif->ionic = ionic;
2796         lif->index = 0;
2797
2798         if (is_kdump_kernel()) {
2799                 lif->ntxq_descs = IONIC_MIN_TXRX_DESC;
2800                 lif->nrxq_descs = IONIC_MIN_TXRX_DESC;
2801         } else {
2802                 lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
2803                 lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
2804         }
2805
2806         /* Convert the default coalesce value to actual hw resolution */
2807         lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
2808         lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
2809                                                     lif->rx_coalesce_usecs);
2810         lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2811         lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2812         set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
2813         set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
2814
2815         snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
2816
2817         mutex_init(&lif->queue_lock);
2818         mutex_init(&lif->config_lock);
2819
2820         spin_lock_init(&lif->adminq_lock);
2821
2822         spin_lock_init(&lif->deferred.lock);
2823         INIT_LIST_HEAD(&lif->deferred.list);
2824         INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
2825
2826         /* allocate lif info */
2827         lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
2828         lif->info = dma_alloc_coherent(dev, lif->info_sz,
2829                                        &lif->info_pa, GFP_KERNEL);
2830         if (!lif->info) {
2831                 dev_err(dev, "Failed to allocate lif info, aborting\n");
2832                 err = -ENOMEM;
2833                 goto err_out_free_mutex;
2834         }
2835
2836         ionic_debugfs_add_lif(lif);
2837
2838         /* allocate control queues and txrx queue arrays */
2839         ionic_lif_queue_identify(lif);
2840         err = ionic_qcqs_alloc(lif);
2841         if (err)
2842                 goto err_out_free_lif_info;
2843
2844         /* allocate rss indirection table */
2845         tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
2846         lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
2847         lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
2848                                               &lif->rss_ind_tbl_pa,
2849                                               GFP_KERNEL);
2850
2851         if (!lif->rss_ind_tbl) {
2852                 err = -ENOMEM;
2853                 dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
2854                 goto err_out_free_qcqs;
2855         }
2856         netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
2857
2858         ionic_lif_alloc_phc(lif);
2859
2860         return 0;
2861
2862 err_out_free_qcqs:
2863         ionic_qcqs_free(lif);
2864 err_out_free_lif_info:
2865         dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2866         lif->info = NULL;
2867         lif->info_pa = 0;
2868 err_out_free_mutex:
2869         mutex_destroy(&lif->config_lock);
2870         mutex_destroy(&lif->queue_lock);
2871 err_out_free_netdev:
2872         free_netdev(lif->netdev);
2873         lif = NULL;
2874 err_out_free_lid:
2875         kfree(lid);
2876
2877         return err;
2878 }
2879
2880 static void ionic_lif_reset(struct ionic_lif *lif)
2881 {
2882         struct ionic_dev *idev = &lif->ionic->idev;
2883
2884         mutex_lock(&lif->ionic->dev_cmd_lock);
2885         ionic_dev_cmd_lif_reset(idev, lif->index);
2886         ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2887         mutex_unlock(&lif->ionic->dev_cmd_lock);
2888 }
2889
2890 static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
2891 {
2892         struct ionic *ionic = lif->ionic;
2893
2894         if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
2895                 return;
2896
2897         dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
2898
2899         netif_device_detach(lif->netdev);
2900
2901         mutex_lock(&lif->queue_lock);
2902         if (test_bit(IONIC_LIF_F_UP, lif->state)) {
2903                 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
2904                 ionic_stop_queues(lif);
2905         }
2906
2907         if (netif_running(lif->netdev)) {
2908                 ionic_txrx_deinit(lif);
2909                 ionic_txrx_free(lif);
2910         }
2911         ionic_lif_deinit(lif);
2912         ionic_reset(ionic);
2913         ionic_qcqs_free(lif);
2914
2915         mutex_unlock(&lif->queue_lock);
2916
2917         clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state);
2918         dev_info(ionic->dev, "FW Down: LIFs stopped\n");
2919 }
2920
2921 static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
2922 {
2923         struct ionic *ionic = lif->ionic;
2924         int err;
2925
2926         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2927                 return;
2928
2929         dev_info(ionic->dev, "FW Up: restarting LIFs\n");
2930
2931         ionic_init_devinfo(ionic);
2932         err = ionic_identify(ionic);
2933         if (err)
2934                 goto err_out;
2935         err = ionic_port_identify(ionic);
2936         if (err)
2937                 goto err_out;
2938         err = ionic_port_init(ionic);
2939         if (err)
2940                 goto err_out;
2941
2942         mutex_lock(&lif->queue_lock);
2943
2944         err = ionic_qcqs_alloc(lif);
2945         if (err)
2946                 goto err_unlock;
2947
2948         err = ionic_lif_init(lif);
2949         if (err)
2950                 goto err_qcqs_free;
2951
2952         if (lif->registered)
2953                 ionic_lif_set_netdev_info(lif);
2954
2955         ionic_rx_filter_replay(lif);
2956
2957         if (netif_running(lif->netdev)) {
2958                 err = ionic_txrx_alloc(lif);
2959                 if (err)
2960                         goto err_lifs_deinit;
2961
2962                 err = ionic_txrx_init(lif);
2963                 if (err)
2964                         goto err_txrx_free;
2965         }
2966
2967         mutex_unlock(&lif->queue_lock);
2968
2969         clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
2970         ionic_link_status_check_request(lif, CAN_SLEEP);
2971         netif_device_attach(lif->netdev);
2972         dev_info(ionic->dev, "FW Up: LIFs restarted\n");
2973
2974         /* restore the hardware timestamping queues */
2975         ionic_lif_hwstamp_replay(lif);
2976
2977         return;
2978
2979 err_txrx_free:
2980         ionic_txrx_free(lif);
2981 err_lifs_deinit:
2982         ionic_lif_deinit(lif);
2983 err_qcqs_free:
2984         ionic_qcqs_free(lif);
2985 err_unlock:
2986         mutex_unlock(&lif->queue_lock);
2987 err_out:
2988         dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
2989 }
2990
2991 void ionic_lif_free(struct ionic_lif *lif)
2992 {
2993         struct device *dev = lif->ionic->dev;
2994
2995         ionic_lif_free_phc(lif);
2996
2997         /* free rss indirection table */
2998         dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
2999                           lif->rss_ind_tbl_pa);
3000         lif->rss_ind_tbl = NULL;
3001         lif->rss_ind_tbl_pa = 0;
3002
3003         /* free queues */
3004         ionic_qcqs_free(lif);
3005         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
3006                 ionic_lif_reset(lif);
3007
3008         /* free lif info */
3009         kfree(lif->identity);
3010         dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
3011         lif->info = NULL;
3012         lif->info_pa = 0;
3013
3014         /* unmap doorbell page */
3015         ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3016         lif->kern_dbpage = NULL;
3017
3018         mutex_destroy(&lif->config_lock);
3019         mutex_destroy(&lif->queue_lock);
3020
3021         /* free netdev & lif */
3022         ionic_debugfs_del_lif(lif);
3023         free_netdev(lif->netdev);
3024 }
3025
3026 void ionic_lif_deinit(struct ionic_lif *lif)
3027 {
3028         if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
3029                 return;
3030
3031         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3032                 cancel_work_sync(&lif->deferred.work);
3033                 cancel_work_sync(&lif->tx_timeout_work);
3034                 ionic_rx_filters_deinit(lif);
3035                 if (lif->netdev->features & NETIF_F_RXHASH)
3036                         ionic_lif_rss_deinit(lif);
3037         }
3038
3039         napi_disable(&lif->adminqcq->napi);
3040         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3041         ionic_lif_qcq_deinit(lif, lif->adminqcq);
3042
3043         ionic_lif_reset(lif);
3044 }
3045
3046 static int ionic_lif_adminq_init(struct ionic_lif *lif)
3047 {
3048         struct device *dev = lif->ionic->dev;
3049         struct ionic_q_init_comp comp;
3050         struct ionic_dev *idev;
3051         struct ionic_qcq *qcq;
3052         struct ionic_queue *q;
3053         int err;
3054
3055         idev = &lif->ionic->idev;
3056         qcq = lif->adminqcq;
3057         q = &qcq->q;
3058
3059         mutex_lock(&lif->ionic->dev_cmd_lock);
3060         ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
3061         err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3062         ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3063         mutex_unlock(&lif->ionic->dev_cmd_lock);
3064         if (err) {
3065                 netdev_err(lif->netdev, "adminq init failed %d\n", err);
3066                 return err;
3067         }
3068
3069         q->hw_type = comp.hw_type;
3070         q->hw_index = le32_to_cpu(comp.hw_index);
3071         q->dbval = IONIC_DBELL_QID(q->hw_index);
3072
3073         dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
3074         dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
3075
3076         netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
3077                        NAPI_POLL_WEIGHT);
3078
3079         napi_enable(&qcq->napi);
3080
3081         if (qcq->flags & IONIC_QCQ_F_INTR)
3082                 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
3083                                 IONIC_INTR_MASK_CLEAR);
3084
3085         qcq->flags |= IONIC_QCQ_F_INITED;
3086
3087         return 0;
3088 }
3089
3090 static int ionic_lif_notifyq_init(struct ionic_lif *lif)
3091 {
3092         struct ionic_qcq *qcq = lif->notifyqcq;
3093         struct device *dev = lif->ionic->dev;
3094         struct ionic_queue *q = &qcq->q;
3095         int err;
3096
3097         struct ionic_admin_ctx ctx = {
3098                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3099                 .cmd.q_init = {
3100                         .opcode = IONIC_CMD_Q_INIT,
3101                         .lif_index = cpu_to_le16(lif->index),
3102                         .type = q->type,
3103                         .ver = lif->qtype_info[q->type].version,
3104                         .index = cpu_to_le32(q->index),
3105                         .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
3106                                              IONIC_QINIT_F_ENA),
3107                         .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
3108                         .pid = cpu_to_le16(q->pid),
3109                         .ring_size = ilog2(q->num_descs),
3110                         .ring_base = cpu_to_le64(q->base_pa),
3111                 }
3112         };
3113
3114         dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
3115         dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
3116         dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
3117         dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
3118
3119         err = ionic_adminq_post_wait(lif, &ctx);
3120         if (err)
3121                 return err;
3122
3123         lif->last_eid = 0;
3124         q->hw_type = ctx.comp.q_init.hw_type;
3125         q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
3126         q->dbval = IONIC_DBELL_QID(q->hw_index);
3127
3128         dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
3129         dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
3130
3131         /* preset the callback info */
3132         q->info[0].cb_arg = lif;
3133
3134         qcq->flags |= IONIC_QCQ_F_INITED;
3135
3136         return 0;
3137 }
3138
3139 static int ionic_station_set(struct ionic_lif *lif)
3140 {
3141         struct net_device *netdev = lif->netdev;
3142         struct ionic_admin_ctx ctx = {
3143                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3144                 .cmd.lif_getattr = {
3145                         .opcode = IONIC_CMD_LIF_GETATTR,
3146                         .index = cpu_to_le16(lif->index),
3147                         .attr = IONIC_LIF_ATTR_MAC,
3148                 },
3149         };
3150         struct sockaddr addr;
3151         int err;
3152
3153         err = ionic_adminq_post_wait(lif, &ctx);
3154         if (err)
3155                 return err;
3156         netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
3157                    ctx.comp.lif_getattr.mac);
3158         if (is_zero_ether_addr(ctx.comp.lif_getattr.mac))
3159                 return 0;
3160
3161         if (!is_zero_ether_addr(netdev->dev_addr)) {
3162                 /* If the netdev mac is non-zero and doesn't match the default
3163                  * device address, it was set by something earlier and we're
3164                  * likely here again after a fw-upgrade reset.  We need to be
3165                  * sure the netdev mac is in our filter list.
3166                  */
3167                 if (!ether_addr_equal(ctx.comp.lif_getattr.mac,
3168                                       netdev->dev_addr))
3169                         ionic_lif_addr_add(lif, netdev->dev_addr);
3170         } else {
3171                 /* Update the netdev mac with the device's mac */
3172                 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);
3173                 addr.sa_family = AF_INET;
3174                 err = eth_prepare_mac_addr_change(netdev, &addr);
3175                 if (err) {
3176                         netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
3177                                     addr.sa_data, err);
3178                         return 0;
3179                 }
3180
3181                 eth_commit_mac_addr_change(netdev, &addr);
3182         }
3183
3184         netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
3185                    netdev->dev_addr);
3186         ionic_lif_addr_add(lif, netdev->dev_addr);
3187
3188         return 0;
3189 }
3190
3191 int ionic_lif_init(struct ionic_lif *lif)
3192 {
3193         struct ionic_dev *idev = &lif->ionic->idev;
3194         struct device *dev = lif->ionic->dev;
3195         struct ionic_lif_init_comp comp;
3196         int dbpage_num;
3197         int err;
3198
3199         mutex_lock(&lif->ionic->dev_cmd_lock);
3200         ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
3201         err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
3202         ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
3203         mutex_unlock(&lif->ionic->dev_cmd_lock);
3204         if (err)
3205                 return err;
3206
3207         lif->hw_index = le16_to_cpu(comp.hw_index);
3208
3209         /* now that we have the hw_index we can figure out our doorbell page */
3210         lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
3211         if (!lif->dbid_count) {
3212                 dev_err(dev, "No doorbell pages, aborting\n");
3213                 return -EINVAL;
3214         }
3215
3216         lif->kern_pid = 0;
3217         dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
3218         lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
3219         if (!lif->kern_dbpage) {
3220                 dev_err(dev, "Cannot map dbpage, aborting\n");
3221                 return -ENOMEM;
3222         }
3223
3224         err = ionic_lif_adminq_init(lif);
3225         if (err)
3226                 goto err_out_adminq_deinit;
3227
3228         if (lif->ionic->nnqs_per_lif) {
3229                 err = ionic_lif_notifyq_init(lif);
3230                 if (err)
3231                         goto err_out_notifyq_deinit;
3232         }
3233
3234         err = ionic_init_nic_features(lif);
3235         if (err)
3236                 goto err_out_notifyq_deinit;
3237
3238         if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
3239                 err = ionic_rx_filters_init(lif);
3240                 if (err)
3241                         goto err_out_notifyq_deinit;
3242         }
3243
3244         err = ionic_station_set(lif);
3245         if (err)
3246                 goto err_out_notifyq_deinit;
3247
3248         lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
3249
3250         set_bit(IONIC_LIF_F_INITED, lif->state);
3251
3252         INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
3253
3254         return 0;
3255
3256 err_out_notifyq_deinit:
3257         napi_disable(&lif->adminqcq->napi);
3258         ionic_lif_qcq_deinit(lif, lif->notifyqcq);
3259 err_out_adminq_deinit:
3260         ionic_lif_qcq_deinit(lif, lif->adminqcq);
3261         ionic_lif_reset(lif);
3262         ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
3263         lif->kern_dbpage = NULL;
3264
3265         return err;
3266 }
3267
3268 static void ionic_lif_notify_work(struct work_struct *ws)
3269 {
3270 }
3271
3272 static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
3273 {
3274         struct ionic_admin_ctx ctx = {
3275                 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
3276                 .cmd.lif_setattr = {
3277                         .opcode = IONIC_CMD_LIF_SETATTR,
3278                         .index = cpu_to_le16(lif->index),
3279                         .attr = IONIC_LIF_ATTR_NAME,
3280                 },
3281         };
3282
3283         strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
3284                 sizeof(ctx.cmd.lif_setattr.name));
3285
3286         ionic_adminq_post_wait(lif, &ctx);
3287 }
3288
3289 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
3290 {
3291         if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
3292                 return NULL;
3293
3294         return netdev_priv(netdev);
3295 }
3296
3297 static int ionic_lif_notify(struct notifier_block *nb,
3298                             unsigned long event, void *info)
3299 {
3300         struct net_device *ndev = netdev_notifier_info_to_dev(info);
3301         struct ionic *ionic = container_of(nb, struct ionic, nb);
3302         struct ionic_lif *lif = ionic_netdev_lif(ndev);
3303
3304         if (!lif || lif->ionic != ionic)
3305                 return NOTIFY_DONE;
3306
3307         switch (event) {
3308         case NETDEV_CHANGENAME:
3309                 ionic_lif_set_netdev_info(lif);
3310                 break;
3311         }
3312
3313         return NOTIFY_DONE;
3314 }
3315
3316 int ionic_lif_register(struct ionic_lif *lif)
3317 {
3318         int err;
3319
3320         ionic_lif_register_phc(lif);
3321
3322         INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work);
3323
3324         lif->ionic->nb.notifier_call = ionic_lif_notify;
3325
3326         err = register_netdevice_notifier(&lif->ionic->nb);
3327         if (err)
3328                 lif->ionic->nb.notifier_call = NULL;
3329
3330         /* only register LIF0 for now */
3331         err = register_netdev(lif->netdev);
3332         if (err) {
3333                 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n");
3334                 ionic_lif_unregister_phc(lif);
3335                 return err;
3336         }
3337
3338         ionic_link_status_check_request(lif, CAN_SLEEP);
3339         lif->registered = true;
3340         ionic_lif_set_netdev_info(lif);
3341
3342         return 0;
3343 }
3344
3345 void ionic_lif_unregister(struct ionic_lif *lif)
3346 {
3347         if (lif->ionic->nb.notifier_call) {
3348                 unregister_netdevice_notifier(&lif->ionic->nb);
3349                 cancel_work_sync(&lif->ionic->nb_work);
3350                 lif->ionic->nb.notifier_call = NULL;
3351         }
3352
3353         if (lif->netdev->reg_state == NETREG_REGISTERED)
3354                 unregister_netdev(lif->netdev);
3355
3356         ionic_lif_unregister_phc(lif);
3357
3358         lif->registered = false;
3359 }
3360
3361 static void ionic_lif_queue_identify(struct ionic_lif *lif)
3362 {
3363         union ionic_q_identity __iomem *q_ident;
3364         struct ionic *ionic = lif->ionic;
3365         struct ionic_dev *idev;
3366         int qtype;
3367         int err;
3368
3369         idev = &lif->ionic->idev;
3370         q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data;
3371
3372         for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
3373                 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3374
3375                 /* filter out the ones we know about */
3376                 switch (qtype) {
3377                 case IONIC_QTYPE_ADMINQ:
3378                 case IONIC_QTYPE_NOTIFYQ:
3379                 case IONIC_QTYPE_RXQ:
3380                 case IONIC_QTYPE_TXQ:
3381                         break;
3382                 default:
3383                         continue;
3384                 }
3385
3386                 memset(qti, 0, sizeof(*qti));
3387
3388                 mutex_lock(&ionic->dev_cmd_lock);
3389                 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
3390                                              ionic_qtype_versions[qtype]);
3391                 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3392                 if (!err) {
3393                         qti->version   = readb(&q_ident->version);
3394                         qti->supported = readb(&q_ident->supported);
3395                         qti->features  = readq(&q_ident->features);
3396                         qti->desc_sz   = readw(&q_ident->desc_sz);
3397                         qti->comp_sz   = readw(&q_ident->comp_sz);
3398                         qti->sg_desc_sz   = readw(&q_ident->sg_desc_sz);
3399                         qti->max_sg_elems = readw(&q_ident->max_sg_elems);
3400                         qti->sg_desc_stride = readw(&q_ident->sg_desc_stride);
3401                 }
3402                 mutex_unlock(&ionic->dev_cmd_lock);
3403
3404                 if (err == -EINVAL) {
3405                         dev_err(ionic->dev, "qtype %d not supported\n", qtype);
3406                         continue;
3407                 } else if (err == -EIO) {
3408                         dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
3409                         return;
3410                 } else if (err) {
3411                         dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
3412                                 qtype, err);
3413                         return;
3414                 }
3415
3416                 dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
3417                         qtype, qti->version);
3418                 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
3419                         qtype, qti->supported);
3420                 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
3421                         qtype, qti->features);
3422                 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
3423                         qtype, qti->desc_sz);
3424                 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
3425                         qtype, qti->comp_sz);
3426                 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
3427                         qtype, qti->sg_desc_sz);
3428                 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
3429                         qtype, qti->max_sg_elems);
3430                 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
3431                         qtype, qti->sg_desc_stride);
3432         }
3433 }
3434
3435 int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
3436                        union ionic_lif_identity *lid)
3437 {
3438         struct ionic_dev *idev = &ionic->idev;
3439         size_t sz;
3440         int err;
3441
3442         sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
3443
3444         mutex_lock(&ionic->dev_cmd_lock);
3445         ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
3446         err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3447         memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
3448         mutex_unlock(&ionic->dev_cmd_lock);
3449         if (err)
3450                 return (err);
3451
3452         dev_dbg(ionic->dev, "capabilities 0x%llx\n",
3453                 le64_to_cpu(lid->capabilities));
3454
3455         dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
3456                 le32_to_cpu(lid->eth.max_ucast_filters));
3457         dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
3458                 le32_to_cpu(lid->eth.max_mcast_filters));
3459         dev_dbg(ionic->dev, "eth.features 0x%llx\n",
3460                 le64_to_cpu(lid->eth.config.features));
3461         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
3462                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
3463         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
3464                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
3465         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
3466                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
3467         dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
3468                 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
3469         dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
3470         dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
3471         dev_dbg(ionic->dev, "eth.config.mtu %d\n",
3472                 le32_to_cpu(lid->eth.config.mtu));
3473
3474         return 0;
3475 }
3476
3477 int ionic_lif_size(struct ionic *ionic)
3478 {
3479         struct ionic_identity *ident = &ionic->ident;
3480         unsigned int nintrs, dev_nintrs;
3481         union ionic_lif_config *lc;
3482         unsigned int ntxqs_per_lif;
3483         unsigned int nrxqs_per_lif;
3484         unsigned int neqs_per_lif;
3485         unsigned int nnqs_per_lif;
3486         unsigned int nxqs, neqs;
3487         unsigned int min_intrs;
3488         int err;
3489
3490         /* retrieve basic values from FW */
3491         lc = &ident->lif.eth.config;
3492         dev_nintrs = le32_to_cpu(ident->dev.nintrs);
3493         neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
3494         nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
3495         ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
3496         nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
3497
3498         /* limit values to play nice with kdump */
3499         if (is_kdump_kernel()) {
3500                 dev_nintrs = 2;
3501                 neqs_per_lif = 0;
3502                 nnqs_per_lif = 0;
3503                 ntxqs_per_lif = 1;
3504                 nrxqs_per_lif = 1;
3505         }
3506
3507         /* reserve last queue id for hardware timestamping */
3508         if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) {
3509                 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) {
3510                         lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP);
3511                 } else {
3512                         ntxqs_per_lif -= 1;
3513                         nrxqs_per_lif -= 1;
3514                 }
3515         }
3516
3517         nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
3518         nxqs = min(nxqs, num_online_cpus());
3519         neqs = min(neqs_per_lif, num_online_cpus());
3520
3521 try_again:
3522         /* interrupt usage:
3523          *    1 for master lif adminq/notifyq
3524          *    1 for each CPU for master lif TxRx queue pairs
3525          *    whatever's left is for RDMA queues
3526          */
3527         nintrs = 1 + nxqs + neqs;
3528         min_intrs = 2;  /* adminq + 1 TxRx queue pair */
3529
3530         if (nintrs > dev_nintrs)
3531                 goto try_fewer;
3532
3533         err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
3534         if (err < 0 && err != -ENOSPC) {
3535                 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
3536                 return err;
3537         }
3538         if (err == -ENOSPC)
3539                 goto try_fewer;
3540
3541         if (err != nintrs) {
3542                 ionic_bus_free_irq_vectors(ionic);
3543                 goto try_fewer;
3544         }
3545
3546         ionic->nnqs_per_lif = nnqs_per_lif;
3547         ionic->neqs_per_lif = neqs;
3548         ionic->ntxqs_per_lif = nxqs;
3549         ionic->nrxqs_per_lif = nxqs;
3550         ionic->nintrs = nintrs;
3551
3552         ionic_debugfs_add_sizes(ionic);
3553
3554         return 0;
3555
3556 try_fewer:
3557         if (nnqs_per_lif > 1) {
3558                 nnqs_per_lif >>= 1;
3559                 goto try_again;
3560         }
3561         if (neqs > 1) {
3562                 neqs >>= 1;
3563                 goto try_again;
3564         }
3565         if (nxqs > 1) {
3566                 nxqs >>= 1;
3567                 goto try_again;
3568         }
3569         dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
3570         return -ENOSPC;
3571 }