2 * drivers/net/ethernet/nxp/lpc_eth.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
7 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/crc32.h>
32 #include <linux/platform_device.h>
33 #include <linux/spinlock.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/clk.h>
37 #include <linux/workqueue.h>
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/phy.h>
42 #include <linux/dma-mapping.h>
44 #include <linux/of_net.h>
45 #include <linux/types.h>
48 #include <mach/board.h>
49 #include <mach/platform.h>
50 #include <mach/hardware.h>
52 #define MODNAME "lpc-eth"
53 #define DRV_VERSION "1.00"
55 #define ENET_MAXF_SIZE 1536
56 #define ENET_RX_DESC 48
57 #define ENET_TX_DESC 16
59 #define NAPI_WEIGHT 16
62 * Ethernet MAC controller Register offsets
64 #define LPC_ENET_MAC1(x) (x + 0x000)
65 #define LPC_ENET_MAC2(x) (x + 0x004)
66 #define LPC_ENET_IPGT(x) (x + 0x008)
67 #define LPC_ENET_IPGR(x) (x + 0x00C)
68 #define LPC_ENET_CLRT(x) (x + 0x010)
69 #define LPC_ENET_MAXF(x) (x + 0x014)
70 #define LPC_ENET_SUPP(x) (x + 0x018)
71 #define LPC_ENET_TEST(x) (x + 0x01C)
72 #define LPC_ENET_MCFG(x) (x + 0x020)
73 #define LPC_ENET_MCMD(x) (x + 0x024)
74 #define LPC_ENET_MADR(x) (x + 0x028)
75 #define LPC_ENET_MWTD(x) (x + 0x02C)
76 #define LPC_ENET_MRDD(x) (x + 0x030)
77 #define LPC_ENET_MIND(x) (x + 0x034)
78 #define LPC_ENET_SA0(x) (x + 0x040)
79 #define LPC_ENET_SA1(x) (x + 0x044)
80 #define LPC_ENET_SA2(x) (x + 0x048)
81 #define LPC_ENET_COMMAND(x) (x + 0x100)
82 #define LPC_ENET_STATUS(x) (x + 0x104)
83 #define LPC_ENET_RXDESCRIPTOR(x) (x + 0x108)
84 #define LPC_ENET_RXSTATUS(x) (x + 0x10C)
85 #define LPC_ENET_RXDESCRIPTORNUMBER(x) (x + 0x110)
86 #define LPC_ENET_RXPRODUCEINDEX(x) (x + 0x114)
87 #define LPC_ENET_RXCONSUMEINDEX(x) (x + 0x118)
88 #define LPC_ENET_TXDESCRIPTOR(x) (x + 0x11C)
89 #define LPC_ENET_TXSTATUS(x) (x + 0x120)
90 #define LPC_ENET_TXDESCRIPTORNUMBER(x) (x + 0x124)
91 #define LPC_ENET_TXPRODUCEINDEX(x) (x + 0x128)
92 #define LPC_ENET_TXCONSUMEINDEX(x) (x + 0x12C)
93 #define LPC_ENET_TSV0(x) (x + 0x158)
94 #define LPC_ENET_TSV1(x) (x + 0x15C)
95 #define LPC_ENET_RSV(x) (x + 0x160)
96 #define LPC_ENET_FLOWCONTROLCOUNTER(x) (x + 0x170)
97 #define LPC_ENET_FLOWCONTROLSTATUS(x) (x + 0x174)
98 #define LPC_ENET_RXFILTER_CTRL(x) (x + 0x200)
99 #define LPC_ENET_RXFILTERWOLSTATUS(x) (x + 0x204)
100 #define LPC_ENET_RXFILTERWOLCLEAR(x) (x + 0x208)
101 #define LPC_ENET_HASHFILTERL(x) (x + 0x210)
102 #define LPC_ENET_HASHFILTERH(x) (x + 0x214)
103 #define LPC_ENET_INTSTATUS(x) (x + 0xFE0)
104 #define LPC_ENET_INTENABLE(x) (x + 0xFE4)
105 #define LPC_ENET_INTCLEAR(x) (x + 0xFE8)
106 #define LPC_ENET_INTSET(x) (x + 0xFEC)
107 #define LPC_ENET_POWERDOWN(x) (x + 0xFF4)
110 * mac1 register definitions
112 #define LPC_MAC1_RECV_ENABLE (1 << 0)
113 #define LPC_MAC1_PASS_ALL_RX_FRAMES (1 << 1)
114 #define LPC_MAC1_RX_FLOW_CONTROL (1 << 2)
115 #define LPC_MAC1_TX_FLOW_CONTROL (1 << 3)
116 #define LPC_MAC1_LOOPBACK (1 << 4)
117 #define LPC_MAC1_RESET_TX (1 << 8)
118 #define LPC_MAC1_RESET_MCS_TX (1 << 9)
119 #define LPC_MAC1_RESET_RX (1 << 10)
120 #define LPC_MAC1_RESET_MCS_RX (1 << 11)
121 #define LPC_MAC1_SIMULATION_RESET (1 << 14)
122 #define LPC_MAC1_SOFT_RESET (1 << 15)
125 * mac2 register definitions
127 #define LPC_MAC2_FULL_DUPLEX (1 << 0)
128 #define LPC_MAC2_FRAME_LENGTH_CHECKING (1 << 1)
129 #define LPC_MAC2_HUGH_LENGTH_CHECKING (1 << 2)
130 #define LPC_MAC2_DELAYED_CRC (1 << 3)
131 #define LPC_MAC2_CRC_ENABLE (1 << 4)
132 #define LPC_MAC2_PAD_CRC_ENABLE (1 << 5)
133 #define LPC_MAC2_VLAN_PAD_ENABLE (1 << 6)
134 #define LPC_MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7)
135 #define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT (1 << 8)
136 #define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT (1 << 9)
137 #define LPC_MAC2_NO_BACKOFF (1 << 12)
138 #define LPC_MAC2_BACK_PRESSURE (1 << 13)
139 #define LPC_MAC2_EXCESS_DEFER (1 << 14)
142 * ipgt register definitions
144 #define LPC_IPGT_LOAD(n) ((n) & 0x7F)
147 * ipgr register definitions
149 #define LPC_IPGR_LOAD_PART2(n) ((n) & 0x7F)
150 #define LPC_IPGR_LOAD_PART1(n) (((n) & 0x7F) << 8)
153 * clrt register definitions
155 #define LPC_CLRT_LOAD_RETRY_MAX(n) ((n) & 0xF)
156 #define LPC_CLRT_LOAD_COLLISION_WINDOW(n) (((n) & 0x3F) << 8)
159 * maxf register definitions
161 #define LPC_MAXF_LOAD_MAX_FRAME_LEN(n) ((n) & 0xFFFF)
164 * supp register definitions
166 #define LPC_SUPP_SPEED (1 << 8)
167 #define LPC_SUPP_RESET_RMII (1 << 11)
170 * test register definitions
172 #define LPC_TEST_SHORTCUT_PAUSE_QUANTA (1 << 0)
173 #define LPC_TEST_PAUSE (1 << 1)
174 #define LPC_TEST_BACKPRESSURE (1 << 2)
177 * mcfg register definitions
179 #define LPC_MCFG_SCAN_INCREMENT (1 << 0)
180 #define LPC_MCFG_SUPPRESS_PREAMBLE (1 << 1)
181 #define LPC_MCFG_CLOCK_SELECT(n) (((n) & 0x7) << 2)
182 #define LPC_MCFG_CLOCK_HOST_DIV_4 0
183 #define LPC_MCFG_CLOCK_HOST_DIV_6 2
184 #define LPC_MCFG_CLOCK_HOST_DIV_8 3
185 #define LPC_MCFG_CLOCK_HOST_DIV_10 4
186 #define LPC_MCFG_CLOCK_HOST_DIV_14 5
187 #define LPC_MCFG_CLOCK_HOST_DIV_20 6
188 #define LPC_MCFG_CLOCK_HOST_DIV_28 7
189 #define LPC_MCFG_RESET_MII_MGMT (1 << 15)
192 * mcmd register definitions
194 #define LPC_MCMD_READ (1 << 0)
195 #define LPC_MCMD_SCAN (1 << 1)
198 * madr register definitions
200 #define LPC_MADR_REGISTER_ADDRESS(n) ((n) & 0x1F)
201 #define LPC_MADR_PHY_0ADDRESS(n) (((n) & 0x1F) << 8)
204 * mwtd register definitions
206 #define LPC_MWDT_WRITE(n) ((n) & 0xFFFF)
209 * mrdd register definitions
211 #define LPC_MRDD_READ_MASK 0xFFFF
214 * mind register definitions
216 #define LPC_MIND_BUSY (1 << 0)
217 #define LPC_MIND_SCANNING (1 << 1)
218 #define LPC_MIND_NOT_VALID (1 << 2)
219 #define LPC_MIND_MII_LINK_FAIL (1 << 3)
222 * command register definitions
224 #define LPC_COMMAND_RXENABLE (1 << 0)
225 #define LPC_COMMAND_TXENABLE (1 << 1)
226 #define LPC_COMMAND_REG_RESET (1 << 3)
227 #define LPC_COMMAND_TXRESET (1 << 4)
228 #define LPC_COMMAND_RXRESET (1 << 5)
229 #define LPC_COMMAND_PASSRUNTFRAME (1 << 6)
230 #define LPC_COMMAND_PASSRXFILTER (1 << 7)
231 #define LPC_COMMAND_TXFLOWCONTROL (1 << 8)
232 #define LPC_COMMAND_RMII (1 << 9)
233 #define LPC_COMMAND_FULLDUPLEX (1 << 10)
236 * status register definitions
238 #define LPC_STATUS_RXACTIVE (1 << 0)
239 #define LPC_STATUS_TXACTIVE (1 << 1)
242 * tsv0 register definitions
244 #define LPC_TSV0_CRC_ERROR (1 << 0)
245 #define LPC_TSV0_LENGTH_CHECK_ERROR (1 << 1)
246 #define LPC_TSV0_LENGTH_OUT_OF_RANGE (1 << 2)
247 #define LPC_TSV0_DONE (1 << 3)
248 #define LPC_TSV0_MULTICAST (1 << 4)
249 #define LPC_TSV0_BROADCAST (1 << 5)
250 #define LPC_TSV0_PACKET_DEFER (1 << 6)
251 #define LPC_TSV0_ESCESSIVE_DEFER (1 << 7)
252 #define LPC_TSV0_ESCESSIVE_COLLISION (1 << 8)
253 #define LPC_TSV0_LATE_COLLISION (1 << 9)
254 #define LPC_TSV0_GIANT (1 << 10)
255 #define LPC_TSV0_UNDERRUN (1 << 11)
256 #define LPC_TSV0_TOTAL_BYTES(n) (((n) >> 12) & 0xFFFF)
257 #define LPC_TSV0_CONTROL_FRAME (1 << 28)
258 #define LPC_TSV0_PAUSE (1 << 29)
259 #define LPC_TSV0_BACKPRESSURE (1 << 30)
260 #define LPC_TSV0_VLAN (1 << 31)
263 * tsv1 register definitions
265 #define LPC_TSV1_TRANSMIT_BYTE_COUNT(n) ((n) & 0xFFFF)
266 #define LPC_TSV1_COLLISION_COUNT(n) (((n) >> 16) & 0xF)
269 * rsv register definitions
271 #define LPC_RSV_RECEIVED_BYTE_COUNT(n) ((n) & 0xFFFF)
272 #define LPC_RSV_RXDV_EVENT_IGNORED (1 << 16)
273 #define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN (1 << 17)
274 #define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN (1 << 18)
275 #define LPC_RSV_RECEIVE_CODE_VIOLATION (1 << 19)
276 #define LPC_RSV_CRC_ERROR (1 << 20)
277 #define LPC_RSV_LENGTH_CHECK_ERROR (1 << 21)
278 #define LPC_RSV_LENGTH_OUT_OF_RANGE (1 << 22)
279 #define LPC_RSV_RECEIVE_OK (1 << 23)
280 #define LPC_RSV_MULTICAST (1 << 24)
281 #define LPC_RSV_BROADCAST (1 << 25)
282 #define LPC_RSV_DRIBBLE_NIBBLE (1 << 26)
283 #define LPC_RSV_CONTROL_FRAME (1 << 27)
284 #define LPC_RSV_PAUSE (1 << 28)
285 #define LPC_RSV_UNSUPPORTED_OPCODE (1 << 29)
286 #define LPC_RSV_VLAN (1 << 30)
289 * flowcontrolcounter register definitions
291 #define LPC_FCCR_MIRRORCOUNTER(n) ((n) & 0xFFFF)
292 #define LPC_FCCR_PAUSETIMER(n) (((n) >> 16) & 0xFFFF)
295 * flowcontrolstatus register definitions
297 #define LPC_FCCR_MIRRORCOUNTERCURRENT(n) ((n) & 0xFFFF)
300 * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
301 * register definitions
303 #define LPC_RXFLTRW_ACCEPTUNICAST (1 << 0)
304 #define LPC_RXFLTRW_ACCEPTUBROADCAST (1 << 1)
305 #define LPC_RXFLTRW_ACCEPTUMULTICAST (1 << 2)
306 #define LPC_RXFLTRW_ACCEPTUNICASTHASH (1 << 3)
307 #define LPC_RXFLTRW_ACCEPTUMULTICASTHASH (1 << 4)
308 #define LPC_RXFLTRW_ACCEPTPERFECT (1 << 5)
311 * rxfliterctrl register definitions
313 #define LPC_RXFLTRWSTS_MAGICPACKETENWOL (1 << 12)
314 #define LPC_RXFLTRWSTS_RXFILTERENWOL (1 << 13)
317 * rxfilterwolstatus/rxfilterwolclear register definitions
319 #define LPC_RXFLTRWSTS_RXFILTERWOL (1 << 7)
320 #define LPC_RXFLTRWSTS_MAGICPACKETWOL (1 << 8)
323 * intstatus, intenable, intclear, and Intset shared register
326 #define LPC_MACINT_RXOVERRUNINTEN (1 << 0)
327 #define LPC_MACINT_RXERRORONINT (1 << 1)
328 #define LPC_MACINT_RXFINISHEDINTEN (1 << 2)
329 #define LPC_MACINT_RXDONEINTEN (1 << 3)
330 #define LPC_MACINT_TXUNDERRUNINTEN (1 << 4)
331 #define LPC_MACINT_TXERRORINTEN (1 << 5)
332 #define LPC_MACINT_TXFINISHEDINTEN (1 << 6)
333 #define LPC_MACINT_TXDONEINTEN (1 << 7)
334 #define LPC_MACINT_SOFTINTEN (1 << 12)
335 #define LPC_MACINT_WAKEUPINTEN (1 << 13)
338 * powerdown register definitions
340 #define LPC_POWERDOWN_MACAHB (1 << 31)
342 static phy_interface_t lpc_phy_interface_mode(struct device *dev)
344 if (dev && dev->of_node) {
345 const char *mode = of_get_property(dev->of_node,
347 if (mode && !strcmp(mode, "mii"))
348 return PHY_INTERFACE_MODE_MII;
349 return PHY_INTERFACE_MODE_RMII;
353 #ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
354 return PHY_INTERFACE_MODE_MII;
356 return PHY_INTERFACE_MODE_RMII;
360 static bool use_iram_for_net(struct device *dev)
362 if (dev && dev->of_node)
363 return of_property_read_bool(dev->of_node, "use-iram");
366 #ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
373 /* Receive Status information word */
374 #define RXSTATUS_SIZE 0x000007FF
375 #define RXSTATUS_CONTROL (1 << 18)
376 #define RXSTATUS_VLAN (1 << 19)
377 #define RXSTATUS_FILTER (1 << 20)
378 #define RXSTATUS_MULTICAST (1 << 21)
379 #define RXSTATUS_BROADCAST (1 << 22)
380 #define RXSTATUS_CRC (1 << 23)
381 #define RXSTATUS_SYMBOL (1 << 24)
382 #define RXSTATUS_LENGTH (1 << 25)
383 #define RXSTATUS_RANGE (1 << 26)
384 #define RXSTATUS_ALIGN (1 << 27)
385 #define RXSTATUS_OVERRUN (1 << 28)
386 #define RXSTATUS_NODESC (1 << 29)
387 #define RXSTATUS_LAST (1 << 30)
388 #define RXSTATUS_ERROR (1 << 31)
390 #define RXSTATUS_STATUS_ERROR \
391 (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \
392 RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
394 /* Receive Descriptor control word */
395 #define RXDESC_CONTROL_SIZE 0x000007FF
396 #define RXDESC_CONTROL_INT (1 << 31)
398 /* Transmit Status information word */
399 #define TXSTATUS_COLLISIONS_GET(x) (((x) >> 21) & 0xF)
400 #define TXSTATUS_DEFER (1 << 25)
401 #define TXSTATUS_EXCESSDEFER (1 << 26)
402 #define TXSTATUS_EXCESSCOLL (1 << 27)
403 #define TXSTATUS_LATECOLL (1 << 28)
404 #define TXSTATUS_UNDERRUN (1 << 29)
405 #define TXSTATUS_NODESC (1 << 30)
406 #define TXSTATUS_ERROR (1 << 31)
408 /* Transmit Descriptor control word */
409 #define TXDESC_CONTROL_SIZE 0x000007FF
410 #define TXDESC_CONTROL_OVERRIDE (1 << 26)
411 #define TXDESC_CONTROL_HUGE (1 << 27)
412 #define TXDESC_CONTROL_PAD (1 << 28)
413 #define TXDESC_CONTROL_CRC (1 << 29)
414 #define TXDESC_CONTROL_LAST (1 << 30)
415 #define TXDESC_CONTROL_INT (1 << 31)
418 * Structure of a TX/RX descriptors and RX status
426 __le32 statushashcrc;
430 * Device driver data structure
432 struct netdata_local {
433 struct platform_device *pdev;
434 struct net_device *ndev;
436 void __iomem *net_base;
438 unsigned int skblen[ENET_TX_DESC];
439 unsigned int last_tx_idx;
440 unsigned int num_used_tx_buffs;
441 struct mii_bus *mii_bus;
442 struct phy_device *phy_dev;
444 dma_addr_t dma_buff_base_p;
445 void *dma_buff_base_v;
446 size_t dma_buff_size;
447 struct txrx_desc_t *tx_desc_v;
450 struct txrx_desc_t *rx_desc_v;
451 struct rx_status_t *rx_stat_v;
456 struct napi_struct napi;
460 * MAC support functions
462 static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
466 /* Set station address */
467 tmp = mac[0] | ((u32)mac[1] << 8);
468 writel(tmp, LPC_ENET_SA2(pldat->net_base));
469 tmp = mac[2] | ((u32)mac[3] << 8);
470 writel(tmp, LPC_ENET_SA1(pldat->net_base));
471 tmp = mac[4] | ((u32)mac[5] << 8);
472 writel(tmp, LPC_ENET_SA0(pldat->net_base));
474 netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
477 static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
481 /* Get station address */
482 tmp = readl(LPC_ENET_SA2(pldat->net_base));
485 tmp = readl(LPC_ENET_SA1(pldat->net_base));
488 tmp = readl(LPC_ENET_SA0(pldat->net_base));
493 static void __lpc_eth_clock_enable(struct netdata_local *pldat,
497 clk_enable(pldat->clk);
499 clk_disable(pldat->clk);
502 static void __lpc_params_setup(struct netdata_local *pldat)
506 if (pldat->duplex == DUPLEX_FULL) {
507 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
508 tmp |= LPC_MAC2_FULL_DUPLEX;
509 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
510 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
511 tmp |= LPC_COMMAND_FULLDUPLEX;
512 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
513 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
515 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
516 tmp &= ~LPC_MAC2_FULL_DUPLEX;
517 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
518 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
519 tmp &= ~LPC_COMMAND_FULLDUPLEX;
520 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
521 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
524 if (pldat->speed == SPEED_100)
525 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
527 writel(0, LPC_ENET_SUPP(pldat->net_base));
530 static void __lpc_eth_reset(struct netdata_local *pldat)
532 /* Reset all MAC logic */
533 writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
534 LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
535 LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
536 writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
537 LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
540 static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
542 /* Reset MII management hardware */
543 writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
545 /* Setup MII clock to slowest rate with a /28 divider */
546 writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
547 LPC_ENET_MCFG(pldat->net_base));
552 static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
556 phaddr = addr - pldat->dma_buff_base_v;
557 phaddr += pldat->dma_buff_base_p;
562 static void lpc_eth_enable_int(void __iomem *regbase)
564 writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
565 LPC_ENET_INTENABLE(regbase));
568 static void lpc_eth_disable_int(void __iomem *regbase)
570 writel(0, LPC_ENET_INTENABLE(regbase));
573 /* Setup TX/RX descriptors */
574 static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
579 struct txrx_desc_t *ptxrxdesc;
580 struct rx_status_t *prxstat;
582 tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
584 /* Setup TX descriptors, status, and buffers */
585 pldat->tx_desc_v = tbuff;
586 tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
588 pldat->tx_stat_v = tbuff;
589 tbuff += sizeof(u32) * ENET_TX_DESC;
591 tbuff = PTR_ALIGN(tbuff, 16);
592 pldat->tx_buff_v = tbuff;
593 tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
595 /* Setup RX descriptors, status, and buffers */
596 pldat->rx_desc_v = tbuff;
597 tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
599 tbuff = PTR_ALIGN(tbuff, 16);
600 pldat->rx_stat_v = tbuff;
601 tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
603 tbuff = PTR_ALIGN(tbuff, 16);
604 pldat->rx_buff_v = tbuff;
605 tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
607 /* Map the TX descriptors to the TX buffers in hardware */
608 for (i = 0; i < ENET_TX_DESC; i++) {
609 ptxstat = &pldat->tx_stat_v[i];
610 ptxrxdesc = &pldat->tx_desc_v[i];
612 ptxrxdesc->packet = __va_to_pa(
613 pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
614 ptxrxdesc->control = 0;
618 /* Map the RX descriptors to the RX buffers in hardware */
619 for (i = 0; i < ENET_RX_DESC; i++) {
620 prxstat = &pldat->rx_stat_v[i];
621 ptxrxdesc = &pldat->rx_desc_v[i];
623 ptxrxdesc->packet = __va_to_pa(
624 pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
625 ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
626 prxstat->statusinfo = 0;
627 prxstat->statushashcrc = 0;
630 /* Setup base addresses in hardware to point to buffers and
633 writel((ENET_TX_DESC - 1),
634 LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
635 writel(__va_to_pa(pldat->tx_desc_v, pldat),
636 LPC_ENET_TXDESCRIPTOR(pldat->net_base));
637 writel(__va_to_pa(pldat->tx_stat_v, pldat),
638 LPC_ENET_TXSTATUS(pldat->net_base));
639 writel((ENET_RX_DESC - 1),
640 LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
641 writel(__va_to_pa(pldat->rx_desc_v, pldat),
642 LPC_ENET_RXDESCRIPTOR(pldat->net_base));
643 writel(__va_to_pa(pldat->rx_stat_v, pldat),
644 LPC_ENET_RXSTATUS(pldat->net_base));
647 static void __lpc_eth_init(struct netdata_local *pldat)
651 /* Disable controller and reset */
652 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
653 tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
654 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
655 tmp = readl(LPC_ENET_MAC1(pldat->net_base));
656 tmp &= ~LPC_MAC1_RECV_ENABLE;
657 writel(tmp, LPC_ENET_MAC1(pldat->net_base));
659 /* Initial MAC setup */
660 writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
661 writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
662 LPC_ENET_MAC2(pldat->net_base));
663 writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
665 /* Collision window, gap */
666 writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
667 LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
668 LPC_ENET_CLRT(pldat->net_base));
669 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
671 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
672 writel(LPC_COMMAND_PASSRUNTFRAME,
673 LPC_ENET_COMMAND(pldat->net_base));
675 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
676 LPC_ENET_COMMAND(pldat->net_base));
677 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
680 __lpc_params_setup(pldat);
682 /* Setup TX and RX descriptors */
683 __lpc_txrx_desc_setup(pldat);
685 /* Setup packet filtering */
686 writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
687 LPC_ENET_RXFILTER_CTRL(pldat->net_base));
689 /* Get the next TX buffer output index */
690 pldat->num_used_tx_buffs = 0;
692 readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
694 /* Clear and enable interrupts */
695 writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
697 lpc_eth_enable_int(pldat->net_base);
699 /* Enable controller */
700 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
701 tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
702 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
703 tmp = readl(LPC_ENET_MAC1(pldat->net_base));
704 tmp |= LPC_MAC1_RECV_ENABLE;
705 writel(tmp, LPC_ENET_MAC1(pldat->net_base));
708 static void __lpc_eth_shutdown(struct netdata_local *pldat)
710 /* Reset ethernet and power down PHY */
711 __lpc_eth_reset(pldat);
712 writel(0, LPC_ENET_MAC1(pldat->net_base));
713 writel(0, LPC_ENET_MAC2(pldat->net_base));
717 * MAC<--->PHY support functions
719 static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
721 struct netdata_local *pldat = bus->priv;
722 unsigned long timeout = jiffies + msecs_to_jiffies(100);
725 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
726 writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
728 /* Wait for unbusy status */
729 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
730 if (time_after(jiffies, timeout))
735 lps = readl(LPC_ENET_MRDD(pldat->net_base));
736 writel(0, LPC_ENET_MCMD(pldat->net_base));
741 static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
744 struct netdata_local *pldat = bus->priv;
745 unsigned long timeout = jiffies + msecs_to_jiffies(100);
747 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
748 writel(phydata, LPC_ENET_MWTD(pldat->net_base));
750 /* Wait for completion */
751 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
752 if (time_after(jiffies, timeout))
760 static int lpc_mdio_reset(struct mii_bus *bus)
762 return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
765 static void lpc_handle_link_change(struct net_device *ndev)
767 struct netdata_local *pldat = netdev_priv(ndev);
768 struct phy_device *phydev = pldat->phy_dev;
771 bool status_change = false;
773 spin_lock_irqsave(&pldat->lock, flags);
776 if ((pldat->speed != phydev->speed) ||
777 (pldat->duplex != phydev->duplex)) {
778 pldat->speed = phydev->speed;
779 pldat->duplex = phydev->duplex;
780 status_change = true;
784 if (phydev->link != pldat->link) {
789 pldat->link = phydev->link;
791 status_change = true;
794 spin_unlock_irqrestore(&pldat->lock, flags);
797 __lpc_params_setup(pldat);
800 static int lpc_mii_probe(struct net_device *ndev)
802 struct netdata_local *pldat = netdev_priv(ndev);
803 struct phy_device *phydev = phy_find_first(pldat->mii_bus);
806 netdev_err(ndev, "no PHY found\n");
810 /* Attach to the PHY */
811 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
812 netdev_info(ndev, "using MII interface\n");
814 netdev_info(ndev, "using RMII interface\n");
815 phydev = phy_connect(ndev, dev_name(&phydev->dev),
816 &lpc_handle_link_change, 0,
817 lpc_phy_interface_mode(&pldat->pdev->dev));
819 if (IS_ERR(phydev)) {
820 netdev_err(ndev, "Could not attach to PHY\n");
821 return PTR_ERR(phydev);
824 /* mask with MAC supported features */
825 phydev->supported &= PHY_BASIC_FEATURES;
827 phydev->advertising = phydev->supported;
832 pldat->phy_dev = phydev;
835 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
836 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
840 static int lpc_mii_init(struct netdata_local *pldat)
844 pldat->mii_bus = mdiobus_alloc();
845 if (!pldat->mii_bus) {
851 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
852 writel(LPC_COMMAND_PASSRUNTFRAME,
853 LPC_ENET_COMMAND(pldat->net_base));
855 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
856 LPC_ENET_COMMAND(pldat->net_base));
857 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
860 pldat->mii_bus->name = "lpc_mii_bus";
861 pldat->mii_bus->read = &lpc_mdio_read;
862 pldat->mii_bus->write = &lpc_mdio_write;
863 pldat->mii_bus->reset = &lpc_mdio_reset;
864 snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
865 pldat->pdev->name, pldat->pdev->id);
866 pldat->mii_bus->priv = pldat;
867 pldat->mii_bus->parent = &pldat->pdev->dev;
869 pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
870 if (!pldat->mii_bus->irq) {
875 for (i = 0; i < PHY_MAX_ADDR; i++)
876 pldat->mii_bus->irq[i] = PHY_POLL;
878 platform_set_drvdata(pldat->pdev, pldat->mii_bus);
880 if (mdiobus_register(pldat->mii_bus))
881 goto err_out_free_mdio_irq;
883 if (lpc_mii_probe(pldat->ndev) != 0)
884 goto err_out_unregister_bus;
888 err_out_unregister_bus:
889 mdiobus_unregister(pldat->mii_bus);
890 err_out_free_mdio_irq:
891 kfree(pldat->mii_bus->irq);
893 mdiobus_free(pldat->mii_bus);
898 static void __lpc_handle_xmit(struct net_device *ndev)
900 struct netdata_local *pldat = netdev_priv(ndev);
901 u32 txcidx, *ptxstat, txstat;
903 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
904 while (pldat->last_tx_idx != txcidx) {
905 unsigned int skblen = pldat->skblen[pldat->last_tx_idx];
907 /* A buffer is available, get buffer status */
908 ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
911 /* Next buffer and decrement used buffer counter */
912 pldat->num_used_tx_buffs--;
913 pldat->last_tx_idx++;
914 if (pldat->last_tx_idx >= ENET_TX_DESC)
915 pldat->last_tx_idx = 0;
917 /* Update collision counter */
918 ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
920 /* Any errors occurred? */
921 if (txstat & TXSTATUS_ERROR) {
922 if (txstat & TXSTATUS_UNDERRUN) {
924 ndev->stats.tx_fifo_errors++;
926 if (txstat & TXSTATUS_LATECOLL) {
928 ndev->stats.tx_aborted_errors++;
930 if (txstat & TXSTATUS_EXCESSCOLL) {
931 /* Excessive collision */
932 ndev->stats.tx_aborted_errors++;
934 if (txstat & TXSTATUS_EXCESSDEFER) {
936 ndev->stats.tx_aborted_errors++;
938 ndev->stats.tx_errors++;
941 ndev->stats.tx_packets++;
942 ndev->stats.tx_bytes += skblen;
945 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
948 if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) {
949 if (netif_queue_stopped(ndev))
950 netif_wake_queue(ndev);
954 static int __lpc_handle_recv(struct net_device *ndev, int budget)
956 struct netdata_local *pldat = netdev_priv(ndev);
958 u32 rxconsidx, len, ethst;
959 struct rx_status_t *prxstat;
963 /* Get the current RX buffer indexes */
964 rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
965 while (rx_done < budget && rxconsidx !=
966 readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
967 /* Get pointer to receive status */
968 prxstat = &pldat->rx_stat_v[rxconsidx];
969 len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
972 ethst = prxstat->statusinfo;
973 if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
974 (RXSTATUS_ERROR | RXSTATUS_RANGE))
975 ethst &= ~RXSTATUS_ERROR;
977 if (ethst & RXSTATUS_ERROR) {
978 int si = prxstat->statusinfo;
980 if (si & RXSTATUS_OVERRUN) {
982 ndev->stats.rx_fifo_errors++;
983 } else if (si & RXSTATUS_CRC) {
985 ndev->stats.rx_crc_errors++;
986 } else if (si & RXSTATUS_LENGTH) {
988 ndev->stats.rx_length_errors++;
989 } else if (si & RXSTATUS_ERROR) {
991 ndev->stats.rx_length_errors++;
993 ndev->stats.rx_errors++;
996 skb = dev_alloc_skb(len);
998 ndev->stats.rx_dropped++;
1000 prdbuf = skb_put(skb, len);
1002 /* Copy packet from buffer */
1003 memcpy(prdbuf, pldat->rx_buff_v +
1004 rxconsidx * ENET_MAXF_SIZE, len);
1006 /* Pass to upper layer */
1007 skb->protocol = eth_type_trans(skb, ndev);
1008 netif_receive_skb(skb);
1009 ndev->stats.rx_packets++;
1010 ndev->stats.rx_bytes += len;
1014 /* Increment consume index */
1015 rxconsidx = rxconsidx + 1;
1016 if (rxconsidx >= ENET_RX_DESC)
1019 LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
1026 static int lpc_eth_poll(struct napi_struct *napi, int budget)
1028 struct netdata_local *pldat = container_of(napi,
1029 struct netdata_local, napi);
1030 struct net_device *ndev = pldat->ndev;
1032 struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
1034 __netif_tx_lock(txq, smp_processor_id());
1035 __lpc_handle_xmit(ndev);
1036 __netif_tx_unlock(txq);
1037 rx_done = __lpc_handle_recv(ndev, budget);
1039 if (rx_done < budget) {
1040 napi_complete(napi);
1041 lpc_eth_enable_int(pldat->net_base);
1047 static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
1049 struct net_device *ndev = dev_id;
1050 struct netdata_local *pldat = netdev_priv(ndev);
1053 spin_lock(&pldat->lock);
1055 tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
1056 /* Clear interrupts */
1057 writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
1059 lpc_eth_disable_int(pldat->net_base);
1060 if (likely(napi_schedule_prep(&pldat->napi)))
1061 __napi_schedule(&pldat->napi);
1063 spin_unlock(&pldat->lock);
1068 static int lpc_eth_close(struct net_device *ndev)
1070 unsigned long flags;
1071 struct netdata_local *pldat = netdev_priv(ndev);
1073 if (netif_msg_ifdown(pldat))
1074 dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
1076 napi_disable(&pldat->napi);
1077 netif_stop_queue(ndev);
1080 phy_stop(pldat->phy_dev);
1082 spin_lock_irqsave(&pldat->lock, flags);
1083 __lpc_eth_reset(pldat);
1084 netif_carrier_off(ndev);
1085 writel(0, LPC_ENET_MAC1(pldat->net_base));
1086 writel(0, LPC_ENET_MAC2(pldat->net_base));
1087 spin_unlock_irqrestore(&pldat->lock, flags);
1089 __lpc_eth_clock_enable(pldat, false);
1094 static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1096 struct netdata_local *pldat = netdev_priv(ndev);
1099 struct txrx_desc_t *ptxrxdesc;
1103 spin_lock_irq(&pldat->lock);
1105 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
1106 /* This function should never be called when there are no
1108 netif_stop_queue(ndev);
1109 spin_unlock_irq(&pldat->lock);
1110 WARN(1, "BUG! TX request when no free TX buffers!\n");
1111 return NETDEV_TX_BUSY;
1114 /* Get the next TX descriptor index */
1115 txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1117 /* Setup control for the transfer */
1118 ptxstat = &pldat->tx_stat_v[txidx];
1120 ptxrxdesc = &pldat->tx_desc_v[txidx];
1121 ptxrxdesc->control =
1122 (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
1124 /* Copy data to the DMA buffer */
1125 memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
1127 /* Save the buffer and increment the buffer counter */
1128 pldat->skblen[txidx] = len;
1129 pldat->num_used_tx_buffs++;
1131 /* Start transmit */
1133 if (txidx >= ENET_TX_DESC)
1135 writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1137 /* Stop queue if no more TX buffers */
1138 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
1139 netif_stop_queue(ndev);
1141 spin_unlock_irq(&pldat->lock);
1144 return NETDEV_TX_OK;
1147 static int lpc_set_mac_address(struct net_device *ndev, void *p)
1149 struct sockaddr *addr = p;
1150 struct netdata_local *pldat = netdev_priv(ndev);
1151 unsigned long flags;
1153 if (!is_valid_ether_addr(addr->sa_data))
1154 return -EADDRNOTAVAIL;
1155 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
1157 spin_lock_irqsave(&pldat->lock, flags);
1159 /* Set station address */
1160 __lpc_set_mac(pldat, ndev->dev_addr);
1162 spin_unlock_irqrestore(&pldat->lock, flags);
1167 static void lpc_eth_set_multicast_list(struct net_device *ndev)
1169 struct netdata_local *pldat = netdev_priv(ndev);
1170 struct netdev_hw_addr_list *mcptr = &ndev->mc;
1171 struct netdev_hw_addr *ha;
1172 u32 tmp32, hash_val, hashlo, hashhi;
1173 unsigned long flags;
1175 spin_lock_irqsave(&pldat->lock, flags);
1177 /* Set station address */
1178 __lpc_set_mac(pldat, ndev->dev_addr);
1180 tmp32 = LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
1182 if (ndev->flags & IFF_PROMISC)
1183 tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
1184 LPC_RXFLTRW_ACCEPTUMULTICAST;
1185 if (ndev->flags & IFF_ALLMULTI)
1186 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
1188 if (netdev_hw_addr_list_count(mcptr))
1189 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
1191 writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
1194 /* Set initial hash table */
1198 /* 64 bits : multicast address in hash table */
1199 netdev_hw_addr_list_for_each(ha, mcptr) {
1200 hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
1203 hashhi |= 1 << (hash_val - 32);
1205 hashlo |= 1 << hash_val;
1208 writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
1209 writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
1211 spin_unlock_irqrestore(&pldat->lock, flags);
1214 static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1216 struct netdata_local *pldat = netdev_priv(ndev);
1217 struct phy_device *phydev = pldat->phy_dev;
1219 if (!netif_running(ndev))
1225 return phy_mii_ioctl(phydev, req, cmd);
1228 static int lpc_eth_open(struct net_device *ndev)
1230 struct netdata_local *pldat = netdev_priv(ndev);
1232 if (netif_msg_ifup(pldat))
1233 dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
1235 if (!is_valid_ether_addr(ndev->dev_addr))
1236 return -EADDRNOTAVAIL;
1238 __lpc_eth_clock_enable(pldat, true);
1240 /* Reset and initialize */
1241 __lpc_eth_reset(pldat);
1242 __lpc_eth_init(pldat);
1244 /* schedule a link state check */
1245 phy_start(pldat->phy_dev);
1246 netif_start_queue(ndev);
1247 napi_enable(&pldat->napi);
1255 static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
1256 struct ethtool_drvinfo *info)
1258 strcpy(info->driver, MODNAME);
1259 strcpy(info->version, DRV_VERSION);
1260 strcpy(info->bus_info, dev_name(ndev->dev.parent));
1263 static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
1265 struct netdata_local *pldat = netdev_priv(ndev);
1267 return pldat->msg_enable;
1270 static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
1272 struct netdata_local *pldat = netdev_priv(ndev);
1274 pldat->msg_enable = level;
1277 static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
1278 struct ethtool_cmd *cmd)
1280 struct netdata_local *pldat = netdev_priv(ndev);
1281 struct phy_device *phydev = pldat->phy_dev;
1286 return phy_ethtool_gset(phydev, cmd);
1289 static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
1290 struct ethtool_cmd *cmd)
1292 struct netdata_local *pldat = netdev_priv(ndev);
1293 struct phy_device *phydev = pldat->phy_dev;
1298 return phy_ethtool_sset(phydev, cmd);
1301 static const struct ethtool_ops lpc_eth_ethtool_ops = {
1302 .get_drvinfo = lpc_eth_ethtool_getdrvinfo,
1303 .get_settings = lpc_eth_ethtool_getsettings,
1304 .set_settings = lpc_eth_ethtool_setsettings,
1305 .get_msglevel = lpc_eth_ethtool_getmsglevel,
1306 .set_msglevel = lpc_eth_ethtool_setmsglevel,
1307 .get_link = ethtool_op_get_link,
1310 static const struct net_device_ops lpc_netdev_ops = {
1311 .ndo_open = lpc_eth_open,
1312 .ndo_stop = lpc_eth_close,
1313 .ndo_start_xmit = lpc_eth_hard_start_xmit,
1314 .ndo_set_rx_mode = lpc_eth_set_multicast_list,
1315 .ndo_do_ioctl = lpc_eth_ioctl,
1316 .ndo_set_mac_address = lpc_set_mac_address,
1317 .ndo_change_mtu = eth_change_mtu,
1320 static int lpc_eth_drv_probe(struct platform_device *pdev)
1322 struct resource *res;
1323 struct net_device *ndev;
1324 struct netdata_local *pldat;
1325 struct phy_device *phydev;
1326 dma_addr_t dma_handle;
1330 /* Setup network interface for RMII or MII mode */
1331 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
1332 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
1333 if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII)
1334 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
1336 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
1337 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
1339 /* Get platform resources */
1340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1341 irq = platform_get_irq(pdev, 0);
1342 if ((!res) || (irq < 0) || (irq >= NR_IRQS)) {
1343 dev_err(&pdev->dev, "error getting resources.\n");
1348 /* Allocate net driver data structure */
1349 ndev = alloc_etherdev(sizeof(struct netdata_local));
1351 dev_err(&pdev->dev, "could not allocate device.\n");
1356 SET_NETDEV_DEV(ndev, &pdev->dev);
1358 pldat = netdev_priv(ndev);
1362 spin_lock_init(&pldat->lock);
1364 /* Save resources */
1367 /* Get clock for the device */
1368 pldat->clk = clk_get(&pdev->dev, NULL);
1369 if (IS_ERR(pldat->clk)) {
1370 dev_err(&pdev->dev, "error getting clock.\n");
1371 ret = PTR_ERR(pldat->clk);
1372 goto err_out_free_dev;
1375 /* Enable network clock */
1376 __lpc_eth_clock_enable(pldat, true);
1379 pldat->net_base = ioremap(res->start, res->end - res->start + 1);
1380 if (!pldat->net_base) {
1381 dev_err(&pdev->dev, "failed to map registers\n");
1383 goto err_out_disable_clocks;
1385 ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
1388 dev_err(&pdev->dev, "error requesting interrupt.\n");
1389 goto err_out_iounmap;
1392 /* Fill in the fields of the device structure with ethernet values. */
1395 /* Setup driver functions */
1396 ndev->netdev_ops = &lpc_netdev_ops;
1397 ndev->ethtool_ops = &lpc_eth_ethtool_ops;
1398 ndev->watchdog_timeo = msecs_to_jiffies(2500);
1400 /* Get size of DMA buffers/descriptors region */
1401 pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
1402 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
1403 pldat->dma_buff_base_v = 0;
1405 if (use_iram_for_net(&pldat->pdev->dev)) {
1406 dma_handle = LPC32XX_IRAM_BASE;
1407 if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
1408 pldat->dma_buff_base_v =
1409 io_p2v(LPC32XX_IRAM_BASE);
1412 "IRAM not big enough for net buffers, using SDRAM instead.\n");
1415 if (pldat->dma_buff_base_v == 0) {
1416 pldat->pdev->dev.coherent_dma_mask = 0xFFFFFFFF;
1417 pldat->pdev->dev.dma_mask = &pldat->pdev->dev.coherent_dma_mask;
1418 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
1420 /* Allocate a chunk of memory for the DMA ethernet buffers
1422 pldat->dma_buff_base_v =
1423 dma_alloc_coherent(&pldat->pdev->dev,
1424 pldat->dma_buff_size, &dma_handle,
1427 if (pldat->dma_buff_base_v == NULL) {
1428 dev_err(&pdev->dev, "error getting DMA region.\n");
1430 goto err_out_free_irq;
1433 pldat->dma_buff_base_p = dma_handle;
1435 netdev_dbg(ndev, "IO address start :0x%08x\n",
1437 netdev_dbg(ndev, "IO address size :%d\n",
1438 res->end - res->start + 1);
1439 netdev_dbg(ndev, "IO address (mapped) :0x%p\n",
1441 netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);
1442 netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size);
1443 netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
1444 pldat->dma_buff_base_p);
1445 netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
1446 pldat->dma_buff_base_v);
1448 /* Get MAC address from current HW setting (POR state is all zeros) */
1449 __lpc_get_mac(pldat, ndev->dev_addr);
1451 #ifdef CONFIG_OF_NET
1452 if (!is_valid_ether_addr(ndev->dev_addr)) {
1453 const char *macaddr = of_get_mac_address(pdev->dev.of_node);
1455 memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
1458 if (!is_valid_ether_addr(ndev->dev_addr))
1459 eth_hw_addr_random(ndev);
1461 /* Reset the ethernet controller */
1462 __lpc_eth_reset(pldat);
1464 /* then shut everything down to save power */
1465 __lpc_eth_shutdown(pldat);
1467 /* Set default parameters */
1468 pldat->msg_enable = NETIF_MSG_LINK;
1470 /* Force an MII interface reset and clock setup */
1471 __lpc_mii_mngt_reset(pldat);
1473 /* Force default PHY interface setup in chip, this will probably be
1474 changed by the PHY driver */
1477 pldat->duplex = DUPLEX_FULL;
1478 __lpc_params_setup(pldat);
1480 netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
1482 ret = register_netdev(ndev);
1484 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1485 goto err_out_dma_unmap;
1487 platform_set_drvdata(pdev, ndev);
1489 if (lpc_mii_init(pldat) != 0)
1490 goto err_out_unregister_netdev;
1492 netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
1493 res->start, ndev->irq);
1495 phydev = pldat->phy_dev;
1497 device_init_wakeup(&pdev->dev, 1);
1498 device_set_wakeup_enable(&pdev->dev, 0);
1502 err_out_unregister_netdev:
1503 platform_set_drvdata(pdev, NULL);
1504 unregister_netdev(ndev);
1506 if (!use_iram_for_net(&pldat->pdev->dev) ||
1507 pldat->dma_buff_size > lpc32xx_return_iram_size())
1508 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1509 pldat->dma_buff_base_v,
1510 pldat->dma_buff_base_p);
1512 free_irq(ndev->irq, ndev);
1514 iounmap(pldat->net_base);
1515 err_out_disable_clocks:
1516 clk_disable(pldat->clk);
1517 clk_put(pldat->clk);
1521 pr_err("%s: not found (%d).\n", MODNAME, ret);
1525 static int lpc_eth_drv_remove(struct platform_device *pdev)
1527 struct net_device *ndev = platform_get_drvdata(pdev);
1528 struct netdata_local *pldat = netdev_priv(ndev);
1530 unregister_netdev(ndev);
1531 platform_set_drvdata(pdev, NULL);
1533 if (!use_iram_for_net(&pldat->pdev->dev) ||
1534 pldat->dma_buff_size > lpc32xx_return_iram_size())
1535 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1536 pldat->dma_buff_base_v,
1537 pldat->dma_buff_base_p);
1538 free_irq(ndev->irq, ndev);
1539 iounmap(pldat->net_base);
1540 mdiobus_free(pldat->mii_bus);
1541 clk_disable(pldat->clk);
1542 clk_put(pldat->clk);
1549 static int lpc_eth_drv_suspend(struct platform_device *pdev,
1552 struct net_device *ndev = platform_get_drvdata(pdev);
1553 struct netdata_local *pldat = netdev_priv(ndev);
1555 if (device_may_wakeup(&pdev->dev))
1556 enable_irq_wake(ndev->irq);
1559 if (netif_running(ndev)) {
1560 netif_device_detach(ndev);
1561 __lpc_eth_shutdown(pldat);
1562 clk_disable(pldat->clk);
1565 * Reset again now clock is disable to be sure
1568 __lpc_eth_reset(pldat);
1575 static int lpc_eth_drv_resume(struct platform_device *pdev)
1577 struct net_device *ndev = platform_get_drvdata(pdev);
1578 struct netdata_local *pldat;
1580 if (device_may_wakeup(&pdev->dev))
1581 disable_irq_wake(ndev->irq);
1584 if (netif_running(ndev)) {
1585 pldat = netdev_priv(ndev);
1587 /* Enable interface clock */
1588 clk_enable(pldat->clk);
1590 /* Reset and initialize */
1591 __lpc_eth_reset(pldat);
1592 __lpc_eth_init(pldat);
1594 netif_device_attach(ndev);
1603 static const struct of_device_id lpc_eth_match[] = {
1604 { .compatible = "nxp,lpc-eth" },
1607 MODULE_DEVICE_TABLE(of, lpc_eth_match);
1610 static struct platform_driver lpc_eth_driver = {
1611 .probe = lpc_eth_drv_probe,
1612 .remove = __devexit_p(lpc_eth_drv_remove),
1614 .suspend = lpc_eth_drv_suspend,
1615 .resume = lpc_eth_drv_resume,
1619 .of_match_table = of_match_ptr(lpc_eth_match),
1623 module_platform_driver(lpc_eth_driver);
1625 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1626 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1627 MODULE_DESCRIPTION("LPC Ethernet Driver");
1628 MODULE_LICENSE("GPL");