drivers/net/ethernet/ni/nixge.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016-2017, National Instruments Corp.
   3  *
   4  * Author: Moritz Fischer <mdf@kernel.org>
   5  */
   6
   7 #include <linux/etherdevice.h>
   8 #include <linux/module.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/of.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_net.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/skbuff.h>
  15 #include <linux/phy.h>
  16 #include <linux/mii.h>
  17 #include <linux/nvmem-consumer.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/iopoll.h>
  20
  21 #define TX_BD_NUM               64
  22 #define RX_BD_NUM               128
  23
  24 /* Axi DMA Register definitions */
  25 #define XAXIDMA_TX_CR_OFFSET    0x00 /* Channel control */
  26 #define XAXIDMA_TX_SR_OFFSET    0x04 /* Status */
  27 #define XAXIDMA_TX_CDESC_OFFSET 0x08 /* Current descriptor pointer */
  28 #define XAXIDMA_TX_TDESC_OFFSET 0x10 /* Tail descriptor pointer */
  29
  30 #define XAXIDMA_RX_CR_OFFSET    0x30 /* Channel control */
  31 #define XAXIDMA_RX_SR_OFFSET    0x34 /* Status */
  32 #define XAXIDMA_RX_CDESC_OFFSET 0x38 /* Current descriptor pointer */
  33 #define XAXIDMA_RX_TDESC_OFFSET 0x40 /* Tail descriptor pointer */
  34
  35 #define XAXIDMA_CR_RUNSTOP_MASK 0x1 /* Start/stop DMA channel */
  36 #define XAXIDMA_CR_RESET_MASK   0x4 /* Reset DMA engine */
  37
  38 #define XAXIDMA_BD_CTRL_LENGTH_MASK     0x007FFFFF /* Requested len */
  39 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  40 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  41 #define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
  42
  43 #define XAXIDMA_DELAY_MASK              0xFF000000 /* Delay timeout counter */
  44 #define XAXIDMA_COALESCE_MASK           0x00FF0000 /* Coalesce counter */
  45
  46 #define XAXIDMA_DELAY_SHIFT             24
  47 #define XAXIDMA_COALESCE_SHIFT          16
  48
  49 #define XAXIDMA_IRQ_IOC_MASK            0x00001000 /* Completion intr */
  50 #define XAXIDMA_IRQ_DELAY_MASK          0x00002000 /* Delay interrupt */
  51 #define XAXIDMA_IRQ_ERROR_MASK          0x00004000 /* Error interrupt */
  52 #define XAXIDMA_IRQ_ALL_MASK            0x00007000 /* All interrupts */
  53
  54 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
  55 #define XAXIDMA_DFT_TX_THRESHOLD        24
  56 #define XAXIDMA_DFT_TX_WAITBOUND        254
  57 #define XAXIDMA_DFT_RX_THRESHOLD        24
  58 #define XAXIDMA_DFT_RX_WAITBOUND        254
  59
  60 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
  61 #define XAXIDMA_BD_STS_COMPLETE_MASK    0x80000000 /* Completed */
  62 #define XAXIDMA_BD_STS_DEC_ERR_MASK     0x40000000 /* Decode error */
  63 #define XAXIDMA_BD_STS_SLV_ERR_MASK     0x20000000 /* Slave error */
  64 #define XAXIDMA_BD_STS_INT_ERR_MASK     0x10000000 /* Internal err */
  65 #define XAXIDMA_BD_STS_ALL_ERR_MASK     0x70000000 /* All errors */
  66 #define XAXIDMA_BD_STS_RXSOF_MASK       0x08000000 /* First rx pkt */
  67 #define XAXIDMA_BD_STS_RXEOF_MASK       0x04000000 /* Last rx pkt */
  68 #define XAXIDMA_BD_STS_ALL_MASK         0xFC000000 /* All status bits */
  69
  70 #define NIXGE_REG_CTRL_OFFSET   0x4000
  71 #define NIXGE_REG_INFO          0x00
  72 #define NIXGE_REG_MAC_CTL       0x04
  73 #define NIXGE_REG_PHY_CTL       0x08
  74 #define NIXGE_REG_LED_CTL       0x0c
  75 #define NIXGE_REG_MDIO_DATA     0x10
  76 #define NIXGE_REG_MDIO_ADDR     0x14
  77 #define NIXGE_REG_MDIO_OP       0x18
  78 #define NIXGE_REG_MDIO_CTRL     0x1c
  79
  80 #define NIXGE_ID_LED_CTL_EN     BIT(0)
  81 #define NIXGE_ID_LED_CTL_VAL    BIT(1)
  82
  83 #define NIXGE_MDIO_CLAUSE45     BIT(12)
  84 #define NIXGE_MDIO_CLAUSE22     0
  85 #define NIXGE_MDIO_OP(n)     (((n) & 0x3) << 10)
  86 #define NIXGE_MDIO_OP_ADDRESS   0
  87 #define NIXGE_MDIO_C45_WRITE    BIT(0)
  88 #define NIXGE_MDIO_C45_READ     (BIT(1) | BIT(0))
  89 #define NIXGE_MDIO_C22_WRITE    BIT(0)
  90 #define NIXGE_MDIO_C22_READ     BIT(1)
  91 #define NIXGE_MDIO_ADDR(n)   (((n) & 0x1f) << 5)
  92 #define NIXGE_MDIO_MMD(n)    (((n) & 0x1f) << 0)
  93
  94 #define NIXGE_REG_MAC_LSB       0x1000
  95 #define NIXGE_REG_MAC_MSB       0x1004
  96
  97 /* Packet size info */
  98 #define NIXGE_HDR_SIZE          14 /* Size of Ethernet header */
  99 #define NIXGE_TRL_SIZE          4 /* Size of Ethernet trailer (FCS) */
 100 #define NIXGE_MTU               1500 /* Max MTU of an Ethernet frame */
 101 #define NIXGE_JUMBO_MTU         9000 /* Max MTU of a jumbo Eth. frame */
 102
 103 #define NIXGE_MAX_FRAME_SIZE     (NIXGE_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 104 #define NIXGE_MAX_JUMBO_FRAME_SIZE \
 105         (NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
 106
 107 enum nixge_version {
 108         NIXGE_V2,
 109         NIXGE_V3,
 110         NIXGE_VERSION_COUNT
 111 };
 112
 113 struct nixge_hw_dma_bd {
 114         u32 next_lo;
 115         u32 next_hi;
 116         u32 phys_lo;
 117         u32 phys_hi;
 118         u32 reserved3;
 119         u32 reserved4;
 120         u32 cntrl;
 121         u32 status;
 122         u32 app0;
 123         u32 app1;
 124         u32 app2;
 125         u32 app3;
 126         u32 app4;
 127         u32 sw_id_offset_lo;
 128         u32 sw_id_offset_hi;
 129         u32 reserved6;
 130 };
 131
 132 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 133 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 134         do { \
 135                 (bd)->field##_lo = lower_32_bits((addr)); \
 136                 (bd)->field##_hi = upper_32_bits((addr)); \
 137         } while (0)
 138 #else
 139 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
 140         ((bd)->field##_lo = lower_32_bits((addr)))
 141 #endif
 142
 143 #define nixge_hw_dma_bd_set_phys(bd, addr) \
 144         nixge_hw_dma_bd_set_addr((bd), phys, (addr))
 145
 146 #define nixge_hw_dma_bd_set_next(bd, addr) \
 147         nixge_hw_dma_bd_set_addr((bd), next, (addr))
 148
 149 #define nixge_hw_dma_bd_set_offset(bd, addr) \
 150         nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
 151
 152 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 153 #define nixge_hw_dma_bd_get_addr(bd, field) \
 154         (dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
 155 #else
 156 #define nixge_hw_dma_bd_get_addr(bd, field) \
 157         (dma_addr_t)((bd)->field##_lo)
 158 #endif
 159
 160 struct nixge_tx_skb {
 161         struct sk_buff *skb;
 162         dma_addr_t mapping;
 163         size_t size;
 164         bool mapped_as_page;
 165 };
 166
 167 struct nixge_priv {
 168         struct net_device *ndev;
 169         struct napi_struct napi;
 170         struct device *dev;
 171
 172         /* Connection to PHY device */
 173         struct device_node *phy_node;
 174         phy_interface_t         phy_mode;
 175
 176         int link;
 177         unsigned int speed;
 178         unsigned int duplex;
 179
 180         /* MDIO bus data */
 181         struct mii_bus *mii_bus;        /* MII bus reference */
 182
 183         /* IO registers, dma functions and IRQs */
 184         void __iomem *ctrl_regs;
 185         void __iomem *dma_regs;
 186
 187         struct tasklet_struct dma_err_tasklet;
 188
 189         int tx_irq;
 190         int rx_irq;
 191
 192         /* Buffer descriptors */
 193         struct nixge_hw_dma_bd *tx_bd_v;
 194         struct nixge_tx_skb *tx_skb;
 195         dma_addr_t tx_bd_p;
 196
 197         struct nixge_hw_dma_bd *rx_bd_v;
 198         dma_addr_t rx_bd_p;
 199         u32 tx_bd_ci;
 200         u32 tx_bd_tail;
 201         u32 rx_bd_ci;
 202
 203         u32 coalesce_count_rx;
 204         u32 coalesce_count_tx;
 205 };
 206
 207 static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 208 {
 209         writel(val, priv->dma_regs + offset);
 210 }
 211
 212 static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
 213                                      dma_addr_t addr)
 214 {
 215         writel(lower_32_bits(addr), priv->dma_regs + offset);
 216 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 217         writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
 218 #endif
 219 }
 220
 221 static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
 222 {
 223         return readl(priv->dma_regs + offset);
 224 }
 225
 226 static void nixge_ctrl_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
 227 {
 228         writel(val, priv->ctrl_regs + offset);
 229 }
 230
 231 static u32 nixge_ctrl_read_reg(struct nixge_priv *priv, off_t offset)
 232 {
 233         return readl(priv->ctrl_regs + offset);
 234 }
 235
 236 #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 237         readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \
 238                            (sleep_us), (timeout_us))
 239
 240 #define nixge_dma_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 241         readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \
 242                            (sleep_us), (timeout_us))
 243
 244 static void nixge_hw_dma_bd_release(struct net_device *ndev)
 245 {
 246         struct nixge_priv *priv = netdev_priv(ndev);
 247         dma_addr_t phys_addr;
 248         struct sk_buff *skb;
 249         int i;
 250
 251         if (priv->rx_bd_v) {
 252                 for (i = 0; i < RX_BD_NUM; i++) {
 253                         phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 254                                                              phys);
 255
 256                         dma_unmap_single(ndev->dev.parent, phys_addr,
 257                                          NIXGE_MAX_JUMBO_FRAME_SIZE,
 258                                          DMA_FROM_DEVICE);
 259
 260                         skb = (struct sk_buff *)(uintptr_t)
 261                                 nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
 262                                                          sw_id_offset);
 263                         dev_kfree_skb(skb);
 264                 }
 265
 266                 dma_free_coherent(ndev->dev.parent,
 267                                   sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 268                                   priv->rx_bd_v,
 269                                   priv->rx_bd_p);
 270         }
 271
 272         if (priv->tx_skb)
 273                 devm_kfree(ndev->dev.parent, priv->tx_skb);
 274
 275         if (priv->tx_bd_v)
 276                 dma_free_coherent(ndev->dev.parent,
 277                                   sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 278                                   priv->tx_bd_v,
 279                                   priv->tx_bd_p);
 280 }
 281
 282 static int nixge_hw_dma_bd_init(struct net_device *ndev)
 283 {
 284         struct nixge_priv *priv = netdev_priv(ndev);
 285         struct sk_buff *skb;
 286         dma_addr_t phys;
 287         u32 cr;
 288         int i;
 289
 290         /* Reset the indexes which are used for accessing the BDs */
 291         priv->tx_bd_ci = 0;
 292         priv->tx_bd_tail = 0;
 293         priv->rx_bd_ci = 0;
 294
 295         /* Allocate the Tx and Rx buffer descriptors. */
 296         priv->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 297                                            sizeof(*priv->tx_bd_v) * TX_BD_NUM,
 298                                            &priv->tx_bd_p, GFP_KERNEL);
 299         if (!priv->tx_bd_v)
 300                 goto out;
 301
 302         priv->tx_skb = devm_kcalloc(ndev->dev.parent,
 303                                     TX_BD_NUM, sizeof(*priv->tx_skb),
 304                                     GFP_KERNEL);
 305         if (!priv->tx_skb)
 306                 goto out;
 307
 308         priv->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
 309                                            sizeof(*priv->rx_bd_v) * RX_BD_NUM,
 310                                            &priv->rx_bd_p, GFP_KERNEL);
 311         if (!priv->rx_bd_v)
 312                 goto out;
 313
 314         for (i = 0; i < TX_BD_NUM; i++) {
 315                 nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
 316                                          priv->tx_bd_p +
 317                                          sizeof(*priv->tx_bd_v) *
 318                                          ((i + 1) % TX_BD_NUM));
 319         }
 320
 321         for (i = 0; i < RX_BD_NUM; i++) {
 322                 nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
 323                                          priv->rx_bd_p
 324                                          + sizeof(*priv->rx_bd_v) *
 325                                          ((i + 1) % RX_BD_NUM));
 326
 327                 skb = __netdev_alloc_skb_ip_align(ndev,
 328                                                   NIXGE_MAX_JUMBO_FRAME_SIZE,
 329                                                   GFP_KERNEL);
 330                 if (!skb)
 331                         goto out;
 332
 333                 nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], (uintptr_t)skb);
 334                 phys = dma_map_single(ndev->dev.parent, skb->data,
 335                                       NIXGE_MAX_JUMBO_FRAME_SIZE,
 336                                       DMA_FROM_DEVICE);
 337
 338                 nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
 339
 340                 priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 341         }
 342
 343         /* Start updating the Rx channel control register */
 344         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 345         /* Update the interrupt coalesce count */
 346         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 347               ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
 348         /* Update the delay timer count */
 349         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 350               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 351         /* Enable coalesce, delay timer and error interrupts */
 352         cr |= XAXIDMA_IRQ_ALL_MASK;
 353         /* Write to the Rx channel control register */
 354         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 355
 356         /* Start updating the Tx channel control register */
 357         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 358         /* Update the interrupt coalesce count */
 359         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 360               ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
 361         /* Update the delay timer count */
 362         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 363               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 364         /* Enable coalesce, delay timer and error interrupts */
 365         cr |= XAXIDMA_IRQ_ALL_MASK;
 366         /* Write to the Tx channel control register */
 367         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 368
 369         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 370          * halted state. This will make the Rx side ready for reception.
 371          */
 372         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
 373         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 374         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 375                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 376         nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
 377                             (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
 378
 379         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 380          * Tx channel is now ready to run. But only after we write to the
 381          * tail pointer register that the Tx channel will start transmitting.
 382          */
 383         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
 384         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 385         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 386                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 387
 388         return 0;
 389 out:
 390         nixge_hw_dma_bd_release(ndev);
 391         return -ENOMEM;
 392 }
 393
 394 static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
 395 {
 396         u32 status;
 397         int err;
 398
 399         /* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
 400          * The reset process of Axi DMA takes a while to complete as all
 401          * pending commands/transfers will be flushed or completed during
 402          * this reset process.
 403          */
 404         nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
 405         err = nixge_dma_poll_timeout(priv, offset, status,
 406                                      !(status & XAXIDMA_CR_RESET_MASK), 10,
 407                                      1000);
 408         if (err)
 409                 netdev_err(priv->ndev, "%s: DMA reset timeout!\n", __func__);
 410 }
 411
 412 static void nixge_device_reset(struct net_device *ndev)
 413 {
 414         struct nixge_priv *priv = netdev_priv(ndev);
 415
 416         __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET);
 417         __nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET);
 418
 419         if (nixge_hw_dma_bd_init(ndev))
 420                 netdev_err(ndev, "%s: descriptor allocation failed\n",
 421                            __func__);
 422
 423         netif_trans_update(ndev);
 424 }
 425
 426 static void nixge_handle_link_change(struct net_device *ndev)
 427 {
 428         struct nixge_priv *priv = netdev_priv(ndev);
 429         struct phy_device *phydev = ndev->phydev;
 430
 431         if (phydev->link != priv->link || phydev->speed != priv->speed ||
 432             phydev->duplex != priv->duplex) {
 433                 priv->link = phydev->link;
 434                 priv->speed = phydev->speed;
 435                 priv->duplex = phydev->duplex;
 436                 phy_print_status(phydev);
 437         }
 438 }
 439
 440 static void nixge_tx_skb_unmap(struct nixge_priv *priv,
 441                                struct nixge_tx_skb *tx_skb)
 442 {
 443         if (tx_skb->mapping) {
 444                 if (tx_skb->mapped_as_page)
 445                         dma_unmap_page(priv->ndev->dev.parent, tx_skb->mapping,
 446                                        tx_skb->size, DMA_TO_DEVICE);
 447                 else
 448                         dma_unmap_single(priv->ndev->dev.parent,
 449                                          tx_skb->mapping,
 450                                          tx_skb->size, DMA_TO_DEVICE);
 451                 tx_skb->mapping = 0;
 452         }
 453
 454         if (tx_skb->skb) {
 455                 dev_kfree_skb_any(tx_skb->skb);
 456                 tx_skb->skb = NULL;
 457         }
 458 }
 459
 460 static void nixge_start_xmit_done(struct net_device *ndev)
 461 {
 462         struct nixge_priv *priv = netdev_priv(ndev);
 463         struct nixge_hw_dma_bd *cur_p;
 464         struct nixge_tx_skb *tx_skb;
 465         unsigned int status = 0;
 466         u32 packets = 0;
 467         u32 size = 0;
 468
 469         cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 470         tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 471
 472         status = cur_p->status;
 473
 474         while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
 475                 nixge_tx_skb_unmap(priv, tx_skb);
 476                 cur_p->status = 0;
 477
 478                 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 479                 packets++;
 480
 481                 ++priv->tx_bd_ci;
 482                 priv->tx_bd_ci %= TX_BD_NUM;
 483                 cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
 484                 tx_skb = &priv->tx_skb[priv->tx_bd_ci];
 485                 status = cur_p->status;
 486         }
 487
 488         ndev->stats.tx_packets += packets;
 489         ndev->stats.tx_bytes += size;
 490
 491         if (packets)
 492                 netif_wake_queue(ndev);
 493 }
 494
 495 static int nixge_check_tx_bd_space(struct nixge_priv *priv,
 496                                    int num_frag)
 497 {
 498         struct nixge_hw_dma_bd *cur_p;
 499
 500         cur_p = &priv->tx_bd_v[(priv->tx_bd_tail + num_frag) % TX_BD_NUM];
 501         if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
 502                 return NETDEV_TX_BUSY;
 503         return 0;
 504 }
 505
 506 static netdev_tx_t nixge_start_xmit(struct sk_buff *skb,
 507                                     struct net_device *ndev)
 508 {
 509         struct nixge_priv *priv = netdev_priv(ndev);
 510         struct nixge_hw_dma_bd *cur_p;
 511         struct nixge_tx_skb *tx_skb;
 512         dma_addr_t tail_p, cur_phys;
 513         skb_frag_t *frag;
 514         u32 num_frag;
 515         u32 ii;
 516
 517         num_frag = skb_shinfo(skb)->nr_frags;
 518         cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 519         tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 520
 521         if (nixge_check_tx_bd_space(priv, num_frag)) {
 522                 if (!netif_queue_stopped(ndev))
 523                         netif_stop_queue(ndev);
 524                 return NETDEV_TX_OK;
 525         }
 526
 527         cur_phys = dma_map_single(ndev->dev.parent, skb->data,
 528                                   skb_headlen(skb), DMA_TO_DEVICE);
 529         if (dma_mapping_error(ndev->dev.parent, cur_phys))
 530                 goto drop;
 531         nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 532
 533         cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
 534
 535         tx_skb->skb = NULL;
 536         tx_skb->mapping = cur_phys;
 537         tx_skb->size = skb_headlen(skb);
 538         tx_skb->mapped_as_page = false;
 539
 540         for (ii = 0; ii < num_frag; ii++) {
 541                 ++priv->tx_bd_tail;
 542                 priv->tx_bd_tail %= TX_BD_NUM;
 543                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 544                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 545                 frag = &skb_shinfo(skb)->frags[ii];
 546
 547                 cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
 548                                             skb_frag_size(frag),
 549                                             DMA_TO_DEVICE);
 550                 if (dma_mapping_error(ndev->dev.parent, cur_phys))
 551                         goto frag_err;
 552                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 553
 554                 cur_p->cntrl = skb_frag_size(frag);
 555
 556                 tx_skb->skb = NULL;
 557                 tx_skb->mapping = cur_phys;
 558                 tx_skb->size = skb_frag_size(frag);
 559                 tx_skb->mapped_as_page = true;
 560         }
 561
 562         /* last buffer of the frame */
 563         tx_skb->skb = skb;
 564
 565         cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
 566
 567         tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
 568         /* Start the transfer */
 569         nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
 570         ++priv->tx_bd_tail;
 571         priv->tx_bd_tail %= TX_BD_NUM;
 572
 573         return NETDEV_TX_OK;
 574 frag_err:
 575         for (; ii > 0; ii--) {
 576                 if (priv->tx_bd_tail)
 577                         priv->tx_bd_tail--;
 578                 else
 579                         priv->tx_bd_tail = TX_BD_NUM - 1;
 580
 581                 tx_skb = &priv->tx_skb[priv->tx_bd_tail];
 582                 nixge_tx_skb_unmap(priv, tx_skb);
 583
 584                 cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
 585                 cur_p->status = 0;
 586         }
 587         dma_unmap_single(priv->ndev->dev.parent,
 588                          tx_skb->mapping,
 589                          tx_skb->size, DMA_TO_DEVICE);
 590 drop:
 591         ndev->stats.tx_dropped++;
 592         return NETDEV_TX_OK;
 593 }
 594
 595 static int nixge_recv(struct net_device *ndev, int budget)
 596 {
 597         struct nixge_priv *priv = netdev_priv(ndev);
 598         struct sk_buff *skb, *new_skb;
 599         struct nixge_hw_dma_bd *cur_p;
 600         dma_addr_t tail_p = 0, cur_phys = 0;
 601         u32 packets = 0;
 602         u32 length = 0;
 603         u32 size = 0;
 604
 605         cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 606
 607         while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK &&
 608                 budget > packets)) {
 609                 tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
 610                          priv->rx_bd_ci;
 611
 612                 skb = (struct sk_buff *)(uintptr_t)
 613                         nixge_hw_dma_bd_get_addr(cur_p, sw_id_offset);
 614
 615                 length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 616                 if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
 617                         length = NIXGE_MAX_JUMBO_FRAME_SIZE;
 618
 619                 dma_unmap_single(ndev->dev.parent,
 620                                  nixge_hw_dma_bd_get_addr(cur_p, phys),
 621                                  NIXGE_MAX_JUMBO_FRAME_SIZE,
 622                                  DMA_FROM_DEVICE);
 623
 624                 skb_put(skb, length);
 625
 626                 skb->protocol = eth_type_trans(skb, ndev);
 627                 skb_checksum_none_assert(skb);
 628
 629                 /* For now mark them as CHECKSUM_NONE since
 630                  * we don't have offload capabilities
 631                  */
 632                 skb->ip_summed = CHECKSUM_NONE;
 633
 634                 napi_gro_receive(&priv->napi, skb);
 635
 636                 size += length;
 637                 packets++;
 638
 639                 new_skb = netdev_alloc_skb_ip_align(ndev,
 640                                                     NIXGE_MAX_JUMBO_FRAME_SIZE);
 641                 if (!new_skb)
 642                         return packets;
 643
 644                 cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
 645                                           NIXGE_MAX_JUMBO_FRAME_SIZE,
 646                                           DMA_FROM_DEVICE);
 647                 if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
 648                         /* FIXME: bail out and clean up */
 649                         netdev_err(ndev, "Failed to map ...\n");
 650                 }
 651                 nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
 652                 cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
 653                 cur_p->status = 0;
 654                 nixge_hw_dma_bd_set_offset(cur_p, (uintptr_t)new_skb);
 655
 656                 ++priv->rx_bd_ci;
 657                 priv->rx_bd_ci %= RX_BD_NUM;
 658                 cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
 659         }
 660
 661         ndev->stats.rx_packets += packets;
 662         ndev->stats.rx_bytes += size;
 663
 664         if (tail_p)
 665                 nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
 666
 667         return packets;
 668 }
 669
 670 static int nixge_poll(struct napi_struct *napi, int budget)
 671 {
 672         struct nixge_priv *priv = container_of(napi, struct nixge_priv, napi);
 673         int work_done;
 674         u32 status, cr;
 675
 676         work_done = 0;
 677
 678         work_done = nixge_recv(priv->ndev, budget);
 679         if (work_done < budget) {
 680                 napi_complete_done(napi, work_done);
 681                 status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 682
 683                 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 684                         /* If there's more, reschedule, but clear */
 685                         nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 686                         napi_reschedule(napi);
 687                 } else {
 688                         /* if not, turn on RX IRQs again ... */
 689                         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 690                         cr |= (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 691                         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 692                 }
 693         }
 694
 695         return work_done;
 696 }
 697
 698 static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
 699 {
 700         struct nixge_priv *priv = netdev_priv(_ndev);
 701         struct net_device *ndev = _ndev;
 702         unsigned int status;
 703         dma_addr_t phys;
 704         u32 cr;
 705
 706         status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
 707         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 708                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 709                 nixge_start_xmit_done(priv->ndev);
 710                 goto out;
 711         }
 712         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 713                 netdev_err(ndev, "No interrupts asserted in Tx path\n");
 714                 return IRQ_NONE;
 715         }
 716         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 717                 phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
 718                                                 phys);
 719
 720                 netdev_err(ndev, "DMA Tx error 0x%x\n", status);
 721                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 722
 723                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 724                 /* Disable coalesce, delay timer and error interrupts */
 725                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 726                 /* Write to the Tx channel control register */
 727                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 728
 729                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 730                 /* Disable coalesce, delay timer and error interrupts */
 731                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 732                 /* Write to the Rx channel control register */
 733                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 734
 735                 tasklet_schedule(&priv->dma_err_tasklet);
 736                 nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
 737         }
 738 out:
 739         return IRQ_HANDLED;
 740 }
 741
 742 static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
 743 {
 744         struct nixge_priv *priv = netdev_priv(_ndev);
 745         struct net_device *ndev = _ndev;
 746         unsigned int status;
 747         dma_addr_t phys;
 748         u32 cr;
 749
 750         status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
 751         if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
 752                 /* Turn of IRQs because NAPI */
 753                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 754                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 755                 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
 756                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 757
 758                 if (napi_schedule_prep(&priv->napi))
 759                         __napi_schedule(&priv->napi);
 760                 goto out;
 761         }
 762         if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
 763                 netdev_err(ndev, "No interrupts asserted in Rx path\n");
 764                 return IRQ_NONE;
 765         }
 766         if (status & XAXIDMA_IRQ_ERROR_MASK) {
 767                 phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
 768                                                 phys);
 769                 netdev_err(ndev, "DMA Rx error 0x%x\n", status);
 770                 netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
 771
 772                 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 773                 /* Disable coalesce, delay timer and error interrupts */
 774                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 775                 /* Finally write to the Tx channel control register */
 776                 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
 777
 778                 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 779                 /* Disable coalesce, delay timer and error interrupts */
 780                 cr &= (~XAXIDMA_IRQ_ALL_MASK);
 781                 /* write to the Rx channel control register */
 782                 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
 783
 784                 tasklet_schedule(&priv->dma_err_tasklet);
 785                 nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
 786         }
 787 out:
 788         return IRQ_HANDLED;
 789 }
 790
 791 static void nixge_dma_err_handler(struct tasklet_struct *t)
 792 {
 793         struct nixge_priv *lp = from_tasklet(lp, t, dma_err_tasklet);
 794         struct nixge_hw_dma_bd *cur_p;
 795         struct nixge_tx_skb *tx_skb;
 796         u32 cr, i;
 797
 798         __nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
 799         __nixge_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
 800
 801         for (i = 0; i < TX_BD_NUM; i++) {
 802                 cur_p = &lp->tx_bd_v[i];
 803                 tx_skb = &lp->tx_skb[i];
 804                 nixge_tx_skb_unmap(lp, tx_skb);
 805
 806                 nixge_hw_dma_bd_set_phys(cur_p, 0);
 807                 cur_p->cntrl = 0;
 808                 cur_p->status = 0;
 809                 nixge_hw_dma_bd_set_offset(cur_p, 0);
 810         }
 811
 812         for (i = 0; i < RX_BD_NUM; i++) {
 813                 cur_p = &lp->rx_bd_v[i];
 814                 cur_p->status = 0;
 815         }
 816
 817         lp->tx_bd_ci = 0;
 818         lp->tx_bd_tail = 0;
 819         lp->rx_bd_ci = 0;
 820
 821         /* Start updating the Rx channel control register */
 822         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 823         /* Update the interrupt coalesce count */
 824         cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
 825               (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 826         /* Update the delay timer count */
 827         cr = ((cr & ~XAXIDMA_DELAY_MASK) |
 828               (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 829         /* Enable coalesce, delay timer and error interrupts */
 830         cr |= XAXIDMA_IRQ_ALL_MASK;
 831         /* Finally write to the Rx channel control register */
 832         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);
 833
 834         /* Start updating the Tx channel control register */
 835         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 836         /* Update the interrupt coalesce count */
 837         cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
 838               (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
 839         /* Update the delay timer count */
 840         cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
 841               (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
 842         /* Enable coalesce, delay timer and error interrupts */
 843         cr |= XAXIDMA_IRQ_ALL_MASK;
 844         /* Finally write to the Tx channel control register */
 845         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);
 846
 847         /* Populate the tail pointer and bring the Rx Axi DMA engine out of
 848          * halted state. This will make the Rx side ready for reception.
 849          */
 850         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
 851         cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
 852         nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
 853                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 854         nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
 855                             (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
 856
 857         /* Write to the RS (Run-stop) bit in the Tx channel control register.
 858          * Tx channel is now ready to run. But only after we write to the
 859          * tail pointer register that the Tx channel will start transmitting
 860          */
 861         nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
 862         cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
 863         nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
 864                             cr | XAXIDMA_CR_RUNSTOP_MASK);
 865 }
 866
 867 static int nixge_open(struct net_device *ndev)
 868 {
 869         struct nixge_priv *priv = netdev_priv(ndev);
 870         struct phy_device *phy;
 871         int ret;
 872
 873         nixge_device_reset(ndev);
 874
 875         phy = of_phy_connect(ndev, priv->phy_node,
 876                              &nixge_handle_link_change, 0, priv->phy_mode);
 877         if (!phy)
 878                 return -ENODEV;
 879
 880         phy_start(phy);
 881
 882         /* Enable tasklets for Axi DMA error handling */
 883         tasklet_setup(&priv->dma_err_tasklet, nixge_dma_err_handler);
 884
 885         napi_enable(&priv->napi);
 886
 887         /* Enable interrupts for Axi DMA Tx */
 888         ret = request_irq(priv->tx_irq, nixge_tx_irq, 0, ndev->name, ndev);
 889         if (ret)
 890                 goto err_tx_irq;
 891         /* Enable interrupts for Axi DMA Rx */
 892         ret = request_irq(priv->rx_irq, nixge_rx_irq, 0, ndev->name, ndev);
 893         if (ret)
 894                 goto err_rx_irq;
 895
 896         netif_start_queue(ndev);
 897
 898         return 0;
 899
 900 err_rx_irq:
 901         free_irq(priv->tx_irq, ndev);
 902 err_tx_irq:
 903         napi_disable(&priv->napi);
 904         phy_stop(phy);
 905         phy_disconnect(phy);
 906         tasklet_kill(&priv->dma_err_tasklet);
 907         netdev_err(ndev, "request_irq() failed\n");
 908         return ret;
 909 }
 910
 911 static int nixge_stop(struct net_device *ndev)
 912 {
 913         struct nixge_priv *priv = netdev_priv(ndev);
 914         u32 cr;
 915
 916         netif_stop_queue(ndev);
 917         napi_disable(&priv->napi);
 918
 919         if (ndev->phydev) {
 920                 phy_stop(ndev->phydev);
 921                 phy_disconnect(ndev->phydev);
 922         }
 923
 924         cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
 925         nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
 926                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 927         cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
 928         nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
 929                             cr & (~XAXIDMA_CR_RUNSTOP_MASK));
 930
 931         tasklet_kill(&priv->dma_err_tasklet);
 932
 933         free_irq(priv->tx_irq, ndev);
 934         free_irq(priv->rx_irq, ndev);
 935
 936         nixge_hw_dma_bd_release(ndev);
 937
 938         return 0;
 939 }
 940
 941 static int nixge_change_mtu(struct net_device *ndev, int new_mtu)
 942 {
 943         if (netif_running(ndev))
 944                 return -EBUSY;
 945
 946         if ((new_mtu + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE) >
 947              NIXGE_MAX_JUMBO_FRAME_SIZE)
 948                 return -EINVAL;
 949
 950         ndev->mtu = new_mtu;
 951
 952         return 0;
 953 }
 954
 955 static s32 __nixge_hw_set_mac_address(struct net_device *ndev)
 956 {
 957         struct nixge_priv *priv = netdev_priv(ndev);
 958
 959         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
 960                              (ndev->dev_addr[2]) << 24 |
 961                              (ndev->dev_addr[3] << 16) |
 962                              (ndev->dev_addr[4] << 8) |
 963                              (ndev->dev_addr[5] << 0));
 964
 965         nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
 966                              (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
 967
 968         return 0;
 969 }
 970
 971 static int nixge_net_set_mac_address(struct net_device *ndev, void *p)
 972 {
 973         int err;
 974
 975         err = eth_mac_addr(ndev, p);
 976         if (!err)
 977                 __nixge_hw_set_mac_address(ndev);
 978
 979         return err;
 980 }
 981
 982 static const struct net_device_ops nixge_netdev_ops = {
 983         .ndo_open = nixge_open,
 984         .ndo_stop = nixge_stop,
 985         .ndo_start_xmit = nixge_start_xmit,
 986         .ndo_change_mtu = nixge_change_mtu,
 987         .ndo_set_mac_address = nixge_net_set_mac_address,
 988         .ndo_validate_addr = eth_validate_addr,
 989 };
 990
 991 static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
 992                                        struct ethtool_drvinfo *ed)
 993 {
 994         strscpy(ed->driver, "nixge", sizeof(ed->driver));
 995         strscpy(ed->bus_info, "platform", sizeof(ed->bus_info));
 996 }
 997
 998 static int
 999 nixge_ethtools_get_coalesce(struct net_device *ndev,
1000                             struct ethtool_coalesce *ecoalesce,
1001                             struct kernel_ethtool_coalesce *kernel_coal,
1002                             struct netlink_ext_ack *extack)
1003 {
1004         struct nixge_priv *priv = netdev_priv(ndev);
1005         u32 regval = 0;
1006
1007         regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
1008         ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1009                                              >> XAXIDMA_COALESCE_SHIFT;
1010         regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
1011         ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1012                                              >> XAXIDMA_COALESCE_SHIFT;
1013         return 0;
1014 }
1015
1016 static int
1017 nixge_ethtools_set_coalesce(struct net_device *ndev,
1018                             struct ethtool_coalesce *ecoalesce,
1019                             struct kernel_ethtool_coalesce *kernel_coal,
1020                             struct netlink_ext_ack *extack)
1021 {
1022         struct nixge_priv *priv = netdev_priv(ndev);
1023
1024         if (netif_running(ndev)) {
1025                 netdev_err(ndev,
1026                            "Please stop netif before applying configuration\n");
1027                 return -EBUSY;
1028         }
1029
1030         if (ecoalesce->rx_max_coalesced_frames)
1031                 priv->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1032         if (ecoalesce->tx_max_coalesced_frames)
1033                 priv->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1034
1035         return 0;
1036 }
1037
1038 static int nixge_ethtools_set_phys_id(struct net_device *ndev,
1039                                       enum ethtool_phys_id_state state)
1040 {
1041         struct nixge_priv *priv = netdev_priv(ndev);
1042         u32 ctrl;
1043
1044         ctrl = nixge_ctrl_read_reg(priv, NIXGE_REG_LED_CTL);
1045         switch (state) {
1046         case ETHTOOL_ID_ACTIVE:
1047                 ctrl |= NIXGE_ID_LED_CTL_EN;
1048                 /* Enable identification LED override*/
1049                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1050                 return 2;
1051
1052         case ETHTOOL_ID_ON:
1053                 ctrl |= NIXGE_ID_LED_CTL_VAL;
1054                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1055                 break;
1056
1057         case ETHTOOL_ID_OFF:
1058                 ctrl &= ~NIXGE_ID_LED_CTL_VAL;
1059                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1060                 break;
1061
1062         case ETHTOOL_ID_INACTIVE:
1063                 /* Restore LED settings */
1064                 ctrl &= ~NIXGE_ID_LED_CTL_EN;
1065                 nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1066                 break;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static const struct ethtool_ops nixge_ethtool_ops = {
1073         .supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES,
1074         .get_drvinfo    = nixge_ethtools_get_drvinfo,
1075         .get_coalesce   = nixge_ethtools_get_coalesce,
1076         .set_coalesce   = nixge_ethtools_set_coalesce,
1077         .set_phys_id    = nixge_ethtools_set_phys_id,
1078         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1079         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1080         .get_link               = ethtool_op_get_link,
1081 };
1082
1083 static int nixge_mdio_read_c22(struct mii_bus *bus, int phy_id, int reg)
1084 {
1085         struct nixge_priv *priv = bus->priv;
1086         u32 status, tmp;
1087         int err;
1088         u16 device;
1089
1090         device = reg & 0x1f;
1091
1092         tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
1093               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1094
1095         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1096         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1097
1098         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1099                                       !status, 10, 1000);
1100         if (err) {
1101                 dev_err(priv->dev, "timeout setting read command");
1102                 return err;
1103         }
1104
1105         status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1106
1107         return status;
1108 }
1109
1110 static int nixge_mdio_read_c45(struct mii_bus *bus, int phy_id, int device,
1111                                int reg)
1112 {
1113         struct nixge_priv *priv = bus->priv;
1114         u32 status, tmp;
1115         int err;
1116
1117         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1118
1119         tmp = NIXGE_MDIO_CLAUSE45 |
1120               NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
1121               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1122
1123         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1124         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1125
1126         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1127                                       !status, 10, 1000);
1128         if (err) {
1129                 dev_err(priv->dev, "timeout setting address");
1130                 return err;
1131         }
1132
1133         tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
1134               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1135
1136         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1137         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1138
1139         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1140                                       !status, 10, 1000);
1141         if (err) {
1142                 dev_err(priv->dev, "timeout setting read command");
1143                 return err;
1144         }
1145
1146         status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1147
1148         return status;
1149 }
1150
1151 static int nixge_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg,
1152                                 u16 val)
1153 {
1154         struct nixge_priv *priv = bus->priv;
1155         u32 status, tmp;
1156         u16 device;
1157         int err;
1158
1159         device = reg & 0x1f;
1160
1161         tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
1162               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1163
1164         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1165         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1166         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1167
1168         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1169                                       !status, 10, 1000);
1170         if (err)
1171                 dev_err(priv->dev, "timeout setting write command");
1172
1173         return err;
1174 }
1175
1176 static int nixge_mdio_write_c45(struct mii_bus *bus, int phy_id,
1177                                 int device, int reg, u16 val)
1178 {
1179         struct nixge_priv *priv = bus->priv;
1180         u32 status, tmp;
1181         int err;
1182
1183         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1184
1185         tmp = NIXGE_MDIO_CLAUSE45 |
1186               NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
1187               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1188
1189         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1190         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1191
1192         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1193                                       !status, 10, 1000);
1194         if (err) {
1195                 dev_err(priv->dev, "timeout setting address");
1196                 return err;
1197         }
1198
1199         tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) |
1200               NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1201
1202         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1203         nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1204
1205         err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1206                                       !status, 10, 1000);
1207         if (err)
1208                 dev_err(priv->dev, "timeout setting write command");
1209
1210         return err;
1211 }
1212
1213 static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
1214 {
1215         struct mii_bus *bus;
1216
1217         bus = devm_mdiobus_alloc(priv->dev);
1218         if (!bus)
1219                 return -ENOMEM;
1220
1221         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
1222         bus->priv = priv;
1223         bus->name = "nixge_mii_bus";
1224         bus->read = nixge_mdio_read_c22;
1225         bus->write = nixge_mdio_write_c22;
1226         bus->read_c45 = nixge_mdio_read_c45;
1227         bus->write_c45 = nixge_mdio_write_c45;
1228         bus->parent = priv->dev;
1229
1230         priv->mii_bus = bus;
1231
1232         return of_mdiobus_register(bus, np);
1233 }
1234
1235 static void *nixge_get_nvmem_address(struct device *dev)
1236 {
1237         struct nvmem_cell *cell;
1238         size_t cell_size;
1239         char *mac;
1240
1241         cell = nvmem_cell_get(dev, "address");
1242         if (IS_ERR(cell))
1243                 return cell;
1244
1245         mac = nvmem_cell_read(cell, &cell_size);
1246         nvmem_cell_put(cell);
1247
1248         return mac;
1249 }
1250
1251 /* Match table for of_platform binding */
1252 static const struct of_device_id nixge_dt_ids[] = {
1253         { .compatible = "ni,xge-enet-2.00", .data = (void *)NIXGE_V2 },
1254         { .compatible = "ni,xge-enet-3.00", .data = (void *)NIXGE_V3 },
1255         {},
1256 };
1257 MODULE_DEVICE_TABLE(of, nixge_dt_ids);
1258
1259 static int nixge_of_get_resources(struct platform_device *pdev)
1260 {
1261         const struct of_device_id *of_id;
1262         enum nixge_version version;
1263         struct net_device *ndev;
1264         struct nixge_priv *priv;
1265
1266         ndev = platform_get_drvdata(pdev);
1267         priv = netdev_priv(ndev);
1268         of_id = of_match_node(nixge_dt_ids, pdev->dev.of_node);
1269         if (!of_id)
1270                 return -ENODEV;
1271
1272         version = (enum nixge_version)of_id->data;
1273         if (version <= NIXGE_V2)
1274                 priv->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1275         else
1276                 priv->dma_regs = devm_platform_ioremap_resource_byname(pdev, "dma");
1277         if (IS_ERR(priv->dma_regs)) {
1278                 netdev_err(ndev, "failed to map dma regs\n");
1279                 return PTR_ERR(priv->dma_regs);
1280         }
1281         if (version <= NIXGE_V2)
1282                 priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1283         else
1284                 priv->ctrl_regs = devm_platform_ioremap_resource_byname(pdev, "ctrl");
1285         if (IS_ERR(priv->ctrl_regs)) {
1286                 netdev_err(ndev, "failed to map ctrl regs\n");
1287                 return PTR_ERR(priv->ctrl_regs);
1288         }
1289         return 0;
1290 }
1291
1292 static int nixge_probe(struct platform_device *pdev)
1293 {
1294         struct device_node *mn, *phy_node;
1295         struct nixge_priv *priv;
1296         struct net_device *ndev;
1297         const u8 *mac_addr;
1298         int err;
1299
1300         ndev = alloc_etherdev(sizeof(*priv));
1301         if (!ndev)
1302                 return -ENOMEM;
1303
1304         platform_set_drvdata(pdev, ndev);
1305         SET_NETDEV_DEV(ndev, &pdev->dev);
1306
1307         ndev->features = NETIF_F_SG;
1308         ndev->netdev_ops = &nixge_netdev_ops;
1309         ndev->ethtool_ops = &nixge_ethtool_ops;
1310
1311         /* MTU range: 64 - 9000 */
1312         ndev->min_mtu = 64;
1313         ndev->max_mtu = NIXGE_JUMBO_MTU;
1314
1315         mac_addr = nixge_get_nvmem_address(&pdev->dev);
1316         if (!IS_ERR(mac_addr) && is_valid_ether_addr(mac_addr)) {
1317                 eth_hw_addr_set(ndev, mac_addr);
1318                 kfree(mac_addr);
1319         } else {
1320                 eth_hw_addr_random(ndev);
1321         }
1322
1323         priv = netdev_priv(ndev);
1324         priv->ndev = ndev;
1325         priv->dev = &pdev->dev;
1326
1327         netif_napi_add(ndev, &priv->napi, nixge_poll);
1328         err = nixge_of_get_resources(pdev);
1329         if (err)
1330                 goto free_netdev;
1331         __nixge_hw_set_mac_address(ndev);
1332
1333         priv->tx_irq = platform_get_irq_byname(pdev, "tx");
1334         if (priv->tx_irq < 0) {
1335                 netdev_err(ndev, "could not find 'tx' irq");
1336                 err = priv->tx_irq;
1337                 goto free_netdev;
1338         }
1339
1340         priv->rx_irq = platform_get_irq_byname(pdev, "rx");
1341         if (priv->rx_irq < 0) {
1342                 netdev_err(ndev, "could not find 'rx' irq");
1343                 err = priv->rx_irq;
1344                 goto free_netdev;
1345         }
1346
1347         priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1348         priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1349
1350         mn = of_get_child_by_name(pdev->dev.of_node, "mdio");
1351         if (mn) {
1352                 err = nixge_mdio_setup(priv, mn);
1353                 of_node_put(mn);
1354                 if (err) {
1355                         netdev_err(ndev, "error registering mdio bus");
1356                         goto free_netdev;
1357                 }
1358         }
1359
1360         err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
1361         if (err) {
1362                 netdev_err(ndev, "not find \"phy-mode\" property\n");
1363                 goto unregister_mdio;
1364         }
1365
1366         phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1367         if (!phy_node && of_phy_is_fixed_link(pdev->dev.of_node)) {
1368                 err = of_phy_register_fixed_link(pdev->dev.of_node);
1369                 if (err < 0) {
1370                         netdev_err(ndev, "broken fixed-link specification\n");
1371                         goto unregister_mdio;
1372                 }
1373                 phy_node = of_node_get(pdev->dev.of_node);
1374         }
1375         priv->phy_node = phy_node;
1376
1377         err = register_netdev(priv->ndev);
1378         if (err) {
1379                 netdev_err(ndev, "register_netdev() error (%i)\n", err);
1380                 goto free_phy;
1381         }
1382
1383         return 0;
1384
1385 free_phy:
1386         if (of_phy_is_fixed_link(pdev->dev.of_node))
1387                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1388         of_node_put(phy_node);
1389
1390 unregister_mdio:
1391         if (priv->mii_bus)
1392                 mdiobus_unregister(priv->mii_bus);
1393
1394 free_netdev:
1395         free_netdev(ndev);
1396
1397         return err;
1398 }
1399
1400 static int nixge_remove(struct platform_device *pdev)
1401 {
1402         struct net_device *ndev = platform_get_drvdata(pdev);
1403         struct nixge_priv *priv = netdev_priv(ndev);
1404
1405         unregister_netdev(ndev);
1406
1407         if (of_phy_is_fixed_link(pdev->dev.of_node))
1408                 of_phy_deregister_fixed_link(pdev->dev.of_node);
1409         of_node_put(priv->phy_node);
1410
1411         if (priv->mii_bus)
1412                 mdiobus_unregister(priv->mii_bus);
1413
1414         free_netdev(ndev);
1415
1416         return 0;
1417 }
1418
1419 static struct platform_driver nixge_driver = {
1420         .probe          = nixge_probe,
1421         .remove         = nixge_remove,
1422         .driver         = {
1423                 .name           = "nixge",
1424                 .of_match_table = nixge_dt_ids,
1425         },
1426 };
1427 module_platform_driver(nixge_driver);
1428
1429 MODULE_LICENSE("GPL v2");
1430 MODULE_DESCRIPTION("National Instruments XGE Management MAC");
1431 MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");