net: mscc: describe the PTP register range
[platform/kernel/linux-starfive.git] / drivers / net / ethernet / mscc / ocelot_ptp.h
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /*
3  * Microsemi Ocelot Switch driver
4  *
5  * License: Dual MIT/GPL
6  * Copyright (c) 2017 Microsemi Corporation
7  */
8
9 #ifndef _MSCC_OCELOT_PTP_H_
10 #define _MSCC_OCELOT_PTP_H_
11
12 #define PTP_PIN_CFG_RSZ                 0x20
13 #define PTP_PIN_TOD_SEC_MSB_RSZ         PTP_PIN_CFG_RSZ
14 #define PTP_PIN_TOD_SEC_LSB_RSZ         PTP_PIN_CFG_RSZ
15 #define PTP_PIN_TOD_NSEC_RSZ            PTP_PIN_CFG_RSZ
16
17 #define PTP_PIN_CFG_DOM                 BIT(0)
18 #define PTP_PIN_CFG_SYNC                BIT(2)
19 #define PTP_PIN_CFG_ACTION(x)           ((x) << 3)
20 #define PTP_PIN_CFG_ACTION_MASK         PTP_PIN_CFG_ACTION(0x7)
21
22 enum {
23         PTP_PIN_ACTION_IDLE = 0,
24         PTP_PIN_ACTION_LOAD,
25         PTP_PIN_ACTION_SAVE,
26         PTP_PIN_ACTION_CLOCK,
27         PTP_PIN_ACTION_DELTA,
28         PTP_PIN_ACTION_NOSYNC,
29         PTP_PIN_ACTION_SYNC,
30 };
31
32 #define PTP_CFG_MISC_PTP_EN             BIT(2)
33
34 #define PSEC_PER_SEC                    1000000000000LL
35
36 #define PTP_CFG_CLK_ADJ_CFG_ENA         BIT(0)
37 #define PTP_CFG_CLK_ADJ_CFG_DIR         BIT(1)
38
39 #define PTP_CFG_CLK_ADJ_FREQ_NS         BIT(30)
40
41 #endif