drivers/net/ethernet/mscc/ocelot_board.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7 #include <linux/interrupt.h>
   8 #include <linux/module.h>
   9 #include <linux/of_net.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/of_mdio.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/skbuff.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ocelot.h"
  18
  19 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
  20
  21 static int ocelot_parse_ifh(u32 *_ifh, struct frame_info *info)
  22 {
  23         u8 llen, wlen;
  24         u64 ifh[2];
  25
  26         ifh[0] = be64_to_cpu(((__force __be64 *)_ifh)[0]);
  27         ifh[1] = be64_to_cpu(((__force __be64 *)_ifh)[1]);
  28
  29         wlen = IFH_EXTRACT_BITFIELD64(ifh[0], 7,  8);
  30         llen = IFH_EXTRACT_BITFIELD64(ifh[0], 15,  6);
  31
  32         info->len = OCELOT_BUFFER_CELL_SZ * wlen + llen - 80;
  33
  34         info->port = IFH_EXTRACT_BITFIELD64(ifh[1], 43, 4);
  35
  36         info->tag_type = IFH_EXTRACT_BITFIELD64(ifh[1], 16,  1);
  37         info->vid = IFH_EXTRACT_BITFIELD64(ifh[1], 0,  12);
  38
  39         return 0;
  40 }
  41
  42 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
  43                                 u32 *rval)
  44 {
  45         u32 val;
  46         u32 bytes_valid;
  47
  48         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  49         if (val == XTR_NOT_READY) {
  50                 if (ifh)
  51                         return -EIO;
  52
  53                 do {
  54                         val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  55                 } while (val == XTR_NOT_READY);
  56         }
  57
  58         switch (val) {
  59         case XTR_ABORT:
  60                 return -EIO;
  61         case XTR_EOF_0:
  62         case XTR_EOF_1:
  63         case XTR_EOF_2:
  64         case XTR_EOF_3:
  65         case XTR_PRUNED:
  66                 bytes_valid = XTR_VALID_BYTES(val);
  67                 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  68                 if (val == XTR_ESCAPE)
  69                         *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  70                 else
  71                         *rval = val;
  72
  73                 return bytes_valid;
  74         case XTR_ESCAPE:
  75                 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
  76
  77                 return 4;
  78         default:
  79                 *rval = val;
  80
  81                 return 4;
  82         }
  83 }
  84
  85 static irqreturn_t ocelot_xtr_irq_handler(int irq, void *arg)
  86 {
  87         struct ocelot *ocelot = arg;
  88         int i = 0, grp = 0;
  89         int err = 0;
  90
  91         if (!(ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)))
  92                 return IRQ_NONE;
  93
  94         do {
  95                 struct sk_buff *skb;
  96                 struct net_device *dev;
  97                 u32 *buf;
  98                 int sz, len, buf_len;
  99                 u32 ifh[4];
 100                 u32 val;
 101                 struct frame_info info;
 102
 103                 for (i = 0; i < IFH_LEN; i++) {
 104                         err = ocelot_rx_frame_word(ocelot, grp, true, &ifh[i]);
 105                         if (err != 4)
 106                                 break;
 107                 }
 108
 109                 if (err != 4)
 110                         break;
 111
 112                 ocelot_parse_ifh(ifh, &info);
 113
 114                 dev = ocelot->ports[info.port]->dev;
 115
 116                 skb = netdev_alloc_skb(dev, info.len);
 117
 118                 if (unlikely(!skb)) {
 119                         netdev_err(dev, "Unable to allocate sk_buff\n");
 120                         err = -ENOMEM;
 121                         break;
 122                 }
 123                 buf_len = info.len - ETH_FCS_LEN;
 124                 buf = (u32 *)skb_put(skb, buf_len);
 125
 126                 len = 0;
 127                 do {
 128                         sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 129                         *buf++ = val;
 130                         len += sz;
 131                 } while (len < buf_len);
 132
 133                 /* Read the FCS */
 134                 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
 135                 /* Update the statistics if part of the FCS was read before */
 136                 len -= ETH_FCS_LEN - sz;
 137
 138                 if (unlikely(dev->features & NETIF_F_RXFCS)) {
 139                         buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
 140                         *buf = val;
 141                 }
 142
 143                 if (sz < 0) {
 144                         err = sz;
 145                         break;
 146                 }
 147
 148                 /* Everything we see on an interface that is in the HW bridge
 149                  * has already been forwarded.
 150                  */
 151                 if (ocelot->bridge_mask & BIT(info.port))
 152                         skb->offload_fwd_mark = 1;
 153
 154                 skb->protocol = eth_type_trans(skb, dev);
 155                 netif_rx(skb);
 156                 dev->stats.rx_bytes += len;
 157                 dev->stats.rx_packets++;
 158         } while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp));
 159
 160         if (err)
 161                 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
 162                         ocelot_read_rix(ocelot, QS_XTR_RD, grp);
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 static const struct of_device_id mscc_ocelot_match[] = {
 168         { .compatible = "mscc,vsc7514-switch" },
 169         { }
 170 };
 171 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
 172
 173 static int mscc_ocelot_probe(struct platform_device *pdev)
 174 {
 175         int err, irq;
 176         unsigned int i;
 177         struct device_node *np = pdev->dev.of_node;
 178         struct device_node *ports, *portnp;
 179         struct ocelot *ocelot;
 180         struct regmap *hsio;
 181         u32 val;
 182
 183         struct {
 184                 enum ocelot_target id;
 185                 char *name;
 186                 u8 optional:1;
 187         } res[] = {
 188                 { SYS, "sys" },
 189                 { REW, "rew" },
 190                 { QSYS, "qsys" },
 191                 { ANA, "ana" },
 192                 { QS, "qs" },
 193                 { S2, "s2" },
 194                 { PTP, "ptp", 1 },
 195         };
 196
 197         if (!np && !pdev->dev.platform_data)
 198                 return -ENODEV;
 199
 200         ocelot = devm_kzalloc(&pdev->dev, sizeof(*ocelot), GFP_KERNEL);
 201         if (!ocelot)
 202                 return -ENOMEM;
 203
 204         platform_set_drvdata(pdev, ocelot);
 205         ocelot->dev = &pdev->dev;
 206
 207         for (i = 0; i < ARRAY_SIZE(res); i++) {
 208                 struct regmap *target;
 209
 210                 target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
 211                 if (IS_ERR(target)) {
 212                         if (res[i].optional) {
 213                                 ocelot->targets[res[i].id] = NULL;
 214                                 continue;
 215                         }
 216
 217                         return PTR_ERR(target);
 218                 }
 219
 220                 ocelot->targets[res[i].id] = target;
 221         }
 222
 223         hsio = syscon_regmap_lookup_by_compatible("mscc,ocelot-hsio");
 224         if (IS_ERR(hsio)) {
 225                 dev_err(&pdev->dev, "missing hsio syscon\n");
 226                 return PTR_ERR(hsio);
 227         }
 228
 229         ocelot->targets[HSIO] = hsio;
 230
 231         err = ocelot_chip_init(ocelot);
 232         if (err)
 233                 return err;
 234
 235         irq = platform_get_irq_byname(pdev, "xtr");
 236         if (irq < 0)
 237                 return -ENODEV;
 238
 239         err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 240                                         ocelot_xtr_irq_handler, IRQF_ONESHOT,
 241                                         "frame extraction", ocelot);
 242         if (err)
 243                 return err;
 244
 245         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
 246         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 247
 248         do {
 249                 msleep(1);
 250                 regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
 251                                   &val);
 252         } while (val);
 253
 254         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
 255         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
 256
 257         ocelot->num_cpu_ports = 1; /* 1 port on the switch, two groups */
 258
 259         ports = of_get_child_by_name(np, "ethernet-ports");
 260         if (!ports) {
 261                 dev_err(&pdev->dev, "no ethernet-ports child node found\n");
 262                 return -ENODEV;
 263         }
 264
 265         ocelot->num_phys_ports = of_get_child_count(ports);
 266
 267         ocelot->ports = devm_kcalloc(&pdev->dev, ocelot->num_phys_ports,
 268                                      sizeof(struct ocelot_port *), GFP_KERNEL);
 269
 270         INIT_LIST_HEAD(&ocelot->multicast);
 271         ocelot_init(ocelot);
 272
 273         for_each_available_child_of_node(ports, portnp) {
 274                 struct device_node *phy_node;
 275                 struct phy_device *phy;
 276                 struct resource *res;
 277                 struct phy *serdes;
 278                 void __iomem *regs;
 279                 char res_name[8];
 280                 int phy_mode;
 281                 u32 port;
 282
 283                 if (of_property_read_u32(portnp, "reg", &port))
 284                         continue;
 285
 286                 snprintf(res_name, sizeof(res_name), "port%d", port);
 287
 288                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 289                                                    res_name);
 290                 regs = devm_ioremap_resource(&pdev->dev, res);
 291                 if (IS_ERR(regs))
 292                         continue;
 293
 294                 phy_node = of_parse_phandle(portnp, "phy-handle", 0);
 295                 if (!phy_node)
 296                         continue;
 297
 298                 phy = of_phy_find_device(phy_node);
 299                 if (!phy)
 300                         continue;
 301
 302                 err = ocelot_probe_port(ocelot, port, regs, phy);
 303                 if (err) {
 304                         of_node_put(portnp);
 305                         return err;
 306                 }
 307
 308                 phy_mode = of_get_phy_mode(portnp);
 309                 if (phy_mode < 0)
 310                         ocelot->ports[port]->phy_mode = PHY_INTERFACE_MODE_NA;
 311                 else
 312                         ocelot->ports[port]->phy_mode = phy_mode;
 313
 314                 switch (ocelot->ports[port]->phy_mode) {
 315                 case PHY_INTERFACE_MODE_NA:
 316                         continue;
 317                 case PHY_INTERFACE_MODE_SGMII:
 318                         break;
 319                 case PHY_INTERFACE_MODE_QSGMII:
 320                         /* Ensure clock signals and speed is set on all
 321                          * QSGMII links
 322                          */
 323                         ocelot_port_writel(ocelot->ports[port],
 324                                            DEV_CLOCK_CFG_LINK_SPEED
 325                                            (OCELOT_SPEED_1000),
 326                                            DEV_CLOCK_CFG);
 327                         break;
 328                 default:
 329                         dev_err(ocelot->dev,
 330                                 "invalid phy mode for port%d, (Q)SGMII only\n",
 331                                 port);
 332                         of_node_put(portnp);
 333                         return -EINVAL;
 334                 }
 335
 336                 serdes = devm_of_phy_get(ocelot->dev, portnp, NULL);
 337                 if (IS_ERR(serdes)) {
 338                         err = PTR_ERR(serdes);
 339                         if (err == -EPROBE_DEFER)
 340                                 dev_dbg(ocelot->dev, "deferring probe\n");
 341                         else
 342                                 dev_err(ocelot->dev,
 343                                         "missing SerDes phys for port%d\n",
 344                                         port);
 345
 346                         goto err_probe_ports;
 347                 }
 348
 349                 ocelot->ports[port]->serdes = serdes;
 350         }
 351
 352         register_netdevice_notifier(&ocelot_netdevice_nb);
 353         register_switchdev_notifier(&ocelot_switchdev_nb);
 354         register_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 355
 356         dev_info(&pdev->dev, "Ocelot switch probed\n");
 357
 358         return 0;
 359
 360 err_probe_ports:
 361         return err;
 362 }
 363
 364 static int mscc_ocelot_remove(struct platform_device *pdev)
 365 {
 366         struct ocelot *ocelot = platform_get_drvdata(pdev);
 367
 368         ocelot_deinit(ocelot);
 369         unregister_switchdev_blocking_notifier(&ocelot_switchdev_blocking_nb);
 370         unregister_switchdev_notifier(&ocelot_switchdev_nb);
 371         unregister_netdevice_notifier(&ocelot_netdevice_nb);
 372
 373         return 0;
 374 }
 375
 376 static struct platform_driver mscc_ocelot_driver = {
 377         .probe = mscc_ocelot_probe,
 378         .remove = mscc_ocelot_remove,
 379         .driver = {
 380                 .name = "ocelot-switch",
 381                 .of_match_table = mscc_ocelot_match,
 382         },
 383 };
 384
 385 module_platform_driver(mscc_ocelot_driver);
 386
 387 MODULE_DESCRIPTION("Microsemi Ocelot switch driver");
 388 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
 389 MODULE_LICENSE("Dual MIT/GPL");