1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
8 #ifndef _MSCC_OCELOT_H_
9 #define _MSCC_OCELOT_H_
11 #include <linux/bitops.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/phy.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
19 #include "ocelot_ana.h"
20 #include "ocelot_dev.h"
21 #include "ocelot_qsys.h"
22 #include "ocelot_rew.h"
23 #include "ocelot_sys.h"
24 #include "ocelot_qs.h"
25 #include "ocelot_tc.h"
31 #define PGID_CPU (PGID_AGGR - 5)
32 #define PGID_UC (PGID_AGGR - 4)
33 #define PGID_MC (PGID_AGGR - 3)
34 #define PGID_MCIPV4 (PGID_AGGR - 2)
35 #define PGID_MCIPV6 (PGID_AGGR - 1)
37 #define OCELOT_BUFFER_CELL_SZ 60
39 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
51 #define IFH_INJ_BYPASS BIT(31)
52 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
54 #define IFH_TAG_TYPE_C 0
55 #define IFH_TAG_TYPE_S 1
57 #define OCELOT_SPEED_2500 0
58 #define OCELOT_SPEED_1000 1
59 #define OCELOT_SPEED_100 2
60 #define OCELOT_SPEED_10 3
62 #define TARGET_OFFSET 24
63 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
64 #define REG(reg, offset) [reg & REG_MASK] = offset
78 ANA_ADVLEARN = ANA << TARGET_OFFSET,
102 ANA_TABLES_STREAMDATA,
103 ANA_TABLES_MACACCESS,
105 ANA_TABLES_VLANACCESS,
107 ANA_TABLES_ISDXACCESS,
110 ANA_TABLES_PTP_ID_HIGH,
111 ANA_TABLES_PTP_ID_LOW,
112 ANA_TABLES_STREAMACCESS,
113 ANA_TABLES_STREAMTIDX,
114 ANA_TABLES_SEQ_HISTORY,
116 ANA_TABLES_SFID_MASK,
117 ANA_TABLES_SFIDACCESS,
127 ANA_SG_GCL_GS_CONFIG,
128 ANA_SG_GCL_TI_CONFIG,
136 ANA_PORT_VCAP_S1_KEY_CFG,
137 ANA_PORT_VCAP_S2_CFG,
138 ANA_PORT_PCP_DEI_MAP,
139 ANA_PORT_CPU_FWD_CFG,
140 ANA_PORT_CPU_FWD_BPDU_CFG,
141 ANA_PORT_CPU_FWD_GARP_CFG,
142 ANA_PORT_CPU_FWD_CCM_CFG,
146 ANA_PORT_PTP_DLY1_CFG,
147 ANA_PORT_PTP_DLY2_CFG,
161 ANA_VCAP_RNG_TYPE_CFG,
162 ANA_VCAP_RNG_VAL_CFG,
177 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
189 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
190 QSYS_SWITCH_PORT_MODE,
202 QSYS_TIMED_FRAME_ENTRY,
205 QSYS_TFRM_TIMER_CFG_1,
206 QSYS_TFRM_TIMER_CFG_2,
207 QSYS_TFRM_TIMER_CFG_3,
208 QSYS_TFRM_TIMER_CFG_4,
209 QSYS_TFRM_TIMER_CFG_5,
210 QSYS_TFRM_TIMER_CFG_6,
211 QSYS_TFRM_TIMER_CFG_7,
212 QSYS_TFRM_TIMER_CFG_8,
240 QSYS_TAS_PARAM_CFG_CTRL,
242 QSYS_PARAM_CFG_REG_1,
243 QSYS_PARAM_CFG_REG_2,
244 QSYS_PARAM_CFG_REG_3,
245 QSYS_PARAM_CFG_REG_4,
246 QSYS_PARAM_CFG_REG_5,
249 QSYS_PARAM_STATUS_REG_1,
250 QSYS_PARAM_STATUS_REG_2,
251 QSYS_PARAM_STATUS_REG_3,
252 QSYS_PARAM_STATUS_REG_4,
253 QSYS_PARAM_STATUS_REG_5,
254 QSYS_PARAM_STATUS_REG_6,
255 QSYS_PARAM_STATUS_REG_7,
256 QSYS_PARAM_STATUS_REG_8,
257 QSYS_PARAM_STATUS_REG_9,
258 QSYS_GCL_STATUS_REG_1,
259 QSYS_GCL_STATUS_REG_2,
260 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
264 REW_PCP_DEI_QOS_MAP_CFG,
268 REW_DSCP_REMAP_DP1_CFG,
273 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
274 SYS_COUNT_RX_UNICAST,
275 SYS_COUNT_RX_MULTICAST,
276 SYS_COUNT_RX_BROADCAST,
278 SYS_COUNT_RX_FRAGMENTS,
279 SYS_COUNT_RX_JABBERS,
280 SYS_COUNT_RX_CRC_ALIGN_ERRS,
281 SYS_COUNT_RX_SYM_ERRS,
284 SYS_COUNT_RX_128_255,
285 SYS_COUNT_RX_256_1023,
286 SYS_COUNT_RX_1024_1526,
287 SYS_COUNT_RX_1527_MAX,
289 SYS_COUNT_RX_CONTROL,
291 SYS_COUNT_RX_CLASSIFIED_DROPS,
293 SYS_COUNT_TX_UNICAST,
294 SYS_COUNT_TX_MULTICAST,
295 SYS_COUNT_TX_BROADCAST,
296 SYS_COUNT_TX_COLLISION,
301 SYS_COUNT_TX_128_511,
302 SYS_COUNT_TX_512_1023,
303 SYS_COUNT_TX_1024_1526,
304 SYS_COUNT_TX_1527_MAX,
315 SYS_REW_MAC_HIGH_CFG,
317 SYS_TIMESTAMP_OFFSET,
339 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
348 enum ocelot_regfield {
349 ANA_ADVLEARN_VLAN_CHK,
350 ANA_ADVLEARN_LEARN_MIRROR,
351 ANA_ANEVENTS_FLOOD_DISCARD,
352 ANA_ANEVENTS_MSTI_DROP,
353 ANA_ANEVENTS_ACLKILL,
354 ANA_ANEVENTS_ACLUSED,
355 ANA_ANEVENTS_AUTOAGE,
356 ANA_ANEVENTS_VS2TTL1,
357 ANA_ANEVENTS_STORM_DROP,
358 ANA_ANEVENTS_LEARN_DROP,
359 ANA_ANEVENTS_AGED_ENTRY,
360 ANA_ANEVENTS_CPU_LEARN_FAILED,
361 ANA_ANEVENTS_AUTO_LEARN_FAILED,
362 ANA_ANEVENTS_LEARN_REMOVE,
363 ANA_ANEVENTS_AUTO_LEARNED,
364 ANA_ANEVENTS_AUTO_MOVED,
365 ANA_ANEVENTS_DROPPED,
366 ANA_ANEVENTS_CLASSIFIED_DROP,
367 ANA_ANEVENTS_CLASSIFIED_COPY,
368 ANA_ANEVENTS_VLAN_DISCARD,
369 ANA_ANEVENTS_FWD_DISCARD,
370 ANA_ANEVENTS_MULTICAST_FLOOD,
371 ANA_ANEVENTS_UNICAST_FLOOD,
372 ANA_ANEVENTS_DEST_KNOWN,
373 ANA_ANEVENTS_BUCKET3_MATCH,
374 ANA_ANEVENTS_BUCKET2_MATCH,
375 ANA_ANEVENTS_BUCKET1_MATCH,
376 ANA_ANEVENTS_BUCKET0_MATCH,
377 ANA_ANEVENTS_CPU_OPERATION,
378 ANA_ANEVENTS_DMAC_LOOKUP,
379 ANA_ANEVENTS_SMAC_LOOKUP,
380 ANA_ANEVENTS_SEQ_GEN_ERR_0,
381 ANA_ANEVENTS_SEQ_GEN_ERR_1,
382 ANA_TABLES_MACACCESS_B_DOM,
383 ANA_TABLES_MACTINDX_BUCKET,
384 ANA_TABLES_MACTINDX_M_INDEX,
385 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
386 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
387 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
388 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
389 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
390 SYS_RESET_CFG_CORE_ENA,
391 SYS_RESET_CFG_MEM_ENA,
392 SYS_RESET_CFG_MEM_INIT,
396 struct ocelot_multicast {
397 struct list_head list;
398 unsigned char addr[ETH_ALEN];
405 struct ocelot_stat_layout {
407 char name[ETH_GSTRING_LEN];
413 struct regmap *targets[TARGET_MAX];
414 struct regmap_field *regfields[REGFIELD_MAX];
415 const u32 *const *map;
416 const struct ocelot_stat_layout *stats_layout;
417 unsigned int num_stats;
419 u8 base_mac[ETH_ALEN];
421 struct net_device *hw_bridge_dev;
425 struct workqueue_struct *ocelot_owq;
431 struct ocelot_port **ports;
435 /* Keep track of the vlan port masks */
436 u32 vlan_mask[VLAN_N_VID];
438 struct list_head multicast;
440 /* Workqueue to check statistics for overflow with its lock */
441 struct mutex stats_lock;
443 struct delayed_work stats_work;
444 struct workqueue_struct *stats_queue;
448 struct net_device *dev;
449 struct ocelot *ocelot;
450 struct phy_device *phy;
454 /* Ingress default VLAN (pvid) */
457 /* Egress default VLAN (vid) */
464 phy_interface_t phy_mode;
467 struct ocelot_port_tc tc;
470 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
471 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
472 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
473 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
474 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
476 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
477 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
478 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
479 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
480 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
482 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask,
484 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
485 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
486 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
487 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
489 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
490 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
492 int ocelot_regfields_init(struct ocelot *ocelot,
493 const struct reg_field *const regfields);
494 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
495 struct platform_device *pdev,
498 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
499 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
501 int ocelot_init(struct ocelot *ocelot);
502 void ocelot_deinit(struct ocelot *ocelot);
503 int ocelot_chip_init(struct ocelot *ocelot);
504 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
506 struct phy_device *phy);
508 extern struct notifier_block ocelot_netdevice_nb;
509 extern struct notifier_block ocelot_switchdev_nb;
510 extern struct notifier_block ocelot_switchdev_blocking_nb;