1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
8 #ifndef _MSCC_OCELOT_H_
9 #define _MSCC_OCELOT_H_
11 #include <linux/bitops.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/phy.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17 #include <linux/regmap.h>
19 #include "ocelot_ana.h"
20 #include "ocelot_dev.h"
21 #include "ocelot_qsys.h"
22 #include "ocelot_rew.h"
23 #include "ocelot_sys.h"
24 #include "ocelot_qs.h"
30 #define PGID_CPU (PGID_AGGR - 5)
31 #define PGID_UC (PGID_AGGR - 4)
32 #define PGID_MC (PGID_AGGR - 3)
33 #define PGID_MCIPV4 (PGID_AGGR - 2)
34 #define PGID_MCIPV6 (PGID_AGGR - 1)
36 #define OCELOT_BUFFER_CELL_SZ 60
38 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
50 #define IFH_INJ_BYPASS BIT(31)
51 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
53 #define IFH_TAG_TYPE_C 0
54 #define IFH_TAG_TYPE_S 1
56 #define OCELOT_SPEED_2500 0
57 #define OCELOT_SPEED_1000 1
58 #define OCELOT_SPEED_100 2
59 #define OCELOT_SPEED_10 3
61 #define TARGET_OFFSET 24
62 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
63 #define REG(reg, offset) [reg & REG_MASK] = offset
76 ANA_ADVLEARN = ANA << TARGET_OFFSET,
100 ANA_TABLES_STREAMDATA,
101 ANA_TABLES_MACACCESS,
103 ANA_TABLES_VLANACCESS,
105 ANA_TABLES_ISDXACCESS,
108 ANA_TABLES_PTP_ID_HIGH,
109 ANA_TABLES_PTP_ID_LOW,
110 ANA_TABLES_STREAMACCESS,
111 ANA_TABLES_STREAMTIDX,
112 ANA_TABLES_SEQ_HISTORY,
114 ANA_TABLES_SFID_MASK,
115 ANA_TABLES_SFIDACCESS,
125 ANA_SG_GCL_GS_CONFIG,
126 ANA_SG_GCL_TI_CONFIG,
134 ANA_PORT_VCAP_S1_KEY_CFG,
135 ANA_PORT_VCAP_S2_CFG,
136 ANA_PORT_PCP_DEI_MAP,
137 ANA_PORT_CPU_FWD_CFG,
138 ANA_PORT_CPU_FWD_BPDU_CFG,
139 ANA_PORT_CPU_FWD_GARP_CFG,
140 ANA_PORT_CPU_FWD_CCM_CFG,
144 ANA_PORT_PTP_DLY1_CFG,
145 ANA_PORT_PTP_DLY2_CFG,
159 ANA_VCAP_RNG_TYPE_CFG,
160 ANA_VCAP_RNG_VAL_CFG,
175 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
187 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
188 QSYS_SWITCH_PORT_MODE,
200 QSYS_TIMED_FRAME_ENTRY,
203 QSYS_TFRM_TIMER_CFG_1,
204 QSYS_TFRM_TIMER_CFG_2,
205 QSYS_TFRM_TIMER_CFG_3,
206 QSYS_TFRM_TIMER_CFG_4,
207 QSYS_TFRM_TIMER_CFG_5,
208 QSYS_TFRM_TIMER_CFG_6,
209 QSYS_TFRM_TIMER_CFG_7,
210 QSYS_TFRM_TIMER_CFG_8,
238 QSYS_TAS_PARAM_CFG_CTRL,
240 QSYS_PARAM_CFG_REG_1,
241 QSYS_PARAM_CFG_REG_2,
242 QSYS_PARAM_CFG_REG_3,
243 QSYS_PARAM_CFG_REG_4,
244 QSYS_PARAM_CFG_REG_5,
247 QSYS_PARAM_STATUS_REG_1,
248 QSYS_PARAM_STATUS_REG_2,
249 QSYS_PARAM_STATUS_REG_3,
250 QSYS_PARAM_STATUS_REG_4,
251 QSYS_PARAM_STATUS_REG_5,
252 QSYS_PARAM_STATUS_REG_6,
253 QSYS_PARAM_STATUS_REG_7,
254 QSYS_PARAM_STATUS_REG_8,
255 QSYS_PARAM_STATUS_REG_9,
256 QSYS_GCL_STATUS_REG_1,
257 QSYS_GCL_STATUS_REG_2,
258 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
262 REW_PCP_DEI_QOS_MAP_CFG,
266 REW_DSCP_REMAP_DP1_CFG,
271 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
272 SYS_COUNT_RX_UNICAST,
273 SYS_COUNT_RX_MULTICAST,
274 SYS_COUNT_RX_BROADCAST,
276 SYS_COUNT_RX_FRAGMENTS,
277 SYS_COUNT_RX_JABBERS,
278 SYS_COUNT_RX_CRC_ALIGN_ERRS,
279 SYS_COUNT_RX_SYM_ERRS,
282 SYS_COUNT_RX_128_255,
283 SYS_COUNT_RX_256_1023,
284 SYS_COUNT_RX_1024_1526,
285 SYS_COUNT_RX_1527_MAX,
287 SYS_COUNT_RX_CONTROL,
289 SYS_COUNT_RX_CLASSIFIED_DROPS,
291 SYS_COUNT_TX_UNICAST,
292 SYS_COUNT_TX_MULTICAST,
293 SYS_COUNT_TX_BROADCAST,
294 SYS_COUNT_TX_COLLISION,
299 SYS_COUNT_TX_128_511,
300 SYS_COUNT_TX_512_1023,
301 SYS_COUNT_TX_1024_1526,
302 SYS_COUNT_TX_1527_MAX,
313 SYS_REW_MAC_HIGH_CFG,
315 SYS_TIMESTAMP_OFFSET,
339 enum ocelot_regfield {
340 ANA_ADVLEARN_VLAN_CHK,
341 ANA_ADVLEARN_LEARN_MIRROR,
342 ANA_ANEVENTS_FLOOD_DISCARD,
343 ANA_ANEVENTS_MSTI_DROP,
344 ANA_ANEVENTS_ACLKILL,
345 ANA_ANEVENTS_ACLUSED,
346 ANA_ANEVENTS_AUTOAGE,
347 ANA_ANEVENTS_VS2TTL1,
348 ANA_ANEVENTS_STORM_DROP,
349 ANA_ANEVENTS_LEARN_DROP,
350 ANA_ANEVENTS_AGED_ENTRY,
351 ANA_ANEVENTS_CPU_LEARN_FAILED,
352 ANA_ANEVENTS_AUTO_LEARN_FAILED,
353 ANA_ANEVENTS_LEARN_REMOVE,
354 ANA_ANEVENTS_AUTO_LEARNED,
355 ANA_ANEVENTS_AUTO_MOVED,
356 ANA_ANEVENTS_DROPPED,
357 ANA_ANEVENTS_CLASSIFIED_DROP,
358 ANA_ANEVENTS_CLASSIFIED_COPY,
359 ANA_ANEVENTS_VLAN_DISCARD,
360 ANA_ANEVENTS_FWD_DISCARD,
361 ANA_ANEVENTS_MULTICAST_FLOOD,
362 ANA_ANEVENTS_UNICAST_FLOOD,
363 ANA_ANEVENTS_DEST_KNOWN,
364 ANA_ANEVENTS_BUCKET3_MATCH,
365 ANA_ANEVENTS_BUCKET2_MATCH,
366 ANA_ANEVENTS_BUCKET1_MATCH,
367 ANA_ANEVENTS_BUCKET0_MATCH,
368 ANA_ANEVENTS_CPU_OPERATION,
369 ANA_ANEVENTS_DMAC_LOOKUP,
370 ANA_ANEVENTS_SMAC_LOOKUP,
371 ANA_ANEVENTS_SEQ_GEN_ERR_0,
372 ANA_ANEVENTS_SEQ_GEN_ERR_1,
373 ANA_TABLES_MACACCESS_B_DOM,
374 ANA_TABLES_MACTINDX_BUCKET,
375 ANA_TABLES_MACTINDX_M_INDEX,
376 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
377 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
378 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
379 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
380 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
381 SYS_RESET_CFG_CORE_ENA,
382 SYS_RESET_CFG_MEM_ENA,
383 SYS_RESET_CFG_MEM_INIT,
387 struct ocelot_multicast {
388 struct list_head list;
389 unsigned char addr[ETH_ALEN];
396 struct ocelot_stat_layout {
398 char name[ETH_GSTRING_LEN];
404 struct regmap *targets[TARGET_MAX];
405 struct regmap_field *regfields[REGFIELD_MAX];
406 const u32 *const *map;
407 const struct ocelot_stat_layout *stats_layout;
408 unsigned int num_stats;
410 u8 base_mac[ETH_ALEN];
412 struct net_device *hw_bridge_dev;
416 struct workqueue_struct *ocelot_owq;
422 struct ocelot_port **ports;
426 /* Keep track of the vlan port masks */
427 u32 vlan_mask[VLAN_N_VID];
429 struct list_head multicast;
431 /* Workqueue to check statistics for overflow with its lock */
432 struct mutex stats_lock;
434 struct delayed_work stats_work;
435 struct workqueue_struct *stats_queue;
439 struct net_device *dev;
440 struct ocelot *ocelot;
441 struct phy_device *phy;
445 /* Ingress default VLAN (pvid) */
448 /* Egress default VLAN (vid) */
455 phy_interface_t phy_mode;
459 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
460 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
461 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
462 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
463 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
465 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
466 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
467 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
468 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
469 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
471 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 mask,
473 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
474 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
475 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
476 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
478 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
479 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
481 int ocelot_regfields_init(struct ocelot *ocelot,
482 const struct reg_field *const regfields);
483 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
484 struct platform_device *pdev,
487 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
488 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
490 int ocelot_init(struct ocelot *ocelot);
491 void ocelot_deinit(struct ocelot *ocelot);
492 int ocelot_chip_init(struct ocelot *ocelot);
493 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
495 struct phy_device *phy);
497 extern struct notifier_block ocelot_netdevice_nb;
498 extern struct notifier_block ocelot_switchdev_nb;
499 extern struct notifier_block ocelot_switchdev_blocking_nb;