1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/ptp_classify.h>
10 #include <soc/mscc/ocelot_vcap.h>
12 #include "ocelot_vcap.h"
14 #define TABLE_UPDATE_SLEEP_US 10
15 #define TABLE_UPDATE_TIMEOUT_US 100000
16 #define OCELOT_RSV_VLAN_RANGE_START 4000
18 struct ocelot_mact_entry {
21 enum macaccess_entry_type type;
24 /* Caller must hold &ocelot->mact_lock */
25 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
27 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
30 /* Caller must hold &ocelot->mact_lock */
31 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
35 return readx_poll_timeout(ocelot_mact_read_macaccess,
37 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
39 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
42 /* Caller must hold &ocelot->mact_lock */
43 static void ocelot_mact_select(struct ocelot *ocelot,
44 const unsigned char mac[ETH_ALEN],
47 u32 macl = 0, mach = 0;
49 /* Set the MAC address to handle and the vlan associated in a format
50 * understood by the hardware.
60 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
61 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
65 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
66 const unsigned char mac[ETH_ALEN],
67 unsigned int vid, enum macaccess_entry_type type)
69 u32 cmd = ANA_TABLES_MACACCESS_VALID |
70 ANA_TABLES_MACACCESS_DEST_IDX(port) |
71 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
72 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
73 unsigned int mc_ports;
76 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
77 if (type == ENTRYTYPE_MACv4)
78 mc_ports = (mac[1] << 8) | mac[2];
79 else if (type == ENTRYTYPE_MACv6)
80 mc_ports = (mac[0] << 8) | mac[1];
84 if (mc_ports & BIT(ocelot->num_phys_ports))
85 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
87 ocelot_mact_select(ocelot, mac, vid);
89 /* Issue a write command */
90 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
92 err = ocelot_mact_wait_for_completion(ocelot);
97 int ocelot_mact_learn(struct ocelot *ocelot, int port,
98 const unsigned char mac[ETH_ALEN],
99 unsigned int vid, enum macaccess_entry_type type)
103 mutex_lock(&ocelot->mact_lock);
104 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
105 mutex_unlock(&ocelot->mact_lock);
109 EXPORT_SYMBOL(ocelot_mact_learn);
111 int ocelot_mact_forget(struct ocelot *ocelot,
112 const unsigned char mac[ETH_ALEN], unsigned int vid)
116 mutex_lock(&ocelot->mact_lock);
118 ocelot_mact_select(ocelot, mac, vid);
120 /* Issue a forget command */
122 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
123 ANA_TABLES_MACACCESS);
125 err = ocelot_mact_wait_for_completion(ocelot);
127 mutex_unlock(&ocelot->mact_lock);
131 EXPORT_SYMBOL(ocelot_mact_forget);
133 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
134 const unsigned char mac[ETH_ALEN],
135 unsigned int vid, enum macaccess_entry_type *type)
139 mutex_lock(&ocelot->mact_lock);
141 ocelot_mact_select(ocelot, mac, vid);
143 /* Issue a read command with MACACCESS_VALID=1. */
144 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
145 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
146 ANA_TABLES_MACACCESS);
148 if (ocelot_mact_wait_for_completion(ocelot)) {
149 mutex_unlock(&ocelot->mact_lock);
153 /* Read back the entry flags */
154 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
156 mutex_unlock(&ocelot->mact_lock);
158 if (!(val & ANA_TABLES_MACACCESS_VALID))
161 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
162 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
166 EXPORT_SYMBOL(ocelot_mact_lookup);
168 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
169 const unsigned char mac[ETH_ALEN],
171 enum macaccess_entry_type type,
176 mutex_lock(&ocelot->mact_lock);
179 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
180 ANA_TABLES_STREAMDATA_SFID(sfid) |
181 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
182 ANA_TABLES_STREAMDATA_SSID(ssid),
183 ANA_TABLES_STREAMDATA);
185 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
187 mutex_unlock(&ocelot->mact_lock);
191 EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
193 static void ocelot_mact_init(struct ocelot *ocelot)
195 /* Configure the learning mode entries attributes:
196 * - Do not copy the frame to the CPU extraction queues.
197 * - Use the vlan and mac_cpoy for dmac lookup.
199 ocelot_rmw(ocelot, 0,
200 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
201 | ANA_AGENCTRL_LEARN_FWD_KILL
202 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
205 /* Clear the MAC table. We are not concurrent with anyone, so
206 * holding &ocelot->mact_lock is pointless.
208 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
211 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
213 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
214 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
215 ANA_PORT_VCAP_S2_CFG, port);
217 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
218 ANA_PORT_VCAP_CFG, port);
220 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
225 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
226 struct netlink_ext_ack *extack)
228 struct net_device *bridge = NULL;
231 for (port = 0; port < ocelot->num_phys_ports; port++) {
232 struct ocelot_port *ocelot_port = ocelot->ports[port];
234 if (!ocelot_port || !ocelot_port->bridge ||
235 !br_vlan_enabled(ocelot_port->bridge))
239 bridge = ocelot_port->bridge;
243 if (bridge == ocelot_port->bridge)
246 NL_SET_ERR_MSG_MOD(extack,
247 "Only one VLAN-aware bridge is supported");
254 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
256 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
259 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
263 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
266 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
267 ANA_TABLES_VLANACCESS_CMD_IDLE,
268 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
271 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
273 /* Select the VID to configure */
274 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
275 ANA_TABLES_VLANTIDX);
276 /* Set the vlan port members mask and issue a write command */
277 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
278 ANA_TABLES_VLANACCESS_CMD_WRITE,
279 ANA_TABLES_VLANACCESS);
281 return ocelot_vlant_wait_for_completion(ocelot);
284 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
286 struct ocelot_bridge_vlan *vlan;
287 int num_untagged = 0;
289 list_for_each_entry(vlan, &ocelot->vlans, list) {
290 if (!(vlan->portmask & BIT(port)))
293 if (vlan->untagged & BIT(port))
300 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
302 struct ocelot_bridge_vlan *vlan;
305 list_for_each_entry(vlan, &ocelot->vlans, list) {
306 if (!(vlan->portmask & BIT(port)))
309 if (!(vlan->untagged & BIT(port)))
316 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
317 * _one_ egress-untagged VLAN (_the_ native VLAN)
319 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
321 return ocelot_port_num_tagged_vlans(ocelot, port) &&
322 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
325 static struct ocelot_bridge_vlan *
326 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
328 struct ocelot_bridge_vlan *vlan;
330 list_for_each_entry(vlan, &ocelot->vlans, list)
331 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
337 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
338 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
341 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
343 struct ocelot_port *ocelot_port = ocelot->ports[port];
344 enum ocelot_port_tag_config tag_cfg;
345 bool uses_native_vlan = false;
347 if (ocelot_port->vlan_aware) {
348 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
350 if (uses_native_vlan)
351 tag_cfg = OCELOT_PORT_TAG_NATIVE;
352 else if (ocelot_port_num_untagged_vlans(ocelot, port))
353 tag_cfg = OCELOT_PORT_TAG_DISABLED;
355 tag_cfg = OCELOT_PORT_TAG_TRUNK;
357 tag_cfg = OCELOT_PORT_TAG_DISABLED;
360 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
361 REW_TAG_CFG_TAG_CFG_M,
364 if (uses_native_vlan) {
365 struct ocelot_bridge_vlan *native_vlan;
367 /* Not having a native VLAN is impossible, because
368 * ocelot_port_num_untagged_vlans has returned 1.
369 * So there is no use in checking for NULL here.
371 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
373 ocelot_rmw_gix(ocelot,
374 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
375 REW_PORT_VLAN_CFG_PORT_VID_M,
376 REW_PORT_VLAN_CFG, port);
380 int ocelot_bridge_num_find(struct ocelot *ocelot,
381 const struct net_device *bridge)
385 for (port = 0; port < ocelot->num_phys_ports; port++) {
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
388 if (ocelot_port && ocelot_port->bridge == bridge)
389 return ocelot_port->bridge_num;
394 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
396 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
397 const struct net_device *bridge)
401 /* Standalone ports use VID 0 */
405 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
406 if (WARN_ON(bridge_num < 0))
409 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
410 return VLAN_N_VID - bridge_num - 1;
413 /* Default vlan to clasify for untagged frames (may be zero) */
414 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
415 const struct ocelot_bridge_vlan *pvid_vlan)
417 struct ocelot_port *ocelot_port = ocelot->ports[port];
418 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
421 ocelot_port->pvid_vlan = pvid_vlan;
423 if (ocelot_port->vlan_aware && pvid_vlan)
424 pvid = pvid_vlan->vid;
426 ocelot_rmw_gix(ocelot,
427 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
428 ANA_PORT_VLAN_CFG_VLAN_VID_M,
429 ANA_PORT_VLAN_CFG, port);
431 /* If there's no pvid, we should drop not only untagged traffic (which
432 * happens automatically), but also 802.1p traffic which gets
433 * classified to VLAN 0, but that is always in our RX filter, so it
434 * would get accepted were it not for this setting.
436 if (!pvid_vlan && ocelot_port->vlan_aware)
437 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
438 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
440 ocelot_rmw_gix(ocelot, val,
441 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
442 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
443 ANA_PORT_DROP_CFG, port);
446 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
449 struct ocelot_bridge_vlan *vlan;
451 list_for_each_entry(vlan, &ocelot->vlans, list)
452 if (vlan->vid == vid)
458 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
461 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
462 unsigned long portmask;
466 portmask = vlan->portmask | BIT(port);
468 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
472 vlan->portmask = portmask;
473 /* Bridge VLANs can be overwritten with a different
474 * egress-tagging setting, so make sure to override an untagged
475 * with a tagged VID if that's going on.
478 vlan->untagged |= BIT(port);
480 vlan->untagged &= ~BIT(port);
485 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
489 portmask = BIT(port);
491 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
498 vlan->portmask = portmask;
500 vlan->untagged = BIT(port);
501 INIT_LIST_HEAD(&vlan->list);
502 list_add_tail(&vlan->list, &ocelot->vlans);
507 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
509 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
510 unsigned long portmask;
516 portmask = vlan->portmask & ~BIT(port);
518 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
522 vlan->portmask = portmask;
526 list_del(&vlan->list);
532 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
533 const struct net_device *bridge)
535 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
537 return ocelot_vlan_member_add(ocelot, port, vid, true);
540 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
541 const struct net_device *bridge)
543 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
545 return ocelot_vlan_member_del(ocelot, port, vid);
548 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
549 bool vlan_aware, struct netlink_ext_ack *extack)
551 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
552 struct ocelot_port *ocelot_port = ocelot->ports[port];
553 struct ocelot_vcap_filter *filter;
557 list_for_each_entry(filter, &block->rules, list) {
558 if (filter->ingress_port_mask & BIT(port) &&
559 filter->action.vid_replace_ena) {
560 NL_SET_ERR_MSG_MOD(extack,
561 "Cannot change VLAN state with vlan modify rules active");
566 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
571 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
572 ocelot_port->bridge);
573 else if (ocelot_port->bridge)
574 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
575 ocelot_port->bridge);
579 ocelot_port->vlan_aware = vlan_aware;
582 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
583 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
586 ocelot_rmw_gix(ocelot, val,
587 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
588 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
589 ANA_PORT_VLAN_CFG, port);
591 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
592 ocelot_port_manage_port_tag(ocelot, port);
596 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
598 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
599 bool untagged, struct netlink_ext_ack *extack)
602 /* We are adding an egress-tagged VLAN */
603 if (ocelot_port_uses_native_vlan(ocelot, port)) {
604 NL_SET_ERR_MSG_MOD(extack,
605 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
609 /* We are adding an egress-tagged VLAN */
610 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
611 NL_SET_ERR_MSG_MOD(extack,
612 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
617 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
618 NL_SET_ERR_MSG_MOD(extack,
619 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
625 EXPORT_SYMBOL(ocelot_vlan_prepare);
627 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
632 /* Ignore VID 0 added to our RX filter by the 8021q module, since
633 * that collides with OCELOT_STANDALONE_PVID and changes it from
634 * egress-untagged to egress-tagged.
639 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
643 /* Default ingress vlan classification */
645 ocelot_port_set_pvid(ocelot, port,
646 ocelot_bridge_vlan_find(ocelot, vid));
648 /* Untagged egress vlan clasification */
649 ocelot_port_manage_port_tag(ocelot, port);
653 EXPORT_SYMBOL(ocelot_vlan_add);
655 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
657 struct ocelot_port *ocelot_port = ocelot->ports[port];
658 bool del_pvid = false;
664 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
667 err = ocelot_vlan_member_del(ocelot, port, vid);
673 ocelot_port_set_pvid(ocelot, port, NULL);
676 ocelot_port_manage_port_tag(ocelot, port);
680 EXPORT_SYMBOL(ocelot_vlan_del);
682 static void ocelot_vlan_init(struct ocelot *ocelot)
684 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
687 /* Clear VLAN table, by default all ports are members of all VLANs */
688 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
689 ANA_TABLES_VLANACCESS);
690 ocelot_vlant_wait_for_completion(ocelot);
692 /* Configure the port VLAN memberships */
693 for (vid = 1; vid < VLAN_N_VID; vid++)
694 ocelot_vlant_set_mask(ocelot, vid, 0);
696 /* We need VID 0 to get traffic on standalone ports.
697 * It is added automatically if the 8021q module is loaded, but we
698 * can't rely on that since it might not be.
700 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
702 /* Set vlan ingress filter mask to all ports but the CPU port by
705 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
707 for (port = 0; port < ocelot->num_phys_ports; port++) {
708 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
709 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
713 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
715 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
718 static int ocelot_port_flush(struct ocelot *ocelot, int port)
720 unsigned int pause_ena;
723 /* Disable dequeuing from the egress queues */
724 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
725 QSYS_PORT_MODE_DEQUEUE_DIS,
726 QSYS_PORT_MODE, port);
728 /* Disable flow control */
729 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
730 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
732 /* Disable priority flow control */
733 ocelot_fields_write(ocelot, port,
734 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
736 /* Wait at least the time it takes to receive a frame of maximum length
738 * Worst-case delays for 10 kilobyte jumbo frames are:
740 * 800 μs on a 100M port
741 * 80 μs on a 1G port
742 * 32 μs on a 2.5G port
744 usleep_range(8000, 10000);
746 /* Disable half duplex backpressure. */
747 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
748 SYS_FRONT_PORT_MODE, port);
750 /* Flush the queues associated with the port. */
751 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
754 /* Enable dequeuing from the egress queues. */
755 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
758 /* Wait until flushing is complete. */
759 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
760 100, 2000000, false, ocelot, port);
762 /* Clear flushing again. */
763 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
765 /* Re-enable flow control */
766 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
771 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
772 unsigned int link_an_mode,
773 phy_interface_t interface,
774 unsigned long quirks)
776 struct ocelot_port *ocelot_port = ocelot->ports[port];
779 ocelot_port->speed = SPEED_UNKNOWN;
781 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
784 if (ocelot->ops->cut_through_fwd) {
785 mutex_lock(&ocelot->fwd_domain_lock);
786 ocelot->ops->cut_through_fwd(ocelot);
787 mutex_unlock(&ocelot->fwd_domain_lock);
790 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
792 err = ocelot_port_flush(ocelot, port);
794 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
797 /* Put the port in reset. */
798 if (interface != PHY_INTERFACE_MODE_QSGMII ||
799 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
800 ocelot_port_rmwl(ocelot_port,
801 DEV_CLOCK_CFG_MAC_TX_RST |
802 DEV_CLOCK_CFG_MAC_RX_RST,
803 DEV_CLOCK_CFG_MAC_TX_RST |
804 DEV_CLOCK_CFG_MAC_RX_RST,
807 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
809 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
810 struct phy_device *phydev,
811 unsigned int link_an_mode,
812 phy_interface_t interface,
813 int speed, int duplex,
814 bool tx_pause, bool rx_pause,
815 unsigned long quirks)
817 struct ocelot_port *ocelot_port = ocelot->ports[port];
818 int mac_speed, mode = 0;
821 ocelot_port->speed = speed;
823 /* The MAC might be integrated in systems where the MAC speed is fixed
824 * and it's the PCS who is performing the rate adaptation, so we have
825 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
826 * (which is also its default value).
828 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
829 speed == SPEED_1000) {
830 mac_speed = OCELOT_SPEED_1000;
831 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
832 } else if (speed == SPEED_2500) {
833 mac_speed = OCELOT_SPEED_2500;
834 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
835 } else if (speed == SPEED_100) {
836 mac_speed = OCELOT_SPEED_100;
838 mac_speed = OCELOT_SPEED_10;
841 if (duplex == DUPLEX_FULL)
842 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
844 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
846 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
847 * PORT_RST bits in DEV_CLOCK_CFG.
849 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
854 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
857 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
861 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
864 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
869 /* Handle RX pause in all cases, with 2500base-X this is used for rate
872 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
875 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
876 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
877 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
878 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
880 /* Flow control. Link speed is only used here to evaluate the time
881 * specification in incoming pause frames.
883 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
885 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
887 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
888 if (port != ocelot->npi)
889 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
892 /* Undo the effects of ocelot_phylink_mac_link_down:
895 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
896 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
898 /* If the port supports cut-through forwarding, update the masks before
899 * enabling forwarding on the port.
901 if (ocelot->ops->cut_through_fwd) {
902 mutex_lock(&ocelot->fwd_domain_lock);
903 ocelot->ops->cut_through_fwd(ocelot);
904 mutex_unlock(&ocelot->fwd_domain_lock);
907 /* Core: Enable port for frame transfer */
908 ocelot_fields_write(ocelot, port,
909 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
911 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
913 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
914 struct sk_buff *clone)
916 struct ocelot_port *ocelot_port = ocelot->ports[port];
919 spin_lock_irqsave(&ocelot->ts_id_lock, flags);
921 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID ||
922 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) {
923 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
927 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
928 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */
929 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id;
931 ocelot_port->ts_id++;
932 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID)
933 ocelot_port->ts_id = 0;
935 ocelot_port->ptp_skbs_in_flight++;
936 ocelot->ptp_skbs_in_flight++;
938 skb_queue_tail(&ocelot_port->tx_skbs, clone);
940 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
945 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb,
946 unsigned int ptp_class)
948 struct ptp_header *hdr;
951 hdr = ptp_parse_header(skb, ptp_class);
955 msgtype = ptp_get_msgtype(hdr, ptp_class);
956 twostep = hdr->flag_field[0] & 0x2;
958 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0)
964 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
966 struct sk_buff **clone)
968 struct ocelot_port *ocelot_port = ocelot->ports[port];
969 u8 ptp_cmd = ocelot_port->ptp_cmd;
970 unsigned int ptp_class;
973 /* Don't do anything if PTP timestamping not enabled */
977 ptp_class = ptp_classify_raw(skb);
978 if (ptp_class == PTP_CLASS_NONE)
981 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */
982 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
983 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) {
984 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
988 /* Fall back to two-step timestamping */
989 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
992 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
993 *clone = skb_clone_sk(skb);
997 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone);
1001 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
1002 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class;
1007 EXPORT_SYMBOL(ocelot_port_txtstamp_request);
1009 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
1010 struct timespec64 *ts)
1012 unsigned long flags;
1015 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
1017 /* Read current PTP time to get seconds */
1018 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
1020 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
1021 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
1022 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
1023 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
1025 /* Read packet HW timestamp from FIFO */
1026 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
1027 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
1029 /* Sec has incremented since the ts was registered */
1030 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
1033 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
1036 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid)
1038 struct ptp_header *hdr;
1040 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class);
1044 return seqid == ntohs(hdr->sequence_id);
1047 void ocelot_get_txtstamp(struct ocelot *ocelot)
1049 int budget = OCELOT_PTP_QUEUE_SZ;
1052 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
1053 struct skb_shared_hwtstamps shhwtstamps;
1054 u32 val, id, seqid, txport;
1055 struct ocelot_port *port;
1056 struct timespec64 ts;
1057 unsigned long flags;
1059 val = ocelot_read(ocelot, SYS_PTP_STATUS);
1061 /* Check if a timestamp can be retrieved */
1062 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
1065 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
1067 /* Retrieve the ts ID and Tx port */
1068 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
1069 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
1070 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val);
1072 port = ocelot->ports[txport];
1074 spin_lock(&ocelot->ts_id_lock);
1075 port->ptp_skbs_in_flight--;
1076 ocelot->ptp_skbs_in_flight--;
1077 spin_unlock(&ocelot->ts_id_lock);
1079 /* Retrieve its associated skb */
1081 spin_lock_irqsave(&port->tx_skbs.lock, flags);
1083 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
1084 if (OCELOT_SKB_CB(skb)->ts_id != id)
1086 __skb_unlink(skb, &port->tx_skbs);
1091 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
1093 if (WARN_ON(!skb_match))
1096 if (!ocelot_validate_ptp_skb(skb_match, seqid)) {
1097 dev_err_ratelimited(ocelot->dev,
1098 "port %d received stale TX timestamp for seqid %d, discarding\n",
1100 dev_kfree_skb_any(skb);
1104 /* Get the h/w timestamp */
1105 ocelot_get_hwtimestamp(ocelot, &ts);
1107 /* Set the timestamp into the skb */
1108 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1109 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
1110 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
1113 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
1116 EXPORT_SYMBOL(ocelot_get_txtstamp);
1118 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1121 u32 bytes_valid, val;
1123 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1124 if (val == XTR_NOT_READY) {
1129 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1130 } while (val == XTR_NOT_READY);
1141 bytes_valid = XTR_VALID_BYTES(val);
1142 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1143 if (val == XTR_ESCAPE)
1144 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1150 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1160 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1164 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1165 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1167 return (err < 0) ? err : -EIO;
1173 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1176 struct skb_shared_hwtstamps *shhwtstamps;
1177 u64 tod_in_ns, full_ts_in_ns;
1178 struct timespec64 ts;
1180 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1182 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1183 if ((tod_in_ns & 0xffffffff) < timestamp)
1184 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1187 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1190 shhwtstamps = skb_hwtstamps(skb);
1191 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1192 shhwtstamps->hwtstamp = full_ts_in_ns;
1194 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1196 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1198 u64 timestamp, src_port, len;
1199 u32 xfh[OCELOT_TAG_LEN / 4];
1200 struct net_device *dev;
1201 struct sk_buff *skb;
1206 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1210 ocelot_xfh_get_src_port(xfh, &src_port);
1211 ocelot_xfh_get_len(xfh, &len);
1212 ocelot_xfh_get_rew_val(xfh, ×tamp);
1214 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1217 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1221 skb = netdev_alloc_skb(dev, len);
1222 if (unlikely(!skb)) {
1223 netdev_err(dev, "Unable to allocate sk_buff\n");
1227 buf_len = len - ETH_FCS_LEN;
1228 buf = (u32 *)skb_put(skb, buf_len);
1232 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1239 } while (len < buf_len);
1242 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1248 /* Update the statistics if part of the FCS was read before */
1249 len -= ETH_FCS_LEN - sz;
1251 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1252 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1257 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1259 /* Everything we see on an interface that is in the HW bridge
1260 * has already been forwarded.
1262 if (ocelot->ports[src_port]->bridge)
1263 skb->offload_fwd_mark = 1;
1265 skb->protocol = eth_type_trans(skb, dev);
1275 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1277 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1279 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1281 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1283 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1288 EXPORT_SYMBOL(ocelot_can_inject);
1290 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag)
1292 ocelot_ifh_set_bypass(ifh, 1);
1293 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1294 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1296 ocelot_ifh_set_vlan_tci(ifh, vlan_tag);
1298 ocelot_ifh_set_rew_op(ifh, rew_op);
1300 EXPORT_SYMBOL(ocelot_ifh_port_set);
1302 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1303 u32 rew_op, struct sk_buff *skb)
1305 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1306 unsigned int i, count, last;
1308 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1309 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1311 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb));
1313 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1314 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1316 count = DIV_ROUND_UP(skb->len, 4);
1317 last = skb->len % 4;
1318 for (i = 0; i < count; i++)
1319 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1322 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1323 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1327 /* Indicate EOF and valid bytes in last word */
1328 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1329 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1334 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1335 skb_tx_timestamp(skb);
1337 skb->dev->stats.tx_packets++;
1338 skb->dev->stats.tx_bytes += skb->len;
1340 EXPORT_SYMBOL(ocelot_port_inject_frame);
1342 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1344 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1345 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1347 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1349 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1350 u16 vid, const struct net_device *bridge)
1353 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1355 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1357 EXPORT_SYMBOL(ocelot_fdb_add);
1359 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1360 u16 vid, const struct net_device *bridge)
1363 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1365 return ocelot_mact_forget(ocelot, addr, vid);
1367 EXPORT_SYMBOL(ocelot_fdb_del);
1369 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
1370 bool is_static, void *data)
1372 struct ocelot_dump_ctx *dump = data;
1373 u32 portid = NETLINK_CB(dump->cb->skb).portid;
1374 u32 seq = dump->cb->nlh->nlmsg_seq;
1375 struct nlmsghdr *nlh;
1378 if (dump->idx < dump->cb->args[2])
1381 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
1382 sizeof(*ndm), NLM_F_MULTI);
1386 ndm = nlmsg_data(nlh);
1387 ndm->ndm_family = AF_BRIDGE;
1390 ndm->ndm_flags = NTF_SELF;
1392 ndm->ndm_ifindex = dump->dev->ifindex;
1393 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
1395 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
1396 goto nla_put_failure;
1398 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
1399 goto nla_put_failure;
1401 nlmsg_end(dump->skb, nlh);
1408 nlmsg_cancel(dump->skb, nlh);
1411 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
1413 /* Caller must hold &ocelot->mact_lock */
1414 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1415 struct ocelot_mact_entry *entry)
1417 u32 val, dst, macl, mach;
1420 /* Set row and column to read from */
1421 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1422 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1424 /* Issue a read command */
1425 ocelot_write(ocelot,
1426 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1427 ANA_TABLES_MACACCESS);
1429 if (ocelot_mact_wait_for_completion(ocelot))
1432 /* Read the entry flags */
1433 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1434 if (!(val & ANA_TABLES_MACACCESS_VALID))
1437 /* If the entry read has another port configured as its destination,
1440 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1444 /* Get the entry's MAC address and VLAN id */
1445 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1446 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1448 mac[0] = (mach >> 8) & 0xff;
1449 mac[1] = (mach >> 0) & 0xff;
1450 mac[2] = (macl >> 24) & 0xff;
1451 mac[3] = (macl >> 16) & 0xff;
1452 mac[4] = (macl >> 8) & 0xff;
1453 mac[5] = (macl >> 0) & 0xff;
1455 entry->vid = (mach >> 16) & 0xfff;
1456 ether_addr_copy(entry->mac, mac);
1461 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1465 mutex_lock(&ocelot->mact_lock);
1467 /* Program ageing filter for a single port */
1468 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1471 /* Flushing dynamic FDB entries requires two successive age scans */
1472 ocelot_write(ocelot,
1473 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1474 ANA_TABLES_MACACCESS);
1476 err = ocelot_mact_wait_for_completion(ocelot);
1478 mutex_unlock(&ocelot->mact_lock);
1483 ocelot_write(ocelot,
1484 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1485 ANA_TABLES_MACACCESS);
1487 err = ocelot_mact_wait_for_completion(ocelot);
1489 /* Restore ageing filter */
1490 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1492 mutex_unlock(&ocelot->mact_lock);
1496 EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1498 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1499 dsa_fdb_dump_cb_t *cb, void *data)
1504 /* We could take the lock just around ocelot_mact_read, but doing so
1505 * thousands of times in a row seems rather pointless and inefficient.
1507 mutex_lock(&ocelot->mact_lock);
1509 /* Loop through all the mac tables entries. */
1510 for (i = 0; i < ocelot->num_mact_rows; i++) {
1511 for (j = 0; j < 4; j++) {
1512 struct ocelot_mact_entry entry;
1515 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1516 /* If the entry is invalid (wrong port, invalid...),
1524 is_static = (entry.type == ENTRYTYPE_LOCKED);
1526 /* Hide the reserved VLANs used for
1527 * VLAN-unaware bridging.
1529 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1532 err = cb(entry.mac, entry.vid, is_static, data);
1538 mutex_unlock(&ocelot->mact_lock);
1542 EXPORT_SYMBOL(ocelot_fdb_dump);
1544 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap)
1546 trap->key_type = OCELOT_VCAP_KEY_ETYPE;
1547 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588);
1548 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff);
1552 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap)
1554 trap->key_type = OCELOT_VCAP_KEY_IPV4;
1555 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1556 trap->key.ipv4.proto.mask[0] = 0xff;
1557 trap->key.ipv4.dport.value = PTP_EV_PORT;
1558 trap->key.ipv4.dport.mask = 0xffff;
1562 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap)
1564 trap->key_type = OCELOT_VCAP_KEY_IPV6;
1565 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1566 trap->key.ipv4.proto.mask[0] = 0xff;
1567 trap->key.ipv6.dport.value = PTP_EV_PORT;
1568 trap->key.ipv6.dport.mask = 0xffff;
1572 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap)
1574 trap->key_type = OCELOT_VCAP_KEY_IPV4;
1575 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1576 trap->key.ipv4.proto.mask[0] = 0xff;
1577 trap->key.ipv4.dport.value = PTP_GEN_PORT;
1578 trap->key.ipv4.dport.mask = 0xffff;
1582 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap)
1584 trap->key_type = OCELOT_VCAP_KEY_IPV6;
1585 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1586 trap->key.ipv4.proto.mask[0] = 0xff;
1587 trap->key.ipv6.dport.value = PTP_GEN_PORT;
1588 trap->key.ipv6.dport.mask = 0xffff;
1591 int ocelot_trap_add(struct ocelot *ocelot, int port,
1592 unsigned long cookie, bool take_ts,
1593 void (*populate)(struct ocelot_vcap_filter *f))
1595 struct ocelot_vcap_block *block_vcap_is2;
1596 struct ocelot_vcap_filter *trap;
1600 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1602 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1605 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1611 trap->id.cookie = cookie;
1612 trap->id.tc_offload = false;
1613 trap->block_id = VCAP_IS2;
1614 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1616 trap->action.cpu_copy_ena = true;
1617 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1618 trap->action.port_mask = 0;
1619 trap->take_ts = take_ts;
1620 trap->is_trap = true;
1624 trap->ingress_port_mask |= BIT(port);
1627 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1629 err = ocelot_vcap_filter_replace(ocelot, trap);
1631 trap->ingress_port_mask &= ~BIT(port);
1632 if (!trap->ingress_port_mask)
1640 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1642 struct ocelot_vcap_block *block_vcap_is2;
1643 struct ocelot_vcap_filter *trap;
1645 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1647 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1652 trap->ingress_port_mask &= ~BIT(port);
1653 if (!trap->ingress_port_mask)
1654 return ocelot_vcap_filter_del(ocelot, trap);
1656 return ocelot_vcap_filter_replace(ocelot, trap);
1659 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port)
1661 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot);
1663 return ocelot_trap_add(ocelot, port, l2_cookie, true,
1664 ocelot_populate_l2_ptp_trap_key);
1667 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port)
1669 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot);
1671 return ocelot_trap_del(ocelot, port, l2_cookie);
1674 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port)
1676 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot);
1677 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot);
1680 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, true,
1681 ocelot_populate_ipv4_ptp_event_trap_key);
1685 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, false,
1686 ocelot_populate_ipv4_ptp_general_trap_key);
1688 ocelot_trap_del(ocelot, port, ipv4_ev_cookie);
1693 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port)
1695 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot);
1696 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot);
1699 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie);
1700 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie);
1704 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port)
1706 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot);
1707 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot);
1710 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, true,
1711 ocelot_populate_ipv6_ptp_event_trap_key);
1715 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, false,
1716 ocelot_populate_ipv6_ptp_general_trap_key);
1718 ocelot_trap_del(ocelot, port, ipv6_ev_cookie);
1723 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port)
1725 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot);
1726 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot);
1729 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie);
1730 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie);
1734 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port,
1740 err = ocelot_l2_ptp_trap_add(ocelot, port);
1742 err = ocelot_l2_ptp_trap_del(ocelot, port);
1747 err = ocelot_ipv4_ptp_trap_add(ocelot, port);
1751 err = ocelot_ipv6_ptp_trap_add(ocelot, port);
1755 err = ocelot_ipv4_ptp_trap_del(ocelot, port);
1757 err |= ocelot_ipv6_ptp_trap_del(ocelot, port);
1765 ocelot_ipv4_ptp_trap_del(ocelot, port);
1768 ocelot_l2_ptp_trap_del(ocelot, port);
1772 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1774 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1775 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1777 EXPORT_SYMBOL(ocelot_hwstamp_get);
1779 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1781 struct ocelot_port *ocelot_port = ocelot->ports[port];
1782 bool l2 = false, l4 = false;
1783 struct hwtstamp_config cfg;
1786 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1789 /* Tx type sanity check */
1790 switch (cfg.tx_type) {
1791 case HWTSTAMP_TX_ON:
1792 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1794 case HWTSTAMP_TX_ONESTEP_SYNC:
1795 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1796 * need to update the origin time.
1798 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1800 case HWTSTAMP_TX_OFF:
1801 ocelot_port->ptp_cmd = 0;
1807 mutex_lock(&ocelot->ptp_lock);
1809 switch (cfg.rx_filter) {
1810 case HWTSTAMP_FILTER_NONE:
1812 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1813 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1814 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1817 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1818 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1819 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1822 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1823 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1824 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1829 mutex_unlock(&ocelot->ptp_lock);
1833 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4);
1835 mutex_unlock(&ocelot->ptp_lock);
1840 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1842 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1844 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1846 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
1848 /* Commit back the result & save it */
1849 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1850 mutex_unlock(&ocelot->ptp_lock);
1852 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1854 EXPORT_SYMBOL(ocelot_hwstamp_set);
1856 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1860 if (sset != ETH_SS_STATS)
1863 for (i = 0; i < OCELOT_NUM_STATS; i++) {
1864 if (ocelot->stats_layout[i].name[0] == '\0')
1867 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1871 EXPORT_SYMBOL(ocelot_get_strings);
1873 /* Caller must hold &ocelot->stats_lock */
1874 static int ocelot_port_update_stats(struct ocelot *ocelot, int port)
1876 unsigned int idx = port * OCELOT_NUM_STATS;
1877 struct ocelot_stats_region *region;
1880 /* Configure the port to read the stats from */
1881 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), SYS_STAT_CFG);
1883 list_for_each_entry(region, &ocelot->stats_regions, node) {
1884 err = ocelot_bulk_read(ocelot, region->base, region->buf,
1889 for (j = 0; j < region->count; j++) {
1890 u64 *stat = &ocelot->stats[idx + j];
1891 u64 val = region->buf[j];
1893 if (val < (*stat & U32_MAX))
1894 *stat += (u64)1 << 32;
1896 *stat = (*stat & ~(u64)U32_MAX) + val;
1899 idx += region->count;
1905 static void ocelot_check_stats_work(struct work_struct *work)
1907 struct delayed_work *del_work = to_delayed_work(work);
1908 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1912 spin_lock(&ocelot->stats_lock);
1913 for (i = 0; i < ocelot->num_phys_ports; i++) {
1914 err = ocelot_port_update_stats(ocelot, i);
1918 spin_unlock(&ocelot->stats_lock);
1921 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err);
1923 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1924 OCELOT_STATS_CHECK_DELAY);
1927 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1931 spin_lock(&ocelot->stats_lock);
1933 /* check and update now */
1934 err = ocelot_port_update_stats(ocelot, port);
1936 /* Copy all supported counters */
1937 for (i = 0; i < OCELOT_NUM_STATS; i++) {
1938 int index = port * OCELOT_NUM_STATS + i;
1940 if (ocelot->stats_layout[i].name[0] == '\0')
1943 *data++ = ocelot->stats[index];
1946 spin_unlock(&ocelot->stats_lock);
1949 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err);
1951 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1953 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1955 int i, num_stats = 0;
1957 if (sset != ETH_SS_STATS)
1960 for (i = 0; i < OCELOT_NUM_STATS; i++)
1961 if (ocelot->stats_layout[i].name[0] != '\0')
1966 EXPORT_SYMBOL(ocelot_get_sset_count);
1968 static int ocelot_prepare_stats_regions(struct ocelot *ocelot)
1970 struct ocelot_stats_region *region = NULL;
1974 INIT_LIST_HEAD(&ocelot->stats_regions);
1976 for (i = 0; i < OCELOT_NUM_STATS; i++) {
1977 if (ocelot->stats_layout[i].name[0] == '\0')
1980 if (region && ocelot->stats_layout[i].reg == last + 4) {
1983 region = devm_kzalloc(ocelot->dev, sizeof(*region),
1988 region->base = ocelot->stats_layout[i].reg;
1990 list_add_tail(®ion->node, &ocelot->stats_regions);
1993 last = ocelot->stats_layout[i].reg;
1996 list_for_each_entry(region, &ocelot->stats_regions, node) {
1997 region->buf = devm_kcalloc(ocelot->dev, region->count,
1998 sizeof(*region->buf), GFP_KERNEL);
2006 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
2007 struct ethtool_ts_info *info)
2009 info->phc_index = ocelot->ptp_clock ?
2010 ptp_clock_index(ocelot->ptp_clock) : -1;
2011 if (info->phc_index == -1) {
2012 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
2013 SOF_TIMESTAMPING_RX_SOFTWARE |
2014 SOF_TIMESTAMPING_SOFTWARE;
2017 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
2018 SOF_TIMESTAMPING_RX_SOFTWARE |
2019 SOF_TIMESTAMPING_SOFTWARE |
2020 SOF_TIMESTAMPING_TX_HARDWARE |
2021 SOF_TIMESTAMPING_RX_HARDWARE |
2022 SOF_TIMESTAMPING_RAW_HARDWARE;
2023 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
2024 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
2025 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
2026 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2027 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2028 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
2032 EXPORT_SYMBOL(ocelot_get_ts_info);
2034 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
2039 lockdep_assert_held(&ocelot->fwd_domain_lock);
2041 for (port = 0; port < ocelot->num_phys_ports; port++) {
2042 struct ocelot_port *ocelot_port = ocelot->ports[port];
2047 if (ocelot_port->bond == bond)
2054 /* The logical port number of a LAG is equal to the lowest numbered physical
2055 * port ID present in that LAG. It may change if that port ever leaves the LAG.
2057 static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
2059 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
2064 return __ffs(bond_mask);
2067 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
2068 struct ocelot_port *cpu)
2073 for (port = 0; port < ocelot->num_phys_ports; port++) {
2074 struct ocelot_port *ocelot_port = ocelot->ports[port];
2079 if (ocelot_port->dsa_8021q_cpu == cpu)
2086 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
2088 struct ocelot_port *ocelot_port = ocelot->ports[port];
2089 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
2094 return BIT(cpu_port->index);
2096 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
2098 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
2100 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
2101 const struct net_device *bridge;
2105 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
2108 bridge = ocelot_port->bridge;
2112 for (port = 0; port < ocelot->num_phys_ports; port++) {
2113 ocelot_port = ocelot->ports[port];
2118 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
2119 ocelot_port->bridge == bridge)
2125 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
2127 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
2131 lockdep_assert_held(&ocelot->fwd_domain_lock);
2133 /* If cut-through forwarding is supported, update the masks before a
2134 * port joins the forwarding domain, to avoid potential underruns if it
2135 * has the highest speed from the new domain.
2137 if (joining && ocelot->ops->cut_through_fwd)
2138 ocelot->ops->cut_through_fwd(ocelot);
2140 /* Apply FWD mask. The loop is needed to add/remove the current port as
2141 * a source for the other ports.
2143 for (port = 0; port < ocelot->num_phys_ports; port++) {
2144 struct ocelot_port *ocelot_port = ocelot->ports[port];
2148 /* Unused ports can't send anywhere */
2150 } else if (ocelot_port->is_dsa_8021q_cpu) {
2151 /* The DSA tag_8021q CPU ports need to be able to
2152 * forward packets to all ports assigned to them.
2154 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
2156 } else if (ocelot_port->bridge) {
2157 struct net_device *bond = ocelot_port->bond;
2159 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2162 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
2166 mask &= ~ocelot_get_bond_mask(ocelot, bond);
2168 /* Standalone ports forward only to DSA tag_8021q CPU
2169 * ports (if those exist), or to the hardware CPU port
2172 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
2176 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
2179 /* If cut-through forwarding is supported and a port is leaving, there
2180 * is a chance that cut-through was disabled on the other ports due to
2181 * the port which is leaving (it has a higher link speed). We need to
2182 * update the cut-through masks of the remaining ports no earlier than
2183 * after the port has left, to prevent underruns from happening between
2184 * the cut-through update and the forwarding domain update.
2186 if (!joining && ocelot->ops->cut_through_fwd)
2187 ocelot->ops->cut_through_fwd(ocelot);
2190 /* Update PGID_CPU which is the destination port mask used for whitelisting
2191 * unicast addresses filtered towards the host. In the normal and NPI modes,
2192 * this points to the analyzer entry for the CPU port module, while in DSA
2193 * tag_8021q mode, it is a bit mask of all active CPU ports.
2194 * PGID_SRC will take care of forwarding a packet from one user port to
2195 * no more than a single CPU port.
2197 static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
2202 for (port = 0; port < ocelot->num_phys_ports; port++) {
2203 struct ocelot_port *ocelot_port = ocelot->ports[port];
2205 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
2208 pgid_cpu |= BIT(port);
2212 pgid_cpu = BIT(ocelot->num_phys_ports);
2214 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
2217 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
2220 struct ocelot_port *cpu_port = ocelot->ports[cpu];
2223 mutex_lock(&ocelot->fwd_domain_lock);
2225 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
2227 if (!cpu_port->is_dsa_8021q_cpu) {
2228 cpu_port->is_dsa_8021q_cpu = true;
2230 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
2231 ocelot_vlan_member_add(ocelot, cpu, vid, true);
2233 ocelot_update_pgid_cpu(ocelot);
2236 ocelot_apply_bridge_fwd_mask(ocelot, true);
2238 mutex_unlock(&ocelot->fwd_domain_lock);
2240 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
2242 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
2244 struct ocelot_port *cpu_port = ocelot->ports[port]->dsa_8021q_cpu;
2249 mutex_lock(&ocelot->fwd_domain_lock);
2251 ocelot->ports[port]->dsa_8021q_cpu = NULL;
2253 for (p = 0; p < ocelot->num_phys_ports; p++) {
2254 if (!ocelot->ports[p])
2257 if (ocelot->ports[p]->dsa_8021q_cpu == cpu_port) {
2264 cpu_port->is_dsa_8021q_cpu = false;
2266 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
2267 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
2269 ocelot_update_pgid_cpu(ocelot);
2272 ocelot_apply_bridge_fwd_mask(ocelot, true);
2274 mutex_unlock(&ocelot->fwd_domain_lock);
2276 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
2278 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
2280 struct ocelot_port *ocelot_port = ocelot->ports[port];
2283 mutex_lock(&ocelot->fwd_domain_lock);
2285 ocelot_port->stp_state = state;
2287 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
2288 ocelot_port->learn_ena)
2289 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
2291 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
2292 ANA_PORT_PORT_CFG, port);
2294 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
2296 mutex_unlock(&ocelot->fwd_domain_lock);
2298 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
2300 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
2302 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
2304 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
2305 * which is clearly not what our intention is. So avoid that.
2310 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
2312 EXPORT_SYMBOL(ocelot_set_ageing_time);
2314 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
2315 const unsigned char *addr,
2318 struct ocelot_multicast *mc;
2320 list_for_each_entry(mc, &ocelot->multicast, list) {
2321 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
2328 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
2330 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
2331 return ENTRYTYPE_MACv4;
2332 if (addr[0] == 0x33 && addr[1] == 0x33)
2333 return ENTRYTYPE_MACv6;
2334 return ENTRYTYPE_LOCKED;
2337 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
2338 unsigned long ports)
2340 struct ocelot_pgid *pgid;
2342 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
2344 return ERR_PTR(-ENOMEM);
2346 pgid->ports = ports;
2347 pgid->index = index;
2348 refcount_set(&pgid->refcount, 1);
2349 list_add_tail(&pgid->list, &ocelot->pgids);
2354 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
2356 if (!refcount_dec_and_test(&pgid->refcount))
2359 list_del(&pgid->list);
2363 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
2364 const struct ocelot_multicast *mc)
2366 struct ocelot_pgid *pgid;
2369 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
2370 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
2371 * destination mask table (PGID), the destination set is programmed as
2372 * part of the entry MAC address.", and the DEST_IDX is set to 0.
2374 if (mc->entry_type == ENTRYTYPE_MACv4 ||
2375 mc->entry_type == ENTRYTYPE_MACv6)
2376 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
2378 list_for_each_entry(pgid, &ocelot->pgids, list) {
2379 /* When searching for a nonreserved multicast PGID, ignore the
2380 * dummy PGID of zero that we have for MACv4/MACv6 entries
2382 if (pgid->index && pgid->ports == mc->ports) {
2383 refcount_inc(&pgid->refcount);
2388 /* Search for a free index in the nonreserved multicast PGID area */
2389 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
2392 list_for_each_entry(pgid, &ocelot->pgids, list) {
2393 if (pgid->index == index) {
2400 return ocelot_pgid_alloc(ocelot, index, mc->ports);
2403 return ERR_PTR(-ENOSPC);
2406 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
2407 struct ocelot_multicast *mc)
2409 ether_addr_copy(addr, mc->addr);
2411 if (mc->entry_type == ENTRYTYPE_MACv4) {
2413 addr[1] = mc->ports >> 8;
2414 addr[2] = mc->ports & 0xff;
2415 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
2416 addr[0] = mc->ports >> 8;
2417 addr[1] = mc->ports & 0xff;
2421 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
2422 const struct switchdev_obj_port_mdb *mdb,
2423 const struct net_device *bridge)
2425 unsigned char addr[ETH_ALEN];
2426 struct ocelot_multicast *mc;
2427 struct ocelot_pgid *pgid;
2431 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2433 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2436 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
2440 mc->entry_type = ocelot_classify_mdb(mdb->addr);
2441 ether_addr_copy(mc->addr, mdb->addr);
2444 list_add_tail(&mc->list, &ocelot->multicast);
2446 /* Existing entry. Clean up the current port mask from
2447 * hardware now, because we'll be modifying it.
2449 ocelot_pgid_free(ocelot, mc->pgid);
2450 ocelot_encode_ports_to_mdb(addr, mc);
2451 ocelot_mact_forget(ocelot, addr, vid);
2454 mc->ports |= BIT(port);
2456 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2458 dev_err(ocelot->dev,
2459 "Cannot allocate PGID for mdb %pM vid %d\n",
2461 devm_kfree(ocelot->dev, mc);
2462 return PTR_ERR(pgid);
2466 ocelot_encode_ports_to_mdb(addr, mc);
2468 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2469 mc->entry_type != ENTRYTYPE_MACv6)
2470 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2473 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2476 EXPORT_SYMBOL(ocelot_port_mdb_add);
2478 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2479 const struct switchdev_obj_port_mdb *mdb,
2480 const struct net_device *bridge)
2482 unsigned char addr[ETH_ALEN];
2483 struct ocelot_multicast *mc;
2484 struct ocelot_pgid *pgid;
2488 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2490 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2494 ocelot_encode_ports_to_mdb(addr, mc);
2495 ocelot_mact_forget(ocelot, addr, vid);
2497 ocelot_pgid_free(ocelot, mc->pgid);
2498 mc->ports &= ~BIT(port);
2500 list_del(&mc->list);
2501 devm_kfree(ocelot->dev, mc);
2505 /* We have a PGID with fewer ports now */
2506 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2508 return PTR_ERR(pgid);
2511 ocelot_encode_ports_to_mdb(addr, mc);
2513 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2514 mc->entry_type != ENTRYTYPE_MACv6)
2515 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2518 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2521 EXPORT_SYMBOL(ocelot_port_mdb_del);
2523 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2524 struct net_device *bridge, int bridge_num,
2525 struct netlink_ext_ack *extack)
2527 struct ocelot_port *ocelot_port = ocelot->ports[port];
2530 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
2534 mutex_lock(&ocelot->fwd_domain_lock);
2536 ocelot_port->bridge = bridge;
2537 ocelot_port->bridge_num = bridge_num;
2539 ocelot_apply_bridge_fwd_mask(ocelot, true);
2541 mutex_unlock(&ocelot->fwd_domain_lock);
2543 if (br_vlan_enabled(bridge))
2546 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2548 EXPORT_SYMBOL(ocelot_port_bridge_join);
2550 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2551 struct net_device *bridge)
2553 struct ocelot_port *ocelot_port = ocelot->ports[port];
2555 mutex_lock(&ocelot->fwd_domain_lock);
2557 if (!br_vlan_enabled(bridge))
2558 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2560 ocelot_port->bridge = NULL;
2561 ocelot_port->bridge_num = -1;
2563 ocelot_port_set_pvid(ocelot, port, NULL);
2564 ocelot_port_manage_port_tag(ocelot, port);
2565 ocelot_apply_bridge_fwd_mask(ocelot, false);
2567 mutex_unlock(&ocelot->fwd_domain_lock);
2569 EXPORT_SYMBOL(ocelot_port_bridge_leave);
2571 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2573 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2576 /* Reset destination and aggregation PGIDS */
2577 for_each_unicast_dest_pgid(ocelot, port)
2578 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2580 for_each_aggr_pgid(ocelot, i)
2581 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2584 /* The visited ports bitmask holds the list of ports offloading any
2585 * bonding interface. Initially we mark all these ports as unvisited,
2586 * then every time we visit a port in this bitmask, we know that it is
2587 * the lowest numbered port, i.e. the one whose logical ID == physical
2588 * port ID == LAG ID. So we mark as visited all further ports in the
2589 * bitmask that are offloading the same bonding interface. This way,
2590 * we set up the aggregation PGIDs only once per bonding interface.
2592 for (port = 0; port < ocelot->num_phys_ports; port++) {
2593 struct ocelot_port *ocelot_port = ocelot->ports[port];
2595 if (!ocelot_port || !ocelot_port->bond)
2598 visited &= ~BIT(port);
2601 /* Now, set PGIDs for each active LAG */
2602 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2603 struct net_device *bond = ocelot->ports[lag]->bond;
2604 int num_active_ports = 0;
2605 unsigned long bond_mask;
2608 if (!bond || (visited & BIT(lag)))
2611 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2613 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2614 struct ocelot_port *ocelot_port = ocelot->ports[port];
2617 ocelot_write_rix(ocelot, bond_mask,
2618 ANA_PGID_PGID, port);
2620 if (ocelot_port->lag_tx_active)
2621 aggr_idx[num_active_ports++] = port;
2624 for_each_aggr_pgid(ocelot, i) {
2627 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2629 /* Don't do division by zero if there was no active
2630 * port. Just make all aggregation codes zero.
2632 if (num_active_ports)
2633 ac |= BIT(aggr_idx[i % num_active_ports]);
2634 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2637 /* Mark all ports in the same LAG as visited to avoid applying
2638 * the same config again.
2640 for (port = lag; port < ocelot->num_phys_ports; port++) {
2641 struct ocelot_port *ocelot_port = ocelot->ports[port];
2646 if (ocelot_port->bond == bond)
2647 visited |= BIT(port);
2652 /* When offloading a bonding interface, the switch ports configured under the
2653 * same bond must have the same logical port ID, equal to the physical port ID
2654 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2655 * bridged mode, each port has a logical port ID equal to its physical port ID.
2657 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2661 for (port = 0; port < ocelot->num_phys_ports; port++) {
2662 struct ocelot_port *ocelot_port = ocelot->ports[port];
2663 struct net_device *bond;
2668 bond = ocelot_port->bond;
2670 int lag = ocelot_bond_get_id(ocelot, bond);
2672 ocelot_rmw_gix(ocelot,
2673 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2674 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2675 ANA_PORT_PORT_CFG, port);
2677 ocelot_rmw_gix(ocelot,
2678 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2679 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2680 ANA_PORT_PORT_CFG, port);
2685 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2686 unsigned long from_mask, unsigned long to_mask)
2688 unsigned char addr[ETH_ALEN];
2689 struct ocelot_pgid *pgid;
2692 dev_dbg(ocelot->dev,
2693 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2694 mc->addr, mc->vid, from_mask, to_mask);
2696 /* First clean up the current port mask from hardware, because
2697 * we'll be modifying it.
2699 ocelot_pgid_free(ocelot, mc->pgid);
2700 ocelot_encode_ports_to_mdb(addr, mc);
2701 ocelot_mact_forget(ocelot, addr, vid);
2703 mc->ports &= ~from_mask;
2704 mc->ports |= to_mask;
2706 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2708 dev_err(ocelot->dev,
2709 "Cannot allocate PGID for mdb %pM vid %d\n",
2711 devm_kfree(ocelot->dev, mc);
2712 return PTR_ERR(pgid);
2716 ocelot_encode_ports_to_mdb(addr, mc);
2718 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2719 mc->entry_type != ENTRYTYPE_MACv6)
2720 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2723 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2727 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2728 unsigned long to_mask)
2730 struct ocelot_multicast *mc;
2733 list_for_each_entry(mc, &ocelot->multicast, list) {
2734 if (!(mc->ports & from_mask))
2737 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2744 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2746 /* Documentation for PORTID_VAL says:
2747 * Logical port number for front port. If port is not a member of a LLAG,
2748 * then PORTID must be set to the physical port number.
2749 * If port is a member of a LLAG, then PORTID must be set to the common
2750 * PORTID_VAL used for all member ports of the LLAG.
2751 * The value must not exceed the number of physical ports on the device.
2753 * This means we have little choice but to migrate FDB entries pointing towards
2754 * a logical port when that changes.
2756 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2757 struct net_device *bond,
2760 struct ocelot_lag_fdb *fdb;
2763 lockdep_assert_held(&ocelot->fwd_domain_lock);
2765 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2766 if (fdb->bond != bond)
2769 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2771 dev_err(ocelot->dev,
2772 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2773 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2776 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2779 dev_err(ocelot->dev,
2780 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2781 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2786 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2787 struct net_device *bond,
2788 struct netdev_lag_upper_info *info)
2790 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2793 mutex_lock(&ocelot->fwd_domain_lock);
2795 ocelot->ports[port]->bond = bond;
2797 ocelot_setup_logical_port_ids(ocelot);
2798 ocelot_apply_bridge_fwd_mask(ocelot, true);
2799 ocelot_set_aggr_pgids(ocelot);
2801 mutex_unlock(&ocelot->fwd_domain_lock);
2805 EXPORT_SYMBOL(ocelot_port_lag_join);
2807 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2808 struct net_device *bond)
2810 int old_lag_id, new_lag_id;
2812 mutex_lock(&ocelot->fwd_domain_lock);
2814 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2816 ocelot->ports[port]->bond = NULL;
2818 ocelot_setup_logical_port_ids(ocelot);
2819 ocelot_apply_bridge_fwd_mask(ocelot, false);
2820 ocelot_set_aggr_pgids(ocelot);
2822 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2824 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2825 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2827 mutex_unlock(&ocelot->fwd_domain_lock);
2829 EXPORT_SYMBOL(ocelot_port_lag_leave);
2831 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2833 struct ocelot_port *ocelot_port = ocelot->ports[port];
2835 mutex_lock(&ocelot->fwd_domain_lock);
2837 ocelot_port->lag_tx_active = lag_tx_active;
2839 /* Rebalance the LAGs */
2840 ocelot_set_aggr_pgids(ocelot);
2842 mutex_unlock(&ocelot->fwd_domain_lock);
2844 EXPORT_SYMBOL(ocelot_port_lag_change);
2846 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2847 const unsigned char *addr, u16 vid,
2848 const struct net_device *bridge)
2850 struct ocelot_lag_fdb *fdb;
2853 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2857 mutex_lock(&ocelot->fwd_domain_lock);
2860 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2862 ether_addr_copy(fdb->addr, addr);
2866 lag = ocelot_bond_get_id(ocelot, bond);
2868 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2870 mutex_unlock(&ocelot->fwd_domain_lock);
2875 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2876 mutex_unlock(&ocelot->fwd_domain_lock);
2880 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2882 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2883 const unsigned char *addr, u16 vid,
2884 const struct net_device *bridge)
2886 struct ocelot_lag_fdb *fdb, *tmp;
2888 mutex_lock(&ocelot->fwd_domain_lock);
2891 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2893 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2894 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2898 ocelot_mact_forget(ocelot, addr, vid);
2899 list_del(&fdb->list);
2900 mutex_unlock(&ocelot->fwd_domain_lock);
2906 mutex_unlock(&ocelot->fwd_domain_lock);
2910 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2912 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2913 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2914 * In the special case that it's the NPI port that we're configuring, the
2915 * length of the tag and optional prefix needs to be accounted for privately,
2916 * in order to be able to sustain communication at the requested @sdu.
2918 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2920 struct ocelot_port *ocelot_port = ocelot->ports[port];
2921 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2922 int pause_start, pause_stop;
2925 if (port == ocelot->npi) {
2926 maxlen += OCELOT_TAG_LEN;
2928 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2929 maxlen += OCELOT_SHORT_PREFIX_LEN;
2930 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2931 maxlen += OCELOT_LONG_PREFIX_LEN;
2934 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2936 /* Set Pause watermark hysteresis */
2937 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2938 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2939 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2941 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2944 /* Tail dropping watermarks */
2945 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2946 OCELOT_BUFFER_CELL_SZ;
2947 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2948 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2949 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2951 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2953 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2955 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2957 if (port == ocelot->npi) {
2958 max_mtu -= OCELOT_TAG_LEN;
2960 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2961 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2962 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2963 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2968 EXPORT_SYMBOL(ocelot_get_max_mtu);
2970 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2973 struct ocelot_port *ocelot_port = ocelot->ports[port];
2977 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2979 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2980 ANA_PORT_PORT_CFG, port);
2982 ocelot_port->learn_ena = enabled;
2985 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2993 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2996 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
3004 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
3005 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
3006 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
3009 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
3017 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
3020 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
3021 struct switchdev_brport_flags flags)
3023 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3029 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
3031 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
3032 struct switchdev_brport_flags flags)
3034 if (flags.mask & BR_LEARNING)
3035 ocelot_port_set_learning(ocelot, port,
3036 !!(flags.val & BR_LEARNING));
3038 if (flags.mask & BR_FLOOD)
3039 ocelot_port_set_ucast_flood(ocelot, port,
3040 !!(flags.val & BR_FLOOD));
3042 if (flags.mask & BR_MCAST_FLOOD)
3043 ocelot_port_set_mcast_flood(ocelot, port,
3044 !!(flags.val & BR_MCAST_FLOOD));
3046 if (flags.mask & BR_BCAST_FLOOD)
3047 ocelot_port_set_bcast_flood(ocelot, port,
3048 !!(flags.val & BR_BCAST_FLOOD));
3050 EXPORT_SYMBOL(ocelot_port_bridge_flags);
3052 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
3054 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
3056 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
3058 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
3060 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
3062 if (prio >= OCELOT_NUM_TC)
3065 ocelot_rmw_gix(ocelot,
3066 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
3067 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
3073 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
3075 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
3077 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
3078 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
3080 /* Return error if DSCP prioritization isn't enabled */
3081 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
3084 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
3085 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
3086 /* Re-read ANA_DSCP_CFG for the translated DSCP */
3087 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
3090 /* If the DSCP value is not trusted, the QoS classification falls back
3091 * to VLAN PCP or port-based default.
3093 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
3096 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
3098 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
3100 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
3104 if (prio >= OCELOT_NUM_TC)
3107 /* There is at least one app table priority (this one), so we need to
3108 * make sure DSCP prioritization is enabled on the port.
3109 * Also make sure DSCP translation is disabled
3110 * (dcbnl doesn't support it).
3112 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
3113 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
3115 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
3116 ANA_PORT_QOS_CFG, port);
3118 /* Trust this DSCP value and map it to the given QoS class */
3119 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
3121 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
3125 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
3127 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
3129 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
3132 /* During a "dcb app replace" command, the new app table entry will be
3133 * added first, then the old one will be deleted. But the hardware only
3134 * supports one QoS class per DSCP value (duh), so if we blindly delete
3135 * the app table entry for this DSCP value, we end up deleting the
3136 * entry with the new priority. Avoid that by checking whether user
3137 * space wants to delete the priority which is currently configured, or
3138 * something else which is no longer current.
3140 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
3143 /* Untrust this DSCP value */
3144 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
3146 for (i = 0; i < 64; i++) {
3147 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
3149 /* There are still app table entries on the port, so we need to
3150 * keep DSCP enabled, nothing to do.
3152 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
3156 /* Disable DSCP QoS classification if there isn't any trusted
3159 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
3160 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
3162 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
3166 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
3168 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
3169 struct netlink_ext_ack *extack)
3171 struct ocelot_mirror *m = ocelot->mirror;
3175 NL_SET_ERR_MSG_MOD(extack,
3176 "Mirroring already configured towards different egress port");
3177 return ERR_PTR(-EBUSY);
3180 refcount_inc(&m->refcount);
3184 m = kzalloc(sizeof(*m), GFP_KERNEL);
3186 return ERR_PTR(-ENOMEM);
3189 refcount_set(&m->refcount, 1);
3192 /* Program the mirror port to hardware */
3193 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
3198 void ocelot_mirror_put(struct ocelot *ocelot)
3200 struct ocelot_mirror *m = ocelot->mirror;
3202 if (!refcount_dec_and_test(&m->refcount))
3205 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
3206 ocelot->mirror = NULL;
3210 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
3211 bool ingress, struct netlink_ext_ack *extack)
3213 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
3219 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
3220 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
3221 ANA_PORT_PORT_CFG, from);
3223 ocelot_rmw(ocelot, BIT(from), BIT(from),
3229 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
3231 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
3234 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
3235 ANA_PORT_PORT_CFG, from);
3237 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
3240 ocelot_mirror_put(ocelot);
3242 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
3244 void ocelot_init_port(struct ocelot *ocelot, int port)
3246 struct ocelot_port *ocelot_port = ocelot->ports[port];
3248 skb_queue_head_init(&ocelot_port->tx_skbs);
3250 /* Basic L2 initialization */
3253 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
3254 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
3256 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
3259 /* Load seed (0) and set MAC HDX late collision */
3260 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
3261 DEV_MAC_HDX_CFG_SEED_LOAD,
3264 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
3267 /* Set Max Length and maximum tags allowed */
3268 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
3269 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
3270 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
3271 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
3272 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
3275 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
3276 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
3277 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
3279 /* Enable transmission of pause frames */
3280 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
3282 /* Drop frames with multicast source address */
3283 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3284 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3285 ANA_PORT_DROP_CFG, port);
3287 /* Set default VLAN and tag type to 8021Q. */
3288 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
3289 REW_PORT_VLAN_CFG_PORT_TPID_M,
3290 REW_PORT_VLAN_CFG, port);
3292 /* Disable source address learning for standalone mode */
3293 ocelot_port_set_learning(ocelot, port, false);
3295 /* Set the port's initial logical port ID value, enable receiving
3296 * frames on it, and configure the MAC address learning type to
3299 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
3300 ANA_PORT_PORT_CFG_RECV_ENA |
3301 ANA_PORT_PORT_CFG_PORTID_VAL(port),
3302 ANA_PORT_PORT_CFG, port);
3304 /* Enable vcap lookups */
3305 ocelot_vcap_enable(ocelot, port);
3307 EXPORT_SYMBOL(ocelot_init_port);
3309 /* Configure and enable the CPU port module, which is a set of queues
3310 * accessible through register MMIO, frame DMA or Ethernet (in case
3311 * NPI mode is used).
3313 static void ocelot_cpu_port_init(struct ocelot *ocelot)
3315 int cpu = ocelot->num_phys_ports;
3317 /* The unicast destination PGID for the CPU port module is unused */
3318 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
3319 /* Instead set up a multicast destination PGID for traffic copied to
3320 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
3321 * addresses will be copied to the CPU via this PGID.
3323 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
3324 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
3325 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
3326 ANA_PORT_PORT_CFG, cpu);
3328 /* Enable CPU port module */
3329 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
3330 /* CPU port Injection/Extraction configuration */
3331 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
3332 OCELOT_TAG_PREFIX_NONE);
3333 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
3334 OCELOT_TAG_PREFIX_NONE);
3336 /* Configure the CPU port to be VLAN aware */
3337 ocelot_write_gix(ocelot,
3338 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
3339 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
3340 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
3341 ANA_PORT_VLAN_CFG, cpu);
3344 static void ocelot_detect_features(struct ocelot *ocelot)
3348 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
3349 * the number of 240-byte free memory words (aka 4-cell chunks) and not
3350 * 192 bytes as the documentation incorrectly says.
3352 mmgt = ocelot_read(ocelot, SYS_MMGT);
3353 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
3355 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
3356 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
3359 int ocelot_init(struct ocelot *ocelot)
3361 char queue_name[32];
3365 if (ocelot->ops->reset) {
3366 ret = ocelot->ops->reset(ocelot);
3368 dev_err(ocelot->dev, "Switch reset failed\n");
3373 ocelot->stats = devm_kcalloc(ocelot->dev,
3374 ocelot->num_phys_ports * OCELOT_NUM_STATS,
3375 sizeof(u64), GFP_KERNEL);
3379 spin_lock_init(&ocelot->stats_lock);
3380 mutex_init(&ocelot->ptp_lock);
3381 mutex_init(&ocelot->mact_lock);
3382 mutex_init(&ocelot->fwd_domain_lock);
3383 mutex_init(&ocelot->tas_lock);
3384 spin_lock_init(&ocelot->ptp_clock_lock);
3385 spin_lock_init(&ocelot->ts_id_lock);
3386 snprintf(queue_name, sizeof(queue_name), "%s-stats",
3387 dev_name(ocelot->dev));
3388 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
3389 if (!ocelot->stats_queue)
3392 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
3394 destroy_workqueue(ocelot->stats_queue);
3398 INIT_LIST_HEAD(&ocelot->multicast);
3399 INIT_LIST_HEAD(&ocelot->pgids);
3400 INIT_LIST_HEAD(&ocelot->vlans);
3401 INIT_LIST_HEAD(&ocelot->lag_fdbs);
3402 ocelot_detect_features(ocelot);
3403 ocelot_mact_init(ocelot);
3404 ocelot_vlan_init(ocelot);
3405 ocelot_vcap_init(ocelot);
3406 ocelot_cpu_port_init(ocelot);
3408 if (ocelot->ops->psfp_init)
3409 ocelot->ops->psfp_init(ocelot);
3411 for (port = 0; port < ocelot->num_phys_ports; port++) {
3412 /* Clear all counters (5 groups) */
3413 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
3414 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
3418 /* Only use S-Tag */
3419 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
3421 /* Aggregation mode */
3422 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
3423 ANA_AGGR_CFG_AC_DMAC_ENA |
3424 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
3425 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
3426 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
3427 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
3430 /* Set MAC age time to default value. The entry is aged after
3433 ocelot_write(ocelot,
3434 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
3437 /* Disable learning for frames discarded by VLAN ingress filtering */
3438 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
3440 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
3441 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
3442 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
3444 /* Setup flooding PGIDs */
3445 for (i = 0; i < ocelot->num_flooding_pgids; i++)
3446 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
3447 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
3448 ANA_FLOODING_FLD_UNICAST(PGID_UC),
3450 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3451 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
3452 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
3453 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
3456 for (port = 0; port < ocelot->num_phys_ports; port++) {
3457 /* Transmit the frame to the local port. */
3458 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3459 /* Do not forward BPDU frames to the front ports. */
3460 ocelot_write_gix(ocelot,
3461 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
3462 ANA_PORT_CPU_FWD_BPDU_CFG,
3464 /* Ensure bridging is disabled */
3465 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3468 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3469 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3471 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3474 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3476 /* Allow broadcast and unknown L2 multicast to the CPU. */
3477 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3478 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3479 ANA_PGID_PGID, PGID_MC);
3480 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3481 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3482 ANA_PGID_PGID, PGID_BC);
3483 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3484 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3486 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
3487 * registers endianness.
3489 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3490 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
3491 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3492 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
3493 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3494 ANA_CPUQ_CFG_CPUQ_LRN(2) |
3495 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
3496 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
3497 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
3498 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
3499 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
3500 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
3501 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
3502 for (i = 0; i < 16; i++)
3503 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3504 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
3505 ANA_CPUQ_8021_CFG, i);
3507 ret = ocelot_prepare_stats_regions(ocelot);
3509 destroy_workqueue(ocelot->stats_queue);
3510 destroy_workqueue(ocelot->owq);
3514 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
3515 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
3516 OCELOT_STATS_CHECK_DELAY);
3520 EXPORT_SYMBOL(ocelot_init);
3522 void ocelot_deinit(struct ocelot *ocelot)
3524 cancel_delayed_work(&ocelot->stats_work);
3525 destroy_workqueue(ocelot->stats_queue);
3526 destroy_workqueue(ocelot->owq);
3528 EXPORT_SYMBOL(ocelot_deinit);
3530 void ocelot_deinit_port(struct ocelot *ocelot, int port)
3532 struct ocelot_port *ocelot_port = ocelot->ports[port];
3534 skb_queue_purge(&ocelot_port->tx_skbs);
3536 EXPORT_SYMBOL(ocelot_deinit_port);
3538 MODULE_LICENSE("Dual MIT/GPL");