1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/etherdevice.h>
8 #include <linux/ethtool.h>
9 #include <linux/if_bridge.h>
10 #include <linux/if_ether.h>
11 #include <linux/if_vlan.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
17 #include <linux/skbuff.h>
18 #include <linux/iopoll.h>
20 #include <net/netevent.h>
21 #include <net/rtnetlink.h>
22 #include <net/switchdev.h>
25 #include "ocelot_ace.h"
27 #define TABLE_UPDATE_SLEEP_US 10
28 #define TABLE_UPDATE_TIMEOUT_US 100000
30 /* MAC table entry types.
31 * ENTRYTYPE_NORMAL is subject to aging.
32 * ENTRYTYPE_LOCKED is not subject to aging.
33 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
34 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
36 enum macaccess_entry_type {
43 struct ocelot_mact_entry {
46 enum macaccess_entry_type type;
49 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
51 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
54 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
58 return readx_poll_timeout(ocelot_mact_read_macaccess,
60 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
62 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
65 static void ocelot_mact_select(struct ocelot *ocelot,
66 const unsigned char mac[ETH_ALEN],
69 u32 macl = 0, mach = 0;
71 /* Set the MAC address to handle and the vlan associated in a format
72 * understood by the hardware.
82 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
83 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
87 static int ocelot_mact_learn(struct ocelot *ocelot, int port,
88 const unsigned char mac[ETH_ALEN],
90 enum macaccess_entry_type type)
92 ocelot_mact_select(ocelot, mac, vid);
94 /* Issue a write command */
95 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
96 ANA_TABLES_MACACCESS_DEST_IDX(port) |
97 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
99 ANA_TABLES_MACACCESS);
101 return ocelot_mact_wait_for_completion(ocelot);
104 static int ocelot_mact_forget(struct ocelot *ocelot,
105 const unsigned char mac[ETH_ALEN],
108 ocelot_mact_select(ocelot, mac, vid);
110 /* Issue a forget command */
112 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
113 ANA_TABLES_MACACCESS);
115 return ocelot_mact_wait_for_completion(ocelot);
118 static void ocelot_mact_init(struct ocelot *ocelot)
120 /* Configure the learning mode entries attributes:
121 * - Do not copy the frame to the CPU extraction queues.
122 * - Use the vlan and mac_cpoy for dmac lookup.
124 ocelot_rmw(ocelot, 0,
125 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
126 | ANA_AGENCTRL_LEARN_FWD_KILL
127 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
130 /* Clear the MAC table */
131 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
134 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
136 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
137 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
138 ANA_PORT_VCAP_S2_CFG, port);
141 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
143 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
146 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
150 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
153 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
154 ANA_TABLES_VLANACCESS_CMD_IDLE,
155 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
158 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
160 /* Select the VID to configure */
161 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
162 ANA_TABLES_VLANTIDX);
163 /* Set the vlan port members mask and issue a write command */
164 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
165 ANA_TABLES_VLANACCESS_CMD_WRITE,
166 ANA_TABLES_VLANACCESS);
168 return ocelot_vlant_wait_for_completion(ocelot);
171 static void ocelot_vlan_mode(struct ocelot *ocelot, int port,
172 netdev_features_t features)
177 val = ocelot_read(ocelot, ANA_VLANMASK);
178 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
182 ocelot_write(ocelot, val, ANA_VLANMASK);
185 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
188 struct ocelot_port *ocelot_port = ocelot->ports[port];
191 if (ocelot_port->vid != vid) {
192 /* Always permit deleting the native VLAN (vid = 0) */
193 if (ocelot_port->vid && vid) {
195 "Port already has a native VLAN: %d\n",
199 ocelot_port->vid = vid;
202 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid),
203 REW_PORT_VLAN_CFG_PORT_VID_M,
204 REW_PORT_VLAN_CFG, port);
206 if (ocelot_port->vlan_aware && !ocelot_port->vid)
207 /* If port is vlan-aware and tagged, drop untagged and priority
210 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
211 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
212 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
213 ocelot_rmw_gix(ocelot, val,
214 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA |
215 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
216 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
217 ANA_PORT_DROP_CFG, port);
219 if (ocelot_port->vlan_aware) {
220 if (ocelot_port->vid)
221 /* Tag all frames except when VID == DEFAULT_VLAN */
222 val = REW_TAG_CFG_TAG_CFG(1);
225 val = REW_TAG_CFG_TAG_CFG(3);
227 /* Port tagging disabled. */
228 val = REW_TAG_CFG_TAG_CFG(0);
230 ocelot_rmw_gix(ocelot, val,
231 REW_TAG_CFG_TAG_CFG_M,
237 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
240 struct ocelot_port *ocelot_port = ocelot->ports[port];
243 ocelot_port->vlan_aware = vlan_aware;
246 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
247 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
250 ocelot_rmw_gix(ocelot, val,
251 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
252 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
253 ANA_PORT_VLAN_CFG, port);
255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid);
257 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
259 /* Default vlan to clasify for untagged frames (may be zero) */
260 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid)
262 struct ocelot_port *ocelot_port = ocelot->ports[port];
264 ocelot_rmw_gix(ocelot,
265 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
266 ANA_PORT_VLAN_CFG_VLAN_VID_M,
267 ANA_PORT_VLAN_CFG, port);
269 ocelot_port->pvid = pvid;
272 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
277 /* Make the port a member of the VLAN */
278 ocelot->vlan_mask[vid] |= BIT(port);
279 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
283 /* Default ingress vlan classification */
285 ocelot_port_set_pvid(ocelot, port, vid);
287 /* Untagged egress vlan clasification */
289 ret = ocelot_port_set_native_vlan(ocelot, port, vid);
296 EXPORT_SYMBOL(ocelot_vlan_add);
298 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
301 struct ocelot_port_private *priv = netdev_priv(dev);
302 struct ocelot_port *ocelot_port = &priv->port;
303 struct ocelot *ocelot = ocelot_port->ocelot;
304 int port = priv->chip_port;
307 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged);
311 /* Add the port MAC address to with the right VLAN information */
312 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid,
318 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
320 struct ocelot_port *ocelot_port = ocelot->ports[port];
323 /* Stop the port from being a member of the vlan */
324 ocelot->vlan_mask[vid] &= ~BIT(port);
325 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
330 if (ocelot_port->pvid == vid)
331 ocelot_port_set_pvid(ocelot, port, 0);
334 if (ocelot_port->vid == vid)
335 ocelot_port_set_native_vlan(ocelot, port, 0);
339 EXPORT_SYMBOL(ocelot_vlan_del);
341 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
343 struct ocelot_port_private *priv = netdev_priv(dev);
344 struct ocelot *ocelot = priv->port.ocelot;
345 int port = priv->chip_port;
348 /* 8021q removes VID 0 on module unload for all interfaces
349 * with VLAN filtering feature. We need to keep it to receive
355 ret = ocelot_vlan_del(ocelot, port, vid);
359 /* Del the port MAC address to with the right VLAN information */
360 ocelot_mact_forget(ocelot, dev->dev_addr, vid);
365 static void ocelot_vlan_init(struct ocelot *ocelot)
369 /* Clear VLAN table, by default all ports are members of all VLANs */
370 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
371 ANA_TABLES_VLANACCESS);
372 ocelot_vlant_wait_for_completion(ocelot);
374 /* Configure the port VLAN memberships */
375 for (vid = 1; vid < VLAN_N_VID; vid++) {
376 ocelot->vlan_mask[vid] = 0;
377 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]);
380 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
381 * traffic. It is added automatically if 8021q module is loaded, but
382 * we can't rely on it since module may be not loaded.
384 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0);
385 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]);
387 /* Set vlan ingress filter mask to all ports but the CPU port by
390 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
393 for (port = 0; port < ocelot->num_phys_ports; port++) {
394 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
395 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
400 * Bit 8: Unit; 0:1, 1:16
401 * Bit 7-0: Value to be multiplied with unit
403 static u16 ocelot_wm_enc(u16 value)
406 return BIT(8) | (value / 16);
411 void ocelot_adjust_link(struct ocelot *ocelot, int port,
412 struct phy_device *phydev)
414 struct ocelot_port *ocelot_port = ocelot->ports[port];
417 switch (phydev->speed) {
419 speed = OCELOT_SPEED_10;
422 speed = OCELOT_SPEED_100;
425 speed = OCELOT_SPEED_1000;
426 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
429 speed = OCELOT_SPEED_2500;
430 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
433 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
434 port, phydev->speed);
438 phy_print_status(phydev);
443 /* Only full duplex supported for now */
444 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
445 mode, DEV_MAC_MODE_CFG);
447 /* Disable HDX fast control */
448 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
451 /* SGMII only for now */
452 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
454 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
457 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
459 /* No aneg on SGMII */
460 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
463 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
465 /* Enable MAC module */
466 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
467 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
469 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
471 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
475 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
476 ANA_PFC_PFC_CFG, port);
478 /* Core: Enable port for frame transfer */
479 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
480 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
481 QSYS_SWITCH_PORT_MODE_PORT_ENA,
482 QSYS_SWITCH_PORT_MODE, port);
485 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
486 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
487 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
488 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
489 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
490 SYS_MAC_FC_CFG, port);
491 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
493 EXPORT_SYMBOL(ocelot_adjust_link);
495 static void ocelot_port_adjust_link(struct net_device *dev)
497 struct ocelot_port_private *priv = netdev_priv(dev);
498 struct ocelot *ocelot = priv->port.ocelot;
499 int port = priv->chip_port;
501 ocelot_adjust_link(ocelot, port, dev->phydev);
504 void ocelot_port_enable(struct ocelot *ocelot, int port,
505 struct phy_device *phy)
507 /* Enable receiving frames on the port, and activate auto-learning of
510 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
511 ANA_PORT_PORT_CFG_RECV_ENA |
512 ANA_PORT_PORT_CFG_PORTID_VAL(port),
513 ANA_PORT_PORT_CFG, port);
515 EXPORT_SYMBOL(ocelot_port_enable);
517 static int ocelot_port_open(struct net_device *dev)
519 struct ocelot_port_private *priv = netdev_priv(dev);
520 struct ocelot_port *ocelot_port = &priv->port;
521 struct ocelot *ocelot = ocelot_port->ocelot;
522 int port = priv->chip_port;
526 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET,
527 ocelot_port->phy_mode);
529 netdev_err(dev, "Could not set mode of SerDes\n");
534 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link,
535 ocelot_port->phy_mode);
537 netdev_err(dev, "Could not attach to PHY\n");
541 dev->phydev = priv->phy;
543 phy_attached_info(priv->phy);
544 phy_start(priv->phy);
546 ocelot_port_enable(ocelot, port, priv->phy);
551 void ocelot_port_disable(struct ocelot *ocelot, int port)
553 struct ocelot_port *ocelot_port = ocelot->ports[port];
555 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
556 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
557 QSYS_SWITCH_PORT_MODE, port);
559 EXPORT_SYMBOL(ocelot_port_disable);
561 static int ocelot_port_stop(struct net_device *dev)
563 struct ocelot_port_private *priv = netdev_priv(dev);
564 struct ocelot *ocelot = priv->port.ocelot;
565 int port = priv->chip_port;
567 phy_disconnect(priv->phy);
571 ocelot_port_disable(ocelot, port);
576 /* Generate the IFH for frame injection
578 * The IFH is a 128bit-value
579 * bit 127: bypass the analyzer processing
580 * bit 56-67: destination mask
581 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
582 * bit 20-27: cpu extraction queue mask
583 * bit 16: tag type 0: C-tag, 1: S-tag
586 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info)
588 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21);
589 ifh[1] = (0xf00 & info->port) >> 8;
590 ifh[2] = (0xff & info->port) << 24;
591 ifh[3] = (info->tag_type << 16) | info->vid;
596 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
599 struct skb_shared_info *shinfo = skb_shinfo(skb);
600 struct ocelot *ocelot = ocelot_port->ocelot;
602 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP &&
603 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
604 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
605 /* Store timestamp ID in cb[0] of sk_buff */
606 skb->cb[0] = ocelot_port->ts_id % 4;
607 skb_queue_tail(&ocelot_port->tx_skbs, skb);
612 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb);
614 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev)
616 struct ocelot_port_private *priv = netdev_priv(dev);
617 struct skb_shared_info *shinfo = skb_shinfo(skb);
618 struct ocelot_port *ocelot_port = &priv->port;
619 struct ocelot *ocelot = ocelot_port->ocelot;
620 u32 val, ifh[OCELOT_TAG_LEN / 4];
621 struct frame_info info = {};
622 u8 grp = 0; /* Send everything on CPU group 0 */
623 unsigned int i, count, last;
624 int port = priv->chip_port;
626 val = ocelot_read(ocelot, QS_INJ_STATUS);
627 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) ||
628 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))))
629 return NETDEV_TX_BUSY;
631 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
632 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
634 info.port = BIT(port);
635 info.tag_type = IFH_TAG_TYPE_C;
636 info.vid = skb_vlan_tag_get(skb);
638 /* Check if timestamping is needed */
639 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) {
640 info.rew_op = ocelot_port->ptp_cmd;
641 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP)
642 info.rew_op |= (ocelot_port->ts_id % 4) << 3;
645 ocelot_gen_ifh(ifh, &info);
647 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
648 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]),
651 count = (skb->len + 3) / 4;
653 for (i = 0; i < count; i++) {
654 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
658 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
659 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
663 /* Indicate EOF and valid bytes in last word */
664 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
665 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
670 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
671 skb_tx_timestamp(skb);
673 dev->stats.tx_packets++;
674 dev->stats.tx_bytes += skb->len;
676 if (!ocelot_port_add_txtstamp_skb(ocelot_port, skb)) {
677 ocelot_port->ts_id++;
681 dev_kfree_skb_any(skb);
685 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
686 struct timespec64 *ts)
691 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
693 /* Read current PTP time to get seconds */
694 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
696 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
697 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
698 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
699 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
701 /* Read packet HW timestamp from FIFO */
702 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
703 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
705 /* Sec has incremented since the ts was registered */
706 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
709 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
712 void ocelot_get_txtstamp(struct ocelot *ocelot)
714 int budget = OCELOT_PTP_QUEUE_SZ;
717 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
718 struct skb_shared_hwtstamps shhwtstamps;
719 struct ocelot_port *port;
720 struct timespec64 ts;
724 val = ocelot_read(ocelot, SYS_PTP_STATUS);
726 /* Check if a timestamp can be retrieved */
727 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
730 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
732 /* Retrieve the ts ID and Tx port */
733 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
734 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
736 /* Retrieve its associated skb */
737 port = ocelot->ports[txport];
739 spin_lock_irqsave(&port->tx_skbs.lock, flags);
741 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
742 if (skb->cb[0] != id)
744 __skb_unlink(skb, &port->tx_skbs);
749 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
752 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
754 if (unlikely(!skb_match))
757 /* Get the h/w timestamp */
758 ocelot_get_hwtimestamp(ocelot, &ts);
760 /* Set the timestamp into the skb */
761 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
762 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
763 skb_tstamp_tx(skb_match, &shhwtstamps);
765 dev_kfree_skb_any(skb_match);
768 EXPORT_SYMBOL(ocelot_get_txtstamp);
770 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr)
772 struct ocelot_port_private *priv = netdev_priv(dev);
773 struct ocelot_port *ocelot_port = &priv->port;
774 struct ocelot *ocelot = ocelot_port->ocelot;
776 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid);
779 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr)
781 struct ocelot_port_private *priv = netdev_priv(dev);
782 struct ocelot_port *ocelot_port = &priv->port;
783 struct ocelot *ocelot = ocelot_port->ocelot;
785 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid,
789 static void ocelot_set_rx_mode(struct net_device *dev)
791 struct ocelot_port_private *priv = netdev_priv(dev);
792 struct ocelot *ocelot = priv->port.ocelot;
796 /* This doesn't handle promiscuous mode because the bridge core is
797 * setting IFF_PROMISC on all slave interfaces and all frames would be
798 * forwarded to the CPU port.
800 val = GENMASK(ocelot->num_phys_ports - 1, 0);
801 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++)
802 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
804 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync);
807 static int ocelot_port_get_phys_port_name(struct net_device *dev,
808 char *buf, size_t len)
810 struct ocelot_port_private *priv = netdev_priv(dev);
811 int port = priv->chip_port;
814 ret = snprintf(buf, len, "p%d", port);
821 static int ocelot_port_set_mac_address(struct net_device *dev, void *p)
823 struct ocelot_port_private *priv = netdev_priv(dev);
824 struct ocelot_port *ocelot_port = &priv->port;
825 struct ocelot *ocelot = ocelot_port->ocelot;
826 const struct sockaddr *addr = p;
828 /* Learn the new net device MAC address in the mac table. */
829 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid,
831 /* Then forget the previous one. */
832 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid);
834 ether_addr_copy(dev->dev_addr, addr->sa_data);
838 static void ocelot_get_stats64(struct net_device *dev,
839 struct rtnl_link_stats64 *stats)
841 struct ocelot_port_private *priv = netdev_priv(dev);
842 struct ocelot *ocelot = priv->port.ocelot;
843 int port = priv->chip_port;
845 /* Configure the port to read the stats from */
846 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port),
850 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS);
851 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) +
852 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) +
853 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) +
854 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) +
855 ocelot_read(ocelot, SYS_COUNT_RX_64) +
856 ocelot_read(ocelot, SYS_COUNT_RX_65_127) +
857 ocelot_read(ocelot, SYS_COUNT_RX_128_255) +
858 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) +
859 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) +
860 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX);
861 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST);
862 stats->rx_dropped = dev->stats.rx_dropped;
865 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS);
866 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) +
867 ocelot_read(ocelot, SYS_COUNT_TX_65_127) +
868 ocelot_read(ocelot, SYS_COUNT_TX_128_511) +
869 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) +
870 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) +
871 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX);
872 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) +
873 ocelot_read(ocelot, SYS_COUNT_TX_AGING);
874 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
877 int ocelot_fdb_add(struct ocelot *ocelot, int port,
878 const unsigned char *addr, u16 vid)
880 struct ocelot_port *ocelot_port = ocelot->ports[port];
883 if (!ocelot_port->vlan_aware)
884 /* If the bridge is not VLAN aware and no VID was
885 * provided, set it to pvid to ensure the MAC entry
886 * matches incoming untagged packets
888 vid = ocelot_port->pvid;
890 /* If the bridge is VLAN aware a VID must be provided as
891 * otherwise the learnt entry wouldn't match any frame.
896 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
898 EXPORT_SYMBOL(ocelot_fdb_add);
900 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
901 struct net_device *dev,
902 const unsigned char *addr,
904 struct netlink_ext_ack *extack)
906 struct ocelot_port_private *priv = netdev_priv(dev);
907 struct ocelot *ocelot = priv->port.ocelot;
908 int port = priv->chip_port;
910 return ocelot_fdb_add(ocelot, port, addr, vid);
913 int ocelot_fdb_del(struct ocelot *ocelot, int port,
914 const unsigned char *addr, u16 vid)
916 return ocelot_mact_forget(ocelot, addr, vid);
918 EXPORT_SYMBOL(ocelot_fdb_del);
920 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
921 struct net_device *dev,
922 const unsigned char *addr, u16 vid)
924 struct ocelot_port_private *priv = netdev_priv(dev);
925 struct ocelot *ocelot = priv->port.ocelot;
926 int port = priv->chip_port;
928 return ocelot_fdb_del(ocelot, port, addr, vid);
931 struct ocelot_dump_ctx {
932 struct net_device *dev;
934 struct netlink_callback *cb;
938 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
939 bool is_static, void *data)
941 struct ocelot_dump_ctx *dump = data;
942 u32 portid = NETLINK_CB(dump->cb->skb).portid;
943 u32 seq = dump->cb->nlh->nlmsg_seq;
944 struct nlmsghdr *nlh;
947 if (dump->idx < dump->cb->args[2])
950 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
951 sizeof(*ndm), NLM_F_MULTI);
955 ndm = nlmsg_data(nlh);
956 ndm->ndm_family = AF_BRIDGE;
959 ndm->ndm_flags = NTF_SELF;
961 ndm->ndm_ifindex = dump->dev->ifindex;
962 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
964 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
965 goto nla_put_failure;
967 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
968 goto nla_put_failure;
970 nlmsg_end(dump->skb, nlh);
977 nlmsg_cancel(dump->skb, nlh);
981 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
982 struct ocelot_mact_entry *entry)
984 u32 val, dst, macl, mach;
987 /* Set row and column to read from */
988 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
989 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
991 /* Issue a read command */
993 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
994 ANA_TABLES_MACACCESS);
996 if (ocelot_mact_wait_for_completion(ocelot))
999 /* Read the entry flags */
1000 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1001 if (!(val & ANA_TABLES_MACACCESS_VALID))
1004 /* If the entry read has another port configured as its destination,
1007 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1011 /* Get the entry's MAC address and VLAN id */
1012 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1013 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1015 mac[0] = (mach >> 8) & 0xff;
1016 mac[1] = (mach >> 0) & 0xff;
1017 mac[2] = (macl >> 24) & 0xff;
1018 mac[3] = (macl >> 16) & 0xff;
1019 mac[4] = (macl >> 8) & 0xff;
1020 mac[5] = (macl >> 0) & 0xff;
1022 entry->vid = (mach >> 16) & 0xfff;
1023 ether_addr_copy(entry->mac, mac);
1028 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1029 dsa_fdb_dump_cb_t *cb, void *data)
1033 /* Loop through all the mac tables entries. */
1034 for (i = 0; i < ocelot->num_mact_rows; i++) {
1035 for (j = 0; j < 4; j++) {
1036 struct ocelot_mact_entry entry;
1040 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
1041 /* If the entry is invalid (wrong port, invalid...),
1049 is_static = (entry.type == ENTRYTYPE_LOCKED);
1051 ret = cb(entry.mac, entry.vid, is_static, data);
1059 EXPORT_SYMBOL(ocelot_fdb_dump);
1061 static int ocelot_port_fdb_dump(struct sk_buff *skb,
1062 struct netlink_callback *cb,
1063 struct net_device *dev,
1064 struct net_device *filter_dev, int *idx)
1066 struct ocelot_port_private *priv = netdev_priv(dev);
1067 struct ocelot *ocelot = priv->port.ocelot;
1068 struct ocelot_dump_ctx dump = {
1074 int port = priv->chip_port;
1077 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump);
1084 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
1087 return ocelot_vlan_vid_add(dev, vid, false, false);
1090 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
1093 return ocelot_vlan_vid_del(dev, vid);
1096 static int ocelot_set_features(struct net_device *dev,
1097 netdev_features_t features)
1099 netdev_features_t changed = dev->features ^ features;
1100 struct ocelot_port_private *priv = netdev_priv(dev);
1101 struct ocelot *ocelot = priv->port.ocelot;
1102 int port = priv->chip_port;
1104 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
1105 priv->tc.offload_cnt) {
1107 "Cannot disable HW TC offload while offloads active\n");
1111 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER)
1112 ocelot_vlan_mode(ocelot, port, features);
1117 static int ocelot_get_port_parent_id(struct net_device *dev,
1118 struct netdev_phys_item_id *ppid)
1120 struct ocelot_port_private *priv = netdev_priv(dev);
1121 struct ocelot *ocelot = priv->port.ocelot;
1123 ppid->id_len = sizeof(ocelot->base_mac);
1124 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len);
1129 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1131 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1132 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1134 EXPORT_SYMBOL(ocelot_hwstamp_get);
1136 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1138 struct ocelot_port *ocelot_port = ocelot->ports[port];
1139 struct hwtstamp_config cfg;
1141 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1144 /* reserved for future extensions */
1148 /* Tx type sanity check */
1149 switch (cfg.tx_type) {
1150 case HWTSTAMP_TX_ON:
1151 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1153 case HWTSTAMP_TX_ONESTEP_SYNC:
1154 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1155 * need to update the origin time.
1157 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1159 case HWTSTAMP_TX_OFF:
1160 ocelot_port->ptp_cmd = 0;
1166 mutex_lock(&ocelot->ptp_lock);
1168 switch (cfg.rx_filter) {
1169 case HWTSTAMP_FILTER_NONE:
1171 case HWTSTAMP_FILTER_ALL:
1172 case HWTSTAMP_FILTER_SOME:
1173 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1174 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1175 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1176 case HWTSTAMP_FILTER_NTP_ALL:
1177 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1178 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1179 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1180 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1181 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1182 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1183 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1184 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1185 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1186 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1189 mutex_unlock(&ocelot->ptp_lock);
1193 /* Commit back the result & save it */
1194 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1195 mutex_unlock(&ocelot->ptp_lock);
1197 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1199 EXPORT_SYMBOL(ocelot_hwstamp_set);
1201 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1203 struct ocelot_port_private *priv = netdev_priv(dev);
1204 struct ocelot *ocelot = priv->port.ocelot;
1205 int port = priv->chip_port;
1210 return ocelot_hwstamp_set(ocelot, port, ifr);
1212 return ocelot_hwstamp_get(ocelot, port, ifr);
1216 return phy_mii_ioctl(dev->phydev, ifr, cmd);
1219 static const struct net_device_ops ocelot_port_netdev_ops = {
1220 .ndo_open = ocelot_port_open,
1221 .ndo_stop = ocelot_port_stop,
1222 .ndo_start_xmit = ocelot_port_xmit,
1223 .ndo_set_rx_mode = ocelot_set_rx_mode,
1224 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name,
1225 .ndo_set_mac_address = ocelot_port_set_mac_address,
1226 .ndo_get_stats64 = ocelot_get_stats64,
1227 .ndo_fdb_add = ocelot_port_fdb_add,
1228 .ndo_fdb_del = ocelot_port_fdb_del,
1229 .ndo_fdb_dump = ocelot_port_fdb_dump,
1230 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid,
1231 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid,
1232 .ndo_set_features = ocelot_set_features,
1233 .ndo_get_port_parent_id = ocelot_get_port_parent_id,
1234 .ndo_setup_tc = ocelot_setup_tc,
1235 .ndo_do_ioctl = ocelot_ioctl,
1238 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1242 if (sset != ETH_SS_STATS)
1245 for (i = 0; i < ocelot->num_stats; i++)
1246 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1249 EXPORT_SYMBOL(ocelot_get_strings);
1251 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset,
1254 struct ocelot_port_private *priv = netdev_priv(netdev);
1255 struct ocelot *ocelot = priv->port.ocelot;
1256 int port = priv->chip_port;
1258 ocelot_get_strings(ocelot, port, sset, data);
1261 static void ocelot_update_stats(struct ocelot *ocelot)
1265 mutex_lock(&ocelot->stats_lock);
1267 for (i = 0; i < ocelot->num_phys_ports; i++) {
1268 /* Configure the port to read the stats from */
1269 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1271 for (j = 0; j < ocelot->num_stats; j++) {
1273 unsigned int idx = i * ocelot->num_stats + j;
1275 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1276 ocelot->stats_layout[j].offset);
1278 if (val < (ocelot->stats[idx] & U32_MAX))
1279 ocelot->stats[idx] += (u64)1 << 32;
1281 ocelot->stats[idx] = (ocelot->stats[idx] &
1282 ~(u64)U32_MAX) + val;
1286 mutex_unlock(&ocelot->stats_lock);
1289 static void ocelot_check_stats_work(struct work_struct *work)
1291 struct delayed_work *del_work = to_delayed_work(work);
1292 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1295 ocelot_update_stats(ocelot);
1297 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1298 OCELOT_STATS_CHECK_DELAY);
1301 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1305 /* check and update now */
1306 ocelot_update_stats(ocelot);
1308 /* Copy all counters */
1309 for (i = 0; i < ocelot->num_stats; i++)
1310 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1312 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1314 static void ocelot_port_get_ethtool_stats(struct net_device *dev,
1315 struct ethtool_stats *stats,
1318 struct ocelot_port_private *priv = netdev_priv(dev);
1319 struct ocelot *ocelot = priv->port.ocelot;
1320 int port = priv->chip_port;
1322 ocelot_get_ethtool_stats(ocelot, port, data);
1325 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1327 if (sset != ETH_SS_STATS)
1330 return ocelot->num_stats;
1332 EXPORT_SYMBOL(ocelot_get_sset_count);
1334 static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
1336 struct ocelot_port_private *priv = netdev_priv(dev);
1337 struct ocelot *ocelot = priv->port.ocelot;
1338 int port = priv->chip_port;
1340 return ocelot_get_sset_count(ocelot, port, sset);
1343 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1344 struct ethtool_ts_info *info)
1346 info->phc_index = ocelot->ptp_clock ?
1347 ptp_clock_index(ocelot->ptp_clock) : -1;
1348 if (info->phc_index == -1) {
1349 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1350 SOF_TIMESTAMPING_RX_SOFTWARE |
1351 SOF_TIMESTAMPING_SOFTWARE;
1354 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1355 SOF_TIMESTAMPING_RX_SOFTWARE |
1356 SOF_TIMESTAMPING_SOFTWARE |
1357 SOF_TIMESTAMPING_TX_HARDWARE |
1358 SOF_TIMESTAMPING_RX_HARDWARE |
1359 SOF_TIMESTAMPING_RAW_HARDWARE;
1360 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1361 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1362 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1366 EXPORT_SYMBOL(ocelot_get_ts_info);
1368 static int ocelot_port_get_ts_info(struct net_device *dev,
1369 struct ethtool_ts_info *info)
1371 struct ocelot_port_private *priv = netdev_priv(dev);
1372 struct ocelot *ocelot = priv->port.ocelot;
1373 int port = priv->chip_port;
1376 return ethtool_op_get_ts_info(dev, info);
1378 return ocelot_get_ts_info(ocelot, port, info);
1381 static const struct ethtool_ops ocelot_ethtool_ops = {
1382 .get_strings = ocelot_port_get_strings,
1383 .get_ethtool_stats = ocelot_port_get_ethtool_stats,
1384 .get_sset_count = ocelot_port_get_sset_count,
1385 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1386 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1387 .get_ts_info = ocelot_port_get_ts_info,
1390 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1395 if (!(BIT(port) & ocelot->bridge_mask))
1398 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1401 case BR_STATE_FORWARDING:
1402 ocelot->bridge_fwd_mask |= BIT(port);
1404 case BR_STATE_LEARNING:
1405 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1409 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1410 ocelot->bridge_fwd_mask &= ~BIT(port);
1414 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
1416 /* Apply FWD mask. The loop is needed to add/remove the current port as
1417 * a source for the other ports.
1419 for (p = 0; p < ocelot->num_phys_ports; p++) {
1420 if (ocelot->bridge_fwd_mask & BIT(p)) {
1421 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
1423 for (i = 0; i < ocelot->num_phys_ports; i++) {
1424 unsigned long bond_mask = ocelot->lags[i];
1429 if (bond_mask & BIT(p)) {
1435 ocelot_write_rix(ocelot, mask,
1436 ANA_PGID_PGID, PGID_SRC + p);
1438 ocelot_write_rix(ocelot, 0,
1439 ANA_PGID_PGID, PGID_SRC + p);
1443 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1445 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
1446 struct switchdev_trans *trans,
1449 if (switchdev_trans_ph_prepare(trans))
1452 ocelot_bridge_stp_state_set(ocelot, port, state);
1455 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1457 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1459 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1460 * which is clearly not what our intention is. So avoid that.
1465 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1467 EXPORT_SYMBOL(ocelot_set_ageing_time);
1469 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
1470 unsigned long ageing_clock_t)
1472 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t);
1473 u32 ageing_time = jiffies_to_msecs(ageing_jiffies);
1475 ocelot_set_ageing_time(ocelot, ageing_time);
1478 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc)
1480 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA |
1481 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA |
1482 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA;
1486 val = cpu_fwd_mcast;
1488 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast,
1489 ANA_PORT_CPU_FWD_CFG, port);
1492 static int ocelot_port_attr_set(struct net_device *dev,
1493 const struct switchdev_attr *attr,
1494 struct switchdev_trans *trans)
1496 struct ocelot_port_private *priv = netdev_priv(dev);
1497 struct ocelot *ocelot = priv->port.ocelot;
1498 int port = priv->chip_port;
1502 case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
1503 ocelot_port_attr_stp_state_set(ocelot, port, trans,
1506 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
1507 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time);
1509 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
1510 ocelot_port_vlan_filtering(ocelot, port,
1511 attr->u.vlan_filtering);
1513 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED:
1514 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled);
1524 static int ocelot_port_obj_add_vlan(struct net_device *dev,
1525 const struct switchdev_obj_port_vlan *vlan,
1526 struct switchdev_trans *trans)
1531 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1532 ret = ocelot_vlan_vid_add(dev, vid,
1533 vlan->flags & BRIDGE_VLAN_INFO_PVID,
1534 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED);
1542 static int ocelot_port_vlan_del_vlan(struct net_device *dev,
1543 const struct switchdev_obj_port_vlan *vlan)
1548 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
1549 ret = ocelot_vlan_vid_del(dev, vid);
1558 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1559 const unsigned char *addr,
1562 struct ocelot_multicast *mc;
1564 list_for_each_entry(mc, &ocelot->multicast, list) {
1565 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1572 static int ocelot_port_obj_add_mdb(struct net_device *dev,
1573 const struct switchdev_obj_port_mdb *mdb,
1574 struct switchdev_trans *trans)
1576 struct ocelot_port_private *priv = netdev_priv(dev);
1577 struct ocelot_port *ocelot_port = &priv->port;
1578 struct ocelot *ocelot = ocelot_port->ocelot;
1579 unsigned char addr[ETH_ALEN];
1580 struct ocelot_multicast *mc;
1581 int port = priv->chip_port;
1586 vid = ocelot_port->pvid;
1588 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1590 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1594 memcpy(mc->addr, mdb->addr, ETH_ALEN);
1597 list_add_tail(&mc->list, &ocelot->multicast);
1601 memcpy(addr, mc->addr, ETH_ALEN);
1605 addr[2] = mc->ports << 0;
1606 addr[1] = mc->ports << 8;
1607 ocelot_mact_forget(ocelot, addr, vid);
1610 mc->ports |= BIT(port);
1611 addr[2] = mc->ports << 0;
1612 addr[1] = mc->ports << 8;
1614 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1617 static int ocelot_port_obj_del_mdb(struct net_device *dev,
1618 const struct switchdev_obj_port_mdb *mdb)
1620 struct ocelot_port_private *priv = netdev_priv(dev);
1621 struct ocelot_port *ocelot_port = &priv->port;
1622 struct ocelot *ocelot = ocelot_port->ocelot;
1623 unsigned char addr[ETH_ALEN];
1624 struct ocelot_multicast *mc;
1625 int port = priv->chip_port;
1629 vid = ocelot_port->pvid;
1631 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1635 memcpy(addr, mc->addr, ETH_ALEN);
1636 addr[2] = mc->ports << 0;
1637 addr[1] = mc->ports << 8;
1639 ocelot_mact_forget(ocelot, addr, vid);
1641 mc->ports &= ~BIT(port);
1643 list_del(&mc->list);
1644 devm_kfree(ocelot->dev, mc);
1648 addr[2] = mc->ports << 0;
1649 addr[1] = mc->ports << 8;
1651 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4);
1654 static int ocelot_port_obj_add(struct net_device *dev,
1655 const struct switchdev_obj *obj,
1656 struct switchdev_trans *trans,
1657 struct netlink_ext_ack *extack)
1662 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1663 ret = ocelot_port_obj_add_vlan(dev,
1664 SWITCHDEV_OBJ_PORT_VLAN(obj),
1667 case SWITCHDEV_OBJ_ID_PORT_MDB:
1668 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj),
1678 static int ocelot_port_obj_del(struct net_device *dev,
1679 const struct switchdev_obj *obj)
1684 case SWITCHDEV_OBJ_ID_PORT_VLAN:
1685 ret = ocelot_port_vlan_del_vlan(dev,
1686 SWITCHDEV_OBJ_PORT_VLAN(obj));
1688 case SWITCHDEV_OBJ_ID_PORT_MDB:
1689 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj));
1698 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1699 struct net_device *bridge)
1701 if (!ocelot->bridge_mask) {
1702 ocelot->hw_bridge_dev = bridge;
1704 if (ocelot->hw_bridge_dev != bridge)
1705 /* This is adding the port to a second bridge, this is
1710 ocelot->bridge_mask |= BIT(port);
1714 EXPORT_SYMBOL(ocelot_port_bridge_join);
1716 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1717 struct net_device *bridge)
1719 ocelot->bridge_mask &= ~BIT(port);
1721 if (!ocelot->bridge_mask)
1722 ocelot->hw_bridge_dev = NULL;
1724 ocelot_port_vlan_filtering(ocelot, port, 0);
1725 ocelot_port_set_pvid(ocelot, port, 0);
1726 return ocelot_port_set_native_vlan(ocelot, port, 0);
1728 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1730 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1734 /* Reset destination and aggregation PGIDS */
1735 for (port = 0; port < ocelot->num_phys_ports; port++)
1736 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1738 for (i = PGID_AGGR; i < PGID_SRC; i++)
1739 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1742 /* Now, set PGIDs for each LAG */
1743 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1744 unsigned long bond_mask;
1748 bond_mask = ocelot->lags[lag];
1752 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1754 ocelot_write_rix(ocelot, bond_mask,
1755 ANA_PGID_PGID, port);
1756 aggr_idx[aggr_count] = port;
1760 for (i = PGID_AGGR; i < PGID_SRC; i++) {
1763 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1765 ac |= BIT(aggr_idx[i % aggr_count]);
1766 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1771 static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1773 unsigned long bond_mask = ocelot->lags[lag];
1776 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1777 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1779 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1781 /* Use lag port as logical port for port i */
1782 ocelot_write_gix(ocelot, port_cfg |
1783 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1784 ANA_PORT_PORT_CFG, p);
1788 static int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1789 struct net_device *bond)
1791 struct net_device *ndev;
1796 for_each_netdev_in_bond_rcu(bond, ndev) {
1797 struct ocelot_port_private *priv = netdev_priv(ndev);
1799 bond_mask |= BIT(priv->chip_port);
1803 lp = __ffs(bond_mask);
1805 /* If the new port is the lowest one, use it as the logical port from
1810 ocelot->lags[port] = bond_mask;
1811 bond_mask &= ~BIT(port);
1813 lp = __ffs(bond_mask);
1814 ocelot->lags[lp] = 0;
1818 ocelot->lags[lp] |= BIT(port);
1821 ocelot_setup_lag(ocelot, lag);
1822 ocelot_set_aggr_pgids(ocelot);
1827 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1828 struct net_device *bond)
1833 /* Remove port from any lag */
1834 for (i = 0; i < ocelot->num_phys_ports; i++)
1835 ocelot->lags[i] &= ~BIT(port);
1837 /* if it was the logical port of the lag, move the lag config to the
1840 if (ocelot->lags[port]) {
1841 int n = __ffs(ocelot->lags[port]);
1843 ocelot->lags[n] = ocelot->lags[port];
1844 ocelot->lags[port] = 0;
1846 ocelot_setup_lag(ocelot, n);
1849 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1850 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1851 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1852 ANA_PORT_PORT_CFG, port);
1854 ocelot_set_aggr_pgids(ocelot);
1857 /* Checks if the net_device instance given to us originate from our driver. */
1858 static bool ocelot_netdevice_dev_check(const struct net_device *dev)
1860 return dev->netdev_ops == &ocelot_port_netdev_ops;
1863 static int ocelot_netdevice_port_event(struct net_device *dev,
1864 unsigned long event,
1865 struct netdev_notifier_changeupper_info *info)
1867 struct ocelot_port_private *priv = netdev_priv(dev);
1868 struct ocelot_port *ocelot_port = &priv->port;
1869 struct ocelot *ocelot = ocelot_port->ocelot;
1870 int port = priv->chip_port;
1874 case NETDEV_CHANGEUPPER:
1875 if (netif_is_bridge_master(info->upper_dev)) {
1876 if (info->linking) {
1877 err = ocelot_port_bridge_join(ocelot, port,
1880 err = ocelot_port_bridge_leave(ocelot, port,
1884 if (netif_is_lag_master(info->upper_dev)) {
1886 err = ocelot_port_lag_join(ocelot, port,
1889 ocelot_port_lag_leave(ocelot, port,
1900 static int ocelot_netdevice_event(struct notifier_block *unused,
1901 unsigned long event, void *ptr)
1903 struct netdev_notifier_changeupper_info *info = ptr;
1904 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
1907 if (!ocelot_netdevice_dev_check(dev))
1910 if (event == NETDEV_PRECHANGEUPPER &&
1911 netif_is_lag_master(info->upper_dev)) {
1912 struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
1913 struct netlink_ext_ack *extack;
1915 if (lag_upper_info &&
1916 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1917 extack = netdev_notifier_info_to_extack(&info->info);
1918 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
1925 if (netif_is_lag_master(dev)) {
1926 struct net_device *slave;
1927 struct list_head *iter;
1929 netdev_for_each_lower_dev(dev, slave, iter) {
1930 ret = ocelot_netdevice_port_event(slave, event, info);
1935 ret = ocelot_netdevice_port_event(dev, event, info);
1939 return notifier_from_errno(ret);
1942 struct notifier_block ocelot_netdevice_nb __read_mostly = {
1943 .notifier_call = ocelot_netdevice_event,
1945 EXPORT_SYMBOL(ocelot_netdevice_nb);
1947 static int ocelot_switchdev_event(struct notifier_block *unused,
1948 unsigned long event, void *ptr)
1950 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1954 case SWITCHDEV_PORT_ATTR_SET:
1955 err = switchdev_handle_port_attr_set(dev, ptr,
1956 ocelot_netdevice_dev_check,
1957 ocelot_port_attr_set);
1958 return notifier_from_errno(err);
1964 struct notifier_block ocelot_switchdev_nb __read_mostly = {
1965 .notifier_call = ocelot_switchdev_event,
1967 EXPORT_SYMBOL(ocelot_switchdev_nb);
1969 static int ocelot_switchdev_blocking_event(struct notifier_block *unused,
1970 unsigned long event, void *ptr)
1972 struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
1976 /* Blocking events. */
1977 case SWITCHDEV_PORT_OBJ_ADD:
1978 err = switchdev_handle_port_obj_add(dev, ptr,
1979 ocelot_netdevice_dev_check,
1980 ocelot_port_obj_add);
1981 return notifier_from_errno(err);
1982 case SWITCHDEV_PORT_OBJ_DEL:
1983 err = switchdev_handle_port_obj_del(dev, ptr,
1984 ocelot_netdevice_dev_check,
1985 ocelot_port_obj_del);
1986 return notifier_from_errno(err);
1987 case SWITCHDEV_PORT_ATTR_SET:
1988 err = switchdev_handle_port_attr_set(dev, ptr,
1989 ocelot_netdevice_dev_check,
1990 ocelot_port_attr_set);
1991 return notifier_from_errno(err);
1997 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = {
1998 .notifier_call = ocelot_switchdev_blocking_event,
2000 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb);
2002 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2003 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2004 * In the special case that it's the NPI port that we're configuring, the
2005 * length of the tag and optional prefix needs to be accounted for privately,
2006 * in order to be able to sustain communication at the requested @sdu.
2008 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2010 struct ocelot_port *ocelot_port = ocelot->ports[port];
2011 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2014 if (port == ocelot->npi) {
2015 maxlen += OCELOT_TAG_LEN;
2017 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2018 maxlen += OCELOT_SHORT_PREFIX_LEN;
2019 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
2020 maxlen += OCELOT_LONG_PREFIX_LEN;
2023 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2025 /* Set Pause WM hysteresis
2026 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ
2027 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ
2029 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
2030 SYS_PAUSE_CFG_PAUSE_STOP(101) |
2031 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
2033 /* Tail dropping watermark */
2034 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) /
2035 OCELOT_BUFFER_CELL_SZ;
2036 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * maxlen),
2038 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
2040 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2042 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2044 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2046 if (port == ocelot->npi) {
2047 max_mtu -= OCELOT_TAG_LEN;
2049 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2050 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2051 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
2052 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2057 EXPORT_SYMBOL(ocelot_get_max_mtu);
2059 void ocelot_init_port(struct ocelot *ocelot, int port)
2061 struct ocelot_port *ocelot_port = ocelot->ports[port];
2063 skb_queue_head_init(&ocelot_port->tx_skbs);
2065 /* Basic L2 initialization */
2068 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2069 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2071 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2074 /* Load seed (0) and set MAC HDX late collision */
2075 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2076 DEV_MAC_HDX_CFG_SEED_LOAD,
2079 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2082 /* Set Max Length and maximum tags allowed */
2083 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2084 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2085 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2086 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2087 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2090 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2091 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2092 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2094 /* Drop frames with multicast source address */
2095 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2096 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2097 ANA_PORT_DROP_CFG, port);
2099 /* Set default VLAN and tag type to 8021Q. */
2100 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2101 REW_PORT_VLAN_CFG_PORT_TPID_M,
2102 REW_PORT_VLAN_CFG, port);
2104 /* Enable vcap lookups */
2105 ocelot_vcap_enable(ocelot, port);
2107 EXPORT_SYMBOL(ocelot_init_port);
2109 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
2111 struct phy_device *phy)
2113 struct ocelot_port_private *priv;
2114 struct ocelot_port *ocelot_port;
2115 struct net_device *dev;
2118 dev = alloc_etherdev(sizeof(struct ocelot_port_private));
2121 SET_NETDEV_DEV(dev, ocelot->dev);
2122 priv = netdev_priv(dev);
2125 priv->chip_port = port;
2126 ocelot_port = &priv->port;
2127 ocelot_port->ocelot = ocelot;
2128 ocelot_port->regs = regs;
2129 ocelot->ports[port] = ocelot_port;
2131 dev->netdev_ops = &ocelot_port_netdev_ops;
2132 dev->ethtool_ops = &ocelot_ethtool_ops;
2134 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS |
2136 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2138 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN);
2139 dev->dev_addr[ETH_ALEN - 1] += port;
2140 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid,
2143 ocelot_init_port(ocelot, port);
2145 err = register_netdev(dev);
2147 dev_err(ocelot->dev, "register_netdev failed\n");
2153 EXPORT_SYMBOL(ocelot_probe_port);
2155 /* Configure and enable the CPU port module, which is a set of queues.
2156 * If @npi contains a valid port index, the CPU port module is connected
2157 * to the Node Processor Interface (NPI). This is the mode through which
2158 * frames can be injected from and extracted to an external CPU,
2161 void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
2162 enum ocelot_tag_prefix injection,
2163 enum ocelot_tag_prefix extraction)
2165 int cpu = ocelot->num_phys_ports;
2168 ocelot->inj_prefix = injection;
2169 ocelot->xtr_prefix = extraction;
2171 /* The unicast destination PGID for the CPU port module is unused */
2172 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2173 /* Instead set up a multicast destination PGID for traffic copied to
2174 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2175 * addresses will be copied to the CPU via this PGID.
2177 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2178 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2179 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2180 ANA_PORT_PORT_CFG, cpu);
2182 if (npi >= 0 && npi < ocelot->num_phys_ports) {
2183 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
2184 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi),
2187 /* Enable NPI port */
2188 ocelot_write_rix(ocelot,
2189 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2190 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2191 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2192 QSYS_SWITCH_PORT_MODE, npi);
2193 /* NPI port Injection/Extraction configuration */
2194 ocelot_write_rix(ocelot,
2195 SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
2196 SYS_PORT_MODE_INCL_INJ_HDR(injection),
2197 SYS_PORT_MODE, npi);
2200 /* Enable CPU port module */
2201 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |
2202 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |
2203 QSYS_SWITCH_PORT_MODE_PORT_ENA,
2204 QSYS_SWITCH_PORT_MODE, cpu);
2205 /* CPU port Injection/Extraction configuration */
2206 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |
2207 SYS_PORT_MODE_INCL_INJ_HDR(injection),
2208 SYS_PORT_MODE, cpu);
2210 /* Configure the CPU port to be VLAN aware */
2211 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
2212 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2213 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2214 ANA_PORT_VLAN_CFG, cpu);
2216 EXPORT_SYMBOL(ocelot_configure_cpu);
2218 int ocelot_init(struct ocelot *ocelot)
2220 char queue_name[32];
2224 if (ocelot->ops->reset) {
2225 ret = ocelot->ops->reset(ocelot);
2227 dev_err(ocelot->dev, "Switch reset failed\n");
2232 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
2233 sizeof(u32), GFP_KERNEL);
2237 ocelot->stats = devm_kcalloc(ocelot->dev,
2238 ocelot->num_phys_ports * ocelot->num_stats,
2239 sizeof(u64), GFP_KERNEL);
2243 mutex_init(&ocelot->stats_lock);
2244 mutex_init(&ocelot->ptp_lock);
2245 spin_lock_init(&ocelot->ptp_clock_lock);
2246 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2247 dev_name(ocelot->dev));
2248 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2249 if (!ocelot->stats_queue)
2252 INIT_LIST_HEAD(&ocelot->multicast);
2253 ocelot_mact_init(ocelot);
2254 ocelot_vlan_init(ocelot);
2255 ocelot_ace_init(ocelot);
2257 for (port = 0; port < ocelot->num_phys_ports; port++) {
2258 /* Clear all counters (5 groups) */
2259 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2260 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2264 /* Only use S-Tag */
2265 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2267 /* Aggregation mode */
2268 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2269 ANA_AGGR_CFG_AC_DMAC_ENA |
2270 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2271 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
2273 /* Set MAC age time to default value. The entry is aged after
2276 ocelot_write(ocelot,
2277 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2280 /* Disable learning for frames discarded by VLAN ingress filtering */
2281 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2283 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2284 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2285 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2287 /* Setup flooding PGIDs */
2288 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2289 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
2290 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2292 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2293 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2294 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2295 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2298 for (port = 0; port < ocelot->num_phys_ports; port++) {
2299 /* Transmit the frame to the local port. */
2300 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2301 /* Do not forward BPDU frames to the front ports. */
2302 ocelot_write_gix(ocelot,
2303 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2304 ANA_PORT_CPU_FWD_BPDU_CFG,
2306 /* Ensure bridging is disabled */
2307 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2310 /* Allow broadcast MAC frames. */
2311 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) {
2312 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2314 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2316 ocelot_write_rix(ocelot,
2317 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
2318 ANA_PGID_PGID, PGID_MC);
2319 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2320 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2322 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2323 * registers endianness.
2325 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2326 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2327 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2328 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2329 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2330 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2331 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2332 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2333 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2334 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2335 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2336 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2337 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2338 for (i = 0; i < 16; i++)
2339 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2340 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2341 ANA_CPUQ_8021_CFG, i);
2343 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2344 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2345 OCELOT_STATS_CHECK_DELAY);
2349 EXPORT_SYMBOL(ocelot_init);
2351 void ocelot_deinit(struct ocelot *ocelot)
2353 struct ocelot_port *port;
2356 cancel_delayed_work(&ocelot->stats_work);
2357 destroy_workqueue(ocelot->stats_queue);
2358 mutex_destroy(&ocelot->stats_lock);
2360 for (i = 0; i < ocelot->num_phys_ports; i++) {
2361 port = ocelot->ports[i];
2362 skb_queue_purge(&port->tx_skbs);
2365 EXPORT_SYMBOL(ocelot_deinit);
2367 MODULE_LICENSE("Dual MIT/GPL");