1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright (c) 2021, Microsoft Corporation. */
4 #include <linux/module.h>
9 static u32 mana_gd_r32(struct gdma_context *g, u64 offset)
11 return readl(g->bar0_va + offset);
14 static u64 mana_gd_r64(struct gdma_context *g, u64 offset)
16 return readq(g->bar0_va + offset);
19 static void mana_gd_init_registers(struct pci_dev *pdev)
21 struct gdma_context *gc = pci_get_drvdata(pdev);
23 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF;
25 gc->db_page_base = gc->bar0_va +
26 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET);
28 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET);
31 static int mana_gd_query_max_resources(struct pci_dev *pdev)
33 struct gdma_context *gc = pci_get_drvdata(pdev);
34 struct gdma_query_max_resources_resp resp = {};
35 struct gdma_general_req req = {};
38 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES,
39 sizeof(req), sizeof(resp));
41 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
42 if (err || resp.hdr.status) {
43 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n",
44 err, resp.hdr.status);
45 return err ? err : -EPROTO;
48 if (gc->num_msix_usable > resp.max_msix)
49 gc->num_msix_usable = resp.max_msix;
51 if (gc->num_msix_usable <= 1)
54 gc->max_num_queues = num_online_cpus();
55 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES)
56 gc->max_num_queues = MANA_MAX_NUM_QUEUES;
58 if (gc->max_num_queues > resp.max_eq)
59 gc->max_num_queues = resp.max_eq;
61 if (gc->max_num_queues > resp.max_cq)
62 gc->max_num_queues = resp.max_cq;
64 if (gc->max_num_queues > resp.max_sq)
65 gc->max_num_queues = resp.max_sq;
67 if (gc->max_num_queues > resp.max_rq)
68 gc->max_num_queues = resp.max_rq;
70 /* The Hardware Channel (HWC) used 1 MSI-X */
71 if (gc->max_num_queues > gc->num_msix_usable - 1)
72 gc->max_num_queues = gc->num_msix_usable - 1;
77 static int mana_gd_detect_devices(struct pci_dev *pdev)
79 struct gdma_context *gc = pci_get_drvdata(pdev);
80 struct gdma_list_devices_resp resp = {};
81 struct gdma_general_req req = {};
82 struct gdma_dev_id dev;
87 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req),
90 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
91 if (err || resp.hdr.status) {
92 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err,
94 return err ? err : -EPROTO;
97 max_num_devs = min_t(u32, MAX_NUM_GDMA_DEVICES, resp.num_of_devs);
99 for (i = 0; i < max_num_devs; i++) {
103 /* HWC is already detected in mana_hwc_create_channel(). */
104 if (dev_type == GDMA_DEVICE_HWC)
107 if (dev_type == GDMA_DEVICE_MANA) {
108 gc->mana.gdma_context = gc;
109 gc->mana.dev_id = dev;
113 return gc->mana.dev_id.type == 0 ? -ENODEV : 0;
116 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req,
117 u32 resp_len, void *resp)
119 struct hw_channel_context *hwc = gc->hwc.driver_data;
121 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp);
124 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length,
125 struct gdma_mem_info *gmi)
127 dma_addr_t dma_handle;
130 if (length < PAGE_SIZE || !is_power_of_2(length))
134 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL);
138 gmi->dma_handle = dma_handle;
139 gmi->virt_addr = buf;
140 gmi->length = length;
145 void mana_gd_free_memory(struct gdma_mem_info *gmi)
147 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr,
151 static int mana_gd_create_hw_eq(struct gdma_context *gc,
152 struct gdma_queue *queue)
154 struct gdma_create_queue_resp resp = {};
155 struct gdma_create_queue_req req = {};
158 if (queue->type != GDMA_EQ)
161 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE,
162 sizeof(req), sizeof(resp));
164 req.hdr.dev_id = queue->gdma_dev->dev_id;
165 req.type = queue->type;
166 req.pdid = queue->gdma_dev->pdid;
167 req.doolbell_id = queue->gdma_dev->doorbell;
168 req.gdma_region = queue->mem_info.gdma_region;
169 req.queue_size = queue->queue_size;
170 req.log2_throttle_limit = queue->eq.log2_throttle_limit;
171 req.eq_pci_msix_index = queue->eq.msix_index;
173 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
174 if (err || resp.hdr.status) {
175 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err,
177 return err ? err : -EPROTO;
180 queue->id = resp.queue_index;
181 queue->eq.disable_needed = true;
182 queue->mem_info.gdma_region = GDMA_INVALID_DMA_REGION;
186 static int mana_gd_disable_queue(struct gdma_queue *queue)
188 struct gdma_context *gc = queue->gdma_dev->gdma_context;
189 struct gdma_disable_queue_req req = {};
190 struct gdma_general_resp resp = {};
193 WARN_ON(queue->type != GDMA_EQ);
195 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE,
196 sizeof(req), sizeof(resp));
198 req.hdr.dev_id = queue->gdma_dev->dev_id;
199 req.type = queue->type;
200 req.queue_index = queue->id;
201 req.alloc_res_id_on_creation = 1;
203 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
204 if (err || resp.hdr.status) {
205 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err,
207 return err ? err : -EPROTO;
213 #define DOORBELL_OFFSET_SQ 0x0
214 #define DOORBELL_OFFSET_RQ 0x400
215 #define DOORBELL_OFFSET_CQ 0x800
216 #define DOORBELL_OFFSET_EQ 0xFF8
218 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index,
219 enum gdma_queue_type q_type, u32 qid,
220 u32 tail_ptr, u8 num_req)
222 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index;
223 union gdma_doorbell_entry e = {};
228 e.eq.tail_ptr = tail_ptr;
231 addr += DOORBELL_OFFSET_EQ;
236 e.cq.tail_ptr = tail_ptr;
239 addr += DOORBELL_OFFSET_CQ;
244 e.rq.tail_ptr = tail_ptr;
245 e.rq.wqe_cnt = num_req;
247 addr += DOORBELL_OFFSET_RQ;
252 e.sq.tail_ptr = tail_ptr;
254 addr += DOORBELL_OFFSET_SQ;
262 /* Ensure all writes are done before ring doorbell */
265 writeq(e.as_uint64, addr);
268 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue)
270 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type,
271 queue->id, queue->head * GDMA_WQE_BU_SIZE, 1);
274 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit)
276 struct gdma_context *gc = cq->gdma_dev->gdma_context;
278 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE;
280 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS);
282 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id,
286 static void mana_gd_process_eqe(struct gdma_queue *eq)
288 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE);
289 struct gdma_context *gc = eq->gdma_dev->gdma_context;
290 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr;
291 union gdma_eqe_info eqe_info;
292 enum gdma_eqe_type type;
293 struct gdma_event event;
294 struct gdma_queue *cq;
295 struct gdma_eqe *eqe;
298 eqe = &eq_eqe_ptr[head];
299 eqe_info.as_uint32 = eqe->eqe_info;
300 type = eqe_info.type;
303 case GDMA_EQE_COMPLETION:
304 cq_id = eqe->details[0] & 0xFFFFFF;
305 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs))
308 cq = gc->cq_table[cq_id];
309 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id))
313 cq->cq.callback(cq->cq.context, cq);
317 case GDMA_EQE_TEST_EVENT:
318 gc->test_event_eq_id = eq->id;
319 complete(&gc->eq_test_event);
322 case GDMA_EQE_HWC_INIT_EQ_ID_DB:
323 case GDMA_EQE_HWC_INIT_DATA:
324 case GDMA_EQE_HWC_INIT_DONE:
325 if (!eq->eq.callback)
329 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE);
330 eq->eq.callback(eq->eq.context, eq, &event);
338 static void mana_gd_process_eq_events(void *arg)
340 u32 owner_bits, new_bits, old_bits;
341 union gdma_eqe_info eqe_info;
342 struct gdma_eqe *eq_eqe_ptr;
343 struct gdma_queue *eq = arg;
344 struct gdma_context *gc;
345 struct gdma_eqe *eqe;
349 gc = eq->gdma_dev->gdma_context;
351 num_eqe = eq->queue_size / GDMA_EQE_SIZE;
352 eq_eqe_ptr = eq->queue_mem_ptr;
354 /* Process up to 5 EQEs at a time, and update the HW head. */
355 for (i = 0; i < 5; i++) {
356 eqe = &eq_eqe_ptr[eq->head % num_eqe];
357 eqe_info.as_uint32 = eqe->eqe_info;
358 owner_bits = eqe_info.owner_bits;
360 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;
361 /* No more entries */
362 if (owner_bits == old_bits)
365 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;
366 if (owner_bits != new_bits) {
367 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id);
371 /* Per GDMA spec, rmb is necessary after checking owner_bits, before
376 mana_gd_process_eqe(eq);
381 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);
383 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,
387 static int mana_gd_register_irq(struct gdma_queue *queue,
388 const struct gdma_queue_spec *spec)
390 struct gdma_dev *gd = queue->gdma_dev;
391 struct gdma_irq_context *gic;
392 struct gdma_context *gc;
393 struct gdma_resource *r;
394 unsigned int msi_index;
399 gc = gd->gdma_context;
400 r = &gc->msix_resource;
403 spin_lock_irqsave(&r->lock, flags);
405 msi_index = find_first_zero_bit(r->map, r->size);
406 if (msi_index >= r->size || msi_index >= gc->num_msix_usable) {
409 bitmap_set(r->map, msi_index, 1);
410 queue->eq.msix_index = msi_index;
413 spin_unlock_irqrestore(&r->lock, flags);
416 dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u",
417 err, msi_index, r->size, gc->num_msix_usable);
422 gic = &gc->irq_contexts[msi_index];
424 WARN_ON(gic->handler || gic->arg);
428 gic->handler = mana_gd_process_eq_events;
433 static void mana_gd_deregiser_irq(struct gdma_queue *queue)
435 struct gdma_dev *gd = queue->gdma_dev;
436 struct gdma_irq_context *gic;
437 struct gdma_context *gc;
438 struct gdma_resource *r;
439 unsigned int msix_index;
442 gc = gd->gdma_context;
443 r = &gc->msix_resource;
445 /* At most num_online_cpus() + 1 interrupts are used. */
446 msix_index = queue->eq.msix_index;
447 if (WARN_ON(msix_index >= gc->num_msix_usable))
450 gic = &gc->irq_contexts[msix_index];
454 spin_lock_irqsave(&r->lock, flags);
455 bitmap_clear(r->map, msix_index, 1);
456 spin_unlock_irqrestore(&r->lock, flags);
458 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
461 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq)
463 struct gdma_generate_test_event_req req = {};
464 struct gdma_general_resp resp = {};
465 struct device *dev = gc->dev;
468 mutex_lock(&gc->eq_test_event_mutex);
470 init_completion(&gc->eq_test_event);
471 gc->test_event_eq_id = INVALID_QUEUE_ID;
473 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE,
474 sizeof(req), sizeof(resp));
476 req.hdr.dev_id = eq->gdma_dev->dev_id;
477 req.queue_index = eq->id;
479 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
481 dev_err(dev, "test_eq failed: %d\n", err);
487 if (resp.hdr.status) {
488 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status);
492 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) {
493 dev_err(dev, "test_eq timed out on queue %d\n", eq->id);
497 if (eq->id != gc->test_event_eq_id) {
498 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n",
499 gc->test_event_eq_id, eq->id);
505 mutex_unlock(&gc->eq_test_event_mutex);
509 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets,
510 struct gdma_queue *queue)
515 err = mana_gd_test_eq(gc, queue);
517 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err);
520 mana_gd_deregiser_irq(queue);
522 if (queue->eq.disable_needed)
523 mana_gd_disable_queue(queue);
526 static int mana_gd_create_eq(struct gdma_dev *gd,
527 const struct gdma_queue_spec *spec,
528 bool create_hwq, struct gdma_queue *queue)
530 struct gdma_context *gc = gd->gdma_context;
531 struct device *dev = gc->dev;
532 u32 log2_num_entries;
535 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
537 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE);
539 if (spec->eq.log2_throttle_limit > log2_num_entries) {
540 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n",
541 spec->eq.log2_throttle_limit, log2_num_entries);
545 err = mana_gd_register_irq(queue, spec);
547 dev_err(dev, "Failed to register irq: %d\n", err);
551 queue->eq.callback = spec->eq.callback;
552 queue->eq.context = spec->eq.context;
553 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
554 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1;
557 err = mana_gd_create_hw_eq(gc, queue);
561 err = mana_gd_test_eq(gc, queue);
568 dev_err(dev, "Failed to create EQ: %d\n", err);
569 mana_gd_destroy_eq(gc, false, queue);
573 static void mana_gd_create_cq(const struct gdma_queue_spec *spec,
574 struct gdma_queue *queue)
576 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE);
578 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries);
579 queue->cq.parent = spec->cq.parent_eq;
580 queue->cq.context = spec->cq.context;
581 queue->cq.callback = spec->cq.callback;
584 static void mana_gd_destroy_cq(struct gdma_context *gc,
585 struct gdma_queue *queue)
589 if (id >= gc->max_num_cqs)
592 if (!gc->cq_table[id])
595 gc->cq_table[id] = NULL;
598 int mana_gd_create_hwc_queue(struct gdma_dev *gd,
599 const struct gdma_queue_spec *spec,
600 struct gdma_queue **queue_ptr)
602 struct gdma_context *gc = gd->gdma_context;
603 struct gdma_mem_info *gmi;
604 struct gdma_queue *queue;
607 queue = kzalloc(sizeof(*queue), GFP_KERNEL);
611 gmi = &queue->mem_info;
612 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
618 queue->queue_mem_ptr = gmi->virt_addr;
619 queue->queue_size = spec->queue_size;
620 queue->monitor_avl_buf = spec->monitor_avl_buf;
621 queue->type = spec->type;
622 queue->gdma_dev = gd;
624 if (spec->type == GDMA_EQ)
625 err = mana_gd_create_eq(gd, spec, false, queue);
626 else if (spec->type == GDMA_CQ)
627 mana_gd_create_cq(spec, queue);
635 mana_gd_free_memory(gmi);
641 static void mana_gd_destroy_dma_region(struct gdma_context *gc, u64 gdma_region)
643 struct gdma_destroy_dma_region_req req = {};
644 struct gdma_general_resp resp = {};
647 if (gdma_region == GDMA_INVALID_DMA_REGION)
650 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req),
652 req.gdma_region = gdma_region;
654 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
655 if (err || resp.hdr.status)
656 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n",
657 err, resp.hdr.status);
660 static int mana_gd_create_dma_region(struct gdma_dev *gd,
661 struct gdma_mem_info *gmi)
663 unsigned int num_page = gmi->length / PAGE_SIZE;
664 struct gdma_create_dma_region_req *req = NULL;
665 struct gdma_create_dma_region_resp resp = {};
666 struct gdma_context *gc = gd->gdma_context;
667 struct hw_channel_context *hwc;
668 u32 length = gmi->length;
673 if (length < PAGE_SIZE || !is_power_of_2(length))
676 if (offset_in_page(gmi->virt_addr) != 0)
679 hwc = gc->hwc.driver_data;
680 req_msg_size = sizeof(*req) + num_page * sizeof(u64);
681 if (req_msg_size > hwc->max_req_msg_size)
684 req = kzalloc(req_msg_size, GFP_KERNEL);
688 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION,
689 req_msg_size, sizeof(resp));
690 req->length = length;
691 req->offset_in_page = 0;
692 req->gdma_page_type = GDMA_PAGE_TYPE_4K;
693 req->page_count = num_page;
694 req->page_addr_list_len = num_page;
696 for (i = 0; i < num_page; i++)
697 req->page_addr_list[i] = gmi->dma_handle + i * PAGE_SIZE;
699 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp);
703 if (resp.hdr.status || resp.gdma_region == GDMA_INVALID_DMA_REGION) {
704 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n",
710 gmi->gdma_region = resp.gdma_region;
716 int mana_gd_create_mana_eq(struct gdma_dev *gd,
717 const struct gdma_queue_spec *spec,
718 struct gdma_queue **queue_ptr)
720 struct gdma_context *gc = gd->gdma_context;
721 struct gdma_mem_info *gmi;
722 struct gdma_queue *queue;
725 if (spec->type != GDMA_EQ)
728 queue = kzalloc(sizeof(*queue), GFP_KERNEL);
732 gmi = &queue->mem_info;
733 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
737 err = mana_gd_create_dma_region(gd, gmi);
743 queue->queue_mem_ptr = gmi->virt_addr;
744 queue->queue_size = spec->queue_size;
745 queue->monitor_avl_buf = spec->monitor_avl_buf;
746 queue->type = spec->type;
747 queue->gdma_dev = gd;
749 err = mana_gd_create_eq(gd, spec, true, queue);
756 mana_gd_free_memory(gmi);
762 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
763 const struct gdma_queue_spec *spec,
764 struct gdma_queue **queue_ptr)
766 struct gdma_context *gc = gd->gdma_context;
767 struct gdma_mem_info *gmi;
768 struct gdma_queue *queue;
771 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ &&
772 spec->type != GDMA_RQ)
775 queue = kzalloc(sizeof(*queue), GFP_KERNEL);
779 gmi = &queue->mem_info;
780 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi);
784 err = mana_gd_create_dma_region(gd, gmi);
790 queue->queue_mem_ptr = gmi->virt_addr;
791 queue->queue_size = spec->queue_size;
792 queue->monitor_avl_buf = spec->monitor_avl_buf;
793 queue->type = spec->type;
794 queue->gdma_dev = gd;
796 if (spec->type == GDMA_CQ)
797 mana_gd_create_cq(spec, queue);
802 mana_gd_free_memory(gmi);
808 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)
810 struct gdma_mem_info *gmi = &queue->mem_info;
812 switch (queue->type) {
814 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue);
818 mana_gd_destroy_cq(gc, queue);
828 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n",
833 mana_gd_destroy_dma_region(gc, gmi->gdma_region);
834 mana_gd_free_memory(gmi);
838 int mana_gd_verify_vf_version(struct pci_dev *pdev)
840 struct gdma_context *gc = pci_get_drvdata(pdev);
841 struct gdma_verify_ver_resp resp = {};
842 struct gdma_verify_ver_req req = {};
845 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION,
846 sizeof(req), sizeof(resp));
848 req.protocol_ver_min = GDMA_PROTOCOL_FIRST;
849 req.protocol_ver_max = GDMA_PROTOCOL_LAST;
851 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1;
852 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2;
853 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3;
854 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4;
856 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
857 if (err || resp.hdr.status) {
858 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n",
859 err, resp.hdr.status);
860 return err ? err : -EPROTO;
866 int mana_gd_register_device(struct gdma_dev *gd)
868 struct gdma_context *gc = gd->gdma_context;
869 struct gdma_register_device_resp resp = {};
870 struct gdma_general_req req = {};
873 gd->pdid = INVALID_PDID;
874 gd->doorbell = INVALID_DOORBELL;
875 gd->gpa_mkey = INVALID_MEM_KEY;
877 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req),
880 req.hdr.dev_id = gd->dev_id;
882 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
883 if (err || resp.hdr.status) {
884 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n",
885 err, resp.hdr.status);
886 return err ? err : -EPROTO;
889 gd->pdid = resp.pdid;
890 gd->gpa_mkey = resp.gpa_mkey;
891 gd->doorbell = resp.db_id;
896 int mana_gd_deregister_device(struct gdma_dev *gd)
898 struct gdma_context *gc = gd->gdma_context;
899 struct gdma_general_resp resp = {};
900 struct gdma_general_req req = {};
903 if (gd->pdid == INVALID_PDID)
906 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req),
909 req.hdr.dev_id = gd->dev_id;
911 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp);
912 if (err || resp.hdr.status) {
913 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n",
914 err, resp.hdr.status);
919 gd->pdid = INVALID_PDID;
920 gd->doorbell = INVALID_DOORBELL;
921 gd->gpa_mkey = INVALID_MEM_KEY;
926 u32 mana_gd_wq_avail_space(struct gdma_queue *wq)
928 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE;
929 u32 wq_size = wq->queue_size;
931 WARN_ON_ONCE(used_space > wq_size);
933 return wq_size - used_space;
936 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset)
938 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1);
940 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size);
942 return wq->queue_mem_ptr + offset;
945 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req,
946 enum gdma_queue_type q_type,
947 u32 client_oob_size, u32 sgl_data_size,
950 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL);
951 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0);
952 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr;
955 memset(header, 0, sizeof(struct gdma_wqe));
956 header->num_sge = wqe_req->num_sge;
957 header->inline_oob_size_div4 = client_oob_size / sizeof(u32);
960 WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2);
962 header->client_oob_in_sgl = 1;
965 header->last_vbytes = wqe_req->sgl[0].size;
968 if (q_type == GDMA_SQ)
969 header->client_data_unit = wqe_req->client_data_unit;
971 /* The size of gdma_wqe + client_oob_size must be less than or equal
972 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond
973 * the queue memory buffer boundary.
975 ptr = wqe_ptr + sizeof(header);
977 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) {
978 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size);
980 if (client_oob_size > wqe_req->inline_oob_size)
981 memset(ptr + wqe_req->inline_oob_size, 0,
982 client_oob_size - wqe_req->inline_oob_size);
985 return sizeof(header) + client_oob_size;
988 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr,
989 const struct gdma_wqe_request *wqe_req)
991 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
992 const u8 *address = (u8 *)wqe_req->sgl;
993 u8 *base_ptr, *end_ptr;
996 base_ptr = wq->queue_mem_ptr;
997 end_ptr = base_ptr + wq->queue_size;
998 size_to_end = (u32)(end_ptr - wqe_ptr);
1000 if (size_to_end < sgl_size) {
1001 memcpy(wqe_ptr, address, size_to_end);
1004 address += size_to_end;
1005 sgl_size -= size_to_end;
1008 memcpy(wqe_ptr, address, sgl_size);
1011 int mana_gd_post_work_request(struct gdma_queue *wq,
1012 const struct gdma_wqe_request *wqe_req,
1013 struct gdma_posted_wqe_info *wqe_info)
1015 u32 client_oob_size = wqe_req->inline_oob_size;
1016 struct gdma_context *gc;
1022 if (wqe_req->num_sge == 0)
1025 if (wq->type == GDMA_RQ) {
1026 if (client_oob_size != 0)
1029 client_oob_size = INLINE_OOB_SMALL_SIZE;
1031 max_wqe_size = GDMA_MAX_RQE_SIZE;
1033 if (client_oob_size != INLINE_OOB_SMALL_SIZE &&
1034 client_oob_size != INLINE_OOB_LARGE_SIZE)
1037 max_wqe_size = GDMA_MAX_SQE_SIZE;
1040 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge;
1041 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size +
1042 sgl_data_size, GDMA_WQE_BU_SIZE);
1043 if (wqe_size > max_wqe_size)
1046 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) {
1047 gc = wq->gdma_dev->gdma_context;
1048 dev_err(gc->dev, "unsuccessful flow control!\n");
1053 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE;
1055 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head);
1056 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size,
1057 sgl_data_size, wqe_ptr);
1058 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size)
1059 wqe_ptr -= wq->queue_size;
1061 mana_gd_write_sgl(wq, wqe_ptr, wqe_req);
1063 wq->head += wqe_size / GDMA_WQE_BU_SIZE;
1068 int mana_gd_post_and_ring(struct gdma_queue *queue,
1069 const struct gdma_wqe_request *wqe_req,
1070 struct gdma_posted_wqe_info *wqe_info)
1072 struct gdma_context *gc = queue->gdma_dev->gdma_context;
1075 err = mana_gd_post_work_request(queue, wqe_req, wqe_info);
1079 mana_gd_wq_ring_doorbell(gc, queue);
1084 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp)
1086 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe);
1087 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr;
1088 u32 owner_bits, new_bits, old_bits;
1089 struct gdma_cqe *cqe;
1091 cqe = &cq_cqe[cq->head % num_cqe];
1092 owner_bits = cqe->cqe_info.owner_bits;
1094 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK;
1095 /* Return 0 if no more entries. */
1096 if (owner_bits == old_bits)
1099 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK;
1100 /* Return -1 if overflow detected. */
1101 if (WARN_ON_ONCE(owner_bits != new_bits))
1104 /* Per GDMA spec, rmb is necessary after checking owner_bits, before
1105 * reading completion info
1109 comp->wq_num = cqe->cqe_info.wq_num;
1110 comp->is_sq = cqe->cqe_info.is_sq;
1111 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE);
1116 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe)
1121 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) {
1122 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]);
1125 cq->head -= cqe_idx;
1138 static irqreturn_t mana_gd_intr(int irq, void *arg)
1140 struct gdma_irq_context *gic = arg;
1143 gic->handler(gic->arg);
1148 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r)
1150 r->map = bitmap_zalloc(res_avail, GFP_KERNEL);
1154 r->size = res_avail;
1155 spin_lock_init(&r->lock);
1160 void mana_gd_free_res_map(struct gdma_resource *r)
1162 bitmap_free(r->map);
1167 static int mana_gd_setup_irqs(struct pci_dev *pdev)
1169 unsigned int max_queues_per_port = num_online_cpus();
1170 struct gdma_context *gc = pci_get_drvdata(pdev);
1171 struct gdma_irq_context *gic;
1172 unsigned int max_irqs;
1176 if (max_queues_per_port > MANA_MAX_NUM_QUEUES)
1177 max_queues_per_port = MANA_MAX_NUM_QUEUES;
1179 /* Need 1 interrupt for the Hardware communication Channel (HWC) */
1180 max_irqs = max_queues_per_port + 1;
1182 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX);
1186 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context),
1188 if (!gc->irq_contexts) {
1190 goto free_irq_vector;
1193 for (i = 0; i < nvec; i++) {
1194 gic = &gc->irq_contexts[i];
1195 gic->handler = NULL;
1198 irq = pci_irq_vector(pdev, i);
1204 err = request_irq(irq, mana_gd_intr, 0, "mana_intr", gic);
1209 err = mana_gd_alloc_res_map(nvec, &gc->msix_resource);
1213 gc->max_num_msix = nvec;
1214 gc->num_msix_usable = nvec;
1219 for (j = i - 1; j >= 0; j--) {
1220 irq = pci_irq_vector(pdev, j);
1221 gic = &gc->irq_contexts[j];
1225 kfree(gc->irq_contexts);
1226 gc->irq_contexts = NULL;
1228 pci_free_irq_vectors(pdev);
1232 static void mana_gd_remove_irqs(struct pci_dev *pdev)
1234 struct gdma_context *gc = pci_get_drvdata(pdev);
1235 struct gdma_irq_context *gic;
1238 if (gc->max_num_msix < 1)
1241 mana_gd_free_res_map(&gc->msix_resource);
1243 for (i = 0; i < gc->max_num_msix; i++) {
1244 irq = pci_irq_vector(pdev, i);
1248 gic = &gc->irq_contexts[i];
1252 pci_free_irq_vectors(pdev);
1254 gc->max_num_msix = 0;
1255 gc->num_msix_usable = 0;
1256 kfree(gc->irq_contexts);
1257 gc->irq_contexts = NULL;
1260 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1262 struct gdma_context *gc;
1263 void __iomem *bar0_va;
1267 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */
1268 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE);
1270 err = pci_enable_device(pdev);
1274 pci_set_master(pdev);
1276 err = pci_request_regions(pdev, "mana");
1280 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1282 goto release_region;
1285 gc = vzalloc(sizeof(*gc));
1287 goto release_region;
1289 bar0_va = pci_iomap(pdev, bar, 0);
1293 gc->bar0_va = bar0_va;
1294 gc->dev = &pdev->dev;
1296 pci_set_drvdata(pdev, gc);
1298 mana_gd_init_registers(pdev);
1300 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base);
1302 err = mana_gd_setup_irqs(pdev);
1306 mutex_init(&gc->eq_test_event_mutex);
1308 err = mana_hwc_create_channel(gc);
1312 err = mana_gd_verify_vf_version(pdev);
1316 err = mana_gd_query_max_resources(pdev);
1320 err = mana_gd_detect_devices(pdev);
1324 err = mana_probe(&gc->mana);
1331 mana_hwc_destroy_channel(gc);
1332 vfree(gc->cq_table);
1333 gc->cq_table = NULL;
1335 mana_gd_remove_irqs(pdev);
1337 pci_iounmap(pdev, bar0_va);
1341 pci_release_regions(pdev);
1343 pci_clear_master(pdev);
1344 pci_disable_device(pdev);
1345 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err);
1349 static void mana_gd_remove(struct pci_dev *pdev)
1351 struct gdma_context *gc = pci_get_drvdata(pdev);
1353 mana_remove(&gc->mana);
1355 mana_hwc_destroy_channel(gc);
1356 vfree(gc->cq_table);
1357 gc->cq_table = NULL;
1359 mana_gd_remove_irqs(pdev);
1361 pci_iounmap(pdev, gc->bar0_va);
1365 pci_release_regions(pdev);
1366 pci_clear_master(pdev);
1367 pci_disable_device(pdev);
1370 #ifndef PCI_VENDOR_ID_MICROSOFT
1371 #define PCI_VENDOR_ID_MICROSOFT 0x1414
1374 static const struct pci_device_id mana_id_table[] = {
1375 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, 0x00BA) },
1379 static struct pci_driver mana_driver = {
1381 .id_table = mana_id_table,
1382 .probe = mana_gd_probe,
1383 .remove = mana_gd_remove,
1386 module_pci_driver(mana_driver);
1388 MODULE_DEVICE_TABLE(pci, mana_id_table);
1390 MODULE_LICENSE("Dual BSD/GPL");
1391 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver");