drivers/net/ethernet/microchip/sparx5/sparx5_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Microchip Sparx5 Switch driver
   3  *
   4  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
   5  *
   6  * The Sparx5 Chip Register Model can be browsed at this location:
   7  * https://github.com/microchip-ung/sparx-5_reginfo
   8  */
   9 #include <linux/module.h>
  10 #include <linux/device.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/of.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <net/switchdev.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/io.h>
  20 #include <linux/printk.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24 #include <linux/types.h>
  25 #include <linux/reset.h>
  26
  27 #include "sparx5_main_regs.h"
  28 #include "sparx5_main.h"
  29 #include "sparx5_port.h"
  30
  31 #define QLIM_WM(fraction) \
  32         ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100)
  33 #define IO_RANGES 3
  34
  35 struct initial_port_config {
  36         u32 portno;
  37         struct device_node *node;
  38         struct sparx5_port_config conf;
  39         struct phy *serdes;
  40 };
  41
  42 struct sparx5_ram_config {
  43         void __iomem *init_reg;
  44         u32 init_val;
  45 };
  46
  47 struct sparx5_main_io_resource {
  48         enum sparx5_target id;
  49         phys_addr_t offset;
  50         int range;
  51 };
  52
  53 static const struct sparx5_main_io_resource sparx5_main_iomap[] =  {
  54         { TARGET_CPU,                         0, 0 }, /* 0x600000000 */
  55         { TARGET_FDMA,                  0x80000, 0 }, /* 0x600080000 */
  56         { TARGET_PCEP,                 0x400000, 0 }, /* 0x600400000 */
  57         { TARGET_DEV2G5,             0x10004000, 1 }, /* 0x610004000 */
  58         { TARGET_DEV5G,              0x10008000, 1 }, /* 0x610008000 */
  59         { TARGET_PCS5G_BR,           0x1000c000, 1 }, /* 0x61000c000 */
  60         { TARGET_DEV2G5 +  1,        0x10010000, 1 }, /* 0x610010000 */
  61         { TARGET_DEV5G +  1,         0x10014000, 1 }, /* 0x610014000 */
  62         { TARGET_PCS5G_BR +  1,      0x10018000, 1 }, /* 0x610018000 */
  63         { TARGET_DEV2G5 +  2,        0x1001c000, 1 }, /* 0x61001c000 */
  64         { TARGET_DEV5G +  2,         0x10020000, 1 }, /* 0x610020000 */
  65         { TARGET_PCS5G_BR +  2,      0x10024000, 1 }, /* 0x610024000 */
  66         { TARGET_DEV2G5 +  6,        0x10028000, 1 }, /* 0x610028000 */
  67         { TARGET_DEV5G +  6,         0x1002c000, 1 }, /* 0x61002c000 */
  68         { TARGET_PCS5G_BR +  6,      0x10030000, 1 }, /* 0x610030000 */
  69         { TARGET_DEV2G5 +  7,        0x10034000, 1 }, /* 0x610034000 */
  70         { TARGET_DEV5G +  7,         0x10038000, 1 }, /* 0x610038000 */
  71         { TARGET_PCS5G_BR +  7,      0x1003c000, 1 }, /* 0x61003c000 */
  72         { TARGET_DEV2G5 +  8,        0x10040000, 1 }, /* 0x610040000 */
  73         { TARGET_DEV5G +  8,         0x10044000, 1 }, /* 0x610044000 */
  74         { TARGET_PCS5G_BR +  8,      0x10048000, 1 }, /* 0x610048000 */
  75         { TARGET_DEV2G5 +  9,        0x1004c000, 1 }, /* 0x61004c000 */
  76         { TARGET_DEV5G +  9,         0x10050000, 1 }, /* 0x610050000 */
  77         { TARGET_PCS5G_BR +  9,      0x10054000, 1 }, /* 0x610054000 */
  78         { TARGET_DEV2G5 + 10,        0x10058000, 1 }, /* 0x610058000 */
  79         { TARGET_DEV5G + 10,         0x1005c000, 1 }, /* 0x61005c000 */
  80         { TARGET_PCS5G_BR + 10,      0x10060000, 1 }, /* 0x610060000 */
  81         { TARGET_DEV2G5 + 11,        0x10064000, 1 }, /* 0x610064000 */
  82         { TARGET_DEV5G + 11,         0x10068000, 1 }, /* 0x610068000 */
  83         { TARGET_PCS5G_BR + 11,      0x1006c000, 1 }, /* 0x61006c000 */
  84         { TARGET_DEV2G5 + 12,        0x10070000, 1 }, /* 0x610070000 */
  85         { TARGET_DEV10G,             0x10074000, 1 }, /* 0x610074000 */
  86         { TARGET_PCS10G_BR,          0x10078000, 1 }, /* 0x610078000 */
  87         { TARGET_DEV2G5 + 14,        0x1007c000, 1 }, /* 0x61007c000 */
  88         { TARGET_DEV10G +  2,        0x10080000, 1 }, /* 0x610080000 */
  89         { TARGET_PCS10G_BR +  2,     0x10084000, 1 }, /* 0x610084000 */
  90         { TARGET_DEV2G5 + 15,        0x10088000, 1 }, /* 0x610088000 */
  91         { TARGET_DEV10G +  3,        0x1008c000, 1 }, /* 0x61008c000 */
  92         { TARGET_PCS10G_BR +  3,     0x10090000, 1 }, /* 0x610090000 */
  93         { TARGET_DEV2G5 + 16,        0x10094000, 1 }, /* 0x610094000 */
  94         { TARGET_DEV2G5 + 17,        0x10098000, 1 }, /* 0x610098000 */
  95         { TARGET_DEV2G5 + 18,        0x1009c000, 1 }, /* 0x61009c000 */
  96         { TARGET_DEV2G5 + 19,        0x100a0000, 1 }, /* 0x6100a0000 */
  97         { TARGET_DEV2G5 + 20,        0x100a4000, 1 }, /* 0x6100a4000 */
  98         { TARGET_DEV2G5 + 21,        0x100a8000, 1 }, /* 0x6100a8000 */
  99         { TARGET_DEV2G5 + 22,        0x100ac000, 1 }, /* 0x6100ac000 */
 100         { TARGET_DEV2G5 + 23,        0x100b0000, 1 }, /* 0x6100b0000 */
 101         { TARGET_DEV2G5 + 32,        0x100b4000, 1 }, /* 0x6100b4000 */
 102         { TARGET_DEV2G5 + 33,        0x100b8000, 1 }, /* 0x6100b8000 */
 103         { TARGET_DEV2G5 + 34,        0x100bc000, 1 }, /* 0x6100bc000 */
 104         { TARGET_DEV2G5 + 35,        0x100c0000, 1 }, /* 0x6100c0000 */
 105         { TARGET_DEV2G5 + 36,        0x100c4000, 1 }, /* 0x6100c4000 */
 106         { TARGET_DEV2G5 + 37,        0x100c8000, 1 }, /* 0x6100c8000 */
 107         { TARGET_DEV2G5 + 38,        0x100cc000, 1 }, /* 0x6100cc000 */
 108         { TARGET_DEV2G5 + 39,        0x100d0000, 1 }, /* 0x6100d0000 */
 109         { TARGET_DEV2G5 + 40,        0x100d4000, 1 }, /* 0x6100d4000 */
 110         { TARGET_DEV2G5 + 41,        0x100d8000, 1 }, /* 0x6100d8000 */
 111         { TARGET_DEV2G5 + 42,        0x100dc000, 1 }, /* 0x6100dc000 */
 112         { TARGET_DEV2G5 + 43,        0x100e0000, 1 }, /* 0x6100e0000 */
 113         { TARGET_DEV2G5 + 44,        0x100e4000, 1 }, /* 0x6100e4000 */
 114         { TARGET_DEV2G5 + 45,        0x100e8000, 1 }, /* 0x6100e8000 */
 115         { TARGET_DEV2G5 + 46,        0x100ec000, 1 }, /* 0x6100ec000 */
 116         { TARGET_DEV2G5 + 47,        0x100f0000, 1 }, /* 0x6100f0000 */
 117         { TARGET_DEV2G5 + 57,        0x100f4000, 1 }, /* 0x6100f4000 */
 118         { TARGET_DEV25G +  1,        0x100f8000, 1 }, /* 0x6100f8000 */
 119         { TARGET_PCS25G_BR +  1,     0x100fc000, 1 }, /* 0x6100fc000 */
 120         { TARGET_DEV2G5 + 59,        0x10104000, 1 }, /* 0x610104000 */
 121         { TARGET_DEV25G +  3,        0x10108000, 1 }, /* 0x610108000 */
 122         { TARGET_PCS25G_BR +  3,     0x1010c000, 1 }, /* 0x61010c000 */
 123         { TARGET_DEV2G5 + 60,        0x10114000, 1 }, /* 0x610114000 */
 124         { TARGET_DEV25G +  4,        0x10118000, 1 }, /* 0x610118000 */
 125         { TARGET_PCS25G_BR +  4,     0x1011c000, 1 }, /* 0x61011c000 */
 126         { TARGET_DEV2G5 + 64,        0x10124000, 1 }, /* 0x610124000 */
 127         { TARGET_DEV5G + 12,         0x10128000, 1 }, /* 0x610128000 */
 128         { TARGET_PCS5G_BR + 12,      0x1012c000, 1 }, /* 0x61012c000 */
 129         { TARGET_PORT_CONF,          0x10130000, 1 }, /* 0x610130000 */
 130         { TARGET_DEV2G5 +  3,        0x10404000, 1 }, /* 0x610404000 */
 131         { TARGET_DEV5G +  3,         0x10408000, 1 }, /* 0x610408000 */
 132         { TARGET_PCS5G_BR +  3,      0x1040c000, 1 }, /* 0x61040c000 */
 133         { TARGET_DEV2G5 +  4,        0x10410000, 1 }, /* 0x610410000 */
 134         { TARGET_DEV5G +  4,         0x10414000, 1 }, /* 0x610414000 */
 135         { TARGET_PCS5G_BR +  4,      0x10418000, 1 }, /* 0x610418000 */
 136         { TARGET_DEV2G5 +  5,        0x1041c000, 1 }, /* 0x61041c000 */
 137         { TARGET_DEV5G +  5,         0x10420000, 1 }, /* 0x610420000 */
 138         { TARGET_PCS5G_BR +  5,      0x10424000, 1 }, /* 0x610424000 */
 139         { TARGET_DEV2G5 + 13,        0x10428000, 1 }, /* 0x610428000 */
 140         { TARGET_DEV10G +  1,        0x1042c000, 1 }, /* 0x61042c000 */
 141         { TARGET_PCS10G_BR +  1,     0x10430000, 1 }, /* 0x610430000 */
 142         { TARGET_DEV2G5 + 24,        0x10434000, 1 }, /* 0x610434000 */
 143         { TARGET_DEV2G5 + 25,        0x10438000, 1 }, /* 0x610438000 */
 144         { TARGET_DEV2G5 + 26,        0x1043c000, 1 }, /* 0x61043c000 */
 145         { TARGET_DEV2G5 + 27,        0x10440000, 1 }, /* 0x610440000 */
 146         { TARGET_DEV2G5 + 28,        0x10444000, 1 }, /* 0x610444000 */
 147         { TARGET_DEV2G5 + 29,        0x10448000, 1 }, /* 0x610448000 */
 148         { TARGET_DEV2G5 + 30,        0x1044c000, 1 }, /* 0x61044c000 */
 149         { TARGET_DEV2G5 + 31,        0x10450000, 1 }, /* 0x610450000 */
 150         { TARGET_DEV2G5 + 48,        0x10454000, 1 }, /* 0x610454000 */
 151         { TARGET_DEV10G +  4,        0x10458000, 1 }, /* 0x610458000 */
 152         { TARGET_PCS10G_BR +  4,     0x1045c000, 1 }, /* 0x61045c000 */
 153         { TARGET_DEV2G5 + 49,        0x10460000, 1 }, /* 0x610460000 */
 154         { TARGET_DEV10G +  5,        0x10464000, 1 }, /* 0x610464000 */
 155         { TARGET_PCS10G_BR +  5,     0x10468000, 1 }, /* 0x610468000 */
 156         { TARGET_DEV2G5 + 50,        0x1046c000, 1 }, /* 0x61046c000 */
 157         { TARGET_DEV10G +  6,        0x10470000, 1 }, /* 0x610470000 */
 158         { TARGET_PCS10G_BR +  6,     0x10474000, 1 }, /* 0x610474000 */
 159         { TARGET_DEV2G5 + 51,        0x10478000, 1 }, /* 0x610478000 */
 160         { TARGET_DEV10G +  7,        0x1047c000, 1 }, /* 0x61047c000 */
 161         { TARGET_PCS10G_BR +  7,     0x10480000, 1 }, /* 0x610480000 */
 162         { TARGET_DEV2G5 + 52,        0x10484000, 1 }, /* 0x610484000 */
 163         { TARGET_DEV10G +  8,        0x10488000, 1 }, /* 0x610488000 */
 164         { TARGET_PCS10G_BR +  8,     0x1048c000, 1 }, /* 0x61048c000 */
 165         { TARGET_DEV2G5 + 53,        0x10490000, 1 }, /* 0x610490000 */
 166         { TARGET_DEV10G +  9,        0x10494000, 1 }, /* 0x610494000 */
 167         { TARGET_PCS10G_BR +  9,     0x10498000, 1 }, /* 0x610498000 */
 168         { TARGET_DEV2G5 + 54,        0x1049c000, 1 }, /* 0x61049c000 */
 169         { TARGET_DEV10G + 10,        0x104a0000, 1 }, /* 0x6104a0000 */
 170         { TARGET_PCS10G_BR + 10,     0x104a4000, 1 }, /* 0x6104a4000 */
 171         { TARGET_DEV2G5 + 55,        0x104a8000, 1 }, /* 0x6104a8000 */
 172         { TARGET_DEV10G + 11,        0x104ac000, 1 }, /* 0x6104ac000 */
 173         { TARGET_PCS10G_BR + 11,     0x104b0000, 1 }, /* 0x6104b0000 */
 174         { TARGET_DEV2G5 + 56,        0x104b4000, 1 }, /* 0x6104b4000 */
 175         { TARGET_DEV25G,             0x104b8000, 1 }, /* 0x6104b8000 */
 176         { TARGET_PCS25G_BR,          0x104bc000, 1 }, /* 0x6104bc000 */
 177         { TARGET_DEV2G5 + 58,        0x104c4000, 1 }, /* 0x6104c4000 */
 178         { TARGET_DEV25G +  2,        0x104c8000, 1 }, /* 0x6104c8000 */
 179         { TARGET_PCS25G_BR +  2,     0x104cc000, 1 }, /* 0x6104cc000 */
 180         { TARGET_DEV2G5 + 61,        0x104d4000, 1 }, /* 0x6104d4000 */
 181         { TARGET_DEV25G +  5,        0x104d8000, 1 }, /* 0x6104d8000 */
 182         { TARGET_PCS25G_BR +  5,     0x104dc000, 1 }, /* 0x6104dc000 */
 183         { TARGET_DEV2G5 + 62,        0x104e4000, 1 }, /* 0x6104e4000 */
 184         { TARGET_DEV25G +  6,        0x104e8000, 1 }, /* 0x6104e8000 */
 185         { TARGET_PCS25G_BR +  6,     0x104ec000, 1 }, /* 0x6104ec000 */
 186         { TARGET_DEV2G5 + 63,        0x104f4000, 1 }, /* 0x6104f4000 */
 187         { TARGET_DEV25G +  7,        0x104f8000, 1 }, /* 0x6104f8000 */
 188         { TARGET_PCS25G_BR +  7,     0x104fc000, 1 }, /* 0x6104fc000 */
 189         { TARGET_DSM,                0x10504000, 1 }, /* 0x610504000 */
 190         { TARGET_ASM,                0x10600000, 1 }, /* 0x610600000 */
 191         { TARGET_GCB,                0x11010000, 2 }, /* 0x611010000 */
 192         { TARGET_QS,                 0x11030000, 2 }, /* 0x611030000 */
 193         { TARGET_ANA_ACL,            0x11050000, 2 }, /* 0x611050000 */
 194         { TARGET_LRN,                0x11060000, 2 }, /* 0x611060000 */
 195         { TARGET_VCAP_SUPER,         0x11080000, 2 }, /* 0x611080000 */
 196         { TARGET_QSYS,               0x110a0000, 2 }, /* 0x6110a0000 */
 197         { TARGET_QFWD,               0x110b0000, 2 }, /* 0x6110b0000 */
 198         { TARGET_XQS,                0x110c0000, 2 }, /* 0x6110c0000 */
 199         { TARGET_CLKGEN,             0x11100000, 2 }, /* 0x611100000 */
 200         { TARGET_ANA_AC_POL,         0x11200000, 2 }, /* 0x611200000 */
 201         { TARGET_QRES,               0x11280000, 2 }, /* 0x611280000 */
 202         { TARGET_EACL,               0x112c0000, 2 }, /* 0x6112c0000 */
 203         { TARGET_ANA_CL,             0x11400000, 2 }, /* 0x611400000 */
 204         { TARGET_ANA_L3,             0x11480000, 2 }, /* 0x611480000 */
 205         { TARGET_HSCH,               0x11580000, 2 }, /* 0x611580000 */
 206         { TARGET_REW,                0x11600000, 2 }, /* 0x611600000 */
 207         { TARGET_ANA_L2,             0x11800000, 2 }, /* 0x611800000 */
 208         { TARGET_ANA_AC,             0x11900000, 2 }, /* 0x611900000 */
 209         { TARGET_VOP,                0x11a00000, 2 }, /* 0x611a00000 */
 210 };
 211
 212 static int sparx5_create_targets(struct sparx5 *sparx5)
 213 {
 214         struct resource *iores[IO_RANGES];
 215         void __iomem *iomem[IO_RANGES];
 216         void __iomem *begin[IO_RANGES];
 217         int range_id[IO_RANGES];
 218         int idx, jdx;
 219
 220         for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
 221                 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
 222
 223                 if (idx == iomap->range) {
 224                         range_id[idx] = jdx;
 225                         idx++;
 226                 }
 227         }
 228         for (idx = 0; idx < IO_RANGES; idx++) {
 229                 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,
 230                                                    idx);
 231                 if (!iores[idx]) {
 232                         dev_err(sparx5->dev, "Invalid resource\n");
 233                         return -EINVAL;
 234                 }
 235                 iomem[idx] = devm_ioremap(sparx5->dev,
 236                                           iores[idx]->start,
 237                                           resource_size(iores[idx]));
 238                 if (!iomem[idx]) {
 239                         dev_err(sparx5->dev, "Unable to get switch registers: %s\n",
 240                                 iores[idx]->name);
 241                         return -ENOMEM;
 242                 }
 243                 begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset;
 244         }
 245         for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) {
 246                 const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx];
 247
 248                 sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset;
 249         }
 250         return 0;
 251 }
 252
 253 static int sparx5_create_port(struct sparx5 *sparx5,
 254                               struct initial_port_config *config)
 255 {
 256         struct sparx5_port *spx5_port;
 257         struct net_device *ndev;
 258         struct phylink *phylink;
 259         int err;
 260
 261         ndev = sparx5_create_netdev(sparx5, config->portno);
 262         if (IS_ERR(ndev)) {
 263                 dev_err(sparx5->dev, "Could not create net device: %02u\n",
 264                         config->portno);
 265                 return PTR_ERR(ndev);
 266         }
 267         spx5_port = netdev_priv(ndev);
 268         spx5_port->of_node = config->node;
 269         spx5_port->serdes = config->serdes;
 270         spx5_port->pvid = NULL_VID;
 271         spx5_port->signd_internal = true;
 272         spx5_port->signd_active_high = true;
 273         spx5_port->signd_enable = true;
 274         spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
 275         spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
 276         spx5_port->custom_etype = 0x8880; /* Vitesse */
 277         spx5_port->phylink_pcs.poll = true;
 278         spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops;
 279         sparx5->ports[config->portno] = spx5_port;
 280
 281         err = sparx5_port_init(sparx5, spx5_port, &config->conf);
 282         if (err) {
 283                 dev_err(sparx5->dev, "port init failed\n");
 284                 return err;
 285         }
 286         spx5_port->conf = config->conf;
 287
 288         /* Setup VLAN */
 289         sparx5_vlan_port_setup(sparx5, spx5_port->portno);
 290
 291         /* Create a phylink for PHY management.  Also handles SFPs */
 292         spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
 293         spx5_port->phylink_config.type = PHYLINK_NETDEV;
 294         spx5_port->phylink_config.pcs_poll = true;
 295         spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
 296                 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
 297                 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
 298
 299         __set_bit(PHY_INTERFACE_MODE_SGMII,
 300                   spx5_port->phylink_config.supported_interfaces);
 301         __set_bit(PHY_INTERFACE_MODE_QSGMII,
 302                   spx5_port->phylink_config.supported_interfaces);
 303         __set_bit(PHY_INTERFACE_MODE_1000BASEX,
 304                   spx5_port->phylink_config.supported_interfaces);
 305         __set_bit(PHY_INTERFACE_MODE_2500BASEX,
 306                   spx5_port->phylink_config.supported_interfaces);
 307
 308         if (spx5_port->conf.bandwidth == SPEED_5000 ||
 309             spx5_port->conf.bandwidth == SPEED_10000 ||
 310             spx5_port->conf.bandwidth == SPEED_25000)
 311                 __set_bit(PHY_INTERFACE_MODE_5GBASER,
 312                           spx5_port->phylink_config.supported_interfaces);
 313
 314         if (spx5_port->conf.bandwidth == SPEED_10000 ||
 315             spx5_port->conf.bandwidth == SPEED_25000)
 316                 __set_bit(PHY_INTERFACE_MODE_10GBASER,
 317                           spx5_port->phylink_config.supported_interfaces);
 318
 319         if (spx5_port->conf.bandwidth == SPEED_25000)
 320                 __set_bit(PHY_INTERFACE_MODE_25GBASER,
 321                           spx5_port->phylink_config.supported_interfaces);
 322
 323         phylink = phylink_create(&spx5_port->phylink_config,
 324                                  of_fwnode_handle(config->node),
 325                                  config->conf.phy_mode,
 326                                  &sparx5_phylink_mac_ops);
 327         if (IS_ERR(phylink))
 328                 return PTR_ERR(phylink);
 329
 330         spx5_port->phylink = phylink;
 331
 332         return 0;
 333 }
 334
 335 static int sparx5_init_ram(struct sparx5 *s5)
 336 {
 337         const struct sparx5_ram_config spx5_ram_cfg[] = {
 338                 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
 339                 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
 340                 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 341                 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 342                 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 343                 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 344                 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 345                 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 346                 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
 347                 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}
 348         };
 349         const struct sparx5_ram_config *cfg;
 350         u32 value, pending, jdx, idx;
 351
 352         for (jdx = 0; jdx < 10; jdx++) {
 353                 pending = ARRAY_SIZE(spx5_ram_cfg);
 354                 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {
 355                         cfg = &spx5_ram_cfg[idx];
 356                         if (jdx == 0) {
 357                                 writel(cfg->init_val, cfg->init_reg);
 358                         } else {
 359                                 value = readl(cfg->init_reg);
 360                                 if ((value & cfg->init_val) != cfg->init_val)
 361                                         pending--;
 362                         }
 363                 }
 364                 if (!pending)
 365                         break;
 366                 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
 367         }
 368
 369         if (pending > 0) {
 370                 /* Still initializing, should be complete in
 371                  * less than 1ms
 372                  */
 373                 dev_err(s5->dev, "Memory initialization error\n");
 374                 return -EINVAL;
 375         }
 376         return 0;
 377 }
 378
 379 static int sparx5_init_switchcore(struct sparx5 *sparx5)
 380 {
 381         u32 value;
 382         int err = 0;
 383
 384         spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
 385                  EACL_POL_EACL_CFG_EACL_FORCE_INIT,
 386                  sparx5,
 387                  EACL_POL_EACL_CFG);
 388
 389         spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
 390                  EACL_POL_EACL_CFG_EACL_FORCE_INIT,
 391                  sparx5,
 392                  EACL_POL_EACL_CFG);
 393
 394         /* Initialize memories, if not done already */
 395         value = spx5_rd(sparx5, HSCH_RESET_CFG);
 396         if (!(value & HSCH_RESET_CFG_CORE_ENA)) {
 397                 err = sparx5_init_ram(sparx5);
 398                 if (err)
 399                         return err;
 400         }
 401
 402         /* Reset counters */
 403         spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET);
 404         spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG);
 405
 406         /* Enable switch-core and queue system */
 407         spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG);
 408
 409         return 0;
 410 }
 411
 412 static int sparx5_init_coreclock(struct sparx5 *sparx5)
 413 {
 414         enum sparx5_core_clockfreq freq = sparx5->coreclock;
 415         u32 clk_div, clk_period, pol_upd_int, idx;
 416
 417         /* Verify if core clock frequency is supported on target.
 418          * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported
 419          * freq. is used
 420          */
 421         switch (sparx5->target_ct) {
 422         case SPX5_TARGET_CT_7546:
 423                 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
 424                         freq = SPX5_CORE_CLOCK_250MHZ;
 425                 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ)
 426                         freq = 0; /* Not supported */
 427                 break;
 428         case SPX5_TARGET_CT_7549:
 429         case SPX5_TARGET_CT_7552:
 430         case SPX5_TARGET_CT_7556:
 431                 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
 432                         freq = SPX5_CORE_CLOCK_500MHZ;
 433                 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ)
 434                         freq = 0; /* Not supported */
 435                 break;
 436         case SPX5_TARGET_CT_7558:
 437         case SPX5_TARGET_CT_7558TSN:
 438                 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
 439                         freq = SPX5_CORE_CLOCK_625MHZ;
 440                 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ)
 441                         freq = 0; /* Not supported */
 442                 break;
 443         case SPX5_TARGET_CT_7546TSN:
 444                 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
 445                         freq = SPX5_CORE_CLOCK_625MHZ;
 446                 break;
 447         case SPX5_TARGET_CT_7549TSN:
 448         case SPX5_TARGET_CT_7552TSN:
 449         case SPX5_TARGET_CT_7556TSN:
 450                 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
 451                         freq = SPX5_CORE_CLOCK_625MHZ;
 452                 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
 453                         freq = 0; /* Not supported */
 454                 break;
 455         default:
 456                 dev_err(sparx5->dev, "Target (%#04x) not supported\n",
 457                         sparx5->target_ct);
 458                 return -ENODEV;
 459         }
 460
 461         switch (freq) {
 462         case SPX5_CORE_CLOCK_250MHZ:
 463                 clk_div = 10;
 464                 pol_upd_int = 312;
 465                 break;
 466         case SPX5_CORE_CLOCK_500MHZ:
 467                 clk_div = 5;
 468                 pol_upd_int = 624;
 469                 break;
 470         case SPX5_CORE_CLOCK_625MHZ:
 471                 clk_div = 4;
 472                 pol_upd_int = 780;
 473                 break;
 474         default:
 475                 dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n",
 476                         sparx5->coreclock, sparx5->target_ct);
 477                 return -EINVAL;
 478         }
 479
 480         /* Update state with chosen frequency */
 481         sparx5->coreclock = freq;
 482
 483         /* Configure the LCPLL */
 484         spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
 485                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
 486                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
 487                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
 488                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
 489                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
 490                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
 491                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
 492                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
 493                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
 494                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
 495                  CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
 496                  sparx5,
 497                  CLKGEN_LCPLL1_CORE_CLK_CFG);
 498
 499         clk_period = sparx5_clk_period(freq);
 500
 501         spx5_rmw(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(clk_period / 100),
 502                  HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS,
 503                  sparx5,
 504                  HSCH_SYS_CLK_PER);
 505
 506         spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
 507                  ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS,
 508                  sparx5,
 509                  ANA_AC_POL_BDLB_DLB_CTRL);
 510
 511         spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
 512                  ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS,
 513                  sparx5,
 514                  ANA_AC_POL_SLB_DLB_CTRL);
 515
 516         spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
 517                  LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS,
 518                  sparx5,
 519                  LRN_AUTOAGE_CFG_1);
 520
 521         for (idx = 0; idx < 3; idx++)
 522                 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
 523                          GCB_SIO_CLOCK_SYS_CLK_PERIOD,
 524                          sparx5,
 525                          GCB_SIO_CLOCK(idx));
 526
 527         spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
 528                  ((256 * 1000) / clk_period),
 529                  HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY,
 530                  sparx5,
 531                  HSCH_TAS_STATEMACHINE_CFG);
 532
 533         spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
 534                  ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT,
 535                  sparx5,
 536                  ANA_AC_POL_POL_UPD_INT_CFG);
 537
 538         return 0;
 539 }
 540
 541 static int sparx5_qlim_set(struct sparx5 *sparx5)
 542 {
 543         u32 res, dp, prio;
 544
 545         for (res = 0; res < 2; res++) {
 546                 for (prio = 0; prio < 8; prio++)
 547                         spx5_wr(0xFFF, sparx5,
 548                                 QRES_RES_CFG(prio + 630 + res * 1024));
 549
 550                 for (dp = 0; dp < 4; dp++)
 551                         spx5_wr(0xFFF, sparx5,
 552                                 QRES_RES_CFG(dp + 638 + res * 1024));
 553         }
 554
 555         /* Set 80,90,95,100% of memory size for top watermarks */
 556         spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0));
 557         spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0));
 558         spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0));
 559         spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0));
 560
 561         return 0;
 562 }
 563
 564 /* Some boards needs to map the SGPIO for signal detect explicitly to the
 565  * port module
 566  */
 567 static void sparx5_board_init(struct sparx5 *sparx5)
 568 {
 569         int idx;
 570
 571         if (!sparx5->sd_sgpio_remapping)
 572                 return;
 573
 574         /* Enable SGPIO Signal Detect remapping */
 575         spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
 576                  GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
 577                  sparx5,
 578                  GCB_HW_SGPIO_SD_CFG);
 579
 580         /* Refer to LOS SGPIO */
 581         for (idx = 0; idx < SPX5_PORTS; idx++)
 582                 if (sparx5->ports[idx])
 583                         if (sparx5->ports[idx]->conf.sd_sgpio != ~0)
 584                                 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,
 585                                         sparx5,
 586                                         GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));
 587 }
 588
 589 static int sparx5_start(struct sparx5 *sparx5)
 590 {
 591         u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 592         char queue_name[32];
 593         u32 idx;
 594         int err;
 595
 596         /* Setup own UPSIDs */
 597         for (idx = 0; idx < 3; idx++) {
 598                 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));
 599                 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));
 600                 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));
 601                 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));
 602         }
 603
 604         /* Enable CPU ports */
 605         for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++)
 606                 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
 607                          QFWD_SWITCH_PORT_MODE_PORT_ENA,
 608                          sparx5,
 609                          QFWD_SWITCH_PORT_MODE(idx));
 610
 611         /* Init masks */
 612         sparx5_update_fwd(sparx5);
 613
 614         /* CPU copy CPU pgids */
 615         spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
 616                 sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU));
 617         spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1),
 618                 sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST));
 619
 620         /* Recalc injected frame FCS */
 621         for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++)
 622                 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
 623                          ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
 624                          sparx5, ANA_CL_FILTER_CTRL(idx));
 625
 626         /* Init MAC table, ageing */
 627         sparx5_mact_init(sparx5);
 628
 629         /* Setup VLANs */
 630         sparx5_vlan_init(sparx5);
 631
 632         /* Add host mode BC address (points only to CPU) */
 633         sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID);
 634
 635         /* Enable queue limitation watermarks */
 636         sparx5_qlim_set(sparx5);
 637
 638         err = sparx5_config_auto_calendar(sparx5);
 639         if (err)
 640                 return err;
 641
 642         err = sparx5_config_dsm_calendar(sparx5);
 643         if (err)
 644                 return err;
 645
 646         /* Init stats */
 647         err = sparx_stats_init(sparx5);
 648         if (err)
 649                 return err;
 650
 651         /* Init mact_sw struct */
 652         mutex_init(&sparx5->mact_lock);
 653         INIT_LIST_HEAD(&sparx5->mact_entries);
 654         snprintf(queue_name, sizeof(queue_name), "%s-mact",
 655                  dev_name(sparx5->dev));
 656         sparx5->mact_queue = create_singlethread_workqueue(queue_name);
 657         INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
 658         queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
 659                            SPX5_MACT_PULL_DELAY);
 660
 661         err = sparx5_register_netdevs(sparx5);
 662         if (err)
 663                 return err;
 664
 665         sparx5_board_init(sparx5);
 666         err = sparx5_register_notifier_blocks(sparx5);
 667
 668         /* Start Frame DMA with fallback to register based INJ/XTR */
 669         err = -ENXIO;
 670         if (sparx5->fdma_irq >= 0) {
 671                 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0)
 672                         err = devm_request_threaded_irq(sparx5->dev,
 673                                                         sparx5->fdma_irq,
 674                                                         NULL,
 675                                                         sparx5_fdma_handler,
 676                                                         IRQF_ONESHOT,
 677                                                         "sparx5-fdma", sparx5);
 678                 if (!err)
 679                         err = sparx5_fdma_start(sparx5);
 680                 if (err)
 681                         sparx5->fdma_irq = -ENXIO;
 682         } else {
 683                 sparx5->fdma_irq = -ENXIO;
 684         }
 685         if (err && sparx5->xtr_irq >= 0) {
 686                 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
 687                                        sparx5_xtr_handler, IRQF_SHARED,
 688                                        "sparx5-xtr", sparx5);
 689                 if (!err)
 690                         err = sparx5_manual_injection_mode(sparx5);
 691                 if (err)
 692                         sparx5->xtr_irq = -ENXIO;
 693         } else {
 694                 sparx5->xtr_irq = -ENXIO;
 695         }
 696         return err;
 697 }
 698
 699 static void sparx5_cleanup_ports(struct sparx5 *sparx5)
 700 {
 701         sparx5_unregister_netdevs(sparx5);
 702         sparx5_destroy_netdevs(sparx5);
 703 }
 704
 705 static int mchp_sparx5_probe(struct platform_device *pdev)
 706 {
 707         struct initial_port_config *configs, *config;
 708         struct device_node *np = pdev->dev.of_node;
 709         struct device_node *ports, *portnp;
 710         struct reset_control *reset;
 711         struct sparx5 *sparx5;
 712         int idx = 0, err = 0;
 713
 714         if (!np && !pdev->dev.platform_data)
 715                 return -ENODEV;
 716
 717         sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL);
 718         if (!sparx5)
 719                 return -ENOMEM;
 720
 721         platform_set_drvdata(pdev, sparx5);
 722         sparx5->pdev = pdev;
 723         sparx5->dev = &pdev->dev;
 724
 725         /* Do switch core reset if available */
 726         reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
 727         if (IS_ERR(reset))
 728                 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
 729                                      "Failed to get switch reset controller.\n");
 730         reset_control_reset(reset);
 731
 732         /* Default values, some from DT */
 733         sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT;
 734
 735         ports = of_get_child_by_name(np, "ethernet-ports");
 736         if (!ports) {
 737                 dev_err(sparx5->dev, "no ethernet-ports child node found\n");
 738                 return -ENODEV;
 739         }
 740         sparx5->port_count = of_get_child_count(ports);
 741
 742         configs = kcalloc(sparx5->port_count,
 743                           sizeof(struct initial_port_config), GFP_KERNEL);
 744         if (!configs) {
 745                 err = -ENOMEM;
 746                 goto cleanup_pnode;
 747         }
 748
 749         for_each_available_child_of_node(ports, portnp) {
 750                 struct sparx5_port_config *conf;
 751                 struct phy *serdes;
 752                 u32 portno;
 753
 754                 err = of_property_read_u32(portnp, "reg", &portno);
 755                 if (err) {
 756                         dev_err(sparx5->dev, "port reg property error\n");
 757                         continue;
 758                 }
 759                 config = &configs[idx];
 760                 conf = &config->conf;
 761                 conf->speed = SPEED_UNKNOWN;
 762                 conf->bandwidth = SPEED_UNKNOWN;
 763                 err = of_get_phy_mode(portnp, &conf->phy_mode);
 764                 if (err) {
 765                         dev_err(sparx5->dev, "port %u: missing phy-mode\n",
 766                                 portno);
 767                         continue;
 768                 }
 769                 err = of_property_read_u32(portnp, "microchip,bandwidth",
 770                                            &conf->bandwidth);
 771                 if (err) {
 772                         dev_err(sparx5->dev, "port %u: missing bandwidth\n",
 773                                 portno);
 774                         continue;
 775                 }
 776                 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio);
 777                 if (err)
 778                         conf->sd_sgpio = ~0;
 779                 else
 780                         sparx5->sd_sgpio_remapping = true;
 781                 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
 782                 if (IS_ERR(serdes)) {
 783                         err = dev_err_probe(sparx5->dev, PTR_ERR(serdes),
 784                                             "port %u: missing serdes\n",
 785                                             portno);
 786                         of_node_put(portnp);
 787                         goto cleanup_config;
 788                 }
 789                 config->portno = portno;
 790                 config->node = portnp;
 791                 config->serdes = serdes;
 792
 793                 conf->media = PHY_MEDIA_DAC;
 794                 conf->serdes_reset = true;
 795                 conf->portmode = conf->phy_mode;
 796                 conf->power_down = true;
 797                 idx++;
 798         }
 799
 800         err = sparx5_create_targets(sparx5);
 801         if (err)
 802                 goto cleanup_config;
 803
 804         if (!of_get_mac_address(np, sparx5->base_mac)) {
 805                 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
 806                 eth_random_addr(sparx5->base_mac);
 807                 sparx5->base_mac[5] = 0;
 808         }
 809
 810         sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
 811         sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
 812
 813         /* Read chip ID to check CPU interface */
 814         sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
 815
 816         sparx5->target_ct = (enum spx5_target_chiptype)
 817                 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id);
 818
 819         /* Initialize Switchcore and internal RAMs */
 820         err = sparx5_init_switchcore(sparx5);
 821         if (err) {
 822                 dev_err(sparx5->dev, "Switchcore initialization error\n");
 823                 goto cleanup_config;
 824         }
 825
 826         /* Initialize the LC-PLL (core clock) and set affected registers */
 827         err = sparx5_init_coreclock(sparx5);
 828         if (err) {
 829                 dev_err(sparx5->dev, "LC-PLL initialization error\n");
 830                 goto cleanup_config;
 831         }
 832
 833         for (idx = 0; idx < sparx5->port_count; ++idx) {
 834                 config = &configs[idx];
 835                 if (!config->node)
 836                         continue;
 837
 838                 err = sparx5_create_port(sparx5, config);
 839                 if (err) {
 840                         dev_err(sparx5->dev, "port create error\n");
 841                         goto cleanup_ports;
 842                 }
 843         }
 844
 845         err = sparx5_start(sparx5);
 846         if (err) {
 847                 dev_err(sparx5->dev, "Start failed\n");
 848                 goto cleanup_ports;
 849         }
 850         goto cleanup_config;
 851
 852 cleanup_ports:
 853         sparx5_cleanup_ports(sparx5);
 854 cleanup_config:
 855         kfree(configs);
 856 cleanup_pnode:
 857         of_node_put(ports);
 858         return err;
 859 }
 860
 861 static int mchp_sparx5_remove(struct platform_device *pdev)
 862 {
 863         struct sparx5 *sparx5 = platform_get_drvdata(pdev);
 864
 865         if (sparx5->xtr_irq) {
 866                 disable_irq(sparx5->xtr_irq);
 867                 sparx5->xtr_irq = -ENXIO;
 868         }
 869         if (sparx5->fdma_irq) {
 870                 disable_irq(sparx5->fdma_irq);
 871                 sparx5->fdma_irq = -ENXIO;
 872         }
 873         sparx5_fdma_stop(sparx5);
 874         sparx5_cleanup_ports(sparx5);
 875         /* Unregister netdevs */
 876         sparx5_unregister_notifier_blocks(sparx5);
 877
 878         return 0;
 879 }
 880
 881 static const struct of_device_id mchp_sparx5_match[] = {
 882         { .compatible = "microchip,sparx5-switch" },
 883         { }
 884 };
 885 MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
 886
 887 static struct platform_driver mchp_sparx5_driver = {
 888         .probe = mchp_sparx5_probe,
 889         .remove = mchp_sparx5_remove,
 890         .driver = {
 891                 .name = "sparx5-switch",
 892                 .of_match_table = mchp_sparx5_match,
 893         },
 894 };
 895
 896 module_platform_driver(mchp_sparx5_driver);
 897
 898 MODULE_DESCRIPTION("Microchip Sparx5 switch driver");
 899 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
 900 MODULE_LICENSE("Dual MIT/GPL");