1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2018 Microchip Technology Inc. */
8 #include "lan743x_ptp.h"
10 #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>"
11 #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver"
12 #define DRIVER_NAME "lan743x"
14 /* Register Definitions */
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
19 #define ID_REV_ID_LAN743X_ (0x74300000)
20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22 #define ID_REV_ID_A0X1_ (0xA0010000)
23 #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
26 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
27 #define ID_REV_CHIP_REV_A0_ (0x00000000)
28 #define ID_REV_CHIP_REV_B0_ (0x00000010)
30 #define FPGA_REV (0x04)
31 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
32 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
33 #define FPGA_SGMII_OP BIT(24)
35 #define STRAP_READ (0x0C)
36 #define STRAP_READ_USE_SGMII_EN_ BIT(22)
37 #define STRAP_READ_SGMII_EN_ BIT(6)
38 #define STRAP_READ_SGMII_REFCLK_ BIT(5)
39 #define STRAP_READ_SGMII_2_5G_ BIT(4)
40 #define STRAP_READ_BASE_X_ BIT(3)
41 #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
42 #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1)
43 #define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
45 #define HW_CFG (0x010)
46 #define HW_CFG_RST_PROTECT_PCIE_ BIT(19)
47 #define HW_CFG_HOT_RESET_DIS_ BIT(15)
48 #define HW_CFG_D3_VAUX_OVR_ BIT(14)
49 #define HW_CFG_D3_RESET_DIS_ BIT(13)
50 #define HW_CFG_RST_PROTECT_ BIT(12)
51 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
52 #define HW_CFG_EE_OTP_RELOAD_ BIT(4)
53 #define HW_CFG_LRST_ BIT(1)
55 #define PMT_CTL (0x014)
56 #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27)
57 #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25)
58 #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24)
59 #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23)
60 #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18)
61 #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15)
62 #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13)
63 #define PMT_CTL_READY_ BIT(7)
64 #define PMT_CTL_ETH_PHY_RST_ BIT(4)
65 #define PMT_CTL_WOL_EN_ BIT(3)
66 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
67 #define PMT_CTL_WUPS_MASK_ (0x00000003)
69 #define DP_SEL (0x024)
70 #define DP_SEL_DPRDY_ BIT(31)
71 #define DP_SEL_MASK_ (0x0000001F)
72 #define DP_SEL_RFE_RAM (0x00000001)
74 #define DP_SEL_VHF_HASH_LEN (16)
75 #define DP_SEL_VHF_VLAN_LEN (128)
77 #define DP_CMD (0x028)
78 #define DP_CMD_WRITE_ (0x00000001)
80 #define DP_ADDR (0x02C)
82 #define DP_DATA_0 (0x030)
84 #define E2P_CMD (0x040)
85 #define E2P_CMD_EPC_BUSY_ BIT(31)
86 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
87 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
88 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
89 #define E2P_CMD_EPC_TIMEOUT_ BIT(10)
90 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
92 #define E2P_DATA (0x044)
94 /* Hearthstone top level & System Reg Addresses */
95 #define ETH_CTRL_REG_ADDR_BASE (0x0000)
96 #define ETH_SYS_REG_ADDR_BASE (0x4000)
97 #define CONFIG_REG_ADDR_BASE (0x0000)
98 #define ETH_EEPROM_REG_ADDR_BASE (0x0E00)
99 #define ETH_OTP_REG_ADDR_BASE (0x1000)
100 #define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)
101 #define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \
102 CONFIG_REG_ADDR_BASE + \
103 GEN_SYS_CONFIG_LOAD_STARTED_REG)
104 #define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4)
105 #define SYS_LOCK_REG (0x00A0)
106 #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7)
107 #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5)
108 #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4)
109 #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3)
110 #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
111 #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1)
112 #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)
113 #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \
114 CONFIG_REG_ADDR_BASE + \
116 #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \
117 ETH_EEPROM_REG_ADDR_BASE)
118 #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)
119 #define HS_E2P_CMD_EPC_BUSY_ BIT(31)
120 #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28)
121 #define HS_E2P_CMD_EPC_CMD_READ_ (0x0)
122 #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17)
123 #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)
124 #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)
125 #define HS_E2P_DATA_MASK_ GENMASK(7, 0)
126 #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)
127 #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)
128 #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12)
129 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
130 #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)
131 #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)
133 #define GPIO_CFG0 (0x050)
134 #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
135 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
137 #define GPIO_CFG1 (0x054)
138 #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
139 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
141 #define GPIO_CFG2 (0x058)
142 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
144 #define GPIO_CFG3 (0x05C)
145 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
146 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
148 #define FCT_RX_CTL (0xAC)
149 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
150 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
151 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel))
153 #define FCT_TX_CTL (0xC4)
154 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel))
155 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel))
156 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel))
158 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
159 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
160 #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \
161 ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_)
162 #define FCT_FLOW_CTL_REQ_EN_ BIT(7)
163 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
164 #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \
165 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
167 #define MAC_CR (0x100)
168 #define MAC_CR_MII_EN_ BIT(19)
169 #define MAC_CR_EEE_EN_ BIT(17)
170 #define MAC_CR_ADD_ BIT(12)
171 #define MAC_CR_ASD_ BIT(11)
172 #define MAC_CR_CNTR_RST_ BIT(5)
173 #define MAC_CR_DPX_ BIT(3)
174 #define MAC_CR_CFG_H_ BIT(2)
175 #define MAC_CR_CFG_L_ BIT(1)
176 #define MAC_CR_RST_ BIT(0)
178 #define MAC_RX (0x104)
179 #define MAC_RX_MAX_SIZE_SHIFT_ (16)
180 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
181 #define MAC_RX_RXD_ BIT(1)
182 #define MAC_RX_RXEN_ BIT(0)
184 #define MAC_TX (0x108)
185 #define MAC_TX_TXD_ BIT(1)
186 #define MAC_TX_TXEN_ BIT(0)
188 #define MAC_FLOW (0x10C)
189 #define MAC_FLOW_CR_TX_FCEN_ BIT(30)
190 #define MAC_FLOW_CR_RX_FCEN_ BIT(29)
191 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
193 #define MAC_RX_ADDRH (0x118)
195 #define MAC_RX_ADDRL (0x11C)
197 #define MAC_MII_ACC (0x120)
198 #define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16)
199 #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
200 #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
201 #define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1)
202 #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)
203 #define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3)
204 #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)
205 #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
206 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
207 #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
208 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
209 #define MAC_MII_ACC_MII_READ_ (0x00000000)
210 #define MAC_MII_ACC_MII_WRITE_ (0x00000002)
211 #define MAC_MII_ACC_MII_BUSY_ BIT(0)
213 #define MAC_MII_ACC_MIIMMD_SHIFT_ (6)
214 #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
215 #define MAC_MII_ACC_MIICL45_ BIT(3)
216 #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
217 #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
218 #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
219 #define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
220 #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
222 #define MAC_MII_DATA (0x124)
224 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
226 #define MAC_WUCSR (0x140)
227 #define MAC_MP_SO_EN_ BIT(21)
228 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
229 #define MAC_WUCSR_PFDA_EN_ BIT(3)
230 #define MAC_WUCSR_WAKE_EN_ BIT(2)
231 #define MAC_WUCSR_MPEN_ BIT(1)
232 #define MAC_WUCSR_BCST_EN_ BIT(0)
234 #define MAC_WK_SRC (0x144)
235 #define MAC_MP_SO_HI (0x148)
236 #define MAC_MP_SO_LO (0x14C)
238 #define MAC_WUF_CFG0 (0x150)
239 #define MAC_NUM_OF_WUF_CFG (32)
240 #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0)
241 #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index)))
242 #define MAC_WUF_CFG_EN_ BIT(31)
243 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
244 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
245 #define MAC_WUF_CFG_OFFSET_SHIFT_ (16)
246 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
248 #define MAC_WUF_MASK0_0 (0x200)
249 #define MAC_WUF_MASK0_1 (0x204)
250 #define MAC_WUF_MASK0_2 (0x208)
251 #define MAC_WUF_MASK0_3 (0x20C)
252 #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0)
253 #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1)
254 #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2)
255 #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3)
256 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
257 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
258 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
259 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
261 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
262 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
263 #define RFE_ADDR_FILT_HI_VALID_ BIT(31)
265 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
266 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
268 #define RFE_CTL (0x508)
269 #define RFE_CTL_AB_ BIT(10)
270 #define RFE_CTL_AM_ BIT(9)
271 #define RFE_CTL_AU_ BIT(8)
272 #define RFE_CTL_MCAST_HASH_ BIT(3)
273 #define RFE_CTL_DA_PERFECT_ BIT(1)
275 #define RFE_RSS_CFG (0x554)
276 #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16)
277 #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15)
278 #define RFE_RSS_CFG_IPV6_EX_ BIT(14)
279 #define RFE_RSS_CFG_UDP_IPV6_ BIT(13)
280 #define RFE_RSS_CFG_TCP_IPV6_ BIT(12)
281 #define RFE_RSS_CFG_IPV6_ BIT(11)
282 #define RFE_RSS_CFG_UDP_IPV4_ BIT(10)
283 #define RFE_RSS_CFG_TCP_IPV4_ BIT(9)
284 #define RFE_RSS_CFG_IPV4_ BIT(8)
285 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
286 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
287 #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1)
288 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
290 #define RFE_HASH_KEY(index) (0x558 + (index << 2))
292 #define RFE_INDX(index) (0x580 + (index << 2))
294 #define MAC_WUCSR2 (0x600)
296 #define SGMII_ACC (0x720)
297 #define SGMII_ACC_SGMII_BZY_ BIT(31)
298 #define SGMII_ACC_SGMII_WR_ BIT(30)
299 #define SGMII_ACC_SGMII_MMD_SHIFT_ (16)
300 #define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16)
301 #define SGMII_ACC_SGMII_MMD_VSR_ BIT(15)
302 #define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)
303 #define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)
304 #define SGMII_DATA (0x724)
305 #define SGMII_DATA_SHIFT_ (0)
306 #define SGMII_DATA_MASK_ GENMASK(15, 0)
307 #define SGMII_CTL (0x728)
308 #define SGMII_CTL_SGMII_ENABLE_ BIT(31)
309 #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)
310 #define SGMII_CTL_SGMII_POWER_DN_ BIT(1)
312 /* Vendor Specific SGMII MMD details */
313 #define SR_VSMMD_PCS_ID1 0x0004
314 #define SR_VSMMD_PCS_ID2 0x0005
315 #define SR_VSMMD_STS 0x0008
316 #define SR_VSMMD_CTRL 0x0009
318 #define VR_MII_DIG_CTRL1 0x8000
319 #define VR_MII_DIG_CTRL1_VR_RST_ BIT(15)
320 #define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14)
321 #define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13)
322 #define VR_MII_DIG_CTRL1_CS_EN_ BIT(10)
323 #define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9)
324 #define VR_MII_DIG_CTRL1_INIT_ BIT(8)
325 #define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4)
326 #define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3)
327 #define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2)
328 #define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1)
329 #define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)
330 #define VR_MII_AN_CTRL 0x8001
331 #define VR_MII_AN_CTRL_MII_CTRL_ BIT(8)
332 #define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4)
333 #define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3)
334 #define VR_MII_AN_CTRL_1000BASE_X_ (0)
335 #define VR_MII_AN_CTRL_SGMII_MODE_ (2)
336 #define VR_MII_AN_CTRL_QSGMII_MODE_ (3)
337 #define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1)
338 #define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)
339 #define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)
340 #define VR_MII_AN_INTR_STS 0x8002
341 #define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4)
342 #define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)
343 #define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3)
344 #define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2)
345 #define VR_MII_AN_INTR_STS_10_MBPS_ (0)
346 #define VR_MII_AN_INTR_STS_FDX_ BIT(1)
347 #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)
349 #define VR_MII_LINK_TIMER_CTRL 0x800A
350 #define VR_MII_DIG_STS 0x8010
351 #define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)
352 #define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2)
353 #define VR_MII_GEN2_4_MPLL_CTRL0 0x8078
354 #define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12)
355 #define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4)
356 #define VR_MII_GEN2_4_MPLL_CTRL1 0x8079
357 #define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)
358 #define VR_MII_BAUD_RATE_3P125GBPS (3125)
359 #define VR_MII_BAUD_RATE_1P25GBPS (1250)
360 #define VR_MII_MPLL_MULTIPLIER_125 (125)
361 #define VR_MII_MPLL_MULTIPLIER_100 (100)
362 #define VR_MII_MPLL_MULTIPLIER_50 (50)
363 #define VR_MII_MPLL_MULTIPLIER_40 (40)
364 #define VR_MII_GEN2_4_MISC_CTRL1 0x809A
365 #define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)
366 #define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2)
367 #define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)
368 #define VR_MII_MPLL_BAUD_CLK (0)
369 #define VR_MII_MPLL_BAUD_CLK_DIV_2 (1)
370 #define VR_MII_MPLL_BAUD_CLK_DIV_4 (2)
372 #define INT_STS (0x780)
373 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
374 #define INT_BIT_ALL_RX_ (0x0F000000)
375 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel))
376 #define INT_BIT_ALL_TX_ (0x000F0000)
377 #define INT_BIT_SW_GP_ BIT(9)
378 #define INT_BIT_1588_ BIT(7)
379 #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_)
380 #define INT_BIT_MAS_ BIT(0)
382 #define INT_SET (0x784)
384 #define INT_EN_SET (0x788)
386 #define INT_EN_CLR (0x78C)
388 #define INT_STS_R2C (0x790)
390 #define INT_VEC_EN_SET (0x794)
391 #define INT_VEC_EN_CLR (0x798)
392 #define INT_VEC_EN_AUTO_CLR (0x79C)
393 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
395 #define INT_VEC_MAP0 (0x7A0)
396 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \
397 (((u32)(vector)) << ((channel) << 2))
399 #define INT_VEC_MAP1 (0x7A4)
400 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \
401 (((u32)(vector)) << ((channel) << 2))
403 #define INT_VEC_MAP2 (0x7A8)
405 #define INT_MOD_MAP0 (0x7B0)
407 #define INT_MOD_MAP1 (0x7B4)
409 #define INT_MOD_MAP2 (0x7B8)
411 #define INT_MOD_CFG0 (0x7C0)
412 #define INT_MOD_CFG1 (0x7C4)
413 #define INT_MOD_CFG2 (0x7C8)
414 #define INT_MOD_CFG3 (0x7CC)
415 #define INT_MOD_CFG4 (0x7D0)
416 #define INT_MOD_CFG5 (0x7D4)
417 #define INT_MOD_CFG6 (0x7D8)
418 #define INT_MOD_CFG7 (0x7DC)
419 #define INT_MOD_CFG8 (0x7E0)
420 #define INT_MOD_CFG9 (0x7E4)
422 #define PTP_CMD_CTL (0x0A00)
423 #define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13)
424 #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6)
425 #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5)
426 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
427 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
428 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
429 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1)
430 #define PTP_CMD_CTL_PTP_RESET_ BIT(0)
431 #define PTP_GENERAL_CONFIG (0x0A04)
432 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
433 (0x7 << (1 + ((channel) << 2)))
434 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
435 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1)
436 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
437 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3)
438 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4)
439 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5)
440 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6)
441 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
442 (((value) & 0x7) << (1 + ((channel) << 2)))
443 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2))
445 #define HS_PTP_GENERAL_CONFIG (0x0A04)
446 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \
447 (0xf << (4 + ((channel) << 2)))
448 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
449 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1)
450 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2)
451 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3)
452 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4)
453 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5)
454 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6)
455 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7)
456 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8)
457 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9)
458 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10)
459 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11)
460 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12)
461 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13)
462 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14)
463 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15)
464 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \
465 (((value) & 0xf) << (4 + ((channel) << 2)))
466 #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2)))
467 #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2))
469 #define PTP_INT_STS (0x0A08)
470 #define PTP_INT_IO_FE_MASK_ GENMASK(31, 24)
471 #define PTP_INT_IO_FE_SHIFT_ (24)
472 #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel))
473 #define PTP_INT_IO_RE_MASK_ GENMASK(23, 16)
474 #define PTP_INT_IO_RE_SHIFT_ (16)
475 #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel))
476 #define PTP_INT_TX_TS_OVRFL_INT_ BIT(14)
477 #define PTP_INT_TX_SWTS_ERR_INT_ BIT(13)
478 #define PTP_INT_TX_TS_INT_ BIT(12)
479 #define PTP_INT_RX_TS_OVRFL_INT_ BIT(9)
480 #define PTP_INT_RX_TS_INT_ BIT(8)
481 #define PTP_INT_TIMER_INT_B_ BIT(1)
482 #define PTP_INT_TIMER_INT_A_ BIT(0)
483 #define PTP_INT_EN_SET (0x0A0C)
484 #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel))
485 #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel))
486 #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel)
487 #define PTP_INT_EN_CLR (0x0A10)
488 #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel))
489 #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel))
490 #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13)
491 #define PTP_INT_BIT_TX_TS_ BIT(12)
492 #define PTP_INT_BIT_TIMER_B_ BIT(1)
493 #define PTP_INT_BIT_TIMER_A_ BIT(0)
495 #define PTP_CLOCK_SEC (0x0A14)
496 #define PTP_CLOCK_NS (0x0A18)
497 #define PTP_CLOCK_SUBNS (0x0A1C)
498 #define PTP_CLOCK_RATE_ADJ (0x0A20)
499 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31)
500 #define PTP_CLOCK_STEP_ADJ (0x0A2C)
501 #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31)
502 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
503 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
504 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
505 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
506 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
507 #define PTP_LTC_SET_SEC_HI (0x0A50)
508 #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
509 #define PTP_VERSION (0x0A54)
510 #define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24)
511 #define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16)
512 #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8)
513 #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)
514 #define PTP_IO_SEL (0x0A58)
515 #define PTP_IO_SEL_MASK_ GENMASK(10, 8)
516 #define PTP_IO_SEL_SHIFT_ (8)
517 #define PTP_LATENCY (0x0A5C)
518 #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16)
519 #define PTP_LATENCY_RX_SET_(rx_latency) \
520 (((u32)(rx_latency)) & 0x0000FFFF)
521 #define PTP_CAP_INFO (0x0A60)
522 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
524 #define PTP_TX_MOD (0x0AA4)
525 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
527 #define PTP_TX_MOD2 (0x0AA8)
528 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
530 #define PTP_TX_EGRESS_SEC (0x0AAC)
531 #define PTP_TX_EGRESS_NS (0x0AB0)
532 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
533 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
534 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
535 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
537 #define PTP_TX_MSG_HEADER (0x0AB4)
538 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
539 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
541 #define PTP_TX_CAP_INFO (0x0AB8)
542 #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)
543 #define PTP_TX_DOMAIN (0x0ABC)
544 #define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16)
545 #define PTP_TX_DOMAIN_RANGE_EN_ BIT(15)
546 #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)
547 #define PTP_TX_SDOID (0x0AC0)
548 #define PTP_TX_SDOID_MASK_ GENMASK(23, 16)
549 #define PTP_TX_SDOID_RANGE_EN_ BIT(15)
550 #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)
551 #define PTP_IO_CAP_CONFIG (0x0AC4)
552 #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel))
553 #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel))
554 #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel))
555 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))
556 #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)
557 #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)
558 #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)
559 #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)
560 #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)
561 #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel))
562 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))
563 #define PTP_IO_PIN_CFG (0x0ADC)
564 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))
565 #define PTP_LTC_RD_SEC_HI (0x0AF0)
566 #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
567 #define PTP_LTC_RD_SEC_LO (0x0AF4)
568 #define PTP_LTC_RD_NS (0x0AF8)
569 #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)
570 #define PTP_LTC_RD_SUBNS (0x0AFC)
571 #define PTP_RX_USER_MAC_HI (0x0B00)
572 #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
573 #define PTP_RX_USER_MAC_LO (0x0B04)
574 #define PTP_RX_USER_IP_ADDR_0 (0x0B20)
575 #define PTP_RX_USER_IP_ADDR_1 (0x0B24)
576 #define PTP_RX_USER_IP_ADDR_2 (0x0B28)
577 #define PTP_RX_USER_IP_ADDR_3 (0x0B2C)
578 #define PTP_RX_USER_IP_MASK_0 (0x0B30)
579 #define PTP_RX_USER_IP_MASK_1 (0x0B34)
580 #define PTP_RX_USER_IP_MASK_2 (0x0B38)
581 #define PTP_RX_USER_IP_MASK_3 (0x0B3C)
582 #define PTP_TX_USER_MAC_HI (0x0B40)
583 #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
584 #define PTP_TX_USER_MAC_LO (0x0B44)
585 #define PTP_TX_USER_IP_ADDR_0 (0x0B60)
586 #define PTP_TX_USER_IP_ADDR_1 (0x0B64)
587 #define PTP_TX_USER_IP_ADDR_2 (0x0B68)
588 #define PTP_TX_USER_IP_ADDR_3 (0x0B6C)
589 #define PTP_TX_USER_IP_MASK_0 (0x0B70)
590 #define PTP_TX_USER_IP_MASK_1 (0x0B74)
591 #define PTP_TX_USER_IP_MASK_2 (0x0B78)
592 #define PTP_TX_USER_IP_MASK_3 (0x0B7C)
594 #define DMAC_CFG (0xC00)
595 #define DMAC_CFG_COAL_EN_ BIT(16)
596 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
597 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
598 #define DMAC_CFG_MAX_READ_REQ_SET_(val) \
599 ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_)
600 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
601 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
602 #define DMAC_CFG_MAX_DSPACE_64_ BIT(1)
603 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
605 #define DMAC_COAL_CFG (0xC04)
606 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
607 #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \
608 ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_)
609 #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19)
610 #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18)
611 #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17)
612 #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16)
613 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
614 #define DMAC_COAL_CFG_TX_THRES_SET_(val) \
615 ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_)
616 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
617 #define DMAC_COAL_CFG_RX_THRES_SET_(val) \
618 (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_)
620 #define DMAC_OBFF_CFG (0xC08)
621 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
622 #define DMAC_OBFF_TX_THRES_SET_(val) \
623 ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_)
624 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
625 #define DMAC_OBFF_RX_THRES_SET_(val) \
626 (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_)
628 #define DMAC_CMD (0xC0C)
629 #define DMAC_CMD_SWR_ BIT(31)
630 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel))
631 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel))
632 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel))
633 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel))
634 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel))
635 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
637 #define DMAC_INT_STS (0xC10)
638 #define DMAC_INT_EN_SET (0xC14)
639 #define DMAC_INT_EN_CLR (0xC18)
640 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel))
641 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
643 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
644 #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30)
645 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
646 #define RX_CFG_A_RX_WB_THRES_SET_(val) \
647 ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_)
648 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
649 #define RX_CFG_A_RX_PF_THRES_SET_(val) \
650 ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_)
651 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
652 #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \
653 ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_)
654 #define RX_CFG_A_RX_HP_WB_EN_ BIT(5)
656 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
657 #define RX_CFG_B_TS_ALL_RX_ BIT(29)
658 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
659 #define RX_CFG_B_RX_PAD_0_ (0x00000000)
660 #define RX_CFG_B_RX_PAD_2_ (0x02000000)
661 #define RX_CFG_B_RDMABL_512_ (0x00040000)
662 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
664 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
666 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
668 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
670 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
672 #define RX_HEAD(channel) (0xC58 + ((channel) << 6))
674 #define RX_TAIL(channel) (0xC5C + ((channel) << 6))
675 #define RX_TAIL_SET_TOP_INT_EN_ BIT(30)
676 #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
678 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
679 #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6)
680 #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4)
681 #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3)
682 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
684 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
685 #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30)
686 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
687 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
688 #define TX_CFG_A_TX_PF_THRES_SET_(value) \
689 ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_)
690 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
691 #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \
692 ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_)
693 #define TX_CFG_A_TX_HP_WB_EN_ BIT(5)
694 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
695 #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \
696 (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_)
698 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
699 #define TX_CFG_B_TDMABL_512_ (0x00040000)
700 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
702 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
704 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
706 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
708 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
710 #define TX_HEAD(channel) (0xD58 + ((channel) << 6))
712 #define TX_TAIL(channel) (0xD5C + ((channel) << 6))
713 #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31)
714 #define TX_TAIL_SET_TOP_INT_EN_ BIT(30)
715 #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29)
717 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
718 #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6)
719 #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5)
720 #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4)
721 #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
722 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
724 #define OTP_PWR_DN (0x1000)
725 #define OTP_PWR_DN_PWRDN_N_ BIT(0)
727 #define OTP_ADDR_HIGH (0x1004)
728 #define OTP_ADDR_LOW (0x1008)
730 #define OTP_PRGM_DATA (0x1010)
732 #define OTP_PRGM_MODE (0x1014)
733 #define OTP_PRGM_MODE_BYTE_ BIT(0)
735 #define OTP_READ_DATA (0x1018)
737 #define OTP_FUNC_CMD (0x1020)
738 #define OTP_FUNC_CMD_READ_ BIT(0)
740 #define OTP_TST_CMD (0x1024)
741 #define OTP_TST_CMD_PRGVRFY_ BIT(3)
743 #define OTP_CMD_GO (0x1028)
744 #define OTP_CMD_GO_GO_ BIT(0)
746 #define OTP_STATUS (0x1030)
747 #define OTP_STATUS_BUSY_ BIT(0)
749 /* Hearthstone OTP block registers */
750 #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \
751 ETH_OTP_REG_ADDR_BASE)
752 #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)
753 #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)
754 #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)
755 #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)
756 #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)
757 #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)
758 #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)
759 #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)
760 #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)
761 #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)
763 /* MAC statistics registers */
764 #define STAT_RX_FCS_ERRORS (0x1200)
765 #define STAT_RX_ALIGNMENT_ERRORS (0x1204)
766 #define STAT_RX_FRAGMENT_ERRORS (0x1208)
767 #define STAT_RX_JABBER_ERRORS (0x120C)
768 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
769 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
770 #define STAT_RX_DROPPED_FRAMES (0x1218)
771 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
772 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
773 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
774 #define STAT_RX_UNICAST_FRAMES (0x1228)
775 #define STAT_RX_BROADCAST_FRAMES (0x122C)
776 #define STAT_RX_MULTICAST_FRAMES (0x1230)
777 #define STAT_RX_PAUSE_FRAMES (0x1234)
778 #define STAT_RX_64_BYTE_FRAMES (0x1238)
779 #define STAT_RX_65_127_BYTE_FRAMES (0x123C)
780 #define STAT_RX_128_255_BYTE_FRAMES (0x1240)
781 #define STAT_RX_256_511_BYTES_FRAMES (0x1244)
782 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
783 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
784 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
785 #define STAT_RX_TOTAL_FRAMES (0x1254)
786 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
787 #define STAT_EEE_RX_LPI_TIME (0x125C)
788 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
790 #define STAT_TX_FCS_ERRORS (0x1280)
791 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
792 #define STAT_TX_CARRIER_ERRORS (0x1288)
793 #define STAT_TX_BAD_BYTE_COUNT (0x128C)
794 #define STAT_TX_SINGLE_COLLISIONS (0x1290)
795 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
796 #define STAT_TX_EXCESSIVE_COLLISION (0x1298)
797 #define STAT_TX_LATE_COLLISIONS (0x129C)
798 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
799 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
800 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
801 #define STAT_TX_UNICAST_FRAMES (0x12AC)
802 #define STAT_TX_BROADCAST_FRAMES (0x12B0)
803 #define STAT_TX_MULTICAST_FRAMES (0x12B4)
804 #define STAT_TX_PAUSE_FRAMES (0x12B8)
805 #define STAT_TX_64_BYTE_FRAMES (0x12BC)
806 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
807 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
808 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
809 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
810 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
811 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
812 #define STAT_TX_TOTAL_FRAMES (0x12D8)
813 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
814 #define STAT_EEE_TX_LPI_TIME (0x12E0)
815 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
817 /* End of Register definitions */
819 #define LAN743X_MAX_RX_CHANNELS (4)
820 #define LAN743X_MAX_TX_CHANNELS (1)
821 #define PCI11X1X_MAX_TX_CHANNELS (4)
822 struct lan743x_adapter;
824 #define LAN743X_USED_RX_CHANNELS (4)
825 #define LAN743X_USED_TX_CHANNELS (1)
826 #define PCI11X1X_USED_TX_CHANNELS (4)
827 #define LAN743X_INT_MOD (400)
829 #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS)
830 #error Invalid LAN743X_USED_RX_CHANNELS
832 #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS)
833 #error Invalid LAN743X_USED_TX_CHANNELS
835 #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS)
836 #error Invalid PCI11X1X_USED_TX_CHANNELS
840 /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */
841 #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR
842 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
843 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
844 #define PCI_DEVICE_ID_SMSC_A011 (0xA011)
845 #define PCI_DEVICE_ID_SMSC_A041 (0xA041)
847 #define PCI_CONFIG_LENGTH (0x1000)
850 #define CSR_LENGTH (0x2000)
852 #define LAN743X_CSR_FLAG_IS_A0 BIT(0)
853 #define LAN743X_CSR_FLAG_IS_B0 BIT(1)
854 #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8)
858 u8 __iomem *csr_address;
864 typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags);
866 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
867 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1)
868 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
869 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3)
870 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4)
871 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5)
872 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6)
873 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7)
874 #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8)
875 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9)
876 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10)
877 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11)
878 #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12)
879 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13)
880 #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14)
881 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15)
883 struct lan743x_vector {
886 struct lan743x_adapter *adapter;
889 lan743x_vector_handler handler;
893 #define LAN743X_MAX_VECTOR_COUNT (8)
894 #define PCI11X1X_MAX_VECTOR_COUNT (16)
896 struct lan743x_intr {
901 struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT];
902 int number_of_vectors;
905 bool software_isr_flag;
906 wait_queue_head_t software_isr_wq;
909 #define LAN743X_MAX_FRAME_SIZE (9 * 1024)
914 u8 fc_request_control;
918 struct lan743x_tx_descriptor;
919 struct lan743x_tx_buffer_info;
921 #define GPIO_QUEUE_STARTED (0)
922 #define GPIO_TX_FUNCTION (1)
923 #define GPIO_TX_COMPLETION (2)
924 #define GPIO_TX_FRAGMENT (3)
926 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
928 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
929 #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1)
932 struct lan743x_adapter *adapter;
938 size_t ring_allocation_size;
939 struct lan743x_tx_descriptor *ring_cpu_ptr;
940 dma_addr_t ring_dma_ptr;
941 /* ring_lock: used to prevent concurrent access to tx ring */
942 spinlock_t ring_lock;
948 struct lan743x_tx_buffer_info *buffer_info;
950 __le32 *head_cpu_ptr;
951 dma_addr_t head_dma_ptr;
955 struct napi_struct napi;
958 struct sk_buff *overflow_skb;
961 void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
962 bool enable_timestamping,
963 bool enable_onestep_sync);
966 struct lan743x_rx_descriptor;
967 struct lan743x_rx_buffer_info;
970 struct lan743x_adapter *adapter;
975 size_t ring_allocation_size;
976 struct lan743x_rx_descriptor *ring_cpu_ptr;
977 dma_addr_t ring_dma_ptr;
979 struct lan743x_rx_buffer_info *buffer_info;
981 __le32 *head_cpu_ptr;
982 dma_addr_t head_dma_ptr;
986 struct napi_struct napi;
990 struct sk_buff *skb_head, *skb_tail;
993 /* SGMII Link Speed Duplex status */
994 enum lan743x_sgmii_lsd {
1008 struct lan743x_adapter {
1009 struct net_device *netdev;
1010 struct mii_bus *mdiobus;
1014 u8 sopass[SOPASS_MAX];
1016 struct pci_dev *pdev;
1017 struct lan743x_csr csr;
1018 struct lan743x_intr intr;
1020 struct lan743x_gpio gpio;
1021 struct lan743x_ptp ptp;
1023 u8 mac_address[ETH_ALEN];
1025 struct lan743x_phy phy;
1026 struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS];
1027 struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS];
1030 /* protect ethernet syslock */
1031 spinlock_t eth_syslock_spinlock;
1032 bool eth_syslock_en;
1033 u32 eth_syslock_acquire_cnt;
1034 struct mutex sgmii_rw_lock;
1035 /* SGMII Link Speed & Duplex status */
1036 enum lan743x_sgmii_lsd sgmii_lsd;
1038 u8 used_tx_channels;
1039 u8 max_vector_count;
1041 #define LAN743X_ADAPTER_FLAG_OTP BIT(0)
1046 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel))
1048 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
1049 #define INTR_FLAG_MSI_ENABLED BIT(8)
1050 #define INTR_FLAG_MSIX_ENABLED BIT(9)
1052 #define MAC_MII_READ 1
1053 #define MAC_MII_WRITE 0
1055 #define PHY_FLAG_OPENED BIT(0)
1056 #define PHY_FLAG_ATTACHED BIT(1)
1058 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1059 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
1061 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
1063 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
1064 #define DMA_DESCRIPTOR_SPACING_16 (16)
1065 #define DMA_DESCRIPTOR_SPACING_32 (32)
1066 #define DMA_DESCRIPTOR_SPACING_64 (64)
1067 #define DMA_DESCRIPTOR_SPACING_128 (128)
1068 #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES)
1070 #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \
1071 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1072 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
1073 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
1074 #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1)
1075 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
1077 /* TX Descriptor bits */
1078 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
1079 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
1080 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
1081 #define TX_DESC_DATA0_FS_ (0x20000000)
1082 #define TX_DESC_DATA0_LS_ (0x10000000)
1083 #define TX_DESC_DATA0_EXT_ (0x08000000)
1084 #define TX_DESC_DATA0_IOC_ (0x04000000)
1085 #define TX_DESC_DATA0_ICE_ (0x00400000)
1086 #define TX_DESC_DATA0_IPE_ (0x00200000)
1087 #define TX_DESC_DATA0_TPE_ (0x00100000)
1088 #define TX_DESC_DATA0_FCS_ (0x00020000)
1089 #define TX_DESC_DATA0_TSE_ (0x00010000)
1090 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
1091 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
1092 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
1093 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
1095 struct lan743x_tx_descriptor {
1100 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1102 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1103 #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1)
1104 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
1105 #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3)
1106 struct lan743x_tx_buffer_info {
1108 struct sk_buff *skb;
1110 unsigned int buffer_length;
1113 #define LAN743X_TX_RING_SIZE (50)
1115 /* OWN bit is set. ie, Descs are owned by RX DMAC */
1116 #define RX_DESC_DATA0_OWN_ (0x00008000)
1117 /* OWN bit is clear. ie, Descs are owned by host */
1118 #define RX_DESC_DATA0_FS_ (0x80000000)
1119 #define RX_DESC_DATA0_LS_ (0x40000000)
1120 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
1121 #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \
1122 (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16)
1123 #define RX_DESC_DATA0_EXT_ (0x00004000)
1124 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
1125 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
1127 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1128 #error NET_IP_ALIGN must be 0 or 2
1131 #define RX_HEAD_PADDING NET_IP_ALIGN
1133 struct lan743x_rx_descriptor {
1138 } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING);
1140 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1141 struct lan743x_rx_buffer_info {
1143 struct sk_buff *skb;
1146 unsigned int buffer_length;
1149 #define LAN743X_RX_RING_SIZE (128)
1151 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0)
1152 #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1)
1154 u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset);
1155 void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data);
1156 int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout);
1157 void lan743x_hs_syslock_release(struct lan743x_adapter *adapter);
1159 #endif /* _LAN743X_H */