1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <linux/log2.h>
26 #include <linux/refcount.h>
27 #include <linux/rhashtable.h>
28 #include <net/switchdev.h>
29 #include <net/pkt_cls.h>
30 #include <net/netevent.h>
31 #include <net/addrconf.h>
32 #include <linux/ptp_classify.h>
42 #include "spectrum_cnt.h"
43 #include "spectrum_dpipe.h"
44 #include "spectrum_acl_flex_actions.h"
45 #include "spectrum_span.h"
46 #include "spectrum_ptp.h"
47 #include "spectrum_trap.h"
49 #define MLXSW_SP_FWREV_MINOR 2010
50 #define MLXSW_SP_FWREV_SUBMINOR 1006
52 #define MLXSW_SP1_FWREV_MAJOR 13
53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
56 .major = MLXSW_SP1_FWREV_MAJOR,
57 .minor = MLXSW_SP_FWREV_MINOR,
58 .subminor = MLXSW_SP_FWREV_SUBMINOR,
59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
62 #define MLXSW_SP1_FW_FILENAME \
63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
64 "." __stringify(MLXSW_SP_FWREV_MINOR) \
65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
67 #define MLXSW_SP2_FWREV_MAJOR 29
69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
70 .major = MLXSW_SP2_FWREV_MAJOR,
71 .minor = MLXSW_SP_FWREV_MINOR,
72 .subminor = MLXSW_SP_FWREV_SUBMINOR,
75 #define MLXSW_SP2_FW_FILENAME \
76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
77 "." __stringify(MLXSW_SP_FWREV_MINOR) \
78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
80 #define MLXSW_SP3_FWREV_MAJOR 30
82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
83 .major = MLXSW_SP3_FWREV_MAJOR,
84 .minor = MLXSW_SP_FWREV_MINOR,
85 .subminor = MLXSW_SP_FWREV_SUBMINOR,
88 #define MLXSW_SP3_FW_FILENAME \
89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
90 "." __stringify(MLXSW_SP_FWREV_MINOR) \
91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \
94 "mellanox/lc_ini_bundle_" \
95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \
96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin"
98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4";
103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
114 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
117 * Packet control type.
118 * 0 - Ethernet control (e.g. EMADs, LACP)
121 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
124 * Packet protocol type. Must be set to 1 (Ethernet).
126 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
128 /* tx_hdr_rx_is_router
129 * Packet is sent from the router. Valid for data packets only.
131 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
134 * Indicates if the 'fid' field is valid and should be used for
135 * forwarding lookup. Valid for data packets only.
137 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
140 * Switch partition ID. Must be set to 0.
142 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
144 /* tx_hdr_control_tclass
145 * Indicates if the packet should use the control TClass and not one
146 * of the data TClasses.
148 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
151 * Egress TClass to be used on the egress device on the egress port.
153 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
156 * Destination local port for unicast packets.
157 * Destination multicast ID for multicast packets.
159 * Control packets are directed to a specific egress port, while data
160 * packets are transmitted through the CPU port (0) into the switch partition,
161 * where forwarding rules are applied.
163 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
166 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
167 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
168 * Valid for data packets only.
170 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
174 * 6 - Control packets
176 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
178 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
179 unsigned int counter_index, u64 *packets,
182 char mgpc_pl[MLXSW_REG_MGPC_LEN];
185 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
186 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
187 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
191 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
193 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
197 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
198 unsigned int counter_index)
200 char mgpc_pl[MLXSW_REG_MGPC_LEN];
202 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
203 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
204 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
207 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
208 unsigned int *p_counter_index)
212 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
216 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
218 goto err_counter_clear;
222 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
227 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
228 unsigned int counter_index)
230 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
234 void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
235 const struct mlxsw_tx_info *tx_info)
237 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
239 memset(txhdr, 0, MLXSW_TXHDR_LEN);
241 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
242 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
243 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
244 mlxsw_tx_hdr_swid_set(txhdr, 0);
245 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
246 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
247 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
251 mlxsw_sp_txhdr_ptp_data_construct(struct mlxsw_core *mlxsw_core,
252 struct mlxsw_sp_port *mlxsw_sp_port,
254 const struct mlxsw_tx_info *tx_info)
260 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
262 goto err_skb_cow_head;
265 if (!MLXSW_CORE_RES_VALID(mlxsw_core, FID)) {
269 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID);
271 txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
272 memset(txhdr, 0, MLXSW_TXHDR_LEN);
274 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
275 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
276 mlxsw_tx_hdr_rx_is_router_set(txhdr, true);
277 mlxsw_tx_hdr_fid_valid_set(txhdr, true);
278 mlxsw_tx_hdr_fid_set(txhdr, max_fid + tx_info->local_port - 1);
279 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_DATA);
284 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
285 dev_kfree_skb_any(skb);
289 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb)
293 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
296 type = ptp_classify_raw(skb);
297 return !!ptp_parse_header(skb, type);
300 static int mlxsw_sp_txhdr_handle(struct mlxsw_core *mlxsw_core,
301 struct mlxsw_sp_port *mlxsw_sp_port,
303 const struct mlxsw_tx_info *tx_info)
305 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
307 /* In Spectrum-2 and Spectrum-3, PTP events that require a time stamp
308 * need special handling and cannot be transmitted as regular control
311 if (unlikely(mlxsw_sp_skb_requires_ts(skb)))
312 return mlxsw_sp->ptp_ops->txhdr_construct(mlxsw_core,
316 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
317 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
318 dev_kfree_skb_any(skb);
322 mlxsw_sp_txhdr_construct(skb, tx_info);
326 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
329 case BR_STATE_FORWARDING:
330 return MLXSW_REG_SPMS_STATE_FORWARDING;
331 case BR_STATE_LEARNING:
332 return MLXSW_REG_SPMS_STATE_LEARNING;
333 case BR_STATE_LISTENING:
334 case BR_STATE_DISABLED:
335 case BR_STATE_BLOCKING:
336 return MLXSW_REG_SPMS_STATE_DISCARDING;
342 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
345 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
346 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
350 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
353 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
354 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
356 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
361 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
363 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
369 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
373 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
377 char paos_pl[MLXSW_REG_PAOS_LEN];
379 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
380 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
381 MLXSW_PORT_ADMIN_STATUS_DOWN);
382 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
385 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
386 const unsigned char *addr)
388 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
389 char ppad_pl[MLXSW_REG_PPAD_LEN];
391 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
392 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
396 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
398 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
400 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac,
401 mlxsw_sp_port->local_port);
402 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port,
403 mlxsw_sp_port->dev->dev_addr);
406 static int mlxsw_sp_port_max_mtu_get(struct mlxsw_sp_port *mlxsw_sp_port, int *p_max_mtu)
408 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
409 char pmtu_pl[MLXSW_REG_PMTU_LEN];
412 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
413 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
417 *p_max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
421 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
423 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
424 char pmtu_pl[MLXSW_REG_PMTU_LEN];
426 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
427 if (mtu > mlxsw_sp_port->max_mtu)
430 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
431 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
434 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp,
435 u16 local_port, u8 swid)
437 char pspa_pl[MLXSW_REG_PSPA_LEN];
439 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
440 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
443 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
446 char svpe_pl[MLXSW_REG_SVPE_LEN];
448 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
449 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
452 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
455 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
459 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
462 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
464 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
469 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type)
485 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port,
488 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
489 char spevet_pl[MLXSW_REG_SPEVET_LEN];
493 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
497 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type);
498 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
501 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
502 u16 vid, u16 ethtype)
504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
505 char spvid_pl[MLXSW_REG_SPVID_LEN];
509 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
513 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid,
516 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
519 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
523 char spaft_pl[MLXSW_REG_SPAFT_LEN];
525 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
526 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
529 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
535 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
539 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype);
542 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
544 goto err_port_allow_untagged_set;
547 mlxsw_sp_port->pvid = vid;
550 err_port_allow_untagged_set:
551 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype);
556 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
559 char sspr_pl[MLXSW_REG_SSPR_LEN];
561 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
566 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp,
567 u16 local_port, char *pmlp_pl,
568 struct mlxsw_sp_port_mapping *port_mapping)
577 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
578 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0);
579 width = mlxsw_reg_pmlp_width_get(pmlp_pl);
580 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
581 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
583 if (width && !is_power_of_2(width)) {
584 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
589 for (i = 0; i < width; i++) {
590 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
591 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
595 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) {
596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n",
601 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
602 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
607 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) {
608 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
614 port_mapping->module = module;
615 port_mapping->slot_index = slot_index;
616 port_mapping->width = width;
617 port_mapping->module_width = width;
618 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
623 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port,
624 struct mlxsw_sp_port_mapping *port_mapping)
626 char pmlp_pl[MLXSW_REG_PMLP_LEN];
629 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
630 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
633 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
634 pmlp_pl, port_mapping);
638 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port,
639 const struct mlxsw_sp_port_mapping *port_mapping)
641 char pmlp_pl[MLXSW_REG_PMLP_LEN];
644 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index,
645 port_mapping->module);
647 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
648 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
649 for (i = 0; i < port_mapping->width; i++) {
650 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i,
651 port_mapping->slot_index);
652 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
653 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
656 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
662 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index,
663 port_mapping->module);
667 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port,
668 u8 slot_index, u8 module)
670 char pmlp_pl[MLXSW_REG_PMLP_LEN];
672 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
673 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
674 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
675 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module);
678 static int mlxsw_sp_port_open(struct net_device *dev)
680 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
681 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
684 err = mlxsw_env_module_port_up(mlxsw_sp->core,
685 mlxsw_sp_port->mapping.slot_index,
686 mlxsw_sp_port->mapping.module);
689 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
691 goto err_port_admin_status_set;
692 netif_start_queue(dev);
695 err_port_admin_status_set:
696 mlxsw_env_module_port_down(mlxsw_sp->core,
697 mlxsw_sp_port->mapping.slot_index,
698 mlxsw_sp_port->mapping.module);
702 static int mlxsw_sp_port_stop(struct net_device *dev)
704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
705 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
707 netif_stop_queue(dev);
708 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
709 mlxsw_env_module_port_down(mlxsw_sp->core,
710 mlxsw_sp_port->mapping.slot_index,
711 mlxsw_sp_port->mapping.module);
715 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
716 struct net_device *dev)
718 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
719 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
720 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
721 const struct mlxsw_tx_info tx_info = {
722 .local_port = mlxsw_sp_port->local_port,
728 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
730 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
731 return NETDEV_TX_BUSY;
733 if (eth_skb_pad(skb)) {
734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
738 err = mlxsw_sp_txhdr_handle(mlxsw_sp->core, mlxsw_sp_port, skb,
743 /* TX header is consumed by HW on the way so we shouldn't count its
744 * bytes as being sent.
746 len = skb->len - MLXSW_TXHDR_LEN;
748 /* Due to a race we might fail here because of a full queue. In that
749 * unlikely case we simply drop the packet.
751 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
754 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
755 u64_stats_update_begin(&pcpu_stats->syncp);
756 pcpu_stats->tx_packets++;
757 pcpu_stats->tx_bytes += len;
758 u64_stats_update_end(&pcpu_stats->syncp);
760 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
761 dev_kfree_skb_any(skb);
766 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
770 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
773 struct sockaddr *addr = p;
776 if (!is_valid_ether_addr(addr->sa_data))
777 return -EADDRNOTAVAIL;
779 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
782 eth_hw_addr_set(dev, addr->sa_data);
786 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
788 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
789 struct mlxsw_sp_hdroom orig_hdroom;
790 struct mlxsw_sp_hdroom hdroom;
793 orig_hdroom = *mlxsw_sp_port->hdroom;
795 hdroom = orig_hdroom;
797 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
799 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
801 netdev_err(dev, "Failed to configure port's headroom\n");
805 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
807 goto err_port_mtu_set;
812 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
817 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
818 struct rtnl_link_stats64 *stats)
820 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
821 struct mlxsw_sp_port_pcpu_stats *p;
822 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
827 for_each_possible_cpu(i) {
828 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
830 start = u64_stats_fetch_begin_irq(&p->syncp);
831 rx_packets = p->rx_packets;
832 rx_bytes = p->rx_bytes;
833 tx_packets = p->tx_packets;
834 tx_bytes = p->tx_bytes;
835 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
837 stats->rx_packets += rx_packets;
838 stats->rx_bytes += rx_bytes;
839 stats->tx_packets += tx_packets;
840 stats->tx_bytes += tx_bytes;
841 /* tx_dropped is u32, updated without syncp protection. */
842 tx_dropped += p->tx_dropped;
844 stats->tx_dropped = tx_dropped;
848 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
851 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
858 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
862 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
863 return mlxsw_sp_port_get_sw_stats64(dev, sp);
869 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
870 int prio, char *ppcnt_pl)
872 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
875 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
876 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
879 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
880 struct rtnl_link_stats64 *stats)
882 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
885 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
891 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
893 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
895 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
897 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
899 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
901 stats->rx_crc_errors =
902 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
903 stats->rx_frame_errors =
904 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
906 stats->rx_length_errors = (
907 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
908 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
909 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
911 stats->rx_errors = (stats->rx_crc_errors +
912 stats->rx_frame_errors + stats->rx_length_errors);
919 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
920 struct mlxsw_sp_port_xstats *xstats)
922 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
925 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
928 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
930 for (i = 0; i < TC_MAX_QUEUE; i++) {
931 err = mlxsw_sp_port_get_stats_raw(dev,
932 MLXSW_REG_PPCNT_TC_CONG_CNT,
937 xstats->wred_drop[i] =
938 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
939 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl);
942 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
948 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
949 xstats->tail_drop[i] =
950 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
953 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
954 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
959 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
960 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
964 static void update_stats_cache(struct work_struct *work)
966 struct mlxsw_sp_port *mlxsw_sp_port =
967 container_of(work, struct mlxsw_sp_port,
968 periodic_hw_stats.update_dw.work);
970 if (!netif_carrier_ok(mlxsw_sp_port->dev))
971 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
972 * necessary when port goes down.
976 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
977 &mlxsw_sp_port->periodic_hw_stats.stats);
978 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
979 &mlxsw_sp_port->periodic_hw_stats.xstats);
982 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
983 MLXSW_HW_STATS_UPDATE_TIME);
986 /* Return the stats from a cache that is updated periodically,
987 * as this function might get called in an atomic context.
990 mlxsw_sp_port_get_stats64(struct net_device *dev,
991 struct rtnl_link_stats64 *stats)
993 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
995 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
998 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
999 u16 vid_begin, u16 vid_end,
1000 bool is_member, bool untagged)
1002 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1006 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1010 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1011 vid_end, is_member, untagged);
1012 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1017 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1018 u16 vid_end, bool is_member, bool untagged)
1023 for (vid = vid_begin; vid <= vid_end;
1024 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1025 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1028 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1029 is_member, untagged);
1037 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1040 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1042 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1043 &mlxsw_sp_port->vlans_list, list) {
1044 if (!flush_default &&
1045 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1047 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1052 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1054 if (mlxsw_sp_port_vlan->bridge_port)
1055 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1056 else if (mlxsw_sp_port_vlan->fid)
1057 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1060 struct mlxsw_sp_port_vlan *
1061 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1063 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1064 bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1067 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1068 if (mlxsw_sp_port_vlan)
1069 return ERR_PTR(-EEXIST);
1071 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1073 return ERR_PTR(err);
1075 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1076 if (!mlxsw_sp_port_vlan) {
1078 goto err_port_vlan_alloc;
1081 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1082 mlxsw_sp_port_vlan->vid = vid;
1083 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1085 return mlxsw_sp_port_vlan;
1087 err_port_vlan_alloc:
1088 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1089 return ERR_PTR(err);
1092 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1094 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1095 u16 vid = mlxsw_sp_port_vlan->vid;
1097 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1098 list_del(&mlxsw_sp_port_vlan->list);
1099 kfree(mlxsw_sp_port_vlan);
1100 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1103 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1104 __be16 __always_unused proto, u16 vid)
1106 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1108 /* VLAN 0 is added to HW filter when device goes up, but it is
1109 * reserved in our case, so simply return.
1114 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1117 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1118 __be16 __always_unused proto, u16 vid)
1120 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1121 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1123 /* VLAN 0 is removed from HW filter when device goes down, but
1124 * it is reserved in our case, so simply return.
1129 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1130 if (!mlxsw_sp_port_vlan)
1132 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1137 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1138 struct flow_block_offload *f)
1140 switch (f->binder_type) {
1141 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
1142 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
1143 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
1144 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
1145 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
1146 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
1147 case FLOW_BLOCK_BINDER_TYPE_RED_MARK:
1148 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f);
1154 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1157 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1160 case TC_SETUP_BLOCK:
1161 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1162 case TC_SETUP_QDISC_RED:
1163 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1164 case TC_SETUP_QDISC_PRIO:
1165 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1166 case TC_SETUP_QDISC_ETS:
1167 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
1168 case TC_SETUP_QDISC_TBF:
1169 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
1170 case TC_SETUP_QDISC_FIFO:
1171 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
1177 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1179 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1182 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
1183 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
1184 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1187 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
1188 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
1190 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
1191 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
1196 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1198 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1199 char pplr_pl[MLXSW_REG_PPLR_LEN];
1202 if (netif_running(dev))
1203 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1205 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1206 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1209 if (netif_running(dev))
1210 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1215 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1217 static int mlxsw_sp_handle_feature(struct net_device *dev,
1218 netdev_features_t wanted_features,
1219 netdev_features_t feature,
1220 mlxsw_sp_feature_handler feature_handler)
1222 netdev_features_t changes = wanted_features ^ dev->features;
1223 bool enable = !!(wanted_features & feature);
1226 if (!(changes & feature))
1229 err = feature_handler(dev, enable);
1231 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1232 enable ? "Enable" : "Disable", &feature, err);
1237 dev->features |= feature;
1239 dev->features &= ~feature;
1243 static int mlxsw_sp_set_features(struct net_device *dev,
1244 netdev_features_t features)
1246 netdev_features_t oper_features = dev->features;
1249 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1250 mlxsw_sp_feature_hw_tc);
1251 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1252 mlxsw_sp_feature_loopback);
1255 dev->features = oper_features;
1262 static struct devlink_port *
1263 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1265 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1266 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1268 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1269 mlxsw_sp_port->local_port);
1272 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1275 struct hwtstamp_config config;
1278 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1281 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1286 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1292 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1295 struct hwtstamp_config config;
1298 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1303 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1309 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1311 struct hwtstamp_config config = {0};
1313 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1317 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1319 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1323 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1325 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1331 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1332 .ndo_open = mlxsw_sp_port_open,
1333 .ndo_stop = mlxsw_sp_port_stop,
1334 .ndo_start_xmit = mlxsw_sp_port_xmit,
1335 .ndo_setup_tc = mlxsw_sp_setup_tc,
1336 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1337 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1338 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1339 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1340 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1341 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1342 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1343 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1344 .ndo_set_features = mlxsw_sp_set_features,
1345 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
1346 .ndo_eth_ioctl = mlxsw_sp_port_ioctl,
1350 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
1352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1353 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
1354 const struct mlxsw_sp_port_type_speed_ops *ops;
1355 char ptys_pl[MLXSW_REG_PTYS_LEN];
1356 u32 eth_proto_cap_masked;
1359 ops = mlxsw_sp->port_type_speed_ops;
1361 /* Set advertised speeds to speeds supported by both the driver
1364 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1366 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1370 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
1371 ð_proto_admin, ð_proto_oper);
1372 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap);
1373 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1374 eth_proto_cap_masked,
1375 mlxsw_sp_port->link.autoneg);
1376 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1379 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
1381 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
1382 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1383 char ptys_pl[MLXSW_REG_PTYS_LEN];
1387 port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
1388 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
1389 mlxsw_sp_port->local_port, 0,
1391 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1394 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
1396 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
1400 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1401 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1402 bool dwrr, u8 dwrr_weight)
1404 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1405 char qeec_pl[MLXSW_REG_QEEC_LEN];
1407 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1409 mlxsw_reg_qeec_de_set(qeec_pl, true);
1410 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1411 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1412 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1415 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1416 enum mlxsw_reg_qeec_hr hr, u8 index,
1417 u8 next_index, u32 maxrate, u8 burst_size)
1419 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1420 char qeec_pl[MLXSW_REG_QEEC_LEN];
1422 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1424 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1425 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1426 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
1427 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1430 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
1431 enum mlxsw_reg_qeec_hr hr, u8 index,
1432 u8 next_index, u32 minrate)
1434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1435 char qeec_pl[MLXSW_REG_QEEC_LEN];
1437 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1439 mlxsw_reg_qeec_mise_set(qeec_pl, true);
1440 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
1442 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1445 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1446 u8 switch_prio, u8 tclass)
1448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1449 char qtct_pl[MLXSW_REG_QTCT_LEN];
1451 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1453 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1456 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1460 /* Setup the elements hierarcy, so that each TC is linked to
1461 * one subgroup, which are all member in the same group.
1463 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1464 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
1467 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1468 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1469 MLXSW_REG_QEEC_HR_SUBGROUP, i,
1474 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1475 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1476 MLXSW_REG_QEEC_HR_TC, i, i,
1481 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1482 MLXSW_REG_QEEC_HR_TC,
1489 /* Make sure the max shaper is disabled in all hierarchies that support
1490 * it. Note that this disables ptps (PTP shaper), but that is intended
1491 * for the initial configuration.
1493 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1494 MLXSW_REG_QEEC_HR_PORT, 0, 0,
1495 MLXSW_REG_QEEC_MAS_DIS, 0);
1498 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1499 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1500 MLXSW_REG_QEEC_HR_SUBGROUP,
1502 MLXSW_REG_QEEC_MAS_DIS, 0);
1506 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1507 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1508 MLXSW_REG_QEEC_HR_TC,
1510 MLXSW_REG_QEEC_MAS_DIS, 0);
1514 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1515 MLXSW_REG_QEEC_HR_TC,
1517 MLXSW_REG_QEEC_MAS_DIS, 0);
1522 /* Configure the min shaper for multicast TCs. */
1523 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1524 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
1525 MLXSW_REG_QEEC_HR_TC,
1527 MLXSW_REG_QEEC_MIS_MIN);
1532 /* Map all priorities to traffic class 0. */
1533 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1534 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1542 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
1545 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1546 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
1548 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
1549 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
1552 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port)
1554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1555 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1556 u8 module = mlxsw_sp_port->mapping.module;
1557 u64 overheat_counter;
1560 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index,
1561 module, &overheat_counter);
1565 mlxsw_sp_port->module_overheat_initial_val = overheat_counter;
1570 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port,
1571 bool is_8021ad_tagged,
1572 bool is_8021q_tagged)
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 char spvc_pl[MLXSW_REG_SPVC_LEN];
1577 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port,
1578 is_8021ad_tagged, is_8021q_tagged);
1579 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
1582 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp,
1583 u16 local_port, u8 *port_number,
1584 u8 *split_port_subnumber,
1587 char pllp_pl[MLXSW_REG_PLLP_LEN];
1590 mlxsw_reg_pllp_pack(pllp_pl, local_port);
1591 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl);
1594 mlxsw_reg_pllp_unpack(pllp_pl, port_number,
1595 split_port_subnumber, slot_index);
1599 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port,
1601 struct mlxsw_sp_port_mapping *port_mapping)
1603 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1604 struct mlxsw_sp_port *mlxsw_sp_port;
1605 u32 lanes = port_mapping->width;
1606 u8 split_port_subnumber;
1607 struct net_device *dev;
1613 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping);
1615 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
1620 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0);
1622 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1624 goto err_port_swid_set;
1627 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number,
1628 &split_port_subnumber, &slot_index);
1630 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n",
1632 goto err_port_label_info_get;
1635 splittable = lanes > 1 && !split;
1636 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index,
1637 port_number, split, split_port_subnumber,
1638 splittable, lanes, mlxsw_sp->base_mac,
1639 sizeof(mlxsw_sp->base_mac));
1641 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1643 goto err_core_port_init;
1646 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1649 goto err_alloc_etherdev;
1651 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
1652 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
1653 mlxsw_sp_port = netdev_priv(dev);
1654 mlxsw_sp_port->dev = dev;
1655 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1656 mlxsw_sp_port->local_port = local_port;
1657 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
1658 mlxsw_sp_port->split = split;
1659 mlxsw_sp_port->mapping = *port_mapping;
1660 mlxsw_sp_port->link.autoneg = 1;
1661 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
1663 mlxsw_sp_port->pcpu_stats =
1664 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1665 if (!mlxsw_sp_port->pcpu_stats) {
1667 goto err_alloc_stats;
1670 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1671 &update_stats_cache);
1673 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1674 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1676 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1678 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1679 mlxsw_sp_port->local_port);
1680 goto err_dev_addr_init;
1683 netif_carrier_off(dev);
1685 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1686 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
1687 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
1690 dev->max_mtu = ETH_MAX_MTU;
1692 /* Each packet needs to have a Tx header (metadata) on top all other
1695 dev->needed_headroom = MLXSW_TXHDR_LEN;
1697 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1699 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1700 mlxsw_sp_port->local_port);
1701 goto err_port_system_port_mapping_set;
1704 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
1706 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1707 mlxsw_sp_port->local_port);
1708 goto err_port_speed_by_width_set;
1711 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
1712 &mlxsw_sp_port->max_speed);
1714 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
1715 mlxsw_sp_port->local_port);
1716 goto err_max_speed_get;
1719 err = mlxsw_sp_port_max_mtu_get(mlxsw_sp_port, &mlxsw_sp_port->max_mtu);
1721 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum MTU\n",
1722 mlxsw_sp_port->local_port);
1723 goto err_port_max_mtu_get;
1726 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1728 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1729 mlxsw_sp_port->local_port);
1730 goto err_port_mtu_set;
1733 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1735 goto err_port_admin_status_set;
1737 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1739 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1740 mlxsw_sp_port->local_port);
1741 goto err_port_buffers_init;
1744 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1746 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1747 mlxsw_sp_port->local_port);
1748 goto err_port_ets_init;
1751 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
1753 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
1754 mlxsw_sp_port->local_port);
1755 goto err_port_tc_mc_mode;
1758 /* ETS and buffers must be initialized before DCB. */
1759 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1762 mlxsw_sp_port->local_port);
1763 goto err_port_dcb_init;
1766 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
1768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
1769 mlxsw_sp_port->local_port);
1770 goto err_port_fids_init;
1773 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
1775 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
1776 mlxsw_sp_port->local_port);
1777 goto err_port_qdiscs_init;
1780 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
1783 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
1784 mlxsw_sp_port->local_port);
1785 goto err_port_vlan_clear;
1788 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
1790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
1791 mlxsw_sp_port->local_port);
1792 goto err_port_nve_init;
1795 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
1798 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
1799 mlxsw_sp_port->local_port);
1800 goto err_port_pvid_set;
1803 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
1804 MLXSW_SP_DEFAULT_VID);
1805 if (IS_ERR(mlxsw_sp_port_vlan)) {
1806 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
1807 mlxsw_sp_port->local_port);
1808 err = PTR_ERR(mlxsw_sp_port_vlan);
1809 goto err_port_vlan_create;
1811 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
1813 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat
1814 * only packets with 802.1q header as tagged packets.
1816 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true);
1818 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
1820 goto err_port_vlan_classification_set;
1823 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
1824 mlxsw_sp->ptp_ops->shaper_work);
1826 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1828 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port);
1830 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
1831 mlxsw_sp_port->local_port);
1832 goto err_port_overheat_init_val_set;
1835 err = register_netdev(dev);
1837 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1838 mlxsw_sp_port->local_port);
1839 goto err_register_netdev;
1842 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
1843 mlxsw_sp_port, dev);
1844 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
1847 err_register_netdev:
1848 err_port_overheat_init_val_set:
1849 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1850 err_port_vlan_classification_set:
1851 mlxsw_sp->ports[local_port] = NULL;
1852 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1853 err_port_vlan_create:
1855 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1857 err_port_vlan_clear:
1858 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1859 err_port_qdiscs_init:
1860 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1862 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1864 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1865 err_port_tc_mc_mode:
1867 mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1868 err_port_buffers_init:
1869 err_port_admin_status_set:
1871 err_port_max_mtu_get:
1873 err_port_speed_by_width_set:
1874 err_port_system_port_mapping_set:
1876 free_percpu(mlxsw_sp_port->pcpu_stats);
1880 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1882 err_port_label_info_get:
1883 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1884 MLXSW_PORT_SWID_DISABLED_PORT);
1886 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port,
1887 port_mapping->slot_index,
1888 port_mapping->module);
1892 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1894 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1895 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1896 u8 module = mlxsw_sp_port->mapping.module;
1898 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
1899 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
1900 mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
1901 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
1902 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1903 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1904 mlxsw_sp->ports[local_port] = NULL;
1905 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
1906 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1907 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1908 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1909 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1910 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1911 mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1912 free_percpu(mlxsw_sp_port->pcpu_stats);
1913 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
1914 free_netdev(mlxsw_sp_port->dev);
1915 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1916 mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1917 MLXSW_PORT_SWID_DISABLED_PORT);
1918 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module);
1921 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
1923 struct mlxsw_sp_port *mlxsw_sp_port;
1926 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
1930 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1931 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
1933 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
1936 sizeof(mlxsw_sp->base_mac));
1938 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
1939 goto err_core_cpu_port_init;
1942 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
1945 err_core_cpu_port_init:
1946 kfree(mlxsw_sp_port);
1950 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
1952 struct mlxsw_sp_port *mlxsw_sp_port =
1953 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
1955 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
1956 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
1957 kfree(mlxsw_sp_port);
1960 static bool mlxsw_sp_local_port_valid(u16 local_port)
1962 return local_port != MLXSW_PORT_CPU_PORT;
1965 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1967 if (!mlxsw_sp_local_port_valid(local_port))
1969 return mlxsw_sp->ports[local_port] != NULL;
1972 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp,
1973 u16 local_port, bool enable)
1975 char pmecr_pl[MLXSW_REG_PMECR_LEN];
1977 mlxsw_reg_pmecr_pack(pmecr_pl, local_port,
1978 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT :
1979 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT);
1980 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl);
1983 struct mlxsw_sp_port_mapping_event {
1984 struct list_head list;
1985 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1988 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work)
1990 struct mlxsw_sp_port_mapping_event *event, *next_event;
1991 struct mlxsw_sp_port_mapping_events *events;
1992 struct mlxsw_sp_port_mapping port_mapping;
1993 struct mlxsw_sp *mlxsw_sp;
1994 struct devlink *devlink;
1995 LIST_HEAD(event_queue);
1999 events = container_of(work, struct mlxsw_sp_port_mapping_events, work);
2000 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events);
2001 devlink = priv_to_devlink(mlxsw_sp->core);
2003 spin_lock_bh(&events->queue_lock);
2004 list_splice_init(&events->queue, &event_queue);
2005 spin_unlock_bh(&events->queue_lock);
2007 list_for_each_entry_safe(event, next_event, &event_queue, list) {
2008 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl);
2009 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
2010 event->pmlp_pl, &port_mapping);
2014 if (WARN_ON_ONCE(!port_mapping.width))
2019 if (!mlxsw_sp_port_created(mlxsw_sp, local_port))
2020 mlxsw_sp_port_create(mlxsw_sp, local_port,
2021 false, &port_mapping);
2025 devl_unlock(devlink);
2027 mlxsw_sp->port_mapping[local_port] = port_mapping;
2035 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg,
2036 char *pmlp_pl, void *priv)
2038 struct mlxsw_sp_port_mapping_events *events;
2039 struct mlxsw_sp_port_mapping_event *event;
2040 struct mlxsw_sp *mlxsw_sp = priv;
2043 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl);
2044 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2047 events = &mlxsw_sp->port_mapping_events;
2048 event = kmalloc(sizeof(*event), GFP_ATOMIC);
2051 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl));
2052 spin_lock(&events->queue_lock);
2053 list_add_tail(&event->list, &events->queue);
2054 spin_unlock(&events->queue_lock);
2055 mlxsw_core_schedule_work(&events->work);
2059 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp)
2061 struct mlxsw_sp_port_mapping_event *event, *next_event;
2062 struct mlxsw_sp_port_mapping_events *events;
2064 events = &mlxsw_sp->port_mapping_events;
2066 /* Caller needs to make sure that no new event is going to appear. */
2067 cancel_work_sync(&events->work);
2068 list_for_each_entry_safe(event, next_event, &events->queue, list) {
2069 list_del(&event->list);
2074 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2076 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2079 for (i = 1; i < max_ports; i++)
2080 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2081 /* Make sure all scheduled events are processed */
2082 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2084 for (i = 1; i < max_ports; i++)
2085 if (mlxsw_sp_port_created(mlxsw_sp, i))
2086 mlxsw_sp_port_remove(mlxsw_sp, i);
2087 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2088 kfree(mlxsw_sp->ports);
2089 mlxsw_sp->ports = NULL;
2093 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core,
2094 bool (*selector)(void *priv, u16 local_port),
2097 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2098 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core);
2101 for (i = 1; i < max_ports; i++)
2102 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i))
2103 mlxsw_sp_port_remove(mlxsw_sp, i);
2106 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2108 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2109 struct mlxsw_sp_port_mapping_events *events;
2110 struct mlxsw_sp_port_mapping *port_mapping;
2115 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
2116 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2117 if (!mlxsw_sp->ports)
2120 events = &mlxsw_sp->port_mapping_events;
2121 INIT_LIST_HEAD(&events->queue);
2122 spin_lock_init(&events->queue_lock);
2123 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work);
2125 for (i = 1; i < max_ports; i++) {
2126 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true);
2128 goto err_event_enable;
2131 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
2133 goto err_cpu_port_create;
2135 for (i = 1; i < max_ports; i++) {
2136 port_mapping = &mlxsw_sp->port_mapping[i];
2137 if (!port_mapping->width)
2139 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping);
2141 goto err_port_create;
2146 for (i--; i >= 1; i--)
2147 if (mlxsw_sp_port_created(mlxsw_sp, i))
2148 mlxsw_sp_port_remove(mlxsw_sp, i);
2150 mlxsw_sp_cpu_port_remove(mlxsw_sp);
2151 err_cpu_port_create:
2153 for (i--; i >= 1; i--)
2154 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2155 /* Make sure all scheduled events are processed */
2156 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2157 kfree(mlxsw_sp->ports);
2158 mlxsw_sp->ports = NULL;
2162 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
2164 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2165 struct mlxsw_sp_port_mapping *port_mapping;
2169 mlxsw_sp->port_mapping = kcalloc(max_ports,
2170 sizeof(struct mlxsw_sp_port_mapping),
2172 if (!mlxsw_sp->port_mapping)
2175 for (i = 1; i < max_ports; i++) {
2176 port_mapping = &mlxsw_sp->port_mapping[i];
2177 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping);
2179 goto err_port_module_info_get;
2183 err_port_module_info_get:
2184 kfree(mlxsw_sp->port_mapping);
2188 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
2190 kfree(mlxsw_sp->port_mapping);
2194 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp,
2195 struct mlxsw_sp_port_mapping *port_mapping,
2196 unsigned int count, const char *pmtdb_pl)
2198 struct mlxsw_sp_port_mapping split_port_mapping;
2201 split_port_mapping = *port_mapping;
2202 split_port_mapping.width /= count;
2203 for (i = 0; i < count; i++) {
2204 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2206 if (!mlxsw_sp_local_port_valid(s_local_port))
2209 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port,
2210 true, &split_port_mapping);
2212 goto err_port_create;
2213 split_port_mapping.lane += split_port_mapping.width;
2219 for (i--; i >= 0; i--) {
2220 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2222 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2223 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2228 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2230 const char *pmtdb_pl)
2232 struct mlxsw_sp_port_mapping *port_mapping;
2235 /* Go over original unsplit ports in the gap and recreate them. */
2236 for (i = 0; i < count; i++) {
2237 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2239 port_mapping = &mlxsw_sp->port_mapping[local_port];
2240 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port))
2242 mlxsw_sp_port_create(mlxsw_sp, local_port,
2243 false, port_mapping);
2247 static struct mlxsw_sp_port *
2248 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port)
2250 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
2251 return mlxsw_sp->ports[local_port];
2255 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port,
2257 struct netlink_ext_ack *extack)
2259 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2260 struct mlxsw_sp_port_mapping port_mapping;
2261 struct mlxsw_sp_port *mlxsw_sp_port;
2262 enum mlxsw_reg_pmtdb_status status;
2263 char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2267 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2268 if (!mlxsw_sp_port) {
2269 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2271 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2275 if (mlxsw_sp_port->split) {
2276 NL_SET_ERR_MSG_MOD(extack, "Port is already split");
2280 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2281 mlxsw_sp_port->mapping.module,
2282 mlxsw_sp_port->mapping.module_width / count,
2284 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2286 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2290 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl);
2291 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) {
2292 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration");
2296 port_mapping = mlxsw_sp_port->mapping;
2298 for (i = 0; i < count; i++) {
2299 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2301 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2302 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2305 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping,
2308 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2309 goto err_port_split_create;
2314 err_port_split_create:
2315 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2320 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port,
2321 struct netlink_ext_ack *extack)
2323 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2324 struct mlxsw_sp_port *mlxsw_sp_port;
2325 char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2330 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2331 if (!mlxsw_sp_port) {
2332 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2334 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2338 if (!mlxsw_sp_port->split) {
2339 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
2343 count = mlxsw_sp_port->mapping.module_width /
2344 mlxsw_sp_port->mapping.width;
2346 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2347 mlxsw_sp_port->mapping.module,
2348 mlxsw_sp_port->mapping.module_width / count,
2350 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2352 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2356 for (i = 0; i < count; i++) {
2357 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2359 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2360 mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2363 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2369 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
2373 for (i = 0; i < TC_MAX_QUEUE; i++)
2374 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
2377 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2378 char *pude_pl, void *priv)
2380 struct mlxsw_sp *mlxsw_sp = priv;
2381 struct mlxsw_sp_port *mlxsw_sp_port;
2382 enum mlxsw_reg_pude_oper_status status;
2385 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2387 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2389 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2393 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2394 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2395 netdev_info(mlxsw_sp_port->dev, "link up\n");
2396 netif_carrier_on(mlxsw_sp_port->dev);
2397 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
2399 netdev_info(mlxsw_sp_port->dev, "link down\n");
2400 netif_carrier_off(mlxsw_sp_port->dev);
2401 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
2405 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
2406 char *mtpptr_pl, bool ingress)
2412 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
2413 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
2414 for (i = 0; i < num_rec; i++) {
2420 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
2421 &domain_number, &sequence_id,
2423 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
2424 message_type, domain_number,
2425 sequence_id, timestamp);
2429 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
2430 char *mtpptr_pl, void *priv)
2432 struct mlxsw_sp *mlxsw_sp = priv;
2434 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
2437 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
2438 char *mtpptr_pl, void *priv)
2440 struct mlxsw_sp *mlxsw_sp = priv;
2442 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
2445 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2446 u16 local_port, void *priv)
2448 struct mlxsw_sp *mlxsw_sp = priv;
2449 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2450 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2452 if (unlikely(!mlxsw_sp_port)) {
2453 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2458 skb->dev = mlxsw_sp_port->dev;
2460 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2461 u64_stats_update_begin(&pcpu_stats->syncp);
2462 pcpu_stats->rx_packets++;
2463 pcpu_stats->rx_bytes += skb->len;
2464 u64_stats_update_end(&pcpu_stats->syncp);
2466 skb->protocol = eth_type_trans(skb, skb->dev);
2467 netif_receive_skb(skb);
2470 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port,
2473 skb->offload_fwd_mark = 1;
2474 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2477 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
2478 u16 local_port, void *priv)
2480 skb->offload_l3_fwd_mark = 1;
2481 skb->offload_fwd_mark = 1;
2482 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2485 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2488 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
2491 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2492 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2493 _is_ctrl, SP_##_trap_group, DISCARD)
2495 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2496 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
2497 _is_ctrl, SP_##_trap_group, DISCARD)
2499 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2500 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
2501 _is_ctrl, SP_##_trap_group, DISCARD)
2503 #define MLXSW_SP_EVENTL(_func, _trap_id) \
2504 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2506 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2508 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2510 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
2512 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
2514 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
2515 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
2517 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
2519 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
2521 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
2523 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
2525 /* Multicast Router Traps */
2526 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
2527 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
2529 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false),
2532 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
2534 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
2535 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
2538 static const struct mlxsw_listener mlxsw_sp2_listener[] = {
2540 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE),
2543 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2545 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2546 char qpcr_pl[MLXSW_REG_QPCR_LEN];
2547 enum mlxsw_reg_qpcr_ir_units ir_units;
2548 int max_cpu_policers;
2554 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2557 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2559 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2560 for (i = 0; i < max_cpu_policers; i++) {
2563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2565 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2573 __set_bit(i, mlxsw_sp->trap->policers_usage);
2574 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2576 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2584 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2586 char htgt_pl[MLXSW_REG_HTGT_LEN];
2587 enum mlxsw_reg_htgt_trap_group i;
2588 int max_cpu_policers;
2589 int max_trap_groups;
2594 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2597 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2598 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2600 for (i = 0; i < max_trap_groups; i++) {
2603 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2605 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2610 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2611 tc = MLXSW_REG_HTGT_DEFAULT_TC;
2612 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2618 if (max_cpu_policers <= policer_id &&
2619 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2622 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2623 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2631 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2633 struct mlxsw_sp_trap *trap;
2637 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
2639 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
2640 trap = kzalloc(struct_size(trap, policers_usage,
2641 BITS_TO_LONGS(max_policers)), GFP_KERNEL);
2644 trap->max_policers = max_policers;
2645 mlxsw_sp->trap = trap;
2647 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2649 goto err_cpu_policers_set;
2651 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2653 goto err_trap_groups_set;
2655 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener,
2656 ARRAY_SIZE(mlxsw_sp_listener),
2659 goto err_traps_register;
2661 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners,
2662 mlxsw_sp->listeners_count, mlxsw_sp);
2664 goto err_extra_traps_init;
2668 err_extra_traps_init:
2669 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2670 ARRAY_SIZE(mlxsw_sp_listener),
2673 err_trap_groups_set:
2674 err_cpu_policers_set:
2679 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2681 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners,
2682 mlxsw_sp->listeners_count,
2684 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2685 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp);
2686 kfree(mlxsw_sp->trap);
2689 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
2691 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2693 char slcr_pl[MLXSW_REG_SLCR_LEN];
2697 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
2698 MLXSW_SP_LAG_SEED_INIT);
2699 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2700 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2701 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2702 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2703 MLXSW_REG_SLCR_LAG_HASH_SIP |
2704 MLXSW_REG_SLCR_LAG_HASH_DIP |
2705 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2706 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2707 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
2708 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2712 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
2713 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
2716 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
2717 sizeof(struct mlxsw_sp_upper),
2719 if (!mlxsw_sp->lags)
2725 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2727 kfree(mlxsw_sp->lags);
2730 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
2731 .clock_init = mlxsw_sp1_ptp_clock_init,
2732 .clock_fini = mlxsw_sp1_ptp_clock_fini,
2733 .init = mlxsw_sp1_ptp_init,
2734 .fini = mlxsw_sp1_ptp_fini,
2735 .receive = mlxsw_sp1_ptp_receive,
2736 .transmitted = mlxsw_sp1_ptp_transmitted,
2737 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
2738 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
2739 .shaper_work = mlxsw_sp1_ptp_shaper_work,
2740 .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
2741 .get_stats_count = mlxsw_sp1_get_stats_count,
2742 .get_stats_strings = mlxsw_sp1_get_stats_strings,
2743 .get_stats = mlxsw_sp1_get_stats,
2744 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
2747 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
2748 .clock_init = mlxsw_sp2_ptp_clock_init,
2749 .clock_fini = mlxsw_sp2_ptp_clock_fini,
2750 .init = mlxsw_sp2_ptp_init,
2751 .fini = mlxsw_sp2_ptp_fini,
2752 .receive = mlxsw_sp2_ptp_receive,
2753 .transmitted = mlxsw_sp2_ptp_transmitted,
2754 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
2755 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
2756 .shaper_work = mlxsw_sp2_ptp_shaper_work,
2757 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
2758 .get_stats_count = mlxsw_sp2_get_stats_count,
2759 .get_stats_strings = mlxsw_sp2_get_stats_strings,
2760 .get_stats = mlxsw_sp2_get_stats,
2761 .txhdr_construct = mlxsw_sp2_ptp_txhdr_construct,
2764 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = {
2765 .clock_init = mlxsw_sp2_ptp_clock_init,
2766 .clock_fini = mlxsw_sp2_ptp_clock_fini,
2767 .init = mlxsw_sp2_ptp_init,
2768 .fini = mlxsw_sp2_ptp_fini,
2769 .receive = mlxsw_sp2_ptp_receive,
2770 .transmitted = mlxsw_sp2_ptp_transmitted,
2771 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
2772 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
2773 .shaper_work = mlxsw_sp2_ptp_shaper_work,
2774 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
2775 .get_stats_count = mlxsw_sp2_get_stats_count,
2776 .get_stats_strings = mlxsw_sp2_get_stats_strings,
2777 .get_stats = mlxsw_sp2_get_stats,
2778 .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
2781 struct mlxsw_sp_sample_trigger_node {
2782 struct mlxsw_sp_sample_trigger trigger;
2783 struct mlxsw_sp_sample_params params;
2784 struct rhash_head ht_node;
2785 struct rcu_head rcu;
2786 refcount_t refcount;
2789 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = {
2790 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger),
2791 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node),
2792 .key_len = sizeof(struct mlxsw_sp_sample_trigger),
2793 .automatic_shrinking = true,
2797 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key,
2798 const struct mlxsw_sp_sample_trigger *trigger)
2800 memset(key, 0, sizeof(*key));
2801 key->type = trigger->type;
2802 key->local_port = trigger->local_port;
2805 /* RCU read lock must be held */
2806 struct mlxsw_sp_sample_params *
2807 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
2808 const struct mlxsw_sp_sample_trigger *trigger)
2810 struct mlxsw_sp_sample_trigger_node *trigger_node;
2811 struct mlxsw_sp_sample_trigger key;
2813 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2814 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
2815 mlxsw_sp_sample_trigger_ht_params);
2819 return &trigger_node->params;
2823 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
2824 const struct mlxsw_sp_sample_trigger *trigger,
2825 const struct mlxsw_sp_sample_params *params)
2827 struct mlxsw_sp_sample_trigger_node *trigger_node;
2830 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL);
2834 trigger_node->trigger = *trigger;
2835 trigger_node->params = *params;
2836 refcount_set(&trigger_node->refcount, 1);
2838 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
2839 &trigger_node->ht_node,
2840 mlxsw_sp_sample_trigger_ht_params);
2842 goto err_rhashtable_insert;
2846 err_rhashtable_insert:
2847 kfree(trigger_node);
2852 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
2853 struct mlxsw_sp_sample_trigger_node *trigger_node)
2855 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
2856 &trigger_node->ht_node,
2857 mlxsw_sp_sample_trigger_ht_params);
2858 kfree_rcu(trigger_node, rcu);
2862 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
2863 const struct mlxsw_sp_sample_trigger *trigger,
2864 const struct mlxsw_sp_sample_params *params,
2865 struct netlink_ext_ack *extack)
2867 struct mlxsw_sp_sample_trigger_node *trigger_node;
2868 struct mlxsw_sp_sample_trigger key;
2872 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2874 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2876 mlxsw_sp_sample_trigger_ht_params);
2878 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
2881 if (trigger_node->trigger.local_port) {
2882 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port");
2886 if (trigger_node->params.psample_group != params->psample_group ||
2887 trigger_node->params.truncate != params->truncate ||
2888 trigger_node->params.rate != params->rate ||
2889 trigger_node->params.trunc_size != params->trunc_size) {
2890 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger");
2894 refcount_inc(&trigger_node->refcount);
2900 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
2901 const struct mlxsw_sp_sample_trigger *trigger)
2903 struct mlxsw_sp_sample_trigger_node *trigger_node;
2904 struct mlxsw_sp_sample_trigger key;
2908 mlxsw_sp_sample_trigger_key_init(&key, trigger);
2910 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2912 mlxsw_sp_sample_trigger_ht_params);
2916 if (!refcount_dec_and_test(&trigger_node->refcount))
2919 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
2922 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
2923 unsigned long event, void *ptr);
2925 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96
2926 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128
2927 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789
2929 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp)
2931 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
2932 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT;
2933 mutex_init(&mlxsw_sp->parsing.lock);
2936 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp)
2938 mutex_destroy(&mlxsw_sp->parsing.lock);
2941 struct mlxsw_sp_ipv6_addr_node {
2942 struct in6_addr key;
2943 struct rhash_head ht_node;
2945 refcount_t refcount;
2948 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = {
2949 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key),
2950 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node),
2951 .key_len = sizeof(struct in6_addr),
2952 .automatic_shrinking = true,
2956 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6,
2959 struct mlxsw_sp_ipv6_addr_node *node;
2960 char rips_pl[MLXSW_REG_RIPS_LEN];
2963 err = mlxsw_sp_kvdl_alloc(mlxsw_sp,
2964 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
2969 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6);
2970 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl);
2972 goto err_rips_write;
2974 node = kzalloc(sizeof(*node), GFP_KERNEL);
2977 goto err_node_alloc;
2981 node->kvdl_index = *p_kvdl_index;
2982 refcount_set(&node->refcount, 1);
2984 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht,
2986 mlxsw_sp_ipv6_addr_ht_params);
2988 goto err_rhashtable_insert;
2992 err_rhashtable_insert:
2996 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3001 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp,
3002 struct mlxsw_sp_ipv6_addr_node *node)
3004 u32 kvdl_index = node->kvdl_index;
3006 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node,
3007 mlxsw_sp_ipv6_addr_ht_params);
3009 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
3013 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp,
3014 const struct in6_addr *addr6,
3017 struct mlxsw_sp_ipv6_addr_node *node;
3020 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3021 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3022 mlxsw_sp_ipv6_addr_ht_params);
3024 refcount_inc(&node->refcount);
3025 *p_kvdl_index = node->kvdl_index;
3029 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index);
3032 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3037 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6)
3039 struct mlxsw_sp_ipv6_addr_node *node;
3041 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
3042 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
3043 mlxsw_sp_ipv6_addr_ht_params);
3047 if (!refcount_dec_and_test(&node->refcount))
3050 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node);
3053 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
3056 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp)
3060 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht,
3061 &mlxsw_sp_ipv6_addr_ht_params);
3065 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock);
3069 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp)
3071 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock);
3072 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht);
3075 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3076 const struct mlxsw_bus_info *mlxsw_bus_info,
3077 struct netlink_ext_ack *extack)
3079 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3082 mlxsw_sp->core = mlxsw_core;
3083 mlxsw_sp->bus_info = mlxsw_bus_info;
3085 mlxsw_sp_parsing_init(mlxsw_sp);
3086 mlxsw_core_emad_string_tlv_enable(mlxsw_core);
3088 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3090 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3094 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3096 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3100 err = mlxsw_sp_pgt_init(mlxsw_sp);
3102 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n");
3106 err = mlxsw_sp_fids_init(mlxsw_sp);
3108 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3112 err = mlxsw_sp_policers_init(mlxsw_sp);
3114 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
3115 goto err_policers_init;
3118 err = mlxsw_sp_traps_init(mlxsw_sp);
3120 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3121 goto err_traps_init;
3124 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
3126 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
3127 goto err_devlink_traps_init;
3130 err = mlxsw_sp_buffers_init(mlxsw_sp);
3132 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3133 goto err_buffers_init;
3136 err = mlxsw_sp_lag_init(mlxsw_sp);
3138 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3142 /* Initialize SPAN before router and switchdev, so that those components
3143 * can call mlxsw_sp_span_respin().
3145 err = mlxsw_sp_span_init(mlxsw_sp);
3147 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3151 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3153 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3154 goto err_switchdev_init;
3157 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3159 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3160 goto err_counter_pool_init;
3163 err = mlxsw_sp_afa_init(mlxsw_sp);
3165 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3169 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp);
3171 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n");
3172 goto err_ipv6_addr_ht_init;
3175 err = mlxsw_sp_nve_init(mlxsw_sp);
3177 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3181 err = mlxsw_sp_acl_init(mlxsw_sp);
3183 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3187 err = mlxsw_sp_router_init(mlxsw_sp, extack);
3189 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3190 goto err_router_init;
3193 if (mlxsw_sp->bus_info->read_clock_capable) {
3194 /* NULL is a valid return value from clock_init */
3196 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
3197 mlxsw_sp->bus_info->dev);
3198 if (IS_ERR(mlxsw_sp->clock)) {
3199 err = PTR_ERR(mlxsw_sp->clock);
3200 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
3201 goto err_ptp_clock_init;
3205 if (mlxsw_sp->clock) {
3206 /* NULL is a valid return value from ptp_ops->init */
3207 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
3208 if (IS_ERR(mlxsw_sp->ptp_state)) {
3209 err = PTR_ERR(mlxsw_sp->ptp_state);
3210 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
3215 /* Initialize netdevice notifier after SPAN is initialized, so that the
3216 * event handler can call SPAN respin.
3218 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3219 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3220 &mlxsw_sp->netdevice_nb);
3222 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3223 goto err_netdev_notifier;
3226 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3228 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3229 goto err_dpipe_init;
3232 err = mlxsw_sp_port_module_info_init(mlxsw_sp);
3234 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
3235 goto err_port_module_info_init;
3238 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
3239 &mlxsw_sp_sample_trigger_ht_params);
3241 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
3242 goto err_sample_trigger_init;
3245 err = mlxsw_sp_ports_create(mlxsw_sp);
3247 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3248 goto err_ports_create;
3254 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3255 err_sample_trigger_init:
3256 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3257 err_port_module_info_init:
3258 mlxsw_sp_dpipe_fini(mlxsw_sp);
3260 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3261 &mlxsw_sp->netdevice_nb);
3262 err_netdev_notifier:
3263 if (mlxsw_sp->clock)
3264 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3266 if (mlxsw_sp->clock)
3267 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3269 mlxsw_sp_router_fini(mlxsw_sp);
3271 mlxsw_sp_acl_fini(mlxsw_sp);
3273 mlxsw_sp_nve_fini(mlxsw_sp);
3275 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3276 err_ipv6_addr_ht_init:
3277 mlxsw_sp_afa_fini(mlxsw_sp);
3279 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3280 err_counter_pool_init:
3281 mlxsw_sp_switchdev_fini(mlxsw_sp);
3283 mlxsw_sp_span_fini(mlxsw_sp);
3285 mlxsw_sp_lag_fini(mlxsw_sp);
3287 mlxsw_sp_buffers_fini(mlxsw_sp);
3289 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3290 err_devlink_traps_init:
3291 mlxsw_sp_traps_fini(mlxsw_sp);
3293 mlxsw_sp_policers_fini(mlxsw_sp);
3295 mlxsw_sp_fids_fini(mlxsw_sp);
3297 mlxsw_sp_pgt_fini(mlxsw_sp);
3299 mlxsw_sp_kvdl_fini(mlxsw_sp);
3300 mlxsw_sp_parsing_fini(mlxsw_sp);
3304 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3305 const struct mlxsw_bus_info *mlxsw_bus_info,
3306 struct netlink_ext_ack *extack)
3308 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3310 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
3311 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3312 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3313 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3314 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3315 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
3316 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3317 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3318 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
3319 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
3320 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
3321 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
3322 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
3323 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
3324 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
3325 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
3326 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
3327 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
3328 mlxsw_sp->listeners = mlxsw_sp1_listener;
3329 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
3330 mlxsw_sp->fid_family_arr = mlxsw_sp1_fid_family_arr;
3331 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
3332 mlxsw_sp->pgt_smpe_index_valid = true;
3334 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3337 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3338 const struct mlxsw_bus_info *mlxsw_bus_info,
3339 struct netlink_ext_ack *extack)
3341 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3343 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3344 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3345 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3346 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3347 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3348 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3349 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3350 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3351 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3352 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3353 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3354 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
3355 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3356 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3357 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
3358 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3359 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3360 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3361 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3362 mlxsw_sp->listeners = mlxsw_sp2_listener;
3363 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3364 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3365 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
3366 mlxsw_sp->pgt_smpe_index_valid = false;
3368 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3371 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
3372 const struct mlxsw_bus_info *mlxsw_bus_info,
3373 struct netlink_ext_ack *extack)
3375 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3377 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3378 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3379 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3380 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3381 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3382 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3383 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3384 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3385 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3386 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3387 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3388 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3389 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3390 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3391 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3392 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3393 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3394 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3395 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3396 mlxsw_sp->listeners = mlxsw_sp2_listener;
3397 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3398 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3399 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
3400 mlxsw_sp->pgt_smpe_index_valid = false;
3402 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3405 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core,
3406 const struct mlxsw_bus_info *mlxsw_bus_info,
3407 struct netlink_ext_ack *extack)
3409 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3411 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3412 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3413 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3414 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops;
3415 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3416 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3417 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3418 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops;
3419 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3420 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3421 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3422 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3423 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3424 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops;
3425 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3426 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3427 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3428 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3429 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3430 mlxsw_sp->listeners = mlxsw_sp2_listener;
3431 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3432 mlxsw_sp->fid_family_arr = mlxsw_sp2_fid_family_arr;
3433 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;
3434 mlxsw_sp->pgt_smpe_index_valid = false;
3436 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3439 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3441 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3443 mlxsw_sp_ports_remove(mlxsw_sp);
3444 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3445 mlxsw_sp_port_module_info_fini(mlxsw_sp);
3446 mlxsw_sp_dpipe_fini(mlxsw_sp);
3447 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3448 &mlxsw_sp->netdevice_nb);
3449 if (mlxsw_sp->clock) {
3450 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3451 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3453 mlxsw_sp_router_fini(mlxsw_sp);
3454 mlxsw_sp_acl_fini(mlxsw_sp);
3455 mlxsw_sp_nve_fini(mlxsw_sp);
3456 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3457 mlxsw_sp_afa_fini(mlxsw_sp);
3458 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3459 mlxsw_sp_switchdev_fini(mlxsw_sp);
3460 mlxsw_sp_span_fini(mlxsw_sp);
3461 mlxsw_sp_lag_fini(mlxsw_sp);
3462 mlxsw_sp_buffers_fini(mlxsw_sp);
3463 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3464 mlxsw_sp_traps_fini(mlxsw_sp);
3465 mlxsw_sp_policers_fini(mlxsw_sp);
3466 mlxsw_sp_fids_fini(mlxsw_sp);
3467 mlxsw_sp_pgt_fini(mlxsw_sp);
3468 mlxsw_sp_kvdl_fini(mlxsw_sp);
3469 mlxsw_sp_parsing_fini(mlxsw_sp);
3472 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3473 .used_flood_mode = 1,
3474 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3475 .used_max_ib_mc = 1,
3481 .used_kvd_sizes = 1,
3482 .kvd_hash_single_parts = 59,
3483 .kvd_hash_double_parts = 41,
3484 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3488 .type = MLXSW_PORT_SWID_TYPE_ETH,
3493 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3494 .used_flood_mode = 1,
3495 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3496 .used_max_ib_mc = 1,
3505 .type = MLXSW_PORT_SWID_TYPE_ETH,
3508 .used_cqe_time_stamp_type = 1,
3509 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
3513 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3514 struct devlink_resource_size_params *kvd_size_params,
3515 struct devlink_resource_size_params *linear_size_params,
3516 struct devlink_resource_size_params *hash_double_size_params,
3517 struct devlink_resource_size_params *hash_single_size_params)
3519 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3520 KVD_SINGLE_MIN_SIZE);
3521 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3522 KVD_DOUBLE_MIN_SIZE);
3523 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3524 u32 linear_size_min = 0;
3526 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3527 MLXSW_SP_KVD_GRANULARITY,
3528 DEVLINK_RESOURCE_UNIT_ENTRY);
3529 devlink_resource_size_params_init(linear_size_params, linear_size_min,
3530 kvd_size - single_size_min -
3532 MLXSW_SP_KVD_GRANULARITY,
3533 DEVLINK_RESOURCE_UNIT_ENTRY);
3534 devlink_resource_size_params_init(hash_double_size_params,
3536 kvd_size - single_size_min -
3538 MLXSW_SP_KVD_GRANULARITY,
3539 DEVLINK_RESOURCE_UNIT_ENTRY);
3540 devlink_resource_size_params_init(hash_single_size_params,
3542 kvd_size - double_size_min -
3544 MLXSW_SP_KVD_GRANULARITY,
3545 DEVLINK_RESOURCE_UNIT_ENTRY);
3548 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3550 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3551 struct devlink_resource_size_params hash_single_size_params;
3552 struct devlink_resource_size_params hash_double_size_params;
3553 struct devlink_resource_size_params linear_size_params;
3554 struct devlink_resource_size_params kvd_size_params;
3555 u32 kvd_size, single_size, double_size, linear_size;
3556 const struct mlxsw_config_profile *profile;
3559 profile = &mlxsw_sp1_config_profile;
3560 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3563 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3564 &linear_size_params,
3565 &hash_double_size_params,
3566 &hash_single_size_params);
3568 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3569 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3570 kvd_size, MLXSW_SP_RESOURCE_KVD,
3571 DEVLINK_RESOURCE_ID_PARENT_TOP,
3576 linear_size = profile->kvd_linear_size;
3577 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3579 MLXSW_SP_RESOURCE_KVD_LINEAR,
3580 MLXSW_SP_RESOURCE_KVD,
3581 &linear_size_params);
3585 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
3589 double_size = kvd_size - linear_size;
3590 double_size *= profile->kvd_hash_double_parts;
3591 double_size /= profile->kvd_hash_double_parts +
3592 profile->kvd_hash_single_parts;
3593 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
3594 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3596 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3597 MLXSW_SP_RESOURCE_KVD,
3598 &hash_double_size_params);
3602 single_size = kvd_size - double_size - linear_size;
3603 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3605 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3606 MLXSW_SP_RESOURCE_KVD,
3607 &hash_single_size_params);
3614 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3616 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3617 struct devlink_resource_size_params kvd_size_params;
3620 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3623 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3624 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
3625 MLXSW_SP_KVD_GRANULARITY,
3626 DEVLINK_RESOURCE_UNIT_ENTRY);
3628 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3629 kvd_size, MLXSW_SP_RESOURCE_KVD,
3630 DEVLINK_RESOURCE_ID_PARENT_TOP,
3634 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
3636 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3637 struct devlink_resource_size_params span_size_params;
3640 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
3643 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
3644 devlink_resource_size_params_init(&span_size_params, max_span, max_span,
3645 1, DEVLINK_RESOURCE_UNIT_ENTRY);
3647 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
3648 max_span, MLXSW_SP_RESOURCE_SPAN,
3649 DEVLINK_RESOURCE_ID_PARENT_TOP,
3654 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core)
3656 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3657 struct devlink_resource_size_params size_params;
3658 u8 max_rif_mac_profiles;
3660 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES))
3661 max_rif_mac_profiles = 1;
3663 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core,
3664 MAX_RIF_MAC_PROFILES);
3665 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles,
3666 max_rif_mac_profiles, 1,
3667 DEVLINK_RESOURCE_UNIT_ENTRY);
3669 return devl_resource_register(devlink,
3671 max_rif_mac_profiles,
3672 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES,
3673 DEVLINK_RESOURCE_ID_PARENT_TOP,
3677 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core)
3679 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3680 struct devlink_resource_size_params size_params;
3683 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS))
3686 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS);
3687 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs,
3688 1, DEVLINK_RESOURCE_UNIT_ENTRY);
3690 return devl_resource_register(devlink, "rifs", max_rifs,
3691 MLXSW_SP_RESOURCE_RIFS,
3692 DEVLINK_RESOURCE_ID_PARENT_TOP,
3696 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
3700 err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
3704 err = mlxsw_sp_resources_span_register(mlxsw_core);
3706 goto err_resources_span_register;
3708 err = mlxsw_sp_counter_resources_register(mlxsw_core);
3710 goto err_resources_counter_register;
3712 err = mlxsw_sp_policer_resources_register(mlxsw_core);
3714 goto err_policer_resources_register;
3716 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3718 goto err_resources_rif_mac_profile_register;
3720 err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3722 goto err_resources_rifs_register;
3726 err_resources_rifs_register:
3727 err_resources_rif_mac_profile_register:
3728 err_policer_resources_register:
3729 err_resources_counter_register:
3730 err_resources_span_register:
3731 devl_resources_unregister(priv_to_devlink(mlxsw_core));
3735 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
3739 err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
3743 err = mlxsw_sp_resources_span_register(mlxsw_core);
3745 goto err_resources_span_register;
3747 err = mlxsw_sp_counter_resources_register(mlxsw_core);
3749 goto err_resources_counter_register;
3751 err = mlxsw_sp_policer_resources_register(mlxsw_core);
3753 goto err_policer_resources_register;
3755 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3757 goto err_resources_rif_mac_profile_register;
3759 err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3761 goto err_resources_rifs_register;
3765 err_resources_rifs_register:
3766 err_resources_rif_mac_profile_register:
3767 err_policer_resources_register:
3768 err_resources_counter_register:
3769 err_resources_span_register:
3770 devl_resources_unregister(priv_to_devlink(mlxsw_core));
3774 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3775 const struct mlxsw_config_profile *profile,
3776 u64 *p_single_size, u64 *p_double_size,
3779 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3783 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3784 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
3787 /* The hash part is what left of the kvd without the
3788 * linear part. It is split to the single size and
3789 * double size by the parts ratio from the profile.
3790 * Both sizes must be a multiplications of the
3791 * granularity from the profile. In case the user
3792 * provided the sizes they are obtained via devlink.
3794 err = devl_resource_size_get(devlink,
3795 MLXSW_SP_RESOURCE_KVD_LINEAR,
3798 *p_linear_size = profile->kvd_linear_size;
3800 err = devl_resource_size_get(devlink,
3801 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3804 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3806 double_size *= profile->kvd_hash_double_parts;
3807 double_size /= profile->kvd_hash_double_parts +
3808 profile->kvd_hash_single_parts;
3809 *p_double_size = rounddown(double_size,
3810 MLXSW_SP_KVD_GRANULARITY);
3813 err = devl_resource_size_get(devlink,
3814 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3817 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3818 *p_double_size - *p_linear_size;
3820 /* Check results are legal. */
3821 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3822 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3823 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3830 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
3831 struct devlink_param_gset_ctx *ctx)
3833 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3834 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3836 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
3841 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
3842 struct devlink_param_gset_ctx *ctx)
3844 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
3845 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3847 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
3850 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
3851 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3852 "acl_region_rehash_interval",
3853 DEVLINK_PARAM_TYPE_U32,
3854 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
3855 mlxsw_sp_params_acl_region_rehash_intrvl_get,
3856 mlxsw_sp_params_acl_region_rehash_intrvl_set,
3860 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
3862 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3863 union devlink_param_value value;
3866 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
3867 ARRAY_SIZE(mlxsw_sp2_devlink_params));
3872 devlink_param_driverinit_value_set(devlink,
3873 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
3878 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
3880 devlink_params_unregister(priv_to_devlink(mlxsw_core),
3881 mlxsw_sp2_devlink_params,
3882 ARRAY_SIZE(mlxsw_sp2_devlink_params));
3885 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
3886 struct sk_buff *skb, u16 local_port)
3888 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3890 skb_pull(skb, MLXSW_TXHDR_LEN);
3891 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
3894 static struct mlxsw_driver mlxsw_sp1_driver = {
3895 .kind = mlxsw_sp1_driver_name,
3896 .priv_size = sizeof(struct mlxsw_sp),
3897 .fw_req_rev = &mlxsw_sp1_fw_rev,
3898 .fw_filename = MLXSW_SP1_FW_FILENAME,
3899 .init = mlxsw_sp1_init,
3900 .fini = mlxsw_sp_fini,
3901 .port_split = mlxsw_sp_port_split,
3902 .port_unsplit = mlxsw_sp_port_unsplit,
3903 .sb_pool_get = mlxsw_sp_sb_pool_get,
3904 .sb_pool_set = mlxsw_sp_sb_pool_set,
3905 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3906 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3907 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3908 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3909 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3910 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3911 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3912 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3913 .trap_init = mlxsw_sp_trap_init,
3914 .trap_fini = mlxsw_sp_trap_fini,
3915 .trap_action_set = mlxsw_sp_trap_action_set,
3916 .trap_group_init = mlxsw_sp_trap_group_init,
3917 .trap_group_set = mlxsw_sp_trap_group_set,
3918 .trap_policer_init = mlxsw_sp_trap_policer_init,
3919 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
3920 .trap_policer_set = mlxsw_sp_trap_policer_set,
3921 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
3922 .txhdr_construct = mlxsw_sp_txhdr_construct,
3923 .resources_register = mlxsw_sp1_resources_register,
3924 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
3925 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
3926 .txhdr_len = MLXSW_TXHDR_LEN,
3927 .profile = &mlxsw_sp1_config_profile,
3928 .sdq_supports_cqe_v2 = false,
3931 static struct mlxsw_driver mlxsw_sp2_driver = {
3932 .kind = mlxsw_sp2_driver_name,
3933 .priv_size = sizeof(struct mlxsw_sp),
3934 .fw_req_rev = &mlxsw_sp2_fw_rev,
3935 .fw_filename = MLXSW_SP2_FW_FILENAME,
3936 .init = mlxsw_sp2_init,
3937 .fini = mlxsw_sp_fini,
3938 .port_split = mlxsw_sp_port_split,
3939 .port_unsplit = mlxsw_sp_port_unsplit,
3940 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
3941 .sb_pool_get = mlxsw_sp_sb_pool_get,
3942 .sb_pool_set = mlxsw_sp_sb_pool_set,
3943 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3944 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3945 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3946 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3947 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3948 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3949 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3950 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3951 .trap_init = mlxsw_sp_trap_init,
3952 .trap_fini = mlxsw_sp_trap_fini,
3953 .trap_action_set = mlxsw_sp_trap_action_set,
3954 .trap_group_init = mlxsw_sp_trap_group_init,
3955 .trap_group_set = mlxsw_sp_trap_group_set,
3956 .trap_policer_init = mlxsw_sp_trap_policer_init,
3957 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
3958 .trap_policer_set = mlxsw_sp_trap_policer_set,
3959 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
3960 .txhdr_construct = mlxsw_sp_txhdr_construct,
3961 .resources_register = mlxsw_sp2_resources_register,
3962 .params_register = mlxsw_sp2_params_register,
3963 .params_unregister = mlxsw_sp2_params_unregister,
3964 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
3965 .txhdr_len = MLXSW_TXHDR_LEN,
3966 .profile = &mlxsw_sp2_config_profile,
3967 .sdq_supports_cqe_v2 = true,
3970 static struct mlxsw_driver mlxsw_sp3_driver = {
3971 .kind = mlxsw_sp3_driver_name,
3972 .priv_size = sizeof(struct mlxsw_sp),
3973 .fw_req_rev = &mlxsw_sp3_fw_rev,
3974 .fw_filename = MLXSW_SP3_FW_FILENAME,
3975 .init = mlxsw_sp3_init,
3976 .fini = mlxsw_sp_fini,
3977 .port_split = mlxsw_sp_port_split,
3978 .port_unsplit = mlxsw_sp_port_unsplit,
3979 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
3980 .sb_pool_get = mlxsw_sp_sb_pool_get,
3981 .sb_pool_set = mlxsw_sp_sb_pool_set,
3982 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3983 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3984 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3985 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3986 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3987 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3988 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3989 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3990 .trap_init = mlxsw_sp_trap_init,
3991 .trap_fini = mlxsw_sp_trap_fini,
3992 .trap_action_set = mlxsw_sp_trap_action_set,
3993 .trap_group_init = mlxsw_sp_trap_group_init,
3994 .trap_group_set = mlxsw_sp_trap_group_set,
3995 .trap_policer_init = mlxsw_sp_trap_policer_init,
3996 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
3997 .trap_policer_set = mlxsw_sp_trap_policer_set,
3998 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
3999 .txhdr_construct = mlxsw_sp_txhdr_construct,
4000 .resources_register = mlxsw_sp2_resources_register,
4001 .params_register = mlxsw_sp2_params_register,
4002 .params_unregister = mlxsw_sp2_params_unregister,
4003 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
4004 .txhdr_len = MLXSW_TXHDR_LEN,
4005 .profile = &mlxsw_sp2_config_profile,
4006 .sdq_supports_cqe_v2 = true,
4009 static struct mlxsw_driver mlxsw_sp4_driver = {
4010 .kind = mlxsw_sp4_driver_name,
4011 .priv_size = sizeof(struct mlxsw_sp),
4012 .init = mlxsw_sp4_init,
4013 .fini = mlxsw_sp_fini,
4014 .port_split = mlxsw_sp_port_split,
4015 .port_unsplit = mlxsw_sp_port_unsplit,
4016 .ports_remove_selected = mlxsw_sp_ports_remove_selected,
4017 .sb_pool_get = mlxsw_sp_sb_pool_get,
4018 .sb_pool_set = mlxsw_sp_sb_pool_set,
4019 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4020 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4021 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4022 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4023 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4024 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4025 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4026 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4027 .trap_init = mlxsw_sp_trap_init,
4028 .trap_fini = mlxsw_sp_trap_fini,
4029 .trap_action_set = mlxsw_sp_trap_action_set,
4030 .trap_group_init = mlxsw_sp_trap_group_init,
4031 .trap_group_set = mlxsw_sp_trap_group_set,
4032 .trap_policer_init = mlxsw_sp_trap_policer_init,
4033 .trap_policer_fini = mlxsw_sp_trap_policer_fini,
4034 .trap_policer_set = mlxsw_sp_trap_policer_set,
4035 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
4036 .txhdr_construct = mlxsw_sp_txhdr_construct,
4037 .resources_register = mlxsw_sp2_resources_register,
4038 .params_register = mlxsw_sp2_params_register,
4039 .params_unregister = mlxsw_sp2_params_unregister,
4040 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
4041 .txhdr_len = MLXSW_TXHDR_LEN,
4042 .profile = &mlxsw_sp2_config_profile,
4043 .sdq_supports_cqe_v2 = true,
4046 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4048 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4051 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev,
4052 struct netdev_nested_priv *priv)
4056 if (mlxsw_sp_port_dev_check(lower_dev)) {
4057 priv->data = (void *)netdev_priv(lower_dev);
4064 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
4066 struct netdev_nested_priv priv = {
4070 if (mlxsw_sp_port_dev_check(dev))
4071 return netdev_priv(dev);
4073 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv);
4075 return (struct mlxsw_sp_port *)priv.data;
4078 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4080 struct mlxsw_sp_port *mlxsw_sp_port;
4082 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4083 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4086 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4088 struct netdev_nested_priv priv = {
4092 if (mlxsw_sp_port_dev_check(dev))
4093 return netdev_priv(dev);
4095 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4098 return (struct mlxsw_sp_port *)priv.data;
4101 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4103 struct mlxsw_sp_port *mlxsw_sp_port;
4106 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4108 dev_hold(mlxsw_sp_port->dev);
4110 return mlxsw_sp_port;
4113 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4115 dev_put(mlxsw_sp_port->dev);
4118 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp)
4120 char mprs_pl[MLXSW_REG_MPRS_LEN];
4123 mutex_lock(&mlxsw_sp->parsing.lock);
4125 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref))
4128 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH,
4129 mlxsw_sp->parsing.vxlan_udp_dport);
4130 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4134 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH;
4135 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1);
4138 mutex_unlock(&mlxsw_sp->parsing.lock);
4142 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp)
4144 char mprs_pl[MLXSW_REG_MPRS_LEN];
4146 mutex_lock(&mlxsw_sp->parsing.lock);
4148 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref))
4151 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH,
4152 mlxsw_sp->parsing.vxlan_udp_dport);
4153 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4154 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
4157 mutex_unlock(&mlxsw_sp->parsing.lock);
4160 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp,
4163 char mprs_pl[MLXSW_REG_MPRS_LEN];
4166 mutex_lock(&mlxsw_sp->parsing.lock);
4168 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth,
4169 be16_to_cpu(udp_dport));
4170 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4174 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport);
4177 mutex_unlock(&mlxsw_sp->parsing.lock);
4182 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
4183 struct net_device *lag_dev)
4185 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
4186 struct net_device *upper_dev;
4187 struct list_head *iter;
4189 if (netif_is_bridge_port(lag_dev))
4190 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
4192 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4193 if (!netif_is_bridge_port(upper_dev))
4195 br_dev = netdev_master_upper_dev_get(upper_dev);
4196 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
4200 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4202 char sldr_pl[MLXSW_REG_SLDR_LEN];
4204 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4205 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4208 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4210 char sldr_pl[MLXSW_REG_SLDR_LEN];
4212 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4213 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4216 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4217 u16 lag_id, u8 port_index)
4219 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4220 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4222 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4223 lag_id, port_index);
4224 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4227 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4230 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4231 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4233 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4238 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4242 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4244 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4246 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4249 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4252 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4253 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4255 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4260 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4261 struct net_device *lag_dev,
4264 struct mlxsw_sp_upper *lag;
4265 int free_lag_id = -1;
4269 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4270 for (i = 0; i < max_lag; i++) {
4271 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4272 if (lag->ref_count) {
4273 if (lag->dev == lag_dev) {
4277 } else if (free_lag_id < 0) {
4281 if (free_lag_id < 0)
4283 *p_lag_id = free_lag_id;
4288 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4289 struct net_device *lag_dev,
4290 struct netdev_lag_upper_info *lag_upper_info,
4291 struct netlink_ext_ack *extack)
4295 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4296 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
4299 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4300 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4306 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4307 u16 lag_id, u8 *p_port_index)
4309 u64 max_lag_members;
4312 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4314 for (i = 0; i < max_lag_members; i++) {
4315 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4323 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4324 struct net_device *lag_dev,
4325 struct netlink_ext_ack *extack)
4327 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4328 struct mlxsw_sp_upper *lag;
4333 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4336 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4337 if (!lag->ref_count) {
4338 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4344 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4347 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4349 goto err_col_port_add;
4351 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4352 mlxsw_sp_port->local_port);
4353 mlxsw_sp_port->lag_id = lag_id;
4354 mlxsw_sp_port->lagged = 1;
4357 /* Port is no longer usable as a router interface */
4358 if (mlxsw_sp_port->default_vlan->fid)
4359 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
4361 /* Join a router interface configured on the LAG, if exists */
4362 err = mlxsw_sp_port_vlan_router_join(mlxsw_sp_port->default_vlan,
4365 goto err_router_join;
4371 mlxsw_sp_port->lagged = 0;
4372 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4373 mlxsw_sp_port->local_port);
4374 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4376 if (!lag->ref_count)
4377 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4381 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4382 struct net_device *lag_dev)
4384 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4385 u16 lag_id = mlxsw_sp_port->lag_id;
4386 struct mlxsw_sp_upper *lag;
4388 if (!mlxsw_sp_port->lagged)
4390 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4391 WARN_ON(lag->ref_count == 0);
4393 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4395 /* Any VLANs configured on the port are no longer valid */
4396 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
4397 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
4398 /* Make the LAG and its directly linked uppers leave bridges they
4401 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
4403 if (lag->ref_count == 1)
4404 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4406 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4407 mlxsw_sp_port->local_port);
4408 mlxsw_sp_port->lagged = 0;
4411 /* Make sure untagged frames are allowed to ingress */
4412 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
4416 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4419 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4420 char sldr_pl[MLXSW_REG_SLDR_LEN];
4422 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4423 mlxsw_sp_port->local_port);
4424 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4427 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4430 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4431 char sldr_pl[MLXSW_REG_SLDR_LEN];
4433 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4434 mlxsw_sp_port->local_port);
4435 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4439 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
4443 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
4444 mlxsw_sp_port->lag_id);
4448 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4450 goto err_dist_port_add;
4455 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4460 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
4464 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4465 mlxsw_sp_port->lag_id);
4469 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
4470 mlxsw_sp_port->lag_id);
4472 goto err_col_port_disable;
4476 err_col_port_disable:
4477 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4481 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4482 struct netdev_lag_lower_state_info *info)
4484 if (info->tx_enabled)
4485 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
4487 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4490 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4493 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4494 enum mlxsw_reg_spms_state spms_state;
4499 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4500 MLXSW_REG_SPMS_STATE_DISCARDING;
4502 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4505 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4507 for (vid = 0; vid < VLAN_N_VID; vid++)
4508 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4510 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4515 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4520 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4523 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4525 goto err_port_stp_set;
4526 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4529 goto err_port_vlan_set;
4531 for (; vid <= VLAN_N_VID - 1; vid++) {
4532 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4535 goto err_vid_learning_set;
4540 err_vid_learning_set:
4541 for (vid--; vid >= 1; vid--)
4542 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4544 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4546 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4550 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4554 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4555 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4558 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4560 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4561 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4564 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4566 unsigned int num_vxlans = 0;
4567 struct net_device *dev;
4568 struct list_head *iter;
4570 netdev_for_each_lower_dev(br_dev, dev, iter) {
4571 if (netif_is_vxlan(dev))
4575 return num_vxlans > 1;
4578 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
4580 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
4581 struct net_device *dev;
4582 struct list_head *iter;
4584 netdev_for_each_lower_dev(br_dev, dev, iter) {
4588 if (!netif_is_vxlan(dev))
4591 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
4595 if (test_and_set_bit(pvid, vlans))
4602 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4603 struct netlink_ext_ack *extack)
4605 if (br_multicast_enabled(br_dev)) {
4606 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4610 if (!br_vlan_enabled(br_dev) &&
4611 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4612 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4616 if (br_vlan_enabled(br_dev) &&
4617 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
4618 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
4625 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4626 struct net_device *dev,
4627 unsigned long event, void *ptr)
4629 struct netdev_notifier_changeupper_info *info;
4630 struct mlxsw_sp_port *mlxsw_sp_port;
4631 struct netlink_ext_ack *extack;
4632 struct net_device *upper_dev;
4633 struct mlxsw_sp *mlxsw_sp;
4637 mlxsw_sp_port = netdev_priv(dev);
4638 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4640 extack = netdev_notifier_info_to_extack(&info->info);
4643 case NETDEV_PRECHANGEUPPER:
4644 upper_dev = info->upper_dev;
4645 if (!is_vlan_dev(upper_dev) &&
4646 !netif_is_lag_master(upper_dev) &&
4647 !netif_is_bridge_master(upper_dev) &&
4648 !netif_is_ovs_master(upper_dev) &&
4649 !netif_is_macvlan(upper_dev) &&
4650 !netif_is_l3_master(upper_dev)) {
4651 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4656 if (netif_is_bridge_master(upper_dev) &&
4657 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4658 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4659 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4661 if (netdev_has_any_upper_dev(upper_dev) &&
4662 (!netif_is_bridge_master(upper_dev) ||
4663 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4665 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4668 if (netif_is_lag_master(upper_dev) &&
4669 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4670 info->upper_info, extack))
4672 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4673 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4676 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4677 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4678 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4681 if (netif_is_macvlan(upper_dev) &&
4682 !mlxsw_sp_rif_exists(mlxsw_sp, lower_dev)) {
4683 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4686 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4687 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4690 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4691 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4694 if (netif_is_bridge_master(upper_dev)) {
4695 br_vlan_get_proto(upper_dev, &proto);
4696 if (br_vlan_enabled(upper_dev) &&
4697 proto != ETH_P_8021Q && proto != ETH_P_8021AD) {
4698 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported");
4701 if (vlan_uses_dev(lower_dev) &&
4702 br_vlan_enabled(upper_dev) &&
4703 proto == ETH_P_8021AD) {
4704 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported");
4708 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) {
4709 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev);
4711 if (br_vlan_enabled(br_dev)) {
4712 br_vlan_get_proto(br_dev, &proto);
4713 if (proto == ETH_P_8021AD) {
4714 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge");
4719 if (is_vlan_dev(upper_dev) &&
4720 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
4721 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
4725 case NETDEV_CHANGEUPPER:
4726 upper_dev = info->upper_dev;
4727 if (netif_is_bridge_master(upper_dev)) {
4729 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4734 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4737 } else if (netif_is_lag_master(upper_dev)) {
4738 if (info->linking) {
4739 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4742 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4743 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4746 } else if (netif_is_ovs_master(upper_dev)) {
4748 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4750 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4751 } else if (netif_is_macvlan(upper_dev)) {
4753 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4754 } else if (is_vlan_dev(upper_dev)) {
4755 struct net_device *br_dev;
4757 if (!netif_is_bridge_port(upper_dev))
4761 br_dev = netdev_master_upper_dev_get(upper_dev);
4762 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
4771 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4772 unsigned long event, void *ptr)
4774 struct netdev_notifier_changelowerstate_info *info;
4775 struct mlxsw_sp_port *mlxsw_sp_port;
4778 mlxsw_sp_port = netdev_priv(dev);
4782 case NETDEV_CHANGELOWERSTATE:
4783 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4784 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4785 info->lower_state_info);
4787 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4795 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4796 struct net_device *port_dev,
4797 unsigned long event, void *ptr)
4800 case NETDEV_PRECHANGEUPPER:
4801 case NETDEV_CHANGEUPPER:
4802 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4804 case NETDEV_CHANGELOWERSTATE:
4805 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4812 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4813 unsigned long event, void *ptr)
4815 struct net_device *dev;
4816 struct list_head *iter;
4819 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4820 if (mlxsw_sp_port_dev_check(dev)) {
4821 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4831 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4832 struct net_device *dev,
4833 unsigned long event, void *ptr,
4836 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4837 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4838 struct netdev_notifier_changeupper_info *info = ptr;
4839 struct netlink_ext_ack *extack;
4840 struct net_device *upper_dev;
4843 extack = netdev_notifier_info_to_extack(&info->info);
4846 case NETDEV_PRECHANGEUPPER:
4847 upper_dev = info->upper_dev;
4848 if (!netif_is_bridge_master(upper_dev) &&
4849 !netif_is_macvlan(upper_dev) &&
4850 !netif_is_l3_master(upper_dev)) {
4851 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4856 if (netif_is_bridge_master(upper_dev) &&
4857 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4858 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4859 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4861 if (netdev_has_any_upper_dev(upper_dev) &&
4862 (!netif_is_bridge_master(upper_dev) ||
4863 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4865 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
4868 if (netif_is_macvlan(upper_dev) &&
4869 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
4870 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4874 case NETDEV_CHANGEUPPER:
4875 upper_dev = info->upper_dev;
4876 if (netif_is_bridge_master(upper_dev)) {
4878 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4883 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4886 } else if (netif_is_macvlan(upper_dev)) {
4888 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4896 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4897 struct net_device *lag_dev,
4898 unsigned long event,
4901 struct net_device *dev;
4902 struct list_head *iter;
4905 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4906 if (mlxsw_sp_port_dev_check(dev)) {
4907 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4918 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
4919 struct net_device *br_dev,
4920 unsigned long event, void *ptr,
4923 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
4924 struct netdev_notifier_changeupper_info *info = ptr;
4925 struct netlink_ext_ack *extack;
4926 struct net_device *upper_dev;
4931 extack = netdev_notifier_info_to_extack(&info->info);
4934 case NETDEV_PRECHANGEUPPER:
4935 upper_dev = info->upper_dev;
4936 if (!netif_is_macvlan(upper_dev) &&
4937 !netif_is_l3_master(upper_dev)) {
4938 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4943 if (netif_is_macvlan(upper_dev) &&
4944 !mlxsw_sp_rif_exists(mlxsw_sp, vlan_dev)) {
4945 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
4949 case NETDEV_CHANGEUPPER:
4950 upper_dev = info->upper_dev;
4953 if (netif_is_macvlan(upper_dev))
4954 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4961 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4962 unsigned long event, void *ptr)
4964 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4965 u16 vid = vlan_dev_vlan_id(vlan_dev);
4967 if (mlxsw_sp_port_dev_check(real_dev))
4968 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4970 else if (netif_is_lag_master(real_dev))
4971 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4974 else if (netif_is_bridge_master(real_dev))
4975 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
4981 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4982 unsigned long event, void *ptr)
4984 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4985 struct netdev_notifier_changeupper_info *info = ptr;
4986 struct netlink_ext_ack *extack;
4987 struct net_device *upper_dev;
4993 extack = netdev_notifier_info_to_extack(&info->info);
4996 case NETDEV_PRECHANGEUPPER:
4997 upper_dev = info->upper_dev;
4998 if (!is_vlan_dev(upper_dev) &&
4999 !netif_is_macvlan(upper_dev) &&
5000 !netif_is_l3_master(upper_dev)) {
5001 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5006 if (br_vlan_enabled(br_dev)) {
5007 br_vlan_get_proto(br_dev, &proto);
5008 if (proto == ETH_P_8021AD) {
5009 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge");
5013 if (is_vlan_dev(upper_dev) &&
5014 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
5015 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
5018 if (netif_is_macvlan(upper_dev) &&
5019 !mlxsw_sp_rif_exists(mlxsw_sp, br_dev)) {
5020 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
5024 case NETDEV_CHANGEUPPER:
5025 upper_dev = info->upper_dev;
5028 if (is_vlan_dev(upper_dev))
5029 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
5030 if (netif_is_macvlan(upper_dev))
5031 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5038 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
5039 unsigned long event, void *ptr)
5041 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
5042 struct netdev_notifier_changeupper_info *info = ptr;
5043 struct netlink_ext_ack *extack;
5044 struct net_device *upper_dev;
5046 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
5049 extack = netdev_notifier_info_to_extack(&info->info);
5050 upper_dev = info->upper_dev;
5052 if (!netif_is_l3_master(upper_dev)) {
5053 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5060 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
5061 struct net_device *dev,
5062 unsigned long event, void *ptr)
5064 struct netdev_notifier_changeupper_info *cu_info;
5065 struct netdev_notifier_info *info = ptr;
5066 struct netlink_ext_ack *extack;
5067 struct net_device *upper_dev;
5069 extack = netdev_notifier_info_to_extack(info);
5072 case NETDEV_CHANGEUPPER:
5073 cu_info = container_of(info,
5074 struct netdev_notifier_changeupper_info,
5076 upper_dev = cu_info->upper_dev;
5077 if (!netif_is_bridge_master(upper_dev))
5079 if (!mlxsw_sp_lower_get(upper_dev))
5081 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5083 if (cu_info->linking) {
5084 if (!netif_running(dev))
5086 /* When the bridge is VLAN-aware, the VNI of the VxLAN
5087 * device needs to be mapped to a VLAN, but at this
5088 * point no VLANs are configured on the VxLAN device
5090 if (br_vlan_enabled(upper_dev))
5092 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5095 /* VLANs were already flushed, which triggered the
5098 if (br_vlan_enabled(upper_dev))
5100 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5104 upper_dev = netdev_master_upper_dev_get(dev);
5107 if (!netif_is_bridge_master(upper_dev))
5109 if (!mlxsw_sp_lower_get(upper_dev))
5111 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
5114 upper_dev = netdev_master_upper_dev_get(dev);
5117 if (!netif_is_bridge_master(upper_dev))
5119 if (!mlxsw_sp_lower_get(upper_dev))
5121 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5128 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5129 unsigned long event, void *ptr)
5131 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5132 struct mlxsw_sp_span_entry *span_entry;
5133 struct mlxsw_sp *mlxsw_sp;
5136 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5137 if (event == NETDEV_UNREGISTER) {
5138 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5140 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5142 mlxsw_sp_span_respin(mlxsw_sp);
5144 if (netif_is_vxlan(dev))
5145 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5146 else if (mlxsw_sp_port_dev_check(dev))
5147 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
5148 else if (netif_is_lag_master(dev))
5149 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5150 else if (is_vlan_dev(dev))
5151 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
5152 else if (netif_is_bridge_master(dev))
5153 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
5154 else if (netif_is_macvlan(dev))
5155 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5157 return notifier_from_errno(err);
5160 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
5161 .notifier_call = mlxsw_sp_inetaddr_valid_event,
5164 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
5165 .notifier_call = mlxsw_sp_inet6addr_valid_event,
5168 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5169 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5173 static struct pci_driver mlxsw_sp1_pci_driver = {
5174 .name = mlxsw_sp1_driver_name,
5175 .id_table = mlxsw_sp1_pci_id_table,
5178 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5179 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
5183 static struct pci_driver mlxsw_sp2_pci_driver = {
5184 .name = mlxsw_sp2_driver_name,
5185 .id_table = mlxsw_sp2_pci_id_table,
5188 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
5189 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
5193 static struct pci_driver mlxsw_sp3_pci_driver = {
5194 .name = mlxsw_sp3_driver_name,
5195 .id_table = mlxsw_sp3_pci_id_table,
5198 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = {
5199 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0},
5203 static struct pci_driver mlxsw_sp4_pci_driver = {
5204 .name = mlxsw_sp4_driver_name,
5205 .id_table = mlxsw_sp4_pci_id_table,
5208 static int __init mlxsw_sp_module_init(void)
5212 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5213 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5215 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5217 goto err_sp1_core_driver_register;
5219 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5221 goto err_sp2_core_driver_register;
5223 err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
5225 goto err_sp3_core_driver_register;
5227 err = mlxsw_core_driver_register(&mlxsw_sp4_driver);
5229 goto err_sp4_core_driver_register;
5231 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5233 goto err_sp1_pci_driver_register;
5235 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5237 goto err_sp2_pci_driver_register;
5239 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
5241 goto err_sp3_pci_driver_register;
5243 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver);
5245 goto err_sp4_pci_driver_register;
5249 err_sp4_pci_driver_register:
5250 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5251 err_sp3_pci_driver_register:
5252 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5253 err_sp2_pci_driver_register:
5254 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5255 err_sp1_pci_driver_register:
5256 mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5257 err_sp4_core_driver_register:
5258 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5259 err_sp3_core_driver_register:
5260 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5261 err_sp2_core_driver_register:
5262 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5263 err_sp1_core_driver_register:
5264 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5265 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5269 static void __exit mlxsw_sp_module_exit(void)
5271 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver);
5272 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5273 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5274 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5275 mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5276 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5277 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5278 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5279 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
5280 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5283 module_init(mlxsw_sp_module_init);
5284 module_exit(mlxsw_sp_module_exit);
5286 MODULE_LICENSE("Dual BSD/GPL");
5287 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5288 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5289 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5290 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5291 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
5292 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table);
5293 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
5294 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
5295 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);
5296 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME);