1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
3 /* Header file for Mellanox BlueField GigE register defines
5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
8 #ifndef __MLXBF_GIGE_REGS_H__
9 #define __MLXBF_GIGE_REGS_H__
11 #define MLXBF_GIGE_VERSION 0x0000
12 #define MLXBF_GIGE_VERSION_BF2 0x0
13 #define MLXBF_GIGE_STATUS 0x0010
14 #define MLXBF_GIGE_STATUS_READY BIT(0)
15 #define MLXBF_GIGE_INT_STATUS 0x0028
16 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)
17 #define MLXBF_GIGE_INT_STATUS_RX_MAC_ERROR BIT(1)
18 #define MLXBF_GIGE_INT_STATUS_RX_TRN_ERROR BIT(2)
19 #define MLXBF_GIGE_INT_STATUS_SW_ACCESS_ERROR BIT(3)
20 #define MLXBF_GIGE_INT_STATUS_SW_CONFIG_ERROR BIT(4)
21 #define MLXBF_GIGE_INT_STATUS_TX_PI_CI_EXCEED_WQ_SIZE BIT(5)
22 #define MLXBF_GIGE_INT_STATUS_TX_SMALL_FRAME_SIZE BIT(6)
23 #define MLXBF_GIGE_INT_STATUS_TX_CHECKSUM_INPUTS BIT(7)
24 #define MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR BIT(8)
25 #define MLXBF_GIGE_INT_EN 0x0030
26 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)
27 #define MLXBF_GIGE_INT_EN_RX_MAC_ERROR BIT(1)
28 #define MLXBF_GIGE_INT_EN_RX_TRN_ERROR BIT(2)
29 #define MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR BIT(3)
30 #define MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR BIT(4)
31 #define MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE BIT(5)
32 #define MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE BIT(6)
33 #define MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS BIT(7)
34 #define MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR BIT(8)
35 #define MLXBF_GIGE_INT_MASK 0x0038
36 #define MLXBF_GIGE_INT_MASK_RX_RECEIVE_PACKET BIT(0)
37 #define MLXBF_GIGE_CONTROL 0x0040
38 #define MLXBF_GIGE_CONTROL_PORT_EN BIT(0)
39 #define MLXBF_GIGE_CONTROL_MAC_ID_RANGE_EN BIT(1)
40 #define MLXBF_GIGE_CONTROL_EN_SPECIFIC_MAC BIT(4)
41 #define MLXBF_GIGE_CONTROL_CLEAN_PORT_EN BIT(31)
42 #define MLXBF_GIGE_RX_WQ_BASE 0x0200
43 #define MLXBF_GIGE_RX_WQE_SIZE_LOG2 0x0208
44 #define MLXBF_GIGE_RX_WQE_SIZE_LOG2_RESET_VAL 7
45 #define MLXBF_GIGE_RX_CQ_BASE 0x0210
46 #define MLXBF_GIGE_TX_WQ_BASE 0x0218
47 #define MLXBF_GIGE_TX_WQ_SIZE_LOG2 0x0220
48 #define MLXBF_GIGE_TX_WQ_SIZE_LOG2_RESET_VAL 7
49 #define MLXBF_GIGE_TX_CI_UPDATE_ADDRESS 0x0228
50 #define MLXBF_GIGE_RX_WQE_PI 0x0230
51 #define MLXBF_GIGE_TX_PRODUCER_INDEX 0x0238
52 #define MLXBF_GIGE_RX_MAC_FILTER 0x0240
53 #define MLXBF_GIGE_RX_MAC_FILTER_STRIDE 0x0008
54 #define MLXBF_GIGE_RX_DIN_DROP_COUNTER 0x0260
55 #define MLXBF_GIGE_TX_CONSUMER_INDEX 0x0310
56 #define MLXBF_GIGE_TX_CONTROL 0x0318
57 #define MLXBF_GIGE_TX_CONTROL_GRACEFUL_STOP BIT(0)
58 #define MLXBF_GIGE_TX_STATUS 0x0388
59 #define MLXBF_GIGE_TX_STATUS_DATA_FIFO_FULL BIT(1)
60 #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_START 0x0520
61 #define MLXBF_GIGE_RX_MAC_FILTER_DMAC_RANGE_END 0x0528
62 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC 0x0540
63 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_DISC_EN BIT(0)
64 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS 0x0548
65 #define MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN BIT(0)
66 #define MLXBF_GIGE_RX_PASS_COUNTER_ALL 0x0550
67 #define MLXBF_GIGE_RX_DISC_COUNTER_ALL 0x0560
68 #define MLXBF_GIGE_RX 0x0578
69 #define MLXBF_GIGE_RX_STRIP_CRC_EN BIT(1)
70 #define MLXBF_GIGE_RX_DMA 0x0580
71 #define MLXBF_GIGE_RX_DMA_EN BIT(0)
72 #define MLXBF_GIGE_RX_CQE_PACKET_CI 0x05b0
73 #define MLXBF_GIGE_MAC_CFG 0x05e8
75 /* NOTE: MLXBF_GIGE_MAC_CFG is the last defined register offset,
76 * so use that plus size of single register to derive total size
78 #define MLXBF_GIGE_MMIO_REG_SZ (MLXBF_GIGE_MAC_CFG + 8)
80 #endif /* !defined(__MLXBF_GIGE_REGS_H__) */