2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #include <linux/mlx5/vport.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
57 #ifdef CONFIG_MLX5_CORE_EN
61 #include "fpga/core.h"
62 #include "accel/ipsec.h"
64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
66 MODULE_LICENSE("Dual BSD/GPL");
67 MODULE_VERSION(DRIVER_VERSION);
69 unsigned int mlx5_core_debug_mask;
70 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
71 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
73 #define MLX5_DEFAULT_PROF 2
74 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
75 module_param_named(prof_sel, prof_sel, uint, 0444);
76 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
79 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
80 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
83 static struct mlx5_profile profile[] = {
88 .mask = MLX5_PROF_MASK_QP_SIZE,
92 .mask = MLX5_PROF_MASK_QP_SIZE |
93 MLX5_PROF_MASK_MR_CACHE,
182 #define FW_INIT_TIMEOUT_MILI 2000
183 #define FW_INIT_WAIT_MS 2
184 #define FW_PRE_INIT_TIMEOUT_MILI 10000
186 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
188 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
191 while (fw_initializing(dev)) {
192 if (time_after(jiffies, end)) {
196 msleep(FW_INIT_WAIT_MS);
202 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
204 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
206 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
207 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
208 int remaining_size = driver_ver_sz;
211 if (!MLX5_CAP_GEN(dev, driver_version))
214 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
216 strncpy(string, "Linux", remaining_size);
218 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
219 strncat(string, ",", remaining_size);
221 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
222 strncat(string, DRIVER_NAME, remaining_size);
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, ",", remaining_size);
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, DRIVER_VERSION, remaining_size);
231 MLX5_SET(set_driver_version_in, in, opcode,
232 MLX5_CMD_OP_SET_DRIVER_VERSION);
234 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
237 static int set_dma_caps(struct pci_dev *pdev)
241 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
243 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
244 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
246 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
251 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
254 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
255 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
258 "Can't set consistent PCI DMA mask, aborting\n");
263 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
267 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
269 struct pci_dev *pdev = dev->pdev;
272 mutex_lock(&dev->pci_status_mutex);
273 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
274 err = pci_enable_device(pdev);
276 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
278 mutex_unlock(&dev->pci_status_mutex);
283 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
285 struct pci_dev *pdev = dev->pdev;
287 mutex_lock(&dev->pci_status_mutex);
288 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
289 pci_disable_device(pdev);
290 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
292 mutex_unlock(&dev->pci_status_mutex);
295 static int request_bar(struct pci_dev *pdev)
299 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
300 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
304 err = pci_request_regions(pdev, DRIVER_NAME);
306 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
311 static void release_bar(struct pci_dev *pdev)
313 pci_release_regions(pdev);
316 static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
318 struct mlx5_priv *priv = &dev->priv;
319 struct mlx5_eq_table *table = &priv->eq_table;
320 struct irq_affinity irqdesc = {
321 .pre_vectors = MLX5_EQ_VEC_COMP_BASE,
323 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
326 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
327 MLX5_EQ_VEC_COMP_BASE;
328 nvec = min_t(int, nvec, num_eqs);
329 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
332 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
336 nvec = pci_alloc_irq_vectors_affinity(dev->pdev,
337 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
338 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
343 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
348 kfree(priv->irq_info);
352 static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
354 struct mlx5_priv *priv = &dev->priv;
356 pci_free_irq_vectors(dev->pdev);
357 kfree(priv->irq_info);
360 struct mlx5_reg_host_endianness {
365 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
368 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
369 MLX5_DEV_CAP_FLAG_DCT,
372 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
388 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
393 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
394 enum mlx5_cap_type cap_type,
395 enum mlx5_cap_mode cap_mode)
397 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
398 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
399 void *out, *hca_caps;
400 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
403 memset(in, 0, sizeof(in));
404 out = kzalloc(out_sz, GFP_KERNEL);
408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
409 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
410 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
413 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
414 cap_type, cap_mode, err);
418 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
421 case HCA_CAP_OPMOD_GET_MAX:
422 memcpy(dev->caps.hca_max[cap_type], hca_caps,
423 MLX5_UN_SZ_BYTES(hca_cap_union));
425 case HCA_CAP_OPMOD_GET_CUR:
426 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
427 MLX5_UN_SZ_BYTES(hca_cap_union));
431 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
441 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
445 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
448 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
451 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
453 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
455 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
456 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
457 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
460 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
464 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
468 if (MLX5_CAP_GEN(dev, atomic)) {
469 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
478 supported_atomic_req_8B_endianness_mode_1);
480 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
483 set_ctx = kzalloc(set_sz, GFP_KERNEL);
487 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
489 /* Set requestor to host endianness */
490 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
491 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
493 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
499 static int handle_hca_cap(struct mlx5_core_dev *dev)
501 void *set_ctx = NULL;
502 struct mlx5_profile *prof = dev->profile;
504 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
507 set_ctx = kzalloc(set_sz, GFP_KERNEL);
511 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
515 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
517 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
518 MLX5_ST_SZ_BYTES(cmd_hca_cap));
520 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
521 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
523 /* we limit the size of the pkey table to 128 entries for now */
524 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
525 to_fw_pkey_sz(dev, 128));
527 /* Check log_max_qp from HCA caps to set in current profile */
528 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
529 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
530 profile[prof_sel].log_max_qp,
531 MLX5_CAP_GEN_MAX(dev, log_max_qp));
532 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
534 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 /* disable cmdif checksum */
539 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
541 /* Enable 4K UAR only when HCA supports it and page size is bigger
544 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
545 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
547 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
549 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
550 MLX5_SET(cmd_hca_cap,
553 cache_line_size() == 128 ? 1 : 0);
555 err = set_caps(dev, set_ctx, set_sz,
556 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
563 static int set_hca_ctrl(struct mlx5_core_dev *dev)
565 struct mlx5_reg_host_endianness he_in;
566 struct mlx5_reg_host_endianness he_out;
569 if (!mlx5_core_is_pf(dev))
572 memset(&he_in, 0, sizeof(he_in));
573 he_in.he = MLX5_SET_HOST_ENDIANNESS;
574 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
575 &he_out, sizeof(he_out),
576 MLX5_REG_HOST_ENDIANNESS, 0, 1);
580 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
584 /* Disable local_lb by default */
585 if ((MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
586 MLX5_CAP_GEN(dev, disable_local_lb))
587 ret = mlx5_nic_vport_update_local_lb(dev, false);
592 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
594 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
595 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
597 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
598 MLX5_SET(enable_hca_in, in, function_id, func_id);
599 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
602 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
604 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
605 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
607 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
608 MLX5_SET(disable_hca_in, in, function_id, func_id);
609 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
612 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
614 u32 timer_h, timer_h1, timer_l;
616 timer_h = ioread32be(&dev->iseg->internal_timer_h);
617 timer_l = ioread32be(&dev->iseg->internal_timer_l);
618 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
619 if (timer_h != timer_h1) /* wrap around */
620 timer_l = ioread32be(&dev->iseg->internal_timer_l);
622 return (u64)timer_l | (u64)timer_h1 << 32;
625 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
628 struct mlx5_eq_table *table = &dev->priv.eq_table;
629 struct mlx5_eq *eq, *n;
632 spin_lock(&table->lock);
633 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
634 if (eq->index == vector) {
641 spin_unlock(&table->lock);
645 EXPORT_SYMBOL(mlx5_vector2eqn);
647 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
649 struct mlx5_eq_table *table = &dev->priv.eq_table;
652 spin_lock(&table->lock);
653 list_for_each_entry(eq, &table->comp_eqs_list, list)
654 if (eq->eqn == eqn) {
655 spin_unlock(&table->lock);
659 spin_unlock(&table->lock);
661 return ERR_PTR(-ENOENT);
664 static void free_comp_eqs(struct mlx5_core_dev *dev)
666 struct mlx5_eq_table *table = &dev->priv.eq_table;
667 struct mlx5_eq *eq, *n;
669 #ifdef CONFIG_RFS_ACCEL
671 free_irq_cpu_rmap(dev->rmap);
675 spin_lock(&table->lock);
676 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
678 spin_unlock(&table->lock);
679 if (mlx5_destroy_unmap_eq(dev, eq))
680 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
683 spin_lock(&table->lock);
685 spin_unlock(&table->lock);
688 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
690 struct mlx5_eq_table *table = &dev->priv.eq_table;
691 char name[MLX5_MAX_IRQ_NAME];
698 INIT_LIST_HEAD(&table->comp_eqs_list);
699 ncomp_vec = table->num_comp_vectors;
700 nent = MLX5_COMP_EQ_SIZE;
701 #ifdef CONFIG_RFS_ACCEL
702 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
706 for (i = 0; i < ncomp_vec; i++) {
707 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
713 #ifdef CONFIG_RFS_ACCEL
714 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
715 MLX5_EQ_VEC_COMP_BASE + i));
717 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
718 err = mlx5_create_map_eq(dev, eq,
719 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
720 name, MLX5_EQ_TYPE_COMP);
725 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
727 spin_lock(&table->lock);
728 list_add_tail(&eq->list, &table->comp_eqs_list);
729 spin_unlock(&table->lock);
739 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
741 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
742 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
746 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
747 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
748 query_out, sizeof(query_out));
753 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
754 if (!status || syndrome == MLX5_DRIVER_SYND) {
755 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
756 err, status, syndrome);
760 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
765 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
767 if (sup_issi & (1 << 1)) {
768 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
769 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
771 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
772 MLX5_SET(set_issi_in, set_in, current_issi, 1);
773 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
774 set_out, sizeof(set_out));
776 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
784 } else if (sup_issi & (1 << 0) || !sup_issi) {
792 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
794 struct pci_dev *pdev = dev->pdev;
797 pci_set_drvdata(dev->pdev, dev);
798 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
799 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
801 mutex_init(&priv->pgdir_mutex);
802 INIT_LIST_HEAD(&priv->pgdir_list);
803 spin_lock_init(&priv->mkey_lock);
805 mutex_init(&priv->alloc_mutex);
807 priv->numa_node = dev_to_node(&dev->pdev->dev);
809 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
813 err = mlx5_pci_enable_device(dev);
815 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
819 err = request_bar(pdev);
821 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
825 pci_set_master(pdev);
827 err = set_dma_caps(pdev);
829 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
833 dev->iseg_base = pci_resource_start(dev->pdev, 0);
834 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
837 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
844 pci_clear_master(dev->pdev);
845 release_bar(dev->pdev);
847 mlx5_pci_disable_device(dev);
850 debugfs_remove(priv->dbg_root);
854 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
857 pci_clear_master(dev->pdev);
858 release_bar(dev->pdev);
859 mlx5_pci_disable_device(dev);
860 debugfs_remove(priv->dbg_root);
863 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
865 struct pci_dev *pdev = dev->pdev;
868 err = mlx5_query_board_id(dev);
870 dev_err(&pdev->dev, "query board id failed\n");
874 err = mlx5_eq_init(dev);
876 dev_err(&pdev->dev, "failed to initialize eq\n");
880 err = mlx5_init_cq_table(dev);
882 dev_err(&pdev->dev, "failed to initialize cq table\n");
886 mlx5_init_qp_table(dev);
888 mlx5_init_srq_table(dev);
890 mlx5_init_mkey_table(dev);
892 mlx5_init_reserved_gids(dev);
894 err = mlx5_init_rl_table(dev);
896 dev_err(&pdev->dev, "Failed to init rate limiting\n");
897 goto err_tables_cleanup;
900 #ifdef CONFIG_MLX5_CORE_EN
901 err = mlx5_eswitch_init(dev);
903 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
908 err = mlx5_sriov_init(dev);
910 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
911 goto err_eswitch_cleanup;
914 err = mlx5_fpga_init(dev);
916 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
917 goto err_sriov_cleanup;
923 mlx5_sriov_cleanup(dev);
925 #ifdef CONFIG_MLX5_CORE_EN
926 mlx5_eswitch_cleanup(dev->priv.eswitch);
930 mlx5_cleanup_rl_table(dev);
933 mlx5_cleanup_mkey_table(dev);
934 mlx5_cleanup_srq_table(dev);
935 mlx5_cleanup_qp_table(dev);
936 mlx5_cleanup_cq_table(dev);
939 mlx5_eq_cleanup(dev);
945 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
947 mlx5_fpga_cleanup(dev);
948 mlx5_sriov_cleanup(dev);
949 #ifdef CONFIG_MLX5_CORE_EN
950 mlx5_eswitch_cleanup(dev->priv.eswitch);
952 mlx5_cleanup_rl_table(dev);
953 mlx5_cleanup_reserved_gids(dev);
954 mlx5_cleanup_mkey_table(dev);
955 mlx5_cleanup_srq_table(dev);
956 mlx5_cleanup_qp_table(dev);
957 mlx5_cleanup_cq_table(dev);
958 mlx5_eq_cleanup(dev);
961 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
964 struct pci_dev *pdev = dev->pdev;
967 mutex_lock(&dev->intf_state_mutex);
968 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
969 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
974 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
975 fw_rev_min(dev), fw_rev_sub(dev));
977 /* on load removing any previous indication of internal error, device is
980 dev->state = MLX5_DEVICE_STATE_UP;
982 /* wait for firmware to accept initialization segments configurations
984 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
986 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
987 FW_PRE_INIT_TIMEOUT_MILI);
991 err = mlx5_cmd_init(dev);
993 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
997 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
999 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1000 FW_INIT_TIMEOUT_MILI);
1001 goto err_cmd_cleanup;
1004 err = mlx5_core_enable_hca(dev, 0);
1006 dev_err(&pdev->dev, "enable hca failed\n");
1007 goto err_cmd_cleanup;
1010 err = mlx5_core_set_issi(dev);
1012 dev_err(&pdev->dev, "failed to set issi\n");
1013 goto err_disable_hca;
1016 err = mlx5_satisfy_startup_pages(dev, 1);
1018 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1019 goto err_disable_hca;
1022 err = set_hca_ctrl(dev);
1024 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1025 goto reclaim_boot_pages;
1028 err = handle_hca_cap(dev);
1030 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1031 goto reclaim_boot_pages;
1034 err = handle_hca_cap_atomic(dev);
1036 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1037 goto reclaim_boot_pages;
1040 err = mlx5_satisfy_startup_pages(dev, 0);
1042 dev_err(&pdev->dev, "failed to allocate init pages\n");
1043 goto reclaim_boot_pages;
1046 err = mlx5_pagealloc_start(dev);
1048 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1049 goto reclaim_boot_pages;
1052 err = mlx5_cmd_init_hca(dev);
1054 dev_err(&pdev->dev, "init hca failed\n");
1055 goto err_pagealloc_stop;
1058 mlx5_set_driver_version(dev);
1060 mlx5_start_health_poll(dev);
1062 err = mlx5_query_hca_caps(dev);
1064 dev_err(&pdev->dev, "query hca failed\n");
1068 if (boot && mlx5_init_once(dev, priv)) {
1069 dev_err(&pdev->dev, "sw objs init failed\n");
1073 err = mlx5_alloc_irq_vectors(dev);
1075 dev_err(&pdev->dev, "alloc irq vectors failed\n");
1076 goto err_cleanup_once;
1079 dev->priv.uar = mlx5_get_uars_page(dev);
1080 if (!dev->priv.uar) {
1081 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1082 goto err_disable_msix;
1085 err = mlx5_start_eqs(dev);
1087 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1091 err = alloc_comp_eqs(dev);
1093 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1097 err = mlx5_init_fs(dev);
1099 dev_err(&pdev->dev, "Failed to init flow steering\n");
1103 err = mlx5_core_set_hca_defaults(dev);
1105 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1109 #ifdef CONFIG_MLX5_CORE_EN
1110 mlx5_eswitch_attach(dev->priv.eswitch);
1113 err = mlx5_sriov_attach(dev);
1115 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1119 err = mlx5_fpga_device_start(dev);
1121 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1122 goto err_fpga_start;
1124 err = mlx5_accel_ipsec_init(dev);
1126 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1127 goto err_ipsec_start;
1130 if (mlx5_device_registered(dev)) {
1131 mlx5_attach_device(dev);
1133 err = mlx5_register_device(dev);
1135 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1140 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1142 mutex_unlock(&dev->intf_state_mutex);
1147 mlx5_accel_ipsec_cleanup(dev);
1149 mlx5_fpga_device_stop(dev);
1152 mlx5_sriov_detach(dev);
1155 #ifdef CONFIG_MLX5_CORE_EN
1156 mlx5_eswitch_detach(dev->priv.eswitch);
1158 mlx5_cleanup_fs(dev);
1167 mlx5_put_uars_page(dev, priv->uar);
1170 mlx5_free_irq_vectors(dev);
1174 mlx5_cleanup_once(dev);
1177 mlx5_stop_health_poll(dev);
1178 if (mlx5_cmd_teardown_hca(dev)) {
1179 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1184 mlx5_pagealloc_stop(dev);
1187 mlx5_reclaim_startup_pages(dev);
1190 mlx5_core_disable_hca(dev, 0);
1193 mlx5_cmd_cleanup(dev);
1196 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1197 mutex_unlock(&dev->intf_state_mutex);
1202 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1208 mlx5_drain_health_recovery(dev);
1210 mutex_lock(&dev->intf_state_mutex);
1211 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1212 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1215 mlx5_cleanup_once(dev);
1219 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1221 if (mlx5_device_registered(dev))
1222 mlx5_detach_device(dev);
1224 mlx5_accel_ipsec_cleanup(dev);
1225 mlx5_fpga_device_stop(dev);
1227 mlx5_sriov_detach(dev);
1228 #ifdef CONFIG_MLX5_CORE_EN
1229 mlx5_eswitch_detach(dev->priv.eswitch);
1231 mlx5_cleanup_fs(dev);
1234 mlx5_put_uars_page(dev, priv->uar);
1235 mlx5_free_irq_vectors(dev);
1237 mlx5_cleanup_once(dev);
1238 mlx5_stop_health_poll(dev);
1239 err = mlx5_cmd_teardown_hca(dev);
1241 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1244 mlx5_pagealloc_stop(dev);
1245 mlx5_reclaim_startup_pages(dev);
1246 mlx5_core_disable_hca(dev, 0);
1247 mlx5_cmd_cleanup(dev);
1250 mutex_unlock(&dev->intf_state_mutex);
1254 struct mlx5_core_event_handler {
1255 void (*event)(struct mlx5_core_dev *dev,
1256 enum mlx5_dev_event event,
1260 static const struct devlink_ops mlx5_devlink_ops = {
1261 #ifdef CONFIG_MLX5_CORE_EN
1262 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1263 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1264 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1265 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1266 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1267 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1271 #define MLX5_IB_MOD "mlx5_ib"
1272 static int init_one(struct pci_dev *pdev,
1273 const struct pci_device_id *id)
1275 struct mlx5_core_dev *dev;
1276 struct devlink *devlink;
1277 struct mlx5_priv *priv;
1280 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1282 dev_err(&pdev->dev, "kzalloc failed\n");
1286 dev = devlink_priv(devlink);
1288 priv->pci_dev_data = id->driver_data;
1290 pci_set_drvdata(pdev, dev);
1293 dev->event = mlx5_core_event;
1294 dev->profile = &profile[prof_sel];
1296 INIT_LIST_HEAD(&priv->ctx_list);
1297 spin_lock_init(&priv->ctx_lock);
1298 mutex_init(&dev->pci_status_mutex);
1299 mutex_init(&dev->intf_state_mutex);
1301 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1302 err = init_srcu_struct(&priv->pfault_srcu);
1304 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1309 mutex_init(&priv->bfregs.reg_head.lock);
1310 mutex_init(&priv->bfregs.wc_head.lock);
1311 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1312 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1314 err = mlx5_pci_init(dev, priv);
1316 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1320 err = mlx5_health_init(dev);
1322 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1326 mlx5_pagealloc_init(dev);
1328 err = mlx5_load_one(dev, priv, true);
1330 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1334 request_module_nowait(MLX5_IB_MOD);
1336 err = devlink_register(devlink, &pdev->dev);
1340 pci_save_state(pdev);
1344 mlx5_unload_one(dev, priv, true);
1346 mlx5_pagealloc_cleanup(dev);
1347 mlx5_health_cleanup(dev);
1349 mlx5_pci_close(dev, priv);
1351 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1352 cleanup_srcu_struct(&priv->pfault_srcu);
1355 pci_set_drvdata(pdev, NULL);
1356 devlink_free(devlink);
1361 static void remove_one(struct pci_dev *pdev)
1363 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1364 struct devlink *devlink = priv_to_devlink(dev);
1365 struct mlx5_priv *priv = &dev->priv;
1367 devlink_unregister(devlink);
1368 mlx5_unregister_device(dev);
1370 if (mlx5_unload_one(dev, priv, true)) {
1371 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1372 mlx5_health_cleanup(dev);
1376 mlx5_pagealloc_cleanup(dev);
1377 mlx5_health_cleanup(dev);
1378 mlx5_pci_close(dev, priv);
1379 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1380 cleanup_srcu_struct(&priv->pfault_srcu);
1382 pci_set_drvdata(pdev, NULL);
1383 devlink_free(devlink);
1386 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1387 pci_channel_state_t state)
1389 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1390 struct mlx5_priv *priv = &dev->priv;
1392 dev_info(&pdev->dev, "%s was called\n", __func__);
1394 mlx5_enter_error_state(dev, false);
1395 mlx5_unload_one(dev, priv, false);
1396 /* In case of kernel call drain the health wq */
1398 mlx5_drain_health_wq(dev);
1399 mlx5_pci_disable_device(dev);
1402 return state == pci_channel_io_perm_failure ?
1403 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1406 /* wait for the device to show vital signs by waiting
1407 * for the health counter to start counting.
1409 static int wait_vital(struct pci_dev *pdev)
1411 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1412 struct mlx5_core_health *health = &dev->priv.health;
1413 const int niter = 100;
1418 for (i = 0; i < niter; i++) {
1419 count = ioread32be(health->health_counter);
1420 if (count && count != 0xffffffff) {
1421 if (last_count && last_count != count) {
1422 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1433 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1435 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1438 dev_info(&pdev->dev, "%s was called\n", __func__);
1440 err = mlx5_pci_enable_device(dev);
1442 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1444 return PCI_ERS_RESULT_DISCONNECT;
1447 pci_set_master(pdev);
1448 pci_restore_state(pdev);
1449 pci_save_state(pdev);
1451 if (wait_vital(pdev)) {
1452 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1453 return PCI_ERS_RESULT_DISCONNECT;
1456 return PCI_ERS_RESULT_RECOVERED;
1459 static void mlx5_pci_resume(struct pci_dev *pdev)
1461 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1462 struct mlx5_priv *priv = &dev->priv;
1465 dev_info(&pdev->dev, "%s was called\n", __func__);
1467 err = mlx5_load_one(dev, priv, false);
1469 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1472 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1475 static const struct pci_error_handlers mlx5_err_handler = {
1476 .error_detected = mlx5_pci_err_detected,
1477 .slot_reset = mlx5_pci_slot_reset,
1478 .resume = mlx5_pci_resume
1481 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1485 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1486 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1490 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1491 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1495 ret = mlx5_cmd_force_teardown_hca(dev);
1497 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1501 mlx5_enter_error_state(dev, true);
1506 static void shutdown(struct pci_dev *pdev)
1508 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1509 struct mlx5_priv *priv = &dev->priv;
1512 dev_info(&pdev->dev, "Shutdown was called\n");
1513 err = mlx5_try_fast_unload(dev);
1515 mlx5_unload_one(dev, priv, false);
1516 mlx5_pci_disable_device(dev);
1519 static const struct pci_device_id mlx5_core_pci_table[] = {
1520 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1521 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1522 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1523 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1524 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1525 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1526 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1527 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1528 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1529 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1530 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1531 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1532 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1533 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1537 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1539 void mlx5_disable_device(struct mlx5_core_dev *dev)
1541 mlx5_pci_err_detected(dev->pdev, 0);
1544 void mlx5_recover_device(struct mlx5_core_dev *dev)
1546 mlx5_pci_disable_device(dev);
1547 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1548 mlx5_pci_resume(dev->pdev);
1551 static struct pci_driver mlx5_core_driver = {
1552 .name = DRIVER_NAME,
1553 .id_table = mlx5_core_pci_table,
1555 .remove = remove_one,
1556 .shutdown = shutdown,
1557 .err_handler = &mlx5_err_handler,
1558 .sriov_configure = mlx5_core_sriov_configure,
1561 static void mlx5_core_verify_params(void)
1563 if (prof_sel >= ARRAY_SIZE(profile)) {
1564 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1566 ARRAY_SIZE(profile) - 1,
1568 prof_sel = MLX5_DEFAULT_PROF;
1572 static int __init init(void)
1576 mlx5_core_verify_params();
1577 mlx5_register_debugfs();
1579 err = pci_register_driver(&mlx5_core_driver);
1583 #ifdef CONFIG_MLX5_CORE_EN
1590 mlx5_unregister_debugfs();
1594 static void __exit cleanup(void)
1596 #ifdef CONFIG_MLX5_CORE_EN
1599 pci_unregister_driver(&mlx5_core_driver);
1600 mlx5_unregister_debugfs();
1604 module_exit(cleanup);