2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/mlx5/mlx5_ifc.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <net/devlink.h>
54 #include "mlx5_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
60 #include "fpga/core.h"
61 #include "accel/ipsec.h"
63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
64 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
65 MODULE_LICENSE("Dual BSD/GPL");
66 MODULE_VERSION(DRIVER_VERSION);
68 unsigned int mlx5_core_debug_mask;
69 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
70 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
72 #define MLX5_DEFAULT_PROF 2
73 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
74 module_param_named(prof_sel, prof_sel, uint, 0444);
75 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
78 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
79 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
82 static struct mlx5_profile profile[] = {
87 .mask = MLX5_PROF_MASK_QP_SIZE,
91 .mask = MLX5_PROF_MASK_QP_SIZE |
92 MLX5_PROF_MASK_MR_CACHE,
181 #define FW_INIT_TIMEOUT_MILI 2000
182 #define FW_INIT_WAIT_MS 2
183 #define FW_PRE_INIT_TIMEOUT_MILI 10000
185 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
187 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
190 while (fw_initializing(dev)) {
191 if (time_after(jiffies, end)) {
195 msleep(FW_INIT_WAIT_MS);
201 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
203 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
205 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
206 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
207 int remaining_size = driver_ver_sz;
210 if (!MLX5_CAP_GEN(dev, driver_version))
213 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
215 strncpy(string, "Linux", remaining_size);
217 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
218 strncat(string, ",", remaining_size);
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, DRIVER_NAME, remaining_size);
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, ",", remaining_size);
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, DRIVER_VERSION, remaining_size);
230 MLX5_SET(set_driver_version_in, in, opcode,
231 MLX5_CMD_OP_SET_DRIVER_VERSION);
233 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
236 static int set_dma_caps(struct pci_dev *pdev)
240 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
242 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
243 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
245 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
250 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
253 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
254 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
257 "Can't set consistent PCI DMA mask, aborting\n");
262 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
266 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
268 struct pci_dev *pdev = dev->pdev;
271 mutex_lock(&dev->pci_status_mutex);
272 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
273 err = pci_enable_device(pdev);
275 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
277 mutex_unlock(&dev->pci_status_mutex);
282 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
284 struct pci_dev *pdev = dev->pdev;
286 mutex_lock(&dev->pci_status_mutex);
287 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
288 pci_disable_device(pdev);
289 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
291 mutex_unlock(&dev->pci_status_mutex);
294 static int request_bar(struct pci_dev *pdev)
298 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
299 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
303 err = pci_request_regions(pdev, DRIVER_NAME);
305 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
310 static void release_bar(struct pci_dev *pdev)
312 pci_release_regions(pdev);
315 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
317 struct mlx5_priv *priv = &dev->priv;
318 struct mlx5_eq_table *table = &priv->eq_table;
319 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
323 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
324 MLX5_EQ_VEC_COMP_BASE;
325 nvec = min_t(int, nvec, num_eqs);
326 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
329 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
331 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
332 if (!priv->msix_arr || !priv->irq_info)
335 for (i = 0; i < nvec; i++)
336 priv->msix_arr[i].entry = i;
338 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
339 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
343 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
348 kfree(priv->irq_info);
349 kfree(priv->msix_arr);
353 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
355 struct mlx5_priv *priv = &dev->priv;
357 pci_disable_msix(dev->pdev);
358 kfree(priv->irq_info);
359 kfree(priv->msix_arr);
362 struct mlx5_reg_host_endianness {
367 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
370 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
371 MLX5_DEV_CAP_FLAG_DCT,
374 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
390 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
395 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
396 enum mlx5_cap_type cap_type,
397 enum mlx5_cap_mode cap_mode)
399 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
400 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
401 void *out, *hca_caps;
402 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
405 memset(in, 0, sizeof(in));
406 out = kzalloc(out_sz, GFP_KERNEL);
410 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
411 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
412 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
415 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
416 cap_type, cap_mode, err);
420 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
423 case HCA_CAP_OPMOD_GET_MAX:
424 memcpy(dev->caps.hca_max[cap_type], hca_caps,
425 MLX5_UN_SZ_BYTES(hca_cap_union));
427 case HCA_CAP_OPMOD_GET_CUR:
428 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
429 MLX5_UN_SZ_BYTES(hca_cap_union));
433 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
443 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
447 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
450 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
453 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
455 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
457 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
458 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
459 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
462 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
466 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
470 if (MLX5_CAP_GEN(dev, atomic)) {
471 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
480 supported_atomic_req_8B_endianness_mode_1);
482 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
485 set_ctx = kzalloc(set_sz, GFP_KERNEL);
489 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
491 /* Set requestor to host endianness */
492 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
493 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
495 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
501 static int handle_hca_cap(struct mlx5_core_dev *dev)
503 void *set_ctx = NULL;
504 struct mlx5_profile *prof = dev->profile;
506 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
509 set_ctx = kzalloc(set_sz, GFP_KERNEL);
513 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
517 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
519 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
520 MLX5_ST_SZ_BYTES(cmd_hca_cap));
522 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
523 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
525 /* we limit the size of the pkey table to 128 entries for now */
526 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
527 to_fw_pkey_sz(dev, 128));
529 /* Check log_max_qp from HCA caps to set in current profile */
530 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
532 profile[prof_sel].log_max_qp,
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
540 /* disable cmdif checksum */
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
543 /* Enable 4K UAR only when HCA supports it and page size is bigger
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
555 cache_line_size() == 128 ? 1 : 0);
557 err = set_caps(dev, set_ctx, set_sz,
558 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
565 static int set_hca_ctrl(struct mlx5_core_dev *dev)
567 struct mlx5_reg_host_endianness he_in;
568 struct mlx5_reg_host_endianness he_out;
571 if (!mlx5_core_is_pf(dev))
574 memset(&he_in, 0, sizeof(he_in));
575 he_in.he = MLX5_SET_HOST_ENDIANNESS;
576 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
577 &he_out, sizeof(he_out),
578 MLX5_REG_HOST_ENDIANNESS, 0, 1);
582 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
584 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
585 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
587 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
588 MLX5_SET(enable_hca_in, in, function_id, func_id);
589 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
592 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
594 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
595 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
597 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
598 MLX5_SET(disable_hca_in, in, function_id, func_id);
599 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
602 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
604 u32 timer_h, timer_h1, timer_l;
606 timer_h = ioread32be(&dev->iseg->internal_timer_h);
607 timer_l = ioread32be(&dev->iseg->internal_timer_l);
608 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
609 if (timer_h != timer_h1) /* wrap around */
610 timer_l = ioread32be(&dev->iseg->internal_timer_l);
612 return (u64)timer_l | (u64)timer_h1 << 32;
615 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
617 struct mlx5_priv *priv = &mdev->priv;
618 struct msix_entry *msix = priv->msix_arr;
619 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
621 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
622 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
626 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
627 priv->irq_info[i].mask);
629 if (IS_ENABLED(CONFIG_SMP) &&
630 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
631 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
636 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
638 struct mlx5_priv *priv = &mdev->priv;
639 struct msix_entry *msix = priv->msix_arr;
640 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
642 irq_set_affinity_hint(irq, NULL);
643 free_cpumask_var(priv->irq_info[i].mask);
646 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
651 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
652 err = mlx5_irq_set_affinity_hint(mdev, i);
660 for (i--; i >= 0; i--)
661 mlx5_irq_clear_affinity_hint(mdev, i);
666 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
670 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
671 mlx5_irq_clear_affinity_hint(mdev, i);
674 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
677 struct mlx5_eq_table *table = &dev->priv.eq_table;
678 struct mlx5_eq *eq, *n;
681 spin_lock(&table->lock);
682 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
683 if (eq->index == vector) {
690 spin_unlock(&table->lock);
694 EXPORT_SYMBOL(mlx5_vector2eqn);
696 struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
698 struct mlx5_eq_table *table = &dev->priv.eq_table;
701 spin_lock(&table->lock);
702 list_for_each_entry(eq, &table->comp_eqs_list, list)
703 if (eq->eqn == eqn) {
704 spin_unlock(&table->lock);
708 spin_unlock(&table->lock);
710 return ERR_PTR(-ENOENT);
713 static void free_comp_eqs(struct mlx5_core_dev *dev)
715 struct mlx5_eq_table *table = &dev->priv.eq_table;
716 struct mlx5_eq *eq, *n;
718 #ifdef CONFIG_RFS_ACCEL
720 free_irq_cpu_rmap(dev->rmap);
724 spin_lock(&table->lock);
725 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
727 spin_unlock(&table->lock);
728 if (mlx5_destroy_unmap_eq(dev, eq))
729 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
732 spin_lock(&table->lock);
734 spin_unlock(&table->lock);
737 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
739 struct mlx5_eq_table *table = &dev->priv.eq_table;
740 char name[MLX5_MAX_IRQ_NAME];
747 INIT_LIST_HEAD(&table->comp_eqs_list);
748 ncomp_vec = table->num_comp_vectors;
749 nent = MLX5_COMP_EQ_SIZE;
750 #ifdef CONFIG_RFS_ACCEL
751 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
755 for (i = 0; i < ncomp_vec; i++) {
756 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
762 #ifdef CONFIG_RFS_ACCEL
763 irq_cpu_rmap_add(dev->rmap,
764 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
766 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
767 err = mlx5_create_map_eq(dev, eq,
768 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
769 name, MLX5_EQ_TYPE_COMP);
774 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
776 spin_lock(&table->lock);
777 list_add_tail(&eq->list, &table->comp_eqs_list);
778 spin_unlock(&table->lock);
788 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
790 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
791 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
795 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
796 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
797 query_out, sizeof(query_out));
802 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
803 if (!status || syndrome == MLX5_DRIVER_SYND) {
804 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
805 err, status, syndrome);
809 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
814 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
816 if (sup_issi & (1 << 1)) {
817 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
818 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
820 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
821 MLX5_SET(set_issi_in, set_in, current_issi, 1);
822 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
823 set_out, sizeof(set_out));
825 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
833 } else if (sup_issi & (1 << 0) || !sup_issi) {
841 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
843 struct pci_dev *pdev = dev->pdev;
846 pci_set_drvdata(dev->pdev, dev);
847 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
848 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
850 mutex_init(&priv->pgdir_mutex);
851 INIT_LIST_HEAD(&priv->pgdir_list);
852 spin_lock_init(&priv->mkey_lock);
854 mutex_init(&priv->alloc_mutex);
856 priv->numa_node = dev_to_node(&dev->pdev->dev);
858 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
862 err = mlx5_pci_enable_device(dev);
864 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
868 err = request_bar(pdev);
870 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
874 pci_set_master(pdev);
876 err = set_dma_caps(pdev);
878 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
882 dev->iseg_base = pci_resource_start(dev->pdev, 0);
883 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
886 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
893 pci_clear_master(dev->pdev);
894 release_bar(dev->pdev);
896 mlx5_pci_disable_device(dev);
899 debugfs_remove(priv->dbg_root);
903 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
906 pci_clear_master(dev->pdev);
907 release_bar(dev->pdev);
908 mlx5_pci_disable_device(dev);
909 debugfs_remove(priv->dbg_root);
912 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
914 struct pci_dev *pdev = dev->pdev;
917 err = mlx5_query_board_id(dev);
919 dev_err(&pdev->dev, "query board id failed\n");
923 err = mlx5_eq_init(dev);
925 dev_err(&pdev->dev, "failed to initialize eq\n");
929 err = mlx5_init_cq_table(dev);
931 dev_err(&pdev->dev, "failed to initialize cq table\n");
935 mlx5_init_qp_table(dev);
937 mlx5_init_srq_table(dev);
939 mlx5_init_mkey_table(dev);
941 mlx5_init_reserved_gids(dev);
943 err = mlx5_init_rl_table(dev);
945 dev_err(&pdev->dev, "Failed to init rate limiting\n");
946 goto err_tables_cleanup;
949 #ifdef CONFIG_MLX5_CORE_EN
950 err = mlx5_eswitch_init(dev);
952 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
957 err = mlx5_sriov_init(dev);
959 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
960 goto err_eswitch_cleanup;
963 err = mlx5_fpga_init(dev);
965 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
966 goto err_sriov_cleanup;
972 mlx5_sriov_cleanup(dev);
974 #ifdef CONFIG_MLX5_CORE_EN
975 mlx5_eswitch_cleanup(dev->priv.eswitch);
979 mlx5_cleanup_rl_table(dev);
982 mlx5_cleanup_mkey_table(dev);
983 mlx5_cleanup_srq_table(dev);
984 mlx5_cleanup_qp_table(dev);
985 mlx5_cleanup_cq_table(dev);
988 mlx5_eq_cleanup(dev);
994 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
996 mlx5_fpga_cleanup(dev);
997 mlx5_sriov_cleanup(dev);
998 #ifdef CONFIG_MLX5_CORE_EN
999 mlx5_eswitch_cleanup(dev->priv.eswitch);
1001 mlx5_cleanup_rl_table(dev);
1002 mlx5_cleanup_reserved_gids(dev);
1003 mlx5_cleanup_mkey_table(dev);
1004 mlx5_cleanup_srq_table(dev);
1005 mlx5_cleanup_qp_table(dev);
1006 mlx5_cleanup_cq_table(dev);
1007 mlx5_eq_cleanup(dev);
1010 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1013 struct pci_dev *pdev = dev->pdev;
1016 mutex_lock(&dev->intf_state_mutex);
1017 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1018 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1023 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1024 fw_rev_min(dev), fw_rev_sub(dev));
1026 /* on load removing any previous indication of internal error, device is
1029 dev->state = MLX5_DEVICE_STATE_UP;
1031 /* wait for firmware to accept initialization segments configurations
1033 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1035 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1036 FW_PRE_INIT_TIMEOUT_MILI);
1040 err = mlx5_cmd_init(dev);
1042 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1046 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1048 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1049 FW_INIT_TIMEOUT_MILI);
1050 goto err_cmd_cleanup;
1053 err = mlx5_core_enable_hca(dev, 0);
1055 dev_err(&pdev->dev, "enable hca failed\n");
1056 goto err_cmd_cleanup;
1059 err = mlx5_core_set_issi(dev);
1061 dev_err(&pdev->dev, "failed to set issi\n");
1062 goto err_disable_hca;
1065 err = mlx5_satisfy_startup_pages(dev, 1);
1067 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1068 goto err_disable_hca;
1071 err = set_hca_ctrl(dev);
1073 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1074 goto reclaim_boot_pages;
1077 err = handle_hca_cap(dev);
1079 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1080 goto reclaim_boot_pages;
1083 err = handle_hca_cap_atomic(dev);
1085 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1086 goto reclaim_boot_pages;
1089 err = mlx5_satisfy_startup_pages(dev, 0);
1091 dev_err(&pdev->dev, "failed to allocate init pages\n");
1092 goto reclaim_boot_pages;
1095 err = mlx5_pagealloc_start(dev);
1097 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1098 goto reclaim_boot_pages;
1101 err = mlx5_cmd_init_hca(dev);
1103 dev_err(&pdev->dev, "init hca failed\n");
1104 goto err_pagealloc_stop;
1107 mlx5_set_driver_version(dev);
1109 mlx5_start_health_poll(dev);
1111 err = mlx5_query_hca_caps(dev);
1113 dev_err(&pdev->dev, "query hca failed\n");
1117 if (boot && mlx5_init_once(dev, priv)) {
1118 dev_err(&pdev->dev, "sw objs init failed\n");
1122 err = mlx5_enable_msix(dev);
1124 dev_err(&pdev->dev, "enable msix failed\n");
1125 goto err_cleanup_once;
1128 dev->priv.uar = mlx5_get_uars_page(dev);
1129 if (!dev->priv.uar) {
1130 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1131 goto err_disable_msix;
1134 err = mlx5_start_eqs(dev);
1136 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1140 err = alloc_comp_eqs(dev);
1142 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1146 err = mlx5_irq_set_affinity_hints(dev);
1148 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1149 goto err_affinity_hints;
1152 err = mlx5_init_fs(dev);
1154 dev_err(&pdev->dev, "Failed to init flow steering\n");
1158 #ifdef CONFIG_MLX5_CORE_EN
1159 mlx5_eswitch_attach(dev->priv.eswitch);
1162 err = mlx5_sriov_attach(dev);
1164 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1168 err = mlx5_fpga_device_start(dev);
1170 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1171 goto err_fpga_start;
1173 err = mlx5_accel_ipsec_init(dev);
1175 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1176 goto err_ipsec_start;
1179 if (mlx5_device_registered(dev)) {
1180 mlx5_attach_device(dev);
1182 err = mlx5_register_device(dev);
1184 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1189 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1191 mutex_unlock(&dev->intf_state_mutex);
1196 mlx5_accel_ipsec_cleanup(dev);
1198 mlx5_fpga_device_stop(dev);
1201 mlx5_sriov_detach(dev);
1204 #ifdef CONFIG_MLX5_CORE_EN
1205 mlx5_eswitch_detach(dev->priv.eswitch);
1207 mlx5_cleanup_fs(dev);
1210 mlx5_irq_clear_affinity_hints(dev);
1219 mlx5_put_uars_page(dev, priv->uar);
1222 mlx5_disable_msix(dev);
1226 mlx5_cleanup_once(dev);
1229 mlx5_stop_health_poll(dev);
1230 if (mlx5_cmd_teardown_hca(dev)) {
1231 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1236 mlx5_pagealloc_stop(dev);
1239 mlx5_reclaim_startup_pages(dev);
1242 mlx5_core_disable_hca(dev, 0);
1245 mlx5_cmd_cleanup(dev);
1248 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1249 mutex_unlock(&dev->intf_state_mutex);
1254 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1260 mlx5_drain_health_recovery(dev);
1262 mutex_lock(&dev->intf_state_mutex);
1263 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1264 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1267 mlx5_cleanup_once(dev);
1271 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1273 if (mlx5_device_registered(dev))
1274 mlx5_detach_device(dev);
1276 mlx5_accel_ipsec_cleanup(dev);
1277 mlx5_fpga_device_stop(dev);
1279 mlx5_sriov_detach(dev);
1280 #ifdef CONFIG_MLX5_CORE_EN
1281 mlx5_eswitch_detach(dev->priv.eswitch);
1283 mlx5_cleanup_fs(dev);
1284 mlx5_irq_clear_affinity_hints(dev);
1287 mlx5_put_uars_page(dev, priv->uar);
1288 mlx5_disable_msix(dev);
1290 mlx5_cleanup_once(dev);
1291 mlx5_stop_health_poll(dev);
1292 err = mlx5_cmd_teardown_hca(dev);
1294 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1297 mlx5_pagealloc_stop(dev);
1298 mlx5_reclaim_startup_pages(dev);
1299 mlx5_core_disable_hca(dev, 0);
1300 mlx5_cmd_cleanup(dev);
1303 mutex_unlock(&dev->intf_state_mutex);
1307 struct mlx5_core_event_handler {
1308 void (*event)(struct mlx5_core_dev *dev,
1309 enum mlx5_dev_event event,
1313 static const struct devlink_ops mlx5_devlink_ops = {
1314 #ifdef CONFIG_MLX5_CORE_EN
1315 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1316 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1317 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1318 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1319 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1320 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1324 #define MLX5_IB_MOD "mlx5_ib"
1325 static int init_one(struct pci_dev *pdev,
1326 const struct pci_device_id *id)
1328 struct mlx5_core_dev *dev;
1329 struct devlink *devlink;
1330 struct mlx5_priv *priv;
1333 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1335 dev_err(&pdev->dev, "kzalloc failed\n");
1339 dev = devlink_priv(devlink);
1341 priv->pci_dev_data = id->driver_data;
1343 pci_set_drvdata(pdev, dev);
1346 dev->event = mlx5_core_event;
1347 dev->profile = &profile[prof_sel];
1349 INIT_LIST_HEAD(&priv->ctx_list);
1350 spin_lock_init(&priv->ctx_lock);
1351 mutex_init(&dev->pci_status_mutex);
1352 mutex_init(&dev->intf_state_mutex);
1354 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1355 err = init_srcu_struct(&priv->pfault_srcu);
1357 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1362 mutex_init(&priv->bfregs.reg_head.lock);
1363 mutex_init(&priv->bfregs.wc_head.lock);
1364 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1365 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1367 err = mlx5_pci_init(dev, priv);
1369 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1373 err = mlx5_health_init(dev);
1375 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1379 mlx5_pagealloc_init(dev);
1381 err = mlx5_load_one(dev, priv, true);
1383 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1387 request_module_nowait(MLX5_IB_MOD);
1389 err = devlink_register(devlink, &pdev->dev);
1393 pci_save_state(pdev);
1397 mlx5_unload_one(dev, priv, true);
1399 mlx5_pagealloc_cleanup(dev);
1400 mlx5_health_cleanup(dev);
1402 mlx5_pci_close(dev, priv);
1404 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1405 cleanup_srcu_struct(&priv->pfault_srcu);
1408 pci_set_drvdata(pdev, NULL);
1409 devlink_free(devlink);
1414 static void remove_one(struct pci_dev *pdev)
1416 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1417 struct devlink *devlink = priv_to_devlink(dev);
1418 struct mlx5_priv *priv = &dev->priv;
1420 devlink_unregister(devlink);
1421 mlx5_unregister_device(dev);
1423 if (mlx5_unload_one(dev, priv, true)) {
1424 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1425 mlx5_health_cleanup(dev);
1429 mlx5_pagealloc_cleanup(dev);
1430 mlx5_health_cleanup(dev);
1431 mlx5_pci_close(dev, priv);
1432 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1433 cleanup_srcu_struct(&priv->pfault_srcu);
1435 pci_set_drvdata(pdev, NULL);
1436 devlink_free(devlink);
1439 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1440 pci_channel_state_t state)
1442 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1443 struct mlx5_priv *priv = &dev->priv;
1445 dev_info(&pdev->dev, "%s was called\n", __func__);
1447 mlx5_enter_error_state(dev, false);
1448 mlx5_unload_one(dev, priv, false);
1449 /* In case of kernel call drain the health wq */
1451 mlx5_drain_health_wq(dev);
1452 mlx5_pci_disable_device(dev);
1455 return state == pci_channel_io_perm_failure ?
1456 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1459 /* wait for the device to show vital signs by waiting
1460 * for the health counter to start counting.
1462 static int wait_vital(struct pci_dev *pdev)
1464 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1465 struct mlx5_core_health *health = &dev->priv.health;
1466 const int niter = 100;
1471 for (i = 0; i < niter; i++) {
1472 count = ioread32be(health->health_counter);
1473 if (count && count != 0xffffffff) {
1474 if (last_count && last_count != count) {
1475 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1486 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1488 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1491 dev_info(&pdev->dev, "%s was called\n", __func__);
1493 err = mlx5_pci_enable_device(dev);
1495 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1497 return PCI_ERS_RESULT_DISCONNECT;
1500 pci_set_master(pdev);
1501 pci_restore_state(pdev);
1502 pci_save_state(pdev);
1504 if (wait_vital(pdev)) {
1505 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1506 return PCI_ERS_RESULT_DISCONNECT;
1509 return PCI_ERS_RESULT_RECOVERED;
1512 static void mlx5_pci_resume(struct pci_dev *pdev)
1514 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1515 struct mlx5_priv *priv = &dev->priv;
1518 dev_info(&pdev->dev, "%s was called\n", __func__);
1520 err = mlx5_load_one(dev, priv, false);
1522 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1525 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1528 static const struct pci_error_handlers mlx5_err_handler = {
1529 .error_detected = mlx5_pci_err_detected,
1530 .slot_reset = mlx5_pci_slot_reset,
1531 .resume = mlx5_pci_resume
1534 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1538 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1539 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1543 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1544 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1548 ret = mlx5_cmd_force_teardown_hca(dev);
1550 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1554 mlx5_enter_error_state(dev, true);
1559 static void shutdown(struct pci_dev *pdev)
1561 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1562 struct mlx5_priv *priv = &dev->priv;
1565 dev_info(&pdev->dev, "Shutdown was called\n");
1566 err = mlx5_try_fast_unload(dev);
1568 mlx5_unload_one(dev, priv, false);
1569 mlx5_pci_disable_device(dev);
1572 static const struct pci_device_id mlx5_core_pci_table[] = {
1573 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1574 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1575 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1576 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1577 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1578 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1579 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1580 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1581 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1582 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1583 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1584 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1585 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1586 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1590 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1592 void mlx5_disable_device(struct mlx5_core_dev *dev)
1594 mlx5_pci_err_detected(dev->pdev, 0);
1597 void mlx5_recover_device(struct mlx5_core_dev *dev)
1599 mlx5_pci_disable_device(dev);
1600 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1601 mlx5_pci_resume(dev->pdev);
1604 static struct pci_driver mlx5_core_driver = {
1605 .name = DRIVER_NAME,
1606 .id_table = mlx5_core_pci_table,
1608 .remove = remove_one,
1609 .shutdown = shutdown,
1610 .err_handler = &mlx5_err_handler,
1611 .sriov_configure = mlx5_core_sriov_configure,
1614 static void mlx5_core_verify_params(void)
1616 if (prof_sel >= ARRAY_SIZE(profile)) {
1617 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1619 ARRAY_SIZE(profile) - 1,
1621 prof_sel = MLX5_DEFAULT_PROF;
1625 static int __init init(void)
1629 mlx5_core_verify_params();
1630 mlx5_register_debugfs();
1632 err = pci_register_driver(&mlx5_core_driver);
1636 #ifdef CONFIG_MLX5_CORE_EN
1643 mlx5_unregister_debugfs();
1647 static void __exit cleanup(void)
1649 #ifdef CONFIG_MLX5_CORE_EN
1652 pci_unregister_driver(&mlx5_core_driver);
1653 mlx5_unregister_debugfs();
1657 module_exit(cleanup);