2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
64 #include "fpga/core.h"
65 #include "en_accel/ipsec_offload.h"
66 #include "lib/clock.h"
67 #include "lib/vxlan.h"
68 #include "lib/geneve.h"
69 #include "lib/devcom.h"
70 #include "lib/pci_vsc.h"
71 #include "diag/fw_tracer.h"
73 #include "lib/hv_vhca.h"
74 #include "diag/rsc_dump.h"
75 #include "sf/vhca_event.h"
76 #include "sf/dev/dev.h"
80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
82 MODULE_LICENSE("Dual BSD/GPL");
84 unsigned int mlx5_core_debug_mask;
85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
88 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
89 module_param_named(prof_sel, prof_sel, uint, 0444);
90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
92 static u32 sw_owner_id[4];
95 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
99 #define LOG_MAX_SUPPORTED_QPS 0xff
101 static struct mlx5_profile profile[] = {
106 .mask = MLX5_PROF_MASK_QP_SIZE,
110 .mask = MLX5_PROF_MASK_QP_SIZE |
111 MLX5_PROF_MASK_MR_CACHE,
112 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
180 static int fw_initializing(struct mlx5_core_dev *dev)
182 return ioread32be(&dev->iseg->initializing) >> 31;
185 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
188 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
189 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
192 while (fw_initializing(dev)) {
193 if (time_after(jiffies, end)) {
197 if (warn_time_mili && time_after(jiffies, warn)) {
198 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
199 jiffies_to_msecs(end - warn) / 1000);
200 warn = jiffies + msecs_to_jiffies(warn_time_mili);
202 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
213 int remaining_size = driver_ver_sz;
216 if (!MLX5_CAP_GEN(dev, driver_version))
219 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
221 strncpy(string, "Linux", remaining_size);
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, ",", remaining_size);
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, KBUILD_MODNAME, remaining_size);
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, ",", remaining_size);
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
235 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
236 LINUX_VERSION_SUBLEVEL);
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
245 static int set_dma_caps(struct pci_dev *pdev)
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
265 struct pci_dev *pdev = dev->pdev;
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
274 mutex_unlock(&dev->pci_status_mutex);
279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
281 struct pci_dev *pdev = dev->pdev;
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
288 mutex_unlock(&dev->pci_status_mutex);
291 static int request_bar(struct pci_dev *pdev)
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
307 static void release_bar(struct pci_dev *pdev)
309 pci_release_regions(pdev);
312 struct mlx5_reg_host_endianness {
317 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
321 MLX5_DEV_CAP_FLAG_DCT,
324 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
340 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
345 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
346 enum mlx5_cap_type cap_type,
347 enum mlx5_cap_mode cap_mode)
349 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
350 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
351 void *out, *hca_caps;
352 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
355 memset(in, 0, sizeof(in));
356 out = kzalloc(out_sz, GFP_KERNEL);
360 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
361 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
362 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
365 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
366 cap_type, cap_mode, err);
370 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
373 case HCA_CAP_OPMOD_GET_MAX:
374 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
375 MLX5_UN_SZ_BYTES(hca_cap_union));
377 case HCA_CAP_OPMOD_GET_CUR:
378 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
379 MLX5_UN_SZ_BYTES(hca_cap_union));
383 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
393 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
397 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
400 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
403 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
405 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
406 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
407 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
410 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
416 if (!MLX5_CAP_GEN(dev, atomic))
419 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
425 supported_atomic_req_8B_endianness_mode_1);
427 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
430 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
432 /* Set requestor to host endianness */
433 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
434 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
436 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
439 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
445 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
446 !MLX5_CAP_GEN(dev, pg))
449 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
453 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
454 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
455 MLX5_ST_SZ_BYTES(odp_cap));
457 #define ODP_CAP_SET_MAX(dev, field) \
459 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
462 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
466 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
467 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
474 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
475 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
484 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
487 static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev)
489 struct devlink *devlink = priv_to_devlink(dev);
490 union devlink_param_value val;
493 err = devlink_param_driverinit_value_get(devlink,
494 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
498 mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err);
502 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
504 struct mlx5_profile *prof = &dev->profile;
509 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
513 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
515 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
516 MLX5_ST_SZ_BYTES(cmd_hca_cap));
518 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
519 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
521 /* we limit the size of the pkey table to 128 entries for now */
522 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
523 to_fw_pkey_sz(dev, 128));
525 /* Check log_max_qp from HCA caps to set in current profile */
526 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
527 prof->log_max_qp = min_t(u8, 17, MLX5_CAP_GEN_MAX(dev, log_max_qp));
528 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
529 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
531 MLX5_CAP_GEN_MAX(dev, log_max_qp));
532 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
534 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
535 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 /* disable cmdif checksum */
539 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
541 /* Enable 4K UAR only when HCA supports it and page size is bigger
544 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
545 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
547 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
549 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
550 MLX5_SET(cmd_hca_cap,
553 cache_line_size() >= 128 ? 1 : 0);
555 if (MLX5_CAP_GEN_MAX(dev, dct))
556 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
558 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
559 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
561 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
562 MLX5_SET(cmd_hca_cap,
565 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
567 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
568 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
570 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
571 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
573 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
575 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
576 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
577 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
579 if (MLX5_CAP_GEN(dev, roce_rw_supported))
580 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
582 max_uc_list = max_uc_list_get_devlink_param(dev);
584 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list,
587 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
590 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
592 * In case RoCE cap is writable in FW and user/devlink requested to change the
593 * cap, we are yet to query the final state of the above cap.
594 * Hence, the need for this function.
598 * 1) RoCE cap is read only in FW and already disabled
600 * 2) RoCE cap is writable in FW and user/devlink requested it off.
602 * In any other case, return False.
604 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
606 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
607 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
610 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
615 if (is_roce_fw_disabled(dev))
618 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
622 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
623 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
626 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
627 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
628 MLX5_ST_SZ_BYTES(roce_cap));
629 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
631 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
635 static int set_hca_cap(struct mlx5_core_dev *dev)
637 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
641 set_ctx = kzalloc(set_sz, GFP_KERNEL);
645 err = handle_hca_cap(dev, set_ctx);
647 mlx5_core_err(dev, "handle_hca_cap failed\n");
651 memset(set_ctx, 0, set_sz);
652 err = handle_hca_cap_atomic(dev, set_ctx);
654 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
658 memset(set_ctx, 0, set_sz);
659 err = handle_hca_cap_odp(dev, set_ctx);
661 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
665 memset(set_ctx, 0, set_sz);
666 err = handle_hca_cap_roce(dev, set_ctx);
668 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
677 static int set_hca_ctrl(struct mlx5_core_dev *dev)
679 struct mlx5_reg_host_endianness he_in;
680 struct mlx5_reg_host_endianness he_out;
683 if (!mlx5_core_is_pf(dev))
686 memset(&he_in, 0, sizeof(he_in));
687 he_in.he = MLX5_SET_HOST_ENDIANNESS;
688 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
689 &he_out, sizeof(he_out),
690 MLX5_REG_HOST_ENDIANNESS, 0, 1);
694 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
698 /* Disable local_lb by default */
699 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
700 ret = mlx5_nic_vport_update_local_lb(dev, false);
705 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
707 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
709 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
710 MLX5_SET(enable_hca_in, in, function_id, func_id);
711 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
712 dev->caps.embedded_cpu);
713 return mlx5_cmd_exec_in(dev, enable_hca, in);
716 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
718 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
720 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
721 MLX5_SET(disable_hca_in, in, function_id, func_id);
722 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
723 dev->caps.embedded_cpu);
724 return mlx5_cmd_exec_in(dev, disable_hca, in);
727 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
729 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
730 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
734 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
735 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
737 u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome);
738 u8 status = MLX5_GET(query_issi_out, query_out, status);
740 if (!status || syndrome == MLX5_DRIVER_SYND) {
741 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
742 err, status, syndrome);
746 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
751 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
753 if (sup_issi & (1 << 1)) {
754 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
756 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
757 MLX5_SET(set_issi_in, set_in, current_issi, 1);
758 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
760 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
768 } else if (sup_issi & (1 << 0) || !sup_issi) {
775 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
776 const struct pci_device_id *id)
780 mutex_init(&dev->pci_status_mutex);
781 pci_set_drvdata(dev->pdev, dev);
783 dev->bar_addr = pci_resource_start(pdev, 0);
785 err = mlx5_pci_enable_device(dev);
787 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
791 err = request_bar(pdev);
793 mlx5_core_err(dev, "error requesting BARs, aborting\n");
797 pci_set_master(pdev);
799 err = set_dma_caps(pdev);
801 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
805 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
806 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
807 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
808 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
810 dev->iseg_base = dev->bar_addr;
811 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
814 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
818 mlx5_pci_vsc_init(dev);
819 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
823 pci_clear_master(dev->pdev);
824 release_bar(dev->pdev);
826 mlx5_pci_disable_device(dev);
830 static void mlx5_pci_close(struct mlx5_core_dev *dev)
832 /* health work might still be active, and it needs pci bar in
833 * order to know the NIC state. Therefore, drain the health WQ
834 * before removing the pci bars
836 mlx5_drain_health_wq(dev);
838 pci_clear_master(dev->pdev);
839 release_bar(dev->pdev);
840 mlx5_pci_disable_device(dev);
843 static int mlx5_init_once(struct mlx5_core_dev *dev)
847 dev->priv.devcom = mlx5_devcom_register_device(dev);
848 if (IS_ERR(dev->priv.devcom))
849 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
852 err = mlx5_query_board_id(dev);
854 mlx5_core_err(dev, "query board id failed\n");
858 err = mlx5_irq_table_init(dev);
860 mlx5_core_err(dev, "failed to initialize irq table\n");
864 err = mlx5_eq_table_init(dev);
866 mlx5_core_err(dev, "failed to initialize eq\n");
867 goto err_irq_cleanup;
870 err = mlx5_events_init(dev);
872 mlx5_core_err(dev, "failed to initialize events\n");
876 err = mlx5_fw_reset_init(dev);
878 mlx5_core_err(dev, "failed to initialize fw reset events\n");
879 goto err_events_cleanup;
882 mlx5_cq_debugfs_init(dev);
884 mlx5_init_reserved_gids(dev);
886 mlx5_init_clock(dev);
888 dev->vxlan = mlx5_vxlan_create(dev);
889 dev->geneve = mlx5_geneve_create(dev);
891 err = mlx5_init_rl_table(dev);
893 mlx5_core_err(dev, "Failed to init rate limiting\n");
894 goto err_tables_cleanup;
897 err = mlx5_mpfs_init(dev);
899 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
903 err = mlx5_sriov_init(dev);
905 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
906 goto err_mpfs_cleanup;
909 err = mlx5_eswitch_init(dev);
911 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
912 goto err_sriov_cleanup;
915 err = mlx5_fpga_init(dev);
917 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
918 goto err_eswitch_cleanup;
921 err = mlx5_vhca_event_init(dev);
923 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
924 goto err_fpga_cleanup;
927 err = mlx5_sf_hw_table_init(dev);
929 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
930 goto err_sf_hw_table_cleanup;
933 err = mlx5_sf_table_init(dev);
935 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
936 goto err_sf_table_cleanup;
939 dev->dm = mlx5_dm_create(dev);
941 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
943 dev->tracer = mlx5_fw_tracer_create(dev);
944 dev->hv_vhca = mlx5_hv_vhca_create(dev);
945 dev->rsc_dump = mlx5_rsc_dump_create(dev);
949 err_sf_table_cleanup:
950 mlx5_sf_hw_table_cleanup(dev);
951 err_sf_hw_table_cleanup:
952 mlx5_vhca_event_cleanup(dev);
954 mlx5_fpga_cleanup(dev);
956 mlx5_eswitch_cleanup(dev->priv.eswitch);
958 mlx5_sriov_cleanup(dev);
960 mlx5_mpfs_cleanup(dev);
962 mlx5_cleanup_rl_table(dev);
964 mlx5_geneve_destroy(dev->geneve);
965 mlx5_vxlan_destroy(dev->vxlan);
966 mlx5_cq_debugfs_cleanup(dev);
967 mlx5_fw_reset_cleanup(dev);
969 mlx5_events_cleanup(dev);
971 mlx5_eq_table_cleanup(dev);
973 mlx5_irq_table_cleanup(dev);
975 mlx5_devcom_unregister_device(dev->priv.devcom);
980 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
982 mlx5_rsc_dump_destroy(dev);
983 mlx5_hv_vhca_destroy(dev->hv_vhca);
984 mlx5_fw_tracer_destroy(dev->tracer);
985 mlx5_dm_cleanup(dev);
986 mlx5_sf_table_cleanup(dev);
987 mlx5_sf_hw_table_cleanup(dev);
988 mlx5_vhca_event_cleanup(dev);
989 mlx5_fpga_cleanup(dev);
990 mlx5_eswitch_cleanup(dev->priv.eswitch);
991 mlx5_sriov_cleanup(dev);
992 mlx5_mpfs_cleanup(dev);
993 mlx5_cleanup_rl_table(dev);
994 mlx5_geneve_destroy(dev->geneve);
995 mlx5_vxlan_destroy(dev->vxlan);
996 mlx5_cleanup_clock(dev);
997 mlx5_cleanup_reserved_gids(dev);
998 mlx5_cq_debugfs_cleanup(dev);
999 mlx5_fw_reset_cleanup(dev);
1000 mlx5_events_cleanup(dev);
1001 mlx5_eq_table_cleanup(dev);
1002 mlx5_irq_table_cleanup(dev);
1003 mlx5_devcom_unregister_device(dev->priv.devcom);
1006 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
1010 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1011 fw_rev_min(dev), fw_rev_sub(dev));
1013 /* Only PFs hold the relevant PCIe information for this query */
1014 if (mlx5_core_is_pf(dev))
1015 pcie_print_link_status(dev->pdev);
1017 mlx5_tout_set_def_val(dev);
1019 /* wait for firmware to accept initialization segments configurations
1021 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1022 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1024 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1025 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1029 err = mlx5_cmd_init(dev);
1031 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1035 mlx5_tout_query_iseg(dev);
1037 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1039 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1040 mlx5_tout_ms(dev, FW_INIT));
1041 goto err_cmd_cleanup;
1044 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1046 err = mlx5_core_enable_hca(dev, 0);
1048 mlx5_core_err(dev, "enable hca failed\n");
1049 goto err_cmd_cleanup;
1052 err = mlx5_core_set_issi(dev);
1054 mlx5_core_err(dev, "failed to set issi\n");
1055 goto err_disable_hca;
1058 err = mlx5_satisfy_startup_pages(dev, 1);
1060 mlx5_core_err(dev, "failed to allocate boot pages\n");
1061 goto err_disable_hca;
1064 err = mlx5_tout_query_dtor(dev);
1066 mlx5_core_err(dev, "failed to read dtor\n");
1067 goto reclaim_boot_pages;
1070 err = set_hca_ctrl(dev);
1072 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1073 goto reclaim_boot_pages;
1076 err = set_hca_cap(dev);
1078 mlx5_core_err(dev, "set_hca_cap failed\n");
1079 goto reclaim_boot_pages;
1082 err = mlx5_satisfy_startup_pages(dev, 0);
1084 mlx5_core_err(dev, "failed to allocate init pages\n");
1085 goto reclaim_boot_pages;
1088 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1090 mlx5_core_err(dev, "init hca failed\n");
1091 goto reclaim_boot_pages;
1094 mlx5_set_driver_version(dev);
1096 err = mlx5_query_hca_caps(dev);
1098 mlx5_core_err(dev, "query hca failed\n");
1099 goto reclaim_boot_pages;
1102 mlx5_start_health_poll(dev);
1107 mlx5_reclaim_startup_pages(dev);
1109 mlx5_core_disable_hca(dev, 0);
1111 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1112 mlx5_cmd_cleanup(dev);
1117 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1121 mlx5_stop_health_poll(dev, boot);
1122 err = mlx5_cmd_teardown_hca(dev);
1124 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1127 mlx5_reclaim_startup_pages(dev);
1128 mlx5_core_disable_hca(dev, 0);
1129 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1130 mlx5_cmd_cleanup(dev);
1135 static int mlx5_load(struct mlx5_core_dev *dev)
1139 dev->priv.uar = mlx5_get_uars_page(dev);
1140 if (IS_ERR(dev->priv.uar)) {
1141 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1142 err = PTR_ERR(dev->priv.uar);
1146 mlx5_events_start(dev);
1147 mlx5_pagealloc_start(dev);
1149 err = mlx5_irq_table_create(dev);
1151 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1155 err = mlx5_eq_table_create(dev);
1157 mlx5_core_err(dev, "Failed to create EQs\n");
1161 err = mlx5_fw_tracer_init(dev->tracer);
1163 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1164 mlx5_fw_tracer_destroy(dev->tracer);
1168 mlx5_fw_reset_events_start(dev);
1169 mlx5_hv_vhca_init(dev->hv_vhca);
1171 err = mlx5_rsc_dump_init(dev);
1173 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1174 mlx5_rsc_dump_destroy(dev);
1175 dev->rsc_dump = NULL;
1178 err = mlx5_fpga_device_start(dev);
1180 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1181 goto err_fpga_start;
1184 err = mlx5_init_fs(dev);
1186 mlx5_core_err(dev, "Failed to init flow steering\n");
1190 err = mlx5_core_set_hca_defaults(dev);
1192 mlx5_core_err(dev, "Failed to set hca defaults\n");
1196 mlx5_vhca_event_start(dev);
1198 err = mlx5_sf_hw_table_create(dev);
1200 mlx5_core_err(dev, "sf table create failed %d\n", err);
1204 err = mlx5_ec_init(dev);
1206 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1210 mlx5_lag_add_mdev(dev);
1211 err = mlx5_sriov_attach(dev);
1213 mlx5_core_err(dev, "sriov init failed %d\n", err);
1217 mlx5_sf_dev_table_create(dev);
1222 mlx5_lag_remove_mdev(dev);
1223 mlx5_ec_cleanup(dev);
1225 mlx5_sf_hw_table_destroy(dev);
1227 mlx5_vhca_event_stop(dev);
1229 mlx5_cleanup_fs(dev);
1231 mlx5_fpga_device_stop(dev);
1233 mlx5_rsc_dump_cleanup(dev);
1234 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1235 mlx5_fw_reset_events_stop(dev);
1236 mlx5_fw_tracer_cleanup(dev->tracer);
1237 mlx5_eq_table_destroy(dev);
1239 mlx5_irq_table_destroy(dev);
1241 mlx5_pagealloc_stop(dev);
1242 mlx5_events_stop(dev);
1243 mlx5_put_uars_page(dev, dev->priv.uar);
1247 static void mlx5_unload(struct mlx5_core_dev *dev)
1249 mlx5_sf_dev_table_destroy(dev);
1250 mlx5_sriov_detach(dev);
1251 mlx5_lag_remove_mdev(dev);
1252 mlx5_ec_cleanup(dev);
1253 mlx5_sf_hw_table_destroy(dev);
1254 mlx5_vhca_event_stop(dev);
1255 mlx5_cleanup_fs(dev);
1256 mlx5_fpga_device_stop(dev);
1257 mlx5_rsc_dump_cleanup(dev);
1258 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1259 mlx5_fw_reset_events_stop(dev);
1260 mlx5_fw_tracer_cleanup(dev->tracer);
1261 mlx5_eq_table_destroy(dev);
1262 mlx5_irq_table_destroy(dev);
1263 mlx5_pagealloc_stop(dev);
1264 mlx5_events_stop(dev);
1265 mlx5_put_uars_page(dev, dev->priv.uar);
1268 int mlx5_init_one(struct mlx5_core_dev *dev)
1272 mutex_lock(&dev->intf_state_mutex);
1273 dev->state = MLX5_DEVICE_STATE_UP;
1275 err = mlx5_function_setup(dev, true);
1279 err = mlx5_init_once(dev);
1281 mlx5_core_err(dev, "sw objs init failed\n");
1282 goto function_teardown;
1285 err = mlx5_load(dev);
1289 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1291 err = mlx5_devlink_register(priv_to_devlink(dev));
1293 goto err_devlink_reg;
1295 err = mlx5_register_device(dev);
1299 mutex_unlock(&dev->intf_state_mutex);
1303 mlx5_devlink_unregister(priv_to_devlink(dev));
1305 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1308 mlx5_cleanup_once(dev);
1310 mlx5_function_teardown(dev, true);
1312 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1313 mutex_unlock(&dev->intf_state_mutex);
1317 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1319 mutex_lock(&dev->intf_state_mutex);
1321 mlx5_unregister_device(dev);
1322 mlx5_devlink_unregister(priv_to_devlink(dev));
1324 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1325 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1327 mlx5_cleanup_once(dev);
1331 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1333 mlx5_cleanup_once(dev);
1334 mlx5_function_teardown(dev, true);
1336 mutex_unlock(&dev->intf_state_mutex);
1339 int mlx5_load_one(struct mlx5_core_dev *dev)
1343 mutex_lock(&dev->intf_state_mutex);
1344 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1345 mlx5_core_warn(dev, "interface is up, NOP\n");
1348 /* remove any previous indication of internal error */
1349 dev->state = MLX5_DEVICE_STATE_UP;
1351 err = mlx5_function_setup(dev, false);
1355 err = mlx5_load(dev);
1359 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1361 err = mlx5_attach_device(dev);
1365 mutex_unlock(&dev->intf_state_mutex);
1369 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1372 mlx5_function_teardown(dev, false);
1374 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1376 mutex_unlock(&dev->intf_state_mutex);
1380 void mlx5_unload_one(struct mlx5_core_dev *dev)
1382 mutex_lock(&dev->intf_state_mutex);
1384 mlx5_detach_device(dev);
1386 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1387 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1392 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1394 mlx5_function_teardown(dev, false);
1396 mutex_unlock(&dev->intf_state_mutex);
1399 static const int types[] = {
1402 MLX5_CAP_ETHERNET_OFFLOADS,
1403 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1407 MLX5_CAP_IPOIB_OFFLOADS,
1408 MLX5_CAP_FLOW_TABLE,
1409 MLX5_CAP_ESWITCH_FLOW_TABLE,
1411 MLX5_CAP_VECTOR_CALC,
1417 MLX5_CAP_VDPA_EMULATION,
1419 MLX5_CAP_PORT_SELECTION,
1420 MLX5_CAP_DEV_SHAMPO,
1423 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1428 for (i = 0; i < ARRAY_SIZE(types); i++) {
1430 kfree(dev->caps.hca[type]);
1434 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1436 struct mlx5_hca_cap *cap;
1440 for (i = 0; i < ARRAY_SIZE(types); i++) {
1441 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1445 dev->caps.hca[type] = cap;
1451 mlx5_hca_caps_free(dev);
1455 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1457 struct mlx5_priv *priv = &dev->priv;
1460 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1461 INIT_LIST_HEAD(&priv->ctx_list);
1462 spin_lock_init(&priv->ctx_lock);
1463 mutex_init(&dev->intf_state_mutex);
1465 mutex_init(&priv->bfregs.reg_head.lock);
1466 mutex_init(&priv->bfregs.wc_head.lock);
1467 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1468 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1470 mutex_init(&priv->alloc_mutex);
1471 mutex_init(&priv->pgdir_mutex);
1472 INIT_LIST_HEAD(&priv->pgdir_list);
1474 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1475 priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device),
1477 INIT_LIST_HEAD(&priv->traps);
1479 err = mlx5_tout_init(dev);
1481 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1482 goto err_timeout_init;
1485 err = mlx5_health_init(dev);
1487 goto err_health_init;
1489 err = mlx5_pagealloc_init(dev);
1491 goto err_pagealloc_init;
1493 err = mlx5_adev_init(dev);
1497 err = mlx5_hca_caps_alloc(dev);
1504 mlx5_adev_cleanup(dev);
1506 mlx5_pagealloc_cleanup(dev);
1508 mlx5_health_cleanup(dev);
1510 mlx5_tout_cleanup(dev);
1512 debugfs_remove(dev->priv.dbg.dbg_root);
1513 mutex_destroy(&priv->pgdir_mutex);
1514 mutex_destroy(&priv->alloc_mutex);
1515 mutex_destroy(&priv->bfregs.wc_head.lock);
1516 mutex_destroy(&priv->bfregs.reg_head.lock);
1517 mutex_destroy(&dev->intf_state_mutex);
1521 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1523 struct mlx5_priv *priv = &dev->priv;
1525 mlx5_hca_caps_free(dev);
1526 mlx5_adev_cleanup(dev);
1527 mlx5_pagealloc_cleanup(dev);
1528 mlx5_health_cleanup(dev);
1529 mlx5_tout_cleanup(dev);
1530 debugfs_remove_recursive(dev->priv.dbg.dbg_root);
1531 mutex_destroy(&priv->pgdir_mutex);
1532 mutex_destroy(&priv->alloc_mutex);
1533 mutex_destroy(&priv->bfregs.wc_head.lock);
1534 mutex_destroy(&priv->bfregs.reg_head.lock);
1535 mutex_destroy(&dev->intf_state_mutex);
1538 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1540 struct mlx5_core_dev *dev;
1541 struct devlink *devlink;
1544 devlink = mlx5_devlink_alloc(&pdev->dev);
1546 dev_err(&pdev->dev, "devlink alloc failed\n");
1550 dev = devlink_priv(devlink);
1551 dev->device = &pdev->dev;
1554 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1555 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1557 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1558 if (dev->priv.adev_idx < 0) {
1559 err = dev->priv.adev_idx;
1563 err = mlx5_mdev_init(dev, prof_sel);
1567 err = mlx5_pci_init(dev, pdev, id);
1569 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1574 err = mlx5_init_one(dev);
1576 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1581 err = mlx5_crdump_enable(dev);
1583 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1585 pci_save_state(pdev);
1586 devlink_register(devlink);
1590 mlx5_pci_close(dev);
1592 mlx5_mdev_uninit(dev);
1594 mlx5_adev_idx_free(dev->priv.adev_idx);
1596 mlx5_devlink_free(devlink);
1601 static void remove_one(struct pci_dev *pdev)
1603 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1604 struct devlink *devlink = priv_to_devlink(dev);
1606 devlink_unregister(devlink);
1607 mlx5_sriov_disable(pdev);
1608 mlx5_crdump_disable(dev);
1609 mlx5_drain_health_wq(dev);
1610 mlx5_uninit_one(dev);
1611 mlx5_pci_close(dev);
1612 mlx5_mdev_uninit(dev);
1613 mlx5_adev_idx_free(dev->priv.adev_idx);
1614 mlx5_devlink_free(devlink);
1617 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1618 struct mlx5_core_dev *__dev = (dev); \
1619 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1620 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1621 __dev->pci_status, ##__VA_ARGS__); \
1624 static const char *result2str(enum pci_ers_result result)
1626 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1627 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1628 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1632 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1633 pci_channel_state_t state)
1635 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1636 enum pci_ers_result res;
1638 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1640 mlx5_enter_error_state(dev, false);
1641 mlx5_error_sw_reset(dev);
1642 mlx5_unload_one(dev);
1643 mlx5_drain_health_wq(dev);
1644 mlx5_pci_disable_device(dev);
1646 res = state == pci_channel_io_perm_failure ?
1647 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1649 mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res));
1653 /* wait for the device to show vital signs by waiting
1654 * for the health counter to start counting.
1656 static int wait_vital(struct pci_dev *pdev)
1658 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1659 struct mlx5_core_health *health = &dev->priv.health;
1660 const int niter = 100;
1665 for (i = 0; i < niter; i++) {
1666 count = ioread32be(health->health_counter);
1667 if (count && count != 0xffffffff) {
1668 if (last_count && last_count != count) {
1670 "wait vital counter value 0x%x after %d iterations\n",
1682 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1684 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1685 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1688 mlx5_pci_trace(dev, "Enter\n");
1690 err = mlx5_pci_enable_device(dev);
1692 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1697 pci_set_master(pdev);
1698 pci_restore_state(pdev);
1699 pci_save_state(pdev);
1701 err = wait_vital(pdev);
1703 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1708 res = PCI_ERS_RESULT_RECOVERED;
1710 mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res));
1714 static void mlx5_pci_resume(struct pci_dev *pdev)
1716 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1719 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1721 err = mlx5_load_one(dev);
1723 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1724 !err ? "recovered" : "Failed");
1727 static const struct pci_error_handlers mlx5_err_handler = {
1728 .error_detected = mlx5_pci_err_detected,
1729 .slot_reset = mlx5_pci_slot_reset,
1730 .resume = mlx5_pci_resume
1733 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1735 bool fast_teardown = false, force_teardown = false;
1738 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1739 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1741 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1742 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1744 if (!fast_teardown && !force_teardown)
1747 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1748 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1752 /* Panic tear down fw command will stop the PCI bus communication
1753 * with the HCA, so the health polll is no longer needed.
1755 mlx5_drain_health_wq(dev);
1756 mlx5_stop_health_poll(dev, false);
1758 ret = mlx5_cmd_fast_teardown_hca(dev);
1762 ret = mlx5_cmd_force_teardown_hca(dev);
1766 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1767 mlx5_start_health_poll(dev);
1771 mlx5_enter_error_state(dev, true);
1773 /* Some platforms requiring freeing the IRQ's in the shutdown
1774 * flow. If they aren't freed they can't be allocated after
1775 * kexec. There is no need to cleanup the mlx5_core software
1778 mlx5_core_eq_free_irqs(dev);
1783 static void shutdown(struct pci_dev *pdev)
1785 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1788 mlx5_core_info(dev, "Shutdown was called\n");
1789 err = mlx5_try_fast_unload(dev);
1791 mlx5_unload_one(dev);
1792 mlx5_pci_disable_device(dev);
1795 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1797 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1799 mlx5_unload_one(dev);
1804 static int mlx5_resume(struct pci_dev *pdev)
1806 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1808 return mlx5_load_one(dev);
1811 static const struct pci_device_id mlx5_core_pci_table[] = {
1812 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1813 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1814 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1815 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1816 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1817 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1818 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1819 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1820 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1821 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1822 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1823 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1824 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1825 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1826 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1827 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1828 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1829 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1830 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1831 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1832 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1833 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1837 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1839 void mlx5_disable_device(struct mlx5_core_dev *dev)
1841 mlx5_error_sw_reset(dev);
1842 mlx5_unload_one(dev);
1845 int mlx5_recover_device(struct mlx5_core_dev *dev)
1847 if (!mlx5_core_is_sf(dev)) {
1848 mlx5_pci_disable_device(dev);
1849 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1853 return mlx5_load_one(dev);
1856 static struct pci_driver mlx5_core_driver = {
1857 .name = KBUILD_MODNAME,
1858 .id_table = mlx5_core_pci_table,
1860 .remove = remove_one,
1861 .suspend = mlx5_suspend,
1862 .resume = mlx5_resume,
1863 .shutdown = shutdown,
1864 .err_handler = &mlx5_err_handler,
1865 .sriov_configure = mlx5_core_sriov_configure,
1866 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1867 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1871 * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if
1872 * mlx5_core is its driver.
1873 * @pdev: The associated PCI device.
1875 * Upon return the interface state lock stay held to let caller uses it safely.
1876 * Caller must ensure to use the returned mlx5 device for a narrow window
1877 * and put it back with mlx5_vf_put_core_dev() immediately once usage was over.
1879 * Return: Pointer to the associated mlx5_core_dev or NULL.
1881 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev)
1882 __acquires(&mdev->intf_state_mutex)
1884 struct mlx5_core_dev *mdev;
1886 mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver);
1890 mutex_lock(&mdev->intf_state_mutex);
1891 if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) {
1892 mutex_unlock(&mdev->intf_state_mutex);
1898 EXPORT_SYMBOL(mlx5_vf_get_core_dev);
1901 * mlx5_vf_put_core_dev - Put the mlx5 core device back.
1902 * @mdev: The mlx5 core device.
1904 * Upon return the interface state lock is unlocked and caller should not
1905 * access the mdev any more.
1907 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev)
1908 __releases(&mdev->intf_state_mutex)
1910 mutex_unlock(&mdev->intf_state_mutex);
1912 EXPORT_SYMBOL(mlx5_vf_put_core_dev);
1914 static void mlx5_core_verify_params(void)
1916 if (prof_sel >= ARRAY_SIZE(profile)) {
1917 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1919 ARRAY_SIZE(profile) - 1,
1921 prof_sel = MLX5_DEFAULT_PROF;
1925 static int __init init(void)
1929 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1930 "mlx5_core name not in sync with kernel module name");
1932 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1934 mlx5_core_verify_params();
1935 mlx5_register_debugfs();
1937 err = pci_register_driver(&mlx5_core_driver);
1941 err = mlx5_sf_driver_register();
1952 mlx5_sf_driver_unregister();
1954 pci_unregister_driver(&mlx5_core_driver);
1956 mlx5_unregister_debugfs();
1960 static void __exit cleanup(void)
1963 mlx5_sf_driver_unregister();
1964 pci_unregister_driver(&mlx5_core_driver);
1965 mlx5_unregister_debugfs();
1969 module_exit(cleanup);