drivers/net/ethernet/mellanox/mlx5/core/health.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/random.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/mlx5/driver.h>
  38 #include <linux/mlx5/cmd.h>
  39 #include "mlx5_core.h"
  40
  41 enum {
  42         MLX5_HEALTH_POLL_INTERVAL       = 2 * HZ,
  43         MAX_MISSES                      = 3,
  44 };
  45
  46 enum {
  47         MLX5_HEALTH_SYNDR_FW_ERR                = 0x1,
  48         MLX5_HEALTH_SYNDR_IRISC_ERR             = 0x7,
  49         MLX5_HEALTH_SYNDR_CRC_ERR               = 0x9,
  50         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR         = 0xa,
  51         MLX5_HEALTH_SYNDR_HW_FTL_ERR            = 0xb,
  52         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR  = 0xc,
  53         MLX5_HEALTH_SYNDR_EQ_ERR                = 0xd,
  54         MLX5_HEALTH_SYNDR_FFSER_ERR             = 0xf,
  55 };
  56
  57 static DEFINE_SPINLOCK(health_lock);
  58
  59 static LIST_HEAD(health_list);
  60 static struct work_struct health_work;
  61
  62 static health_handler_t reg_handler;
  63 int mlx5_register_health_report_handler(health_handler_t handler)
  64 {
  65         spin_lock_irq(&health_lock);
  66         if (reg_handler) {
  67                 spin_unlock_irq(&health_lock);
  68                 return -EEXIST;
  69         }
  70         reg_handler = handler;
  71         spin_unlock_irq(&health_lock);
  72
  73         return 0;
  74 }
  75 EXPORT_SYMBOL(mlx5_register_health_report_handler);
  76
  77 void mlx5_unregister_health_report_handler(void)
  78 {
  79         spin_lock_irq(&health_lock);
  80         reg_handler = NULL;
  81         spin_unlock_irq(&health_lock);
  82 }
  83 EXPORT_SYMBOL(mlx5_unregister_health_report_handler);
  84
  85 static void health_care(struct work_struct *work)
  86 {
  87         struct mlx5_core_health *health, *n;
  88         struct mlx5_core_dev *dev;
  89         struct mlx5_priv *priv;
  90         LIST_HEAD(tlist);
  91
  92         spin_lock_irq(&health_lock);
  93         list_splice_init(&health_list, &tlist);
  94
  95         spin_unlock_irq(&health_lock);
  96
  97         list_for_each_entry_safe(health, n, &tlist, list) {
  98                 priv = container_of(health, struct mlx5_priv, health);
  99                 dev = container_of(priv, struct mlx5_core_dev, priv);
 100                 mlx5_core_warn(dev, "handling bad device here\n");
 101                 spin_lock_irq(&health_lock);
 102                 if (reg_handler)
 103                         reg_handler(dev->pdev, health->health,
 104                                     sizeof(health->health));
 105
 106                 list_del_init(&health->list);
 107                 spin_unlock_irq(&health_lock);
 108         }
 109 }
 110
 111 static const char *hsynd_str(u8 synd)
 112 {
 113         switch (synd) {
 114         case MLX5_HEALTH_SYNDR_FW_ERR:
 115                 return "firmware internal error";
 116         case MLX5_HEALTH_SYNDR_IRISC_ERR:
 117                 return "irisc not responding";
 118         case MLX5_HEALTH_SYNDR_CRC_ERR:
 119                 return "firmware CRC error";
 120         case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
 121                 return "ICM fetch PCI error";
 122         case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
 123                 return "HW fatal error\n";
 124         case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
 125                 return "async EQ buffer overrun";
 126         case MLX5_HEALTH_SYNDR_EQ_ERR:
 127                 return "EQ error";
 128         case MLX5_HEALTH_SYNDR_FFSER_ERR:
 129                 return "FFSER error";
 130         default:
 131                 return "unrecognized error";
 132         }
 133 }
 134
 135 static u16 read_be16(__be16 __iomem *p)
 136 {
 137         return swab16(readl((__force u16 __iomem *) p));
 138 }
 139
 140 static u32 read_be32(__be32 __iomem *p)
 141 {
 142         return swab32(readl((__force u32 __iomem *) p));
 143 }
 144
 145 static void print_health_info(struct mlx5_core_dev *dev)
 146 {
 147         struct mlx5_core_health *health = &dev->priv.health;
 148         struct health_buffer __iomem *h = health->health;
 149         int i;
 150
 151         for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
 152                 pr_info("assert_var[%d] 0x%08x\n", i, read_be32(h->assert_var + i));
 153
 154         pr_info("assert_exit_ptr 0x%08x\n", read_be32(&h->assert_exit_ptr));
 155         pr_info("assert_callra 0x%08x\n", read_be32(&h->assert_callra));
 156         pr_info("fw_ver 0x%08x\n", read_be32(&h->fw_ver));
 157         pr_info("hw_id 0x%08x\n", read_be32(&h->hw_id));
 158         pr_info("irisc_index %d\n", readb(&h->irisc_index));
 159         pr_info("synd 0x%x: %s\n", readb(&h->synd), hsynd_str(readb(&h->synd)));
 160         pr_info("ext_sync 0x%04x\n", read_be16(&h->ext_sync));
 161 }
 162
 163 static void poll_health(unsigned long data)
 164 {
 165         struct mlx5_core_dev *dev = (struct mlx5_core_dev *)data;
 166         struct mlx5_core_health *health = &dev->priv.health;
 167         unsigned long next;
 168         u32 count;
 169
 170         count = ioread32be(health->health_counter);
 171         if (count == health->prev)
 172                 ++health->miss_counter;
 173         else
 174                 health->miss_counter = 0;
 175
 176         health->prev = count;
 177         if (health->miss_counter == MAX_MISSES) {
 178                 mlx5_core_err(dev, "device's health compromised\n");
 179                 print_health_info(dev);
 180                 spin_lock_irq(&health_lock);
 181                 list_add_tail(&health->list, &health_list);
 182                 spin_unlock_irq(&health_lock);
 183
 184                 queue_work(mlx5_core_wq, &health_work);
 185         } else {
 186                 get_random_bytes(&next, sizeof(next));
 187                 next %= HZ;
 188                 next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
 189                 mod_timer(&health->timer, next);
 190         }
 191 }
 192
 193 void mlx5_start_health_poll(struct mlx5_core_dev *dev)
 194 {
 195         struct mlx5_core_health *health = &dev->priv.health;
 196
 197         INIT_LIST_HEAD(&health->list);
 198         init_timer(&health->timer);
 199         health->health = &dev->iseg->health;
 200         health->health_counter = &dev->iseg->health_counter;
 201
 202         health->timer.data = (unsigned long)dev;
 203         health->timer.function = poll_health;
 204         health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
 205         add_timer(&health->timer);
 206 }
 207
 208 void mlx5_stop_health_poll(struct mlx5_core_dev *dev)
 209 {
 210         struct mlx5_core_health *health = &dev->priv.health;
 211
 212         del_timer_sync(&health->timer);
 213
 214         spin_lock_irq(&health_lock);
 215         if (!list_empty(&health->list))
 216                 list_del_init(&health->list);
 217         spin_unlock_irq(&health_lock);
 218 }
 219
 220 void mlx5_health_cleanup(void)
 221 {
 222 }
 223
 224 void  __init mlx5_health_init(void)
 225 {
 226         INIT_WORK(&health_work, health_care);
 227 }