drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38 #include "fpga/core.h"
  39 #ifdef CONFIG_MLX5_CORE_EN
  40 #include "eswitch.h"
  41 #endif
  42
  43 enum {
  44         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  45         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  46 };
  47
  48 enum {
  49         MLX5_EQ_STATE_ARMED             = 0x9,
  50         MLX5_EQ_STATE_FIRED             = 0xa,
  51         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  52 };
  53
  54 enum {
  55         MLX5_NUM_SPARE_EQE      = 0x80,
  56         MLX5_NUM_ASYNC_EQE      = 0x100,
  57         MLX5_NUM_CMD_EQE        = 32,
  58         MLX5_NUM_PF_DRAIN       = 64,
  59 };
  60
  61 enum {
  62         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  63 };
  64
  65 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  66                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  67                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  68                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  69                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  70                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  71                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  72                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  73                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  74                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  75                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  76                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  77
  78 struct map_eq_in {
  79         u64     mask;
  80         u32     reserved;
  81         u32     unmap_eqn;
  82 };
  83
  84 struct cre_des_eq {
  85         u8      reserved[15];
  86         u8      eqn;
  87 };
  88
  89 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  90 {
  91         u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
  92         u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]   = {0};
  93
  94         MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
  95         MLX5_SET(destroy_eq_in, in, eq_number, eqn);
  96         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  97 }
  98
  99 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
 100 {
 101         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 102 }
 103
 104 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 105 {
 106         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 107
 108         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 109 }
 110
 111 static const char *eqe_type_str(u8 type)
 112 {
 113         switch (type) {
 114         case MLX5_EVENT_TYPE_COMP:
 115                 return "MLX5_EVENT_TYPE_COMP";
 116         case MLX5_EVENT_TYPE_PATH_MIG:
 117                 return "MLX5_EVENT_TYPE_PATH_MIG";
 118         case MLX5_EVENT_TYPE_COMM_EST:
 119                 return "MLX5_EVENT_TYPE_COMM_EST";
 120         case MLX5_EVENT_TYPE_SQ_DRAINED:
 121                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 122         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 123                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 124         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 125                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 126         case MLX5_EVENT_TYPE_CQ_ERROR:
 127                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 128         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 129                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 130         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 131                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 132         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 133                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 134         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 135                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 136         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 137                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 138         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 139                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 140         case MLX5_EVENT_TYPE_PORT_CHANGE:
 141                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 142         case MLX5_EVENT_TYPE_GPIO_EVENT:
 143                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 144         case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
 145                 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
 146         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 147                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 148         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 149                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 150         case MLX5_EVENT_TYPE_STALL_EVENT:
 151                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 152         case MLX5_EVENT_TYPE_CMD:
 153                 return "MLX5_EVENT_TYPE_CMD";
 154         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 155                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 156         case MLX5_EVENT_TYPE_PAGE_FAULT:
 157                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 158         case MLX5_EVENT_TYPE_PPS_EVENT:
 159                 return "MLX5_EVENT_TYPE_PPS_EVENT";
 160         case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 161                 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
 162         case MLX5_EVENT_TYPE_FPGA_ERROR:
 163                 return "MLX5_EVENT_TYPE_FPGA_ERROR";
 164         case MLX5_EVENT_TYPE_GENERAL_EVENT:
 165                 return "MLX5_EVENT_TYPE_GENERAL_EVENT";
 166         default:
 167                 return "Unrecognized event";
 168         }
 169 }
 170
 171 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 172 {
 173         switch (subtype) {
 174         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 175                 return MLX5_DEV_EVENT_PORT_DOWN;
 176         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 177                 return MLX5_DEV_EVENT_PORT_UP;
 178         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 179                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 180         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 181                 return MLX5_DEV_EVENT_LID_CHANGE;
 182         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 183                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 184         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 185                 return MLX5_DEV_EVENT_GUID_CHANGE;
 186         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 187                 return MLX5_DEV_EVENT_CLIENT_REREG;
 188         }
 189         return -1;
 190 }
 191
 192 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 193 {
 194         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 195         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 196         __raw_writel((__force u32)cpu_to_be32(val), addr);
 197         /* We still want ordering, just not swabbing, so add a barrier */
 198         mb();
 199 }
 200
 201 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 202 static void eqe_pf_action(struct work_struct *work)
 203 {
 204         struct mlx5_pagefault *pfault = container_of(work,
 205                                                      struct mlx5_pagefault,
 206                                                      work);
 207         struct mlx5_eq *eq = pfault->eq;
 208
 209         mlx5_core_page_fault(eq->dev, pfault);
 210         mempool_free(pfault, eq->pf_ctx.pool);
 211 }
 212
 213 static void eq_pf_process(struct mlx5_eq *eq)
 214 {
 215         struct mlx5_core_dev *dev = eq->dev;
 216         struct mlx5_eqe_page_fault *pf_eqe;
 217         struct mlx5_pagefault *pfault;
 218         struct mlx5_eqe *eqe;
 219         int set_ci = 0;
 220
 221         while ((eqe = next_eqe_sw(eq))) {
 222                 pfault = mempool_alloc(eq->pf_ctx.pool, GFP_ATOMIC);
 223                 if (!pfault) {
 224                         schedule_work(&eq->pf_ctx.work);
 225                         break;
 226                 }
 227
 228                 dma_rmb();
 229                 pf_eqe = &eqe->data.page_fault;
 230                 pfault->event_subtype = eqe->sub_type;
 231                 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
 232
 233                 mlx5_core_dbg(dev,
 234                               "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
 235                               eqe->sub_type, pfault->bytes_committed);
 236
 237                 switch (eqe->sub_type) {
 238                 case MLX5_PFAULT_SUBTYPE_RDMA:
 239                         /* RDMA based event */
 240                         pfault->type =
 241                                 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
 242                         pfault->token =
 243                                 be32_to_cpu(pf_eqe->rdma.pftype_token) &
 244                                 MLX5_24BIT_MASK;
 245                         pfault->rdma.r_key =
 246                                 be32_to_cpu(pf_eqe->rdma.r_key);
 247                         pfault->rdma.packet_size =
 248                                 be16_to_cpu(pf_eqe->rdma.packet_length);
 249                         pfault->rdma.rdma_op_len =
 250                                 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
 251                         pfault->rdma.rdma_va =
 252                                 be64_to_cpu(pf_eqe->rdma.rdma_va);
 253                         mlx5_core_dbg(dev,
 254                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
 255                                       pfault->type, pfault->token,
 256                                       pfault->rdma.r_key);
 257                         mlx5_core_dbg(dev,
 258                                       "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
 259                                       pfault->rdma.rdma_op_len,
 260                                       pfault->rdma.rdma_va);
 261                         break;
 262
 263                 case MLX5_PFAULT_SUBTYPE_WQE:
 264                         /* WQE based event */
 265                         pfault->type =
 266                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24;
 267                         pfault->token =
 268                                 be32_to_cpu(pf_eqe->wqe.token);
 269                         pfault->wqe.wq_num =
 270                                 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
 271                                 MLX5_24BIT_MASK;
 272                         pfault->wqe.wqe_index =
 273                                 be16_to_cpu(pf_eqe->wqe.wqe_index);
 274                         pfault->wqe.packet_size =
 275                                 be16_to_cpu(pf_eqe->wqe.packet_length);
 276                         mlx5_core_dbg(dev,
 277                                       "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
 278                                       pfault->type, pfault->token,
 279                                       pfault->wqe.wq_num,
 280                                       pfault->wqe.wqe_index);
 281                         break;
 282
 283                 default:
 284                         mlx5_core_warn(dev,
 285                                        "Unsupported page fault event sub-type: 0x%02hhx\n",
 286                                        eqe->sub_type);
 287                         /* Unsupported page faults should still be
 288                          * resolved by the page fault handler
 289                          */
 290                 }
 291
 292                 pfault->eq = eq;
 293                 INIT_WORK(&pfault->work, eqe_pf_action);
 294                 queue_work(eq->pf_ctx.wq, &pfault->work);
 295
 296                 ++eq->cons_index;
 297                 ++set_ci;
 298
 299                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 300                         eq_update_ci(eq, 0);
 301                         set_ci = 0;
 302                 }
 303         }
 304
 305         eq_update_ci(eq, 1);
 306 }
 307
 308 static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
 309 {
 310         struct mlx5_eq *eq = eq_ptr;
 311         unsigned long flags;
 312
 313         if (spin_trylock_irqsave(&eq->pf_ctx.lock, flags)) {
 314                 eq_pf_process(eq);
 315                 spin_unlock_irqrestore(&eq->pf_ctx.lock, flags);
 316         } else {
 317                 schedule_work(&eq->pf_ctx.work);
 318         }
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323 /* mempool_refill() was proposed but unfortunately wasn't accepted
 324  * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
 325  * Chip workaround.
 326  */
 327 static void mempool_refill(mempool_t *pool)
 328 {
 329         while (pool->curr_nr < pool->min_nr)
 330                 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
 331 }
 332
 333 static void eq_pf_action(struct work_struct *work)
 334 {
 335         struct mlx5_eq *eq = container_of(work, struct mlx5_eq, pf_ctx.work);
 336
 337         mempool_refill(eq->pf_ctx.pool);
 338
 339         spin_lock_irq(&eq->pf_ctx.lock);
 340         eq_pf_process(eq);
 341         spin_unlock_irq(&eq->pf_ctx.lock);
 342 }
 343
 344 static int init_pf_ctx(struct mlx5_eq_pagefault *pf_ctx, const char *name)
 345 {
 346         spin_lock_init(&pf_ctx->lock);
 347         INIT_WORK(&pf_ctx->work, eq_pf_action);
 348
 349         pf_ctx->wq = alloc_ordered_workqueue(name,
 350                                              WQ_MEM_RECLAIM);
 351         if (!pf_ctx->wq)
 352                 return -ENOMEM;
 353
 354         pf_ctx->pool = mempool_create_kmalloc_pool
 355                 (MLX5_NUM_PF_DRAIN, sizeof(struct mlx5_pagefault));
 356         if (!pf_ctx->pool)
 357                 goto err_wq;
 358
 359         return 0;
 360 err_wq:
 361         destroy_workqueue(pf_ctx->wq);
 362         return -ENOMEM;
 363 }
 364
 365 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
 366                                 u32 wq_num, u8 type, int error)
 367 {
 368         u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = {0};
 369         u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)]   = {0};
 370
 371         MLX5_SET(page_fault_resume_in, in, opcode,
 372                  MLX5_CMD_OP_PAGE_FAULT_RESUME);
 373         MLX5_SET(page_fault_resume_in, in, error, !!error);
 374         MLX5_SET(page_fault_resume_in, in, page_fault_type, type);
 375         MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
 376         MLX5_SET(page_fault_resume_in, in, token, token);
 377
 378         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 379 }
 380 EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
 381 #endif
 382
 383 static void general_event_handler(struct mlx5_core_dev *dev,
 384                                   struct mlx5_eqe *eqe)
 385 {
 386         switch (eqe->sub_type) {
 387         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
 388                 if (dev->event)
 389                         dev->event(dev, MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 0);
 390                 break;
 391         default:
 392                 mlx5_core_dbg(dev, "General event with unrecognized subtype: sub_type %d\n",
 393                               eqe->sub_type);
 394         }
 395 }
 396
 397 static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
 398 {
 399         struct mlx5_eq *eq = eq_ptr;
 400         struct mlx5_core_dev *dev = eq->dev;
 401         struct mlx5_eqe *eqe;
 402         int set_ci = 0;
 403         u32 cqn = -1;
 404         u32 rsn;
 405         u8 port;
 406
 407         while ((eqe = next_eqe_sw(eq))) {
 408                 /*
 409                  * Make sure we read EQ entry contents after we've
 410                  * checked the ownership bit.
 411                  */
 412                 dma_rmb();
 413
 414                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 415                               eq->eqn, eqe_type_str(eqe->type));
 416                 switch (eqe->type) {
 417                 case MLX5_EVENT_TYPE_COMP:
 418                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 419                         mlx5_cq_completion(dev, cqn);
 420                         break;
 421
 422                 case MLX5_EVENT_TYPE_PATH_MIG:
 423                 case MLX5_EVENT_TYPE_COMM_EST:
 424                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 425                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 426                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 427                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 428                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 429                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 430                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 431                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
 432                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 433                                       eqe_type_str(eqe->type), eqe->type, rsn);
 434                         mlx5_rsc_event(dev, rsn, eqe->type);
 435                         break;
 436
 437                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 438                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 439                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 440                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 441                                       eqe_type_str(eqe->type), eqe->type, rsn);
 442                         mlx5_srq_event(dev, rsn, eqe->type);
 443                         break;
 444
 445                 case MLX5_EVENT_TYPE_CMD:
 446                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
 447                         break;
 448
 449                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 450                         port = (eqe->data.port.port >> 4) & 0xf;
 451                         switch (eqe->sub_type) {
 452                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 453                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 454                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 455                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 456                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 457                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 458                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 459                                 if (dev->event)
 460                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 461                                                    (unsigned long)port);
 462                                 break;
 463                         default:
 464                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 465                                                port, eqe->sub_type);
 466                         }
 467                         break;
 468                 case MLX5_EVENT_TYPE_CQ_ERROR:
 469                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 470                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 471                                        cqn, eqe->data.cq_err.syndrome);
 472                         mlx5_cq_event(dev, cqn, eqe->type);
 473                         break;
 474
 475                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 476                         {
 477                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 478                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 479
 480                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 481                                               func_id, npages);
 482                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 483                         }
 484                         break;
 485
 486 #ifdef CONFIG_MLX5_CORE_EN
 487                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 488                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
 489                         break;
 490 #endif
 491
 492                 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
 493                         mlx5_port_module_event(dev, eqe);
 494                         break;
 495
 496                 case MLX5_EVENT_TYPE_PPS_EVENT:
 497                         if (dev->event)
 498                                 dev->event(dev, MLX5_DEV_EVENT_PPS, (unsigned long)eqe);
 499                         break;
 500
 501                 case MLX5_EVENT_TYPE_FPGA_ERROR:
 502                         mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
 503                         break;
 504
 505                 case MLX5_EVENT_TYPE_GENERAL_EVENT:
 506                         general_event_handler(dev, eqe);
 507                         break;
 508                 default:
 509                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 510                                        eqe->type, eq->eqn);
 511                         break;
 512                 }
 513
 514                 ++eq->cons_index;
 515                 ++set_ci;
 516
 517                 /* The HCA will think the queue has overflowed if we
 518                  * don't tell it we've been processing events.  We
 519                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 520                  * entries, so we must update our consumer index at
 521                  * least that often.
 522                  */
 523                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 524                         eq_update_ci(eq, 0);
 525                         set_ci = 0;
 526                 }
 527         }
 528
 529         eq_update_ci(eq, 1);
 530
 531         if (cqn != -1)
 532                 tasklet_schedule(&eq->tasklet_ctx.task);
 533
 534         return IRQ_HANDLED;
 535 }
 536
 537 static void init_eq_buf(struct mlx5_eq *eq)
 538 {
 539         struct mlx5_eqe *eqe;
 540         int i;
 541
 542         for (i = 0; i < eq->nent; i++) {
 543                 eqe = get_eqe(eq, i);
 544                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 545         }
 546 }
 547
 548 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 549                        int nent, u64 mask, const char *name,
 550                        enum mlx5_eq_type type)
 551 {
 552         u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
 553         struct mlx5_priv *priv = &dev->priv;
 554         irq_handler_t handler;
 555         __be64 *pas;
 556         void *eqc;
 557         int inlen;
 558         u32 *in;
 559         int err;
 560
 561         eq->type = type;
 562         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 563         eq->cons_index = 0;
 564         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 565         if (err)
 566                 return err;
 567
 568 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 569         if (type == MLX5_EQ_TYPE_PF)
 570                 handler = mlx5_eq_pf_int;
 571         else
 572 #endif
 573                 handler = mlx5_eq_int;
 574
 575         init_eq_buf(eq);
 576
 577         inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
 578                 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
 579
 580         in = kvzalloc(inlen, GFP_KERNEL);
 581         if (!in) {
 582                 err = -ENOMEM;
 583                 goto err_buf;
 584         }
 585
 586         pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
 587         mlx5_fill_page_array(&eq->buf, pas);
 588
 589         MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
 590         MLX5_SET64(create_eq_in, in, event_bitmask, mask);
 591
 592         eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
 593         MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
 594         MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
 595         MLX5_SET(eqc, eqc, intr, vecidx);
 596         MLX5_SET(eqc, eqc, log_page_size,
 597                  eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 598
 599         err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
 600         if (err)
 601                 goto err_in;
 602
 603         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 604                  name, pci_name(dev->pdev));
 605
 606         eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
 607         eq->irqn = priv->msix_arr[vecidx].vector;
 608         eq->dev = dev;
 609         eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
 610         err = request_irq(eq->irqn, handler, 0,
 611                           priv->irq_info[vecidx].name, eq);
 612         if (err)
 613                 goto err_eq;
 614
 615         err = mlx5_debug_eq_add(dev, eq);
 616         if (err)
 617                 goto err_irq;
 618
 619 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 620         if (type == MLX5_EQ_TYPE_PF) {
 621                 err = init_pf_ctx(&eq->pf_ctx, name);
 622                 if (err)
 623                         goto err_irq;
 624         } else
 625 #endif
 626         {
 627                 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
 628                 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
 629                 spin_lock_init(&eq->tasklet_ctx.lock);
 630                 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
 631                              (unsigned long)&eq->tasklet_ctx);
 632         }
 633
 634         /* EQs are created in ARMED state
 635          */
 636         eq_update_ci(eq, 1);
 637
 638         kvfree(in);
 639         return 0;
 640
 641 err_irq:
 642         free_irq(priv->msix_arr[vecidx].vector, eq);
 643
 644 err_eq:
 645         mlx5_cmd_destroy_eq(dev, eq->eqn);
 646
 647 err_in:
 648         kvfree(in);
 649
 650 err_buf:
 651         mlx5_buf_free(dev, &eq->buf);
 652         return err;
 653 }
 654 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 655
 656 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 657 {
 658         int err;
 659
 660         mlx5_debug_eq_remove(dev, eq);
 661         free_irq(eq->irqn, eq);
 662         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 663         if (err)
 664                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 665                                eq->eqn);
 666         synchronize_irq(eq->irqn);
 667
 668         if (eq->type == MLX5_EQ_TYPE_COMP) {
 669                 tasklet_disable(&eq->tasklet_ctx.task);
 670 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 671         } else if (eq->type == MLX5_EQ_TYPE_PF) {
 672                 cancel_work_sync(&eq->pf_ctx.work);
 673                 destroy_workqueue(eq->pf_ctx.wq);
 674                 mempool_destroy(eq->pf_ctx.pool);
 675 #endif
 676         }
 677         mlx5_buf_free(dev, &eq->buf);
 678
 679         return err;
 680 }
 681 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 682
 683 u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
 684 {
 685         return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
 686 }
 687
 688 int mlx5_eq_init(struct mlx5_core_dev *dev)
 689 {
 690         int err;
 691
 692         spin_lock_init(&dev->priv.eq_table.lock);
 693
 694         err = mlx5_eq_debugfs_init(dev);
 695
 696         return err;
 697 }
 698
 699 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 700 {
 701         mlx5_eq_debugfs_cleanup(dev);
 702 }
 703
 704 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 705 {
 706         struct mlx5_eq_table *table = &dev->priv.eq_table;
 707         u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 708         int err;
 709
 710         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 711             MLX5_CAP_GEN(dev, vport_group_manager) &&
 712             mlx5_core_is_pf(dev))
 713                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 714
 715         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 716             MLX5_CAP_GEN(dev, general_notification_event))
 717                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
 718
 719         if (MLX5_CAP_GEN(dev, port_module_event))
 720                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
 721         else
 722                 mlx5_core_dbg(dev, "port_module_event is not set\n");
 723
 724         if (MLX5_CAP_GEN(dev, pps))
 725                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
 726
 727         if (MLX5_CAP_GEN(dev, fpga))
 728                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
 729
 730         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 731                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 732                                  "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
 733         if (err) {
 734                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 735                 return err;
 736         }
 737
 738         mlx5_cmd_use_events(dev);
 739
 740         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 741                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 742                                  "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
 743         if (err) {
 744                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 745                 goto err1;
 746         }
 747
 748         err = mlx5_create_map_eq(dev, &table->pages_eq,
 749                                  MLX5_EQ_VEC_PAGES,
 750                                  /* TODO: sriov max_vf + */ 1,
 751                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 752                                  MLX5_EQ_TYPE_ASYNC);
 753         if (err) {
 754                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 755                 goto err2;
 756         }
 757
 758 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 759         if (MLX5_CAP_GEN(dev, pg)) {
 760                 err = mlx5_create_map_eq(dev, &table->pfault_eq,
 761                                          MLX5_EQ_VEC_PFAULT,
 762                                          MLX5_NUM_ASYNC_EQE,
 763                                          1 << MLX5_EVENT_TYPE_PAGE_FAULT,
 764                                          "mlx5_page_fault_eq",
 765                                          MLX5_EQ_TYPE_PF);
 766                 if (err) {
 767                         mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
 768                                        err);
 769                         goto err3;
 770                 }
 771         }
 772
 773         return err;
 774 err3:
 775         mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 776 #else
 777         return err;
 778 #endif
 779
 780 err2:
 781         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 782
 783 err1:
 784         mlx5_cmd_use_polling(dev);
 785         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 786         return err;
 787 }
 788
 789 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
 790 {
 791         struct mlx5_eq_table *table = &dev->priv.eq_table;
 792         int err;
 793
 794 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 795         if (MLX5_CAP_GEN(dev, pg)) {
 796                 err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq);
 797                 if (err)
 798                         return err;
 799         }
 800 #endif
 801
 802         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 803         if (err)
 804                 return err;
 805
 806         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 807         mlx5_cmd_use_polling(dev);
 808
 809         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 810         if (err)
 811                 mlx5_cmd_use_events(dev);
 812
 813         return err;
 814 }
 815
 816 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 817                        u32 *out, int outlen)
 818 {
 819         u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
 820
 821         MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
 822         MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
 823         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
 824 }
 825 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);