drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/flow_offload.h>
  35 #include <net/sch_generic.h>
  36 #include <net/pkt_cls.h>
  37 #include <linux/mlx5/fs.h>
  38 #include <linux/mlx5/device.h>
  39 #include <linux/rhashtable.h>
  40 #include <linux/refcount.h>
  41 #include <linux/completion.h>
  42 #include <net/arp.h>
  43 #include <net/ipv6_stubs.h>
  44 #include <net/bareudp.h>
  45 #include <net/bonding.h>
  46 #include <net/dst_metadata.h>
  47 #include "devlink.h"
  48 #include "en.h"
  49 #include "en/tc/post_act.h"
  50 #include "en/tc/act_stats.h"
  51 #include "en_rep.h"
  52 #include "en/rep/tc.h"
  53 #include "en/rep/neigh.h"
  54 #include "en_tc.h"
  55 #include "eswitch.h"
  56 #include "fs_core.h"
  57 #include "en/port.h"
  58 #include "en/tc_tun.h"
  59 #include "en/mapping.h"
  60 #include "en/tc_ct.h"
  61 #include "en/mod_hdr.h"
  62 #include "en/tc_tun_encap.h"
  63 #include "en/tc/sample.h"
  64 #include "en/tc/act/act.h"
  65 #include "en/tc/post_meter.h"
  66 #include "lib/devcom.h"
  67 #include "lib/geneve.h"
  68 #include "lib/fs_chains.h"
  69 #include "diag/en_tc_tracepoint.h"
  70 #include <asm/div64.h>
  71 #include "lag/lag.h"
  72 #include "lag/mp.h"
  73
  74 #define MLX5E_TC_TABLE_NUM_GROUPS 4
  75 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
  76
  77 struct mlx5e_tc_table {
  78         /* Protects the dynamic assignment of the t parameter
  79          * which is the nic tc root table.
  80          */
  81         struct mutex                    t_lock;
  82         struct mlx5e_priv               *priv;
  83         struct mlx5_flow_table          *t;
  84         struct mlx5_flow_table          *miss_t;
  85         struct mlx5_fs_chains           *chains;
  86         struct mlx5e_post_act           *post_act;
  87
  88         struct rhashtable               ht;
  89
  90         struct mod_hdr_tbl mod_hdr;
  91         struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
  92         DECLARE_HASHTABLE(hairpin_tbl, 8);
  93
  94         struct notifier_block     netdevice_nb;
  95         struct netdev_net_notifier      netdevice_nn;
  96
  97         struct mlx5_tc_ct_priv         *ct;
  98         struct mapping_ctx             *mapping;
  99         struct dentry                  *dfs_root;
 100
 101         /* tc action stats */
 102         struct mlx5e_tc_act_stats_handle *action_stats_handle;
 103 };
 104
 105 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
 106         [MAPPED_OBJ_TO_REG] = {
 107                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 108                 .moffset = 0,
 109                 .mlen = 16,
 110         },
 111         [VPORT_TO_REG] = {
 112                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 113                 .moffset = 16,
 114                 .mlen = 16,
 115         },
 116         [TUNNEL_TO_REG] = {
 117                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
 118                 .moffset = 8,
 119                 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
 120                 .soffset = MLX5_BYTE_OFF(fte_match_param,
 121                                          misc_parameters_2.metadata_reg_c_1),
 122         },
 123         [ZONE_TO_REG] = zone_to_reg_ct,
 124         [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
 125         [CTSTATE_TO_REG] = ctstate_to_reg_ct,
 126         [MARK_TO_REG] = mark_to_reg_ct,
 127         [LABELS_TO_REG] = labels_to_reg_ct,
 128         [FTEID_TO_REG] = fteid_to_reg_ct,
 129         /* For NIC rules we store the restore metadata directly
 130          * into reg_b that is passed to SW since we don't
 131          * jump between steering domains.
 132          */
 133         [NIC_MAPPED_OBJ_TO_REG] = {
 134                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
 135                 .moffset = 0,
 136                 .mlen = 16,
 137         },
 138         [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
 139         [PACKET_COLOR_TO_REG] = packet_color_to_reg,
 140 };
 141
 142 struct mlx5e_tc_jump_state {
 143         u32 jump_count;
 144         bool jump_target;
 145         struct mlx5_flow_attr *jumping_attr;
 146
 147         enum flow_action_id last_id;
 148         u32 last_index;
 149 };
 150
 151 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
 152 {
 153         struct mlx5e_tc_table *tc;
 154
 155         tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
 156         return tc ? tc : ERR_PTR(-ENOMEM);
 157 }
 158
 159 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
 160 {
 161         kvfree(tc);
 162 }
 163
 164 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
 165 {
 166         return tc->chains;
 167 }
 168
 169 /* To avoid false lock dependency warning set the tc_ht lock
 170  * class different than the lock class of the ht being used when deleting
 171  * last flow from a group and then deleting a group, we get into del_sw_flow_group()
 172  * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
 173  * it's different than the ht->mutex here.
 174  */
 175 static struct lock_class_key tc_ht_lock_key;
 176 static struct lock_class_key tc_ht_wq_key;
 177
 178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
 179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
 180 static void mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow,
 181                                         struct mlx5_flow_attr *attr);
 182
 183 void
 184 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 185                             enum mlx5e_tc_attr_to_reg type,
 186                             u32 val,
 187                             u32 mask)
 188 {
 189         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 190         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 191         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 192         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 193         u32 max_mask = GENMASK(match_len - 1, 0);
 194         __be32 curr_mask_be, curr_val_be;
 195         u32 curr_mask, curr_val;
 196
 197         fmask = headers_c + soffset;
 198         fval = headers_v + soffset;
 199
 200         memcpy(&curr_mask_be, fmask, 4);
 201         memcpy(&curr_val_be, fval, 4);
 202
 203         curr_mask = be32_to_cpu(curr_mask_be);
 204         curr_val = be32_to_cpu(curr_val_be);
 205
 206         //move to correct offset
 207         WARN_ON(mask > max_mask);
 208         mask <<= moffset;
 209         val <<= moffset;
 210         max_mask <<= moffset;
 211
 212         //zero val and mask
 213         curr_mask &= ~max_mask;
 214         curr_val &= ~max_mask;
 215
 216         //add current to mask
 217         curr_mask |= mask;
 218         curr_val |= val;
 219
 220         //back to be32 and write
 221         curr_mask_be = cpu_to_be32(curr_mask);
 222         curr_val_be = cpu_to_be32(curr_val);
 223
 224         memcpy(fmask, &curr_mask_be, 4);
 225         memcpy(fval, &curr_val_be, 4);
 226
 227         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
 228 }
 229
 230 void
 231 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
 232                                 enum mlx5e_tc_attr_to_reg type,
 233                                 u32 *val,
 234                                 u32 *mask)
 235 {
 236         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 237         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 238         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 239         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 240         u32 max_mask = GENMASK(match_len - 1, 0);
 241         __be32 curr_mask_be, curr_val_be;
 242         u32 curr_mask, curr_val;
 243
 244         fmask = headers_c + soffset;
 245         fval = headers_v + soffset;
 246
 247         memcpy(&curr_mask_be, fmask, 4);
 248         memcpy(&curr_val_be, fval, 4);
 249
 250         curr_mask = be32_to_cpu(curr_mask_be);
 251         curr_val = be32_to_cpu(curr_val_be);
 252
 253         *mask = (curr_mask >> moffset) & max_mask;
 254         *val = (curr_val >> moffset) & max_mask;
 255 }
 256
 257 int
 258 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
 259                                      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 260                                      enum mlx5_flow_namespace_type ns,
 261                                      enum mlx5e_tc_attr_to_reg type,
 262                                      u32 data)
 263 {
 264         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 265         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 266         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 267         char *modact;
 268         int err;
 269
 270         modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
 271         if (IS_ERR(modact))
 272                 return PTR_ERR(modact);
 273
 274         /* Firmware has 5bit length field and 0 means 32bits */
 275         if (mlen == 32)
 276                 mlen = 0;
 277
 278         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 279         MLX5_SET(set_action_in, modact, field, mfield);
 280         MLX5_SET(set_action_in, modact, offset, moffset);
 281         MLX5_SET(set_action_in, modact, length, mlen);
 282         MLX5_SET(set_action_in, modact, data, data);
 283         err = mod_hdr_acts->num_actions;
 284         mod_hdr_acts->num_actions++;
 285
 286         return err;
 287 }
 288
 289 static struct mlx5e_tc_act_stats_handle  *
 290 get_act_stats_handle(struct mlx5e_priv *priv)
 291 {
 292         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 293         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 294         struct mlx5_rep_uplink_priv *uplink_priv;
 295         struct mlx5e_rep_priv *uplink_rpriv;
 296
 297         if (is_mdev_switchdev_mode(priv->mdev)) {
 298                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 299                 uplink_priv = &uplink_rpriv->uplink_priv;
 300
 301                 return uplink_priv->action_stats_handle;
 302         }
 303
 304         return tc->action_stats_handle;
 305 }
 306
 307 struct mlx5e_tc_int_port_priv *
 308 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
 309 {
 310         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 311         struct mlx5_rep_uplink_priv *uplink_priv;
 312         struct mlx5e_rep_priv *uplink_rpriv;
 313
 314         if (is_mdev_switchdev_mode(priv->mdev)) {
 315                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 316                 uplink_priv = &uplink_rpriv->uplink_priv;
 317
 318                 return uplink_priv->int_port_priv;
 319         }
 320
 321         return NULL;
 322 }
 323
 324 struct mlx5e_flow_meters *
 325 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
 326 {
 327         struct mlx5_eswitch *esw = dev->priv.eswitch;
 328         struct mlx5_rep_uplink_priv *uplink_priv;
 329         struct mlx5e_rep_priv *uplink_rpriv;
 330         struct mlx5e_priv *priv;
 331
 332         if (is_mdev_switchdev_mode(dev)) {
 333                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 334                 uplink_priv = &uplink_rpriv->uplink_priv;
 335                 priv = netdev_priv(uplink_rpriv->netdev);
 336                 if (!uplink_priv->flow_meters)
 337                         uplink_priv->flow_meters =
 338                                 mlx5e_flow_meters_init(priv,
 339                                                        MLX5_FLOW_NAMESPACE_FDB,
 340                                                        uplink_priv->post_act);
 341                 if (!IS_ERR(uplink_priv->flow_meters))
 342                         return uplink_priv->flow_meters;
 343         }
 344
 345         return NULL;
 346 }
 347
 348 static struct mlx5_tc_ct_priv *
 349 get_ct_priv(struct mlx5e_priv *priv)
 350 {
 351         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 352         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 353         struct mlx5_rep_uplink_priv *uplink_priv;
 354         struct mlx5e_rep_priv *uplink_rpriv;
 355
 356         if (is_mdev_switchdev_mode(priv->mdev)) {
 357                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 358                 uplink_priv = &uplink_rpriv->uplink_priv;
 359
 360                 return uplink_priv->ct_priv;
 361         }
 362
 363         return tc->ct;
 364 }
 365
 366 static struct mlx5e_tc_psample *
 367 get_sample_priv(struct mlx5e_priv *priv)
 368 {
 369         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 370         struct mlx5_rep_uplink_priv *uplink_priv;
 371         struct mlx5e_rep_priv *uplink_rpriv;
 372
 373         if (is_mdev_switchdev_mode(priv->mdev)) {
 374                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 375                 uplink_priv = &uplink_rpriv->uplink_priv;
 376
 377                 return uplink_priv->tc_psample;
 378         }
 379
 380         return NULL;
 381 }
 382
 383 static struct mlx5e_post_act *
 384 get_post_action(struct mlx5e_priv *priv)
 385 {
 386         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 387         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 388         struct mlx5_rep_uplink_priv *uplink_priv;
 389         struct mlx5e_rep_priv *uplink_rpriv;
 390
 391         if (is_mdev_switchdev_mode(priv->mdev)) {
 392                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 393                 uplink_priv = &uplink_rpriv->uplink_priv;
 394
 395                 return uplink_priv->post_act;
 396         }
 397
 398         return tc->post_act;
 399 }
 400
 401 struct mlx5_flow_handle *
 402 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
 403                     struct mlx5_flow_spec *spec,
 404                     struct mlx5_flow_attr *attr)
 405 {
 406         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 407
 408         if (is_mdev_switchdev_mode(priv->mdev))
 409                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 410
 411         return  mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 412 }
 413
 414 void
 415 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
 416                     struct mlx5_flow_handle *rule,
 417                     struct mlx5_flow_attr *attr)
 418 {
 419         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 420
 421         if (is_mdev_switchdev_mode(priv->mdev)) {
 422                 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 423                 return;
 424         }
 425
 426         mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 427 }
 428
 429 static bool
 430 is_flow_meter_action(struct mlx5_flow_attr *attr)
 431 {
 432         return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
 433                  (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
 434                 attr->flags & MLX5_ATTR_FLAG_MTU);
 435 }
 436
 437 static int
 438 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
 439                         struct mlx5_flow_attr *attr)
 440 {
 441         struct mlx5e_post_act *post_act = get_post_action(priv);
 442         struct mlx5e_post_meter_priv *post_meter;
 443         enum mlx5_flow_namespace_type ns_type;
 444         struct mlx5e_flow_meter_handle *meter;
 445         enum mlx5e_post_meter_type type;
 446
 447         if (IS_ERR(post_act))
 448                 return PTR_ERR(post_act);
 449
 450         meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
 451         if (IS_ERR(meter)) {
 452                 mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
 453                 return PTR_ERR(meter);
 454         }
 455
 456         ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
 457         type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
 458         post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
 459                                            type,
 460                                            meter->act_counter, meter->drop_counter,
 461                                            attr->branch_true, attr->branch_false);
 462         if (IS_ERR(post_meter)) {
 463                 mlx5_core_err(priv->mdev, "Failed to init post meter\n");
 464                 goto err_meter_init;
 465         }
 466
 467         attr->meter_attr.meter = meter;
 468         attr->meter_attr.post_meter = post_meter;
 469         attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
 470         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 471
 472         return 0;
 473
 474 err_meter_init:
 475         mlx5e_tc_meter_put(meter);
 476         return PTR_ERR(post_meter);
 477 }
 478
 479 static void
 480 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
 481 {
 482         mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
 483         mlx5e_tc_meter_put(attr->meter_attr.meter);
 484 }
 485
 486 struct mlx5_flow_handle *
 487 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
 488                       struct mlx5_flow_spec *spec,
 489                       struct mlx5_flow_attr *attr)
 490 {
 491         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 492         int err;
 493
 494         if (!is_mdev_switchdev_mode(priv->mdev))
 495                 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 496
 497         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
 498                 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
 499
 500         if (is_flow_meter_action(attr)) {
 501                 err = mlx5e_tc_add_flow_meter(priv, attr);
 502                 if (err)
 503                         return ERR_PTR(err);
 504         }
 505
 506         return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 507 }
 508
 509 void
 510 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
 511                         struct mlx5_flow_handle *rule,
 512                         struct mlx5_flow_attr *attr)
 513 {
 514         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 515
 516         if (!is_mdev_switchdev_mode(priv->mdev)) {
 517                 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 518                 return;
 519         }
 520
 521         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
 522                 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
 523                 return;
 524         }
 525
 526         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 527
 528         if (attr->meter_attr.meter)
 529                 mlx5e_tc_del_flow_meter(esw, attr);
 530 }
 531
 532 int
 533 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 534                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 535                           enum mlx5_flow_namespace_type ns,
 536                           enum mlx5e_tc_attr_to_reg type,
 537                           u32 data)
 538 {
 539         int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
 540
 541         return ret < 0 ? ret : 0;
 542 }
 543
 544 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
 545                                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 546                                           enum mlx5e_tc_attr_to_reg type,
 547                                           int act_id, u32 data)
 548 {
 549         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 550         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 551         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 552         char *modact;
 553
 554         modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
 555
 556         /* Firmware has 5bit length field and 0 means 32bits */
 557         if (mlen == 32)
 558                 mlen = 0;
 559
 560         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 561         MLX5_SET(set_action_in, modact, field, mfield);
 562         MLX5_SET(set_action_in, modact, offset, moffset);
 563         MLX5_SET(set_action_in, modact, length, mlen);
 564         MLX5_SET(set_action_in, modact, data, data);
 565 }
 566
 567 struct mlx5e_hairpin {
 568         struct mlx5_hairpin *pair;
 569
 570         struct mlx5_core_dev *func_mdev;
 571         struct mlx5e_priv *func_priv;
 572         u32 tdn;
 573         struct mlx5e_tir direct_tir;
 574
 575         int num_channels;
 576         u8 log_num_packets;
 577         struct mlx5e_rqt indir_rqt;
 578         struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
 579         struct mlx5_ttc_table *ttc;
 580 };
 581
 582 struct mlx5e_hairpin_entry {
 583         /* a node of a hash table which keeps all the  hairpin entries */
 584         struct hlist_node hairpin_hlist;
 585
 586         /* protects flows list */
 587         spinlock_t flows_lock;
 588         /* flows sharing the same hairpin */
 589         struct list_head flows;
 590         /* hpe's that were not fully initialized when dead peer update event
 591          * function traversed them.
 592          */
 593         struct list_head dead_peer_wait_list;
 594
 595         u16 peer_vhca_id;
 596         u8 prio;
 597         struct mlx5e_hairpin *hp;
 598         refcount_t refcnt;
 599         struct completion res_ready;
 600 };
 601
 602 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 603                               struct mlx5e_tc_flow *flow);
 604
 605 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 606 {
 607         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 608                 return ERR_PTR(-EINVAL);
 609         return flow;
 610 }
 611
 612 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 613 {
 614         if (refcount_dec_and_test(&flow->refcnt)) {
 615                 mlx5e_tc_del_flow(priv, flow);
 616                 kfree_rcu(flow, rcu_head);
 617         }
 618 }
 619
 620 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 621 {
 622         return flow_flag_test(flow, ESWITCH);
 623 }
 624
 625 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 626 {
 627         return flow_flag_test(flow, FT);
 628 }
 629
 630 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 631 {
 632         return flow_flag_test(flow, OFFLOADED);
 633 }
 634
 635 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
 636 {
 637         return mlx5e_is_eswitch_flow(flow) ?
 638                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 639 }
 640
 641 static struct mlx5_core_dev *
 642 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
 643 {
 644         return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
 645 }
 646
 647 static struct mod_hdr_tbl *
 648 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 649 {
 650         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 651         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 652
 653         return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
 654                 &esw->offloads.mod_hdr :
 655                 &tc->mod_hdr;
 656 }
 657
 658 int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
 659                             struct mlx5e_tc_flow *flow,
 660                             struct mlx5_flow_attr *attr)
 661 {
 662         struct mlx5e_mod_hdr_handle *mh;
 663
 664         mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
 665                                   mlx5e_get_flow_namespace(flow),
 666                                   &attr->parse_attr->mod_hdr_acts);
 667         if (IS_ERR(mh))
 668                 return PTR_ERR(mh);
 669
 670         WARN_ON(attr->modify_hdr);
 671         attr->modify_hdr = mlx5e_mod_hdr_get(mh);
 672         attr->mh = mh;
 673
 674         return 0;
 675 }
 676
 677 void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
 678                              struct mlx5e_tc_flow *flow,
 679                              struct mlx5_flow_attr *attr)
 680 {
 681         /* flow wasn't fully initialized */
 682         if (!attr->mh)
 683                 return;
 684
 685         mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
 686                              attr->mh);
 687         attr->mh = NULL;
 688 }
 689
 690 static
 691 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 692 {
 693         struct mlx5_core_dev *mdev;
 694         struct net_device *netdev;
 695         struct mlx5e_priv *priv;
 696
 697         netdev = dev_get_by_index(net, ifindex);
 698         if (!netdev)
 699                 return ERR_PTR(-ENODEV);
 700
 701         priv = netdev_priv(netdev);
 702         mdev = priv->mdev;
 703         dev_put(netdev);
 704
 705         /* Mirred tc action holds a refcount on the ifindex net_device (see
 706          * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
 707          * after dev_put(netdev), while we're in the context of adding a tc flow.
 708          *
 709          * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
 710          * stored in a hairpin object, which exists until all flows, that refer to it, get
 711          * removed.
 712          *
 713          * On the other hand, after a hairpin object has been created, the peer net_device may
 714          * be removed/unbound while there are still some hairpin flows that are using it. This
 715          * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
 716          * NETDEV_UNREGISTER event of the peer net_device.
 717          */
 718         return mdev;
 719 }
 720
 721 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 722 {
 723         struct mlx5e_tir_builder *builder;
 724         int err;
 725
 726         builder = mlx5e_tir_builder_alloc(false);
 727         if (!builder)
 728                 return -ENOMEM;
 729
 730         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 731         if (err)
 732                 goto out;
 733
 734         mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
 735         err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
 736         if (err)
 737                 goto create_tir_err;
 738
 739 out:
 740         mlx5e_tir_builder_free(builder);
 741         return err;
 742
 743 create_tir_err:
 744         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 745
 746         goto out;
 747 }
 748
 749 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 750 {
 751         mlx5e_tir_destroy(&hp->direct_tir);
 752         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 753 }
 754
 755 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 756 {
 757         struct mlx5e_priv *priv = hp->func_priv;
 758         struct mlx5_core_dev *mdev = priv->mdev;
 759         struct mlx5e_rss_params_indir *indir;
 760         int err;
 761
 762         indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
 763         if (!indir)
 764                 return -ENOMEM;
 765
 766         mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
 767         err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
 768                                    mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
 769                                    indir);
 770
 771         kvfree(indir);
 772         return err;
 773 }
 774
 775 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 776 {
 777         struct mlx5e_priv *priv = hp->func_priv;
 778         struct mlx5e_rss_params_hash rss_hash;
 779         enum mlx5_traffic_types tt, max_tt;
 780         struct mlx5e_tir_builder *builder;
 781         int err = 0;
 782
 783         builder = mlx5e_tir_builder_alloc(false);
 784         if (!builder)
 785                 return -ENOMEM;
 786
 787         rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
 788
 789         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 790                 struct mlx5e_rss_params_traffic_type rss_tt;
 791
 792                 rss_tt = mlx5e_rss_get_default_tt_config(tt);
 793
 794                 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
 795                                             mlx5e_rqt_get_rqtn(&hp->indir_rqt),
 796                                             false);
 797                 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
 798
 799                 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
 800                 if (err) {
 801                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 802                         goto err_destroy_tirs;
 803                 }
 804
 805                 mlx5e_tir_builder_clear(builder);
 806         }
 807
 808 out:
 809         mlx5e_tir_builder_free(builder);
 810         return err;
 811
 812 err_destroy_tirs:
 813         max_tt = tt;
 814         for (tt = 0; tt < max_tt; tt++)
 815                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 816
 817         goto out;
 818 }
 819
 820 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 821 {
 822         int tt;
 823
 824         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 825                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 826 }
 827
 828 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 829                                          struct ttc_params *ttc_params)
 830 {
 831         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 832         int tt;
 833
 834         memset(ttc_params, 0, sizeof(*ttc_params));
 835
 836         ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
 837                                                  MLX5_FLOW_NAMESPACE_KERNEL);
 838         for (tt = 0; tt < MLX5_NUM_TT; tt++) {
 839                 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 840                 ttc_params->dests[tt].tir_num =
 841                         tt == MLX5_TT_ANY ?
 842                                 mlx5e_tir_get_tirn(&hp->direct_tir) :
 843                                 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
 844         }
 845
 846         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 847         ft_attr->prio = MLX5E_TC_PRIO;
 848 }
 849
 850 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 851 {
 852         struct mlx5e_priv *priv = hp->func_priv;
 853         struct ttc_params ttc_params;
 854         struct mlx5_ttc_table *ttc;
 855         int err;
 856
 857         err = mlx5e_hairpin_create_indirect_rqt(hp);
 858         if (err)
 859                 return err;
 860
 861         err = mlx5e_hairpin_create_indirect_tirs(hp);
 862         if (err)
 863                 goto err_create_indirect_tirs;
 864
 865         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 866         hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
 867         if (IS_ERR(hp->ttc)) {
 868                 err = PTR_ERR(hp->ttc);
 869                 goto err_create_ttc_table;
 870         }
 871
 872         ttc = mlx5e_fs_get_ttc(priv->fs, false);
 873         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 874                    hp->num_channels,
 875                    mlx5_get_ttc_flow_table(ttc)->id);
 876
 877         return 0;
 878
 879 err_create_ttc_table:
 880         mlx5e_hairpin_destroy_indirect_tirs(hp);
 881 err_create_indirect_tirs:
 882         mlx5e_rqt_destroy(&hp->indir_rqt);
 883
 884         return err;
 885 }
 886
 887 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 888 {
 889         mlx5_destroy_ttc_table(hp->ttc);
 890         mlx5e_hairpin_destroy_indirect_tirs(hp);
 891         mlx5e_rqt_destroy(&hp->indir_rqt);
 892 }
 893
 894 static struct mlx5e_hairpin *
 895 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 896                      int peer_ifindex)
 897 {
 898         struct mlx5_core_dev *func_mdev, *peer_mdev;
 899         struct mlx5e_hairpin *hp;
 900         struct mlx5_hairpin *pair;
 901         int err;
 902
 903         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 904         if (!hp)
 905                 return ERR_PTR(-ENOMEM);
 906
 907         func_mdev = priv->mdev;
 908         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 909         if (IS_ERR(peer_mdev)) {
 910                 err = PTR_ERR(peer_mdev);
 911                 goto create_pair_err;
 912         }
 913
 914         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 915         if (IS_ERR(pair)) {
 916                 err = PTR_ERR(pair);
 917                 goto create_pair_err;
 918         }
 919         hp->pair = pair;
 920         hp->func_mdev = func_mdev;
 921         hp->func_priv = priv;
 922         hp->num_channels = params->num_channels;
 923         hp->log_num_packets = params->log_num_packets;
 924
 925         err = mlx5e_hairpin_create_transport(hp);
 926         if (err)
 927                 goto create_transport_err;
 928
 929         if (hp->num_channels > 1) {
 930                 err = mlx5e_hairpin_rss_init(hp);
 931                 if (err)
 932                         goto rss_init_err;
 933         }
 934
 935         return hp;
 936
 937 rss_init_err:
 938         mlx5e_hairpin_destroy_transport(hp);
 939 create_transport_err:
 940         mlx5_core_hairpin_destroy(hp->pair);
 941 create_pair_err:
 942         kfree(hp);
 943         return ERR_PTR(err);
 944 }
 945
 946 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 947 {
 948         if (hp->num_channels > 1)
 949                 mlx5e_hairpin_rss_cleanup(hp);
 950         mlx5e_hairpin_destroy_transport(hp);
 951         mlx5_core_hairpin_destroy(hp->pair);
 952         kvfree(hp);
 953 }
 954
 955 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 956 {
 957         return (peer_vhca_id << 16 | prio);
 958 }
 959
 960 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 961                                                      u16 peer_vhca_id, u8 prio)
 962 {
 963         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 964         struct mlx5e_hairpin_entry *hpe;
 965         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 966
 967         hash_for_each_possible(tc->hairpin_tbl, hpe,
 968                                hairpin_hlist, hash_key) {
 969                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 970                         refcount_inc(&hpe->refcnt);
 971                         return hpe;
 972                 }
 973         }
 974
 975         return NULL;
 976 }
 977
 978 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 979                               struct mlx5e_hairpin_entry *hpe)
 980 {
 981         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 982         /* no more hairpin flows for us, release the hairpin pair */
 983         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
 984                 return;
 985         hash_del(&hpe->hairpin_hlist);
 986         mutex_unlock(&tc->hairpin_tbl_lock);
 987
 988         if (!IS_ERR_OR_NULL(hpe->hp)) {
 989                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 990                            dev_name(hpe->hp->pair->peer_mdev->device));
 991
 992                 mlx5e_hairpin_destroy(hpe->hp);
 993         }
 994
 995         WARN_ON(!list_empty(&hpe->flows));
 996         kfree(hpe);
 997 }
 998
 999 #define UNKNOWN_MATCH_PRIO 8
1000
1001 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
1002                                   struct mlx5_flow_spec *spec, u8 *match_prio,
1003                                   struct netlink_ext_ack *extack)
1004 {
1005         void *headers_c, *headers_v;
1006         u8 prio_val, prio_mask = 0;
1007         bool vlan_present;
1008
1009 #ifdef CONFIG_MLX5_CORE_EN_DCB
1010         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1011                 NL_SET_ERR_MSG_MOD(extack,
1012                                    "only PCP trust state supported for hairpin");
1013                 return -EOPNOTSUPP;
1014         }
1015 #endif
1016         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1017         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1018
1019         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1020         if (vlan_present) {
1021                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1022                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1023         }
1024
1025         if (!vlan_present || !prio_mask) {
1026                 prio_val = UNKNOWN_MATCH_PRIO;
1027         } else if (prio_mask != 0x7) {
1028                 NL_SET_ERR_MSG_MOD(extack,
1029                                    "masked priority match not supported for hairpin");
1030                 return -EOPNOTSUPP;
1031         }
1032
1033         *match_prio = prio_val;
1034         return 0;
1035 }
1036
1037 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1038 {
1039         struct mlx5e_tc_table *tc = data;
1040         struct mlx5e_hairpin_entry *hpe;
1041         u32 cnt = 0;
1042         u32 bkt;
1043
1044         mutex_lock(&tc->hairpin_tbl_lock);
1045         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1046                 cnt++;
1047         mutex_unlock(&tc->hairpin_tbl_lock);
1048
1049         *val = cnt;
1050
1051         return 0;
1052 }
1053 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1054                          debugfs_hairpin_num_active_get, NULL, "%llu\n");
1055
1056 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1057
1058 {
1059         struct mlx5e_tc_table *tc = file->private;
1060         struct mlx5e_hairpin_entry *hpe;
1061         u32 bkt;
1062
1063         mutex_lock(&tc->hairpin_tbl_lock);
1064         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1065                 seq_printf(file,
1066                            "Hairpin peer_vhca_id %u prio %u refcnt %u num_channels %u num_packets %lu\n",
1067                            hpe->peer_vhca_id, hpe->prio,
1068                            refcount_read(&hpe->refcnt), hpe->hp->num_channels,
1069                            BIT(hpe->hp->log_num_packets));
1070         mutex_unlock(&tc->hairpin_tbl_lock);
1071
1072         return 0;
1073 }
1074 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1075
1076 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1077                                   struct dentry *dfs_root)
1078 {
1079         if (IS_ERR_OR_NULL(dfs_root))
1080                 return;
1081
1082         tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1083
1084         debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1085                             &fops_hairpin_num_active);
1086         debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1087                             &debugfs_hairpin_table_dump_fops);
1088 }
1089
1090 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1091                                   struct mlx5e_tc_flow *flow,
1092                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
1093                                   struct netlink_ext_ack *extack)
1094 {
1095         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1096         struct devlink *devlink = priv_to_devlink(priv->mdev);
1097         int peer_ifindex = parse_attr->mirred_ifindex[0];
1098         union devlink_param_value val = {};
1099         struct mlx5_hairpin_params params;
1100         struct mlx5_core_dev *peer_mdev;
1101         struct mlx5e_hairpin_entry *hpe;
1102         struct mlx5e_hairpin *hp;
1103         u8 match_prio;
1104         u16 peer_id;
1105         int err;
1106
1107         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1108         if (IS_ERR(peer_mdev)) {
1109                 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1110                 return PTR_ERR(peer_mdev);
1111         }
1112
1113         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1114                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1115                 return -EOPNOTSUPP;
1116         }
1117
1118         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1119         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1120                                      extack);
1121         if (err)
1122                 return err;
1123
1124         mutex_lock(&tc->hairpin_tbl_lock);
1125         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1126         if (hpe) {
1127                 mutex_unlock(&tc->hairpin_tbl_lock);
1128                 wait_for_completion(&hpe->res_ready);
1129
1130                 if (IS_ERR(hpe->hp)) {
1131                         err = -EREMOTEIO;
1132                         goto out_err;
1133                 }
1134                 goto attach_flow;
1135         }
1136
1137         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1138         if (!hpe) {
1139                 mutex_unlock(&tc->hairpin_tbl_lock);
1140                 return -ENOMEM;
1141         }
1142
1143         spin_lock_init(&hpe->flows_lock);
1144         INIT_LIST_HEAD(&hpe->flows);
1145         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1146         hpe->peer_vhca_id = peer_id;
1147         hpe->prio = match_prio;
1148         refcount_set(&hpe->refcnt, 1);
1149         init_completion(&hpe->res_ready);
1150
1151         hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1152                  hash_hairpin_info(peer_id, match_prio));
1153         mutex_unlock(&tc->hairpin_tbl_lock);
1154
1155         err = devl_param_driverinit_value_get(
1156                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &val);
1157         if (err) {
1158                 err = -ENOMEM;
1159                 goto out_err;
1160         }
1161
1162         params.log_num_packets = ilog2(val.vu32);
1163         params.log_data_size =
1164                 clamp_t(u32,
1165                         params.log_num_packets +
1166                                 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1167                         MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1168                         MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1169
1170         params.q_counter = priv->q_counter;
1171         err = devl_param_driverinit_value_get(
1172                 devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &val);
1173         if (err) {
1174                 err = -ENOMEM;
1175                 goto out_err;
1176         }
1177
1178         params.num_channels = val.vu32;
1179
1180         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
1181         hpe->hp = hp;
1182         complete_all(&hpe->res_ready);
1183         if (IS_ERR(hp)) {
1184                 err = PTR_ERR(hp);
1185                 goto out_err;
1186         }
1187
1188         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1189                    mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1190                    dev_name(hp->pair->peer_mdev->device),
1191                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1192
1193 attach_flow:
1194         if (hpe->hp->num_channels > 1) {
1195                 flow_flag_set(flow, HAIRPIN_RSS);
1196                 flow->attr->nic_attr->hairpin_ft =
1197                         mlx5_get_ttc_flow_table(hpe->hp->ttc);
1198         } else {
1199                 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1200         }
1201
1202         flow->hpe = hpe;
1203         spin_lock(&hpe->flows_lock);
1204         list_add(&flow->hairpin, &hpe->flows);
1205         spin_unlock(&hpe->flows_lock);
1206
1207         return 0;
1208
1209 out_err:
1210         mlx5e_hairpin_put(priv, hpe);
1211         return err;
1212 }
1213
1214 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1215                                    struct mlx5e_tc_flow *flow)
1216 {
1217         /* flow wasn't fully initialized */
1218         if (!flow->hpe)
1219                 return;
1220
1221         spin_lock(&flow->hpe->flows_lock);
1222         list_del(&flow->hairpin);
1223         spin_unlock(&flow->hpe->flows_lock);
1224
1225         mlx5e_hairpin_put(priv, flow->hpe);
1226         flow->hpe = NULL;
1227 }
1228
1229 struct mlx5_flow_handle *
1230 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1231                              struct mlx5_flow_spec *spec,
1232                              struct mlx5_flow_attr *attr)
1233 {
1234         struct mlx5_flow_context *flow_context = &spec->flow_context;
1235         struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1236         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1237         struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1238         struct mlx5_flow_destination dest[2] = {};
1239         struct mlx5_fs_chains *nic_chains;
1240         struct mlx5_flow_act flow_act = {
1241                 .action = attr->action,
1242                 .flags    = FLOW_ACT_NO_APPEND,
1243         };
1244         struct mlx5_flow_handle *rule;
1245         struct mlx5_flow_table *ft;
1246         int dest_ix = 0;
1247
1248         nic_chains = mlx5e_nic_chains(tc);
1249         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1250         flow_context->flow_tag = nic_attr->flow_tag;
1251
1252         if (attr->dest_ft) {
1253                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1254                 dest[dest_ix].ft = attr->dest_ft;
1255                 dest_ix++;
1256         } else if (nic_attr->hairpin_ft) {
1257                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1258                 dest[dest_ix].ft = nic_attr->hairpin_ft;
1259                 dest_ix++;
1260         } else if (nic_attr->hairpin_tirn) {
1261                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1262                 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1263                 dest_ix++;
1264         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1265                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1266                 if (attr->dest_chain) {
1267                         dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1268                                                                  attr->dest_chain, 1,
1269                                                                  MLX5E_TC_FT_LEVEL);
1270                         if (IS_ERR(dest[dest_ix].ft))
1271                                 return ERR_CAST(dest[dest_ix].ft);
1272                 } else {
1273                         dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1274                 }
1275                 dest_ix++;
1276         }
1277
1278         if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1279             MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1280                 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1281
1282         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1283                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1284                 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
1285                 dest_ix++;
1286         }
1287
1288         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1289                 flow_act.modify_hdr = attr->modify_hdr;
1290
1291         mutex_lock(&tc->t_lock);
1292         if (IS_ERR_OR_NULL(tc->t)) {
1293                 /* Create the root table here if doesn't exist yet */
1294                 tc->t =
1295                         mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1296
1297                 if (IS_ERR(tc->t)) {
1298                         mutex_unlock(&tc->t_lock);
1299                         netdev_err(priv->netdev,
1300                                    "Failed to create tc offload table\n");
1301                         rule = ERR_CAST(tc->t);
1302                         goto err_ft_get;
1303                 }
1304         }
1305         mutex_unlock(&tc->t_lock);
1306
1307         if (attr->chain || attr->prio)
1308                 ft = mlx5_chains_get_table(nic_chains,
1309                                            attr->chain, attr->prio,
1310                                            MLX5E_TC_FT_LEVEL);
1311         else
1312                 ft = attr->ft;
1313
1314         if (IS_ERR(ft)) {
1315                 rule = ERR_CAST(ft);
1316                 goto err_ft_get;
1317         }
1318
1319         if (attr->outer_match_level != MLX5_MATCH_NONE)
1320                 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1321
1322         rule = mlx5_add_flow_rules(ft, spec,
1323                                    &flow_act, dest, dest_ix);
1324         if (IS_ERR(rule))
1325                 goto err_rule;
1326
1327         return rule;
1328
1329 err_rule:
1330         if (attr->chain || attr->prio)
1331                 mlx5_chains_put_table(nic_chains,
1332                                       attr->chain, attr->prio,
1333                                       MLX5E_TC_FT_LEVEL);
1334 err_ft_get:
1335         if (attr->dest_chain)
1336                 mlx5_chains_put_table(nic_chains,
1337                                       attr->dest_chain, 1,
1338                                       MLX5E_TC_FT_LEVEL);
1339
1340         return ERR_CAST(rule);
1341 }
1342
1343 static int
1344 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1345                         struct mlx5_flow_attr *attr)
1346
1347 {
1348         struct mlx5_fc *counter;
1349
1350         counter = mlx5_fc_create(counter_dev, true);
1351         if (IS_ERR(counter))
1352                 return PTR_ERR(counter);
1353
1354         attr->counter = counter;
1355         return 0;
1356 }
1357
1358 static int
1359 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1360                       struct mlx5e_tc_flow *flow,
1361                       struct netlink_ext_ack *extack)
1362 {
1363         struct mlx5e_tc_flow_parse_attr *parse_attr;
1364         struct mlx5_flow_attr *attr = flow->attr;
1365         struct mlx5_core_dev *dev = priv->mdev;
1366         int err;
1367
1368         parse_attr = attr->parse_attr;
1369
1370         if (flow_flag_test(flow, HAIRPIN)) {
1371                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1372                 if (err)
1373                         return err;
1374         }
1375
1376         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1377                 err = alloc_flow_attr_counter(dev, attr);
1378                 if (err)
1379                         return err;
1380         }
1381
1382         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1383                 err = mlx5e_tc_attach_mod_hdr(priv, flow, attr);
1384                 if (err)
1385                         return err;
1386         }
1387
1388         flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec, attr);
1389         return PTR_ERR_OR_ZERO(flow->rule[0]);
1390 }
1391
1392 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1393                                   struct mlx5_flow_handle *rule,
1394                                   struct mlx5_flow_attr *attr)
1395 {
1396         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1397         struct mlx5_fs_chains *nic_chains;
1398
1399         nic_chains = mlx5e_nic_chains(tc);
1400         mlx5_del_flow_rules(rule);
1401
1402         if (attr->chain || attr->prio)
1403                 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1404                                       MLX5E_TC_FT_LEVEL);
1405
1406         if (attr->dest_chain)
1407                 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1408                                       MLX5E_TC_FT_LEVEL);
1409 }
1410
1411 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1412                                   struct mlx5e_tc_flow *flow)
1413 {
1414         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1415         struct mlx5_flow_attr *attr = flow->attr;
1416
1417         flow_flag_clear(flow, OFFLOADED);
1418
1419         if (!IS_ERR_OR_NULL(flow->rule[0]))
1420                 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1421
1422         /* Remove root table if no rules are left to avoid
1423          * extra steering hops.
1424          */
1425         mutex_lock(&tc->t_lock);
1426         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1427             !IS_ERR_OR_NULL(tc->t)) {
1428                 mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1429                 tc->t = NULL;
1430         }
1431         mutex_unlock(&tc->t_lock);
1432
1433         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1434                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1435                 mlx5e_tc_detach_mod_hdr(priv, flow, attr);
1436         }
1437
1438         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1439                 mlx5_fc_destroy(priv->mdev, attr->counter);
1440
1441         if (flow_flag_test(flow, HAIRPIN))
1442                 mlx5e_hairpin_flow_del(priv, flow);
1443
1444         free_flow_post_acts(flow);
1445         mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
1446
1447         kvfree(attr->parse_attr);
1448         kfree(flow->attr);
1449 }
1450
1451 struct mlx5_flow_handle *
1452 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1453                            struct mlx5e_tc_flow *flow,
1454                            struct mlx5_flow_spec *spec,
1455                            struct mlx5_flow_attr *attr)
1456 {
1457         struct mlx5_flow_handle *rule;
1458
1459         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1460                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1461
1462         rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1463
1464         if (IS_ERR(rule))
1465                 return rule;
1466
1467         if (attr->esw_attr->split_count) {
1468                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1469                 if (IS_ERR(flow->rule[1]))
1470                         goto err_rule1;
1471         }
1472
1473         return rule;
1474
1475 err_rule1:
1476         mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1477         return flow->rule[1];
1478 }
1479
1480 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1481                                   struct mlx5e_tc_flow *flow,
1482                                   struct mlx5_flow_attr *attr)
1483 {
1484         flow_flag_clear(flow, OFFLOADED);
1485
1486         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1487                 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1488
1489         if (attr->esw_attr->split_count)
1490                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1491
1492         mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1493 }
1494
1495 struct mlx5_flow_handle *
1496 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1497                               struct mlx5e_tc_flow *flow,
1498                               struct mlx5_flow_spec *spec)
1499 {
1500         struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1501         struct mlx5e_mod_hdr_handle *mh = NULL;
1502         struct mlx5_flow_attr *slow_attr;
1503         struct mlx5_flow_handle *rule;
1504         bool fwd_and_modify_cap;
1505         u32 chain_mapping = 0;
1506         int err;
1507
1508         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1509         if (!slow_attr)
1510                 return ERR_PTR(-ENOMEM);
1511
1512         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1513         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1514         slow_attr->esw_attr->split_count = 0;
1515         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1516
1517         fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1518         if (!fwd_and_modify_cap)
1519                 goto skip_restore;
1520
1521         err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1522         if (err)
1523                 goto err_get_chain;
1524
1525         err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1526                                         MAPPED_OBJ_TO_REG, chain_mapping);
1527         if (err)
1528                 goto err_reg_set;
1529
1530         mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1531                                   MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1532         if (IS_ERR(mh)) {
1533                 err = PTR_ERR(mh);
1534                 goto err_attach;
1535         }
1536
1537         slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1538         slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1539
1540 skip_restore:
1541         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1542         if (IS_ERR(rule)) {
1543                 err = PTR_ERR(rule);
1544                 goto err_offload;
1545         }
1546
1547         flow->attr->slow_mh = mh;
1548         flow->chain_mapping = chain_mapping;
1549         flow_flag_set(flow, SLOW);
1550
1551         mlx5e_mod_hdr_dealloc(&mod_acts);
1552         kfree(slow_attr);
1553
1554         return rule;
1555
1556 err_offload:
1557         if (fwd_and_modify_cap)
1558                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1559 err_attach:
1560 err_reg_set:
1561         if (fwd_and_modify_cap)
1562                 mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1563 err_get_chain:
1564         mlx5e_mod_hdr_dealloc(&mod_acts);
1565         kfree(slow_attr);
1566         return ERR_PTR(err);
1567 }
1568
1569 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1570                                        struct mlx5e_tc_flow *flow)
1571 {
1572         struct mlx5e_mod_hdr_handle *slow_mh = flow->attr->slow_mh;
1573         struct mlx5_flow_attr *slow_attr;
1574
1575         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1576         if (!slow_attr) {
1577                 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1578                 return;
1579         }
1580
1581         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1582         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1583         slow_attr->esw_attr->split_count = 0;
1584         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1585         if (slow_mh) {
1586                 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1587                 slow_attr->modify_hdr = mlx5e_mod_hdr_get(slow_mh);
1588         }
1589         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1590         if (slow_mh) {
1591                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), slow_mh);
1592                 mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1593                 flow->chain_mapping = 0;
1594                 flow->attr->slow_mh = NULL;
1595         }
1596         flow_flag_clear(flow, SLOW);
1597         kfree(slow_attr);
1598 }
1599
1600 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1601  * function.
1602  */
1603 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1604                              struct list_head *unready_flows)
1605 {
1606         flow_flag_set(flow, NOT_READY);
1607         list_add_tail(&flow->unready, unready_flows);
1608 }
1609
1610 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1611  * function.
1612  */
1613 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1614 {
1615         list_del(&flow->unready);
1616         flow_flag_clear(flow, NOT_READY);
1617 }
1618
1619 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1620 {
1621         struct mlx5_rep_uplink_priv *uplink_priv;
1622         struct mlx5e_rep_priv *rpriv;
1623         struct mlx5_eswitch *esw;
1624
1625         esw = flow->priv->mdev->priv.eswitch;
1626         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1627         uplink_priv = &rpriv->uplink_priv;
1628
1629         mutex_lock(&uplink_priv->unready_flows_lock);
1630         unready_flow_add(flow, &uplink_priv->unready_flows);
1631         mutex_unlock(&uplink_priv->unready_flows_lock);
1632 }
1633
1634 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1635 {
1636         struct mlx5_rep_uplink_priv *uplink_priv;
1637         struct mlx5e_rep_priv *rpriv;
1638         struct mlx5_eswitch *esw;
1639
1640         esw = flow->priv->mdev->priv.eswitch;
1641         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1642         uplink_priv = &rpriv->uplink_priv;
1643
1644         mutex_lock(&uplink_priv->unready_flows_lock);
1645         if (flow_flag_test(flow, NOT_READY))
1646                 unready_flow_del(flow);
1647         mutex_unlock(&uplink_priv->unready_flows_lock);
1648 }
1649
1650 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1651 {
1652         struct mlx5_core_dev *out_mdev, *route_mdev;
1653         struct mlx5e_priv *out_priv, *route_priv;
1654
1655         out_priv = netdev_priv(out_dev);
1656         out_mdev = out_priv->mdev;
1657         route_priv = netdev_priv(route_dev);
1658         route_mdev = route_priv->mdev;
1659
1660         if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1661                 return false;
1662
1663         if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1664             route_mdev->coredev_type != MLX5_COREDEV_SF)
1665                 return false;
1666
1667         return mlx5e_same_hw_devs(out_priv, route_priv);
1668 }
1669
1670 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1671 {
1672         struct mlx5e_priv *out_priv, *route_priv;
1673         struct mlx5_core_dev *route_mdev;
1674         struct mlx5_devcom_comp_dev *pos;
1675         struct mlx5_eswitch *esw;
1676         u16 vhca_id;
1677         int err;
1678
1679         out_priv = netdev_priv(out_dev);
1680         esw = out_priv->mdev->priv.eswitch;
1681         route_priv = netdev_priv(route_dev);
1682         route_mdev = route_priv->mdev;
1683
1684         vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1685         err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1686         if (!err)
1687                 return err;
1688
1689         if (!mlx5_lag_is_active(out_priv->mdev))
1690                 return err;
1691
1692         rcu_read_lock();
1693         err = -ENODEV;
1694         mlx5_devcom_for_each_peer_entry_rcu(esw->devcom, esw, pos) {
1695                 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1696                 if (!err)
1697                         break;
1698         }
1699         rcu_read_unlock();
1700
1701         return err;
1702 }
1703
1704 static int
1705 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1706 {
1707         if (!(actions &
1708               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1709                 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1710                 return -EOPNOTSUPP;
1711         }
1712
1713         if (!(~actions &
1714               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1715                 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1716                 return -EOPNOTSUPP;
1717         }
1718
1719         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1720             actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1721                 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1722                 return -EOPNOTSUPP;
1723         }
1724
1725         return 0;
1726 }
1727
1728 static bool
1729 has_encap_dests(struct mlx5_flow_attr *attr)
1730 {
1731         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
1732         int out_index;
1733
1734         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1735                 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1736                         return true;
1737
1738         return false;
1739 }
1740
1741 static int
1742 post_process_attr(struct mlx5e_tc_flow *flow,
1743                   struct mlx5_flow_attr *attr,
1744                   struct netlink_ext_ack *extack)
1745 {
1746         bool vf_tun;
1747         int err = 0;
1748
1749         err = verify_attr_actions(attr->action, extack);
1750         if (err)
1751                 goto err_out;
1752
1753         if (mlx5e_is_eswitch_flow(flow) && has_encap_dests(attr)) {
1754                 err = mlx5e_tc_tun_encap_dests_set(flow->priv, flow, attr, extack, &vf_tun);
1755                 if (err)
1756                         goto err_out;
1757         }
1758
1759         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1760                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr);
1761                 if (err)
1762                         goto err_out;
1763         }
1764
1765         if (attr->branch_true &&
1766             attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1767                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_true);
1768                 if (err)
1769                         goto err_out;
1770         }
1771
1772         if (attr->branch_false &&
1773             attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1774                 err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_false);
1775                 if (err)
1776                         goto err_out;
1777         }
1778
1779         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1780                 err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1781                 if (err)
1782                         goto err_out;
1783         }
1784
1785 err_out:
1786         return err;
1787 }
1788
1789 static int
1790 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1791                       struct mlx5e_tc_flow *flow,
1792                       struct netlink_ext_ack *extack)
1793 {
1794         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1795         struct mlx5e_tc_flow_parse_attr *parse_attr;
1796         struct mlx5_flow_attr *attr = flow->attr;
1797         struct mlx5_esw_flow_attr *esw_attr;
1798         u32 max_prio, max_chain;
1799         int err = 0;
1800
1801         parse_attr = attr->parse_attr;
1802         esw_attr = attr->esw_attr;
1803
1804         /* We check chain range only for tc flows.
1805          * For ft flows, we checked attr->chain was originally 0 and set it to
1806          * FDB_FT_CHAIN which is outside tc range.
1807          * See mlx5e_rep_setup_ft_cb().
1808          */
1809         max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1810         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1811                 NL_SET_ERR_MSG_MOD(extack,
1812                                    "Requested chain is out of supported range");
1813                 err = -EOPNOTSUPP;
1814                 goto err_out;
1815         }
1816
1817         max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1818         if (attr->prio > max_prio) {
1819                 NL_SET_ERR_MSG_MOD(extack,
1820                                    "Requested priority is out of supported range");
1821                 err = -EOPNOTSUPP;
1822                 goto err_out;
1823         }
1824
1825         if (flow_flag_test(flow, TUN_RX)) {
1826                 err = mlx5e_attach_decap_route(priv, flow);
1827                 if (err)
1828                         goto err_out;
1829
1830                 if (!attr->chain && esw_attr->int_port &&
1831                     attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1832                         /* If decap route device is internal port, change the
1833                          * source vport value in reg_c0 back to uplink just in
1834                          * case the rule performs goto chain > 0. If we have a miss
1835                          * on chain > 0 we want the metadata regs to hold the
1836                          * chain id so SW will resume handling of this packet
1837                          * from the proper chain.
1838                          */
1839                         u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1840                                                                         esw_attr->in_rep->vport);
1841
1842                         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1843                                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1844                                                         metadata);
1845                         if (err)
1846                                 goto err_out;
1847
1848                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1849                 }
1850         }
1851
1852         if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1853                 err = mlx5e_attach_decap(priv, flow, extack);
1854                 if (err)
1855                         goto err_out;
1856         }
1857
1858         if (netif_is_ovs_master(parse_attr->filter_dev)) {
1859                 struct mlx5e_tc_int_port *int_port;
1860
1861                 if (attr->chain) {
1862                         NL_SET_ERR_MSG_MOD(extack,
1863                                            "Internal port rule is only supported on chain 0");
1864                         err = -EOPNOTSUPP;
1865                         goto err_out;
1866                 }
1867
1868                 if (attr->dest_chain) {
1869                         NL_SET_ERR_MSG_MOD(extack,
1870                                            "Internal port rule offload doesn't support goto action");
1871                         err = -EOPNOTSUPP;
1872                         goto err_out;
1873                 }
1874
1875                 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1876                                                  parse_attr->filter_dev->ifindex,
1877                                                  flow_flag_test(flow, EGRESS) ?
1878                                                  MLX5E_TC_INT_PORT_EGRESS :
1879                                                  MLX5E_TC_INT_PORT_INGRESS);
1880                 if (IS_ERR(int_port)) {
1881                         err = PTR_ERR(int_port);
1882                         goto err_out;
1883                 }
1884
1885                 esw_attr->int_port = int_port;
1886         }
1887
1888         err = post_process_attr(flow, attr, extack);
1889         if (err)
1890                 goto err_out;
1891
1892         err = mlx5e_tc_act_stats_add_flow(get_act_stats_handle(priv), flow);
1893         if (err)
1894                 goto err_out;
1895
1896         /* we get here if one of the following takes place:
1897          * (1) there's no error
1898          * (2) there's an encap action and we don't have valid neigh
1899          */
1900         if (flow_flag_test(flow, SLOW))
1901                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1902         else
1903                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1904
1905         if (IS_ERR(flow->rule[0])) {
1906                 err = PTR_ERR(flow->rule[0]);
1907                 goto err_out;
1908         }
1909         flow_flag_set(flow, OFFLOADED);
1910
1911         return 0;
1912
1913 err_out:
1914         flow_flag_set(flow, FAILED);
1915         return err;
1916 }
1917
1918 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1919 {
1920         struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
1921         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1922                                        spec->match_value,
1923                                        misc_parameters_3);
1924         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1925                                              headers_v,
1926                                              geneve_tlv_option_0_data);
1927
1928         return !!geneve_tlv_opt_0_data;
1929 }
1930
1931 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
1932 {
1933         if (!attr)
1934                 return;
1935
1936         mlx5_free_flow_attr_actions(flow, attr);
1937         kvfree(attr->parse_attr);
1938         kfree(attr);
1939 }
1940
1941 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1942                                   struct mlx5e_tc_flow *flow)
1943 {
1944         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1945         struct mlx5_flow_attr *attr = flow->attr;
1946
1947         mlx5e_put_flow_tunnel_id(flow);
1948
1949         remove_unready_flow(flow);
1950
1951         if (mlx5e_is_offloaded_flow(flow)) {
1952                 if (flow_flag_test(flow, SLOW))
1953                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
1954                 else
1955                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1956         }
1957         complete_all(&flow->del_hw_done);
1958
1959         if (mlx5_flow_has_geneve_opt(flow))
1960                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1961
1962         if (flow->decap_route)
1963                 mlx5e_detach_decap_route(priv, flow);
1964
1965         mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
1966
1967         if (flow_flag_test(flow, L3_TO_L2_DECAP))
1968                 mlx5e_detach_decap(priv, flow);
1969
1970         mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow);
1971
1972         free_flow_post_acts(flow);
1973         mlx5_free_flow_attr_actions(flow, attr);
1974
1975         kvfree(attr->esw_attr->rx_tun_attr);
1976         kvfree(attr->parse_attr);
1977         kfree(flow->attr);
1978 }
1979
1980 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1981 {
1982         struct mlx5_flow_attr *attr;
1983
1984         attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
1985         return attr->counter;
1986 }
1987
1988 /* Iterate over tmp_list of flows attached to flow_list head. */
1989 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1990 {
1991         struct mlx5e_tc_flow *flow, *tmp;
1992
1993         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1994                 mlx5e_flow_put(priv, flow);
1995 }
1996
1997 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow,
1998                                        int peer_index)
1999 {
2000         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
2001         struct mlx5e_tc_flow *peer_flow;
2002         struct mlx5e_tc_flow *tmp;
2003
2004         if (!flow_flag_test(flow, ESWITCH) ||
2005             !flow_flag_test(flow, DUP))
2006                 return;
2007
2008         mutex_lock(&esw->offloads.peer_mutex);
2009         list_del(&flow->peer[peer_index]);
2010         mutex_unlock(&esw->offloads.peer_mutex);
2011
2012         list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) {
2013                 if (peer_index != mlx5_get_dev_index(peer_flow->priv->mdev))
2014                         continue;
2015                 if (refcount_dec_and_test(&peer_flow->refcnt)) {
2016                         mlx5e_tc_del_fdb_flow(peer_flow->priv, peer_flow);
2017                         list_del(&peer_flow->peer_flows);
2018                         kfree(peer_flow);
2019                 }
2020         }
2021
2022         if (list_empty(&flow->peer_flows))
2023                 flow_flag_clear(flow, DUP);
2024 }
2025
2026 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow)
2027 {
2028         int i;
2029
2030         for (i = 0; i < MLX5_MAX_PORTS; i++) {
2031                 if (i == mlx5_get_dev_index(flow->priv->mdev))
2032                         continue;
2033                 mlx5e_tc_del_fdb_peer_flow(flow, i);
2034         }
2035 }
2036
2037 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2038                               struct mlx5e_tc_flow *flow)
2039 {
2040         if (mlx5e_is_eswitch_flow(flow)) {
2041                 struct mlx5_devcom_comp_dev *devcom = flow->priv->mdev->priv.eswitch->devcom;
2042
2043                 if (!mlx5_devcom_for_each_peer_begin(devcom)) {
2044                         mlx5e_tc_del_fdb_flow(priv, flow);
2045                         return;
2046                 }
2047
2048                 mlx5e_tc_del_fdb_peers_flow(flow);
2049                 mlx5_devcom_for_each_peer_end(devcom);
2050                 mlx5e_tc_del_fdb_flow(priv, flow);
2051         } else {
2052                 mlx5e_tc_del_nic_flow(priv, flow);
2053         }
2054 }
2055
2056 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2057 {
2058         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2059         struct flow_action *flow_action = &rule->action;
2060         const struct flow_action_entry *act;
2061         int i;
2062
2063         if (chain)
2064                 return false;
2065
2066         flow_action_for_each(i, act, flow_action) {
2067                 switch (act->id) {
2068                 case FLOW_ACTION_GOTO:
2069                         return true;
2070                 case FLOW_ACTION_SAMPLE:
2071                         return true;
2072                 default:
2073                         continue;
2074                 }
2075         }
2076
2077         return false;
2078 }
2079
2080 static int
2081 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2082                                     struct flow_dissector_key_enc_opts *opts,
2083                                     struct netlink_ext_ack *extack,
2084                                     bool *dont_care)
2085 {
2086         struct geneve_opt *opt;
2087         int off = 0;
2088
2089         *dont_care = true;
2090
2091         while (opts->len > off) {
2092                 opt = (struct geneve_opt *)&opts->data[off];
2093
2094                 if (!(*dont_care) || opt->opt_class || opt->type ||
2095                     memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2096                         *dont_care = false;
2097
2098                         if (opt->opt_class != htons(U16_MAX) ||
2099                             opt->type != U8_MAX) {
2100                                 NL_SET_ERR_MSG_MOD(extack,
2101                                                    "Partial match of tunnel options in chain > 0 isn't supported");
2102                                 netdev_warn(priv->netdev,
2103                                             "Partial match of tunnel options in chain > 0 isn't supported");
2104                                 return -EOPNOTSUPP;
2105                         }
2106                 }
2107
2108                 off += sizeof(struct geneve_opt) + opt->length * 4;
2109         }
2110
2111         return 0;
2112 }
2113
2114 #define COPY_DISSECTOR(rule, diss_key, dst)\
2115 ({ \
2116         struct flow_rule *__rule = (rule);\
2117         typeof(dst) __dst = dst;\
2118 \
2119         memcpy(__dst,\
2120                skb_flow_dissector_target(__rule->match.dissector,\
2121                                          diss_key,\
2122                                          __rule->match.key),\
2123                sizeof(*__dst));\
2124 })
2125
2126 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2127                                     struct mlx5e_tc_flow *flow,
2128                                     struct flow_cls_offload *f,
2129                                     struct net_device *filter_dev)
2130 {
2131         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2132         struct netlink_ext_ack *extack = f->common.extack;
2133         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2134         struct flow_match_enc_opts enc_opts_match;
2135         struct tunnel_match_enc_opts tun_enc_opts;
2136         struct mlx5_rep_uplink_priv *uplink_priv;
2137         struct mlx5_flow_attr *attr = flow->attr;
2138         struct mlx5e_rep_priv *uplink_rpriv;
2139         struct tunnel_match_key tunnel_key;
2140         bool enc_opts_is_dont_care = true;
2141         u32 tun_id, enc_opts_id = 0;
2142         struct mlx5_eswitch *esw;
2143         u32 value, mask;
2144         int err;
2145
2146         esw = priv->mdev->priv.eswitch;
2147         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2148         uplink_priv = &uplink_rpriv->uplink_priv;
2149
2150         memset(&tunnel_key, 0, sizeof(tunnel_key));
2151         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2152                        &tunnel_key.enc_control);
2153         if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2154                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2155                                &tunnel_key.enc_ipv4);
2156         else
2157                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2158                                &tunnel_key.enc_ipv6);
2159         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2160         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2161                        &tunnel_key.enc_tp);
2162         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2163                        &tunnel_key.enc_key_id);
2164         tunnel_key.filter_ifindex = filter_dev->ifindex;
2165
2166         err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2167         if (err)
2168                 return err;
2169
2170         flow_rule_match_enc_opts(rule, &enc_opts_match);
2171         err = enc_opts_is_dont_care_or_full_match(priv,
2172                                                   enc_opts_match.mask,
2173                                                   extack,
2174                                                   &enc_opts_is_dont_care);
2175         if (err)
2176                 goto err_enc_opts;
2177
2178         if (!enc_opts_is_dont_care) {
2179                 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2180                 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2181                        sizeof(*enc_opts_match.key));
2182                 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2183                        sizeof(*enc_opts_match.mask));
2184
2185                 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2186                                   &tun_enc_opts, &enc_opts_id);
2187                 if (err)
2188                         goto err_enc_opts;
2189         }
2190
2191         value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2192         mask = enc_opts_id ? TUNNEL_ID_MASK :
2193                              (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2194
2195         if (attr->chain) {
2196                 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2197                                             TUNNEL_TO_REG, value, mask);
2198         } else {
2199                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2200                 err = mlx5e_tc_match_to_reg_set(priv->mdev,
2201                                                 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2202                                                 TUNNEL_TO_REG, value);
2203                 if (err)
2204                         goto err_set;
2205
2206                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2207         }
2208
2209         flow->attr->tunnel_id = value;
2210         return 0;
2211
2212 err_set:
2213         if (enc_opts_id)
2214                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2215                                enc_opts_id);
2216 err_enc_opts:
2217         mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2218         return err;
2219 }
2220
2221 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2222 {
2223         u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2224         u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2225         struct mlx5_rep_uplink_priv *uplink_priv;
2226         struct mlx5e_rep_priv *uplink_rpriv;
2227         struct mlx5_eswitch *esw;
2228
2229         esw = flow->priv->mdev->priv.eswitch;
2230         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2231         uplink_priv = &uplink_rpriv->uplink_priv;
2232
2233         if (tun_id)
2234                 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2235         if (enc_opts_id)
2236                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2237                                enc_opts_id);
2238 }
2239
2240 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2241                             struct flow_match_basic *match, bool outer,
2242                             void *headers_c, void *headers_v)
2243 {
2244         bool ip_version_cap;
2245
2246         ip_version_cap = outer ?
2247                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2248                                           ft_field_support.outer_ip_version) :
2249                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2250                                           ft_field_support.inner_ip_version);
2251
2252         if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2253             (match->key->n_proto == htons(ETH_P_IP) ||
2254              match->key->n_proto == htons(ETH_P_IPV6))) {
2255                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2257                          match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2258         } else {
2259                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2260                          ntohs(match->mask->n_proto));
2261                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2262                          ntohs(match->key->n_proto));
2263         }
2264 }
2265
2266 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2267 {
2268         void *headers_v;
2269         u16 ethertype;
2270         u8 ip_version;
2271
2272         if (outer)
2273                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2274         else
2275                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2276
2277         ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2278         /* Return ip_version converted from ethertype anyway */
2279         if (!ip_version) {
2280                 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2281                 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2282                         ip_version = 4;
2283                 else if (ethertype == ETH_P_IPV6)
2284                         ip_version = 6;
2285         }
2286         return ip_version;
2287 }
2288
2289 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2290  * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2291  *      +---------+----------------------------------------+
2292  *      |Arriving |         Arriving Outer Header          |
2293  *      |   Inner +---------+---------+---------+----------+
2294  *      |  Header | Not-ECT | ECT(0)  | ECT(1)  |   CE     |
2295  *      +---------+---------+---------+---------+----------+
2296  *      | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop>   |
2297  *      |  ECT(0) |  ECT(0) | ECT(0)  | ECT(1)  |   CE*    |
2298  *      |  ECT(1) |  ECT(1) | ECT(1)  | ECT(1)* |   CE*    |
2299  *      |    CE   |   CE    |  CE     | CE      |   CE     |
2300  *      +---------+---------+---------+---------+----------+
2301  *
2302  * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2303  * the inner ip_ecn value before hardware decap action.
2304  *
2305  * Cells marked are changed from original inner packet ip_ecn value during decap, and
2306  * so matching those values on inner ip_ecn before decap will fail.
2307  *
2308  * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2309  * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2310  * and such we can drop the inner ip_ecn=CE match.
2311  */
2312
2313 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2314                                       struct flow_cls_offload *f,
2315                                       bool *match_inner_ecn)
2316 {
2317         u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2318         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2319         struct netlink_ext_ack *extack = f->common.extack;
2320         struct flow_match_ip match;
2321
2322         *match_inner_ecn = true;
2323
2324         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2325                 flow_rule_match_enc_ip(rule, &match);
2326                 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2327                 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2328         }
2329
2330         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2331                 flow_rule_match_ip(rule, &match);
2332                 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2333                 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2334         }
2335
2336         if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2337                 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2338                 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2339                 return -EOPNOTSUPP;
2340         }
2341
2342         if (!outer_ecn_mask) {
2343                 if (!inner_ecn_mask)
2344                         return 0;
2345
2346                 NL_SET_ERR_MSG_MOD(extack,
2347                                    "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2348                 netdev_warn(priv->netdev,
2349                             "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2350                 return -EOPNOTSUPP;
2351         }
2352
2353         if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2354                 NL_SET_ERR_MSG_MOD(extack,
2355                                    "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2356                 netdev_warn(priv->netdev,
2357                             "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2358                 return -EOPNOTSUPP;
2359         }
2360
2361         if (!inner_ecn_mask)
2362                 return 0;
2363
2364         /* Both inner and outer have full mask on ecn */
2365
2366         if (outer_ecn_key == INET_ECN_ECT_1) {
2367                 /* inner ecn might change by DECAP action */
2368
2369                 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2370                 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2371                 return -EOPNOTSUPP;
2372         }
2373
2374         if (outer_ecn_key != INET_ECN_CE)
2375                 return 0;
2376
2377         if (inner_ecn_key != INET_ECN_CE) {
2378                 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2379                 NL_SET_ERR_MSG_MOD(extack,
2380                                    "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2381                 netdev_warn(priv->netdev,
2382                             "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2383                 return -EOPNOTSUPP;
2384         }
2385
2386         /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2387          * drop match on inner ecn
2388          */
2389         *match_inner_ecn = false;
2390
2391         return 0;
2392 }
2393
2394 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2395                              struct mlx5e_tc_flow *flow,
2396                              struct mlx5_flow_spec *spec,
2397                              struct flow_cls_offload *f,
2398                              struct net_device *filter_dev,
2399                              u8 *match_level,
2400                              bool *match_inner)
2401 {
2402         struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2403         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2404         struct netlink_ext_ack *extack = f->common.extack;
2405         bool needs_mapping, sets_mapping;
2406         int err;
2407
2408         if (!mlx5e_is_eswitch_flow(flow)) {
2409                 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2410                 return -EOPNOTSUPP;
2411         }
2412
2413         needs_mapping = !!flow->attr->chain;
2414         sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2415         *match_inner = !needs_mapping;
2416
2417         if ((needs_mapping || sets_mapping) &&
2418             !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2419                 NL_SET_ERR_MSG_MOD(extack,
2420                                    "Chains on tunnel devices isn't supported without register loopback support");
2421                 netdev_warn(priv->netdev,
2422                             "Chains on tunnel devices isn't supported without register loopback support");
2423                 return -EOPNOTSUPP;
2424         }
2425
2426         if (!flow->attr->chain) {
2427                 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2428                                          match_level);
2429                 if (err) {
2430                         NL_SET_ERR_MSG_MOD(extack,
2431                                            "Failed to parse tunnel attributes");
2432                         netdev_warn(priv->netdev,
2433                                     "Failed to parse tunnel attributes");
2434                         return err;
2435                 }
2436
2437                 /* With mpls over udp we decapsulate using packet reformat
2438                  * object
2439                  */
2440                 if (!netif_is_bareudp(filter_dev))
2441                         flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2442                 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2443                 if (err)
2444                         return err;
2445         } else if (tunnel) {
2446                 struct mlx5_flow_spec *tmp_spec;
2447
2448                 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2449                 if (!tmp_spec) {
2450                         NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for tunnel tmp spec");
2451                         netdev_warn(priv->netdev, "Failed to allocate memory for tunnel tmp spec");
2452                         return -ENOMEM;
2453                 }
2454                 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2455
2456                 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2457                 if (err) {
2458                         kvfree(tmp_spec);
2459                         NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2460                         netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2461                         return err;
2462                 }
2463                 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2464                 kvfree(tmp_spec);
2465                 if (err)
2466                         return err;
2467         }
2468
2469         if (!needs_mapping && !sets_mapping)
2470                 return 0;
2471
2472         return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2473 }
2474
2475 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2476 {
2477         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2478                             inner_headers);
2479 }
2480
2481 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2482 {
2483         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2484                             inner_headers);
2485 }
2486
2487 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2488 {
2489         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2490                             outer_headers);
2491 }
2492
2493 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2494 {
2495         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2496                             outer_headers);
2497 }
2498
2499 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2500 {
2501         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2502                 get_match_inner_headers_value(spec) :
2503                 get_match_outer_headers_value(spec);
2504 }
2505
2506 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2507 {
2508         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2509                 get_match_inner_headers_criteria(spec) :
2510                 get_match_outer_headers_criteria(spec);
2511 }
2512
2513 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2514                                    struct flow_cls_offload *f)
2515 {
2516         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2517         struct netlink_ext_ack *extack = f->common.extack;
2518         struct net_device *ingress_dev;
2519         struct flow_match_meta match;
2520
2521         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2522                 return 0;
2523
2524         flow_rule_match_meta(rule, &match);
2525
2526         if (match.mask->l2_miss) {
2527                 NL_SET_ERR_MSG_MOD(f->common.extack, "Can't match on \"l2_miss\"");
2528                 return -EOPNOTSUPP;
2529         }
2530
2531         if (!match.mask->ingress_ifindex)
2532                 return 0;
2533
2534         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2535                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2536                 return -EOPNOTSUPP;
2537         }
2538
2539         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2540                                          match.key->ingress_ifindex);
2541         if (!ingress_dev) {
2542                 NL_SET_ERR_MSG_MOD(extack,
2543                                    "Can't find the ingress port to match on");
2544                 return -ENOENT;
2545         }
2546
2547         if (ingress_dev != filter_dev) {
2548                 NL_SET_ERR_MSG_MOD(extack,
2549                                    "Can't match on the ingress filter port");
2550                 return -EOPNOTSUPP;
2551         }
2552
2553         return 0;
2554 }
2555
2556 static bool skip_key_basic(struct net_device *filter_dev,
2557                            struct flow_cls_offload *f)
2558 {
2559         /* When doing mpls over udp decap, the user needs to provide
2560          * MPLS_UC as the protocol in order to be able to match on mpls
2561          * label fields.  However, the actual ethertype is IP so we want to
2562          * avoid matching on this, otherwise we'll fail the match.
2563          */
2564         if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2565                 return true;
2566
2567         return false;
2568 }
2569
2570 static int __parse_cls_flower(struct mlx5e_priv *priv,
2571                               struct mlx5e_tc_flow *flow,
2572                               struct mlx5_flow_spec *spec,
2573                               struct flow_cls_offload *f,
2574                               struct net_device *filter_dev,
2575                               u8 *inner_match_level, u8 *outer_match_level)
2576 {
2577         struct netlink_ext_ack *extack = f->common.extack;
2578         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2579                                        outer_headers);
2580         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2581                                        outer_headers);
2582         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2583                                     misc_parameters);
2584         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2585                                     misc_parameters);
2586         void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2587                                     misc_parameters_3);
2588         void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2589                                     misc_parameters_3);
2590         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2591         struct flow_dissector *dissector = rule->match.dissector;
2592         enum fs_flow_table_type fs_type;
2593         bool match_inner_ecn = true;
2594         u16 addr_type = 0;
2595         u8 ip_proto = 0;
2596         u8 *match_level;
2597         int err;
2598
2599         fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2600         match_level = outer_match_level;
2601
2602         if (dissector->used_keys &
2603             ~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
2604               BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2605               BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2606               BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2607               BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
2608               BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
2609               BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2610               BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2611               BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
2612               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2613               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2614               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2615               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS)     |
2616               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2617               BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
2618               BIT_ULL(FLOW_DISSECTOR_KEY_IP)  |
2619               BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
2620               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
2621               BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2622               BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
2623               BIT_ULL(FLOW_DISSECTOR_KEY_MPLS))) {
2624                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2625                 netdev_dbg(priv->netdev, "Unsupported key used: 0x%llx\n",
2626                            dissector->used_keys);
2627                 return -EOPNOTSUPP;
2628         }
2629
2630         if (mlx5e_get_tc_tun(filter_dev)) {
2631                 bool match_inner = false;
2632
2633                 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2634                                         outer_match_level, &match_inner);
2635                 if (err)
2636                         return err;
2637
2638                 if (match_inner) {
2639                         /* header pointers should point to the inner headers
2640                          * if the packet was decapsulated already.
2641                          * outer headers are set by parse_tunnel_attr.
2642                          */
2643                         match_level = inner_match_level;
2644                         headers_c = get_match_inner_headers_criteria(spec);
2645                         headers_v = get_match_inner_headers_value(spec);
2646                 }
2647
2648                 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2649                 if (err)
2650                         return err;
2651         }
2652
2653         err = mlx5e_flower_parse_meta(filter_dev, f);
2654         if (err)
2655                 return err;
2656
2657         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2658             !skip_key_basic(filter_dev, f)) {
2659                 struct flow_match_basic match;
2660
2661                 flow_rule_match_basic(rule, &match);
2662                 mlx5e_tc_set_ethertype(priv->mdev, &match,
2663                                        match_level == outer_match_level,
2664                                        headers_c, headers_v);
2665
2666                 if (match.mask->n_proto)
2667                         *match_level = MLX5_MATCH_L2;
2668         }
2669         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2670             is_vlan_dev(filter_dev)) {
2671                 struct flow_dissector_key_vlan filter_dev_mask;
2672                 struct flow_dissector_key_vlan filter_dev_key;
2673                 struct flow_match_vlan match;
2674
2675                 if (is_vlan_dev(filter_dev)) {
2676                         match.key = &filter_dev_key;
2677                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2678                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2679                         match.key->vlan_priority = 0;
2680                         match.mask = &filter_dev_mask;
2681                         memset(match.mask, 0xff, sizeof(*match.mask));
2682                         match.mask->vlan_priority = 0;
2683                 } else {
2684                         flow_rule_match_vlan(rule, &match);
2685                 }
2686                 if (match.mask->vlan_id ||
2687                     match.mask->vlan_priority ||
2688                     match.mask->vlan_tpid) {
2689                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2690                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2691                                          svlan_tag, 1);
2692                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2693                                          svlan_tag, 1);
2694                         } else {
2695                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2696                                          cvlan_tag, 1);
2697                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2698                                          cvlan_tag, 1);
2699                         }
2700
2701                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2702                                  match.mask->vlan_id);
2703                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2704                                  match.key->vlan_id);
2705
2706                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2707                                  match.mask->vlan_priority);
2708                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2709                                  match.key->vlan_priority);
2710
2711                         *match_level = MLX5_MATCH_L2;
2712
2713                         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2714                             match.mask->vlan_eth_type &&
2715                             MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2716                                                     ft_field_support.outer_second_vid,
2717                                                     fs_type)) {
2718                                 MLX5_SET(fte_match_set_misc, misc_c,
2719                                          outer_second_cvlan_tag, 1);
2720                                 spec->match_criteria_enable |=
2721                                         MLX5_MATCH_MISC_PARAMETERS;
2722                         }
2723                 }
2724         } else if (*match_level != MLX5_MATCH_NONE) {
2725                 /* cvlan_tag enabled in match criteria and
2726                  * disabled in match value means both S & C tags
2727                  * don't exist (untagged of both)
2728                  */
2729                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2730                 *match_level = MLX5_MATCH_L2;
2731         }
2732
2733         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2734                 struct flow_match_vlan match;
2735
2736                 flow_rule_match_cvlan(rule, &match);
2737                 if (match.mask->vlan_id ||
2738                     match.mask->vlan_priority ||
2739                     match.mask->vlan_tpid) {
2740                         if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2741                                                      fs_type)) {
2742                                 NL_SET_ERR_MSG_MOD(extack,
2743                                                    "Matching on CVLAN is not supported");
2744                                 return -EOPNOTSUPP;
2745                         }
2746
2747                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2748                                 MLX5_SET(fte_match_set_misc, misc_c,
2749                                          outer_second_svlan_tag, 1);
2750                                 MLX5_SET(fte_match_set_misc, misc_v,
2751                                          outer_second_svlan_tag, 1);
2752                         } else {
2753                                 MLX5_SET(fte_match_set_misc, misc_c,
2754                                          outer_second_cvlan_tag, 1);
2755                                 MLX5_SET(fte_match_set_misc, misc_v,
2756                                          outer_second_cvlan_tag, 1);
2757                         }
2758
2759                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2760                                  match.mask->vlan_id);
2761                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2762                                  match.key->vlan_id);
2763                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2764                                  match.mask->vlan_priority);
2765                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2766                                  match.key->vlan_priority);
2767
2768                         *match_level = MLX5_MATCH_L2;
2769                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2770                 }
2771         }
2772
2773         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2774                 struct flow_match_eth_addrs match;
2775
2776                 flow_rule_match_eth_addrs(rule, &match);
2777                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2778                                              dmac_47_16),
2779                                 match.mask->dst);
2780                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2781                                              dmac_47_16),
2782                                 match.key->dst);
2783
2784                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2785                                              smac_47_16),
2786                                 match.mask->src);
2787                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2788                                              smac_47_16),
2789                                 match.key->src);
2790
2791                 if (!is_zero_ether_addr(match.mask->src) ||
2792                     !is_zero_ether_addr(match.mask->dst))
2793                         *match_level = MLX5_MATCH_L2;
2794         }
2795
2796         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2797                 struct flow_match_control match;
2798
2799                 flow_rule_match_control(rule, &match);
2800                 addr_type = match.key->addr_type;
2801
2802                 /* the HW doesn't support frag first/later */
2803                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2804                         NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
2805                         return -EOPNOTSUPP;
2806                 }
2807
2808                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2809                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2810                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2811                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2812
2813                         /* the HW doesn't need L3 inline to match on frag=no */
2814                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2815                                 *match_level = MLX5_MATCH_L2;
2816         /* ***  L2 attributes parsing up to here *** */
2817                         else
2818                                 *match_level = MLX5_MATCH_L3;
2819                 }
2820         }
2821
2822         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2823                 struct flow_match_basic match;
2824
2825                 flow_rule_match_basic(rule, &match);
2826                 ip_proto = match.key->ip_proto;
2827
2828                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2829                          match.mask->ip_proto);
2830                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2831                          match.key->ip_proto);
2832
2833                 if (match.mask->ip_proto)
2834                         *match_level = MLX5_MATCH_L3;
2835         }
2836
2837         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2838                 struct flow_match_ipv4_addrs match;
2839
2840                 flow_rule_match_ipv4_addrs(rule, &match);
2841                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2842                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2843                        &match.mask->src, sizeof(match.mask->src));
2844                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2845                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2846                        &match.key->src, sizeof(match.key->src));
2847                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2848                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2849                        &match.mask->dst, sizeof(match.mask->dst));
2850                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2851                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2852                        &match.key->dst, sizeof(match.key->dst));
2853
2854                 if (match.mask->src || match.mask->dst)
2855                         *match_level = MLX5_MATCH_L3;
2856         }
2857
2858         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2859                 struct flow_match_ipv6_addrs match;
2860
2861                 flow_rule_match_ipv6_addrs(rule, &match);
2862                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2863                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2864                        &match.mask->src, sizeof(match.mask->src));
2865                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2866                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2867                        &match.key->src, sizeof(match.key->src));
2868
2869                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2870                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2871                        &match.mask->dst, sizeof(match.mask->dst));
2872                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2873                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2874                        &match.key->dst, sizeof(match.key->dst));
2875
2876                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2877                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2878                         *match_level = MLX5_MATCH_L3;
2879         }
2880
2881         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2882                 struct flow_match_ip match;
2883
2884                 flow_rule_match_ip(rule, &match);
2885                 if (match_inner_ecn) {
2886                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2887                                  match.mask->tos & 0x3);
2888                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2889                                  match.key->tos & 0x3);
2890                 }
2891
2892                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2893                          match.mask->tos >> 2);
2894                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2895                          match.key->tos  >> 2);
2896
2897                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2898                          match.mask->ttl);
2899                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2900                          match.key->ttl);
2901
2902                 if (match.mask->ttl &&
2903                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2904                                                 ft_field_support.outer_ipv4_ttl)) {
2905                         NL_SET_ERR_MSG_MOD(extack,
2906                                            "Matching on TTL is not supported");
2907                         return -EOPNOTSUPP;
2908                 }
2909
2910                 if (match.mask->tos || match.mask->ttl)
2911                         *match_level = MLX5_MATCH_L3;
2912         }
2913
2914         /* ***  L3 attributes parsing up to here *** */
2915
2916         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2917                 struct flow_match_ports match;
2918
2919                 flow_rule_match_ports(rule, &match);
2920                 switch (ip_proto) {
2921                 case IPPROTO_TCP:
2922                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2923                                  tcp_sport, ntohs(match.mask->src));
2924                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2925                                  tcp_sport, ntohs(match.key->src));
2926
2927                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2928                                  tcp_dport, ntohs(match.mask->dst));
2929                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2930                                  tcp_dport, ntohs(match.key->dst));
2931                         break;
2932
2933                 case IPPROTO_UDP:
2934                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2935                                  udp_sport, ntohs(match.mask->src));
2936                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2937                                  udp_sport, ntohs(match.key->src));
2938
2939                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2940                                  udp_dport, ntohs(match.mask->dst));
2941                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2942                                  udp_dport, ntohs(match.key->dst));
2943                         break;
2944                 default:
2945                         NL_SET_ERR_MSG_MOD(extack,
2946                                            "Only UDP and TCP transports are supported for L4 matching");
2947                         netdev_err(priv->netdev,
2948                                    "Only UDP and TCP transport are supported\n");
2949                         return -EINVAL;
2950                 }
2951
2952                 if (match.mask->src || match.mask->dst)
2953                         *match_level = MLX5_MATCH_L4;
2954         }
2955
2956         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2957                 struct flow_match_tcp match;
2958
2959                 flow_rule_match_tcp(rule, &match);
2960                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2961                          ntohs(match.mask->flags));
2962                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2963                          ntohs(match.key->flags));
2964
2965                 if (match.mask->flags)
2966                         *match_level = MLX5_MATCH_L4;
2967         }
2968         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2969                 struct flow_match_icmp match;
2970
2971                 flow_rule_match_icmp(rule, &match);
2972                 switch (ip_proto) {
2973                 case IPPROTO_ICMP:
2974                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2975                               MLX5_FLEX_PROTO_ICMP)) {
2976                                 NL_SET_ERR_MSG_MOD(extack,
2977                                                    "Match on Flex protocols for ICMP is not supported");
2978                                 return -EOPNOTSUPP;
2979                         }
2980                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2981                                  match.mask->type);
2982                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2983                                  match.key->type);
2984                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2985                                  match.mask->code);
2986                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2987                                  match.key->code);
2988                         break;
2989                 case IPPROTO_ICMPV6:
2990                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
2991                               MLX5_FLEX_PROTO_ICMPV6)) {
2992                                 NL_SET_ERR_MSG_MOD(extack,
2993                                                    "Match on Flex protocols for ICMPV6 is not supported");
2994                                 return -EOPNOTSUPP;
2995                         }
2996                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2997                                  match.mask->type);
2998                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2999                                  match.key->type);
3000                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
3001                                  match.mask->code);
3002                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
3003                                  match.key->code);
3004                         break;
3005                 default:
3006                         NL_SET_ERR_MSG_MOD(extack,
3007                                            "Code and type matching only with ICMP and ICMPv6");
3008                         netdev_err(priv->netdev,
3009                                    "Code and type matching only with ICMP and ICMPv6\n");
3010                         return -EINVAL;
3011                 }
3012                 if (match.mask->code || match.mask->type) {
3013                         *match_level = MLX5_MATCH_L4;
3014                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3015                 }
3016         }
3017         /* Currently supported only for MPLS over UDP */
3018         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3019             !netif_is_bareudp(filter_dev)) {
3020                 NL_SET_ERR_MSG_MOD(extack,
3021                                    "Matching on MPLS is supported only for MPLS over UDP");
3022                 netdev_err(priv->netdev,
3023                            "Matching on MPLS is supported only for MPLS over UDP\n");
3024                 return -EOPNOTSUPP;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int parse_cls_flower(struct mlx5e_priv *priv,
3031                             struct mlx5e_tc_flow *flow,
3032                             struct mlx5_flow_spec *spec,
3033                             struct flow_cls_offload *f,
3034                             struct net_device *filter_dev)
3035 {
3036         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3037         struct netlink_ext_ack *extack = f->common.extack;
3038         struct mlx5_core_dev *dev = priv->mdev;
3039         struct mlx5_eswitch *esw = dev->priv.eswitch;
3040         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3041         struct mlx5_eswitch_rep *rep;
3042         bool is_eswitch_flow;
3043         int err;
3044
3045         inner_match_level = MLX5_MATCH_NONE;
3046         outer_match_level = MLX5_MATCH_NONE;
3047
3048         err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3049                                  &inner_match_level, &outer_match_level);
3050         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3051                                  outer_match_level : inner_match_level;
3052
3053         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3054         if (!err && is_eswitch_flow) {
3055                 rep = rpriv->rep;
3056                 if (rep->vport != MLX5_VPORT_UPLINK &&
3057                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3058                     esw->offloads.inline_mode < non_tunnel_match_level)) {
3059                         NL_SET_ERR_MSG_MOD(extack,
3060                                            "Flow is not offloaded due to min inline setting");
3061                         netdev_warn(priv->netdev,
3062                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3063                                     non_tunnel_match_level, esw->offloads.inline_mode);
3064                         return -EOPNOTSUPP;
3065                 }
3066         }
3067
3068         flow->attr->inner_match_level = inner_match_level;
3069         flow->attr->outer_match_level = outer_match_level;
3070
3071
3072         return err;
3073 }
3074
3075 struct mlx5_fields {
3076         u8  field;
3077         u8  field_bsize;
3078         u32 field_mask;
3079         u32 offset;
3080         u32 match_offset;
3081 };
3082
3083 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3084                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3085                  offsetof(struct pedit_headers, field) + (off), \
3086                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3087
3088 /* masked values are the same and there are no rewrites that do not have a
3089  * match.
3090  */
3091 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3092         type matchmaskx = *(type *)(matchmaskp); \
3093         type matchvalx = *(type *)(matchvalp); \
3094         type maskx = *(type *)(maskp); \
3095         type valx = *(type *)(valp); \
3096         \
3097         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3098                                                                  matchmaskx)); \
3099 })
3100
3101 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3102                          void *matchmaskp, u8 bsize)
3103 {
3104         bool same = false;
3105
3106         switch (bsize) {
3107         case 8:
3108                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3109                 break;
3110         case 16:
3111                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3112                 break;
3113         case 32:
3114                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3115                 break;
3116         }
3117
3118         return same;
3119 }
3120
3121 static struct mlx5_fields fields[] = {
3122         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3123         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3124         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3125         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3126         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
3127         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3128
3129         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
3130         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
3131         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3132         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3133
3134         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3135                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3136         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3137                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3138         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3139                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3140         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3141                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3142         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3143                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3144         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3145                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3146         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3147                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3148         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3149                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3150         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3151         OFFLOAD(IP_DSCP, 16,  0x0fc0, ip6, 0, ip_dscp),
3152
3153         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
3154         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
3155         /* in linux iphdr tcp_flags is 8 bits long */
3156         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
3157
3158         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3159         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
3160 };
3161
3162 static u32 mask_field_get(void *mask, struct mlx5_fields *f)
3163 {
3164         switch (f->field_bsize) {
3165         case 32:
3166                 return be32_to_cpu(*(__be32 *)mask) & f->field_mask;
3167         case 16:
3168                 return be16_to_cpu(*(__be16 *)mask) & (u16)f->field_mask;
3169         default:
3170                 return *(u8 *)mask & (u8)f->field_mask;
3171         }
3172 }
3173
3174 static void mask_field_clear(void *mask, struct mlx5_fields *f)
3175 {
3176         switch (f->field_bsize) {
3177         case 32:
3178                 *(__be32 *)mask &= ~cpu_to_be32(f->field_mask);
3179                 break;
3180         case 16:
3181                 *(__be16 *)mask &= ~cpu_to_be16((u16)f->field_mask);
3182                 break;
3183         default:
3184                 *(u8 *)mask &= ~(u8)f->field_mask;
3185                 break;
3186         }
3187 }
3188
3189 static int offload_pedit_fields(struct mlx5e_priv *priv,
3190                                 int namespace,
3191                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
3192                                 u32 *action_flags,
3193                                 struct netlink_ext_ack *extack)
3194 {
3195         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3196         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3197         void *headers_c, *headers_v, *action, *vals_p;
3198         struct mlx5e_tc_mod_hdr_acts *mod_acts;
3199         void *s_masks_p, *a_masks_p;
3200         int i, first, last, next_z;
3201         struct mlx5_fields *f;
3202         unsigned long mask;
3203         u32 s_mask, a_mask;
3204         u8 cmd;
3205
3206         mod_acts = &parse_attr->mod_hdr_acts;
3207         headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3208         headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3209
3210         set_masks = &hdrs[0].masks;
3211         add_masks = &hdrs[1].masks;
3212         set_vals = &hdrs[0].vals;
3213         add_vals = &hdrs[1].vals;
3214
3215         for (i = 0; i < ARRAY_SIZE(fields); i++) {
3216                 bool skip;
3217
3218                 f = &fields[i];
3219                 s_masks_p = (void *)set_masks + f->offset;
3220                 a_masks_p = (void *)add_masks + f->offset;
3221
3222                 s_mask = mask_field_get(s_masks_p, f);
3223                 a_mask = mask_field_get(a_masks_p, f);
3224
3225                 if (!s_mask && !a_mask) /* nothing to offload here */
3226                         continue;
3227
3228                 if (s_mask && a_mask) {
3229                         NL_SET_ERR_MSG_MOD(extack,
3230                                            "can't set and add to the same HW field");
3231                         netdev_warn(priv->netdev,
3232                                     "mlx5: can't set and add to the same HW field (%x)\n",
3233                                     f->field);
3234                         return -EOPNOTSUPP;
3235                 }
3236
3237                 skip = false;
3238                 if (s_mask) {
3239                         void *match_mask = headers_c + f->match_offset;
3240                         void *match_val = headers_v + f->match_offset;
3241
3242                         cmd  = MLX5_ACTION_TYPE_SET;
3243                         mask = s_mask;
3244                         vals_p = (void *)set_vals + f->offset;
3245                         /* don't rewrite if we have a match on the same value */
3246                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
3247                                          match_mask, f->field_bsize))
3248                                 skip = true;
3249                         /* clear to denote we consumed this field */
3250                         mask_field_clear(s_masks_p, f);
3251                 } else {
3252                         cmd  = MLX5_ACTION_TYPE_ADD;
3253                         mask = a_mask;
3254                         vals_p = (void *)add_vals + f->offset;
3255                         /* add 0 is no change */
3256                         if (!mask_field_get(vals_p, f))
3257                                 skip = true;
3258                         /* clear to denote we consumed this field */
3259                         mask_field_clear(a_masks_p, f);
3260                 }
3261                 if (skip)
3262                         continue;
3263
3264                 first = find_first_bit(&mask, f->field_bsize);
3265                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3266                 last  = find_last_bit(&mask, f->field_bsize);
3267                 if (first < next_z && next_z < last) {
3268                         NL_SET_ERR_MSG_MOD(extack,
3269                                            "rewrite of few sub-fields isn't supported");
3270                         netdev_warn(priv->netdev,
3271                                     "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3272                                     mask);
3273                         return -EOPNOTSUPP;
3274                 }
3275
3276                 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3277                 if (IS_ERR(action)) {
3278                         NL_SET_ERR_MSG_MOD(extack,
3279                                            "too many pedit actions, can't offload");
3280                         mlx5_core_warn(priv->mdev,
3281                                        "mlx5: parsed %d pedit actions, can't do more\n",
3282                                        mod_acts->num_actions);
3283                         return PTR_ERR(action);
3284                 }
3285
3286                 MLX5_SET(set_action_in, action, action_type, cmd);
3287                 MLX5_SET(set_action_in, action, field, f->field);
3288
3289                 if (cmd == MLX5_ACTION_TYPE_SET) {
3290                         unsigned long field_mask = f->field_mask;
3291                         int start;
3292
3293                         /* if field is bit sized it can start not from first bit */
3294                         start = find_first_bit(&field_mask, f->field_bsize);
3295
3296                         MLX5_SET(set_action_in, action, offset, first - start);
3297                         /* length is num of bits to be written, zero means length of 32 */
3298                         MLX5_SET(set_action_in, action, length, (last - first + 1));
3299                 }
3300
3301                 if (f->field_bsize == 32)
3302                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3303                 else if (f->field_bsize == 16)
3304                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3305                 else if (f->field_bsize == 8)
3306                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3307
3308                 ++mod_acts->num_actions;
3309         }
3310
3311         return 0;
3312 }
3313
3314 static const struct pedit_headers zero_masks = {};
3315
3316 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3317                                        struct mlx5e_tc_flow_parse_attr *parse_attr,
3318                                        struct netlink_ext_ack *extack)
3319 {
3320         struct pedit_headers *cmd_masks;
3321         u8 cmd;
3322
3323         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3324                 cmd_masks = &parse_attr->hdrs[cmd].masks;
3325                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3326                         NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3327                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3328                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3329                                        16, 1, cmd_masks, sizeof(zero_masks), true);
3330                         return -EOPNOTSUPP;
3331                 }
3332         }
3333
3334         return 0;
3335 }
3336
3337 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3338                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
3339                                  u32 *action_flags,
3340                                  struct netlink_ext_ack *extack)
3341 {
3342         int err;
3343
3344         err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3345         if (err)
3346                 goto out_dealloc_parsed_actions;
3347
3348         err = verify_offload_pedit_fields(priv, parse_attr, extack);
3349         if (err)
3350                 goto out_dealloc_parsed_actions;
3351
3352         return 0;
3353
3354 out_dealloc_parsed_actions:
3355         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3356         return err;
3357 }
3358
3359 struct ip_ttl_word {
3360         __u8    ttl;
3361         __u8    protocol;
3362         __sum16 check;
3363 };
3364
3365 struct ipv6_hoplimit_word {
3366         __be16  payload_len;
3367         __u8    nexthdr;
3368         __u8    hop_limit;
3369 };
3370
3371 static bool
3372 is_flow_action_modify_ip_header(struct flow_action *flow_action)
3373 {
3374         const struct flow_action_entry *act;
3375         u32 mask, offset;
3376         u8 htype;
3377         int i;
3378
3379         /* For IPv4 & IPv6 header check 4 byte word,
3380          * to determine that modified fields
3381          * are NOT ttl & hop_limit only.
3382          */
3383         flow_action_for_each(i, act, flow_action) {
3384                 if (act->id != FLOW_ACTION_MANGLE &&
3385                     act->id != FLOW_ACTION_ADD)
3386                         continue;
3387
3388                 htype = act->mangle.htype;
3389                 offset = act->mangle.offset;
3390                 mask = ~act->mangle.mask;
3391
3392                 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3393                         struct ip_ttl_word *ttl_word =
3394                                 (struct ip_ttl_word *)&mask;
3395
3396                         if (offset != offsetof(struct iphdr, ttl) ||
3397                             ttl_word->protocol ||
3398                             ttl_word->check)
3399                                 return true;
3400                 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3401                         struct ipv6_hoplimit_word *hoplimit_word =
3402                                 (struct ipv6_hoplimit_word *)&mask;
3403
3404                         if (offset != offsetof(struct ipv6hdr, payload_len) ||
3405                             hoplimit_word->payload_len ||
3406                             hoplimit_word->nexthdr)
3407                                 return true;
3408                 }
3409         }
3410
3411         return false;
3412 }
3413
3414 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3415                                           struct mlx5_flow_spec *spec,
3416                                           struct flow_action *flow_action,
3417                                           u32 actions,
3418                                           struct netlink_ext_ack *extack)
3419 {
3420         bool modify_ip_header;
3421         void *headers_c;
3422         void *headers_v;
3423         u16 ethertype;
3424         u8 ip_proto;
3425
3426         headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3427         headers_v = mlx5e_get_match_headers_value(actions, spec);
3428         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3429
3430         /* for non-IP we only re-write MACs, so we're okay */
3431         if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3432             ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3433                 goto out_ok;
3434
3435         modify_ip_header = is_flow_action_modify_ip_header(flow_action);
3436         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3437         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3438             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3439                 NL_SET_ERR_MSG_MOD(extack,
3440                                    "can't offload re-write of non TCP/UDP");
3441                 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3442                             ip_proto);
3443                 return false;
3444         }
3445
3446 out_ok:
3447         return true;
3448 }
3449
3450 static bool
3451 actions_match_supported_fdb(struct mlx5e_priv *priv,
3452                             struct mlx5e_tc_flow *flow,
3453                             struct netlink_ext_ack *extack)
3454 {
3455         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3456
3457         if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3458                 NL_SET_ERR_MSG_MOD(extack,
3459                                    "current firmware doesn't support split rule for port mirroring");
3460                 netdev_warn_once(priv->netdev,
3461                                  "current firmware doesn't support split rule for port mirroring\n");
3462                 return false;
3463         }
3464
3465         return true;
3466 }
3467
3468 static bool
3469 actions_match_supported(struct mlx5e_priv *priv,
3470                         struct flow_action *flow_action,
3471                         u32 actions,
3472                         struct mlx5e_tc_flow_parse_attr *parse_attr,
3473                         struct mlx5e_tc_flow *flow,
3474                         struct netlink_ext_ack *extack)
3475 {
3476         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3477             !modify_header_match_supported(priv, &parse_attr->spec, flow_action, actions,
3478                                            extack))
3479                 return false;
3480
3481         if (mlx5e_is_eswitch_flow(flow) &&
3482             !actions_match_supported_fdb(priv, flow, extack))
3483                 return false;
3484
3485         return true;
3486 }
3487
3488 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3489 {
3490         return priv->mdev == peer_priv->mdev;
3491 }
3492
3493 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3494 {
3495         struct mlx5_core_dev *fmdev, *pmdev;
3496         u64 fsystem_guid, psystem_guid;
3497
3498         fmdev = priv->mdev;
3499         pmdev = peer_priv->mdev;
3500
3501         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3502         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3503
3504         return (fsystem_guid == psystem_guid);
3505 }
3506
3507 static int
3508 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3509                                 struct mlx5e_tc_flow *flow,
3510                                 struct mlx5_flow_attr *attr,
3511                                 struct netlink_ext_ack *extack)
3512 {
3513         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3514         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3515         enum mlx5_flow_namespace_type ns_type;
3516         int err;
3517
3518         if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3519             !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3520                 return 0;
3521
3522         ns_type = mlx5e_get_flow_namespace(flow);
3523
3524         err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3525         if (err)
3526                 return err;
3527
3528         if (parse_attr->mod_hdr_acts.num_actions > 0)
3529                 return 0;
3530
3531         /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3532         attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3533         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3534
3535         if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3536                 return 0;
3537
3538         if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3539               (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3540                 attr->esw_attr->split_count = 0;
3541
3542         return 0;
3543 }
3544
3545 static struct mlx5_flow_attr*
3546 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3547                                    enum mlx5_flow_namespace_type ns_type)
3548 {
3549         struct mlx5e_tc_flow_parse_attr *parse_attr;
3550         u32 attr_sz = ns_to_attr_sz(ns_type);
3551         struct mlx5_flow_attr *attr2;
3552
3553         attr2 = mlx5_alloc_flow_attr(ns_type);
3554         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3555         if (!attr2 || !parse_attr) {
3556                 kvfree(parse_attr);
3557                 kfree(attr2);
3558                 return NULL;
3559         }
3560
3561         memcpy(attr2, attr, attr_sz);
3562         INIT_LIST_HEAD(&attr2->list);
3563         parse_attr->filter_dev = attr->parse_attr->filter_dev;
3564         attr2->action = 0;
3565         attr2->counter = NULL;
3566         attr2->tc_act_cookies_count = 0;
3567         attr2->flags = 0;
3568         attr2->parse_attr = parse_attr;
3569         attr2->dest_chain = 0;
3570         attr2->dest_ft = NULL;
3571         attr2->act_id_restore_rule = NULL;
3572         memset(&attr2->ct_attr, 0, sizeof(attr2->ct_attr));
3573
3574         if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3575                 attr2->esw_attr->out_count = 0;
3576                 attr2->esw_attr->split_count = 0;
3577         }
3578
3579         attr2->branch_true = NULL;
3580         attr2->branch_false = NULL;
3581         attr2->jumping_attr = NULL;
3582         return attr2;
3583 }
3584
3585 struct mlx5_flow_attr *
3586 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3587 {
3588         struct mlx5_esw_flow_attr *esw_attr;
3589         struct mlx5_flow_attr *attr;
3590         int i;
3591
3592         list_for_each_entry(attr, &flow->attrs, list) {
3593                 esw_attr = attr->esw_attr;
3594                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3595                         if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3596                                 return attr;
3597                 }
3598         }
3599
3600         return NULL;
3601 }
3602
3603 void
3604 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3605 {
3606         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3607         struct mlx5_flow_attr *attr;
3608
3609         list_for_each_entry(attr, &flow->attrs, list) {
3610                 if (list_is_last(&attr->list, &flow->attrs))
3611                         break;
3612
3613                 mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3614         }
3615 }
3616
3617 static void
3618 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3619 {
3620         struct mlx5_flow_attr *attr, *tmp;
3621
3622         list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3623                 if (list_is_last(&attr->list, &flow->attrs))
3624                         break;
3625
3626                 mlx5_free_flow_attr_actions(flow, attr);
3627
3628                 list_del(&attr->list);
3629                 kvfree(attr->parse_attr);
3630                 kfree(attr);
3631         }
3632 }
3633
3634 int
3635 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3636 {
3637         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3638         struct mlx5_flow_attr *attr;
3639         int err = 0;
3640
3641         list_for_each_entry(attr, &flow->attrs, list) {
3642                 if (list_is_last(&attr->list, &flow->attrs))
3643                         break;
3644
3645                 err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3646                 if (err)
3647                         break;
3648         }
3649
3650         return err;
3651 }
3652
3653 /* TC filter rule HW translation:
3654  *
3655  * +---------------------+
3656  * + ft prio (tc chain)  +
3657  * + original match      +
3658  * +---------------------+
3659  *           |
3660  *           | if multi table action
3661  *           |
3662  *           v
3663  * +---------------------+
3664  * + post act ft         |<----.
3665  * + match fte id        |     | split on multi table action
3666  * + do actions          |-----'
3667  * +---------------------+
3668  *           |
3669  *           |
3670  *           v
3671  * Do rest of the actions after last multi table action.
3672  */
3673 static int
3674 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3675 {
3676         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3677         struct mlx5_flow_attr *attr, *next_attr = NULL;
3678         struct mlx5e_post_act_handle *handle;
3679         int err;
3680
3681         /* This is going in reverse order as needed.
3682          * The first entry is the last attribute.
3683          */
3684         list_for_each_entry(attr, &flow->attrs, list) {
3685                 if (!next_attr) {
3686                         /* Set counter action on last post act rule. */
3687                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3688                 }
3689
3690                 if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3691                         err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3692                         if (err)
3693                                 goto out_free;
3694                 }
3695
3696                 /* Don't add post_act rule for first attr (last in the list).
3697                  * It's being handled by the caller.
3698                  */
3699                 if (list_is_last(&attr->list, &flow->attrs))
3700                         break;
3701
3702                 err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3703                 if (err)
3704                         goto out_free;
3705
3706                 err = post_process_attr(flow, attr, extack);
3707                 if (err)
3708                         goto out_free;
3709
3710                 handle = mlx5e_tc_post_act_add(post_act, attr);
3711                 if (IS_ERR(handle)) {
3712                         err = PTR_ERR(handle);
3713                         goto out_free;
3714                 }
3715
3716                 attr->post_act_handle = handle;
3717
3718                 if (attr->jumping_attr) {
3719                         err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3720                         if (err)
3721                                 goto out_free;
3722                 }
3723
3724                 next_attr = attr;
3725         }
3726
3727         if (flow_flag_test(flow, SLOW))
3728                 goto out;
3729
3730         err = mlx5e_tc_offload_flow_post_acts(flow);
3731         if (err)
3732                 goto out_free;
3733
3734 out:
3735         return 0;
3736
3737 out_free:
3738         free_flow_post_acts(flow);
3739         return err;
3740 }
3741
3742 static int
3743 set_branch_dest_ft(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr)
3744 {
3745         struct mlx5e_post_act *post_act = get_post_action(priv);
3746
3747         if (IS_ERR(post_act))
3748                 return PTR_ERR(post_act);
3749
3750         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3751         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3752
3753         return 0;
3754 }
3755
3756 static int
3757 alloc_branch_attr(struct mlx5e_tc_flow *flow,
3758                   struct mlx5e_tc_act_branch_ctrl *cond,
3759                   struct mlx5_flow_attr **cond_attr,
3760                   u32 *jump_count,
3761                   struct netlink_ext_ack *extack)
3762 {
3763         struct mlx5_flow_attr *attr;
3764         int err = 0;
3765
3766         *cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
3767                                                         mlx5e_get_flow_namespace(flow));
3768         if (!(*cond_attr))
3769                 return -ENOMEM;
3770
3771         attr = *cond_attr;
3772
3773         switch (cond->act_id) {
3774         case FLOW_ACTION_DROP:
3775                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3776                 break;
3777         case FLOW_ACTION_ACCEPT:
3778         case FLOW_ACTION_PIPE:
3779                 if (set_branch_dest_ft(flow->priv, attr))
3780                         goto out_err;
3781                 break;
3782         case FLOW_ACTION_JUMP:
3783                 if (*jump_count) {
3784                         NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
3785                         err = -EOPNOTSUPP;
3786                         goto out_err;
3787                 }
3788                 *jump_count = cond->extval;
3789                 if (set_branch_dest_ft(flow->priv, attr))
3790                         goto out_err;
3791                 break;
3792         default:
3793                 err = -EOPNOTSUPP;
3794                 goto out_err;
3795         }
3796
3797         return err;
3798 out_err:
3799         kfree(*cond_attr);
3800         *cond_attr = NULL;
3801         return err;
3802 }
3803
3804 static void
3805 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3806                struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
3807                struct mlx5e_tc_jump_state *jump_state)
3808 {
3809         if (!jump_state->jump_count)
3810                 return;
3811
3812         /* Single tc action can instantiate multiple offload actions (e.g. pedit)
3813          * Jump only over a tc action
3814          */
3815         if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
3816                 return;
3817
3818         jump_state->last_id = act->id;
3819         jump_state->last_index = act->hw_index;
3820
3821         /* nothing to do for intermediate actions */
3822         if (--jump_state->jump_count > 1)
3823                 return;
3824
3825         if (jump_state->jump_count == 1) { /* last action in the jump action list */
3826
3827                 /* create a new attribute after this action */
3828                 jump_state->jump_target = true;
3829
3830                 if (tc_act->is_terminating_action) { /* the branch ends here */
3831                         attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
3832                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3833                 } else { /* the branch continues executing the rest of the actions */
3834                         struct mlx5e_post_act *post_act;
3835
3836                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3837                         post_act = get_post_action(priv);
3838                         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3839                 }
3840         } else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
3841                 /* This is the post action for the jumping attribute (either red or green)
3842                  * Use the stored jumping_attr to set the post act id on the jumping attribute
3843                  */
3844                 attr->jumping_attr = jump_state->jumping_attr;
3845         }
3846 }
3847
3848 static int
3849 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3850                   struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
3851                   struct mlx5e_tc_jump_state *jump_state,
3852                   struct netlink_ext_ack *extack)
3853 {
3854         struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
3855         u32 jump_count = jump_state->jump_count;
3856         int err;
3857
3858         if (!tc_act->get_branch_ctrl)
3859                 return 0;
3860
3861         tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
3862
3863         err = alloc_branch_attr(flow, &cond_true,
3864                                 &attr->branch_true, &jump_count, extack);
3865         if (err)
3866                 goto out_err;
3867
3868         if (jump_count)
3869                 jump_state->jumping_attr = attr->branch_true;
3870
3871         err = alloc_branch_attr(flow, &cond_false,
3872                                 &attr->branch_false, &jump_count, extack);
3873         if (err)
3874                 goto err_branch_false;
3875
3876         if (jump_count && !jump_state->jumping_attr)
3877                 jump_state->jumping_attr = attr->branch_false;
3878
3879         jump_state->jump_count = jump_count;
3880
3881         /* branching action requires its own counter */
3882         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3883         flow_flag_set(flow, USE_ACT_STATS);
3884
3885         return 0;
3886
3887 err_branch_false:
3888         free_branch_attr(flow, attr->branch_true);
3889 out_err:
3890         return err;
3891 }
3892
3893 static int
3894 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3895                  struct flow_action *flow_action)
3896 {
3897         struct netlink_ext_ack *extack = parse_state->extack;
3898         struct mlx5e_tc_flow *flow = parse_state->flow;
3899         struct mlx5e_tc_jump_state jump_state = {};
3900         struct mlx5_flow_attr *attr = flow->attr;
3901         enum mlx5_flow_namespace_type ns_type;
3902         struct mlx5e_priv *priv = flow->priv;
3903         struct mlx5_flow_attr *prev_attr;
3904         struct flow_action_entry *act;
3905         struct mlx5e_tc_act *tc_act;
3906         int err, i, i_split = 0;
3907         bool is_missable;
3908
3909         ns_type = mlx5e_get_flow_namespace(flow);
3910         list_add(&attr->list, &flow->attrs);
3911
3912         flow_action_for_each(i, act, flow_action) {
3913                 jump_state.jump_target = false;
3914                 is_missable = false;
3915                 prev_attr = attr;
3916
3917                 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3918                 if (!tc_act) {
3919                         NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3920                         err = -EOPNOTSUPP;
3921                         goto out_free_post_acts;
3922                 }
3923
3924                 if (tc_act->can_offload && !tc_act->can_offload(parse_state, act, i, attr)) {
3925                         err = -EOPNOTSUPP;
3926                         goto out_free_post_acts;
3927                 }
3928
3929                 err = tc_act->parse_action(parse_state, act, priv, attr);
3930                 if (err)
3931                         goto out_free_post_acts;
3932
3933                 dec_jump_count(act, tc_act, attr, priv, &jump_state);
3934
3935                 err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
3936                 if (err)
3937                         goto out_free_post_acts;
3938
3939                 parse_state->actions |= attr->action;
3940
3941                 /* Split attr for multi table act if not the last act. */
3942                 if (jump_state.jump_target ||
3943                     (tc_act->is_multi_table_act &&
3944                     tc_act->is_multi_table_act(priv, act, attr) &&
3945                     i < flow_action->num_entries - 1)) {
3946                         is_missable = tc_act->is_missable ? tc_act->is_missable(act) : false;
3947
3948                         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr,
3949                                                       ns_type);
3950                         if (err)
3951                                 goto out_free_post_acts;
3952
3953                         attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
3954                         if (!attr) {
3955                                 err = -ENOMEM;
3956                                 goto out_free_post_acts;
3957                         }
3958
3959                         i_split = i + 1;
3960                         parse_state->if_count = 0;
3961                         list_add(&attr->list, &flow->attrs);
3962                 }
3963
3964                 if (is_missable) {
3965                         /* Add counter to prev, and assign act to new (next) attr */
3966                         prev_attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3967                         flow_flag_set(flow, USE_ACT_STATS);
3968
3969                         attr->tc_act_cookies[attr->tc_act_cookies_count++] = act->cookie;
3970                 } else if (!tc_act->stats_action) {
3971                         prev_attr->tc_act_cookies[prev_attr->tc_act_cookies_count++] = act->cookie;
3972                 }
3973         }
3974
3975         err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr, ns_type);
3976         if (err)
3977                 goto out_free_post_acts;
3978
3979         err = alloc_flow_post_acts(flow, extack);
3980         if (err)
3981                 goto out_free_post_acts;
3982
3983         return 0;
3984
3985 out_free_post_acts:
3986         free_flow_post_acts(flow);
3987
3988         return err;
3989 }
3990
3991 static int
3992 flow_action_supported(struct flow_action *flow_action,
3993                       struct netlink_ext_ack *extack)
3994 {
3995         if (!flow_action_has_entries(flow_action)) {
3996                 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3997                 return -EINVAL;
3998         }
3999
4000         if (!flow_action_hw_stats_check(flow_action, extack,
4001                                         FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
4002                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4003                 return -EOPNOTSUPP;
4004         }
4005
4006         return 0;
4007 }
4008
4009 static int
4010 parse_tc_nic_actions(struct mlx5e_priv *priv,
4011                      struct flow_action *flow_action,
4012                      struct mlx5e_tc_flow *flow,
4013                      struct netlink_ext_ack *extack)
4014 {
4015         struct mlx5e_tc_act_parse_state *parse_state;
4016         struct mlx5e_tc_flow_parse_attr *parse_attr;
4017         struct mlx5_flow_attr *attr = flow->attr;
4018         int err;
4019
4020         err = flow_action_supported(flow_action, extack);
4021         if (err)
4022                 return err;
4023
4024         attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
4025         parse_attr = attr->parse_attr;
4026         parse_state = &parse_attr->parse_state;
4027         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4028         parse_state->ct_priv = get_ct_priv(priv);
4029
4030         err = parse_tc_actions(parse_state, flow_action);
4031         if (err)
4032                 return err;
4033
4034         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4035         if (err)
4036                 return err;
4037
4038         err = verify_attr_actions(attr->action, extack);
4039         if (err)
4040                 return err;
4041
4042         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4043                                      parse_attr, flow, extack))
4044                 return -EOPNOTSUPP;
4045
4046         return 0;
4047 }
4048
4049 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4050                                   struct net_device *peer_netdev)
4051 {
4052         struct mlx5e_priv *peer_priv;
4053
4054         peer_priv = netdev_priv(peer_netdev);
4055
4056         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4057                 mlx5e_eswitch_vf_rep(priv->netdev) &&
4058                 mlx5e_eswitch_vf_rep(peer_netdev) &&
4059                 mlx5e_same_hw_devs(priv, peer_priv));
4060 }
4061
4062 static bool same_hw_reps(struct mlx5e_priv *priv,
4063                          struct net_device *peer_netdev)
4064 {
4065         struct mlx5e_priv *peer_priv;
4066
4067         peer_priv = netdev_priv(peer_netdev);
4068
4069         return mlx5e_eswitch_rep(priv->netdev) &&
4070                mlx5e_eswitch_rep(peer_netdev) &&
4071                mlx5e_same_hw_devs(priv, peer_priv);
4072 }
4073
4074 static bool is_lag_dev(struct mlx5e_priv *priv,
4075                        struct net_device *peer_netdev)
4076 {
4077         return ((mlx5_lag_is_sriov(priv->mdev) ||
4078                  mlx5_lag_is_multipath(priv->mdev)) &&
4079                  same_hw_reps(priv, peer_netdev));
4080 }
4081
4082 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4083 {
4084         return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev);
4085 }
4086
4087 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4088                                     struct net_device *out_dev)
4089 {
4090         if (is_merged_eswitch_vfs(priv, out_dev))
4091                 return true;
4092
4093         if (is_multiport_eligible(priv, out_dev))
4094                 return true;
4095
4096         if (is_lag_dev(priv, out_dev))
4097                 return true;
4098
4099         return mlx5e_eswitch_rep(out_dev) &&
4100                same_port_devs(priv, netdev_priv(out_dev));
4101 }
4102
4103 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4104                                       struct mlx5_flow_attr *attr,
4105                                       int ifindex,
4106                                       enum mlx5e_tc_int_port_type type,
4107                                       u32 *action,
4108                                       int out_index)
4109 {
4110         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4111         struct mlx5e_tc_int_port_priv *int_port_priv;
4112         struct mlx5e_tc_flow_parse_attr *parse_attr;
4113         struct mlx5e_tc_int_port *dest_int_port;
4114         int err;
4115
4116         parse_attr = attr->parse_attr;
4117         int_port_priv = mlx5e_get_int_port_priv(priv);
4118
4119         dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4120         if (IS_ERR(dest_int_port))
4121                 return PTR_ERR(dest_int_port);
4122
4123         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4124                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4125                                         mlx5e_tc_int_port_get_metadata(dest_int_port));
4126         if (err) {
4127                 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4128                 return err;
4129         }
4130
4131         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4132
4133         esw_attr->dest_int_port = dest_int_port;
4134         esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4135         esw_attr->split_count = out_index;
4136
4137         /* Forward to root fdb for matching against the new source vport */
4138         attr->dest_chain = 0;
4139
4140         return 0;
4141 }
4142
4143 static int
4144 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4145                      struct flow_action *flow_action,
4146                      struct mlx5e_tc_flow *flow,
4147                      struct netlink_ext_ack *extack)
4148 {
4149         struct mlx5e_tc_act_parse_state *parse_state;
4150         struct mlx5e_tc_flow_parse_attr *parse_attr;
4151         struct mlx5_flow_attr *attr = flow->attr;
4152         struct mlx5_esw_flow_attr *esw_attr;
4153         struct net_device *filter_dev;
4154         int err;
4155
4156         err = flow_action_supported(flow_action, extack);
4157         if (err)
4158                 return err;
4159
4160         esw_attr = attr->esw_attr;
4161         parse_attr = attr->parse_attr;
4162         filter_dev = parse_attr->filter_dev;
4163         parse_state = &parse_attr->parse_state;
4164         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4165         parse_state->ct_priv = get_ct_priv(priv);
4166
4167         err = parse_tc_actions(parse_state, flow_action);
4168         if (err)
4169                 return err;
4170
4171         /* Forward to/from internal port can only have 1 dest */
4172         if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4173             esw_attr->out_count > 1) {
4174                 NL_SET_ERR_MSG_MOD(extack,
4175                                    "Rules with internal port can have only one destination");
4176                 return -EOPNOTSUPP;
4177         }
4178
4179         /* Forward from tunnel/internal port to internal port is not supported */
4180         if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4181             esw_attr->dest_int_port) {
4182                 NL_SET_ERR_MSG_MOD(extack,
4183                                    "Forwarding from tunnel/internal port to internal port is not supported");
4184                 return -EOPNOTSUPP;
4185         }
4186
4187         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4188         if (err)
4189                 return err;
4190
4191         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4192                                      parse_attr, flow, extack))
4193                 return -EOPNOTSUPP;
4194
4195         return 0;
4196 }
4197
4198 static void get_flags(int flags, unsigned long *flow_flags)
4199 {
4200         unsigned long __flow_flags = 0;
4201
4202         if (flags & MLX5_TC_FLAG(INGRESS))
4203                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4204         if (flags & MLX5_TC_FLAG(EGRESS))
4205                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4206
4207         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4208                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4209         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4210                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4211         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4212                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4213
4214         *flow_flags = __flow_flags;
4215 }
4216
4217 static const struct rhashtable_params tc_ht_params = {
4218         .head_offset = offsetof(struct mlx5e_tc_flow, node),
4219         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4220         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4221         .automatic_shrinking = true,
4222 };
4223
4224 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4225                                     unsigned long flags)
4226 {
4227         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4228         struct mlx5e_rep_priv *rpriv;
4229
4230         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4231                 rpriv = priv->ppriv;
4232                 return &rpriv->tc_ht;
4233         } else /* NIC offload */
4234                 return &tc->ht;
4235 }
4236
4237 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4238 {
4239         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4240         struct mlx5_flow_attr *attr = flow->attr;
4241         bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4242                 flow_flag_test(flow, INGRESS);
4243         bool act_is_encap = !!(attr->action &
4244                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4245         bool esw_paired = mlx5_devcom_comp_is_ready(esw_attr->in_mdev->priv.eswitch->devcom);
4246
4247         if (!esw_paired)
4248                 return false;
4249
4250         if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4251              mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4252             (is_rep_ingress || act_is_encap))
4253                 return true;
4254
4255         if (mlx5_lag_is_mpesw(esw_attr->in_mdev))
4256                 return true;
4257
4258         return false;
4259 }
4260
4261 struct mlx5_flow_attr *
4262 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4263 {
4264         u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB)  ?
4265                                 sizeof(struct mlx5_esw_flow_attr) :
4266                                 sizeof(struct mlx5_nic_flow_attr);
4267         struct mlx5_flow_attr *attr;
4268
4269         attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4270         if (!attr)
4271                 return attr;
4272
4273         INIT_LIST_HEAD(&attr->list);
4274         return attr;
4275 }
4276
4277 static void
4278 mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4279 {
4280         struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4281         struct mlx5_esw_flow_attr *esw_attr;
4282
4283         if (!attr)
4284                 return;
4285
4286         if (attr->post_act_handle)
4287                 mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4288
4289         mlx5e_tc_tun_encap_dests_unset(flow->priv, flow, attr);
4290
4291         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4292                 mlx5_fc_destroy(counter_dev, attr->counter);
4293
4294         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4295                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4296                 mlx5e_tc_detach_mod_hdr(flow->priv, flow, attr);
4297         }
4298
4299         if (mlx5e_is_eswitch_flow(flow)) {
4300                 esw_attr = attr->esw_attr;
4301
4302                 if (esw_attr->int_port)
4303                         mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4304                                               esw_attr->int_port);
4305
4306                 if (esw_attr->dest_int_port)
4307                         mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4308                                               esw_attr->dest_int_port);
4309         }
4310
4311         mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
4312
4313         free_branch_attr(flow, attr->branch_true);
4314         free_branch_attr(flow, attr->branch_false);
4315 }
4316
4317 static int
4318 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4319                  struct flow_cls_offload *f, unsigned long flow_flags,
4320                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
4321                  struct mlx5e_tc_flow **__flow)
4322 {
4323         struct mlx5e_tc_flow_parse_attr *parse_attr;
4324         struct mlx5_flow_attr *attr;
4325         struct mlx5e_tc_flow *flow;
4326         int err = -ENOMEM;
4327         int out_index;
4328
4329         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4330         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4331         if (!parse_attr || !flow)
4332                 goto err_free;
4333
4334         flow->flags = flow_flags;
4335         flow->cookie = f->cookie;
4336         flow->priv = priv;
4337
4338         attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4339         if (!attr)
4340                 goto err_free;
4341
4342         flow->attr = attr;
4343
4344         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4345                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4346         INIT_LIST_HEAD(&flow->hairpin);
4347         INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4348         INIT_LIST_HEAD(&flow->attrs);
4349         INIT_LIST_HEAD(&flow->peer_flows);
4350         refcount_set(&flow->refcnt, 1);
4351         init_completion(&flow->init_done);
4352         init_completion(&flow->del_hw_done);
4353
4354         *__flow = flow;
4355         *__parse_attr = parse_attr;
4356
4357         return 0;
4358
4359 err_free:
4360         kfree(flow);
4361         kvfree(parse_attr);
4362         return err;
4363 }
4364
4365 static void
4366 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4367                      struct mlx5e_tc_flow_parse_attr *parse_attr,
4368                      struct flow_cls_offload *f)
4369 {
4370         attr->parse_attr = parse_attr;
4371         attr->chain = f->common.chain_index;
4372         attr->prio = f->common.prio;
4373 }
4374
4375 static void
4376 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4377                          struct mlx5e_priv *priv,
4378                          struct mlx5e_tc_flow_parse_attr *parse_attr,
4379                          struct flow_cls_offload *f,
4380                          struct mlx5_eswitch_rep *in_rep,
4381                          struct mlx5_core_dev *in_mdev)
4382 {
4383         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4384         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4385
4386         mlx5e_flow_attr_init(attr, parse_attr, f);
4387
4388         esw_attr->in_rep = in_rep;
4389         esw_attr->in_mdev = in_mdev;
4390
4391         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4392             MLX5_COUNTER_SOURCE_ESWITCH)
4393                 esw_attr->counter_dev = in_mdev;
4394         else
4395                 esw_attr->counter_dev = priv->mdev;
4396 }
4397
4398 static struct mlx5e_tc_flow *
4399 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4400                      struct flow_cls_offload *f,
4401                      unsigned long flow_flags,
4402                      struct net_device *filter_dev,
4403                      struct mlx5_eswitch_rep *in_rep,
4404                      struct mlx5_core_dev *in_mdev)
4405 {
4406         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4407         struct netlink_ext_ack *extack = f->common.extack;
4408         struct mlx5e_tc_flow_parse_attr *parse_attr;
4409         struct mlx5e_tc_flow *flow;
4410         int attr_size, err;
4411
4412         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4413         attr_size  = sizeof(struct mlx5_esw_flow_attr);
4414         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4415                                &parse_attr, &flow);
4416         if (err)
4417                 goto out;
4418
4419         parse_attr->filter_dev = filter_dev;
4420         mlx5e_flow_esw_attr_init(flow->attr,
4421                                  priv, parse_attr,
4422                                  f, in_rep, in_mdev);
4423
4424         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4425                                f, filter_dev);
4426         if (err)
4427                 goto err_free;
4428
4429         /* actions validation depends on parsing the ct matches first */
4430         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4431                                    &flow->attr->ct_attr, extack);
4432         if (err)
4433                 goto err_free;
4434
4435         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4436         if (err)
4437                 goto err_free;
4438
4439         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4440         complete_all(&flow->init_done);
4441         if (err) {
4442                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4443                         goto err_free;
4444
4445                 add_unready_flow(flow);
4446         }
4447
4448         return flow;
4449
4450 err_free:
4451         mlx5e_flow_put(priv, flow);
4452 out:
4453         return ERR_PTR(err);
4454 }
4455
4456 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4457                                       struct mlx5e_tc_flow *flow,
4458                                       unsigned long flow_flags,
4459                                       struct mlx5_eswitch *peer_esw)
4460 {
4461         struct mlx5e_priv *priv = flow->priv, *peer_priv;
4462         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4463         struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4464         struct mlx5e_tc_flow_parse_attr *parse_attr;
4465         int i = mlx5_get_dev_index(peer_esw->dev);
4466         struct mlx5e_rep_priv *peer_urpriv;
4467         struct mlx5e_tc_flow *peer_flow;
4468         struct mlx5_core_dev *in_mdev;
4469         int err = 0;
4470
4471         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4472         peer_priv = netdev_priv(peer_urpriv->netdev);
4473
4474         /* in_mdev is assigned of which the packet originated from.
4475          * So packets redirected to uplink use the same mdev of the
4476          * original flow and packets redirected from uplink use the
4477          * peer mdev.
4478          * In multiport eswitch it's a special case that we need to
4479          * keep the original mdev.
4480          */
4481         if (attr->in_rep->vport == MLX5_VPORT_UPLINK && !mlx5_lag_is_mpesw(priv->mdev))
4482                 in_mdev = peer_priv->mdev;
4483         else
4484                 in_mdev = priv->mdev;
4485
4486         parse_attr = flow->attr->parse_attr;
4487         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4488                                          parse_attr->filter_dev,
4489                                          attr->in_rep, in_mdev);
4490         if (IS_ERR(peer_flow)) {
4491                 err = PTR_ERR(peer_flow);
4492                 goto out;
4493         }
4494
4495         list_add_tail(&peer_flow->peer_flows, &flow->peer_flows);
4496         flow_flag_set(flow, DUP);
4497         mutex_lock(&esw->offloads.peer_mutex);
4498         list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]);
4499         mutex_unlock(&esw->offloads.peer_mutex);
4500
4501 out:
4502         return err;
4503 }
4504
4505 static int
4506 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4507                    struct flow_cls_offload *f,
4508                    unsigned long flow_flags,
4509                    struct net_device *filter_dev,
4510                    struct mlx5e_tc_flow **__flow)
4511 {
4512         struct mlx5_devcom_comp_dev *devcom = priv->mdev->priv.eswitch->devcom, *pos;
4513         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4514         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4515         struct mlx5_core_dev *in_mdev = priv->mdev;
4516         struct mlx5_eswitch *peer_esw;
4517         struct mlx5e_tc_flow *flow;
4518         int err;
4519
4520         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4521                                     in_mdev);
4522         if (IS_ERR(flow))
4523                 return PTR_ERR(flow);
4524
4525         if (!is_peer_flow_needed(flow)) {
4526                 *__flow = flow;
4527                 return 0;
4528         }
4529
4530         if (!mlx5_devcom_for_each_peer_begin(devcom)) {
4531                 err = -ENODEV;
4532                 goto clean_flow;
4533         }
4534
4535         mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {
4536                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw);
4537                 if (err)
4538                         goto peer_clean;
4539         }
4540
4541         mlx5_devcom_for_each_peer_end(devcom);
4542
4543         *__flow = flow;
4544         return 0;
4545
4546 peer_clean:
4547         mlx5e_tc_del_fdb_peers_flow(flow);
4548         mlx5_devcom_for_each_peer_end(devcom);
4549 clean_flow:
4550         mlx5e_tc_del_fdb_flow(priv, flow);
4551         return err;
4552 }
4553
4554 static int
4555 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4556                    struct flow_cls_offload *f,
4557                    unsigned long flow_flags,
4558                    struct net_device *filter_dev,
4559                    struct mlx5e_tc_flow **__flow)
4560 {
4561         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4562         struct netlink_ext_ack *extack = f->common.extack;
4563         struct mlx5e_tc_flow_parse_attr *parse_attr;
4564         struct mlx5e_tc_flow *flow;
4565         int attr_size, err;
4566
4567         if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4568                 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4569                         return -EOPNOTSUPP;
4570         } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4571                 return -EOPNOTSUPP;
4572         }
4573
4574         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4575         attr_size  = sizeof(struct mlx5_nic_flow_attr);
4576         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4577                                &parse_attr, &flow);
4578         if (err)
4579                 goto out;
4580
4581         parse_attr->filter_dev = filter_dev;
4582         mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4583
4584         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4585                                f, filter_dev);
4586         if (err)
4587                 goto err_free;
4588
4589         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4590                                    &flow->attr->ct_attr, extack);
4591         if (err)
4592                 goto err_free;
4593
4594         err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4595         if (err)
4596                 goto err_free;
4597
4598         err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4599         if (err)
4600                 goto err_free;
4601
4602         flow_flag_set(flow, OFFLOADED);
4603         *__flow = flow;
4604
4605         return 0;
4606
4607 err_free:
4608         flow_flag_set(flow, FAILED);
4609         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4610         mlx5e_flow_put(priv, flow);
4611 out:
4612         return err;
4613 }
4614
4615 static int
4616 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4617                   struct flow_cls_offload *f,
4618                   unsigned long flags,
4619                   struct net_device *filter_dev,
4620                   struct mlx5e_tc_flow **flow)
4621 {
4622         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4623         unsigned long flow_flags;
4624         int err;
4625
4626         get_flags(flags, &flow_flags);
4627
4628         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4629                 return -EOPNOTSUPP;
4630
4631         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4632                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4633                                          filter_dev, flow);
4634         else
4635                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4636                                          filter_dev, flow);
4637
4638         return err;
4639 }
4640
4641 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4642                                            struct mlx5e_rep_priv *rpriv)
4643 {
4644         /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4645          * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4646          * function is called from NIC mode.
4647          */
4648         return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4649 }
4650
4651 /* As IPsec and TC order is not aligned between software and hardware-offload,
4652  * either IPsec offload or TC offload, not both, is allowed for a specific interface.
4653  */
4654 static bool is_tc_ipsec_order_check_needed(struct net_device *filter, struct mlx5e_priv *priv)
4655 {
4656         if (!IS_ENABLED(CONFIG_MLX5_EN_IPSEC))
4657                 return false;
4658
4659         if (filter != priv->netdev)
4660                 return false;
4661
4662         if (mlx5e_eswitch_vf_rep(priv->netdev))
4663                 return false;
4664
4665         return true;
4666 }
4667
4668 static int mlx5e_tc_block_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4669 {
4670         struct mlx5_core_dev *mdev = priv->mdev;
4671
4672         if (!is_tc_ipsec_order_check_needed(filter, priv))
4673                 return 0;
4674
4675         if (mdev->num_block_tc)
4676                 return -EBUSY;
4677
4678         mdev->num_block_ipsec++;
4679
4680         return 0;
4681 }
4682
4683 static void mlx5e_tc_unblock_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4684 {
4685         if (!is_tc_ipsec_order_check_needed(filter, priv))
4686                 return;
4687
4688         priv->mdev->num_block_ipsec--;
4689 }
4690
4691 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4692                            struct flow_cls_offload *f, unsigned long flags)
4693 {
4694         struct netlink_ext_ack *extack = f->common.extack;
4695         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4696         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4697         struct mlx5e_tc_flow *flow;
4698         int err = 0;
4699
4700         if (!mlx5_esw_hold(priv->mdev))
4701                 return -EBUSY;
4702
4703         err = mlx5e_tc_block_ipsec_offload(dev, priv);
4704         if (err)
4705                 goto esw_release;
4706
4707         mlx5_esw_get(priv->mdev);
4708
4709         rcu_read_lock();
4710         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4711         if (flow) {
4712                 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4713                  * just return 0.
4714                  */
4715                 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4716                         goto rcu_unlock;
4717
4718                 NL_SET_ERR_MSG_MOD(extack,
4719                                    "flow cookie already exists, ignoring");
4720                 netdev_warn_once(priv->netdev,
4721                                  "flow cookie %lx already exists, ignoring\n",
4722                                  f->cookie);
4723                 err = -EEXIST;
4724                 goto rcu_unlock;
4725         }
4726 rcu_unlock:
4727         rcu_read_unlock();
4728         if (flow)
4729                 goto out;
4730
4731         trace_mlx5e_configure_flower(f);
4732         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4733         if (err)
4734                 goto out;
4735
4736         /* Flow rule offloaded to non-uplink representor sharing tc block,
4737          * set the flow's owner dev.
4738          */
4739         if (is_flow_rule_duplicate_allowed(dev, rpriv))
4740                 flow->orig_dev = dev;
4741
4742         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4743         if (err)
4744                 goto err_free;
4745
4746         mlx5_esw_release(priv->mdev);
4747         return 0;
4748
4749 err_free:
4750         mlx5e_flow_put(priv, flow);
4751 out:
4752         mlx5e_tc_unblock_ipsec_offload(dev, priv);
4753         mlx5_esw_put(priv->mdev);
4754 esw_release:
4755         mlx5_esw_release(priv->mdev);
4756         return err;
4757 }
4758
4759 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4760 {
4761         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4762         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4763
4764         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4765                 flow_flag_test(flow, EGRESS) == dir_egress;
4766 }
4767
4768 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4769                         struct flow_cls_offload *f, unsigned long flags)
4770 {
4771         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4772         struct mlx5e_tc_flow *flow;
4773         int err;
4774
4775         rcu_read_lock();
4776         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4777         if (!flow || !same_flow_direction(flow, flags)) {
4778                 err = -EINVAL;
4779                 goto errout;
4780         }
4781
4782         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4783          * set.
4784          */
4785         if (flow_flag_test_and_set(flow, DELETED)) {
4786                 err = -EINVAL;
4787                 goto errout;
4788         }
4789         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4790         rcu_read_unlock();
4791
4792         trace_mlx5e_delete_flower(f);
4793         mlx5e_flow_put(priv, flow);
4794
4795         mlx5e_tc_unblock_ipsec_offload(dev, priv);
4796         mlx5_esw_put(priv->mdev);
4797         return 0;
4798
4799 errout:
4800         rcu_read_unlock();
4801         return err;
4802 }
4803
4804 int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
4805                                struct flow_offload_action *fl_act)
4806 {
4807         return mlx5e_tc_act_stats_fill_stats(get_act_stats_handle(priv), fl_act);
4808 }
4809
4810 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4811                        struct flow_cls_offload *f, unsigned long flags)
4812 {
4813         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4814         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4815         struct mlx5e_tc_flow *flow;
4816         struct mlx5_fc *counter;
4817         u64 lastuse = 0;
4818         u64 packets = 0;
4819         u64 bytes = 0;
4820         int err = 0;
4821
4822         rcu_read_lock();
4823         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4824                                                 tc_ht_params));
4825         rcu_read_unlock();
4826         if (IS_ERR(flow))
4827                 return PTR_ERR(flow);
4828
4829         if (!same_flow_direction(flow, flags)) {
4830                 err = -EINVAL;
4831                 goto errout;
4832         }
4833
4834         if (mlx5e_is_offloaded_flow(flow)) {
4835                 if (flow_flag_test(flow, USE_ACT_STATS)) {
4836                         f->use_act_stats = true;
4837                 } else {
4838                         counter = mlx5e_tc_get_counter(flow);
4839                         if (!counter)
4840                                 goto errout;
4841
4842                         mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4843                 }
4844         }
4845
4846         /* Under multipath it's possible for one rule to be currently
4847          * un-offloaded while the other rule is offloaded.
4848          */
4849         if (esw && !mlx5_devcom_for_each_peer_begin(esw->devcom))
4850                 goto out;
4851
4852         if (flow_flag_test(flow, DUP)) {
4853                 struct mlx5e_tc_flow *peer_flow;
4854
4855                 list_for_each_entry(peer_flow, &flow->peer_flows, peer_flows) {
4856                         u64 packets2;
4857                         u64 lastuse2;
4858                         u64 bytes2;
4859
4860                         if (!flow_flag_test(peer_flow, OFFLOADED))
4861                                 continue;
4862                         if (flow_flag_test(flow, USE_ACT_STATS)) {
4863                                 f->use_act_stats = true;
4864                                 break;
4865                         }
4866
4867                         counter = mlx5e_tc_get_counter(peer_flow);
4868                         if (!counter)
4869                                 goto no_peer_counter;
4870                         mlx5_fc_query_cached(counter, &bytes2, &packets2,
4871                                              &lastuse2);
4872
4873                         bytes += bytes2;
4874                         packets += packets2;
4875                         lastuse = max_t(u64, lastuse, lastuse2);
4876                 }
4877         }
4878
4879 no_peer_counter:
4880         if (esw)
4881                 mlx5_devcom_for_each_peer_end(esw->devcom);
4882 out:
4883         flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
4884                           FLOW_ACTION_HW_STATS_DELAYED);
4885         trace_mlx5e_stats_flower(f);
4886 errout:
4887         mlx5e_flow_put(priv, flow);
4888         return err;
4889 }
4890
4891 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
4892                                struct netlink_ext_ack *extack)
4893 {
4894         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4895         struct mlx5_eswitch *esw;
4896         u32 rate_mbps = 0;
4897         u16 vport_num;
4898         int err;
4899
4900         vport_num = rpriv->rep->vport;
4901         if (vport_num >= MLX5_VPORT_ECPF) {
4902                 NL_SET_ERR_MSG_MOD(extack,
4903                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4904                 return -EOPNOTSUPP;
4905         }
4906
4907         esw = priv->mdev->priv.eswitch;
4908         /* rate is given in bytes/sec.
4909          * First convert to bits/sec and then round to the nearest mbit/secs.
4910          * mbit means million bits.
4911          * Moreover, if rate is non zero we choose to configure to a minimum of
4912          * 1 mbit/sec.
4913          */
4914         if (rate) {
4915                 rate = (rate * BITS_PER_BYTE) + 500000;
4916                 do_div(rate, 1000000);
4917                 rate_mbps = max_t(u32, rate, 1);
4918         }
4919
4920         err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
4921         if (err)
4922                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4923
4924         return err;
4925 }
4926
4927 static int
4928 tc_matchall_police_validate(const struct flow_action *action,
4929                             const struct flow_action_entry *act,
4930                             struct netlink_ext_ack *extack)
4931 {
4932         if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
4933                 NL_SET_ERR_MSG_MOD(extack,
4934                                    "Offload not supported when conform action is not continue");
4935                 return -EOPNOTSUPP;
4936         }
4937
4938         if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
4939                 NL_SET_ERR_MSG_MOD(extack,
4940                                    "Offload not supported when exceed action is not drop");
4941                 return -EOPNOTSUPP;
4942         }
4943
4944         if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
4945             !flow_action_is_last_entry(action, act)) {
4946                 NL_SET_ERR_MSG_MOD(extack,
4947                                    "Offload not supported when conform action is ok, but action is not last");
4948                 return -EOPNOTSUPP;
4949         }
4950
4951         if (act->police.peakrate_bytes_ps ||
4952             act->police.avrate || act->police.overhead) {
4953                 NL_SET_ERR_MSG_MOD(extack,
4954                                    "Offload not supported when peakrate/avrate/overhead is configured");
4955                 return -EOPNOTSUPP;
4956         }
4957
4958         return 0;
4959 }
4960
4961 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4962                                         struct flow_action *flow_action,
4963                                         struct netlink_ext_ack *extack)
4964 {
4965         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4966         const struct flow_action_entry *act;
4967         int err;
4968         int i;
4969
4970         if (!flow_action_has_entries(flow_action)) {
4971                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4972                 return -EINVAL;
4973         }
4974
4975         if (!flow_offload_has_one_action(flow_action)) {
4976                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4977                 return -EOPNOTSUPP;
4978         }
4979
4980         if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4981                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4982                 return -EOPNOTSUPP;
4983         }
4984
4985         flow_action_for_each(i, act, flow_action) {
4986                 switch (act->id) {
4987                 case FLOW_ACTION_POLICE:
4988                         err = tc_matchall_police_validate(flow_action, act, extack);
4989                         if (err)
4990                                 return err;
4991
4992                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4993                         if (err)
4994                                 return err;
4995
4996                         mlx5e_stats_copy_rep_stats(&rpriv->prev_vf_vport_stats,
4997                                                    &priv->stats.rep_stats);
4998                         break;
4999                 default:
5000                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5001                         return -EOPNOTSUPP;
5002                 }
5003         }
5004
5005         return 0;
5006 }
5007
5008 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5009                                 struct tc_cls_matchall_offload *ma)
5010 {
5011         struct netlink_ext_ack *extack = ma->common.extack;
5012
5013         if (ma->common.prio != 1) {
5014                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5015                 return -EINVAL;
5016         }
5017
5018         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5019 }
5020
5021 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5022                              struct tc_cls_matchall_offload *ma)
5023 {
5024         struct netlink_ext_ack *extack = ma->common.extack;
5025
5026         return apply_police_params(priv, 0, extack);
5027 }
5028
5029 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5030                              struct tc_cls_matchall_offload *ma)
5031 {
5032         struct mlx5e_rep_priv *rpriv = priv->ppriv;
5033         struct rtnl_link_stats64 cur_stats;
5034         u64 dbytes;
5035         u64 dpkts;
5036
5037         mlx5e_stats_copy_rep_stats(&cur_stats, &priv->stats.rep_stats);
5038         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5039         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5040         rpriv->prev_vf_vport_stats = cur_stats;
5041         flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
5042                           FLOW_ACTION_HW_STATS_DELAYED);
5043 }
5044
5045 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5046                                               struct mlx5e_priv *peer_priv)
5047 {
5048         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5049         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
5050         struct mlx5e_hairpin_entry *hpe, *tmp;
5051         LIST_HEAD(init_wait_list);
5052         u16 peer_vhca_id;
5053         int bkt;
5054
5055         if (!mlx5e_same_hw_devs(priv, peer_priv))
5056                 return;
5057
5058         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5059
5060         mutex_lock(&tc->hairpin_tbl_lock);
5061         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
5062                 if (refcount_inc_not_zero(&hpe->refcnt))
5063                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5064         mutex_unlock(&tc->hairpin_tbl_lock);
5065
5066         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5067                 wait_for_completion(&hpe->res_ready);
5068                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
5069                         mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
5070
5071                 mlx5e_hairpin_put(priv, hpe);
5072         }
5073 }
5074
5075 static int mlx5e_tc_netdev_event(struct notifier_block *this,
5076                                  unsigned long event, void *ptr)
5077 {
5078         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5079         struct mlx5e_priv *peer_priv;
5080         struct mlx5e_tc_table *tc;
5081         struct mlx5e_priv *priv;
5082
5083         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5084             event != NETDEV_UNREGISTER ||
5085             ndev->reg_state == NETREG_REGISTERED)
5086                 return NOTIFY_DONE;
5087
5088         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5089         priv = tc->priv;
5090         peer_priv = netdev_priv(ndev);
5091         if (priv == peer_priv ||
5092             !(priv->netdev->features & NETIF_F_HW_TC))
5093                 return NOTIFY_DONE;
5094
5095         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5096
5097         return NOTIFY_DONE;
5098 }
5099
5100 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5101 {
5102         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5103         struct mlx5_flow_table **ft = &tc->miss_t;
5104         struct mlx5_flow_table_attr ft_attr = {};
5105         struct mlx5_flow_namespace *ns;
5106         int err = 0;
5107
5108         ft_attr.max_fte = 1;
5109         ft_attr.autogroup.max_num_groups = 1;
5110         ft_attr.level = MLX5E_TC_MISS_LEVEL;
5111         ft_attr.prio = 0;
5112         ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5113
5114         *ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5115         if (IS_ERR(*ft)) {
5116                 err = PTR_ERR(*ft);
5117                 netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5118         }
5119
5120         return err;
5121 }
5122
5123 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5124 {
5125         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5126
5127         mlx5_destroy_flow_table(tc->miss_t);
5128 }
5129
5130 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5131 {
5132         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5133         struct mlx5_core_dev *dev = priv->mdev;
5134         struct mapping_ctx *chains_mapping;
5135         struct mlx5_chains_attr attr = {};
5136         u64 mapping_id;
5137         int err;
5138
5139         mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5140         mutex_init(&tc->t_lock);
5141         mutex_init(&tc->hairpin_tbl_lock);
5142         hash_init(tc->hairpin_tbl);
5143         tc->priv = priv;
5144
5145         err = rhashtable_init(&tc->ht, &tc_ht_params);
5146         if (err)
5147                 return err;
5148
5149         lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5150         lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5151
5152         mapping_id = mlx5_query_nic_system_image_guid(dev);
5153
5154         chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5155                                                sizeof(struct mlx5_mapped_obj),
5156                                                MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5157
5158         if (IS_ERR(chains_mapping)) {
5159                 err = PTR_ERR(chains_mapping);
5160                 goto err_mapping;
5161         }
5162         tc->mapping = chains_mapping;
5163
5164         err = mlx5e_tc_nic_create_miss_table(priv);
5165         if (err)
5166                 goto err_chains;
5167
5168         if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5169                 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5170                         MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5171         attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5172         attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5173         attr.default_ft = tc->miss_t;
5174         attr.mapping = chains_mapping;
5175         attr.fs_base_prio = MLX5E_TC_PRIO;
5176
5177         tc->chains = mlx5_chains_create(dev, &attr);
5178         if (IS_ERR(tc->chains)) {
5179                 err = PTR_ERR(tc->chains);
5180                 goto err_miss;
5181         }
5182
5183         mlx5_chains_print_info(tc->chains);
5184
5185         tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5186         tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5187                                  MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5188
5189         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5190         err = register_netdevice_notifier_dev_net(priv->netdev,
5191                                                   &tc->netdevice_nb,
5192                                                   &tc->netdevice_nn);
5193         if (err) {
5194                 tc->netdevice_nb.notifier_call = NULL;
5195                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5196                 goto err_reg;
5197         }
5198
5199         mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5200
5201         tc->action_stats_handle = mlx5e_tc_act_stats_create();
5202         if (IS_ERR(tc->action_stats_handle)) {
5203                 err = PTR_ERR(tc->action_stats_handle);
5204                 goto err_act_stats;
5205         }
5206
5207         return 0;
5208
5209 err_act_stats:
5210         unregister_netdevice_notifier_dev_net(priv->netdev,
5211                                               &tc->netdevice_nb,
5212                                               &tc->netdevice_nn);
5213 err_reg:
5214         mlx5_tc_ct_clean(tc->ct);
5215         mlx5e_tc_post_act_destroy(tc->post_act);
5216         mlx5_chains_destroy(tc->chains);
5217 err_miss:
5218         mlx5e_tc_nic_destroy_miss_table(priv);
5219 err_chains:
5220         mapping_destroy(chains_mapping);
5221 err_mapping:
5222         rhashtable_destroy(&tc->ht);
5223         return err;
5224 }
5225
5226 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5227 {
5228         struct mlx5e_tc_flow *flow = ptr;
5229         struct mlx5e_priv *priv = flow->priv;
5230
5231         mlx5e_tc_del_flow(priv, flow);
5232         kfree(flow);
5233 }
5234
5235 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5236 {
5237         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5238
5239         debugfs_remove_recursive(tc->dfs_root);
5240
5241         if (tc->netdevice_nb.notifier_call)
5242                 unregister_netdevice_notifier_dev_net(priv->netdev,
5243                                                       &tc->netdevice_nb,
5244                                                       &tc->netdevice_nn);
5245
5246         mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5247         mutex_destroy(&tc->hairpin_tbl_lock);
5248
5249         rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5250
5251         if (!IS_ERR_OR_NULL(tc->t)) {
5252                 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5253                 tc->t = NULL;
5254         }
5255         mutex_destroy(&tc->t_lock);
5256
5257         mlx5_tc_ct_clean(tc->ct);
5258         mlx5e_tc_post_act_destroy(tc->post_act);
5259         mapping_destroy(tc->mapping);
5260         mlx5_chains_destroy(tc->chains);
5261         mlx5e_tc_nic_destroy_miss_table(priv);
5262         mlx5e_tc_act_stats_free(tc->action_stats_handle);
5263 }
5264
5265 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5266 {
5267         int err;
5268
5269         err = rhashtable_init(tc_ht, &tc_ht_params);
5270         if (err)
5271                 return err;
5272
5273         lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5274         lockdep_init_map(&tc_ht->run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5275
5276         return 0;
5277 }
5278
5279 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5280 {
5281         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5282 }
5283
5284 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5285 {
5286         const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5287         struct netdev_phys_item_id ppid;
5288         struct mlx5e_rep_priv *rpriv;
5289         struct mapping_ctx *mapping;
5290         struct mlx5_eswitch *esw;
5291         struct mlx5e_priv *priv;
5292         u64 mapping_id, key;
5293         int err = 0;
5294
5295         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5296         priv = netdev_priv(rpriv->netdev);
5297         esw = priv->mdev->priv.eswitch;
5298
5299         uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5300                                                        MLX5_FLOW_NAMESPACE_FDB);
5301         uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5302                                                esw_chains(esw),
5303                                                &esw->offloads.mod_hdr,
5304                                                MLX5_FLOW_NAMESPACE_FDB,
5305                                                uplink_priv->post_act);
5306
5307         uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5308
5309         uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5310
5311         mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5312
5313         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5314                                         sizeof(struct tunnel_match_key),
5315                                         TUNNEL_INFO_BITS_MASK, true);
5316
5317         if (IS_ERR(mapping)) {
5318                 err = PTR_ERR(mapping);
5319                 goto err_tun_mapping;
5320         }
5321         uplink_priv->tunnel_mapping = mapping;
5322
5323         /* Two last values are reserved for stack devices slow path table mark
5324          * and bridge ingress push mark.
5325          */
5326         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5327                                         sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5328         if (IS_ERR(mapping)) {
5329                 err = PTR_ERR(mapping);
5330                 goto err_enc_opts_mapping;
5331         }
5332         uplink_priv->tunnel_enc_opts_mapping = mapping;
5333
5334         uplink_priv->encap = mlx5e_tc_tun_init(priv);
5335         if (IS_ERR(uplink_priv->encap)) {
5336                 err = PTR_ERR(uplink_priv->encap);
5337                 goto err_register_fib_notifier;
5338         }
5339
5340         uplink_priv->action_stats_handle = mlx5e_tc_act_stats_create();
5341         if (IS_ERR(uplink_priv->action_stats_handle)) {
5342                 err = PTR_ERR(uplink_priv->action_stats_handle);
5343                 goto err_action_counter;
5344         }
5345
5346         err = dev_get_port_parent_id(priv->netdev, &ppid, false);
5347         if (!err) {
5348                 memcpy(&key, &ppid.id, sizeof(key));
5349                 mlx5_esw_offloads_devcom_init(esw, key);
5350         }
5351
5352         return 0;
5353
5354 err_action_counter:
5355         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5356 err_register_fib_notifier:
5357         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5358 err_enc_opts_mapping:
5359         mapping_destroy(uplink_priv->tunnel_mapping);
5360 err_tun_mapping:
5361         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5362         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5363         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5364         netdev_warn(priv->netdev,
5365                     "Failed to initialize tc (eswitch), err: %d", err);
5366         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5367         return err;
5368 }
5369
5370 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5371 {
5372         struct mlx5e_rep_priv *rpriv;
5373         struct mlx5_eswitch *esw;
5374         struct mlx5e_priv *priv;
5375
5376         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5377         priv = netdev_priv(rpriv->netdev);
5378         esw = priv->mdev->priv.eswitch;
5379
5380         mlx5_esw_offloads_devcom_cleanup(esw);
5381
5382         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5383
5384         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5385         mapping_destroy(uplink_priv->tunnel_mapping);
5386
5387         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5388         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5389         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5390         mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5391         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5392         mlx5e_tc_act_stats_free(uplink_priv->action_stats_handle);
5393 }
5394
5395 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5396 {
5397         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5398
5399         return atomic_read(&tc_ht->nelems);
5400 }
5401
5402 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5403 {
5404         struct mlx5e_tc_flow *flow, *tmp;
5405         int i;
5406
5407         for (i = 0; i < MLX5_MAX_PORTS; i++) {
5408                 if (i == mlx5_get_dev_index(esw->dev))
5409                         continue;
5410                 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
5411                         mlx5e_tc_del_fdb_peers_flow(flow);
5412         }
5413 }
5414
5415 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5416 {
5417         struct mlx5_rep_uplink_priv *rpriv =
5418                 container_of(work, struct mlx5_rep_uplink_priv,
5419                              reoffload_flows_work);
5420         struct mlx5e_tc_flow *flow, *tmp;
5421
5422         mutex_lock(&rpriv->unready_flows_lock);
5423         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5424                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5425                         unready_flow_del(flow);
5426         }
5427         mutex_unlock(&rpriv->unready_flows_lock);
5428 }
5429
5430 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5431                                      struct flow_cls_offload *cls_flower,
5432                                      unsigned long flags)
5433 {
5434         switch (cls_flower->command) {
5435         case FLOW_CLS_REPLACE:
5436                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5437                                               flags);
5438         case FLOW_CLS_DESTROY:
5439                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5440                                            flags);
5441         case FLOW_CLS_STATS:
5442                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5443                                           flags);
5444         default:
5445                 return -EOPNOTSUPP;
5446         }
5447 }
5448
5449 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5450                             void *cb_priv)
5451 {
5452         unsigned long flags = MLX5_TC_FLAG(INGRESS);
5453         struct mlx5e_priv *priv = cb_priv;
5454
5455         if (!priv->netdev || !netif_device_present(priv->netdev))
5456                 return -EOPNOTSUPP;
5457
5458         if (mlx5e_is_uplink_rep(priv))
5459                 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5460         else
5461                 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5462
5463         switch (type) {
5464         case TC_SETUP_CLSFLOWER:
5465                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5466         default:
5467                 return -EOPNOTSUPP;
5468         }
5469 }
5470
5471 static bool mlx5e_tc_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
5472                                     struct mlx5e_tc_update_priv *tc_priv,
5473                                     u32 tunnel_id)
5474 {
5475         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5476         struct tunnel_match_enc_opts enc_opts = {};
5477         struct mlx5_rep_uplink_priv *uplink_priv;
5478         struct mlx5e_rep_priv *uplink_rpriv;
5479         struct metadata_dst *tun_dst;
5480         struct tunnel_match_key key;
5481         u32 tun_id, enc_opts_id;
5482         struct net_device *dev;
5483         int err;
5484
5485         enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
5486         tun_id = tunnel_id >> ENC_OPTS_BITS;
5487
5488         if (!tun_id)
5489                 return true;
5490
5491         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5492         uplink_priv = &uplink_rpriv->uplink_priv;
5493
5494         err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
5495         if (err) {
5496                 netdev_dbg(priv->netdev,
5497                            "Couldn't find tunnel for tun_id: %d, err: %d\n",
5498                            tun_id, err);
5499                 return false;
5500         }
5501
5502         if (enc_opts_id) {
5503                 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
5504                                    enc_opts_id, &enc_opts);
5505                 if (err) {
5506                         netdev_dbg(priv->netdev,
5507                                    "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
5508                                    enc_opts_id, err);
5509                         return false;
5510                 }
5511         }
5512
5513         switch (key.enc_control.addr_type) {
5514         case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
5515                 tun_dst = __ip_tun_set_dst(key.enc_ipv4.src, key.enc_ipv4.dst,
5516                                            key.enc_ip.tos, key.enc_ip.ttl,
5517                                            key.enc_tp.dst, TUNNEL_KEY,
5518                                            key32_to_tunnel_id(key.enc_key_id.keyid),
5519                                            enc_opts.key.len);
5520                 break;
5521         case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
5522                 tun_dst = __ipv6_tun_set_dst(&key.enc_ipv6.src, &key.enc_ipv6.dst,
5523                                              key.enc_ip.tos, key.enc_ip.ttl,
5524                                              key.enc_tp.dst, 0, TUNNEL_KEY,
5525                                              key32_to_tunnel_id(key.enc_key_id.keyid),
5526                                              enc_opts.key.len);
5527                 break;
5528         default:
5529                 netdev_dbg(priv->netdev,
5530                            "Couldn't restore tunnel, unsupported addr_type: %d\n",
5531                            key.enc_control.addr_type);
5532                 return false;
5533         }
5534
5535         if (!tun_dst) {
5536                 netdev_dbg(priv->netdev, "Couldn't restore tunnel, no tun_dst\n");
5537                 return false;
5538         }
5539
5540         tun_dst->u.tun_info.key.tp_src = key.enc_tp.src;
5541
5542         if (enc_opts.key.len)
5543                 ip_tunnel_info_opts_set(&tun_dst->u.tun_info,
5544                                         enc_opts.key.data,
5545                                         enc_opts.key.len,
5546                                         enc_opts.key.dst_opt_type);
5547
5548         skb_dst_set(skb, (struct dst_entry *)tun_dst);
5549         dev = dev_get_by_index(&init_net, key.filter_ifindex);
5550         if (!dev) {
5551                 netdev_dbg(priv->netdev,
5552                            "Couldn't find tunnel device with ifindex: %d\n",
5553                            key.filter_ifindex);
5554                 return false;
5555         }
5556
5557         /* Set fwd_dev so we do dev_put() after datapath */
5558         tc_priv->fwd_dev = dev;
5559
5560         skb->dev = dev;
5561
5562         return true;
5563 }
5564
5565 static bool mlx5e_tc_restore_skb_tc_meta(struct sk_buff *skb, struct mlx5_tc_ct_priv *ct_priv,
5566                                          struct mlx5_mapped_obj *mapped_obj, u32 zone_restore_id,
5567                                          u32 tunnel_id,  struct mlx5e_tc_update_priv *tc_priv)
5568 {
5569         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5570         struct tc_skb_ext *tc_skb_ext;
5571         u64 act_miss_cookie;
5572         u32 chain;
5573
5574         chain = mapped_obj->type == MLX5_MAPPED_OBJ_CHAIN ? mapped_obj->chain : 0;
5575         act_miss_cookie = mapped_obj->type == MLX5_MAPPED_OBJ_ACT_MISS ?
5576                           mapped_obj->act_miss_cookie : 0;
5577         if (chain || act_miss_cookie) {
5578                 if (!mlx5e_tc_ct_restore_flow(ct_priv, skb, zone_restore_id))
5579                         return false;
5580
5581                 tc_skb_ext = tc_skb_ext_alloc(skb);
5582                 if (!tc_skb_ext) {
5583                         WARN_ON(1);
5584                         return false;
5585                 }
5586
5587                 if (act_miss_cookie) {
5588                         tc_skb_ext->act_miss_cookie = act_miss_cookie;
5589                         tc_skb_ext->act_miss = 1;
5590                 } else {
5591                         tc_skb_ext->chain = chain;
5592                 }
5593         }
5594
5595         if (tc_priv)
5596                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5597
5598         return true;
5599 }
5600
5601 static void mlx5e_tc_restore_skb_sample(struct mlx5e_priv *priv, struct sk_buff *skb,
5602                                         struct mlx5_mapped_obj *mapped_obj,
5603                                         struct mlx5e_tc_update_priv *tc_priv)
5604 {
5605         if (!mlx5e_tc_restore_tunnel(priv, skb, tc_priv, mapped_obj->sample.tunnel_id)) {
5606                 netdev_dbg(priv->netdev,
5607                            "Failed to restore tunnel info for sampled packet\n");
5608                 return;
5609         }
5610         mlx5e_tc_sample_skb(skb, mapped_obj);
5611 }
5612
5613 static bool mlx5e_tc_restore_skb_int_port(struct mlx5e_priv *priv, struct sk_buff *skb,
5614                                           struct mlx5_mapped_obj *mapped_obj,
5615                                           struct mlx5e_tc_update_priv *tc_priv,
5616                                           u32 tunnel_id)
5617 {
5618         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5619         struct mlx5_rep_uplink_priv *uplink_priv;
5620         struct mlx5e_rep_priv *uplink_rpriv;
5621         bool forward_tx = false;
5622
5623         /* Tunnel restore takes precedence over int port restore */
5624         if (tunnel_id)
5625                 return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5626
5627         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5628         uplink_priv = &uplink_rpriv->uplink_priv;
5629
5630         if (mlx5e_tc_int_port_dev_fwd(uplink_priv->int_port_priv, skb,
5631                                       mapped_obj->int_port_metadata, &forward_tx)) {
5632                 /* Set fwd_dev for future dev_put */
5633                 tc_priv->fwd_dev = skb->dev;
5634                 tc_priv->forward_tx = forward_tx;
5635
5636                 return true;
5637         }
5638
5639         return false;
5640 }
5641
5642 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
5643                          struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
5644                          struct mlx5_tc_ct_priv *ct_priv,
5645                          u32 zone_restore_id, u32 tunnel_id,
5646                          struct mlx5e_tc_update_priv *tc_priv)
5647 {
5648         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5649         struct mlx5_mapped_obj mapped_obj;
5650         int err;
5651
5652         err = mapping_find(mapping_ctx, mapped_obj_id, &mapped_obj);
5653         if (err) {
5654                 netdev_dbg(skb->dev,
5655                            "Couldn't find mapped object for mapped_obj_id: %d, err: %d\n",
5656                            mapped_obj_id, err);
5657                 return false;
5658         }
5659
5660         switch (mapped_obj.type) {
5661         case MLX5_MAPPED_OBJ_CHAIN:
5662         case MLX5_MAPPED_OBJ_ACT_MISS:
5663                 return mlx5e_tc_restore_skb_tc_meta(skb, ct_priv, &mapped_obj, zone_restore_id,
5664                                                     tunnel_id, tc_priv);
5665         case MLX5_MAPPED_OBJ_SAMPLE:
5666                 mlx5e_tc_restore_skb_sample(priv, skb, &mapped_obj, tc_priv);
5667                 tc_priv->skb_done = true;
5668                 return true;
5669         case MLX5_MAPPED_OBJ_INT_PORT_METADATA:
5670                 return mlx5e_tc_restore_skb_int_port(priv, skb, &mapped_obj, tc_priv, tunnel_id);
5671         default:
5672                 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5673                 return false;
5674         }
5675
5676         return false;
5677 }
5678
5679 bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
5680 {
5681         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5682         u32 mapped_obj_id, reg_b, zone_restore_id;
5683         struct mlx5_tc_ct_priv *ct_priv;
5684         struct mapping_ctx *mapping_ctx;
5685         struct mlx5e_tc_table *tc;
5686
5687         reg_b = be32_to_cpu(cqe->ft_metadata);
5688         tc = mlx5e_fs_get_tc(priv->fs);
5689         mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5690         zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5691                           ESW_ZONE_ID_MASK;
5692         ct_priv = tc->ct;
5693         mapping_ctx = tc->mapping;
5694
5695         return mlx5e_tc_update_skb(cqe, skb, mapping_ctx, mapped_obj_id, ct_priv, zone_restore_id,
5696                                    0, NULL);
5697 }
5698
5699 static struct mapping_ctx *
5700 mlx5e_get_priv_obj_mapping(struct mlx5e_priv *priv)
5701 {
5702         struct mlx5e_tc_table *tc;
5703         struct mlx5_eswitch *esw;
5704         struct mapping_ctx *ctx;
5705
5706         if (is_mdev_switchdev_mode(priv->mdev)) {
5707                 esw = priv->mdev->priv.eswitch;
5708                 ctx = esw->offloads.reg_c0_obj_pool;
5709         } else {
5710                 tc = mlx5e_fs_get_tc(priv->fs);
5711                 ctx = tc->mapping;
5712         }
5713
5714         return ctx;
5715 }
5716
5717 int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5718                                      u64 act_miss_cookie, u32 *act_miss_mapping)
5719 {
5720         struct mlx5_mapped_obj mapped_obj = {};
5721         struct mlx5_eswitch *esw;
5722         struct mapping_ctx *ctx;
5723         int err;
5724
5725         ctx = mlx5e_get_priv_obj_mapping(priv);
5726         mapped_obj.type = MLX5_MAPPED_OBJ_ACT_MISS;
5727         mapped_obj.act_miss_cookie = act_miss_cookie;
5728         err = mapping_add(ctx, &mapped_obj, act_miss_mapping);
5729         if (err)
5730                 return err;
5731
5732         if (!is_mdev_switchdev_mode(priv->mdev))
5733                 return 0;
5734
5735         esw = priv->mdev->priv.eswitch;
5736         attr->act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);
5737         if (IS_ERR(attr->act_id_restore_rule)) {
5738                 err = PTR_ERR(attr->act_id_restore_rule);
5739                 goto err_rule;
5740         }
5741
5742         return 0;
5743
5744 err_rule:
5745         mapping_remove(ctx, *act_miss_mapping);
5746         return err;
5747 }
5748
5749 void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5750                                       u32 act_miss_mapping)
5751 {
5752         struct mapping_ctx *ctx = mlx5e_get_priv_obj_mapping(priv);
5753
5754         if (is_mdev_switchdev_mode(priv->mdev))
5755                 mlx5_del_flow_rules(attr->act_id_restore_rule);
5756         mapping_remove(ctx, act_miss_mapping);
5757 }