drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/flow_offload.h>
  35 #include <net/sch_generic.h>
  36 #include <net/pkt_cls.h>
  37 #include <linux/mlx5/fs.h>
  38 #include <linux/mlx5/device.h>
  39 #include <linux/rhashtable.h>
  40 #include <linux/refcount.h>
  41 #include <linux/completion.h>
  42 #include <net/arp.h>
  43 #include <net/ipv6_stubs.h>
  44 #include <net/bareudp.h>
  45 #include <net/bonding.h>
  46 #include "en.h"
  47 #include "en/tc/post_act.h"
  48 #include "en_rep.h"
  49 #include "en/rep/tc.h"
  50 #include "en/rep/neigh.h"
  51 #include "en_tc.h"
  52 #include "eswitch.h"
  53 #include "fs_core.h"
  54 #include "en/port.h"
  55 #include "en/tc_tun.h"
  56 #include "en/mapping.h"
  57 #include "en/tc_ct.h"
  58 #include "en/mod_hdr.h"
  59 #include "en/tc_tun_encap.h"
  60 #include "en/tc/sample.h"
  61 #include "en/tc/act/act.h"
  62 #include "en/tc/post_meter.h"
  63 #include "lib/devcom.h"
  64 #include "lib/geneve.h"
  65 #include "lib/fs_chains.h"
  66 #include "diag/en_tc_tracepoint.h"
  67 #include <asm/div64.h>
  68 #include "lag/lag.h"
  69 #include "lag/mp.h"
  70
  71 #define MLX5E_TC_TABLE_NUM_GROUPS 4
  72 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
  73
  74 struct mlx5e_hairpin_params {
  75         struct mlx5_core_dev *mdev;
  76         u32 num_queues;
  77         u32 queue_size;
  78 };
  79
  80 struct mlx5e_tc_table {
  81         /* Protects the dynamic assignment of the t parameter
  82          * which is the nic tc root table.
  83          */
  84         struct mutex                    t_lock;
  85         struct mlx5e_priv               *priv;
  86         struct mlx5_flow_table          *t;
  87         struct mlx5_flow_table          *miss_t;
  88         struct mlx5_fs_chains           *chains;
  89         struct mlx5e_post_act           *post_act;
  90
  91         struct rhashtable               ht;
  92
  93         struct mod_hdr_tbl mod_hdr;
  94         struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
  95         DECLARE_HASHTABLE(hairpin_tbl, 8);
  96
  97         struct notifier_block     netdevice_nb;
  98         struct netdev_net_notifier      netdevice_nn;
  99
 100         struct mlx5_tc_ct_priv         *ct;
 101         struct mapping_ctx             *mapping;
 102         struct mlx5e_hairpin_params    hairpin_params;
 103         struct dentry                  *dfs_root;
 104 };
 105
 106 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
 107         [CHAIN_TO_REG] = {
 108                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 109                 .moffset = 0,
 110                 .mlen = 16,
 111         },
 112         [VPORT_TO_REG] = {
 113                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 114                 .moffset = 16,
 115                 .mlen = 16,
 116         },
 117         [TUNNEL_TO_REG] = {
 118                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
 119                 .moffset = 8,
 120                 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
 121                 .soffset = MLX5_BYTE_OFF(fte_match_param,
 122                                          misc_parameters_2.metadata_reg_c_1),
 123         },
 124         [ZONE_TO_REG] = zone_to_reg_ct,
 125         [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
 126         [CTSTATE_TO_REG] = ctstate_to_reg_ct,
 127         [MARK_TO_REG] = mark_to_reg_ct,
 128         [LABELS_TO_REG] = labels_to_reg_ct,
 129         [FTEID_TO_REG] = fteid_to_reg_ct,
 130         /* For NIC rules we store the restore metadata directly
 131          * into reg_b that is passed to SW since we don't
 132          * jump between steering domains.
 133          */
 134         [NIC_CHAIN_TO_REG] = {
 135                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
 136                 .moffset = 0,
 137                 .mlen = 16,
 138         },
 139         [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
 140         [PACKET_COLOR_TO_REG] = packet_color_to_reg,
 141 };
 142
 143 struct mlx5e_tc_jump_state {
 144         u32 jump_count;
 145         bool jump_target;
 146         struct mlx5_flow_attr *jumping_attr;
 147
 148         enum flow_action_id last_id;
 149         u32 last_index;
 150 };
 151
 152 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
 153 {
 154         struct mlx5e_tc_table *tc;
 155
 156         tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
 157         return tc ? tc : ERR_PTR(-ENOMEM);
 158 }
 159
 160 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
 161 {
 162         kvfree(tc);
 163 }
 164
 165 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
 166 {
 167         return tc->chains;
 168 }
 169
 170 /* To avoid false lock dependency warning set the tc_ht lock
 171  * class different than the lock class of the ht being used when deleting
 172  * last flow from a group and then deleting a group, we get into del_sw_flow_group()
 173  * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
 174  * it's different than the ht->mutex here.
 175  */
 176 static struct lock_class_key tc_ht_lock_key;
 177
 178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
 179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
 180 static void mlx5_free_flow_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr);
 181
 182 void
 183 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 184                             enum mlx5e_tc_attr_to_reg type,
 185                             u32 val,
 186                             u32 mask)
 187 {
 188         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 189         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 190         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 191         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 192         u32 max_mask = GENMASK(match_len - 1, 0);
 193         __be32 curr_mask_be, curr_val_be;
 194         u32 curr_mask, curr_val;
 195
 196         fmask = headers_c + soffset;
 197         fval = headers_v + soffset;
 198
 199         memcpy(&curr_mask_be, fmask, 4);
 200         memcpy(&curr_val_be, fval, 4);
 201
 202         curr_mask = be32_to_cpu(curr_mask_be);
 203         curr_val = be32_to_cpu(curr_val_be);
 204
 205         //move to correct offset
 206         WARN_ON(mask > max_mask);
 207         mask <<= moffset;
 208         val <<= moffset;
 209         max_mask <<= moffset;
 210
 211         //zero val and mask
 212         curr_mask &= ~max_mask;
 213         curr_val &= ~max_mask;
 214
 215         //add current to mask
 216         curr_mask |= mask;
 217         curr_val |= val;
 218
 219         //back to be32 and write
 220         curr_mask_be = cpu_to_be32(curr_mask);
 221         curr_val_be = cpu_to_be32(curr_val);
 222
 223         memcpy(fmask, &curr_mask_be, 4);
 224         memcpy(fval, &curr_val_be, 4);
 225
 226         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
 227 }
 228
 229 void
 230 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
 231                                 enum mlx5e_tc_attr_to_reg type,
 232                                 u32 *val,
 233                                 u32 *mask)
 234 {
 235         void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
 236         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 237         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 238         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 239         u32 max_mask = GENMASK(match_len - 1, 0);
 240         __be32 curr_mask_be, curr_val_be;
 241         u32 curr_mask, curr_val;
 242
 243         fmask = headers_c + soffset;
 244         fval = headers_v + soffset;
 245
 246         memcpy(&curr_mask_be, fmask, 4);
 247         memcpy(&curr_val_be, fval, 4);
 248
 249         curr_mask = be32_to_cpu(curr_mask_be);
 250         curr_val = be32_to_cpu(curr_val_be);
 251
 252         *mask = (curr_mask >> moffset) & max_mask;
 253         *val = (curr_val >> moffset) & max_mask;
 254 }
 255
 256 int
 257 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
 258                                      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 259                                      enum mlx5_flow_namespace_type ns,
 260                                      enum mlx5e_tc_attr_to_reg type,
 261                                      u32 data)
 262 {
 263         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 264         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 265         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 266         char *modact;
 267         int err;
 268
 269         modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
 270         if (IS_ERR(modact))
 271                 return PTR_ERR(modact);
 272
 273         /* Firmware has 5bit length field and 0 means 32bits */
 274         if (mlen == 32)
 275                 mlen = 0;
 276
 277         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 278         MLX5_SET(set_action_in, modact, field, mfield);
 279         MLX5_SET(set_action_in, modact, offset, moffset);
 280         MLX5_SET(set_action_in, modact, length, mlen);
 281         MLX5_SET(set_action_in, modact, data, data);
 282         err = mod_hdr_acts->num_actions;
 283         mod_hdr_acts->num_actions++;
 284
 285         return err;
 286 }
 287
 288 struct mlx5e_tc_int_port_priv *
 289 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
 290 {
 291         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 292         struct mlx5_rep_uplink_priv *uplink_priv;
 293         struct mlx5e_rep_priv *uplink_rpriv;
 294
 295         if (is_mdev_switchdev_mode(priv->mdev)) {
 296                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 297                 uplink_priv = &uplink_rpriv->uplink_priv;
 298
 299                 return uplink_priv->int_port_priv;
 300         }
 301
 302         return NULL;
 303 }
 304
 305 struct mlx5e_flow_meters *
 306 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
 307 {
 308         struct mlx5_eswitch *esw = dev->priv.eswitch;
 309         struct mlx5_rep_uplink_priv *uplink_priv;
 310         struct mlx5e_rep_priv *uplink_rpriv;
 311         struct mlx5e_priv *priv;
 312
 313         if (is_mdev_switchdev_mode(dev)) {
 314                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 315                 uplink_priv = &uplink_rpriv->uplink_priv;
 316                 priv = netdev_priv(uplink_rpriv->netdev);
 317                 if (!uplink_priv->flow_meters)
 318                         uplink_priv->flow_meters =
 319                                 mlx5e_flow_meters_init(priv,
 320                                                        MLX5_FLOW_NAMESPACE_FDB,
 321                                                        uplink_priv->post_act);
 322                 if (!IS_ERR(uplink_priv->flow_meters))
 323                         return uplink_priv->flow_meters;
 324         }
 325
 326         return NULL;
 327 }
 328
 329 static struct mlx5_tc_ct_priv *
 330 get_ct_priv(struct mlx5e_priv *priv)
 331 {
 332         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 333         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 334         struct mlx5_rep_uplink_priv *uplink_priv;
 335         struct mlx5e_rep_priv *uplink_rpriv;
 336
 337         if (is_mdev_switchdev_mode(priv->mdev)) {
 338                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 339                 uplink_priv = &uplink_rpriv->uplink_priv;
 340
 341                 return uplink_priv->ct_priv;
 342         }
 343
 344         return tc->ct;
 345 }
 346
 347 static struct mlx5e_tc_psample *
 348 get_sample_priv(struct mlx5e_priv *priv)
 349 {
 350         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 351         struct mlx5_rep_uplink_priv *uplink_priv;
 352         struct mlx5e_rep_priv *uplink_rpriv;
 353
 354         if (is_mdev_switchdev_mode(priv->mdev)) {
 355                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 356                 uplink_priv = &uplink_rpriv->uplink_priv;
 357
 358                 return uplink_priv->tc_psample;
 359         }
 360
 361         return NULL;
 362 }
 363
 364 static struct mlx5e_post_act *
 365 get_post_action(struct mlx5e_priv *priv)
 366 {
 367         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 368         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 369         struct mlx5_rep_uplink_priv *uplink_priv;
 370         struct mlx5e_rep_priv *uplink_rpriv;
 371
 372         if (is_mdev_switchdev_mode(priv->mdev)) {
 373                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
 374                 uplink_priv = &uplink_rpriv->uplink_priv;
 375
 376                 return uplink_priv->post_act;
 377         }
 378
 379         return tc->post_act;
 380 }
 381
 382 struct mlx5_flow_handle *
 383 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
 384                     struct mlx5_flow_spec *spec,
 385                     struct mlx5_flow_attr *attr)
 386 {
 387         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 388
 389         if (is_mdev_switchdev_mode(priv->mdev))
 390                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 391
 392         return  mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 393 }
 394
 395 void
 396 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
 397                     struct mlx5_flow_handle *rule,
 398                     struct mlx5_flow_attr *attr)
 399 {
 400         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 401
 402         if (is_mdev_switchdev_mode(priv->mdev)) {
 403                 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 404                 return;
 405         }
 406
 407         mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 408 }
 409
 410 static bool
 411 is_flow_meter_action(struct mlx5_flow_attr *attr)
 412 {
 413         return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
 414                  (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
 415                 attr->flags & MLX5_ATTR_FLAG_MTU);
 416 }
 417
 418 static int
 419 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
 420                         struct mlx5_flow_attr *attr)
 421 {
 422         struct mlx5e_post_act *post_act = get_post_action(priv);
 423         struct mlx5e_post_meter_priv *post_meter;
 424         enum mlx5_flow_namespace_type ns_type;
 425         struct mlx5e_flow_meter_handle *meter;
 426         enum mlx5e_post_meter_type type;
 427
 428         meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
 429         if (IS_ERR(meter)) {
 430                 mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
 431                 return PTR_ERR(meter);
 432         }
 433
 434         ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
 435         type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
 436         post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
 437                                            type,
 438                                            meter->act_counter, meter->drop_counter,
 439                                            attr->branch_true, attr->branch_false);
 440         if (IS_ERR(post_meter)) {
 441                 mlx5_core_err(priv->mdev, "Failed to init post meter\n");
 442                 goto err_meter_init;
 443         }
 444
 445         attr->meter_attr.meter = meter;
 446         attr->meter_attr.post_meter = post_meter;
 447         attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
 448         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
 449
 450         return 0;
 451
 452 err_meter_init:
 453         mlx5e_tc_meter_put(meter);
 454         return PTR_ERR(post_meter);
 455 }
 456
 457 static void
 458 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
 459 {
 460         mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
 461         mlx5e_tc_meter_put(attr->meter_attr.meter);
 462 }
 463
 464 struct mlx5_flow_handle *
 465 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
 466                       struct mlx5_flow_spec *spec,
 467                       struct mlx5_flow_attr *attr)
 468 {
 469         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 470         int err;
 471
 472         if (attr->flags & MLX5_ATTR_FLAG_CT) {
 473                 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts =
 474                         &attr->parse_attr->mod_hdr_acts;
 475
 476                 return mlx5_tc_ct_flow_offload(get_ct_priv(priv),
 477                                                spec, attr,
 478                                                mod_hdr_acts);
 479         }
 480
 481         if (!is_mdev_switchdev_mode(priv->mdev))
 482                 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
 483
 484         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
 485                 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
 486
 487         if (is_flow_meter_action(attr)) {
 488                 err = mlx5e_tc_add_flow_meter(priv, attr);
 489                 if (err)
 490                         return ERR_PTR(err);
 491         }
 492
 493         return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
 494 }
 495
 496 void
 497 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
 498                         struct mlx5_flow_handle *rule,
 499                         struct mlx5_flow_attr *attr)
 500 {
 501         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 502
 503         if (attr->flags & MLX5_ATTR_FLAG_CT) {
 504                 mlx5_tc_ct_delete_flow(get_ct_priv(priv), attr);
 505                 return;
 506         }
 507
 508         if (!is_mdev_switchdev_mode(priv->mdev)) {
 509                 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
 510                 return;
 511         }
 512
 513         if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
 514                 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
 515                 return;
 516         }
 517
 518         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
 519
 520         if (attr->meter_attr.meter)
 521                 mlx5e_tc_del_flow_meter(esw, attr);
 522 }
 523
 524 int
 525 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 526                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 527                           enum mlx5_flow_namespace_type ns,
 528                           enum mlx5e_tc_attr_to_reg type,
 529                           u32 data)
 530 {
 531         int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
 532
 533         return ret < 0 ? ret : 0;
 534 }
 535
 536 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
 537                                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 538                                           enum mlx5e_tc_attr_to_reg type,
 539                                           int act_id, u32 data)
 540 {
 541         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 542         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 543         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 544         char *modact;
 545
 546         modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
 547
 548         /* Firmware has 5bit length field and 0 means 32bits */
 549         if (mlen == 32)
 550                 mlen = 0;
 551
 552         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 553         MLX5_SET(set_action_in, modact, field, mfield);
 554         MLX5_SET(set_action_in, modact, offset, moffset);
 555         MLX5_SET(set_action_in, modact, length, mlen);
 556         MLX5_SET(set_action_in, modact, data, data);
 557 }
 558
 559 struct mlx5e_hairpin {
 560         struct mlx5_hairpin *pair;
 561
 562         struct mlx5_core_dev *func_mdev;
 563         struct mlx5e_priv *func_priv;
 564         u32 tdn;
 565         struct mlx5e_tir direct_tir;
 566
 567         int num_channels;
 568         struct mlx5e_rqt indir_rqt;
 569         struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
 570         struct mlx5_ttc_table *ttc;
 571 };
 572
 573 struct mlx5e_hairpin_entry {
 574         /* a node of a hash table which keeps all the  hairpin entries */
 575         struct hlist_node hairpin_hlist;
 576
 577         /* protects flows list */
 578         spinlock_t flows_lock;
 579         /* flows sharing the same hairpin */
 580         struct list_head flows;
 581         /* hpe's that were not fully initialized when dead peer update event
 582          * function traversed them.
 583          */
 584         struct list_head dead_peer_wait_list;
 585
 586         u16 peer_vhca_id;
 587         u8 prio;
 588         struct mlx5e_hairpin *hp;
 589         refcount_t refcnt;
 590         struct completion res_ready;
 591 };
 592
 593 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 594                               struct mlx5e_tc_flow *flow);
 595
 596 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 597 {
 598         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 599                 return ERR_PTR(-EINVAL);
 600         return flow;
 601 }
 602
 603 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 604 {
 605         if (refcount_dec_and_test(&flow->refcnt)) {
 606                 mlx5e_tc_del_flow(priv, flow);
 607                 kfree_rcu(flow, rcu_head);
 608         }
 609 }
 610
 611 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 612 {
 613         return flow_flag_test(flow, ESWITCH);
 614 }
 615
 616 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 617 {
 618         return flow_flag_test(flow, FT);
 619 }
 620
 621 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 622 {
 623         return flow_flag_test(flow, OFFLOADED);
 624 }
 625
 626 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
 627 {
 628         return mlx5e_is_eswitch_flow(flow) ?
 629                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 630 }
 631
 632 static struct mlx5_core_dev *
 633 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
 634 {
 635         return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
 636 }
 637
 638 static struct mod_hdr_tbl *
 639 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
 640 {
 641         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 642         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 643
 644         return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
 645                 &esw->offloads.mod_hdr :
 646                 &tc->mod_hdr;
 647 }
 648
 649 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 650                                 struct mlx5e_tc_flow *flow,
 651                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 652 {
 653         struct mlx5_modify_hdr *modify_hdr;
 654         struct mlx5e_mod_hdr_handle *mh;
 655
 656         mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
 657                                   mlx5e_get_flow_namespace(flow),
 658                                   &parse_attr->mod_hdr_acts);
 659         if (IS_ERR(mh))
 660                 return PTR_ERR(mh);
 661
 662         modify_hdr = mlx5e_mod_hdr_get(mh);
 663         flow->attr->modify_hdr = modify_hdr;
 664         flow->mh = mh;
 665
 666         return 0;
 667 }
 668
 669 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 670                                  struct mlx5e_tc_flow *flow)
 671 {
 672         /* flow wasn't fully initialized */
 673         if (!flow->mh)
 674                 return;
 675
 676         mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
 677                              flow->mh);
 678         flow->mh = NULL;
 679 }
 680
 681 static
 682 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 683 {
 684         struct mlx5_core_dev *mdev;
 685         struct net_device *netdev;
 686         struct mlx5e_priv *priv;
 687
 688         netdev = dev_get_by_index(net, ifindex);
 689         if (!netdev)
 690                 return ERR_PTR(-ENODEV);
 691
 692         priv = netdev_priv(netdev);
 693         mdev = priv->mdev;
 694         dev_put(netdev);
 695
 696         /* Mirred tc action holds a refcount on the ifindex net_device (see
 697          * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
 698          * after dev_put(netdev), while we're in the context of adding a tc flow.
 699          *
 700          * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
 701          * stored in a hairpin object, which exists until all flows, that refer to it, get
 702          * removed.
 703          *
 704          * On the other hand, after a hairpin object has been created, the peer net_device may
 705          * be removed/unbound while there are still some hairpin flows that are using it. This
 706          * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
 707          * NETDEV_UNREGISTER event of the peer net_device.
 708          */
 709         return mdev;
 710 }
 711
 712 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 713 {
 714         struct mlx5e_tir_builder *builder;
 715         int err;
 716
 717         builder = mlx5e_tir_builder_alloc(false);
 718         if (!builder)
 719                 return -ENOMEM;
 720
 721         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 722         if (err)
 723                 goto out;
 724
 725         mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
 726         err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
 727         if (err)
 728                 goto create_tir_err;
 729
 730 out:
 731         mlx5e_tir_builder_free(builder);
 732         return err;
 733
 734 create_tir_err:
 735         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 736
 737         goto out;
 738 }
 739
 740 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 741 {
 742         mlx5e_tir_destroy(&hp->direct_tir);
 743         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 744 }
 745
 746 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 747 {
 748         struct mlx5e_priv *priv = hp->func_priv;
 749         struct mlx5_core_dev *mdev = priv->mdev;
 750         struct mlx5e_rss_params_indir *indir;
 751         int err;
 752
 753         indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
 754         if (!indir)
 755                 return -ENOMEM;
 756
 757         mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
 758         err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
 759                                    mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
 760                                    indir);
 761
 762         kvfree(indir);
 763         return err;
 764 }
 765
 766 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 767 {
 768         struct mlx5e_priv *priv = hp->func_priv;
 769         struct mlx5e_rss_params_hash rss_hash;
 770         enum mlx5_traffic_types tt, max_tt;
 771         struct mlx5e_tir_builder *builder;
 772         int err = 0;
 773
 774         builder = mlx5e_tir_builder_alloc(false);
 775         if (!builder)
 776                 return -ENOMEM;
 777
 778         rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
 779
 780         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 781                 struct mlx5e_rss_params_traffic_type rss_tt;
 782
 783                 rss_tt = mlx5e_rss_get_default_tt_config(tt);
 784
 785                 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
 786                                             mlx5e_rqt_get_rqtn(&hp->indir_rqt),
 787                                             false);
 788                 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
 789
 790                 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
 791                 if (err) {
 792                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 793                         goto err_destroy_tirs;
 794                 }
 795
 796                 mlx5e_tir_builder_clear(builder);
 797         }
 798
 799 out:
 800         mlx5e_tir_builder_free(builder);
 801         return err;
 802
 803 err_destroy_tirs:
 804         max_tt = tt;
 805         for (tt = 0; tt < max_tt; tt++)
 806                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 807
 808         goto out;
 809 }
 810
 811 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 812 {
 813         int tt;
 814
 815         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 816                 mlx5e_tir_destroy(&hp->indir_tir[tt]);
 817 }
 818
 819 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 820                                          struct ttc_params *ttc_params)
 821 {
 822         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 823         int tt;
 824
 825         memset(ttc_params, 0, sizeof(*ttc_params));
 826
 827         ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
 828                                                  MLX5_FLOW_NAMESPACE_KERNEL);
 829         for (tt = 0; tt < MLX5_NUM_TT; tt++) {
 830                 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 831                 ttc_params->dests[tt].tir_num =
 832                         tt == MLX5_TT_ANY ?
 833                                 mlx5e_tir_get_tirn(&hp->direct_tir) :
 834                                 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
 835         }
 836
 837         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 838         ft_attr->prio = MLX5E_TC_PRIO;
 839 }
 840
 841 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 842 {
 843         struct mlx5e_priv *priv = hp->func_priv;
 844         struct ttc_params ttc_params;
 845         struct mlx5_ttc_table *ttc;
 846         int err;
 847
 848         err = mlx5e_hairpin_create_indirect_rqt(hp);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_hairpin_create_indirect_tirs(hp);
 853         if (err)
 854                 goto err_create_indirect_tirs;
 855
 856         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 857         hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
 858         if (IS_ERR(hp->ttc)) {
 859                 err = PTR_ERR(hp->ttc);
 860                 goto err_create_ttc_table;
 861         }
 862
 863         ttc = mlx5e_fs_get_ttc(priv->fs, false);
 864         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 865                    hp->num_channels,
 866                    mlx5_get_ttc_flow_table(ttc)->id);
 867
 868         return 0;
 869
 870 err_create_ttc_table:
 871         mlx5e_hairpin_destroy_indirect_tirs(hp);
 872 err_create_indirect_tirs:
 873         mlx5e_rqt_destroy(&hp->indir_rqt);
 874
 875         return err;
 876 }
 877
 878 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 879 {
 880         mlx5_destroy_ttc_table(hp->ttc);
 881         mlx5e_hairpin_destroy_indirect_tirs(hp);
 882         mlx5e_rqt_destroy(&hp->indir_rqt);
 883 }
 884
 885 static struct mlx5e_hairpin *
 886 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 887                      int peer_ifindex)
 888 {
 889         struct mlx5_core_dev *func_mdev, *peer_mdev;
 890         struct mlx5e_hairpin *hp;
 891         struct mlx5_hairpin *pair;
 892         int err;
 893
 894         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 895         if (!hp)
 896                 return ERR_PTR(-ENOMEM);
 897
 898         func_mdev = priv->mdev;
 899         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 900         if (IS_ERR(peer_mdev)) {
 901                 err = PTR_ERR(peer_mdev);
 902                 goto create_pair_err;
 903         }
 904
 905         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 906         if (IS_ERR(pair)) {
 907                 err = PTR_ERR(pair);
 908                 goto create_pair_err;
 909         }
 910         hp->pair = pair;
 911         hp->func_mdev = func_mdev;
 912         hp->func_priv = priv;
 913         hp->num_channels = params->num_channels;
 914
 915         err = mlx5e_hairpin_create_transport(hp);
 916         if (err)
 917                 goto create_transport_err;
 918
 919         if (hp->num_channels > 1) {
 920                 err = mlx5e_hairpin_rss_init(hp);
 921                 if (err)
 922                         goto rss_init_err;
 923         }
 924
 925         return hp;
 926
 927 rss_init_err:
 928         mlx5e_hairpin_destroy_transport(hp);
 929 create_transport_err:
 930         mlx5_core_hairpin_destroy(hp->pair);
 931 create_pair_err:
 932         kfree(hp);
 933         return ERR_PTR(err);
 934 }
 935
 936 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 937 {
 938         if (hp->num_channels > 1)
 939                 mlx5e_hairpin_rss_cleanup(hp);
 940         mlx5e_hairpin_destroy_transport(hp);
 941         mlx5_core_hairpin_destroy(hp->pair);
 942         kvfree(hp);
 943 }
 944
 945 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 946 {
 947         return (peer_vhca_id << 16 | prio);
 948 }
 949
 950 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 951                                                      u16 peer_vhca_id, u8 prio)
 952 {
 953         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 954         struct mlx5e_hairpin_entry *hpe;
 955         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 956
 957         hash_for_each_possible(tc->hairpin_tbl, hpe,
 958                                hairpin_hlist, hash_key) {
 959                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 960                         refcount_inc(&hpe->refcnt);
 961                         return hpe;
 962                 }
 963         }
 964
 965         return NULL;
 966 }
 967
 968 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 969                               struct mlx5e_hairpin_entry *hpe)
 970 {
 971         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
 972         /* no more hairpin flows for us, release the hairpin pair */
 973         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
 974                 return;
 975         hash_del(&hpe->hairpin_hlist);
 976         mutex_unlock(&tc->hairpin_tbl_lock);
 977
 978         if (!IS_ERR_OR_NULL(hpe->hp)) {
 979                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 980                            dev_name(hpe->hp->pair->peer_mdev->device));
 981
 982                 mlx5e_hairpin_destroy(hpe->hp);
 983         }
 984
 985         WARN_ON(!list_empty(&hpe->flows));
 986         kfree(hpe);
 987 }
 988
 989 #define UNKNOWN_MATCH_PRIO 8
 990
 991 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 992                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 993                                   struct netlink_ext_ack *extack)
 994 {
 995         void *headers_c, *headers_v;
 996         u8 prio_val, prio_mask = 0;
 997         bool vlan_present;
 998
 999 #ifdef CONFIG_MLX5_CORE_EN_DCB
1000         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1001                 NL_SET_ERR_MSG_MOD(extack,
1002                                    "only PCP trust state supported for hairpin");
1003                 return -EOPNOTSUPP;
1004         }
1005 #endif
1006         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1007         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1008
1009         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1010         if (vlan_present) {
1011                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1012                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1013         }
1014
1015         if (!vlan_present || !prio_mask) {
1016                 prio_val = UNKNOWN_MATCH_PRIO;
1017         } else if (prio_mask != 0x7) {
1018                 NL_SET_ERR_MSG_MOD(extack,
1019                                    "masked priority match not supported for hairpin");
1020                 return -EOPNOTSUPP;
1021         }
1022
1023         *match_prio = prio_val;
1024         return 0;
1025 }
1026
1027 static int debugfs_hairpin_queues_set(void *data, u64 val)
1028 {
1029         struct mlx5e_hairpin_params *hp = data;
1030
1031         if (!val) {
1032                 mlx5_core_err(hp->mdev,
1033                               "Number of hairpin queues must be > 0\n");
1034                 return -EINVAL;
1035         }
1036
1037         hp->num_queues = val;
1038
1039         return 0;
1040 }
1041
1042 static int debugfs_hairpin_queues_get(void *data, u64 *val)
1043 {
1044         struct mlx5e_hairpin_params *hp = data;
1045
1046         *val = hp->num_queues;
1047
1048         return 0;
1049 }
1050 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_queues, debugfs_hairpin_queues_get,
1051                          debugfs_hairpin_queues_set, "%llu\n");
1052
1053 static int debugfs_hairpin_queue_size_set(void *data, u64 val)
1054 {
1055         struct mlx5e_hairpin_params *hp = data;
1056
1057         if (val > BIT(MLX5_CAP_GEN(hp->mdev, log_max_hairpin_num_packets))) {
1058                 mlx5_core_err(hp->mdev,
1059                               "Invalid hairpin queue size, must be <= %lu\n",
1060                               BIT(MLX5_CAP_GEN(hp->mdev,
1061                                                log_max_hairpin_num_packets)));
1062                 return -EINVAL;
1063         }
1064
1065         hp->queue_size = roundup_pow_of_two(val);
1066
1067         return 0;
1068 }
1069
1070 static int debugfs_hairpin_queue_size_get(void *data, u64 *val)
1071 {
1072         struct mlx5e_hairpin_params *hp = data;
1073
1074         *val = hp->queue_size;
1075
1076         return 0;
1077 }
1078 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_queue_size,
1079                          debugfs_hairpin_queue_size_get,
1080                          debugfs_hairpin_queue_size_set, "%llu\n");
1081
1082 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1083 {
1084         struct mlx5e_tc_table *tc = data;
1085         struct mlx5e_hairpin_entry *hpe;
1086         u32 cnt = 0;
1087         u32 bkt;
1088
1089         mutex_lock(&tc->hairpin_tbl_lock);
1090         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1091                 cnt++;
1092         mutex_unlock(&tc->hairpin_tbl_lock);
1093
1094         *val = cnt;
1095
1096         return 0;
1097 }
1098 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1099                          debugfs_hairpin_num_active_get, NULL, "%llu\n");
1100
1101 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1102
1103 {
1104         struct mlx5e_tc_table *tc = file->private;
1105         struct mlx5e_hairpin_entry *hpe;
1106         u32 bkt;
1107
1108         mutex_lock(&tc->hairpin_tbl_lock);
1109         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1110                 seq_printf(file, "Hairpin peer_vhca_id %u prio %u refcnt %u\n",
1111                            hpe->peer_vhca_id, hpe->prio,
1112                            refcount_read(&hpe->refcnt));
1113         mutex_unlock(&tc->hairpin_tbl_lock);
1114
1115         return 0;
1116 }
1117 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1118
1119 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1120                                   struct dentry *dfs_root)
1121 {
1122         if (IS_ERR_OR_NULL(dfs_root))
1123                 return;
1124
1125         tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1126         if (!tc->dfs_root)
1127                 return;
1128
1129         debugfs_create_file("hairpin_num_queues", 0644, tc->dfs_root,
1130                             &tc->hairpin_params, &fops_hairpin_queues);
1131         debugfs_create_file("hairpin_queue_size", 0644, tc->dfs_root,
1132                             &tc->hairpin_params, &fops_hairpin_queue_size);
1133         debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1134                             &fops_hairpin_num_active);
1135         debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1136                             &debugfs_hairpin_table_dump_fops);
1137 }
1138
1139 static void
1140 mlx5e_hairpin_params_init(struct mlx5e_hairpin_params *hairpin_params,
1141                           struct mlx5_core_dev *mdev)
1142 {
1143         u64 link_speed64;
1144         u32 link_speed;
1145
1146         hairpin_params->mdev = mdev;
1147         /* set hairpin pair per each 50Gbs share of the link */
1148         mlx5e_port_max_linkspeed(mdev, &link_speed);
1149         link_speed = max_t(u32, link_speed, 50000);
1150         link_speed64 = link_speed;
1151         do_div(link_speed64, 50000);
1152         hairpin_params->num_queues = link_speed64;
1153
1154         hairpin_params->queue_size =
1155                 BIT(min_t(u32, 16 - MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev),
1156                           MLX5_CAP_GEN(mdev, log_max_hairpin_num_packets)));
1157 }
1158
1159 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1160                                   struct mlx5e_tc_flow *flow,
1161                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
1162                                   struct netlink_ext_ack *extack)
1163 {
1164         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1165         int peer_ifindex = parse_attr->mirred_ifindex[0];
1166         struct mlx5_hairpin_params params;
1167         struct mlx5_core_dev *peer_mdev;
1168         struct mlx5e_hairpin_entry *hpe;
1169         struct mlx5e_hairpin *hp;
1170         u8 match_prio;
1171         u16 peer_id;
1172         int err;
1173
1174         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1175         if (IS_ERR(peer_mdev)) {
1176                 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1177                 return PTR_ERR(peer_mdev);
1178         }
1179
1180         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1181                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1182                 return -EOPNOTSUPP;
1183         }
1184
1185         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1186         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1187                                      extack);
1188         if (err)
1189                 return err;
1190
1191         mutex_lock(&tc->hairpin_tbl_lock);
1192         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1193         if (hpe) {
1194                 mutex_unlock(&tc->hairpin_tbl_lock);
1195                 wait_for_completion(&hpe->res_ready);
1196
1197                 if (IS_ERR(hpe->hp)) {
1198                         err = -EREMOTEIO;
1199                         goto out_err;
1200                 }
1201                 goto attach_flow;
1202         }
1203
1204         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1205         if (!hpe) {
1206                 mutex_unlock(&tc->hairpin_tbl_lock);
1207                 return -ENOMEM;
1208         }
1209
1210         spin_lock_init(&hpe->flows_lock);
1211         INIT_LIST_HEAD(&hpe->flows);
1212         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1213         hpe->peer_vhca_id = peer_id;
1214         hpe->prio = match_prio;
1215         refcount_set(&hpe->refcnt, 1);
1216         init_completion(&hpe->res_ready);
1217
1218         hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1219                  hash_hairpin_info(peer_id, match_prio));
1220         mutex_unlock(&tc->hairpin_tbl_lock);
1221
1222         params.log_num_packets = ilog2(tc->hairpin_params.queue_size);
1223         params.log_data_size =
1224                 clamp_t(u32,
1225                         params.log_num_packets +
1226                                 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1227                         MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1228                         MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1229
1230         params.q_counter = priv->q_counter;
1231         params.num_channels = tc->hairpin_params.num_queues;
1232
1233         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
1234         hpe->hp = hp;
1235         complete_all(&hpe->res_ready);
1236         if (IS_ERR(hp)) {
1237                 err = PTR_ERR(hp);
1238                 goto out_err;
1239         }
1240
1241         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1242                    mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1243                    dev_name(hp->pair->peer_mdev->device),
1244                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1245
1246 attach_flow:
1247         if (hpe->hp->num_channels > 1) {
1248                 flow_flag_set(flow, HAIRPIN_RSS);
1249                 flow->attr->nic_attr->hairpin_ft =
1250                         mlx5_get_ttc_flow_table(hpe->hp->ttc);
1251         } else {
1252                 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1253         }
1254
1255         flow->hpe = hpe;
1256         spin_lock(&hpe->flows_lock);
1257         list_add(&flow->hairpin, &hpe->flows);
1258         spin_unlock(&hpe->flows_lock);
1259
1260         return 0;
1261
1262 out_err:
1263         mlx5e_hairpin_put(priv, hpe);
1264         return err;
1265 }
1266
1267 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1268                                    struct mlx5e_tc_flow *flow)
1269 {
1270         /* flow wasn't fully initialized */
1271         if (!flow->hpe)
1272                 return;
1273
1274         spin_lock(&flow->hpe->flows_lock);
1275         list_del(&flow->hairpin);
1276         spin_unlock(&flow->hpe->flows_lock);
1277
1278         mlx5e_hairpin_put(priv, flow->hpe);
1279         flow->hpe = NULL;
1280 }
1281
1282 struct mlx5_flow_handle *
1283 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1284                              struct mlx5_flow_spec *spec,
1285                              struct mlx5_flow_attr *attr)
1286 {
1287         struct mlx5_flow_context *flow_context = &spec->flow_context;
1288         struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1289         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1290         struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1291         struct mlx5_flow_destination dest[2] = {};
1292         struct mlx5_fs_chains *nic_chains;
1293         struct mlx5_flow_act flow_act = {
1294                 .action = attr->action,
1295                 .flags    = FLOW_ACT_NO_APPEND,
1296         };
1297         struct mlx5_flow_handle *rule;
1298         struct mlx5_flow_table *ft;
1299         int dest_ix = 0;
1300
1301         nic_chains = mlx5e_nic_chains(tc);
1302         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1303         flow_context->flow_tag = nic_attr->flow_tag;
1304
1305         if (attr->dest_ft) {
1306                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1307                 dest[dest_ix].ft = attr->dest_ft;
1308                 dest_ix++;
1309         } else if (nic_attr->hairpin_ft) {
1310                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1311                 dest[dest_ix].ft = nic_attr->hairpin_ft;
1312                 dest_ix++;
1313         } else if (nic_attr->hairpin_tirn) {
1314                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1315                 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1316                 dest_ix++;
1317         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1318                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1319                 if (attr->dest_chain) {
1320                         dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1321                                                                  attr->dest_chain, 1,
1322                                                                  MLX5E_TC_FT_LEVEL);
1323                         if (IS_ERR(dest[dest_ix].ft))
1324                                 return ERR_CAST(dest[dest_ix].ft);
1325                 } else {
1326                         dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1327                 }
1328                 dest_ix++;
1329         }
1330
1331         if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1332             MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1333                 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1334
1335         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1336                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1337                 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
1338                 dest_ix++;
1339         }
1340
1341         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1342                 flow_act.modify_hdr = attr->modify_hdr;
1343
1344         mutex_lock(&tc->t_lock);
1345         if (IS_ERR_OR_NULL(tc->t)) {
1346                 /* Create the root table here if doesn't exist yet */
1347                 tc->t =
1348                         mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1349
1350                 if (IS_ERR(tc->t)) {
1351                         mutex_unlock(&tc->t_lock);
1352                         netdev_err(priv->netdev,
1353                                    "Failed to create tc offload table\n");
1354                         rule = ERR_CAST(tc->t);
1355                         goto err_ft_get;
1356                 }
1357         }
1358         mutex_unlock(&tc->t_lock);
1359
1360         if (attr->chain || attr->prio)
1361                 ft = mlx5_chains_get_table(nic_chains,
1362                                            attr->chain, attr->prio,
1363                                            MLX5E_TC_FT_LEVEL);
1364         else
1365                 ft = attr->ft;
1366
1367         if (IS_ERR(ft)) {
1368                 rule = ERR_CAST(ft);
1369                 goto err_ft_get;
1370         }
1371
1372         if (attr->outer_match_level != MLX5_MATCH_NONE)
1373                 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1374
1375         rule = mlx5_add_flow_rules(ft, spec,
1376                                    &flow_act, dest, dest_ix);
1377         if (IS_ERR(rule))
1378                 goto err_rule;
1379
1380         return rule;
1381
1382 err_rule:
1383         if (attr->chain || attr->prio)
1384                 mlx5_chains_put_table(nic_chains,
1385                                       attr->chain, attr->prio,
1386                                       MLX5E_TC_FT_LEVEL);
1387 err_ft_get:
1388         if (attr->dest_chain)
1389                 mlx5_chains_put_table(nic_chains,
1390                                       attr->dest_chain, 1,
1391                                       MLX5E_TC_FT_LEVEL);
1392
1393         return ERR_CAST(rule);
1394 }
1395
1396 static int
1397 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1398                         struct mlx5_flow_attr *attr)
1399
1400 {
1401         struct mlx5_fc *counter;
1402
1403         counter = mlx5_fc_create(counter_dev, true);
1404         if (IS_ERR(counter))
1405                 return PTR_ERR(counter);
1406
1407         attr->counter = counter;
1408         return 0;
1409 }
1410
1411 static int
1412 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1413                       struct mlx5e_tc_flow *flow,
1414                       struct netlink_ext_ack *extack)
1415 {
1416         struct mlx5e_tc_flow_parse_attr *parse_attr;
1417         struct mlx5_flow_attr *attr = flow->attr;
1418         struct mlx5_core_dev *dev = priv->mdev;
1419         int err;
1420
1421         parse_attr = attr->parse_attr;
1422
1423         if (flow_flag_test(flow, HAIRPIN)) {
1424                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1425                 if (err)
1426                         return err;
1427         }
1428
1429         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1430                 err = alloc_flow_attr_counter(dev, attr);
1431                 if (err)
1432                         return err;
1433         }
1434
1435         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1436                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1437                 if (err)
1438                         return err;
1439         }
1440
1441         if (attr->flags & MLX5_ATTR_FLAG_CT)
1442                 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), &parse_attr->spec,
1443                                                         attr, &parse_attr->mod_hdr_acts);
1444         else
1445                 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1446                                                              attr);
1447
1448         return PTR_ERR_OR_ZERO(flow->rule[0]);
1449 }
1450
1451 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1452                                   struct mlx5_flow_handle *rule,
1453                                   struct mlx5_flow_attr *attr)
1454 {
1455         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1456         struct mlx5_fs_chains *nic_chains;
1457
1458         nic_chains = mlx5e_nic_chains(tc);
1459         mlx5_del_flow_rules(rule);
1460
1461         if (attr->chain || attr->prio)
1462                 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1463                                       MLX5E_TC_FT_LEVEL);
1464
1465         if (attr->dest_chain)
1466                 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1467                                       MLX5E_TC_FT_LEVEL);
1468 }
1469
1470 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1471                                   struct mlx5e_tc_flow *flow)
1472 {
1473         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1474         struct mlx5_flow_attr *attr = flow->attr;
1475
1476         flow_flag_clear(flow, OFFLOADED);
1477
1478         if (attr->flags & MLX5_ATTR_FLAG_CT)
1479                 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
1480         else if (!IS_ERR_OR_NULL(flow->rule[0]))
1481                 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1482
1483         /* Remove root table if no rules are left to avoid
1484          * extra steering hops.
1485          */
1486         mutex_lock(&tc->t_lock);
1487         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1488             !IS_ERR_OR_NULL(tc->t)) {
1489                 mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1490                 tc->t = NULL;
1491         }
1492         mutex_unlock(&tc->t_lock);
1493
1494         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1495                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1496                 mlx5e_detach_mod_hdr(priv, flow);
1497         }
1498
1499         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1500                 mlx5_fc_destroy(priv->mdev, attr->counter);
1501
1502         if (flow_flag_test(flow, HAIRPIN))
1503                 mlx5e_hairpin_flow_del(priv, flow);
1504
1505         free_flow_post_acts(flow);
1506
1507         kvfree(attr->parse_attr);
1508         kfree(flow->attr);
1509 }
1510
1511 struct mlx5_flow_handle *
1512 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1513                            struct mlx5e_tc_flow *flow,
1514                            struct mlx5_flow_spec *spec,
1515                            struct mlx5_flow_attr *attr)
1516 {
1517         struct mlx5_flow_handle *rule;
1518
1519         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1520                 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1521
1522         rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1523
1524         if (IS_ERR(rule))
1525                 return rule;
1526
1527         if (attr->esw_attr->split_count) {
1528                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1529                 if (IS_ERR(flow->rule[1]))
1530                         goto err_rule1;
1531         }
1532
1533         return rule;
1534
1535 err_rule1:
1536         mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1537         return flow->rule[1];
1538 }
1539
1540 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1541                                   struct mlx5e_tc_flow *flow,
1542                                   struct mlx5_flow_attr *attr)
1543 {
1544         flow_flag_clear(flow, OFFLOADED);
1545
1546         if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1547                 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1548
1549         if (attr->esw_attr->split_count)
1550                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1551
1552         mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1553 }
1554
1555 struct mlx5_flow_handle *
1556 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1557                               struct mlx5e_tc_flow *flow,
1558                               struct mlx5_flow_spec *spec)
1559 {
1560         struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1561         struct mlx5e_mod_hdr_handle *mh = NULL;
1562         struct mlx5_flow_attr *slow_attr;
1563         struct mlx5_flow_handle *rule;
1564         bool fwd_and_modify_cap;
1565         u32 chain_mapping = 0;
1566         int err;
1567
1568         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1569         if (!slow_attr)
1570                 return ERR_PTR(-ENOMEM);
1571
1572         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1573         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1574         slow_attr->esw_attr->split_count = 0;
1575         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1576
1577         fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1578         if (!fwd_and_modify_cap)
1579                 goto skip_restore;
1580
1581         err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1582         if (err)
1583                 goto err_get_chain;
1584
1585         err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1586                                         CHAIN_TO_REG, chain_mapping);
1587         if (err)
1588                 goto err_reg_set;
1589
1590         mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1591                                   MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1592         if (IS_ERR(mh)) {
1593                 err = PTR_ERR(mh);
1594                 goto err_attach;
1595         }
1596
1597         slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1598         slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1599
1600 skip_restore:
1601         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1602         if (IS_ERR(rule)) {
1603                 err = PTR_ERR(rule);
1604                 goto err_offload;
1605         }
1606
1607         flow->slow_mh = mh;
1608         flow->chain_mapping = chain_mapping;
1609         flow_flag_set(flow, SLOW);
1610
1611         mlx5e_mod_hdr_dealloc(&mod_acts);
1612         kfree(slow_attr);
1613
1614         return rule;
1615
1616 err_offload:
1617         if (fwd_and_modify_cap)
1618                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1619 err_attach:
1620 err_reg_set:
1621         if (fwd_and_modify_cap)
1622                 mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1623 err_get_chain:
1624         mlx5e_mod_hdr_dealloc(&mod_acts);
1625         kfree(slow_attr);
1626         return ERR_PTR(err);
1627 }
1628
1629 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1630                                        struct mlx5e_tc_flow *flow)
1631 {
1632         struct mlx5_flow_attr *slow_attr;
1633
1634         slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1635         if (!slow_attr) {
1636                 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1637                 return;
1638         }
1639
1640         memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1641         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1642         slow_attr->esw_attr->split_count = 0;
1643         slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1644         if (flow->slow_mh) {
1645                 slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1646                 slow_attr->modify_hdr = mlx5e_mod_hdr_get(flow->slow_mh);
1647         }
1648         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1649         if (flow->slow_mh) {
1650                 mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), flow->slow_mh);
1651                 mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1652                 flow->chain_mapping = 0;
1653                 flow->slow_mh = NULL;
1654         }
1655         flow_flag_clear(flow, SLOW);
1656         kfree(slow_attr);
1657 }
1658
1659 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1660  * function.
1661  */
1662 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1663                              struct list_head *unready_flows)
1664 {
1665         flow_flag_set(flow, NOT_READY);
1666         list_add_tail(&flow->unready, unready_flows);
1667 }
1668
1669 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1670  * function.
1671  */
1672 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1673 {
1674         list_del(&flow->unready);
1675         flow_flag_clear(flow, NOT_READY);
1676 }
1677
1678 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1679 {
1680         struct mlx5_rep_uplink_priv *uplink_priv;
1681         struct mlx5e_rep_priv *rpriv;
1682         struct mlx5_eswitch *esw;
1683
1684         esw = flow->priv->mdev->priv.eswitch;
1685         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1686         uplink_priv = &rpriv->uplink_priv;
1687
1688         mutex_lock(&uplink_priv->unready_flows_lock);
1689         unready_flow_add(flow, &uplink_priv->unready_flows);
1690         mutex_unlock(&uplink_priv->unready_flows_lock);
1691 }
1692
1693 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1694 {
1695         struct mlx5_rep_uplink_priv *uplink_priv;
1696         struct mlx5e_rep_priv *rpriv;
1697         struct mlx5_eswitch *esw;
1698
1699         esw = flow->priv->mdev->priv.eswitch;
1700         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1701         uplink_priv = &rpriv->uplink_priv;
1702
1703         mutex_lock(&uplink_priv->unready_flows_lock);
1704         unready_flow_del(flow);
1705         mutex_unlock(&uplink_priv->unready_flows_lock);
1706 }
1707
1708 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1709 {
1710         struct mlx5_core_dev *out_mdev, *route_mdev;
1711         struct mlx5e_priv *out_priv, *route_priv;
1712
1713         out_priv = netdev_priv(out_dev);
1714         out_mdev = out_priv->mdev;
1715         route_priv = netdev_priv(route_dev);
1716         route_mdev = route_priv->mdev;
1717
1718         if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1719                 return false;
1720
1721         if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1722             route_mdev->coredev_type != MLX5_COREDEV_SF)
1723                 return false;
1724
1725         return mlx5e_same_hw_devs(out_priv, route_priv);
1726 }
1727
1728 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1729 {
1730         struct mlx5e_priv *out_priv, *route_priv;
1731         struct mlx5_devcom *devcom = NULL;
1732         struct mlx5_core_dev *route_mdev;
1733         struct mlx5_eswitch *esw;
1734         u16 vhca_id;
1735         int err;
1736
1737         out_priv = netdev_priv(out_dev);
1738         esw = out_priv->mdev->priv.eswitch;
1739         route_priv = netdev_priv(route_dev);
1740         route_mdev = route_priv->mdev;
1741
1742         vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1743         if (mlx5_lag_is_active(out_priv->mdev)) {
1744                 /* In lag case we may get devices from different eswitch instances.
1745                  * If we failed to get vport num, it means, mostly, that we on the wrong
1746                  * eswitch.
1747                  */
1748                 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1749                 if (err != -ENOENT)
1750                         return err;
1751
1752                 devcom = out_priv->mdev->priv.devcom;
1753                 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1754                 if (!esw)
1755                         return -ENODEV;
1756         }
1757
1758         err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1759         if (devcom)
1760                 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1761         return err;
1762 }
1763
1764 int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1765                               struct mlx5e_tc_flow *flow,
1766                               struct mlx5_flow_attr *attr)
1767 {
1768         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1769         struct mlx5_modify_hdr *mod_hdr;
1770
1771         mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1772                                            mlx5e_get_flow_namespace(flow),
1773                                            mod_hdr_acts->num_actions,
1774                                            mod_hdr_acts->actions);
1775         if (IS_ERR(mod_hdr))
1776                 return PTR_ERR(mod_hdr);
1777
1778         WARN_ON(attr->modify_hdr);
1779         attr->modify_hdr = mod_hdr;
1780
1781         return 0;
1782 }
1783
1784 static int
1785 set_encap_dests(struct mlx5e_priv *priv,
1786                 struct mlx5e_tc_flow *flow,
1787                 struct mlx5_flow_attr *attr,
1788                 struct netlink_ext_ack *extack,
1789                 bool *vf_tun)
1790 {
1791         struct mlx5e_tc_flow_parse_attr *parse_attr;
1792         struct mlx5_esw_flow_attr *esw_attr;
1793         struct net_device *encap_dev = NULL;
1794         struct mlx5e_rep_priv *rpriv;
1795         struct mlx5e_priv *out_priv;
1796         int out_index;
1797         int err = 0;
1798
1799         if (!mlx5e_is_eswitch_flow(flow))
1800                 return 0;
1801
1802         parse_attr = attr->parse_attr;
1803         esw_attr = attr->esw_attr;
1804         *vf_tun = false;
1805
1806         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1807                 struct net_device *out_dev;
1808                 int mirred_ifindex;
1809
1810                 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1811                         continue;
1812
1813                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1814                 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1815                 if (!out_dev) {
1816                         NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1817                         err = -ENODEV;
1818                         goto out;
1819                 }
1820                 err = mlx5e_attach_encap(priv, flow, attr, out_dev, out_index,
1821                                          extack, &encap_dev);
1822                 dev_put(out_dev);
1823                 if (err)
1824                         goto out;
1825
1826                 if (esw_attr->dests[out_index].flags &
1827                     MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1828                     !esw_attr->dest_int_port)
1829                         *vf_tun = true;
1830
1831                 out_priv = netdev_priv(encap_dev);
1832                 rpriv = out_priv->ppriv;
1833                 esw_attr->dests[out_index].rep = rpriv->rep;
1834                 esw_attr->dests[out_index].mdev = out_priv->mdev;
1835         }
1836
1837         if (*vf_tun && esw_attr->out_count > 1) {
1838                 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1839                 err = -EOPNOTSUPP;
1840                 goto out;
1841         }
1842
1843 out:
1844         return err;
1845 }
1846
1847 static void
1848 clean_encap_dests(struct mlx5e_priv *priv,
1849                   struct mlx5e_tc_flow *flow,
1850                   struct mlx5_flow_attr *attr,
1851                   bool *vf_tun)
1852 {
1853         struct mlx5_esw_flow_attr *esw_attr;
1854         int out_index;
1855
1856         if (!mlx5e_is_eswitch_flow(flow))
1857                 return;
1858
1859         esw_attr = attr->esw_attr;
1860         *vf_tun = false;
1861
1862         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1863                 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1864                         continue;
1865
1866                 if (esw_attr->dests[out_index].flags &
1867                     MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1868                     !esw_attr->dest_int_port)
1869                         *vf_tun = true;
1870
1871                 mlx5e_detach_encap(priv, flow, attr, out_index);
1872                 kfree(attr->parse_attr->tun_info[out_index]);
1873         }
1874 }
1875
1876 static int
1877 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1878 {
1879         if (!(actions &
1880               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1881                 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1882                 return -EOPNOTSUPP;
1883         }
1884
1885         if (!(~actions &
1886               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1887                 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1888                 return -EOPNOTSUPP;
1889         }
1890
1891         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1892             actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1893                 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1894                 return -EOPNOTSUPP;
1895         }
1896
1897         return 0;
1898 }
1899
1900 static int
1901 post_process_attr(struct mlx5e_tc_flow *flow,
1902                   struct mlx5_flow_attr *attr,
1903                   bool is_post_act_attr,
1904                   struct netlink_ext_ack *extack)
1905 {
1906         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1907         bool vf_tun;
1908         int err = 0;
1909
1910         err = verify_attr_actions(attr->action, extack);
1911         if (err)
1912                 goto err_out;
1913
1914         err = set_encap_dests(flow->priv, flow, attr, extack, &vf_tun);
1915         if (err)
1916                 goto err_out;
1917
1918         if (mlx5e_is_eswitch_flow(flow)) {
1919                 err = mlx5_eswitch_add_vlan_action(esw, attr);
1920                 if (err)
1921                         goto err_out;
1922         }
1923
1924         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1925                 if (vf_tun || is_post_act_attr) {
1926                         err = mlx5e_tc_add_flow_mod_hdr(flow->priv, flow, attr);
1927                         if (err)
1928                                 goto err_out;
1929                 } else {
1930                         err = mlx5e_attach_mod_hdr(flow->priv, flow, attr->parse_attr);
1931                         if (err)
1932                                 goto err_out;
1933                 }
1934         }
1935
1936         if (attr->branch_true &&
1937             attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1938                 err = mlx5e_tc_add_flow_mod_hdr(flow->priv, flow, attr->branch_true);
1939                 if (err)
1940                         goto err_out;
1941         }
1942
1943         if (attr->branch_false &&
1944             attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1945                 err = mlx5e_tc_add_flow_mod_hdr(flow->priv, flow, attr->branch_false);
1946                 if (err)
1947                         goto err_out;
1948         }
1949
1950         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1951                 err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1952                 if (err)
1953                         goto err_out;
1954         }
1955
1956 err_out:
1957         return err;
1958 }
1959
1960 static int
1961 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1962                       struct mlx5e_tc_flow *flow,
1963                       struct netlink_ext_ack *extack)
1964 {
1965         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1966         struct mlx5e_tc_flow_parse_attr *parse_attr;
1967         struct mlx5_flow_attr *attr = flow->attr;
1968         struct mlx5_esw_flow_attr *esw_attr;
1969         u32 max_prio, max_chain;
1970         int err = 0;
1971
1972         parse_attr = attr->parse_attr;
1973         esw_attr = attr->esw_attr;
1974
1975         /* We check chain range only for tc flows.
1976          * For ft flows, we checked attr->chain was originally 0 and set it to
1977          * FDB_FT_CHAIN which is outside tc range.
1978          * See mlx5e_rep_setup_ft_cb().
1979          */
1980         max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1981         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1982                 NL_SET_ERR_MSG_MOD(extack,
1983                                    "Requested chain is out of supported range");
1984                 err = -EOPNOTSUPP;
1985                 goto err_out;
1986         }
1987
1988         max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1989         if (attr->prio > max_prio) {
1990                 NL_SET_ERR_MSG_MOD(extack,
1991                                    "Requested priority is out of supported range");
1992                 err = -EOPNOTSUPP;
1993                 goto err_out;
1994         }
1995
1996         if (flow_flag_test(flow, TUN_RX)) {
1997                 err = mlx5e_attach_decap_route(priv, flow);
1998                 if (err)
1999                         goto err_out;
2000
2001                 if (!attr->chain && esw_attr->int_port &&
2002                     attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2003                         /* If decap route device is internal port, change the
2004                          * source vport value in reg_c0 back to uplink just in
2005                          * case the rule performs goto chain > 0. If we have a miss
2006                          * on chain > 0 we want the metadata regs to hold the
2007                          * chain id so SW will resume handling of this packet
2008                          * from the proper chain.
2009                          */
2010                         u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
2011                                                                         esw_attr->in_rep->vport);
2012
2013                         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
2014                                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
2015                                                         metadata);
2016                         if (err)
2017                                 goto err_out;
2018
2019                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2020                 }
2021         }
2022
2023         if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
2024                 err = mlx5e_attach_decap(priv, flow, extack);
2025                 if (err)
2026                         goto err_out;
2027         }
2028
2029         if (netif_is_ovs_master(parse_attr->filter_dev)) {
2030                 struct mlx5e_tc_int_port *int_port;
2031
2032                 if (attr->chain) {
2033                         NL_SET_ERR_MSG_MOD(extack,
2034                                            "Internal port rule is only supported on chain 0");
2035                         err = -EOPNOTSUPP;
2036                         goto err_out;
2037                 }
2038
2039                 if (attr->dest_chain) {
2040                         NL_SET_ERR_MSG_MOD(extack,
2041                                            "Internal port rule offload doesn't support goto action");
2042                         err = -EOPNOTSUPP;
2043                         goto err_out;
2044                 }
2045
2046                 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
2047                                                  parse_attr->filter_dev->ifindex,
2048                                                  flow_flag_test(flow, EGRESS) ?
2049                                                  MLX5E_TC_INT_PORT_EGRESS :
2050                                                  MLX5E_TC_INT_PORT_INGRESS);
2051                 if (IS_ERR(int_port)) {
2052                         err = PTR_ERR(int_port);
2053                         goto err_out;
2054                 }
2055
2056                 esw_attr->int_port = int_port;
2057         }
2058
2059         err = post_process_attr(flow, attr, false, extack);
2060         if (err)
2061                 goto err_out;
2062
2063         /* we get here if one of the following takes place:
2064          * (1) there's no error
2065          * (2) there's an encap action and we don't have valid neigh
2066          */
2067         if (flow_flag_test(flow, SLOW))
2068                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
2069         else
2070                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
2071
2072         if (IS_ERR(flow->rule[0])) {
2073                 err = PTR_ERR(flow->rule[0]);
2074                 goto err_out;
2075         }
2076         flow_flag_set(flow, OFFLOADED);
2077
2078         return 0;
2079
2080 err_out:
2081         flow_flag_set(flow, FAILED);
2082         return err;
2083 }
2084
2085 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
2086 {
2087         struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
2088         void *headers_v = MLX5_ADDR_OF(fte_match_param,
2089                                        spec->match_value,
2090                                        misc_parameters_3);
2091         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
2092                                              headers_v,
2093                                              geneve_tlv_option_0_data);
2094
2095         return !!geneve_tlv_opt_0_data;
2096 }
2097
2098 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
2099 {
2100         if (!attr)
2101                 return;
2102
2103         mlx5_free_flow_attr(flow, attr);
2104         kvfree(attr->parse_attr);
2105         kfree(attr);
2106 }
2107
2108 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
2109                                   struct mlx5e_tc_flow *flow)
2110 {
2111         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2112         struct mlx5_flow_attr *attr = flow->attr;
2113         struct mlx5_esw_flow_attr *esw_attr;
2114         bool vf_tun;
2115
2116         esw_attr = attr->esw_attr;
2117         mlx5e_put_flow_tunnel_id(flow);
2118
2119         if (flow_flag_test(flow, NOT_READY))
2120                 remove_unready_flow(flow);
2121
2122         if (mlx5e_is_offloaded_flow(flow)) {
2123                 if (flow_flag_test(flow, SLOW))
2124                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
2125                 else
2126                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
2127         }
2128         complete_all(&flow->del_hw_done);
2129
2130         if (mlx5_flow_has_geneve_opt(flow))
2131                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
2132
2133         mlx5_eswitch_del_vlan_action(esw, attr);
2134
2135         if (flow->decap_route)
2136                 mlx5e_detach_decap_route(priv, flow);
2137
2138         clean_encap_dests(priv, flow, attr, &vf_tun);
2139
2140         mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
2141
2142         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
2143                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
2144                 if (vf_tun && attr->modify_hdr)
2145                         mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
2146                 else
2147                         mlx5e_detach_mod_hdr(priv, flow);
2148         }
2149
2150         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2151                 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
2152
2153         if (esw_attr->int_port)
2154                 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->int_port);
2155
2156         if (esw_attr->dest_int_port)
2157                 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->dest_int_port);
2158
2159         if (flow_flag_test(flow, L3_TO_L2_DECAP))
2160                 mlx5e_detach_decap(priv, flow);
2161
2162         free_flow_post_acts(flow);
2163         free_branch_attr(flow, attr->branch_true);
2164         free_branch_attr(flow, attr->branch_false);
2165
2166         if (flow->attr->lag.count)
2167                 mlx5_lag_del_mpesw_rule(esw->dev);
2168
2169         kvfree(attr->esw_attr->rx_tun_attr);
2170         kvfree(attr->parse_attr);
2171         kfree(flow->attr);
2172 }
2173
2174 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
2175 {
2176         struct mlx5_flow_attr *attr;
2177
2178         attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
2179         return attr->counter;
2180 }
2181
2182 /* Iterate over tmp_list of flows attached to flow_list head. */
2183 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
2184 {
2185         struct mlx5e_tc_flow *flow, *tmp;
2186
2187         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
2188                 mlx5e_flow_put(priv, flow);
2189 }
2190
2191 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
2192 {
2193         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
2194
2195         if (!flow_flag_test(flow, ESWITCH) ||
2196             !flow_flag_test(flow, DUP))
2197                 return;
2198
2199         mutex_lock(&esw->offloads.peer_mutex);
2200         list_del(&flow->peer);
2201         mutex_unlock(&esw->offloads.peer_mutex);
2202
2203         flow_flag_clear(flow, DUP);
2204
2205         if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
2206                 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
2207                 kfree(flow->peer_flow);
2208         }
2209
2210         flow->peer_flow = NULL;
2211 }
2212
2213 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
2214 {
2215         struct mlx5_core_dev *dev = flow->priv->mdev;
2216         struct mlx5_devcom *devcom = dev->priv.devcom;
2217         struct mlx5_eswitch *peer_esw;
2218
2219         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2220         if (!peer_esw)
2221                 return;
2222
2223         __mlx5e_tc_del_fdb_peer_flow(flow);
2224         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2225 }
2226
2227 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2228                               struct mlx5e_tc_flow *flow)
2229 {
2230         if (mlx5e_is_eswitch_flow(flow)) {
2231                 mlx5e_tc_del_fdb_peer_flow(flow);
2232                 mlx5e_tc_del_fdb_flow(priv, flow);
2233         } else {
2234                 mlx5e_tc_del_nic_flow(priv, flow);
2235         }
2236 }
2237
2238 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2239 {
2240         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2241         struct flow_action *flow_action = &rule->action;
2242         const struct flow_action_entry *act;
2243         int i;
2244
2245         if (chain)
2246                 return false;
2247
2248         flow_action_for_each(i, act, flow_action) {
2249                 switch (act->id) {
2250                 case FLOW_ACTION_GOTO:
2251                         return true;
2252                 case FLOW_ACTION_SAMPLE:
2253                         return true;
2254                 default:
2255                         continue;
2256                 }
2257         }
2258
2259         return false;
2260 }
2261
2262 static int
2263 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2264                                     struct flow_dissector_key_enc_opts *opts,
2265                                     struct netlink_ext_ack *extack,
2266                                     bool *dont_care)
2267 {
2268         struct geneve_opt *opt;
2269         int off = 0;
2270
2271         *dont_care = true;
2272
2273         while (opts->len > off) {
2274                 opt = (struct geneve_opt *)&opts->data[off];
2275
2276                 if (!(*dont_care) || opt->opt_class || opt->type ||
2277                     memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2278                         *dont_care = false;
2279
2280                         if (opt->opt_class != htons(U16_MAX) ||
2281                             opt->type != U8_MAX) {
2282                                 NL_SET_ERR_MSG_MOD(extack,
2283                                                    "Partial match of tunnel options in chain > 0 isn't supported");
2284                                 netdev_warn(priv->netdev,
2285                                             "Partial match of tunnel options in chain > 0 isn't supported");
2286                                 return -EOPNOTSUPP;
2287                         }
2288                 }
2289
2290                 off += sizeof(struct geneve_opt) + opt->length * 4;
2291         }
2292
2293         return 0;
2294 }
2295
2296 #define COPY_DISSECTOR(rule, diss_key, dst)\
2297 ({ \
2298         struct flow_rule *__rule = (rule);\
2299         typeof(dst) __dst = dst;\
2300 \
2301         memcpy(__dst,\
2302                skb_flow_dissector_target(__rule->match.dissector,\
2303                                          diss_key,\
2304                                          __rule->match.key),\
2305                sizeof(*__dst));\
2306 })
2307
2308 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2309                                     struct mlx5e_tc_flow *flow,
2310                                     struct flow_cls_offload *f,
2311                                     struct net_device *filter_dev)
2312 {
2313         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2314         struct netlink_ext_ack *extack = f->common.extack;
2315         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2316         struct flow_match_enc_opts enc_opts_match;
2317         struct tunnel_match_enc_opts tun_enc_opts;
2318         struct mlx5_rep_uplink_priv *uplink_priv;
2319         struct mlx5_flow_attr *attr = flow->attr;
2320         struct mlx5e_rep_priv *uplink_rpriv;
2321         struct tunnel_match_key tunnel_key;
2322         bool enc_opts_is_dont_care = true;
2323         u32 tun_id, enc_opts_id = 0;
2324         struct mlx5_eswitch *esw;
2325         u32 value, mask;
2326         int err;
2327
2328         esw = priv->mdev->priv.eswitch;
2329         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2330         uplink_priv = &uplink_rpriv->uplink_priv;
2331
2332         memset(&tunnel_key, 0, sizeof(tunnel_key));
2333         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2334                        &tunnel_key.enc_control);
2335         if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2336                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2337                                &tunnel_key.enc_ipv4);
2338         else
2339                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2340                                &tunnel_key.enc_ipv6);
2341         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2342         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2343                        &tunnel_key.enc_tp);
2344         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2345                        &tunnel_key.enc_key_id);
2346         tunnel_key.filter_ifindex = filter_dev->ifindex;
2347
2348         err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2349         if (err)
2350                 return err;
2351
2352         flow_rule_match_enc_opts(rule, &enc_opts_match);
2353         err = enc_opts_is_dont_care_or_full_match(priv,
2354                                                   enc_opts_match.mask,
2355                                                   extack,
2356                                                   &enc_opts_is_dont_care);
2357         if (err)
2358                 goto err_enc_opts;
2359
2360         if (!enc_opts_is_dont_care) {
2361                 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2362                 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2363                        sizeof(*enc_opts_match.key));
2364                 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2365                        sizeof(*enc_opts_match.mask));
2366
2367                 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2368                                   &tun_enc_opts, &enc_opts_id);
2369                 if (err)
2370                         goto err_enc_opts;
2371         }
2372
2373         value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2374         mask = enc_opts_id ? TUNNEL_ID_MASK :
2375                              (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2376
2377         if (attr->chain) {
2378                 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2379                                             TUNNEL_TO_REG, value, mask);
2380         } else {
2381                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2382                 err = mlx5e_tc_match_to_reg_set(priv->mdev,
2383                                                 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2384                                                 TUNNEL_TO_REG, value);
2385                 if (err)
2386                         goto err_set;
2387
2388                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2389         }
2390
2391         flow->attr->tunnel_id = value;
2392         return 0;
2393
2394 err_set:
2395         if (enc_opts_id)
2396                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2397                                enc_opts_id);
2398 err_enc_opts:
2399         mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2400         return err;
2401 }
2402
2403 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2404 {
2405         u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2406         u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2407         struct mlx5_rep_uplink_priv *uplink_priv;
2408         struct mlx5e_rep_priv *uplink_rpriv;
2409         struct mlx5_eswitch *esw;
2410
2411         esw = flow->priv->mdev->priv.eswitch;
2412         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2413         uplink_priv = &uplink_rpriv->uplink_priv;
2414
2415         if (tun_id)
2416                 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2417         if (enc_opts_id)
2418                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2419                                enc_opts_id);
2420 }
2421
2422 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2423                             struct flow_match_basic *match, bool outer,
2424                             void *headers_c, void *headers_v)
2425 {
2426         bool ip_version_cap;
2427
2428         ip_version_cap = outer ?
2429                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2430                                           ft_field_support.outer_ip_version) :
2431                 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2432                                           ft_field_support.inner_ip_version);
2433
2434         if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2435             (match->key->n_proto == htons(ETH_P_IP) ||
2436              match->key->n_proto == htons(ETH_P_IPV6))) {
2437                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2438                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2439                          match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2440         } else {
2441                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2442                          ntohs(match->mask->n_proto));
2443                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2444                          ntohs(match->key->n_proto));
2445         }
2446 }
2447
2448 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2449 {
2450         void *headers_v;
2451         u16 ethertype;
2452         u8 ip_version;
2453
2454         if (outer)
2455                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2456         else
2457                 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2458
2459         ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2460         /* Return ip_version converted from ethertype anyway */
2461         if (!ip_version) {
2462                 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2463                 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2464                         ip_version = 4;
2465                 else if (ethertype == ETH_P_IPV6)
2466                         ip_version = 6;
2467         }
2468         return ip_version;
2469 }
2470
2471 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2472  * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2473  *      +---------+----------------------------------------+
2474  *      |Arriving |         Arriving Outer Header          |
2475  *      |   Inner +---------+---------+---------+----------+
2476  *      |  Header | Not-ECT | ECT(0)  | ECT(1)  |   CE     |
2477  *      +---------+---------+---------+---------+----------+
2478  *      | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop>   |
2479  *      |  ECT(0) |  ECT(0) | ECT(0)  | ECT(1)  |   CE*    |
2480  *      |  ECT(1) |  ECT(1) | ECT(1)  | ECT(1)* |   CE*    |
2481  *      |    CE   |   CE    |  CE     | CE      |   CE     |
2482  *      +---------+---------+---------+---------+----------+
2483  *
2484  * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2485  * the inner ip_ecn value before hardware decap action.
2486  *
2487  * Cells marked are changed from original inner packet ip_ecn value during decap, and
2488  * so matching those values on inner ip_ecn before decap will fail.
2489  *
2490  * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2491  * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2492  * and such we can drop the inner ip_ecn=CE match.
2493  */
2494
2495 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2496                                       struct flow_cls_offload *f,
2497                                       bool *match_inner_ecn)
2498 {
2499         u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2500         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2501         struct netlink_ext_ack *extack = f->common.extack;
2502         struct flow_match_ip match;
2503
2504         *match_inner_ecn = true;
2505
2506         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2507                 flow_rule_match_enc_ip(rule, &match);
2508                 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2509                 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2510         }
2511
2512         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2513                 flow_rule_match_ip(rule, &match);
2514                 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2515                 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2516         }
2517
2518         if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2519                 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2520                 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2521                 return -EOPNOTSUPP;
2522         }
2523
2524         if (!outer_ecn_mask) {
2525                 if (!inner_ecn_mask)
2526                         return 0;
2527
2528                 NL_SET_ERR_MSG_MOD(extack,
2529                                    "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2530                 netdev_warn(priv->netdev,
2531                             "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2532                 return -EOPNOTSUPP;
2533         }
2534
2535         if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2536                 NL_SET_ERR_MSG_MOD(extack,
2537                                    "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2538                 netdev_warn(priv->netdev,
2539                             "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2540                 return -EOPNOTSUPP;
2541         }
2542
2543         if (!inner_ecn_mask)
2544                 return 0;
2545
2546         /* Both inner and outer have full mask on ecn */
2547
2548         if (outer_ecn_key == INET_ECN_ECT_1) {
2549                 /* inner ecn might change by DECAP action */
2550
2551                 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2552                 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2553                 return -EOPNOTSUPP;
2554         }
2555
2556         if (outer_ecn_key != INET_ECN_CE)
2557                 return 0;
2558
2559         if (inner_ecn_key != INET_ECN_CE) {
2560                 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2561                 NL_SET_ERR_MSG_MOD(extack,
2562                                    "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2563                 netdev_warn(priv->netdev,
2564                             "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2565                 return -EOPNOTSUPP;
2566         }
2567
2568         /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2569          * drop match on inner ecn
2570          */
2571         *match_inner_ecn = false;
2572
2573         return 0;
2574 }
2575
2576 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2577                              struct mlx5e_tc_flow *flow,
2578                              struct mlx5_flow_spec *spec,
2579                              struct flow_cls_offload *f,
2580                              struct net_device *filter_dev,
2581                              u8 *match_level,
2582                              bool *match_inner)
2583 {
2584         struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2585         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2586         struct netlink_ext_ack *extack = f->common.extack;
2587         bool needs_mapping, sets_mapping;
2588         int err;
2589
2590         if (!mlx5e_is_eswitch_flow(flow)) {
2591                 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2592                 return -EOPNOTSUPP;
2593         }
2594
2595         needs_mapping = !!flow->attr->chain;
2596         sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2597         *match_inner = !needs_mapping;
2598
2599         if ((needs_mapping || sets_mapping) &&
2600             !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2601                 NL_SET_ERR_MSG_MOD(extack,
2602                                    "Chains on tunnel devices isn't supported without register loopback support");
2603                 netdev_warn(priv->netdev,
2604                             "Chains on tunnel devices isn't supported without register loopback support");
2605                 return -EOPNOTSUPP;
2606         }
2607
2608         if (!flow->attr->chain) {
2609                 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2610                                          match_level);
2611                 if (err) {
2612                         NL_SET_ERR_MSG_MOD(extack,
2613                                            "Failed to parse tunnel attributes");
2614                         netdev_warn(priv->netdev,
2615                                     "Failed to parse tunnel attributes");
2616                         return err;
2617                 }
2618
2619                 /* With mpls over udp we decapsulate using packet reformat
2620                  * object
2621                  */
2622                 if (!netif_is_bareudp(filter_dev))
2623                         flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2624                 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2625                 if (err)
2626                         return err;
2627         } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2628                 struct mlx5_flow_spec *tmp_spec;
2629
2630                 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2631                 if (!tmp_spec) {
2632                         NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2633                         netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2634                         return -ENOMEM;
2635                 }
2636                 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2637
2638                 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2639                 if (err) {
2640                         kvfree(tmp_spec);
2641                         NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2642                         netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2643                         return err;
2644                 }
2645                 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2646                 kvfree(tmp_spec);
2647                 if (err)
2648                         return err;
2649         }
2650
2651         if (!needs_mapping && !sets_mapping)
2652                 return 0;
2653
2654         return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2655 }
2656
2657 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2658 {
2659         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2660                             inner_headers);
2661 }
2662
2663 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2664 {
2665         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2666                             inner_headers);
2667 }
2668
2669 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2670 {
2671         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2672                             outer_headers);
2673 }
2674
2675 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2676 {
2677         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2678                             outer_headers);
2679 }
2680
2681 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2682 {
2683         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2684                 get_match_inner_headers_value(spec) :
2685                 get_match_outer_headers_value(spec);
2686 }
2687
2688 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2689 {
2690         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2691                 get_match_inner_headers_criteria(spec) :
2692                 get_match_outer_headers_criteria(spec);
2693 }
2694
2695 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2696                                    struct flow_cls_offload *f)
2697 {
2698         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2699         struct netlink_ext_ack *extack = f->common.extack;
2700         struct net_device *ingress_dev;
2701         struct flow_match_meta match;
2702
2703         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2704                 return 0;
2705
2706         flow_rule_match_meta(rule, &match);
2707         if (!match.mask->ingress_ifindex)
2708                 return 0;
2709
2710         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2711                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2712                 return -EOPNOTSUPP;
2713         }
2714
2715         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2716                                          match.key->ingress_ifindex);
2717         if (!ingress_dev) {
2718                 NL_SET_ERR_MSG_MOD(extack,
2719                                    "Can't find the ingress port to match on");
2720                 return -ENOENT;
2721         }
2722
2723         if (ingress_dev != filter_dev) {
2724                 NL_SET_ERR_MSG_MOD(extack,
2725                                    "Can't match on the ingress filter port");
2726                 return -EOPNOTSUPP;
2727         }
2728
2729         return 0;
2730 }
2731
2732 static bool skip_key_basic(struct net_device *filter_dev,
2733                            struct flow_cls_offload *f)
2734 {
2735         /* When doing mpls over udp decap, the user needs to provide
2736          * MPLS_UC as the protocol in order to be able to match on mpls
2737          * label fields.  However, the actual ethertype is IP so we want to
2738          * avoid matching on this, otherwise we'll fail the match.
2739          */
2740         if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2741                 return true;
2742
2743         return false;
2744 }
2745
2746 static int __parse_cls_flower(struct mlx5e_priv *priv,
2747                               struct mlx5e_tc_flow *flow,
2748                               struct mlx5_flow_spec *spec,
2749                               struct flow_cls_offload *f,
2750                               struct net_device *filter_dev,
2751                               u8 *inner_match_level, u8 *outer_match_level)
2752 {
2753         struct netlink_ext_ack *extack = f->common.extack;
2754         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2755                                        outer_headers);
2756         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2757                                        outer_headers);
2758         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2759                                     misc_parameters);
2760         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2761                                     misc_parameters);
2762         void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2763                                     misc_parameters_3);
2764         void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2765                                     misc_parameters_3);
2766         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2767         struct flow_dissector *dissector = rule->match.dissector;
2768         enum fs_flow_table_type fs_type;
2769         bool match_inner_ecn = true;
2770         u16 addr_type = 0;
2771         u8 ip_proto = 0;
2772         u8 *match_level;
2773         int err;
2774
2775         fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2776         match_level = outer_match_level;
2777
2778         if (dissector->used_keys &
2779             ~(BIT(FLOW_DISSECTOR_KEY_META) |
2780               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2781               BIT(FLOW_DISSECTOR_KEY_BASIC) |
2782               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2783               BIT(FLOW_DISSECTOR_KEY_VLAN) |
2784               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
2785               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2786               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2787               BIT(FLOW_DISSECTOR_KEY_PORTS) |
2788               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2789               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2790               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2791               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
2792               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2793               BIT(FLOW_DISSECTOR_KEY_TCP) |
2794               BIT(FLOW_DISSECTOR_KEY_IP)  |
2795               BIT(FLOW_DISSECTOR_KEY_CT) |
2796               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2797               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2798               BIT(FLOW_DISSECTOR_KEY_ICMP) |
2799               BIT(FLOW_DISSECTOR_KEY_MPLS))) {
2800                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2801                 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2802                            dissector->used_keys);
2803                 return -EOPNOTSUPP;
2804         }
2805
2806         if (mlx5e_get_tc_tun(filter_dev)) {
2807                 bool match_inner = false;
2808
2809                 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2810                                         outer_match_level, &match_inner);
2811                 if (err)
2812                         return err;
2813
2814                 if (match_inner) {
2815                         /* header pointers should point to the inner headers
2816                          * if the packet was decapsulated already.
2817                          * outer headers are set by parse_tunnel_attr.
2818                          */
2819                         match_level = inner_match_level;
2820                         headers_c = get_match_inner_headers_criteria(spec);
2821                         headers_v = get_match_inner_headers_value(spec);
2822                 }
2823
2824                 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2825                 if (err)
2826                         return err;
2827         }
2828
2829         err = mlx5e_flower_parse_meta(filter_dev, f);
2830         if (err)
2831                 return err;
2832
2833         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2834             !skip_key_basic(filter_dev, f)) {
2835                 struct flow_match_basic match;
2836
2837                 flow_rule_match_basic(rule, &match);
2838                 mlx5e_tc_set_ethertype(priv->mdev, &match,
2839                                        match_level == outer_match_level,
2840                                        headers_c, headers_v);
2841
2842                 if (match.mask->n_proto)
2843                         *match_level = MLX5_MATCH_L2;
2844         }
2845         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2846             is_vlan_dev(filter_dev)) {
2847                 struct flow_dissector_key_vlan filter_dev_mask;
2848                 struct flow_dissector_key_vlan filter_dev_key;
2849                 struct flow_match_vlan match;
2850
2851                 if (is_vlan_dev(filter_dev)) {
2852                         match.key = &filter_dev_key;
2853                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2854                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2855                         match.key->vlan_priority = 0;
2856                         match.mask = &filter_dev_mask;
2857                         memset(match.mask, 0xff, sizeof(*match.mask));
2858                         match.mask->vlan_priority = 0;
2859                 } else {
2860                         flow_rule_match_vlan(rule, &match);
2861                 }
2862                 if (match.mask->vlan_id ||
2863                     match.mask->vlan_priority ||
2864                     match.mask->vlan_tpid) {
2865                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2866                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2867                                          svlan_tag, 1);
2868                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2869                                          svlan_tag, 1);
2870                         } else {
2871                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2872                                          cvlan_tag, 1);
2873                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2874                                          cvlan_tag, 1);
2875                         }
2876
2877                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2878                                  match.mask->vlan_id);
2879                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2880                                  match.key->vlan_id);
2881
2882                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2883                                  match.mask->vlan_priority);
2884                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2885                                  match.key->vlan_priority);
2886
2887                         *match_level = MLX5_MATCH_L2;
2888
2889                         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2890                             match.mask->vlan_eth_type &&
2891                             MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2892                                                     ft_field_support.outer_second_vid,
2893                                                     fs_type)) {
2894                                 MLX5_SET(fte_match_set_misc, misc_c,
2895                                          outer_second_cvlan_tag, 1);
2896                                 spec->match_criteria_enable |=
2897                                         MLX5_MATCH_MISC_PARAMETERS;
2898                         }
2899                 }
2900         } else if (*match_level != MLX5_MATCH_NONE) {
2901                 /* cvlan_tag enabled in match criteria and
2902                  * disabled in match value means both S & C tags
2903                  * don't exist (untagged of both)
2904                  */
2905                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2906                 *match_level = MLX5_MATCH_L2;
2907         }
2908
2909         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2910                 struct flow_match_vlan match;
2911
2912                 flow_rule_match_cvlan(rule, &match);
2913                 if (match.mask->vlan_id ||
2914                     match.mask->vlan_priority ||
2915                     match.mask->vlan_tpid) {
2916                         if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2917                                                      fs_type)) {
2918                                 NL_SET_ERR_MSG_MOD(extack,
2919                                                    "Matching on CVLAN is not supported");
2920                                 return -EOPNOTSUPP;
2921                         }
2922
2923                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2924                                 MLX5_SET(fte_match_set_misc, misc_c,
2925                                          outer_second_svlan_tag, 1);
2926                                 MLX5_SET(fte_match_set_misc, misc_v,
2927                                          outer_second_svlan_tag, 1);
2928                         } else {
2929                                 MLX5_SET(fte_match_set_misc, misc_c,
2930                                          outer_second_cvlan_tag, 1);
2931                                 MLX5_SET(fte_match_set_misc, misc_v,
2932                                          outer_second_cvlan_tag, 1);
2933                         }
2934
2935                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2936                                  match.mask->vlan_id);
2937                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2938                                  match.key->vlan_id);
2939                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2940                                  match.mask->vlan_priority);
2941                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2942                                  match.key->vlan_priority);
2943
2944                         *match_level = MLX5_MATCH_L2;
2945                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2946                 }
2947         }
2948
2949         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2950                 struct flow_match_eth_addrs match;
2951
2952                 flow_rule_match_eth_addrs(rule, &match);
2953                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2954                                              dmac_47_16),
2955                                 match.mask->dst);
2956                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2957                                              dmac_47_16),
2958                                 match.key->dst);
2959
2960                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2961                                              smac_47_16),
2962                                 match.mask->src);
2963                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2964                                              smac_47_16),
2965                                 match.key->src);
2966
2967                 if (!is_zero_ether_addr(match.mask->src) ||
2968                     !is_zero_ether_addr(match.mask->dst))
2969                         *match_level = MLX5_MATCH_L2;
2970         }
2971
2972         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2973                 struct flow_match_control match;
2974
2975                 flow_rule_match_control(rule, &match);
2976                 addr_type = match.key->addr_type;
2977
2978                 /* the HW doesn't support frag first/later */
2979                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2980                         NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
2981                         return -EOPNOTSUPP;
2982                 }
2983
2984                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2985                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2986                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2987                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2988
2989                         /* the HW doesn't need L3 inline to match on frag=no */
2990                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2991                                 *match_level = MLX5_MATCH_L2;
2992         /* ***  L2 attributes parsing up to here *** */
2993                         else
2994                                 *match_level = MLX5_MATCH_L3;
2995                 }
2996         }
2997
2998         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2999                 struct flow_match_basic match;
3000
3001                 flow_rule_match_basic(rule, &match);
3002                 ip_proto = match.key->ip_proto;
3003
3004                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
3005                          match.mask->ip_proto);
3006                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
3007                          match.key->ip_proto);
3008
3009                 if (match.mask->ip_proto)
3010                         *match_level = MLX5_MATCH_L3;
3011         }
3012
3013         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
3014                 struct flow_match_ipv4_addrs match;
3015
3016                 flow_rule_match_ipv4_addrs(rule, &match);
3017                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
3018                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
3019                        &match.mask->src, sizeof(match.mask->src));
3020                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3021                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
3022                        &match.key->src, sizeof(match.key->src));
3023                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
3024                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3025                        &match.mask->dst, sizeof(match.mask->dst));
3026                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3027                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3028                        &match.key->dst, sizeof(match.key->dst));
3029
3030                 if (match.mask->src || match.mask->dst)
3031                         *match_level = MLX5_MATCH_L3;
3032         }
3033
3034         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
3035                 struct flow_match_ipv6_addrs match;
3036
3037                 flow_rule_match_ipv6_addrs(rule, &match);
3038                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
3039                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
3040                        &match.mask->src, sizeof(match.mask->src));
3041                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3042                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
3043                        &match.key->src, sizeof(match.key->src));
3044
3045                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
3046                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
3047                        &match.mask->dst, sizeof(match.mask->dst));
3048                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
3049                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
3050                        &match.key->dst, sizeof(match.key->dst));
3051
3052                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
3053                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
3054                         *match_level = MLX5_MATCH_L3;
3055         }
3056
3057         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
3058                 struct flow_match_ip match;
3059
3060                 flow_rule_match_ip(rule, &match);
3061                 if (match_inner_ecn) {
3062                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
3063                                  match.mask->tos & 0x3);
3064                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
3065                                  match.key->tos & 0x3);
3066                 }
3067
3068                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
3069                          match.mask->tos >> 2);
3070                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
3071                          match.key->tos  >> 2);
3072
3073                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
3074                          match.mask->ttl);
3075                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
3076                          match.key->ttl);
3077
3078                 if (match.mask->ttl &&
3079                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3080                                                 ft_field_support.outer_ipv4_ttl)) {
3081                         NL_SET_ERR_MSG_MOD(extack,
3082                                            "Matching on TTL is not supported");
3083                         return -EOPNOTSUPP;
3084                 }
3085
3086                 if (match.mask->tos || match.mask->ttl)
3087                         *match_level = MLX5_MATCH_L3;
3088         }
3089
3090         /* ***  L3 attributes parsing up to here *** */
3091
3092         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
3093                 struct flow_match_ports match;
3094
3095                 flow_rule_match_ports(rule, &match);
3096                 switch (ip_proto) {
3097                 case IPPROTO_TCP:
3098                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3099                                  tcp_sport, ntohs(match.mask->src));
3100                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3101                                  tcp_sport, ntohs(match.key->src));
3102
3103                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3104                                  tcp_dport, ntohs(match.mask->dst));
3105                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3106                                  tcp_dport, ntohs(match.key->dst));
3107                         break;
3108
3109                 case IPPROTO_UDP:
3110                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3111                                  udp_sport, ntohs(match.mask->src));
3112                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3113                                  udp_sport, ntohs(match.key->src));
3114
3115                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3116                                  udp_dport, ntohs(match.mask->dst));
3117                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3118                                  udp_dport, ntohs(match.key->dst));
3119                         break;
3120                 default:
3121                         NL_SET_ERR_MSG_MOD(extack,
3122                                            "Only UDP and TCP transports are supported for L4 matching");
3123                         netdev_err(priv->netdev,
3124                                    "Only UDP and TCP transport are supported\n");
3125                         return -EINVAL;
3126                 }
3127
3128                 if (match.mask->src || match.mask->dst)
3129                         *match_level = MLX5_MATCH_L4;
3130         }
3131
3132         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
3133                 struct flow_match_tcp match;
3134
3135                 flow_rule_match_tcp(rule, &match);
3136                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
3137                          ntohs(match.mask->flags));
3138                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
3139                          ntohs(match.key->flags));
3140
3141                 if (match.mask->flags)
3142                         *match_level = MLX5_MATCH_L4;
3143         }
3144         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
3145                 struct flow_match_icmp match;
3146
3147                 flow_rule_match_icmp(rule, &match);
3148                 switch (ip_proto) {
3149                 case IPPROTO_ICMP:
3150                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3151                               MLX5_FLEX_PROTO_ICMP)) {
3152                                 NL_SET_ERR_MSG_MOD(extack,
3153                                                    "Match on Flex protocols for ICMP is not supported");
3154                                 return -EOPNOTSUPP;
3155                         }
3156                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
3157                                  match.mask->type);
3158                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
3159                                  match.key->type);
3160                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
3161                                  match.mask->code);
3162                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
3163                                  match.key->code);
3164                         break;
3165                 case IPPROTO_ICMPV6:
3166                         if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3167                               MLX5_FLEX_PROTO_ICMPV6)) {
3168                                 NL_SET_ERR_MSG_MOD(extack,
3169                                                    "Match on Flex protocols for ICMPV6 is not supported");
3170                                 return -EOPNOTSUPP;
3171                         }
3172                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
3173                                  match.mask->type);
3174                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
3175                                  match.key->type);
3176                         MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
3177                                  match.mask->code);
3178                         MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
3179                                  match.key->code);
3180                         break;
3181                 default:
3182                         NL_SET_ERR_MSG_MOD(extack,
3183                                            "Code and type matching only with ICMP and ICMPv6");
3184                         netdev_err(priv->netdev,
3185                                    "Code and type matching only with ICMP and ICMPv6\n");
3186                         return -EINVAL;
3187                 }
3188                 if (match.mask->code || match.mask->type) {
3189                         *match_level = MLX5_MATCH_L4;
3190                         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3191                 }
3192         }
3193         /* Currently supported only for MPLS over UDP */
3194         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3195             !netif_is_bareudp(filter_dev)) {
3196                 NL_SET_ERR_MSG_MOD(extack,
3197                                    "Matching on MPLS is supported only for MPLS over UDP");
3198                 netdev_err(priv->netdev,
3199                            "Matching on MPLS is supported only for MPLS over UDP\n");
3200                 return -EOPNOTSUPP;
3201         }
3202
3203         return 0;
3204 }
3205
3206 static int parse_cls_flower(struct mlx5e_priv *priv,
3207                             struct mlx5e_tc_flow *flow,
3208                             struct mlx5_flow_spec *spec,
3209                             struct flow_cls_offload *f,
3210                             struct net_device *filter_dev)
3211 {
3212         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3213         struct netlink_ext_ack *extack = f->common.extack;
3214         struct mlx5_core_dev *dev = priv->mdev;
3215         struct mlx5_eswitch *esw = dev->priv.eswitch;
3216         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3217         struct mlx5_eswitch_rep *rep;
3218         bool is_eswitch_flow;
3219         int err;
3220
3221         inner_match_level = MLX5_MATCH_NONE;
3222         outer_match_level = MLX5_MATCH_NONE;
3223
3224         err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3225                                  &inner_match_level, &outer_match_level);
3226         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3227                                  outer_match_level : inner_match_level;
3228
3229         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3230         if (!err && is_eswitch_flow) {
3231                 rep = rpriv->rep;
3232                 if (rep->vport != MLX5_VPORT_UPLINK &&
3233                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3234                     esw->offloads.inline_mode < non_tunnel_match_level)) {
3235                         NL_SET_ERR_MSG_MOD(extack,
3236                                            "Flow is not offloaded due to min inline setting");
3237                         netdev_warn(priv->netdev,
3238                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3239                                     non_tunnel_match_level, esw->offloads.inline_mode);
3240                         return -EOPNOTSUPP;
3241                 }
3242         }
3243
3244         flow->attr->inner_match_level = inner_match_level;
3245         flow->attr->outer_match_level = outer_match_level;
3246
3247
3248         return err;
3249 }
3250
3251 struct mlx5_fields {
3252         u8  field;
3253         u8  field_bsize;
3254         u32 field_mask;
3255         u32 offset;
3256         u32 match_offset;
3257 };
3258
3259 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3260                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3261                  offsetof(struct pedit_headers, field) + (off), \
3262                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3263
3264 /* masked values are the same and there are no rewrites that do not have a
3265  * match.
3266  */
3267 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3268         type matchmaskx = *(type *)(matchmaskp); \
3269         type matchvalx = *(type *)(matchvalp); \
3270         type maskx = *(type *)(maskp); \
3271         type valx = *(type *)(valp); \
3272         \
3273         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3274                                                                  matchmaskx)); \
3275 })
3276
3277 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3278                          void *matchmaskp, u8 bsize)
3279 {
3280         bool same = false;
3281
3282         switch (bsize) {
3283         case 8:
3284                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3285                 break;
3286         case 16:
3287                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3288                 break;
3289         case 32:
3290                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3291                 break;
3292         }
3293
3294         return same;
3295 }
3296
3297 static struct mlx5_fields fields[] = {
3298         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3299         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3300         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3301         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3302         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
3303         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3304
3305         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
3306         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
3307         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3308         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3309
3310         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3311                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3312         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3313                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3314         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3315                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3316         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3317                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3318         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3319                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3320         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3321                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3322         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3323                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3324         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3325                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3326         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3327         OFFLOAD(IP_DSCP, 16,  0xc00f, ip6, 0, ip_dscp),
3328
3329         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
3330         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
3331         /* in linux iphdr tcp_flags is 8 bits long */
3332         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
3333
3334         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3335         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
3336 };
3337
3338 static unsigned long mask_to_le(unsigned long mask, int size)
3339 {
3340         __be32 mask_be32;
3341         __be16 mask_be16;
3342
3343         if (size == 32) {
3344                 mask_be32 = (__force __be32)(mask);
3345                 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
3346         } else if (size == 16) {
3347                 mask_be32 = (__force __be32)(mask);
3348                 mask_be16 = *(__be16 *)&mask_be32;
3349                 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
3350         }
3351
3352         return mask;
3353 }
3354
3355 static int offload_pedit_fields(struct mlx5e_priv *priv,
3356                                 int namespace,
3357                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
3358                                 u32 *action_flags,
3359                                 struct netlink_ext_ack *extack)
3360 {
3361         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3362         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3363         void *headers_c, *headers_v, *action, *vals_p;
3364         u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
3365         struct mlx5e_tc_mod_hdr_acts *mod_acts;
3366         unsigned long mask, field_mask;
3367         int i, first, last, next_z;
3368         struct mlx5_fields *f;
3369         u8 cmd;
3370
3371         mod_acts = &parse_attr->mod_hdr_acts;
3372         headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3373         headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3374
3375         set_masks = &hdrs[0].masks;
3376         add_masks = &hdrs[1].masks;
3377         set_vals = &hdrs[0].vals;
3378         add_vals = &hdrs[1].vals;
3379
3380         for (i = 0; i < ARRAY_SIZE(fields); i++) {
3381                 bool skip;
3382
3383                 f = &fields[i];
3384                 /* avoid seeing bits set from previous iterations */
3385                 s_mask = 0;
3386                 a_mask = 0;
3387
3388                 s_masks_p = (void *)set_masks + f->offset;
3389                 a_masks_p = (void *)add_masks + f->offset;
3390
3391                 s_mask = *s_masks_p & f->field_mask;
3392                 a_mask = *a_masks_p & f->field_mask;
3393
3394                 if (!s_mask && !a_mask) /* nothing to offload here */
3395                         continue;
3396
3397                 if (s_mask && a_mask) {
3398                         NL_SET_ERR_MSG_MOD(extack,
3399                                            "can't set and add to the same HW field");
3400                         netdev_warn(priv->netdev,
3401                                     "mlx5: can't set and add to the same HW field (%x)\n",
3402                                     f->field);
3403                         return -EOPNOTSUPP;
3404                 }
3405
3406                 skip = false;
3407                 if (s_mask) {
3408                         void *match_mask = headers_c + f->match_offset;
3409                         void *match_val = headers_v + f->match_offset;
3410
3411                         cmd  = MLX5_ACTION_TYPE_SET;
3412                         mask = s_mask;
3413                         vals_p = (void *)set_vals + f->offset;
3414                         /* don't rewrite if we have a match on the same value */
3415                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
3416                                          match_mask, f->field_bsize))
3417                                 skip = true;
3418                         /* clear to denote we consumed this field */
3419                         *s_masks_p &= ~f->field_mask;
3420                 } else {
3421                         cmd  = MLX5_ACTION_TYPE_ADD;
3422                         mask = a_mask;
3423                         vals_p = (void *)add_vals + f->offset;
3424                         /* add 0 is no change */
3425                         if ((*(u32 *)vals_p & f->field_mask) == 0)
3426                                 skip = true;
3427                         /* clear to denote we consumed this field */
3428                         *a_masks_p &= ~f->field_mask;
3429                 }
3430                 if (skip)
3431                         continue;
3432
3433                 mask = mask_to_le(mask, f->field_bsize);
3434
3435                 first = find_first_bit(&mask, f->field_bsize);
3436                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3437                 last  = find_last_bit(&mask, f->field_bsize);
3438                 if (first < next_z && next_z < last) {
3439                         NL_SET_ERR_MSG_MOD(extack,
3440                                            "rewrite of few sub-fields isn't supported");
3441                         netdev_warn(priv->netdev,
3442                                     "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3443                                     mask);
3444                         return -EOPNOTSUPP;
3445                 }
3446
3447                 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3448                 if (IS_ERR(action)) {
3449                         NL_SET_ERR_MSG_MOD(extack,
3450                                            "too many pedit actions, can't offload");
3451                         mlx5_core_warn(priv->mdev,
3452                                        "mlx5: parsed %d pedit actions, can't do more\n",
3453                                        mod_acts->num_actions);
3454                         return PTR_ERR(action);
3455                 }
3456
3457                 MLX5_SET(set_action_in, action, action_type, cmd);
3458                 MLX5_SET(set_action_in, action, field, f->field);
3459
3460                 if (cmd == MLX5_ACTION_TYPE_SET) {
3461                         int start;
3462
3463                         field_mask = mask_to_le(f->field_mask, f->field_bsize);
3464
3465                         /* if field is bit sized it can start not from first bit */
3466                         start = find_first_bit(&field_mask, f->field_bsize);
3467
3468                         MLX5_SET(set_action_in, action, offset, first - start);
3469                         /* length is num of bits to be written, zero means length of 32 */
3470                         MLX5_SET(set_action_in, action, length, (last - first + 1));
3471                 }
3472
3473                 if (f->field_bsize == 32)
3474                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3475                 else if (f->field_bsize == 16)
3476                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3477                 else if (f->field_bsize == 8)
3478                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3479
3480                 ++mod_acts->num_actions;
3481         }
3482
3483         return 0;
3484 }
3485
3486 static const struct pedit_headers zero_masks = {};
3487
3488 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3489                                        struct mlx5e_tc_flow_parse_attr *parse_attr,
3490                                        struct netlink_ext_ack *extack)
3491 {
3492         struct pedit_headers *cmd_masks;
3493         u8 cmd;
3494
3495         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3496                 cmd_masks = &parse_attr->hdrs[cmd].masks;
3497                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3498                         NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3499                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3500                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3501                                        16, 1, cmd_masks, sizeof(zero_masks), true);
3502                         return -EOPNOTSUPP;
3503                 }
3504         }
3505
3506         return 0;
3507 }
3508
3509 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3510                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
3511                                  u32 *action_flags,
3512                                  struct netlink_ext_ack *extack)
3513 {
3514         int err;
3515
3516         err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3517         if (err)
3518                 goto out_dealloc_parsed_actions;
3519
3520         err = verify_offload_pedit_fields(priv, parse_attr, extack);
3521         if (err)
3522                 goto out_dealloc_parsed_actions;
3523
3524         return 0;
3525
3526 out_dealloc_parsed_actions:
3527         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3528         return err;
3529 }
3530
3531 struct ip_ttl_word {
3532         __u8    ttl;
3533         __u8    protocol;
3534         __sum16 check;
3535 };
3536
3537 struct ipv6_hoplimit_word {
3538         __be16  payload_len;
3539         __u8    nexthdr;
3540         __u8    hop_limit;
3541 };
3542
3543 static bool
3544 is_action_keys_supported(const struct flow_action_entry *act, bool ct_flow,
3545                          bool *modify_ip_header, bool *modify_tuple,
3546                          struct netlink_ext_ack *extack)
3547 {
3548         u32 mask, offset;
3549         u8 htype;
3550
3551         htype = act->mangle.htype;
3552         offset = act->mangle.offset;
3553         mask = ~act->mangle.mask;
3554         /* For IPv4 & IPv6 header check 4 byte word,
3555          * to determine that modified fields
3556          * are NOT ttl & hop_limit only.
3557          */
3558         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3559                 struct ip_ttl_word *ttl_word =
3560                         (struct ip_ttl_word *)&mask;
3561
3562                 if (offset != offsetof(struct iphdr, ttl) ||
3563                     ttl_word->protocol ||
3564                     ttl_word->check) {
3565                         *modify_ip_header = true;
3566                 }
3567
3568                 if (offset >= offsetof(struct iphdr, saddr))
3569                         *modify_tuple = true;
3570
3571                 if (ct_flow && *modify_tuple) {
3572                         NL_SET_ERR_MSG_MOD(extack,
3573                                            "can't offload re-write of ipv4 address with action ct");
3574                         return false;
3575                 }
3576         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3577                 struct ipv6_hoplimit_word *hoplimit_word =
3578                         (struct ipv6_hoplimit_word *)&mask;
3579
3580                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3581                     hoplimit_word->payload_len ||
3582                     hoplimit_word->nexthdr) {
3583                         *modify_ip_header = true;
3584                 }
3585
3586                 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3587                         *modify_tuple = true;
3588
3589                 if (ct_flow && *modify_tuple) {
3590                         NL_SET_ERR_MSG_MOD(extack,
3591                                            "can't offload re-write of ipv6 address with action ct");
3592                         return false;
3593                 }
3594         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3595                    htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3596                 *modify_tuple = true;
3597                 if (ct_flow) {
3598                         NL_SET_ERR_MSG_MOD(extack,
3599                                            "can't offload re-write of transport header ports with action ct");
3600                         return false;
3601                 }
3602         }
3603
3604         return true;
3605 }
3606
3607 static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3608                                    bool ct_flow, struct netlink_ext_ack *extack,
3609                                    struct mlx5e_priv *priv,
3610                                    struct mlx5_flow_spec *spec)
3611 {
3612         if (!modify_tuple || ct_clear)
3613                 return true;
3614
3615         if (ct_flow) {
3616                 NL_SET_ERR_MSG_MOD(extack,
3617                                    "can't offload tuple modification with non-clear ct()");
3618                 netdev_info(priv->netdev,
3619                             "can't offload tuple modification with non-clear ct()");
3620                 return false;
3621         }
3622
3623         /* Add ct_state=-trk match so it will be offloaded for non ct flows
3624          * (or after clear action), as otherwise, since the tuple is changed,
3625          * we can't restore ct state
3626          */
3627         if (mlx5_tc_ct_add_no_trk_match(spec)) {
3628                 NL_SET_ERR_MSG_MOD(extack,
3629                                    "can't offload tuple modification with ct matches and no ct(clear) action");
3630                 netdev_info(priv->netdev,
3631                             "can't offload tuple modification with ct matches and no ct(clear) action");
3632                 return false;
3633         }
3634
3635         return true;
3636 }
3637
3638 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3639                                           struct mlx5_flow_spec *spec,
3640                                           struct flow_action *flow_action,
3641                                           u32 actions, bool ct_flow,
3642                                           bool ct_clear,
3643                                           struct netlink_ext_ack *extack)
3644 {
3645         const struct flow_action_entry *act;
3646         bool modify_ip_header, modify_tuple;
3647         void *headers_c;
3648         void *headers_v;
3649         u16 ethertype;
3650         u8 ip_proto;
3651         int i;
3652
3653         headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3654         headers_v = mlx5e_get_match_headers_value(actions, spec);
3655         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3656
3657         /* for non-IP we only re-write MACs, so we're okay */
3658         if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3659             ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3660                 goto out_ok;
3661
3662         modify_ip_header = false;
3663         modify_tuple = false;
3664         flow_action_for_each(i, act, flow_action) {
3665                 if (act->id != FLOW_ACTION_MANGLE &&
3666                     act->id != FLOW_ACTION_ADD)
3667                         continue;
3668
3669                 if (!is_action_keys_supported(act, ct_flow,
3670                                               &modify_ip_header,
3671                                               &modify_tuple, extack))
3672                         return false;
3673         }
3674
3675         if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3676                                     priv, spec))
3677                 return false;
3678
3679         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3680         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3681             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3682                 NL_SET_ERR_MSG_MOD(extack,
3683                                    "can't offload re-write of non TCP/UDP");
3684                 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3685                             ip_proto);
3686                 return false;
3687         }
3688
3689 out_ok:
3690         return true;
3691 }
3692
3693 static bool
3694 actions_match_supported_fdb(struct mlx5e_priv *priv,
3695                             struct mlx5e_tc_flow_parse_attr *parse_attr,
3696                             struct mlx5e_tc_flow *flow,
3697                             struct netlink_ext_ack *extack)
3698 {
3699         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3700         bool ct_flow, ct_clear;
3701
3702         ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3703         ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3704
3705         if (esw_attr->split_count && ct_flow &&
3706             !MLX5_CAP_GEN(esw_attr->in_mdev, reg_c_preserve)) {
3707                 /* All registers used by ct are cleared when using
3708                  * split rules.
3709                  */
3710                 NL_SET_ERR_MSG_MOD(extack, "Can't offload mirroring with action ct");
3711                 return false;
3712         }
3713
3714         if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3715                 NL_SET_ERR_MSG_MOD(extack,
3716                                    "current firmware doesn't support split rule for port mirroring");
3717                 netdev_warn_once(priv->netdev,
3718                                  "current firmware doesn't support split rule for port mirroring\n");
3719                 return false;
3720         }
3721
3722         return true;
3723 }
3724
3725 static bool
3726 actions_match_supported(struct mlx5e_priv *priv,
3727                         struct flow_action *flow_action,
3728                         u32 actions,
3729                         struct mlx5e_tc_flow_parse_attr *parse_attr,
3730                         struct mlx5e_tc_flow *flow,
3731                         struct netlink_ext_ack *extack)
3732 {
3733         bool ct_flow, ct_clear;
3734
3735         ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3736         ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3737
3738         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3739             !modify_header_match_supported(priv, &parse_attr->spec, flow_action,
3740                                            actions, ct_flow, ct_clear, extack))
3741                 return false;
3742
3743         if (mlx5e_is_eswitch_flow(flow) &&
3744             !actions_match_supported_fdb(priv, parse_attr, flow, extack))
3745                 return false;
3746
3747         return true;
3748 }
3749
3750 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3751 {
3752         return priv->mdev == peer_priv->mdev;
3753 }
3754
3755 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3756 {
3757         struct mlx5_core_dev *fmdev, *pmdev;
3758         u64 fsystem_guid, psystem_guid;
3759
3760         fmdev = priv->mdev;
3761         pmdev = peer_priv->mdev;
3762
3763         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3764         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3765
3766         return (fsystem_guid == psystem_guid);
3767 }
3768
3769 static int
3770 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3771                                 struct mlx5e_tc_flow *flow,
3772                                 struct mlx5_flow_attr *attr,
3773                                 struct netlink_ext_ack *extack)
3774 {
3775         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3776         struct pedit_headers_action *hdrs = parse_attr->hdrs;
3777         enum mlx5_flow_namespace_type ns_type;
3778         int err;
3779
3780         if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3781             !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3782                 return 0;
3783
3784         ns_type = mlx5e_get_flow_namespace(flow);
3785
3786         err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3787         if (err)
3788                 return err;
3789
3790         if (parse_attr->mod_hdr_acts.num_actions > 0)
3791                 return 0;
3792
3793         /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3794         attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3795         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3796
3797         if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3798                 return 0;
3799
3800         if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3801               (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3802                 attr->esw_attr->split_count = 0;
3803
3804         return 0;
3805 }
3806
3807 static struct mlx5_flow_attr*
3808 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3809                                    enum mlx5_flow_namespace_type ns_type)
3810 {
3811         struct mlx5e_tc_flow_parse_attr *parse_attr;
3812         u32 attr_sz = ns_to_attr_sz(ns_type);
3813         struct mlx5_flow_attr *attr2;
3814
3815         attr2 = mlx5_alloc_flow_attr(ns_type);
3816         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3817         if (!attr2 || !parse_attr) {
3818                 kvfree(parse_attr);
3819                 kfree(attr2);
3820                 return NULL;
3821         }
3822
3823         memcpy(attr2, attr, attr_sz);
3824         INIT_LIST_HEAD(&attr2->list);
3825         parse_attr->filter_dev = attr->parse_attr->filter_dev;
3826         attr2->action = 0;
3827         attr2->flags = 0;
3828         attr2->parse_attr = parse_attr;
3829         attr2->dest_chain = 0;
3830         attr2->dest_ft = NULL;
3831
3832         if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3833                 attr2->esw_attr->out_count = 0;
3834                 attr2->esw_attr->split_count = 0;
3835         }
3836
3837         attr2->branch_true = NULL;
3838         attr2->branch_false = NULL;
3839         attr2->jumping_attr = NULL;
3840         return attr2;
3841 }
3842
3843 struct mlx5_flow_attr *
3844 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3845 {
3846         struct mlx5_esw_flow_attr *esw_attr;
3847         struct mlx5_flow_attr *attr;
3848         int i;
3849
3850         list_for_each_entry(attr, &flow->attrs, list) {
3851                 esw_attr = attr->esw_attr;
3852                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3853                         if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3854                                 return attr;
3855                 }
3856         }
3857
3858         return NULL;
3859 }
3860
3861 void
3862 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3863 {
3864         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3865         struct mlx5_flow_attr *attr;
3866
3867         list_for_each_entry(attr, &flow->attrs, list) {
3868                 if (list_is_last(&attr->list, &flow->attrs))
3869                         break;
3870
3871                 mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3872         }
3873 }
3874
3875 static void
3876 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3877 {
3878         struct mlx5_flow_attr *attr, *tmp;
3879
3880         list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3881                 if (list_is_last(&attr->list, &flow->attrs))
3882                         break;
3883
3884                 mlx5_free_flow_attr(flow, attr);
3885                 free_branch_attr(flow, attr->branch_true);
3886                 free_branch_attr(flow, attr->branch_false);
3887
3888                 list_del(&attr->list);
3889                 kvfree(attr->parse_attr);
3890                 kfree(attr);
3891         }
3892 }
3893
3894 int
3895 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3896 {
3897         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3898         struct mlx5_flow_attr *attr;
3899         int err = 0;
3900
3901         list_for_each_entry(attr, &flow->attrs, list) {
3902                 if (list_is_last(&attr->list, &flow->attrs))
3903                         break;
3904
3905                 err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3906                 if (err)
3907                         break;
3908         }
3909
3910         return err;
3911 }
3912
3913 /* TC filter rule HW translation:
3914  *
3915  * +---------------------+
3916  * + ft prio (tc chain)  +
3917  * + original match      +
3918  * +---------------------+
3919  *           |
3920  *           | if multi table action
3921  *           |
3922  *           v
3923  * +---------------------+
3924  * + post act ft         |<----.
3925  * + match fte id        |     | split on multi table action
3926  * + do actions          |-----'
3927  * +---------------------+
3928  *           |
3929  *           |
3930  *           v
3931  * Do rest of the actions after last multi table action.
3932  */
3933 static int
3934 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3935 {
3936         struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3937         struct mlx5_flow_attr *attr, *next_attr = NULL;
3938         struct mlx5e_post_act_handle *handle;
3939         int err;
3940
3941         /* This is going in reverse order as needed.
3942          * The first entry is the last attribute.
3943          */
3944         list_for_each_entry(attr, &flow->attrs, list) {
3945                 if (!next_attr) {
3946                         /* Set counter action on last post act rule. */
3947                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3948                 }
3949
3950                 if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3951                         err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3952                         if (err)
3953                                 goto out_free;
3954                 }
3955
3956                 /* Don't add post_act rule for first attr (last in the list).
3957                  * It's being handled by the caller.
3958                  */
3959                 if (list_is_last(&attr->list, &flow->attrs))
3960                         break;
3961
3962                 err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3963                 if (err)
3964                         goto out_free;
3965
3966                 err = post_process_attr(flow, attr, true, extack);
3967                 if (err)
3968                         goto out_free;
3969
3970                 handle = mlx5e_tc_post_act_add(post_act, attr);
3971                 if (IS_ERR(handle)) {
3972                         err = PTR_ERR(handle);
3973                         goto out_free;
3974                 }
3975
3976                 attr->post_act_handle = handle;
3977
3978                 if (attr->jumping_attr) {
3979                         err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3980                         if (err)
3981                                 goto out_free;
3982                 }
3983
3984                 next_attr = attr;
3985         }
3986
3987         if (flow_flag_test(flow, SLOW))
3988                 goto out;
3989
3990         err = mlx5e_tc_offload_flow_post_acts(flow);
3991         if (err)
3992                 goto out_free;
3993
3994 out:
3995         return 0;
3996
3997 out_free:
3998         free_flow_post_acts(flow);
3999         return err;
4000 }
4001
4002 static int
4003 alloc_branch_attr(struct mlx5e_tc_flow *flow,
4004                   struct mlx5e_tc_act_branch_ctrl *cond,
4005                   struct mlx5_flow_attr **cond_attr,
4006                   u32 *jump_count,
4007                   struct netlink_ext_ack *extack)
4008 {
4009         struct mlx5_flow_attr *attr;
4010         int err = 0;
4011
4012         *cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
4013                                                         mlx5e_get_flow_namespace(flow));
4014         if (!(*cond_attr))
4015                 return -ENOMEM;
4016
4017         attr = *cond_attr;
4018
4019         switch (cond->act_id) {
4020         case FLOW_ACTION_DROP:
4021                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
4022                 break;
4023         case FLOW_ACTION_ACCEPT:
4024         case FLOW_ACTION_PIPE:
4025                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4026                 attr->dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow->priv));
4027                 break;
4028         case FLOW_ACTION_JUMP:
4029                 if (*jump_count) {
4030                         NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
4031                         err = -EOPNOTSUPP;
4032                         goto out_err;
4033                 }
4034                 *jump_count = cond->extval;
4035                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4036                 attr->dest_ft = mlx5e_tc_post_act_get_ft(get_post_action(flow->priv));
4037                 break;
4038         default:
4039                 err = -EOPNOTSUPP;
4040                 goto out_err;
4041         }
4042
4043         return err;
4044 out_err:
4045         kfree(*cond_attr);
4046         *cond_attr = NULL;
4047         return err;
4048 }
4049
4050 static void
4051 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
4052                struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
4053                struct mlx5e_tc_jump_state *jump_state)
4054 {
4055         if (!jump_state->jump_count)
4056                 return;
4057
4058         /* Single tc action can instantiate multiple offload actions (e.g. pedit)
4059          * Jump only over a tc action
4060          */
4061         if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
4062                 return;
4063
4064         jump_state->last_id = act->id;
4065         jump_state->last_index = act->hw_index;
4066
4067         /* nothing to do for intermediate actions */
4068         if (--jump_state->jump_count > 1)
4069                 return;
4070
4071         if (jump_state->jump_count == 1) { /* last action in the jump action list */
4072
4073                 /* create a new attribute after this action */
4074                 jump_state->jump_target = true;
4075
4076                 if (tc_act->is_terminating_action) { /* the branch ends here */
4077                         attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
4078                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
4079                 } else { /* the branch continues executing the rest of the actions */
4080                         struct mlx5e_post_act *post_act;
4081
4082                         attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4083                         post_act = get_post_action(priv);
4084                         attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
4085                 }
4086         } else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
4087                 /* This is the post action for the jumping attribute (either red or green)
4088                  * Use the stored jumping_attr to set the post act id on the jumping attribute
4089                  */
4090                 attr->jumping_attr = jump_state->jumping_attr;
4091         }
4092 }
4093
4094 static int
4095 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
4096                   struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
4097                   struct mlx5e_tc_jump_state *jump_state,
4098                   struct netlink_ext_ack *extack)
4099 {
4100         struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
4101         u32 jump_count = jump_state->jump_count;
4102         int err;
4103
4104         if (!tc_act->get_branch_ctrl)
4105                 return 0;
4106
4107         tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
4108
4109         err = alloc_branch_attr(flow, &cond_true,
4110                                 &attr->branch_true, &jump_count, extack);
4111         if (err)
4112                 goto out_err;
4113
4114         if (jump_count)
4115                 jump_state->jumping_attr = attr->branch_true;
4116
4117         err = alloc_branch_attr(flow, &cond_false,
4118                                 &attr->branch_false, &jump_count, extack);
4119         if (err)
4120                 goto err_branch_false;
4121
4122         if (jump_count && !jump_state->jumping_attr)
4123                 jump_state->jumping_attr = attr->branch_false;
4124
4125         jump_state->jump_count = jump_count;
4126         return 0;
4127
4128 err_branch_false:
4129         free_branch_attr(flow, attr->branch_true);
4130 out_err:
4131         return err;
4132 }
4133
4134 static int
4135 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
4136                  struct flow_action *flow_action)
4137 {
4138         struct netlink_ext_ack *extack = parse_state->extack;
4139         struct mlx5e_tc_flow_action flow_action_reorder;
4140         struct mlx5e_tc_flow *flow = parse_state->flow;
4141         struct mlx5e_tc_jump_state jump_state = {};
4142         struct mlx5_flow_attr *attr = flow->attr;
4143         enum mlx5_flow_namespace_type ns_type;
4144         struct mlx5e_priv *priv = flow->priv;
4145         struct flow_action_entry *act, **_act;
4146         struct mlx5e_tc_act *tc_act;
4147         int err, i;
4148
4149         flow_action_reorder.num_entries = flow_action->num_entries;
4150         flow_action_reorder.entries = kcalloc(flow_action->num_entries,
4151                                               sizeof(flow_action), GFP_KERNEL);
4152         if (!flow_action_reorder.entries)
4153                 return -ENOMEM;
4154
4155         mlx5e_tc_act_reorder_flow_actions(flow_action, &flow_action_reorder);
4156
4157         ns_type = mlx5e_get_flow_namespace(flow);
4158         list_add(&attr->list, &flow->attrs);
4159
4160         flow_action_for_each(i, _act, &flow_action_reorder) {
4161                 jump_state.jump_target = false;
4162                 act = *_act;
4163                 tc_act = mlx5e_tc_act_get(act->id, ns_type);
4164                 if (!tc_act) {
4165                         NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
4166                         err = -EOPNOTSUPP;
4167                         goto out_free;
4168                 }
4169
4170                 if (!tc_act->can_offload(parse_state, act, i, attr)) {
4171                         err = -EOPNOTSUPP;
4172                         goto out_free;
4173                 }
4174
4175                 err = tc_act->parse_action(parse_state, act, priv, attr);
4176                 if (err)
4177                         goto out_free;
4178
4179                 dec_jump_count(act, tc_act, attr, priv, &jump_state);
4180
4181                 err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
4182                 if (err)
4183                         goto out_free;
4184
4185                 parse_state->actions |= attr->action;
4186
4187                 /* Split attr for multi table act if not the last act. */
4188                 if (jump_state.jump_target ||
4189                     (tc_act->is_multi_table_act &&
4190                     tc_act->is_multi_table_act(priv, act, attr) &&
4191                     i < flow_action_reorder.num_entries - 1)) {
4192                         err = mlx5e_tc_act_post_parse(parse_state, flow_action, attr, ns_type);
4193                         if (err)
4194                                 goto out_free;
4195
4196                         attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
4197                         if (!attr) {
4198                                 err = -ENOMEM;
4199                                 goto out_free;
4200                         }
4201
4202                         list_add(&attr->list, &flow->attrs);
4203                 }
4204         }
4205
4206         kfree(flow_action_reorder.entries);
4207
4208         err = mlx5e_tc_act_post_parse(parse_state, flow_action, attr, ns_type);
4209         if (err)
4210                 goto out_free_post_acts;
4211
4212         err = alloc_flow_post_acts(flow, extack);
4213         if (err)
4214                 goto out_free_post_acts;
4215
4216         return 0;
4217
4218 out_free:
4219         kfree(flow_action_reorder.entries);
4220 out_free_post_acts:
4221         free_flow_post_acts(flow);
4222
4223         return err;
4224 }
4225
4226 static int
4227 flow_action_supported(struct flow_action *flow_action,
4228                       struct netlink_ext_ack *extack)
4229 {
4230         if (!flow_action_has_entries(flow_action)) {
4231                 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
4232                 return -EINVAL;
4233         }
4234
4235         if (!flow_action_hw_stats_check(flow_action, extack,
4236                                         FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
4237                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4238                 return -EOPNOTSUPP;
4239         }
4240
4241         return 0;
4242 }
4243
4244 static int
4245 parse_tc_nic_actions(struct mlx5e_priv *priv,
4246                      struct flow_action *flow_action,
4247                      struct mlx5e_tc_flow *flow,
4248                      struct netlink_ext_ack *extack)
4249 {
4250         struct mlx5e_tc_act_parse_state *parse_state;
4251         struct mlx5e_tc_flow_parse_attr *parse_attr;
4252         struct mlx5_flow_attr *attr = flow->attr;
4253         int err;
4254
4255         err = flow_action_supported(flow_action, extack);
4256         if (err)
4257                 return err;
4258
4259         attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
4260         parse_attr = attr->parse_attr;
4261         parse_state = &parse_attr->parse_state;
4262         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4263         parse_state->ct_priv = get_ct_priv(priv);
4264
4265         err = parse_tc_actions(parse_state, flow_action);
4266         if (err)
4267                 return err;
4268
4269         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4270         if (err)
4271                 return err;
4272
4273         err = verify_attr_actions(attr->action, extack);
4274         if (err)
4275                 return err;
4276
4277         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4278                                      parse_attr, flow, extack))
4279                 return -EOPNOTSUPP;
4280
4281         return 0;
4282 }
4283
4284 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4285                                   struct net_device *peer_netdev)
4286 {
4287         struct mlx5e_priv *peer_priv;
4288
4289         peer_priv = netdev_priv(peer_netdev);
4290
4291         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4292                 mlx5e_eswitch_vf_rep(priv->netdev) &&
4293                 mlx5e_eswitch_vf_rep(peer_netdev) &&
4294                 mlx5e_same_hw_devs(priv, peer_priv));
4295 }
4296
4297 static bool same_hw_reps(struct mlx5e_priv *priv,
4298                          struct net_device *peer_netdev)
4299 {
4300         struct mlx5e_priv *peer_priv;
4301
4302         peer_priv = netdev_priv(peer_netdev);
4303
4304         return mlx5e_eswitch_rep(priv->netdev) &&
4305                mlx5e_eswitch_rep(peer_netdev) &&
4306                mlx5e_same_hw_devs(priv, peer_priv);
4307 }
4308
4309 static bool is_lag_dev(struct mlx5e_priv *priv,
4310                        struct net_device *peer_netdev)
4311 {
4312         return ((mlx5_lag_is_sriov(priv->mdev) ||
4313                  mlx5_lag_is_multipath(priv->mdev)) &&
4314                  same_hw_reps(priv, peer_netdev));
4315 }
4316
4317 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4318 {
4319         if (same_hw_reps(priv, out_dev) &&
4320             MLX5_CAP_PORT_SELECTION(priv->mdev, port_select_flow_table) &&
4321             MLX5_CAP_GEN(priv->mdev, create_lag_when_not_master_up))
4322                 return true;
4323
4324         return false;
4325 }
4326
4327 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4328                                     struct net_device *out_dev)
4329 {
4330         if (is_merged_eswitch_vfs(priv, out_dev))
4331                 return true;
4332
4333         if (is_multiport_eligible(priv, out_dev))
4334                 return true;
4335
4336         if (is_lag_dev(priv, out_dev))
4337                 return true;
4338
4339         return mlx5e_eswitch_rep(out_dev) &&
4340                same_port_devs(priv, netdev_priv(out_dev));
4341 }
4342
4343 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4344                                       struct mlx5_flow_attr *attr,
4345                                       int ifindex,
4346                                       enum mlx5e_tc_int_port_type type,
4347                                       u32 *action,
4348                                       int out_index)
4349 {
4350         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4351         struct mlx5e_tc_int_port_priv *int_port_priv;
4352         struct mlx5e_tc_flow_parse_attr *parse_attr;
4353         struct mlx5e_tc_int_port *dest_int_port;
4354         int err;
4355
4356         parse_attr = attr->parse_attr;
4357         int_port_priv = mlx5e_get_int_port_priv(priv);
4358
4359         dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4360         if (IS_ERR(dest_int_port))
4361                 return PTR_ERR(dest_int_port);
4362
4363         err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4364                                         MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4365                                         mlx5e_tc_int_port_get_metadata(dest_int_port));
4366         if (err) {
4367                 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4368                 return err;
4369         }
4370
4371         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4372
4373         esw_attr->dest_int_port = dest_int_port;
4374         esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4375
4376         /* Forward to root fdb for matching against the new source vport */
4377         attr->dest_chain = 0;
4378
4379         return 0;
4380 }
4381
4382 static int
4383 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4384                      struct flow_action *flow_action,
4385                      struct mlx5e_tc_flow *flow,
4386                      struct netlink_ext_ack *extack)
4387 {
4388         struct mlx5e_tc_act_parse_state *parse_state;
4389         struct mlx5e_tc_flow_parse_attr *parse_attr;
4390         struct mlx5_flow_attr *attr = flow->attr;
4391         struct mlx5_esw_flow_attr *esw_attr;
4392         struct net_device *filter_dev;
4393         int err;
4394
4395         err = flow_action_supported(flow_action, extack);
4396         if (err)
4397                 return err;
4398
4399         esw_attr = attr->esw_attr;
4400         parse_attr = attr->parse_attr;
4401         filter_dev = parse_attr->filter_dev;
4402         parse_state = &parse_attr->parse_state;
4403         mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4404         parse_state->ct_priv = get_ct_priv(priv);
4405
4406         err = parse_tc_actions(parse_state, flow_action);
4407         if (err)
4408                 return err;
4409
4410         /* Forward to/from internal port can only have 1 dest */
4411         if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4412             esw_attr->out_count > 1) {
4413                 NL_SET_ERR_MSG_MOD(extack,
4414                                    "Rules with internal port can have only one destination");
4415                 return -EOPNOTSUPP;
4416         }
4417
4418         /* Forward from tunnel/internal port to internal port is not supported */
4419         if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4420             esw_attr->dest_int_port) {
4421                 NL_SET_ERR_MSG_MOD(extack,
4422                                    "Forwarding from tunnel/internal port to internal port is not supported");
4423                 return -EOPNOTSUPP;
4424         }
4425
4426         err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4427         if (err)
4428                 return err;
4429
4430         if (!actions_match_supported(priv, flow_action, parse_state->actions,
4431                                      parse_attr, flow, extack))
4432                 return -EOPNOTSUPP;
4433
4434         return 0;
4435 }
4436
4437 static void get_flags(int flags, unsigned long *flow_flags)
4438 {
4439         unsigned long __flow_flags = 0;
4440
4441         if (flags & MLX5_TC_FLAG(INGRESS))
4442                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4443         if (flags & MLX5_TC_FLAG(EGRESS))
4444                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4445
4446         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4447                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4448         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4449                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4450         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4451                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4452
4453         *flow_flags = __flow_flags;
4454 }
4455
4456 static const struct rhashtable_params tc_ht_params = {
4457         .head_offset = offsetof(struct mlx5e_tc_flow, node),
4458         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4459         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4460         .automatic_shrinking = true,
4461 };
4462
4463 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4464                                     unsigned long flags)
4465 {
4466         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4467         struct mlx5e_rep_priv *rpriv;
4468
4469         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4470                 rpriv = priv->ppriv;
4471                 return &rpriv->tc_ht;
4472         } else /* NIC offload */
4473                 return &tc->ht;
4474 }
4475
4476 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4477 {
4478         struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4479         struct mlx5_flow_attr *attr = flow->attr;
4480         bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4481                 flow_flag_test(flow, INGRESS);
4482         bool act_is_encap = !!(attr->action &
4483                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4484         bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
4485                                                 MLX5_DEVCOM_ESW_OFFLOADS);
4486
4487         if (!esw_paired)
4488                 return false;
4489
4490         if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4491              mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4492             (is_rep_ingress || act_is_encap))
4493                 return true;
4494
4495         return false;
4496 }
4497
4498 struct mlx5_flow_attr *
4499 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4500 {
4501         u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB)  ?
4502                                 sizeof(struct mlx5_esw_flow_attr) :
4503                                 sizeof(struct mlx5_nic_flow_attr);
4504         struct mlx5_flow_attr *attr;
4505
4506         attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4507         if (!attr)
4508                 return attr;
4509
4510         INIT_LIST_HEAD(&attr->list);
4511         return attr;
4512 }
4513
4514 static void
4515 mlx5_free_flow_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4516 {
4517         struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4518         bool vf_tun;
4519
4520         if (!attr)
4521                 return;
4522
4523         if (attr->post_act_handle)
4524                 mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4525
4526         clean_encap_dests(flow->priv, flow, attr, &vf_tun);
4527
4528         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4529                 mlx5_fc_destroy(counter_dev, attr->counter);
4530
4531         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4532                 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4533                 if (attr->modify_hdr)
4534                         mlx5_modify_header_dealloc(flow->priv->mdev, attr->modify_hdr);
4535         }
4536 }
4537
4538 static int
4539 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4540                  struct flow_cls_offload *f, unsigned long flow_flags,
4541                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
4542                  struct mlx5e_tc_flow **__flow)
4543 {
4544         struct mlx5e_tc_flow_parse_attr *parse_attr;
4545         struct mlx5_flow_attr *attr;
4546         struct mlx5e_tc_flow *flow;
4547         int err = -ENOMEM;
4548         int out_index;
4549
4550         flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4551         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4552         if (!parse_attr || !flow)
4553                 goto err_free;
4554
4555         flow->flags = flow_flags;
4556         flow->cookie = f->cookie;
4557         flow->priv = priv;
4558
4559         attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4560         if (!attr)
4561                 goto err_free;
4562
4563         flow->attr = attr;
4564
4565         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4566                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4567         INIT_LIST_HEAD(&flow->hairpin);
4568         INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4569         INIT_LIST_HEAD(&flow->attrs);
4570         refcount_set(&flow->refcnt, 1);
4571         init_completion(&flow->init_done);
4572         init_completion(&flow->del_hw_done);
4573
4574         *__flow = flow;
4575         *__parse_attr = parse_attr;
4576
4577         return 0;
4578
4579 err_free:
4580         kfree(flow);
4581         kvfree(parse_attr);
4582         return err;
4583 }
4584
4585 static void
4586 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4587                      struct mlx5e_tc_flow_parse_attr *parse_attr,
4588                      struct flow_cls_offload *f)
4589 {
4590         attr->parse_attr = parse_attr;
4591         attr->chain = f->common.chain_index;
4592         attr->prio = f->common.prio;
4593 }
4594
4595 static void
4596 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4597                          struct mlx5e_priv *priv,
4598                          struct mlx5e_tc_flow_parse_attr *parse_attr,
4599                          struct flow_cls_offload *f,
4600                          struct mlx5_eswitch_rep *in_rep,
4601                          struct mlx5_core_dev *in_mdev)
4602 {
4603         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4604         struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4605
4606         mlx5e_flow_attr_init(attr, parse_attr, f);
4607
4608         esw_attr->in_rep = in_rep;
4609         esw_attr->in_mdev = in_mdev;
4610
4611         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4612             MLX5_COUNTER_SOURCE_ESWITCH)
4613                 esw_attr->counter_dev = in_mdev;
4614         else
4615                 esw_attr->counter_dev = priv->mdev;
4616 }
4617
4618 static struct mlx5e_tc_flow *
4619 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4620                      struct flow_cls_offload *f,
4621                      unsigned long flow_flags,
4622                      struct net_device *filter_dev,
4623                      struct mlx5_eswitch_rep *in_rep,
4624                      struct mlx5_core_dev *in_mdev)
4625 {
4626         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4627         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4628         struct netlink_ext_ack *extack = f->common.extack;
4629         struct mlx5e_tc_flow_parse_attr *parse_attr;
4630         struct mlx5e_tc_flow *flow;
4631         int attr_size, err;
4632
4633         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4634         attr_size  = sizeof(struct mlx5_esw_flow_attr);
4635         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4636                                &parse_attr, &flow);
4637         if (err)
4638                 goto out;
4639
4640         parse_attr->filter_dev = filter_dev;
4641         mlx5e_flow_esw_attr_init(flow->attr,
4642                                  priv, parse_attr,
4643                                  f, in_rep, in_mdev);
4644
4645         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4646                                f, filter_dev);
4647         if (err)
4648                 goto err_free;
4649
4650         /* actions validation depends on parsing the ct matches first */
4651         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4652                                    &flow->attr->ct_attr, extack);
4653         if (err)
4654                 goto err_free;
4655
4656         /* always set IP version for indirect table handling */
4657         flow->attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4658
4659         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4660         if (err)
4661                 goto err_free;
4662
4663         if (flow->attr->lag.count) {
4664                 err = mlx5_lag_add_mpesw_rule(esw->dev);
4665                 if (err)
4666                         goto err_free;
4667         }
4668
4669         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4670         complete_all(&flow->init_done);
4671         if (err) {
4672                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4673                         goto err_lag;
4674
4675                 add_unready_flow(flow);
4676         }
4677
4678         return flow;
4679
4680 err_lag:
4681         if (flow->attr->lag.count)
4682                 mlx5_lag_del_mpesw_rule(esw->dev);
4683 err_free:
4684         mlx5e_flow_put(priv, flow);
4685 out:
4686         return ERR_PTR(err);
4687 }
4688
4689 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4690                                       struct mlx5e_tc_flow *flow,
4691                                       unsigned long flow_flags)
4692 {
4693         struct mlx5e_priv *priv = flow->priv, *peer_priv;
4694         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4695         struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4696         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4697         struct mlx5e_tc_flow_parse_attr *parse_attr;
4698         struct mlx5e_rep_priv *peer_urpriv;
4699         struct mlx5e_tc_flow *peer_flow;
4700         struct mlx5_core_dev *in_mdev;
4701         int err = 0;
4702
4703         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4704         if (!peer_esw)
4705                 return -ENODEV;
4706
4707         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4708         peer_priv = netdev_priv(peer_urpriv->netdev);
4709
4710         /* in_mdev is assigned of which the packet originated from.
4711          * So packets redirected to uplink use the same mdev of the
4712          * original flow and packets redirected from uplink use the
4713          * peer mdev.
4714          */
4715         if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
4716                 in_mdev = peer_priv->mdev;
4717         else
4718                 in_mdev = priv->mdev;
4719
4720         parse_attr = flow->attr->parse_attr;
4721         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4722                                          parse_attr->filter_dev,
4723                                          attr->in_rep, in_mdev);
4724         if (IS_ERR(peer_flow)) {
4725                 err = PTR_ERR(peer_flow);
4726                 goto out;
4727         }
4728
4729         flow->peer_flow = peer_flow;
4730         flow_flag_set(flow, DUP);
4731         mutex_lock(&esw->offloads.peer_mutex);
4732         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4733         mutex_unlock(&esw->offloads.peer_mutex);
4734
4735 out:
4736         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4737         return err;
4738 }
4739
4740 static int
4741 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4742                    struct flow_cls_offload *f,
4743                    unsigned long flow_flags,
4744                    struct net_device *filter_dev,
4745                    struct mlx5e_tc_flow **__flow)
4746 {
4747         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4748         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4749         struct mlx5_core_dev *in_mdev = priv->mdev;
4750         struct mlx5e_tc_flow *flow;
4751         int err;
4752
4753         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4754                                     in_mdev);
4755         if (IS_ERR(flow))
4756                 return PTR_ERR(flow);
4757
4758         if (is_peer_flow_needed(flow)) {
4759                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
4760                 if (err) {
4761                         mlx5e_tc_del_fdb_flow(priv, flow);
4762                         goto out;
4763                 }
4764         }
4765
4766         *__flow = flow;
4767
4768         return 0;
4769
4770 out:
4771         return err;
4772 }
4773
4774 static int
4775 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4776                    struct flow_cls_offload *f,
4777                    unsigned long flow_flags,
4778                    struct net_device *filter_dev,
4779                    struct mlx5e_tc_flow **__flow)
4780 {
4781         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4782         struct netlink_ext_ack *extack = f->common.extack;
4783         struct mlx5e_tc_flow_parse_attr *parse_attr;
4784         struct mlx5e_tc_flow *flow;
4785         int attr_size, err;
4786
4787         if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4788                 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4789                         return -EOPNOTSUPP;
4790         } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4791                 return -EOPNOTSUPP;
4792         }
4793
4794         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4795         attr_size  = sizeof(struct mlx5_nic_flow_attr);
4796         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4797                                &parse_attr, &flow);
4798         if (err)
4799                 goto out;
4800
4801         parse_attr->filter_dev = filter_dev;
4802         mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4803
4804         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4805                                f, filter_dev);
4806         if (err)
4807                 goto err_free;
4808
4809         err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4810                                    &flow->attr->ct_attr, extack);
4811         if (err)
4812                 goto err_free;
4813
4814         err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4815         if (err)
4816                 goto err_free;
4817
4818         err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4819         if (err)
4820                 goto err_free;
4821
4822         flow_flag_set(flow, OFFLOADED);
4823         *__flow = flow;
4824
4825         return 0;
4826
4827 err_free:
4828         flow_flag_set(flow, FAILED);
4829         mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4830         mlx5e_flow_put(priv, flow);
4831 out:
4832         return err;
4833 }
4834
4835 static int
4836 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4837                   struct flow_cls_offload *f,
4838                   unsigned long flags,
4839                   struct net_device *filter_dev,
4840                   struct mlx5e_tc_flow **flow)
4841 {
4842         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4843         unsigned long flow_flags;
4844         int err;
4845
4846         get_flags(flags, &flow_flags);
4847
4848         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4849                 return -EOPNOTSUPP;
4850
4851         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4852                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4853                                          filter_dev, flow);
4854         else
4855                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4856                                          filter_dev, flow);
4857
4858         return err;
4859 }
4860
4861 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4862                                            struct mlx5e_rep_priv *rpriv)
4863 {
4864         /* Offloaded flow rule is allowed to duplicate on non-uplink representor
4865          * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4866          * function is called from NIC mode.
4867          */
4868         return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4869 }
4870
4871 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4872                            struct flow_cls_offload *f, unsigned long flags)
4873 {
4874         struct netlink_ext_ack *extack = f->common.extack;
4875         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4876         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4877         struct mlx5e_tc_flow *flow;
4878         int err = 0;
4879
4880         if (!mlx5_esw_hold(priv->mdev))
4881                 return -EBUSY;
4882
4883         mlx5_esw_get(priv->mdev);
4884
4885         rcu_read_lock();
4886         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4887         if (flow) {
4888                 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4889                  * just return 0.
4890                  */
4891                 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4892                         goto rcu_unlock;
4893
4894                 NL_SET_ERR_MSG_MOD(extack,
4895                                    "flow cookie already exists, ignoring");
4896                 netdev_warn_once(priv->netdev,
4897                                  "flow cookie %lx already exists, ignoring\n",
4898                                  f->cookie);
4899                 err = -EEXIST;
4900                 goto rcu_unlock;
4901         }
4902 rcu_unlock:
4903         rcu_read_unlock();
4904         if (flow)
4905                 goto out;
4906
4907         trace_mlx5e_configure_flower(f);
4908         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4909         if (err)
4910                 goto out;
4911
4912         /* Flow rule offloaded to non-uplink representor sharing tc block,
4913          * set the flow's owner dev.
4914          */
4915         if (is_flow_rule_duplicate_allowed(dev, rpriv))
4916                 flow->orig_dev = dev;
4917
4918         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4919         if (err)
4920                 goto err_free;
4921
4922         mlx5_esw_release(priv->mdev);
4923         return 0;
4924
4925 err_free:
4926         mlx5e_flow_put(priv, flow);
4927 out:
4928         mlx5_esw_put(priv->mdev);
4929         mlx5_esw_release(priv->mdev);
4930         return err;
4931 }
4932
4933 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4934 {
4935         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4936         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4937
4938         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4939                 flow_flag_test(flow, EGRESS) == dir_egress;
4940 }
4941
4942 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4943                         struct flow_cls_offload *f, unsigned long flags)
4944 {
4945         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4946         struct mlx5e_tc_flow *flow;
4947         int err;
4948
4949         rcu_read_lock();
4950         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4951         if (!flow || !same_flow_direction(flow, flags)) {
4952                 err = -EINVAL;
4953                 goto errout;
4954         }
4955
4956         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4957          * set.
4958          */
4959         if (flow_flag_test_and_set(flow, DELETED)) {
4960                 err = -EINVAL;
4961                 goto errout;
4962         }
4963         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4964         rcu_read_unlock();
4965
4966         trace_mlx5e_delete_flower(f);
4967         mlx5e_flow_put(priv, flow);
4968
4969         mlx5_esw_put(priv->mdev);
4970         return 0;
4971
4972 errout:
4973         rcu_read_unlock();
4974         return err;
4975 }
4976
4977 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4978                        struct flow_cls_offload *f, unsigned long flags)
4979 {
4980         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4981         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4982         struct mlx5_eswitch *peer_esw;
4983         struct mlx5e_tc_flow *flow;
4984         struct mlx5_fc *counter;
4985         u64 lastuse = 0;
4986         u64 packets = 0;
4987         u64 bytes = 0;
4988         int err = 0;
4989
4990         rcu_read_lock();
4991         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4992                                                 tc_ht_params));
4993         rcu_read_unlock();
4994         if (IS_ERR(flow))
4995                 return PTR_ERR(flow);
4996
4997         if (!same_flow_direction(flow, flags)) {
4998                 err = -EINVAL;
4999                 goto errout;
5000         }
5001
5002         if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
5003                 counter = mlx5e_tc_get_counter(flow);
5004                 if (!counter)
5005                         goto errout;
5006
5007                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
5008         }
5009
5010         /* Under multipath it's possible for one rule to be currently
5011          * un-offloaded while the other rule is offloaded.
5012          */
5013         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
5014         if (!peer_esw)
5015                 goto out;
5016
5017         if (flow_flag_test(flow, DUP) &&
5018             flow_flag_test(flow->peer_flow, OFFLOADED)) {
5019                 u64 bytes2;
5020                 u64 packets2;
5021                 u64 lastuse2;
5022
5023                 counter = mlx5e_tc_get_counter(flow->peer_flow);
5024                 if (!counter)
5025                         goto no_peer_counter;
5026                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
5027
5028                 bytes += bytes2;
5029                 packets += packets2;
5030                 lastuse = max_t(u64, lastuse, lastuse2);
5031         }
5032
5033 no_peer_counter:
5034         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
5035 out:
5036         flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
5037                           FLOW_ACTION_HW_STATS_DELAYED);
5038         trace_mlx5e_stats_flower(f);
5039 errout:
5040         mlx5e_flow_put(priv, flow);
5041         return err;
5042 }
5043
5044 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
5045                                struct netlink_ext_ack *extack)
5046 {
5047         struct mlx5e_rep_priv *rpriv = priv->ppriv;
5048         struct mlx5_eswitch *esw;
5049         u32 rate_mbps = 0;
5050         u16 vport_num;
5051         int err;
5052
5053         vport_num = rpriv->rep->vport;
5054         if (vport_num >= MLX5_VPORT_ECPF) {
5055                 NL_SET_ERR_MSG_MOD(extack,
5056                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5057                 return -EOPNOTSUPP;
5058         }
5059
5060         esw = priv->mdev->priv.eswitch;
5061         /* rate is given in bytes/sec.
5062          * First convert to bits/sec and then round to the nearest mbit/secs.
5063          * mbit means million bits.
5064          * Moreover, if rate is non zero we choose to configure to a minimum of
5065          * 1 mbit/sec.
5066          */
5067         if (rate) {
5068                 rate = (rate * BITS_PER_BYTE) + 500000;
5069                 do_div(rate, 1000000);
5070                 rate_mbps = max_t(u32, rate, 1);
5071         }
5072
5073         err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
5074         if (err)
5075                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5076
5077         return err;
5078 }
5079
5080 static int
5081 tc_matchall_police_validate(const struct flow_action *action,
5082                             const struct flow_action_entry *act,
5083                             struct netlink_ext_ack *extack)
5084 {
5085         if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
5086                 NL_SET_ERR_MSG_MOD(extack,
5087                                    "Offload not supported when conform action is not continue");
5088                 return -EOPNOTSUPP;
5089         }
5090
5091         if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
5092                 NL_SET_ERR_MSG_MOD(extack,
5093                                    "Offload not supported when exceed action is not drop");
5094                 return -EOPNOTSUPP;
5095         }
5096
5097         if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
5098             !flow_action_is_last_entry(action, act)) {
5099                 NL_SET_ERR_MSG_MOD(extack,
5100                                    "Offload not supported when conform action is ok, but action is not last");
5101                 return -EOPNOTSUPP;
5102         }
5103
5104         if (act->police.peakrate_bytes_ps ||
5105             act->police.avrate || act->police.overhead) {
5106                 NL_SET_ERR_MSG_MOD(extack,
5107                                    "Offload not supported when peakrate/avrate/overhead is configured");
5108                 return -EOPNOTSUPP;
5109         }
5110
5111         return 0;
5112 }
5113
5114 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5115                                         struct flow_action *flow_action,
5116                                         struct netlink_ext_ack *extack)
5117 {
5118         struct mlx5e_rep_priv *rpriv = priv->ppriv;
5119         const struct flow_action_entry *act;
5120         int err;
5121         int i;
5122
5123         if (!flow_action_has_entries(flow_action)) {
5124                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5125                 return -EINVAL;
5126         }
5127
5128         if (!flow_offload_has_one_action(flow_action)) {
5129                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5130                 return -EOPNOTSUPP;
5131         }
5132
5133         if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
5134                 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
5135                 return -EOPNOTSUPP;
5136         }
5137
5138         flow_action_for_each(i, act, flow_action) {
5139                 switch (act->id) {
5140                 case FLOW_ACTION_POLICE:
5141                         err = tc_matchall_police_validate(flow_action, act, extack);
5142                         if (err)
5143                                 return err;
5144
5145                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5146                         if (err)
5147                                 return err;
5148
5149                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
5150                         break;
5151                 default:
5152                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5153                         return -EOPNOTSUPP;
5154                 }
5155         }
5156
5157         return 0;
5158 }
5159
5160 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5161                                 struct tc_cls_matchall_offload *ma)
5162 {
5163         struct netlink_ext_ack *extack = ma->common.extack;
5164
5165         if (ma->common.prio != 1) {
5166                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5167                 return -EINVAL;
5168         }
5169
5170         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5171 }
5172
5173 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5174                              struct tc_cls_matchall_offload *ma)
5175 {
5176         struct netlink_ext_ack *extack = ma->common.extack;
5177
5178         return apply_police_params(priv, 0, extack);
5179 }
5180
5181 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5182                              struct tc_cls_matchall_offload *ma)
5183 {
5184         struct mlx5e_rep_priv *rpriv = priv->ppriv;
5185         struct rtnl_link_stats64 cur_stats;
5186         u64 dbytes;
5187         u64 dpkts;
5188
5189         cur_stats = priv->stats.vf_vport;
5190         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5191         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5192         rpriv->prev_vf_vport_stats = cur_stats;
5193         flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
5194                           FLOW_ACTION_HW_STATS_DELAYED);
5195 }
5196
5197 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5198                                               struct mlx5e_priv *peer_priv)
5199 {
5200         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5201         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
5202         struct mlx5e_hairpin_entry *hpe, *tmp;
5203         LIST_HEAD(init_wait_list);
5204         u16 peer_vhca_id;
5205         int bkt;
5206
5207         if (!mlx5e_same_hw_devs(priv, peer_priv))
5208                 return;
5209
5210         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5211
5212         mutex_lock(&tc->hairpin_tbl_lock);
5213         hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
5214                 if (refcount_inc_not_zero(&hpe->refcnt))
5215                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5216         mutex_unlock(&tc->hairpin_tbl_lock);
5217
5218         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5219                 wait_for_completion(&hpe->res_ready);
5220                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
5221                         mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
5222
5223                 mlx5e_hairpin_put(priv, hpe);
5224         }
5225 }
5226
5227 static int mlx5e_tc_netdev_event(struct notifier_block *this,
5228                                  unsigned long event, void *ptr)
5229 {
5230         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5231         struct mlx5e_priv *peer_priv;
5232         struct mlx5e_tc_table *tc;
5233         struct mlx5e_priv *priv;
5234
5235         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5236             event != NETDEV_UNREGISTER ||
5237             ndev->reg_state == NETREG_REGISTERED)
5238                 return NOTIFY_DONE;
5239
5240         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5241         priv = tc->priv;
5242         peer_priv = netdev_priv(ndev);
5243         if (priv == peer_priv ||
5244             !(priv->netdev->features & NETIF_F_HW_TC))
5245                 return NOTIFY_DONE;
5246
5247         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5248
5249         return NOTIFY_DONE;
5250 }
5251
5252 static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
5253 {
5254         int tc_grp_size, tc_tbl_size;
5255         u32 max_flow_counter;
5256
5257         max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
5258                             MLX5_CAP_GEN(dev, max_flow_counter_15_0);
5259
5260         tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
5261
5262         tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
5263                             BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
5264
5265         return tc_tbl_size;
5266 }
5267
5268 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5269 {
5270         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5271         struct mlx5_flow_table **ft = &tc->miss_t;
5272         struct mlx5_flow_table_attr ft_attr = {};
5273         struct mlx5_flow_namespace *ns;
5274         int err = 0;
5275
5276         ft_attr.max_fte = 1;
5277         ft_attr.autogroup.max_num_groups = 1;
5278         ft_attr.level = MLX5E_TC_MISS_LEVEL;
5279         ft_attr.prio = 0;
5280         ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5281
5282         *ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5283         if (IS_ERR(*ft)) {
5284                 err = PTR_ERR(*ft);
5285                 netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5286         }
5287
5288         return err;
5289 }
5290
5291 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5292 {
5293         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5294
5295         mlx5_destroy_flow_table(tc->miss_t);
5296 }
5297
5298 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5299 {
5300         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5301         struct mlx5_core_dev *dev = priv->mdev;
5302         struct mapping_ctx *chains_mapping;
5303         struct mlx5_chains_attr attr = {};
5304         u64 mapping_id;
5305         int err;
5306
5307         mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5308         mutex_init(&tc->t_lock);
5309         mutex_init(&tc->hairpin_tbl_lock);
5310         hash_init(tc->hairpin_tbl);
5311         tc->priv = priv;
5312
5313         err = rhashtable_init(&tc->ht, &tc_ht_params);
5314         if (err)
5315                 return err;
5316
5317         lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5318
5319         mapping_id = mlx5_query_nic_system_image_guid(dev);
5320
5321         chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5322                                                sizeof(struct mlx5_mapped_obj),
5323                                                MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5324
5325         if (IS_ERR(chains_mapping)) {
5326                 err = PTR_ERR(chains_mapping);
5327                 goto err_mapping;
5328         }
5329         tc->mapping = chains_mapping;
5330
5331         err = mlx5e_tc_nic_create_miss_table(priv);
5332         if (err)
5333                 goto err_chains;
5334
5335         if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5336                 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5337                         MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5338         attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5339         attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5340         attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5341         attr.default_ft = tc->miss_t;
5342         attr.mapping = chains_mapping;
5343
5344         tc->chains = mlx5_chains_create(dev, &attr);
5345         if (IS_ERR(tc->chains)) {
5346                 err = PTR_ERR(tc->chains);
5347                 goto err_miss;
5348         }
5349
5350         tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5351         tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5352                                  MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5353
5354         mlx5e_hairpin_params_init(&tc->hairpin_params, dev);
5355
5356         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5357         err = register_netdevice_notifier_dev_net(priv->netdev,
5358                                                   &tc->netdevice_nb,
5359                                                   &tc->netdevice_nn);
5360         if (err) {
5361                 tc->netdevice_nb.notifier_call = NULL;
5362                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5363                 goto err_reg;
5364         }
5365
5366         mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5367
5368         return 0;
5369
5370 err_reg:
5371         mlx5_tc_ct_clean(tc->ct);
5372         mlx5e_tc_post_act_destroy(tc->post_act);
5373         mlx5_chains_destroy(tc->chains);
5374 err_miss:
5375         mlx5e_tc_nic_destroy_miss_table(priv);
5376 err_chains:
5377         mapping_destroy(chains_mapping);
5378 err_mapping:
5379         rhashtable_destroy(&tc->ht);
5380         return err;
5381 }
5382
5383 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5384 {
5385         struct mlx5e_tc_flow *flow = ptr;
5386         struct mlx5e_priv *priv = flow->priv;
5387
5388         mlx5e_tc_del_flow(priv, flow);
5389         kfree(flow);
5390 }
5391
5392 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5393 {
5394         struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5395
5396         debugfs_remove_recursive(tc->dfs_root);
5397
5398         if (tc->netdevice_nb.notifier_call)
5399                 unregister_netdevice_notifier_dev_net(priv->netdev,
5400                                                       &tc->netdevice_nb,
5401                                                       &tc->netdevice_nn);
5402
5403         mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5404         mutex_destroy(&tc->hairpin_tbl_lock);
5405
5406         rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5407
5408         if (!IS_ERR_OR_NULL(tc->t)) {
5409                 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5410                 tc->t = NULL;
5411         }
5412         mutex_destroy(&tc->t_lock);
5413
5414         mlx5_tc_ct_clean(tc->ct);
5415         mlx5e_tc_post_act_destroy(tc->post_act);
5416         mapping_destroy(tc->mapping);
5417         mlx5_chains_destroy(tc->chains);
5418         mlx5e_tc_nic_destroy_miss_table(priv);
5419 }
5420
5421 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5422 {
5423         int err;
5424
5425         err = rhashtable_init(tc_ht, &tc_ht_params);
5426         if (err)
5427                 return err;
5428
5429         lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5430
5431         return 0;
5432 }
5433
5434 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5435 {
5436         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5437 }
5438
5439 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5440 {
5441         const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5442         struct mlx5e_rep_priv *rpriv;
5443         struct mapping_ctx *mapping;
5444         struct mlx5_eswitch *esw;
5445         struct mlx5e_priv *priv;
5446         u64 mapping_id;
5447         int err = 0;
5448
5449         rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5450         priv = netdev_priv(rpriv->netdev);
5451         esw = priv->mdev->priv.eswitch;
5452
5453         uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5454                                                        MLX5_FLOW_NAMESPACE_FDB);
5455         uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5456                                                esw_chains(esw),
5457                                                &esw->offloads.mod_hdr,
5458                                                MLX5_FLOW_NAMESPACE_FDB,
5459                                                uplink_priv->post_act);
5460
5461         uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5462
5463         uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5464
5465         mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5466
5467         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5468                                         sizeof(struct tunnel_match_key),
5469                                         TUNNEL_INFO_BITS_MASK, true);
5470
5471         if (IS_ERR(mapping)) {
5472                 err = PTR_ERR(mapping);
5473                 goto err_tun_mapping;
5474         }
5475         uplink_priv->tunnel_mapping = mapping;
5476
5477         /* Two last values are reserved for stack devices slow path table mark
5478          * and bridge ingress push mark.
5479          */
5480         mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5481                                         sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5482         if (IS_ERR(mapping)) {
5483                 err = PTR_ERR(mapping);
5484                 goto err_enc_opts_mapping;
5485         }
5486         uplink_priv->tunnel_enc_opts_mapping = mapping;
5487
5488         uplink_priv->encap = mlx5e_tc_tun_init(priv);
5489         if (IS_ERR(uplink_priv->encap)) {
5490                 err = PTR_ERR(uplink_priv->encap);
5491                 goto err_register_fib_notifier;
5492         }
5493
5494         return 0;
5495
5496 err_register_fib_notifier:
5497         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5498 err_enc_opts_mapping:
5499         mapping_destroy(uplink_priv->tunnel_mapping);
5500 err_tun_mapping:
5501         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5502         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5503         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5504         netdev_warn(priv->netdev,
5505                     "Failed to initialize tc (eswitch), err: %d", err);
5506         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5507         return err;
5508 }
5509
5510 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5511 {
5512         mlx5e_tc_tun_cleanup(uplink_priv->encap);
5513
5514         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5515         mapping_destroy(uplink_priv->tunnel_mapping);
5516
5517         mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5518         mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5519         mlx5_tc_ct_clean(uplink_priv->ct_priv);
5520         mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5521         mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5522 }
5523
5524 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5525 {
5526         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5527
5528         return atomic_read(&tc_ht->nelems);
5529 }
5530
5531 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5532 {
5533         struct mlx5e_tc_flow *flow, *tmp;
5534
5535         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5536                 __mlx5e_tc_del_fdb_peer_flow(flow);
5537 }
5538
5539 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5540 {
5541         struct mlx5_rep_uplink_priv *rpriv =
5542                 container_of(work, struct mlx5_rep_uplink_priv,
5543                              reoffload_flows_work);
5544         struct mlx5e_tc_flow *flow, *tmp;
5545
5546         mutex_lock(&rpriv->unready_flows_lock);
5547         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5548                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5549                         unready_flow_del(flow);
5550         }
5551         mutex_unlock(&rpriv->unready_flows_lock);
5552 }
5553
5554 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5555                                      struct flow_cls_offload *cls_flower,
5556                                      unsigned long flags)
5557 {
5558         switch (cls_flower->command) {
5559         case FLOW_CLS_REPLACE:
5560                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5561                                               flags);
5562         case FLOW_CLS_DESTROY:
5563                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5564                                            flags);
5565         case FLOW_CLS_STATS:
5566                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5567                                           flags);
5568         default:
5569                 return -EOPNOTSUPP;
5570         }
5571 }
5572
5573 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5574                             void *cb_priv)
5575 {
5576         unsigned long flags = MLX5_TC_FLAG(INGRESS);
5577         struct mlx5e_priv *priv = cb_priv;
5578
5579         if (!priv->netdev || !netif_device_present(priv->netdev))
5580                 return -EOPNOTSUPP;
5581
5582         if (mlx5e_is_uplink_rep(priv))
5583                 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5584         else
5585                 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5586
5587         switch (type) {
5588         case TC_SETUP_CLSFLOWER:
5589                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5590         default:
5591                 return -EOPNOTSUPP;
5592         }
5593 }
5594
5595 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5596                          struct sk_buff *skb)
5597 {
5598 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
5599         u32 chain = 0, chain_tag, reg_b, zone_restore_id;
5600         struct mlx5e_priv *priv = netdev_priv(skb->dev);
5601         struct mlx5_mapped_obj mapped_obj;
5602         struct tc_skb_ext *tc_skb_ext;
5603         struct mlx5e_tc_table *tc;
5604         int err;
5605
5606         reg_b = be32_to_cpu(cqe->ft_metadata);
5607         tc = mlx5e_fs_get_tc(priv->fs);
5608         chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5609
5610         err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
5611         if (err) {
5612                 netdev_dbg(priv->netdev,
5613                            "Couldn't find chain for chain tag: %d, err: %d\n",
5614                            chain_tag, err);
5615                 return false;
5616         }
5617
5618         if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5619                 chain = mapped_obj.chain;
5620                 tc_skb_ext = tc_skb_ext_alloc(skb);
5621                 if (WARN_ON(!tc_skb_ext))
5622                         return false;
5623
5624                 tc_skb_ext->chain = chain;
5625
5626                 zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5627                         ESW_ZONE_ID_MASK;
5628
5629                 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5630                                               zone_restore_id))
5631                         return false;
5632         } else {
5633                 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5634                 return false;
5635         }
5636 #endif /* CONFIG_NET_TC_SKB_EXT */
5637
5638         return true;
5639 }