2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
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11 * without modification, are permitted provided that the following
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15 * copyright notice, this list of conditions and the following
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23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_EN_STATS_H__
34 #define __MLX5_EN_STATS_H__
36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld)
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld)
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld)
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld)
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld)
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld)
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld)
56 #define MLX5E_DECLARE_PTP_CQ_STAT(type, fld) "ptp_cq%d_"#fld, offsetof(type, fld)
57 #define MLX5E_DECLARE_PTP_RQ_STAT(type, fld) "ptp_rq%d_"#fld, offsetof(type, fld)
59 #define MLX5E_DECLARE_QOS_TX_STAT(type, fld) "qos_tx%d_"#fld, offsetof(type, fld)
62 char format[ETH_GSTRING_LEN];
63 size_t offset; /* Byte offset */
67 MLX5E_NDO_UPDATE_STATS = BIT(0x1),
71 struct mlx5e_stats_grp {
72 u16 update_stats_mask;
73 int (*get_num_stats)(struct mlx5e_priv *priv);
74 int (*fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx);
75 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
76 void (*update_stats)(struct mlx5e_priv *priv);
79 typedef const struct mlx5e_stats_grp *const mlx5e_stats_grp_t;
81 #define MLX5E_STATS_GRP_OP(grp, name) mlx5e_stats_grp_ ## grp ## _ ## name
83 #define MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(grp) \
84 int MLX5E_STATS_GRP_OP(grp, num_stats)(struct mlx5e_priv *priv)
86 #define MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(grp) \
87 void MLX5E_STATS_GRP_OP(grp, update_stats)(struct mlx5e_priv *priv)
89 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(grp) \
90 int MLX5E_STATS_GRP_OP(grp, fill_strings)(struct mlx5e_priv *priv, u8 *data, int idx)
92 #define MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(grp) \
93 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
95 #define MLX5E_STATS_GRP(grp) mlx5e_stats_grp_ ## grp
97 #define MLX5E_DECLARE_STATS_GRP(grp) \
98 const struct mlx5e_stats_grp MLX5E_STATS_GRP(grp)
100 #define MLX5E_DEFINE_STATS_GRP(grp, mask) \
101 MLX5E_DECLARE_STATS_GRP(grp) = { \
102 .get_num_stats = MLX5E_STATS_GRP_OP(grp, num_stats), \
103 .fill_stats = MLX5E_STATS_GRP_OP(grp, fill_stats), \
104 .fill_strings = MLX5E_STATS_GRP_OP(grp, fill_strings), \
105 .update_stats = MLX5E_STATS_GRP_OP(grp, update_stats), \
106 .update_stats_mask = mask, \
109 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv);
110 void mlx5e_stats_update(struct mlx5e_priv *priv);
111 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
112 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data);
113 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv);
115 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
116 struct ethtool_pause_stats *pause_stats);
117 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
118 struct ethtool_fec_stats *fec_stats);
120 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
121 struct ethtool_eth_phy_stats *phy_stats);
122 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
123 struct ethtool_eth_mac_stats *mac_stats);
124 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
125 struct ethtool_eth_ctrl_stats *ctrl_stats);
126 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
127 struct ethtool_rmon_stats *rmon,
128 const struct ethtool_rmon_hist_range **ranges);
129 void mlx5e_get_link_ext_stats(struct net_device *dev,
130 struct ethtool_link_ext_stats *stats);
132 /* Concrete NIC Stats */
134 struct mlx5e_sw_stats {
141 u64 tx_tso_inner_packets;
142 u64 tx_tso_inner_bytes;
143 u64 tx_added_vlan_packets;
152 u64 rx_gro_match_packets;
153 u64 rx_gro_large_hds;
154 u64 rx_mcast_packets;
156 u64 rx_removed_vlan_packets;
157 u64 rx_csum_unnecessary;
159 u64 rx_csum_complete;
160 u64 rx_csum_complete_tail;
161 u64 rx_csum_complete_tail_slow;
162 u64 rx_csum_unnecessary_inner;
174 u64 tx_csum_partial_inner;
175 u64 tx_queue_stopped;
176 u64 tx_queue_dropped;
190 u64 rx_mpwqe_filler_cqes;
191 u64 rx_mpwqe_filler_strides;
192 u64 rx_oversize_pkts_sw_drop;
193 u64 rx_buff_alloc_err;
194 u64 rx_cqe_compress_blks;
195 u64 rx_cqe_compress_pkts;
205 #ifdef CONFIG_PAGE_POOL_STATS
206 u64 rx_pp_alloc_fast;
207 u64 rx_pp_alloc_slow;
208 u64 rx_pp_alloc_slow_high_order;
209 u64 rx_pp_alloc_empty;
210 u64 rx_pp_alloc_refill;
211 u64 rx_pp_alloc_waive;
212 u64 rx_pp_recycle_cached;
213 u64 rx_pp_recycle_cache_full;
214 u64 rx_pp_recycle_ring;
215 u64 rx_pp_recycle_ring_full;
216 u64 rx_pp_recycle_released_ref;
218 #ifdef CONFIG_MLX5_EN_TLS
219 u64 tx_tls_encrypted_packets;
220 u64 tx_tls_encrypted_bytes;
222 u64 tx_tls_dump_packets;
223 u64 tx_tls_dump_bytes;
224 u64 tx_tls_resync_bytes;
225 u64 tx_tls_skip_no_sync_data;
226 u64 tx_tls_drop_no_sync_data;
227 u64 tx_tls_drop_bypass_req;
229 u64 rx_tls_decrypted_packets;
230 u64 rx_tls_decrypted_bytes;
231 u64 rx_tls_resync_req_pkt;
232 u64 rx_tls_resync_req_start;
233 u64 rx_tls_resync_req_end;
234 u64 rx_tls_resync_req_skip;
235 u64 rx_tls_resync_res_ok;
236 u64 rx_tls_resync_res_retry;
237 u64 rx_tls_resync_res_skip;
243 u64 rx_xsk_csum_complete;
244 u64 rx_xsk_csum_unnecessary;
245 u64 rx_xsk_csum_unnecessary_inner;
246 u64 rx_xsk_csum_none;
248 u64 rx_xsk_removed_vlan_packets;
250 u64 rx_xsk_xdp_redirect;
252 u64 rx_xsk_mpwqe_filler_cqes;
253 u64 rx_xsk_mpwqe_filler_strides;
254 u64 rx_xsk_oversize_pkts_sw_drop;
255 u64 rx_xsk_buff_alloc_err;
256 u64 rx_xsk_cqe_compress_blks;
257 u64 rx_xsk_cqe_compress_pkts;
258 u64 rx_xsk_congst_umr;
268 struct mlx5e_qcounter_stats {
269 u32 rx_out_of_buffer;
270 u32 rx_if_down_packets;
273 #define VNIC_ENV_GET(vnic_env_stats, c) \
274 MLX5_GET(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
277 struct mlx5e_vnic_env_stats {
278 __be64 query_vnic_env_out[MLX5_ST_SZ_QW(query_vnic_env_out)];
281 #define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
282 vstats->query_vport_out, c)
284 struct mlx5e_vport_stats {
285 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
288 #define PPORT_802_3_GET(pstats, c) \
289 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
290 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
291 #define PPORT_2863_GET(pstats, c) \
292 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
293 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
294 #define PPORT_2819_GET(pstats, c) \
295 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
296 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
297 #define PPORT_PHY_STATISTICAL_GET(pstats, c) \
298 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
299 counter_set.phys_layer_statistical_cntrs.c##_high)
300 #define PPORT_PER_PRIO_GET(pstats, prio, c) \
301 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
302 counter_set.eth_per_prio_grp_data_layout.c##_high)
303 #define NUM_PPORT_PRIO 8
304 #define PPORT_ETH_EXT_GET(pstats, c) \
305 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
306 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
308 struct mlx5e_pport_stats {
309 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
310 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
311 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
312 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
313 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
314 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
315 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
316 __be64 per_tc_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
317 __be64 per_tc_congest_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
320 #define PCIE_PERF_GET(pcie_stats, c) \
321 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
322 counter_set.pcie_perf_cntrs_grp_data_layout.c)
324 #define PCIE_PERF_GET64(pcie_stats, c) \
325 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
326 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
328 struct mlx5e_pcie_stats {
329 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
332 struct mlx5e_rq_stats {
336 u64 csum_complete_tail;
337 u64 csum_complete_tail_slow;
338 u64 csum_unnecessary;
339 u64 csum_unnecessary_inner;
346 u64 gro_match_packets;
350 u64 removed_vlan_packets;
354 u64 mpwqe_filler_cqes;
355 u64 mpwqe_filler_strides;
356 u64 oversize_pkts_sw_drop;
358 u64 cqe_compress_blks;
359 u64 cqe_compress_pkts;
363 #ifdef CONFIG_PAGE_POOL_STATS
366 u64 pp_alloc_slow_high_order;
370 u64 pp_recycle_cached;
371 u64 pp_recycle_cache_full;
373 u64 pp_recycle_ring_full;
374 u64 pp_recycle_released_ref;
376 #ifdef CONFIG_MLX5_EN_TLS
377 u64 tls_decrypted_packets;
378 u64 tls_decrypted_bytes;
379 u64 tls_resync_req_pkt;
380 u64 tls_resync_req_start;
381 u64 tls_resync_req_end;
382 u64 tls_resync_req_skip;
383 u64 tls_resync_res_ok;
384 u64 tls_resync_res_retry;
385 u64 tls_resync_res_skip;
390 struct mlx5e_sq_stats {
391 /* commonly accessed in data path */
397 u64 tso_inner_packets;
400 u64 csum_partial_inner;
401 u64 added_vlan_packets;
405 #ifdef CONFIG_MLX5_EN_TLS
406 u64 tls_encrypted_packets;
407 u64 tls_encrypted_bytes;
409 u64 tls_dump_packets;
411 u64 tls_resync_bytes;
412 u64 tls_skip_no_sync_data;
413 u64 tls_drop_no_sync_data;
414 u64 tls_drop_bypass_req;
416 /* less likely accessed in data path */
421 /* dirtied @completion */
422 u64 cqes ____cacheline_aligned_in_smp;
427 struct mlx5e_xdpsq_stats {
434 /* dirtied @completion */
435 u64 cqes ____cacheline_aligned_in_smp;
438 struct mlx5e_ch_stats {
447 struct mlx5e_ptp_cq_stats {
451 u64 abort_abs_diff_ns;
457 struct mlx5e_rep_stats {
458 u64 vport_rx_packets;
459 u64 vport_tx_packets;
462 u64 rx_vport_rdma_unicast_packets;
463 u64 tx_vport_rdma_unicast_packets;
464 u64 rx_vport_rdma_unicast_bytes;
465 u64 tx_vport_rdma_unicast_bytes;
466 u64 rx_vport_rdma_multicast_packets;
467 u64 tx_vport_rdma_multicast_packets;
468 u64 rx_vport_rdma_multicast_bytes;
469 u64 tx_vport_rdma_multicast_bytes;
473 struct mlx5e_sw_stats sw;
474 struct mlx5e_qcounter_stats qcnt;
475 struct mlx5e_vnic_env_stats vnic;
476 struct mlx5e_vport_stats vport;
477 struct mlx5e_pport_stats pport;
478 struct rtnl_link_stats64 vf_vport;
479 struct mlx5e_pcie_stats pcie;
480 struct mlx5e_rep_stats rep_stats;
483 extern mlx5e_stats_grp_t mlx5e_nic_stats_grps[];
484 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv);
486 extern MLX5E_DECLARE_STATS_GRP(sw);
487 extern MLX5E_DECLARE_STATS_GRP(qcnt);
488 extern MLX5E_DECLARE_STATS_GRP(vnic_env);
489 extern MLX5E_DECLARE_STATS_GRP(vport);
490 extern MLX5E_DECLARE_STATS_GRP(802_3);
491 extern MLX5E_DECLARE_STATS_GRP(2863);
492 extern MLX5E_DECLARE_STATS_GRP(2819);
493 extern MLX5E_DECLARE_STATS_GRP(phy);
494 extern MLX5E_DECLARE_STATS_GRP(eth_ext);
495 extern MLX5E_DECLARE_STATS_GRP(pcie);
496 extern MLX5E_DECLARE_STATS_GRP(per_prio);
497 extern MLX5E_DECLARE_STATS_GRP(pme);
498 extern MLX5E_DECLARE_STATS_GRP(channels);
499 extern MLX5E_DECLARE_STATS_GRP(per_port_buff_congest);
500 extern MLX5E_DECLARE_STATS_GRP(ipsec_hw);
501 extern MLX5E_DECLARE_STATS_GRP(ipsec_sw);
502 extern MLX5E_DECLARE_STATS_GRP(ptp);
503 extern MLX5E_DECLARE_STATS_GRP(macsec_hw);
505 #endif /* __MLX5_EN_STATS_H__ */